opcodes/lm32-desc.h

   1 /* CPU data header for lm32.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef LM32_CPU_H
  26 #define LM32_CPU_H
  27
  28 #include "opcode/cgen-bitset.h"
  29
  30 #define CGEN_ARCH lm32
  31
  32 /* Given symbol S, return lm32_cgen_<S>.  */
  33 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  34 #define CGEN_SYM(s) lm32##_cgen_##s
  35 #else
  36 #define CGEN_SYM(s) lm32/**/_cgen_/**/s
  37 #endif
  38
  39
  40 /* Selected cpu families.  */
  41 #define HAVE_CPU_LM32BF
  42
  43 #define CGEN_INSN_LSB0_P 1
  44
  45 /* Minimum size of any insn (in bytes).  */
  46 #define CGEN_MIN_INSN_SIZE 4
  47
  48 /* Maximum size of any insn (in bytes).  */
  49 #define CGEN_MAX_INSN_SIZE 4
  50
  51 #define CGEN_INT_INSN_P 1
  52
  53 /* Maximum number of syntax elements in an instruction.  */
  54 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
  55
  56 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  57    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  58    we can't hash on everything up to the space.  */
  59 #define CGEN_MNEMONIC_OPERANDS
  60
  61 /* Maximum number of fields in an instruction.  */
  62 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 5
  63
  64 /* Enums.  */
  65
  66 /* Enum declaration for opcodes.  */
  67 typedef enum opcodes {
  68   OP_ADD = 45, OP_ADDI = 13, OP_AND = 40, OP_ANDI = 8
  69  , OP_ANDHI = 24, OP_B = 48, OP_BI = 56, OP_BE = 17
  70  , OP_BG = 18, OP_BGE = 19, OP_BGEU = 20, OP_BGU = 21
  71  , OP_BNE = 23, OP_CALL = 54, OP_CALLI = 62, OP_CMPE = 57
  72  , OP_CMPEI = 25, OP_CMPG = 58, OP_CMPGI = 26, OP_CMPGE = 59
  73  , OP_CMPGEI = 27, OP_CMPGEU = 60, OP_CMPGEUI = 28, OP_CMPGU = 61
  74  , OP_CMPGUI = 29, OP_CMPNE = 63, OP_CMPNEI = 31, OP_DIVU = 35
  75  , OP_LB = 4, OP_LBU = 16, OP_LH = 7, OP_LHU = 11
  76  , OP_LW = 10, OP_MODU = 49, OP_MUL = 34, OP_MULI = 2
  77  , OP_NOR = 33, OP_NORI = 1, OP_OR = 46, OP_ORI = 14
  78  , OP_ORHI = 30, OP_RAISE = 43, OP_RCSR = 36, OP_SB = 12
  79  , OP_SEXTB = 44, OP_SEXTH = 55, OP_SH = 3, OP_SL = 47
  80  , OP_SLI = 15, OP_SR = 37, OP_SRI = 5, OP_SRU = 32
  81  , OP_SRUI = 0, OP_SUB = 50, OP_SW = 22, OP_USER = 51
  82  , OP_WCSR = 52, OP_XNOR = 41, OP_XNORI = 9, OP_XOR = 38
  83  , OP_XORI = 6
  84 } OPCODES;
  85
  86 /* Attributes.  */
  87
  88 /* Enum declaration for machine type selection.  */
  89 typedef enum mach_attr {
  90   MACH_BASE, MACH_LM32, MACH_MAX
  91 } MACH_ATTR;
  92
  93 /* Enum declaration for instruction set selection.  */
  94 typedef enum isa_attr {
  95   ISA_LM32, ISA_MAX
  96 } ISA_ATTR;
  97
  98 /* Number of architecture variants.  */
  99 #define MAX_ISAS  1
 100 #define MAX_MACHS ((int) MACH_MAX)
 101
 102 /* Ifield support.  */
 103
 104 /* Ifield attribute indices.  */
 105
 106 /* Enum declaration for cgen_ifld attrs.  */
 107 typedef enum cgen_ifld_attr {
 108   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 109  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 110  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 111 } CGEN_IFLD_ATTR;
 112
 113 /* Number of non-boolean elements in cgen_ifld_attr.  */
 114 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 115
 116 /* cgen_ifld attribute accessor macros.  */
 117 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 118 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 119 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 120 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 121 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
 122 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 123 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
 124
 125 /* Enum declaration for lm32 ifield types.  */
 126 typedef enum ifield_type {
 127   LM32_F_NIL, LM32_F_ANYOF, LM32_F_OPCODE, LM32_F_R0
 128  , LM32_F_R1, LM32_F_R2, LM32_F_RESV0, LM32_F_SHIFT
 129  , LM32_F_IMM, LM32_F_UIMM, LM32_F_CSR, LM32_F_USER
 130  , LM32_F_EXCEPTION, LM32_F_BRANCH, LM32_F_CALL, LM32_F_MAX
 131 } IFIELD_TYPE;
 132
 133 #define MAX_IFLD ((int) LM32_F_MAX)
 134
 135 /* Hardware attribute indices.  */
 136
 137 /* Enum declaration for cgen_hw attrs.  */
 138 typedef enum cgen_hw_attr {
 139   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 140  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 141 } CGEN_HW_ATTR;
 142
 143 /* Number of non-boolean elements in cgen_hw_attr.  */
 144 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 145
 146 /* cgen_hw attribute accessor macros.  */
 147 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 148 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
 149 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 150 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
 151 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
 152
 153 /* Enum declaration for lm32 hardware types.  */
 154 typedef enum cgen_hw_type {
 155   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 156  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CSR
 157  , HW_MAX
 158 } CGEN_HW_TYPE;
 159
 160 #define MAX_HW ((int) HW_MAX)
 161
 162 /* Operand attribute indices.  */
 163
 164 /* Enum declaration for cgen_operand attrs.  */
 165 typedef enum cgen_operand_attr {
 166   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 167  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 168  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 169 } CGEN_OPERAND_ATTR;
 170
 171 /* Number of non-boolean elements in cgen_operand_attr.  */
 172 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 173
 174 /* cgen_operand attribute accessor macros.  */
 175 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 176 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 177 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 178 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 179 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 180 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
 181 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 182 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
 183 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 184
 185 /* Enum declaration for lm32 operand types.  */
 186 typedef enum cgen_operand_type {
 187   LM32_OPERAND_PC, LM32_OPERAND_R0, LM32_OPERAND_R1, LM32_OPERAND_R2
 188  , LM32_OPERAND_SHIFT, LM32_OPERAND_IMM, LM32_OPERAND_UIMM, LM32_OPERAND_BRANCH
 189  , LM32_OPERAND_CALL, LM32_OPERAND_CSR, LM32_OPERAND_USER, LM32_OPERAND_EXCEPTION
 190  , LM32_OPERAND_HI16, LM32_OPERAND_LO16, LM32_OPERAND_GP16, LM32_OPERAND_GOT16
 191  , LM32_OPERAND_GOTOFFHI16, LM32_OPERAND_GOTOFFLO16, LM32_OPERAND_MAX
 192 } CGEN_OPERAND_TYPE;
 193
 194 /* Number of operands types.  */
 195 #define MAX_OPERANDS 18
 196
 197 /* Maximum number of operands referenced by any insn.  */
 198 #define MAX_OPERAND_INSTANCES 5
 199
 200 /* Insn attribute indices.  */
 201
 202 /* Enum declaration for cgen_insn attrs.  */
 203 typedef enum cgen_insn_attr {
 204   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 205  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 206  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
 207  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 208 } CGEN_INSN_ATTR;
 209
 210 /* Number of non-boolean elements in cgen_insn_attr.  */
 211 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 212
 213 /* cgen_insn attribute accessor macros.  */
 214 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 215 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
 216 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
 217 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 218 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
 219 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 220 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 221 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
 222 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
 223 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
 224 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
 225
 226 /* cgen.h uses things we just defined.  */
 227 #include "opcode/cgen.h"
 228
 229 extern const struct cgen_ifld lm32_cgen_ifld_table[];
 230
 231 /* Attributes.  */
 232 extern const CGEN_ATTR_TABLE lm32_cgen_hardware_attr_table[];
 233 extern const CGEN_ATTR_TABLE lm32_cgen_ifield_attr_table[];
 234 extern const CGEN_ATTR_TABLE lm32_cgen_operand_attr_table[];
 235 extern const CGEN_ATTR_TABLE lm32_cgen_insn_attr_table[];
 236
 237 /* Hardware decls.  */
 238
 239 extern CGEN_KEYWORD lm32_cgen_opval_h_gr;
 240 extern CGEN_KEYWORD lm32_cgen_opval_h_csr;
 241
 242 extern const CGEN_HW_ENTRY lm32_cgen_hw_table[];
 243
 244
 245
 246 #endif /* LM32_CPU_H */