opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* SSE support required */
  54 #define CpuSSE          (CpuMMX + 1)
  55 /* SSE2 support required */
  56 #define CpuSSE2         (CpuSSE + 1)
  57 /* 3dnow! support required */
  58 #define Cpu3dnow        (CpuSSE2 + 1)
  59 /* 3dnow! Extensions support required */
  60 #define Cpu3dnowA       (Cpu3dnow + 1)
  61 /* SSE3 support required */
  62 #define CpuSSE3         (Cpu3dnowA + 1)
  63 /* VIA PadLock required */
  64 #define CpuPadLock      (CpuSSE3 + 1)
  65 /* AMD Secure Virtual Machine Ext-s required */
  66 #define CpuSVME         (CpuPadLock + 1)
  67 /* VMX Instructions required */
  68 #define CpuVMX          (CpuSVME + 1)
  69 /* SMX Instructions required */
  70 #define CpuSMX          (CpuVMX + 1)
  71 /* SSSE3 support required */
  72 #define CpuSSSE3        (CpuSMX + 1)
  73 /* SSE4a support required */
  74 #define CpuSSE4a        (CpuSSSE3 + 1)
  75 /* ABM New Instructions required */
  76 #define CpuABM          (CpuSSE4a + 1)
  77 /* SSE4.1 support required */
  78 #define CpuSSE4_1       (CpuABM + 1)
  79 /* SSE4.2 support required */
  80 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  81 /* SSE5 support required */
  82 #define CpuSSE5         (CpuSSE4_2 + 1)
  83 /* AVX support required */
  84 #define CpuAVX          (CpuSSE5 + 1)
  85 /* Xsave/xrstor New Instuctions support required */
  86 #define CpuXsave        (CpuAVX + 1)
  87 /* AES support required */
  88 #define CpuAES          (CpuXsave + 1)
  89 /* PCLMUL support required */
  90 #define CpuPCLMUL       (CpuAES + 1)
  91 /* FMA support required */
  92 #define CpuFMA          (CpuPCLMUL + 1)
  93 /* MOVBE Instuction support required */
  94 #define CpuMovbe        (CpuFMA + 1)
  95 /* EPT Instructions required */
  96 #define CpuEPT          (CpuMovbe + 1)
  97 /* 64bit support available, used by -march= in assembler.  */
  98 #define CpuLM           (CpuEPT + 1)
  99 /* 64bit support required  */
 100 #define Cpu64           (CpuLM + 1)
 101 /* Not supported in the 64bit mode  */
 102 #define CpuNo64         (Cpu64 + 1)
 103 /* The last bitfield in i386_cpu_flags.  */
 104 #define CpuMax          CpuNo64
 105
 106 #define CpuNumOfUints \
 107   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 108 #define CpuNumOfBits \
 109   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 110
 111 /* If you get a compiler error for zero width of the unused field,
 112    comment it out.  */
 113 #define CpuUnused       (CpuMax + 1)
 114
 115 /* We can check if an instruction is available with array instead
 116    of bitfield. */
 117 typedef union i386_cpu_flags
 118 {
 119   struct
 120     {
 121       unsigned int cpui186:1;
 122       unsigned int cpui286:1;
 123       unsigned int cpui386:1;
 124       unsigned int cpui486:1;
 125       unsigned int cpui586:1;
 126       unsigned int cpui686:1;
 127       unsigned int cpup4:1;
 128       unsigned int cpuk6:1;
 129       unsigned int cpuk8:1;
 130       unsigned int cpummx:1;
 131       unsigned int cpusse:1;
 132       unsigned int cpusse2:1;
 133       unsigned int cpua3dnow:1;
 134       unsigned int cpua3dnowa:1;
 135       unsigned int cpusse3:1;
 136       unsigned int cpupadlock:1;
 137       unsigned int cpusvme:1;
 138       unsigned int cpuvmx:1;
 139       unsigned int cpusmx:1;
 140       unsigned int cpussse3:1;
 141       unsigned int cpusse4a:1;
 142       unsigned int cpuabm:1;
 143       unsigned int cpusse4_1:1;
 144       unsigned int cpusse4_2:1;
 145       unsigned int cpusse5:1;
 146       unsigned int cpuavx:1;
 147       unsigned int cpuxsave:1;
 148       unsigned int cpuaes:1;
 149       unsigned int cpupclmul:1;
 150       unsigned int cpufma:1;
 151       unsigned int cpumovbe:1;
 152       unsigned int cpuept:1;
 153       unsigned int cpulm:1;
 154       unsigned int cpu64:1;
 155       unsigned int cpuno64:1;
 156 #ifdef CpuUnused
 157       unsigned int unused:(CpuNumOfBits - CpuUnused);
 158 #endif
 159     } bitfield;
 160   unsigned int array[CpuNumOfUints];
 161 } i386_cpu_flags;
 162
 163 /* Position of opcode_modifier bits.  */
 164
 165 /* has direction bit. */
 166 #define D                       0
 167 /* set if operands can be words or dwords encoded the canonical way */
 168 #define W                       (D + 1)
 169 /* insn has a modrm byte. */
 170 #define Modrm                   (W + 1)
 171 /* register is in low 3 bits of opcode */
 172 #define ShortForm               (Modrm + 1)
 173 /* special case for jump insns.  */
 174 #define Jump                    (ShortForm + 1)
 175 /* call and jump */
 176 #define JumpDword               (Jump + 1)
 177 /* loop and jecxz */
 178 #define JumpByte                (JumpDword + 1)
 179 /* special case for intersegment leaps/calls */
 180 #define JumpInterSegment        (JumpByte + 1)
 181 /* FP insn memory format bit, sized by 0x4 */
 182 #define FloatMF                 (JumpInterSegment + 1)
 183 /* src/dest swap for floats. */
 184 #define FloatR                  (FloatMF + 1)
 185 /* has float insn direction bit. */
 186 #define FloatD                  (FloatR + 1)
 187 /* needs size prefix if in 32-bit mode */
 188 #define Size16                  (FloatD + 1)
 189 /* needs size prefix if in 16-bit mode */
 190 #define Size32                  (Size16 + 1)
 191 /* needs size prefix if in 64-bit mode */
 192 #define Size64                  (Size32 + 1)
 193 /* instruction ignores operand size prefix and in Intel mode ignores
 194    mnemonic size suffix check.  */
 195 #define IgnoreSize              (Size64 + 1)
 196 /* default insn size depends on mode */
 197 #define DefaultSize             (IgnoreSize + 1)
 198 /* b suffix on instruction illegal */
 199 #define No_bSuf                 (DefaultSize + 1)
 200 /* w suffix on instruction illegal */
 201 #define No_wSuf                 (No_bSuf + 1)
 202 /* l suffix on instruction illegal */
 203 #define No_lSuf                 (No_wSuf + 1)
 204 /* s suffix on instruction illegal */
 205 #define No_sSuf                 (No_lSuf + 1)
 206 /* q suffix on instruction illegal */
 207 #define No_qSuf                 (No_sSuf + 1)
 208 /* long double suffix on instruction illegal */
 209 #define No_ldSuf                (No_qSuf + 1)
 210 /* instruction needs FWAIT */
 211 #define FWait                   (No_ldSuf + 1)
 212 /* quick test for string instructions */
 213 #define IsString                (FWait + 1)
 214 /* fake an extra reg operand for clr, imul and special register
 215    processing for some instructions.  */
 216 #define RegKludge               (IsString + 1)
 217 /* The first operand must be xmm0 */
 218 #define FirstXmm0               (RegKludge + 1)
 219 /* An implicit xmm0 as the first operand */
 220 #define Implicit1stXmm0         (FirstXmm0 + 1)
 221 /* BYTE is OK in Intel syntax. */
 222 #define ByteOkIntel             (Implicit1stXmm0 + 1)
 223 /* Convert to DWORD */
 224 #define ToDword                 (ByteOkIntel + 1)
 225 /* Convert to QWORD */
 226 #define ToQword                 (ToDword + 1)
 227 /* Address prefix changes operand 0 */
 228 #define AddrPrefixOp0           (ToQword + 1)
 229 /* opcode is a prefix */
 230 #define IsPrefix                (AddrPrefixOp0 + 1)
 231 /* instruction has extension in 8 bit imm */
 232 #define ImmExt                  (IsPrefix + 1)
 233 /* instruction don't need Rex64 prefix.  */
 234 #define NoRex64                 (ImmExt + 1)
 235 /* instruction require Rex64 prefix.  */
 236 #define Rex64                   (NoRex64 + 1)
 237 /* deprecated fp insn, gets a warning */
 238 #define Ugh                     (Rex64 + 1)
 239 #define Drex                    (Ugh + 1)
 240 /* instruction needs DREX with multiple encodings for memory ops */
 241 #define Drexv                   (Drex + 1)
 242 /* special DREX for comparisons */
 243 #define Drexc                   (Drexv + 1)
 244 /* insn has VEX prefix. */
 245 #define Vex                     (Drexc + 1)
 246 /* insn has 256bit VEX prefix. */
 247 #define Vex256                  (Vex + 1)
 248 /* insn has VEX NDS. Register-only source is encoded in Vex
 249    prefix. */
 250 #define VexNDS                  (Vex256 + 1)
 251 /* insn has VEX NDD. Register destination is encoded in Vex
 252    prefix. */
 253 #define VexNDD                  (VexNDS + 1)
 254 /* insn has VEX W0. */
 255 #define VexW0                   (VexNDD + 1)
 256 /* insn has VEX W1. */
 257 #define VexW1                   (VexW0 + 1)
 258 /* insn has VEX 0x0F opcode prefix. */
 259 #define Vex0F                   (VexW1 + 1)
 260 /* insn has VEX 0x0F38 opcode prefix. */
 261 #define Vex0F38                 (Vex0F + 1)
 262 /* insn has VEX 0x0F3A opcode prefix. */
 263 #define Vex0F3A                 (Vex0F38 + 1)
 264 /* insn has VEX prefix with 3 soures. */
 265 #define Vex3Sources             (Vex0F3A + 1)
 266 /* instruction has VEX 8 bit imm */
 267 #define VexImmExt               (Vex3Sources + 1)
 268 /* SSE to AVX support required */
 269 #define SSE2AVX                 (VexImmExt + 1)
 270 /* No AVX equivalent */
 271 #define NoAVX                   (SSE2AVX + 1)
 272 /* Compatible with old (<= 2.8.1) versions of gcc  */
 273 #define OldGcc                  (NoAVX + 1)
 274 /* AT&T mnemonic.  */
 275 #define ATTMnemonic             (OldGcc + 1)
 276 /* AT&T syntax.  */
 277 #define ATTSyntax               (ATTMnemonic + 1)
 278 /* Intel syntax.  */
 279 #define IntelSyntax             (ATTSyntax + 1)
 280 /* The last bitfield in i386_opcode_modifier.  */
 281 #define Opcode_Modifier_Max     IntelSyntax
 282
 283 typedef struct i386_opcode_modifier
 284 {
 285   unsigned int d:1;
 286   unsigned int w:1;
 287   unsigned int modrm:1;
 288   unsigned int shortform:1;
 289   unsigned int jump:1;
 290   unsigned int jumpdword:1;
 291   unsigned int jumpbyte:1;
 292   unsigned int jumpintersegment:1;
 293   unsigned int floatmf:1;
 294   unsigned int floatr:1;
 295   unsigned int floatd:1;
 296   unsigned int size16:1;
 297   unsigned int size32:1;
 298   unsigned int size64:1;
 299   unsigned int ignoresize:1;
 300   unsigned int defaultsize:1;
 301   unsigned int no_bsuf:1;
 302   unsigned int no_wsuf:1;
 303   unsigned int no_lsuf:1;
 304   unsigned int no_ssuf:1;
 305   unsigned int no_qsuf:1;
 306   unsigned int no_ldsuf:1;
 307   unsigned int fwait:1;
 308   unsigned int isstring:1;
 309   unsigned int regkludge:1;
 310   unsigned int firstxmm0:1;
 311   unsigned int implicit1stxmm0:1;
 312   unsigned int byteokintel:1;
 313   unsigned int todword:1;
 314   unsigned int toqword:1;
 315   unsigned int addrprefixop0:1;
 316   unsigned int isprefix:1;
 317   unsigned int immext:1;
 318   unsigned int norex64:1;
 319   unsigned int rex64:1;
 320   unsigned int ugh:1;
 321   unsigned int drex:1;
 322   unsigned int drexv:1;
 323   unsigned int drexc:1;
 324   unsigned int vex:1;
 325   unsigned int vex256:1;
 326   unsigned int vexnds:1;
 327   unsigned int vexndd:1;
 328   unsigned int vexw0:1;
 329   unsigned int vexw1:1;
 330   unsigned int vex0f:1;
 331   unsigned int vex0f38:1;
 332   unsigned int vex0f3a:1;
 333   unsigned int vex3sources:1;
 334   unsigned int veximmext:1;
 335   unsigned int sse2avx:1;
 336   unsigned int noavx:1;
 337   unsigned int oldgcc:1;
 338   unsigned int attmnemonic:1;
 339   unsigned int attsyntax:1;
 340   unsigned int intelsyntax:1;
 341 } i386_opcode_modifier;
 342
 343 /* Position of operand_type bits.  */
 344
 345 /* 8bit register */
 346 #define Reg8                    0
 347 /* 16bit register */
 348 #define Reg16                   (Reg8 + 1)
 349 /* 32bit register */
 350 #define Reg32                   (Reg16 + 1)
 351 /* 64bit register */
 352 #define Reg64                   (Reg32 + 1)
 353 /* Floating pointer stack register */
 354 #define FloatReg                (Reg64 + 1)
 355 /* MMX register */
 356 #define RegMMX                  (FloatReg + 1)
 357 /* SSE register */
 358 #define RegXMM                  (RegMMX + 1)
 359 /* AVX registers */
 360 #define RegYMM                  (RegXMM + 1)
 361 /* Control register */
 362 #define Control                 (RegYMM + 1)
 363 /* Debug register */
 364 #define Debug                   (Control + 1)
 365 /* Test register */
 366 #define Test                    (Debug + 1)
 367 /* 2 bit segment register */
 368 #define SReg2                   (Test + 1)
 369 /* 3 bit segment register */
 370 #define SReg3                   (SReg2 + 1)
 371 /* 1 bit immediate */
 372 #define Imm1                    (SReg3 + 1)
 373 /* 8 bit immediate */
 374 #define Imm8                    (Imm1 + 1)
 375 /* 8 bit immediate sign extended */
 376 #define Imm8S                   (Imm8 + 1)
 377 /* 16 bit immediate */
 378 #define Imm16                   (Imm8S + 1)
 379 /* 32 bit immediate */
 380 #define Imm32                   (Imm16 + 1)
 381 /* 32 bit immediate sign extended */
 382 #define Imm32S                  (Imm32 + 1)
 383 /* 64 bit immediate */
 384 #define Imm64                   (Imm32S + 1)
 385 /* 8bit/16bit/32bit displacements are used in different ways,
 386    depending on the instruction.  For jumps, they specify the
 387    size of the PC relative displacement, for instructions with
 388    memory operand, they specify the size of the offset relative
 389    to the base register, and for instructions with memory offset
 390    such as `mov 1234,%al' they specify the size of the offset
 391    relative to the segment base.  */
 392 /* 8 bit displacement */
 393 #define Disp8                   (Imm64 + 1)
 394 /* 16 bit displacement */
 395 #define Disp16                  (Disp8 + 1)
 396 /* 32 bit displacement */
 397 #define Disp32                  (Disp16 + 1)
 398 /* 32 bit signed displacement */
 399 #define Disp32S                 (Disp32 + 1)
 400 /* 64 bit displacement */
 401 #define Disp64                  (Disp32S + 1)
 402 /* Accumulator %al/%ax/%eax/%rax */
 403 #define Acc                     (Disp64 + 1)
 404 /* Floating pointer top stack register %st(0) */
 405 #define FloatAcc                (Acc + 1)
 406 /* Register which can be used for base or index in memory operand.  */
 407 #define BaseIndex               (FloatAcc + 1)
 408 /* Register to hold in/out port addr = dx */
 409 #define InOutPortReg            (BaseIndex + 1)
 410 /* Register to hold shift count = cl */
 411 #define ShiftCount              (InOutPortReg + 1)
 412 /* Absolute address for jump.  */
 413 #define JumpAbsolute            (ShiftCount + 1)
 414 /* String insn operand with fixed es segment */
 415 #define EsSeg                   (JumpAbsolute + 1)
 416 /* RegMem is for instructions with a modrm byte where the register
 417    destination operand should be encoded in the mod and regmem fields.
 418    Normally, it will be encoded in the reg field. We add a RegMem
 419    flag to the destination register operand to indicate that it should
 420    be encoded in the regmem field.  */
 421 #define RegMem                  (EsSeg + 1)
 422 /* Memory.  */
 423 #define Mem                     (RegMem + 1)
 424 /* BYTE memory. */
 425 #define Byte                    (Mem + 1)
 426 /* WORD memory. 2 byte */
 427 #define Word                    (Byte + 1)
 428 /* DWORD memory. 4 byte */
 429 #define Dword                   (Word + 1)
 430 /* FWORD memory. 6 byte */
 431 #define Fword                   (Dword + 1)
 432 /* QWORD memory. 8 byte */
 433 #define Qword                   (Fword + 1)
 434 /* TBYTE memory. 10 byte */
 435 #define Tbyte                   (Qword + 1)
 436 /* XMMWORD memory. */
 437 #define Xmmword                 (Tbyte + 1)
 438 /* YMMWORD memory. */
 439 #define Ymmword                 (Xmmword + 1)
 440 /* Unspecified memory size.  */
 441 #define Unspecified             (Ymmword + 1)
 442 /* Any memory size.  */
 443 #define Anysize                 (Unspecified  + 1)
 444
 445 /* VEX 4 bit immediate */
 446 #define Vex_Imm4                (Anysize + 1)
 447
 448 /* The last bitfield in i386_operand_type.  */
 449 #define OTMax                   Vex_Imm4
 450
 451 #define OTNumOfUints \
 452   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 453 #define OTNumOfBits \
 454   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 455
 456 /* If you get a compiler error for zero width of the unused field,
 457    comment it out.  */
 458 #define OTUnused                (OTMax + 1)
 459
 460 typedef union i386_operand_type
 461 {
 462   struct
 463     {
 464       unsigned int reg8:1;
 465       unsigned int reg16:1;
 466       unsigned int reg32:1;
 467       unsigned int reg64:1;
 468       unsigned int floatreg:1;
 469       unsigned int regmmx:1;
 470       unsigned int regxmm:1;
 471       unsigned int regymm:1;
 472       unsigned int control:1;
 473       unsigned int debug:1;
 474       unsigned int test:1;
 475       unsigned int sreg2:1;
 476       unsigned int sreg3:1;
 477       unsigned int imm1:1;
 478       unsigned int imm8:1;
 479       unsigned int imm8s:1;
 480       unsigned int imm16:1;
 481       unsigned int imm32:1;
 482       unsigned int imm32s:1;
 483       unsigned int imm64:1;
 484       unsigned int disp8:1;
 485       unsigned int disp16:1;
 486       unsigned int disp32:1;
 487       unsigned int disp32s:1;
 488       unsigned int disp64:1;
 489       unsigned int acc:1;
 490       unsigned int floatacc:1;
 491       unsigned int baseindex:1;
 492       unsigned int inoutportreg:1;
 493       unsigned int shiftcount:1;
 494       unsigned int jumpabsolute:1;
 495       unsigned int esseg:1;
 496       unsigned int regmem:1;
 497       unsigned int mem:1;
 498       unsigned int byte:1;
 499       unsigned int word:1;
 500       unsigned int dword:1;
 501       unsigned int fword:1;
 502       unsigned int qword:1;
 503       unsigned int tbyte:1;
 504       unsigned int xmmword:1;
 505       unsigned int ymmword:1;
 506       unsigned int unspecified:1;
 507       unsigned int anysize:1;
 508       unsigned int vex_imm4:1;
 509 #ifdef OTUnused
 510       unsigned int unused:(OTNumOfBits - OTUnused);
 511 #endif
 512     } bitfield;
 513   unsigned int array[OTNumOfUints];
 514 } i386_operand_type;
 515
 516 typedef struct template
 517 {
 518   /* instruction name sans width suffix ("mov" for movl insns) */
 519   char *name;
 520
 521   /* how many operands */
 522   unsigned int operands;
 523
 524   /* base_opcode is the fundamental opcode byte without optional
 525      prefix(es).  */
 526   unsigned int base_opcode;
 527 #define Opcode_D        0x2 /* Direction bit:
 528                                set if Reg --> Regmem;
 529                                unset if Regmem --> Reg. */
 530 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 531 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 532
 533   /* extension_opcode is the 3 bit extension for group <n> insns.
 534      This field is also used to store the 8-bit opcode suffix for the
 535      AMD 3DNow! instructions.
 536      If this template has no extension opcode (the usual case) use None
 537      Instructions with Drex use this to specify 2 bits for OC */
 538   unsigned int extension_opcode;
 539 #define None 0xffff             /* If no extension_opcode is possible.  */
 540
 541   /* Opcode length.  */
 542   unsigned char opcode_length;
 543
 544   /* cpu feature flags */
 545   i386_cpu_flags cpu_flags;
 546
 547   /* the bits in opcode_modifier are used to generate the final opcode from
 548      the base_opcode.  These bits also are used to detect alternate forms of
 549      the same instruction */
 550   i386_opcode_modifier opcode_modifier;
 551
 552   /* operand_types[i] describes the type of operand i.  This is made
 553      by OR'ing together all of the possible type masks.  (e.g.
 554      'operand_types[i] = Reg|Imm' specifies that operand i can be
 555      either a register or an immediate operand.  */
 556   i386_operand_type operand_types[MAX_OPERANDS];
 557 }
 558 template;
 559
 560 extern const template i386_optab[];
 561
 562 /* these are for register name --> number & type hash lookup */
 563 typedef struct
 564 {
 565   char *reg_name;
 566   i386_operand_type reg_type;
 567   unsigned char reg_flags;
 568 #define RegRex      0x1  /* Extended register.  */
 569 #define RegRex64    0x2  /* Extended 8 bit register.  */
 570   unsigned char reg_num;
 571 #define RegRip  ((unsigned char ) ~0)
 572 #define RegEip  (RegRip - 1)
 573 /* EIZ and RIZ are fake index registers.  */
 574 #define RegEiz  (RegEip - 1)
 575 #define RegRiz  (RegEiz - 1)
 576 /* FLAT is a fake segment register (Intel mode).  */
 577 #define RegFlat     ((unsigned char) ~0)
 578   signed char dw2_regnum[2];
 579 #define Dw2Inval (-1)
 580 }
 581 reg_entry;
 582
 583 /* Entries in i386_regtab.  */
 584 #define REGNAM_AL 1
 585 #define REGNAM_AX 25
 586 #define REGNAM_EAX 41
 587
 588 extern const reg_entry i386_regtab[];
 589 extern const unsigned int i386_regtab_size;
 590
 591 typedef struct
 592 {
 593   char *seg_name;
 594   unsigned int seg_prefix;
 595 }
 596 seg_entry;
 597
 598 extern const seg_entry cs;
 599 extern const seg_entry ds;
 600 extern const seg_entry ss;
 601 extern const seg_entry es;
 602 extern const seg_entry fs;
 603 extern const seg_entry gs;