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* config/tc-s390.c: Add missing prototypes
[binutils.git] / bfd / coff-sh.c
blobf3b74e91fba569c9f5d7202e662d9faa9b34d4ed
1 /* BFD back-end for Hitachi Super-H COFF binaries.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Cygnus Support.
5 Written by Steve Chamberlain, <sac@cygnus.com>.
6 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7
8 This file is part of BFD, the Binary File Descriptor library.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "bfd.h"
25 #include "sysdep.h"
26 #include "libiberty.h"
27 #include "libbfd.h"
28 #include "bfdlink.h"
29 #include "coff/sh.h"
30 #include "coff/internal.h"
31
32 #ifdef COFF_WITH_PE
33 #include "coff/pe.h"
34
35 #ifndef COFF_IMAGE_WITH_PE
36 static boolean sh_align_load_span
37 PARAMS ((bfd *, asection *, bfd_byte *,
38 boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
39 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, boolean *));
40
41 #define _bfd_sh_align_load_span sh_align_load_span
42 #endif
43 #endif
44
45 #include "libcoff.h"
46
47 /* Internal functions. */
48 static bfd_reloc_status_type sh_reloc
49 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
50 static long get_symbol_value PARAMS ((asymbol *));
51 static boolean sh_relax_section
52 PARAMS ((bfd *, asection *, struct bfd_link_info *, boolean *));
53 static boolean sh_relax_delete_bytes
54 PARAMS ((bfd *, asection *, bfd_vma, int));
55 #ifndef COFF_IMAGE_WITH_PE
56 static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
57 #endif
58 static boolean sh_align_loads
59 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, boolean *));
60 static boolean sh_swap_insns
61 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
62 static boolean sh_relocate_section
63 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
64 struct internal_reloc *, struct internal_syment *, asection **));
65 static bfd_byte *sh_coff_get_relocated_section_contents
66 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
67 bfd_byte *, boolean, asymbol **));
68 static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
69
70 #ifdef COFF_WITH_PE
71 /* Can't build import tables with 2**4 alignment. */
72 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
73 #else
74 /* Default section alignment to 2**4. */
75 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
76 #endif
77
78 #ifdef COFF_IMAGE_WITH_PE
79 /* Align PE executables. */
80 #define COFF_PAGE_SIZE 0x1000
81 #endif
82
83 /* Generate long file names. */
84 #define COFF_LONG_FILENAMES
85
86 #ifdef COFF_WITH_PE
87 static boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
88 /* Return true if this relocation should
89 appear in the output .reloc section. */
90 static boolean in_reloc_p (abfd, howto)
91 bfd * abfd ATTRIBUTE_UNUSED;
92 reloc_howto_type * howto;
93 {
94 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
95 }
96 #endif
97
98 /* The supported relocations. There are a lot of relocations defined
99 in coff/internal.h which we do not expect to ever see. */
100 static reloc_howto_type sh_coff_howtos[] =
101 {
102 EMPTY_HOWTO (0),
103 EMPTY_HOWTO (1),
104 #ifdef COFF_WITH_PE
105 /* Windows CE */
106 HOWTO (R_SH_IMM32CE, /* type */
107 0, /* rightshift */
108 2, /* size (0 = byte, 1 = short, 2 = long) */
109 32, /* bitsize */
110 false, /* pc_relative */
111 0, /* bitpos */
112 complain_overflow_bitfield, /* complain_on_overflow */
113 sh_reloc, /* special_function */
114 "r_imm32ce", /* name */
115 true, /* partial_inplace */
116 0xffffffff, /* src_mask */
117 0xffffffff, /* dst_mask */
118 false), /* pcrel_offset */
119 #else
120 EMPTY_HOWTO (2),
121 #endif
122 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
123 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
124 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
125 EMPTY_HOWTO (6), /* R_SH_IMM24 */
126 EMPTY_HOWTO (7), /* R_SH_LOW16 */
127 EMPTY_HOWTO (8),
128 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
129
130 HOWTO (R_SH_PCDISP8BY2, /* type */
131 1, /* rightshift */
132 1, /* size (0 = byte, 1 = short, 2 = long) */
133 8, /* bitsize */
134 true, /* pc_relative */
135 0, /* bitpos */
136 complain_overflow_signed, /* complain_on_overflow */
137 sh_reloc, /* special_function */
138 "r_pcdisp8by2", /* name */
139 true, /* partial_inplace */
140 0xff, /* src_mask */
141 0xff, /* dst_mask */
142 true), /* pcrel_offset */
143
144 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
145
146 HOWTO (R_SH_PCDISP, /* type */
147 1, /* rightshift */
148 1, /* size (0 = byte, 1 = short, 2 = long) */
149 12, /* bitsize */
150 true, /* pc_relative */
151 0, /* bitpos */
152 complain_overflow_signed, /* complain_on_overflow */
153 sh_reloc, /* special_function */
154 "r_pcdisp12by2", /* name */
155 true, /* partial_inplace */
156 0xfff, /* src_mask */
157 0xfff, /* dst_mask */
158 true), /* pcrel_offset */
159
160 EMPTY_HOWTO (13),
161
162 HOWTO (R_SH_IMM32, /* type */
163 0, /* rightshift */
164 2, /* size (0 = byte, 1 = short, 2 = long) */
165 32, /* bitsize */
166 false, /* pc_relative */
167 0, /* bitpos */
168 complain_overflow_bitfield, /* complain_on_overflow */
169 sh_reloc, /* special_function */
170 "r_imm32", /* name */
171 true, /* partial_inplace */
172 0xffffffff, /* src_mask */
173 0xffffffff, /* dst_mask */
174 false), /* pcrel_offset */
175
176 EMPTY_HOWTO (15),
177 #ifdef COFF_WITH_PE
178 HOWTO (R_SH_IMAGEBASE, /* type */
179 0, /* rightshift */
180 2, /* size (0 = byte, 1 = short, 2 = long) */
181 32, /* bitsize */
182 false, /* pc_relative */
183 0, /* bitpos */
184 complain_overflow_bitfield, /* complain_on_overflow */
185 sh_reloc, /* special_function */
186 "rva32", /* name */
187 true, /* partial_inplace */
188 0xffffffff, /* src_mask */
189 0xffffffff, /* dst_mask */
190 false), /* pcrel_offset */
191 #else
192 EMPTY_HOWTO (16), /* R_SH_IMM8 */
193 #endif
194 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
195 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
196 EMPTY_HOWTO (19), /* R_SH_IMM4 */
197 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
198 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
199
200 HOWTO (R_SH_PCRELIMM8BY2, /* type */
201 1, /* rightshift */
202 1, /* size (0 = byte, 1 = short, 2 = long) */
203 8, /* bitsize */
204 true, /* pc_relative */
205 0, /* bitpos */
206 complain_overflow_unsigned, /* complain_on_overflow */
207 sh_reloc, /* special_function */
208 "r_pcrelimm8by2", /* name */
209 true, /* partial_inplace */
210 0xff, /* src_mask */
211 0xff, /* dst_mask */
212 true), /* pcrel_offset */
213
214 HOWTO (R_SH_PCRELIMM8BY4, /* type */
215 2, /* rightshift */
216 1, /* size (0 = byte, 1 = short, 2 = long) */
217 8, /* bitsize */
218 true, /* pc_relative */
219 0, /* bitpos */
220 complain_overflow_unsigned, /* complain_on_overflow */
221 sh_reloc, /* special_function */
222 "r_pcrelimm8by4", /* name */
223 true, /* partial_inplace */
224 0xff, /* src_mask */
225 0xff, /* dst_mask */
226 true), /* pcrel_offset */
227
228 HOWTO (R_SH_IMM16, /* type */
229 0, /* rightshift */
230 1, /* size (0 = byte, 1 = short, 2 = long) */
231 16, /* bitsize */
232 false, /* pc_relative */
233 0, /* bitpos */
234 complain_overflow_bitfield, /* complain_on_overflow */
235 sh_reloc, /* special_function */
236 "r_imm16", /* name */
237 true, /* partial_inplace */
238 0xffff, /* src_mask */
239 0xffff, /* dst_mask */
240 false), /* pcrel_offset */
241
242 HOWTO (R_SH_SWITCH16, /* type */
243 0, /* rightshift */
244 1, /* size (0 = byte, 1 = short, 2 = long) */
245 16, /* bitsize */
246 false, /* pc_relative */
247 0, /* bitpos */
248 complain_overflow_bitfield, /* complain_on_overflow */
249 sh_reloc, /* special_function */
250 "r_switch16", /* name */
251 true, /* partial_inplace */
252 0xffff, /* src_mask */
253 0xffff, /* dst_mask */
254 false), /* pcrel_offset */
255
256 HOWTO (R_SH_SWITCH32, /* type */
257 0, /* rightshift */
258 2, /* size (0 = byte, 1 = short, 2 = long) */
259 32, /* bitsize */
260 false, /* pc_relative */
261 0, /* bitpos */
262 complain_overflow_bitfield, /* complain_on_overflow */
263 sh_reloc, /* special_function */
264 "r_switch32", /* name */
265 true, /* partial_inplace */
266 0xffffffff, /* src_mask */
267 0xffffffff, /* dst_mask */
268 false), /* pcrel_offset */
269
270 HOWTO (R_SH_USES, /* type */
271 0, /* rightshift */
272 1, /* size (0 = byte, 1 = short, 2 = long) */
273 16, /* bitsize */
274 false, /* pc_relative */
275 0, /* bitpos */
276 complain_overflow_bitfield, /* complain_on_overflow */
277 sh_reloc, /* special_function */
278 "r_uses", /* name */
279 true, /* partial_inplace */
280 0xffff, /* src_mask */
281 0xffff, /* dst_mask */
282 false), /* pcrel_offset */
283
284 HOWTO (R_SH_COUNT, /* type */
285 0, /* rightshift */
286 2, /* size (0 = byte, 1 = short, 2 = long) */
287 32, /* bitsize */
288 false, /* pc_relative */
289 0, /* bitpos */
290 complain_overflow_bitfield, /* complain_on_overflow */
291 sh_reloc, /* special_function */
292 "r_count", /* name */
293 true, /* partial_inplace */
294 0xffffffff, /* src_mask */
295 0xffffffff, /* dst_mask */
296 false), /* pcrel_offset */
297
298 HOWTO (R_SH_ALIGN, /* type */
299 0, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
301 32, /* bitsize */
302 false, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_bitfield, /* complain_on_overflow */
305 sh_reloc, /* special_function */
306 "r_align", /* name */
307 true, /* partial_inplace */
308 0xffffffff, /* src_mask */
309 0xffffffff, /* dst_mask */
310 false), /* pcrel_offset */
311
312 HOWTO (R_SH_CODE, /* type */
313 0, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
315 32, /* bitsize */
316 false, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_bitfield, /* complain_on_overflow */
319 sh_reloc, /* special_function */
320 "r_code", /* name */
321 true, /* partial_inplace */
322 0xffffffff, /* src_mask */
323 0xffffffff, /* dst_mask */
324 false), /* pcrel_offset */
325
326 HOWTO (R_SH_DATA, /* type */
327 0, /* rightshift */
328 2, /* size (0 = byte, 1 = short, 2 = long) */
329 32, /* bitsize */
330 false, /* pc_relative */
331 0, /* bitpos */
332 complain_overflow_bitfield, /* complain_on_overflow */
333 sh_reloc, /* special_function */
334 "r_data", /* name */
335 true, /* partial_inplace */
336 0xffffffff, /* src_mask */
337 0xffffffff, /* dst_mask */
338 false), /* pcrel_offset */
339
340 HOWTO (R_SH_LABEL, /* type */
341 0, /* rightshift */
342 2, /* size (0 = byte, 1 = short, 2 = long) */
343 32, /* bitsize */
344 false, /* pc_relative */
345 0, /* bitpos */
346 complain_overflow_bitfield, /* complain_on_overflow */
347 sh_reloc, /* special_function */
348 "r_label", /* name */
349 true, /* partial_inplace */
350 0xffffffff, /* src_mask */
351 0xffffffff, /* dst_mask */
352 false), /* pcrel_offset */
353
354 HOWTO (R_SH_SWITCH8, /* type */
355 0, /* rightshift */
356 0, /* size (0 = byte, 1 = short, 2 = long) */
357 8, /* bitsize */
358 false, /* pc_relative */
359 0, /* bitpos */
360 complain_overflow_bitfield, /* complain_on_overflow */
361 sh_reloc, /* special_function */
362 "r_switch8", /* name */
363 true, /* partial_inplace */
364 0xff, /* src_mask */
365 0xff, /* dst_mask */
366 false) /* pcrel_offset */
367 };
368
369 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
370
371 /* Check for a bad magic number. */
372 #define BADMAG(x) SHBADMAG(x)
373
374 /* Customize coffcode.h (this is not currently used). */
375 #define SH 1
376
377 /* FIXME: This should not be set here. */
378 #define __A_MAGIC_SET__
379
380 #ifndef COFF_WITH_PE
381 /* Swap the r_offset field in and out. */
382 #define SWAP_IN_RELOC_OFFSET bfd_h_get_32
383 #define SWAP_OUT_RELOC_OFFSET bfd_h_put_32
384
385 /* Swap out extra information in the reloc structure. */
386 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
387 do \
388 { \
389 dst->r_stuff[0] = 'S'; \
390 dst->r_stuff[1] = 'C'; \
391 } \
392 while (0)
393 #endif
394
395 /* Get the value of a symbol, when performing a relocation. */
396
397 static long
398 get_symbol_value (symbol)
399 asymbol *symbol;
400 {
401 bfd_vma relocation;
402
403 if (bfd_is_com_section (symbol->section))
404 relocation = 0;
405 else
406 relocation = (symbol->value +
407 symbol->section->output_section->vma +
408 symbol->section->output_offset);
409
410 return relocation;
411 }
412
413 #ifdef COFF_WITH_PE
414 /* Convert an rtype to howto for the COFF backend linker.
415 Copied from coff-i386. */
416 #define coff_rtype_to_howto coff_sh_rtype_to_howto
417 static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *));
418
419 static reloc_howto_type *
420 coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
421 bfd * abfd ATTRIBUTE_UNUSED;
422 asection * sec;
423 struct internal_reloc * rel;
424 struct coff_link_hash_entry * h;
425 struct internal_syment * sym;
426 bfd_vma * addendp;
427 {
428 reloc_howto_type * howto;
429
430 howto = sh_coff_howtos + rel->r_type;
431
432 *addendp = 0;
433
434 if (howto->pc_relative)
435 *addendp += sec->vma;
436
437 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
438 {
439 /* This is a common symbol. The section contents include the
440 size (sym->n_value) as an addend. The relocate_section
441 function will be adding in the final value of the symbol. We
442 need to subtract out the current size in order to get the
443 correct result. */
444 BFD_ASSERT (h != NULL);
445 }
446
447 if (howto->pc_relative)
448 {
449 *addendp -= 4;
450
451 /* If the symbol is defined, then the generic code is going to
452 add back the symbol value in order to cancel out an
453 adjustment it made to the addend. However, we set the addend
454 to 0 at the start of this function. We need to adjust here,
455 to avoid the adjustment the generic code will make. FIXME:
456 This is getting a bit hackish. */
457 if (sym != NULL && sym->n_scnum != 0)
458 *addendp -= sym->n_value;
459 }
460
461 if (rel->r_type == R_SH_IMAGEBASE)
462 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
463
464 return howto;
465 }
466
467 #endif /* COFF_WITH_PE */
468
469 /* This structure is used to map BFD reloc codes to SH PE relocs. */
470 struct shcoff_reloc_map
471 {
472 unsigned char bfd_reloc_val;
473 unsigned char shcoff_reloc_val;
474 };
475
476 /* An array mapping BFD reloc codes to SH PE relocs. */
477 static const struct shcoff_reloc_map sh_reloc_map[] =
478 {
479 { BFD_RELOC_32, R_SH_IMM32CE },
480 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
481 { BFD_RELOC_CTOR, R_SH_IMM32CE },
482 };
483
484 /* Given a BFD reloc code, return the howto structure for the
485 corresponding SH PE reloc. */
486 #define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
487
488 static reloc_howto_type *
489 sh_coff_reloc_type_lookup (abfd, code)
490 bfd * abfd ATTRIBUTE_UNUSED;
491 bfd_reloc_code_real_type code;
492 {
493 unsigned int i;
494
495 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
496 if (sh_reloc_map[i].bfd_reloc_val == code)
497 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
498
499 fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
500 return NULL;
501 }
502
503 /* This macro is used in coffcode.h to get the howto corresponding to
504 an internal reloc. */
505
506 #define RTYPE2HOWTO(relent, internal) \
507 ((relent)->howto = \
508 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
509 ? &sh_coff_howtos[(internal)->r_type] \
510 : (reloc_howto_type *) NULL))
511
512 /* This is the same as the macro in coffcode.h, except that it copies
513 r_offset into reloc_entry->addend for some relocs. */
514 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
515 { \
516 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
517 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
518 coffsym = (obj_symbols (abfd) \
519 + (cache_ptr->sym_ptr_ptr - symbols)); \
520 else if (ptr) \
521 coffsym = coff_symbol_from (abfd, ptr); \
522 if (coffsym != (coff_symbol_type *) NULL \
523 && coffsym->native->u.syment.n_scnum == 0) \
524 cache_ptr->addend = 0; \
525 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
526 && ptr->section != (asection *) NULL) \
527 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
528 else \
529 cache_ptr->addend = 0; \
530 if ((reloc).r_type == R_SH_SWITCH8 \
531 || (reloc).r_type == R_SH_SWITCH16 \
532 || (reloc).r_type == R_SH_SWITCH32 \
533 || (reloc).r_type == R_SH_USES \
534 || (reloc).r_type == R_SH_COUNT \
535 || (reloc).r_type == R_SH_ALIGN) \
536 cache_ptr->addend = (reloc).r_offset; \
537 }
538
539 /* This is the howto function for the SH relocations. */
540
541 static bfd_reloc_status_type
542 sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
543 error_message)
544 bfd *abfd;
545 arelent *reloc_entry;
546 asymbol *symbol_in;
547 PTR data;
548 asection *input_section;
549 bfd *output_bfd;
550 char **error_message ATTRIBUTE_UNUSED;
551 {
552 unsigned long insn;
553 bfd_vma sym_value;
554 unsigned short r_type;
555 bfd_vma addr = reloc_entry->address;
556 bfd_byte *hit_data = addr + (bfd_byte *) data;
557
558 r_type = reloc_entry->howto->type;
559
560 if (output_bfd != NULL)
561 {
562 /* Partial linking--do nothing. */
563 reloc_entry->address += input_section->output_offset;
564 return bfd_reloc_ok;
565 }
566
567 /* Almost all relocs have to do with relaxing. If any work must be
568 done for them, it has been done in sh_relax_section. */
569 if (r_type != R_SH_IMM32
570 #ifdef COFF_WITH_PE
571 && r_type != R_SH_IMM32CE
572 && r_type != R_SH_IMAGEBASE
573 #endif
574 && (r_type != R_SH_PCDISP
575 || (symbol_in->flags & BSF_LOCAL) != 0))
576 return bfd_reloc_ok;
577
578 if (symbol_in != NULL
579 && bfd_is_und_section (symbol_in->section))
580 return bfd_reloc_undefined;
581
582 sym_value = get_symbol_value (symbol_in);
583
584 switch (r_type)
585 {
586 case R_SH_IMM32:
587 #ifdef COFF_WITH_PE
588 case R_SH_IMM32CE:
589 #endif
590 insn = bfd_get_32 (abfd, hit_data);
591 insn += sym_value + reloc_entry->addend;
592 bfd_put_32 (abfd, insn, hit_data);
593 break;
594 #ifdef COFF_WITH_PE
595 case R_SH_IMAGEBASE:
596 insn = bfd_get_32 (abfd, hit_data);
597 insn += (sym_value + reloc_entry->addend
598 - pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase);
599 bfd_put_32 (abfd, insn, hit_data);
600 break;
601 #endif
602 case R_SH_PCDISP:
603 insn = bfd_get_16 (abfd, hit_data);
604 sym_value += reloc_entry->addend;
605 sym_value -= (input_section->output_section->vma
606 + input_section->output_offset
607 + addr
608 + 4);
609 sym_value += (insn & 0xfff) << 1;
610 if (insn & 0x800)
611 sym_value -= 0x1000;
612 insn = (insn & 0xf000) | (sym_value & 0xfff);
613 bfd_put_16 (abfd, insn, hit_data);
614 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
615 return bfd_reloc_overflow;
616 break;
617 default:
618 abort ();
619 break;
620 }
621
622 return bfd_reloc_ok;
623 }
624
625 #define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
626
627 /* We can do relaxing. */
628 #define coff_bfd_relax_section sh_relax_section
629
630 /* We use the special COFF backend linker. */
631 #define coff_relocate_section sh_relocate_section
632
633 /* When relaxing, we need to use special code to get the relocated
634 section contents. */
635 #define coff_bfd_get_relocated_section_contents \
636 sh_coff_get_relocated_section_contents
637
638 #include "coffcode.h"
639 \f
640 /* This function handles relaxing on the SH.
641
642 Function calls on the SH look like this:
643
644 movl L1,r0
645 ...
646 jsr @r0
647 ...
648 L1:
649 .long function
650
651 The compiler and assembler will cooperate to create R_SH_USES
652 relocs on the jsr instructions. The r_offset field of the
653 R_SH_USES reloc is the PC relative offset to the instruction which
654 loads the register (the r_offset field is computed as though it
655 were a jump instruction, so the offset value is actually from four
656 bytes past the instruction). The linker can use this reloc to
657 determine just which function is being called, and thus decide
658 whether it is possible to replace the jsr with a bsr.
659
660 If multiple function calls are all based on a single register load
661 (i.e., the same function is called multiple times), the compiler
662 guarantees that each function call will have an R_SH_USES reloc.
663 Therefore, if the linker is able to convert each R_SH_USES reloc
664 which refers to that address, it can safely eliminate the register
665 load.
666
667 When the assembler creates an R_SH_USES reloc, it examines it to
668 determine which address is being loaded (L1 in the above example).
669 It then counts the number of references to that address, and
670 creates an R_SH_COUNT reloc at that address. The r_offset field of
671 the R_SH_COUNT reloc will be the number of references. If the
672 linker is able to eliminate a register load, it can use the
673 R_SH_COUNT reloc to see whether it can also eliminate the function
674 address.
675
676 SH relaxing also handles another, unrelated, matter. On the SH, if
677 a load or store instruction is not aligned on a four byte boundary,
678 the memory cycle interferes with the 32 bit instruction fetch,
679 causing a one cycle bubble in the pipeline. Therefore, we try to
680 align load and store instructions on four byte boundaries if we
681 can, by swapping them with one of the adjacent instructions. */
682
683 static boolean
684 sh_relax_section (abfd, sec, link_info, again)
685 bfd *abfd;
686 asection *sec;
687 struct bfd_link_info *link_info;
688 boolean *again;
689 {
690 struct internal_reloc *internal_relocs;
691 struct internal_reloc *free_relocs = NULL;
692 boolean have_code;
693 struct internal_reloc *irel, *irelend;
694 bfd_byte *contents = NULL;
695 bfd_byte *free_contents = NULL;
696
697 *again = false;
698
699 if (link_info->relocateable
700 || (sec->flags & SEC_RELOC) == 0
701 || sec->reloc_count == 0)
702 return true;
703
704 /* If this is the first time we have been called for this section,
705 initialize the cooked size. */
706 if (sec->_cooked_size == 0)
707 sec->_cooked_size = sec->_raw_size;
708
709 internal_relocs = (_bfd_coff_read_internal_relocs
710 (abfd, sec, link_info->keep_memory,
711 (bfd_byte *) NULL, false,
712 (struct internal_reloc *) NULL));
713 if (internal_relocs == NULL)
714 goto error_return;
715 if (! link_info->keep_memory)
716 free_relocs = internal_relocs;
717
718 have_code = false;
719
720 irelend = internal_relocs + sec->reloc_count;
721 for (irel = internal_relocs; irel < irelend; irel++)
722 {
723 bfd_vma laddr, paddr, symval;
724 unsigned short insn;
725 struct internal_reloc *irelfn, *irelscan, *irelcount;
726 struct internal_syment sym;
727 bfd_signed_vma foff;
728
729 if (irel->r_type == R_SH_CODE)
730 have_code = true;
731
732 if (irel->r_type != R_SH_USES)
733 continue;
734
735 /* Get the section contents. */
736 if (contents == NULL)
737 {
738 if (coff_section_data (abfd, sec) != NULL
739 && coff_section_data (abfd, sec)->contents != NULL)
740 contents = coff_section_data (abfd, sec)->contents;
741 else
742 {
743 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
744 if (contents == NULL)
745 goto error_return;
746 free_contents = contents;
747
748 if (! bfd_get_section_contents (abfd, sec, contents,
749 (file_ptr) 0, sec->_raw_size))
750 goto error_return;
751 }
752 }
753
754 /* The r_offset field of the R_SH_USES reloc will point us to
755 the register load. The 4 is because the r_offset field is
756 computed as though it were a jump offset, which are based
757 from 4 bytes after the jump instruction. */
758 laddr = irel->r_vaddr - sec->vma + 4;
759 /* Careful to sign extend the 32-bit offset. */
760 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
761 if (laddr >= sec->_raw_size)
762 {
763 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset",
764 bfd_get_filename (abfd),
765 (unsigned long) irel->r_vaddr);
766 continue;
767 }
768 insn = bfd_get_16 (abfd, contents + laddr);
769
770 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
771 if ((insn & 0xf000) != 0xd000)
772 {
773 ((*_bfd_error_handler)
774 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
775 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr, insn));
776 continue;
777 }
778
779 /* Get the address from which the register is being loaded. The
780 displacement in the mov.l instruction is quadrupled. It is a
781 displacement from four bytes after the movl instruction, but,
782 before adding in the PC address, two least significant bits
783 of the PC are cleared. We assume that the section is aligned
784 on a four byte boundary. */
785 paddr = insn & 0xff;
786 paddr *= 4;
787 paddr += (laddr + 4) &~ 3;
788 if (paddr >= sec->_raw_size)
789 {
790 ((*_bfd_error_handler)
791 ("%s: 0x%lx: warning: bad R_SH_USES load offset",
792 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
793 continue;
794 }
795
796 /* Get the reloc for the address from which the register is
797 being loaded. This reloc will tell us which function is
798 actually being called. */
799 paddr += sec->vma;
800 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
801 if (irelfn->r_vaddr == paddr
802 #ifdef COFF_WITH_PE
803 && (irelfn->r_type == R_SH_IMM32
804 || irelfn->r_type == R_SH_IMM32CE
805 || irelfn->r_type == R_SH_IMAGEBASE))
806
807 #else
808 && irelfn->r_type == R_SH_IMM32)
809 #endif
810 break;
811 if (irelfn >= irelend)
812 {
813 ((*_bfd_error_handler)
814 ("%s: 0x%lx: warning: could not find expected reloc",
815 bfd_get_filename (abfd), (unsigned long) paddr));
816 continue;
817 }
818
819 /* Get the value of the symbol referred to by the reloc. */
820 if (! _bfd_coff_get_external_symbols (abfd))
821 goto error_return;
822 bfd_coff_swap_sym_in (abfd,
823 ((bfd_byte *) obj_coff_external_syms (abfd)
824 + (irelfn->r_symndx
825 * bfd_coff_symesz (abfd))),
826 &sym);
827 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
828 {
829 ((*_bfd_error_handler)
830 ("%s: 0x%lx: warning: symbol in unexpected section",
831 bfd_get_filename (abfd), (unsigned long) paddr));
832 continue;
833 }
834
835 if (sym.n_sclass != C_EXT)
836 {
837 symval = (sym.n_value
838 - sec->vma
839 + sec->output_section->vma
840 + sec->output_offset);
841 }
842 else
843 {
844 struct coff_link_hash_entry *h;
845
846 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
847 BFD_ASSERT (h != NULL);
848 if (h->root.type != bfd_link_hash_defined
849 && h->root.type != bfd_link_hash_defweak)
850 {
851 /* This appears to be a reference to an undefined
852 symbol. Just ignore it--it will be caught by the
853 regular reloc processing. */
854 continue;
855 }
856
857 symval = (h->root.u.def.value
858 + h->root.u.def.section->output_section->vma
859 + h->root.u.def.section->output_offset);
860 }
861
862 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
863
864 /* See if this function call can be shortened. */
865 foff = (symval
866 - (irel->r_vaddr
867 - sec->vma
868 + sec->output_section->vma
869 + sec->output_offset
870 + 4));
871 if (foff < -0x1000 || foff >= 0x1000)
872 {
873 /* After all that work, we can't shorten this function call. */
874 continue;
875 }
876
877 /* Shorten the function call. */
878
879 /* For simplicity of coding, we are going to modify the section
880 contents, the section relocs, and the BFD symbol table. We
881 must tell the rest of the code not to free up this
882 information. It would be possible to instead create a table
883 of changes which have to be made, as is done in coff-mips.c;
884 that would be more work, but would require less memory when
885 the linker is run. */
886
887 if (coff_section_data (abfd, sec) == NULL)
888 {
889 sec->used_by_bfd =
890 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
891 if (sec->used_by_bfd == NULL)
892 goto error_return;
893 }
894
895 coff_section_data (abfd, sec)->relocs = internal_relocs;
896 coff_section_data (abfd, sec)->keep_relocs = true;
897 free_relocs = NULL;
898
899 coff_section_data (abfd, sec)->contents = contents;
900 coff_section_data (abfd, sec)->keep_contents = true;
901 free_contents = NULL;
902
903 obj_coff_keep_syms (abfd) = true;
904
905 /* Replace the jsr with a bsr. */
906
907 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
908 replace the jsr with a bsr. */
909 irel->r_type = R_SH_PCDISP;
910 irel->r_symndx = irelfn->r_symndx;
911 if (sym.n_sclass != C_EXT)
912 {
913 /* If this needs to be changed because of future relaxing,
914 it will be handled here like other internal PCDISP
915 relocs. */
916 bfd_put_16 (abfd,
917 0xb000 | ((foff >> 1) & 0xfff),
918 contents + irel->r_vaddr - sec->vma);
919 }
920 else
921 {
922 /* We can't fully resolve this yet, because the external
923 symbol value may be changed by future relaxing. We let
924 the final link phase handle it. */
925 bfd_put_16 (abfd, 0xb000, contents + irel->r_vaddr - sec->vma);
926 }
927
928 /* See if there is another R_SH_USES reloc referring to the same
929 register load. */
930 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
931 if (irelscan->r_type == R_SH_USES
932 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
933 break;
934 if (irelscan < irelend)
935 {
936 /* Some other function call depends upon this register load,
937 and we have not yet converted that function call.
938 Indeed, we may never be able to convert it. There is
939 nothing else we can do at this point. */
940 continue;
941 }
942
943 /* Look for a R_SH_COUNT reloc on the location where the
944 function address is stored. Do this before deleting any
945 bytes, to avoid confusion about the address. */
946 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
947 if (irelcount->r_vaddr == paddr
948 && irelcount->r_type == R_SH_COUNT)
949 break;
950
951 /* Delete the register load. */
952 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
953 goto error_return;
954
955 /* That will change things, so, just in case it permits some
956 other function call to come within range, we should relax
957 again. Note that this is not required, and it may be slow. */
958 *again = true;
959
960 /* Now check whether we got a COUNT reloc. */
961 if (irelcount >= irelend)
962 {
963 ((*_bfd_error_handler)
964 ("%s: 0x%lx: warning: could not find expected COUNT reloc",
965 bfd_get_filename (abfd), (unsigned long) paddr));
966 continue;
967 }
968
969 /* The number of uses is stored in the r_offset field. We've
970 just deleted one. */
971 if (irelcount->r_offset == 0)
972 {
973 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count",
974 bfd_get_filename (abfd),
975 (unsigned long) paddr));
976 continue;
977 }
978
979 --irelcount->r_offset;
980
981 /* If there are no more uses, we can delete the address. Reload
982 the address from irelfn, in case it was changed by the
983 previous call to sh_relax_delete_bytes. */
984 if (irelcount->r_offset == 0)
985 {
986 if (! sh_relax_delete_bytes (abfd, sec,
987 irelfn->r_vaddr - sec->vma, 4))
988 goto error_return;
989 }
990
991 /* We've done all we can with that function call. */
992 }
993
994 /* Look for load and store instructions that we can align on four
995 byte boundaries. */
996 if (have_code)
997 {
998 boolean swapped;
999
1000 /* Get the section contents. */
1001 if (contents == NULL)
1002 {
1003 if (coff_section_data (abfd, sec) != NULL
1004 && coff_section_data (abfd, sec)->contents != NULL)
1005 contents = coff_section_data (abfd, sec)->contents;
1006 else
1007 {
1008 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
1009 if (contents == NULL)
1010 goto error_return;
1011 free_contents = contents;
1012
1013 if (! bfd_get_section_contents (abfd, sec, contents,
1014 (file_ptr) 0, sec->_raw_size))
1015 goto error_return;
1016 }
1017 }
1018
1019 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1020 goto error_return;
1021
1022 if (swapped)
1023 {
1024 if (coff_section_data (abfd, sec) == NULL)
1025 {
1026 sec->used_by_bfd =
1027 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
1028 if (sec->used_by_bfd == NULL)
1029 goto error_return;
1030 }
1031
1032 coff_section_data (abfd, sec)->relocs = internal_relocs;
1033 coff_section_data (abfd, sec)->keep_relocs = true;
1034 free_relocs = NULL;
1035
1036 coff_section_data (abfd, sec)->contents = contents;
1037 coff_section_data (abfd, sec)->keep_contents = true;
1038 free_contents = NULL;
1039
1040 obj_coff_keep_syms (abfd) = true;
1041 }
1042 }
1043
1044 if (free_relocs != NULL)
1045 {
1046 free (free_relocs);
1047 free_relocs = NULL;
1048 }
1049
1050 if (free_contents != NULL)
1051 {
1052 if (! link_info->keep_memory)
1053 free (free_contents);
1054 else
1055 {
1056 /* Cache the section contents for coff_link_input_bfd. */
1057 if (coff_section_data (abfd, sec) == NULL)
1058 {
1059 sec->used_by_bfd =
1060 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
1061 if (sec->used_by_bfd == NULL)
1062 goto error_return;
1063 coff_section_data (abfd, sec)->relocs = NULL;
1064 }
1065 coff_section_data (abfd, sec)->contents = contents;
1066 }
1067 }
1068
1069 return true;
1070
1071 error_return:
1072 if (free_relocs != NULL)
1073 free (free_relocs);
1074 if (free_contents != NULL)
1075 free (free_contents);
1076 return false;
1077 }
1078
1079 /* Delete some bytes from a section while relaxing. */
1080
1081 static boolean
1082 sh_relax_delete_bytes (abfd, sec, addr, count)
1083 bfd *abfd;
1084 asection *sec;
1085 bfd_vma addr;
1086 int count;
1087 {
1088 bfd_byte *contents;
1089 struct internal_reloc *irel, *irelend;
1090 struct internal_reloc *irelalign;
1091 bfd_vma toaddr;
1092 bfd_byte *esym, *esymend;
1093 bfd_size_type symesz;
1094 struct coff_link_hash_entry **sym_hash;
1095 asection *o;
1096
1097 contents = coff_section_data (abfd, sec)->contents;
1098
1099 /* The deletion must stop at the next ALIGN reloc for an aligment
1100 power larger than the number of bytes we are deleting. */
1101
1102 irelalign = NULL;
1103 toaddr = sec->_cooked_size;
1104
1105 irel = coff_section_data (abfd, sec)->relocs;
1106 irelend = irel + sec->reloc_count;
1107 for (; irel < irelend; irel++)
1108 {
1109 if (irel->r_type == R_SH_ALIGN
1110 && irel->r_vaddr - sec->vma > addr
1111 && count < (1 << irel->r_offset))
1112 {
1113 irelalign = irel;
1114 toaddr = irel->r_vaddr - sec->vma;
1115 break;
1116 }
1117 }
1118
1119 /* Actually delete the bytes. */
1120 memmove (contents + addr, contents + addr + count, toaddr - addr - count);
1121 if (irelalign == NULL)
1122 sec->_cooked_size -= count;
1123 else
1124 {
1125 int i;
1126
1127 #define NOP_OPCODE (0x0009)
1128
1129 BFD_ASSERT ((count & 1) == 0);
1130 for (i = 0; i < count; i += 2)
1131 bfd_put_16 (abfd, NOP_OPCODE, contents + toaddr - count + i);
1132 }
1133
1134 /* Adjust all the relocs. */
1135 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1136 {
1137 bfd_vma nraddr, stop;
1138 bfd_vma start = 0;
1139 int insn = 0;
1140 struct internal_syment sym;
1141 int off, adjust, oinsn;
1142 bfd_signed_vma voff = 0;
1143 boolean overflow;
1144
1145 /* Get the new reloc address. */
1146 nraddr = irel->r_vaddr - sec->vma;
1147 if ((irel->r_vaddr - sec->vma > addr
1148 && irel->r_vaddr - sec->vma < toaddr)
1149 || (irel->r_type == R_SH_ALIGN
1150 && irel->r_vaddr - sec->vma == toaddr))
1151 nraddr -= count;
1152
1153 /* See if this reloc was for the bytes we have deleted, in which
1154 case we no longer care about it. Don't delete relocs which
1155 represent addresses, though. */
1156 if (irel->r_vaddr - sec->vma >= addr
1157 && irel->r_vaddr - sec->vma < addr + count
1158 && irel->r_type != R_SH_ALIGN
1159 && irel->r_type != R_SH_CODE
1160 && irel->r_type != R_SH_DATA
1161 && irel->r_type != R_SH_LABEL)
1162 irel->r_type = R_SH_UNUSED;
1163
1164 /* If this is a PC relative reloc, see if the range it covers
1165 includes the bytes we have deleted. */
1166 switch (irel->r_type)
1167 {
1168 default:
1169 break;
1170
1171 case R_SH_PCDISP8BY2:
1172 case R_SH_PCDISP:
1173 case R_SH_PCRELIMM8BY2:
1174 case R_SH_PCRELIMM8BY4:
1175 start = irel->r_vaddr - sec->vma;
1176 insn = bfd_get_16 (abfd, contents + nraddr);
1177 break;
1178 }
1179
1180 switch (irel->r_type)
1181 {
1182 default:
1183 start = stop = addr;
1184 break;
1185
1186 case R_SH_IMM32:
1187 #ifdef COFF_WITH_PE
1188 case R_SH_IMM32CE:
1189 case R_SH_IMAGEBASE:
1190 #endif
1191 /* If this reloc is against a symbol defined in this
1192 section, and the symbol will not be adjusted below, we
1193 must check the addend to see it will put the value in
1194 range to be adjusted, and hence must be changed. */
1195 bfd_coff_swap_sym_in (abfd,
1196 ((bfd_byte *) obj_coff_external_syms (abfd)
1197 + (irel->r_symndx
1198 * bfd_coff_symesz (abfd))),
1199 &sym);
1200 if (sym.n_sclass != C_EXT
1201 && sym.n_scnum == sec->target_index
1202 && ((bfd_vma) sym.n_value <= addr
1203 || (bfd_vma) sym.n_value >= toaddr))
1204 {
1205 bfd_vma val;
1206
1207 val = bfd_get_32 (abfd, contents + nraddr);
1208 val += sym.n_value;
1209 if (val > addr && val < toaddr)
1210 bfd_put_32 (abfd, val - count, contents + nraddr);
1211 }
1212 start = stop = addr;
1213 break;
1214
1215 case R_SH_PCDISP8BY2:
1216 off = insn & 0xff;
1217 if (off & 0x80)
1218 off -= 0x100;
1219 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1220 break;
1221
1222 case R_SH_PCDISP:
1223 bfd_coff_swap_sym_in (abfd,
1224 ((bfd_byte *) obj_coff_external_syms (abfd)
1225 + (irel->r_symndx
1226 * bfd_coff_symesz (abfd))),
1227 &sym);
1228 if (sym.n_sclass == C_EXT)
1229 start = stop = addr;
1230 else
1231 {
1232 off = insn & 0xfff;
1233 if (off & 0x800)
1234 off -= 0x1000;
1235 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1236 }
1237 break;
1238
1239 case R_SH_PCRELIMM8BY2:
1240 off = insn & 0xff;
1241 stop = start + 4 + off * 2;
1242 break;
1243
1244 case R_SH_PCRELIMM8BY4:
1245 off = insn & 0xff;
1246 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1247 break;
1248
1249 case R_SH_SWITCH8:
1250 case R_SH_SWITCH16:
1251 case R_SH_SWITCH32:
1252 /* These relocs types represent
1253 .word L2-L1
1254 The r_offset field holds the difference between the reloc
1255 address and L1. That is the start of the reloc, and
1256 adding in the contents gives us the top. We must adjust
1257 both the r_offset field and the section contents. */
1258
1259 start = irel->r_vaddr - sec->vma;
1260 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1261
1262 if (start > addr
1263 && start < toaddr
1264 && (stop <= addr || stop >= toaddr))
1265 irel->r_offset += count;
1266 else if (stop > addr
1267 && stop < toaddr
1268 && (start <= addr || start >= toaddr))
1269 irel->r_offset -= count;
1270
1271 start = stop;
1272
1273 if (irel->r_type == R_SH_SWITCH16)
1274 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1275 else if (irel->r_type == R_SH_SWITCH8)
1276 voff = bfd_get_8 (abfd, contents + nraddr);
1277 else
1278 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1279 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1280
1281 break;
1282
1283 case R_SH_USES:
1284 start = irel->r_vaddr - sec->vma;
1285 stop = (bfd_vma) ((bfd_signed_vma) start
1286 + (long) irel->r_offset
1287 + 4);
1288 break;
1289 }
1290
1291 if (start > addr
1292 && start < toaddr
1293 && (stop <= addr || stop >= toaddr))
1294 adjust = count;
1295 else if (stop > addr
1296 && stop < toaddr
1297 && (start <= addr || start >= toaddr))
1298 adjust = - count;
1299 else
1300 adjust = 0;
1301
1302 if (adjust != 0)
1303 {
1304 oinsn = insn;
1305 overflow = false;
1306 switch (irel->r_type)
1307 {
1308 default:
1309 abort ();
1310 break;
1311
1312 case R_SH_PCDISP8BY2:
1313 case R_SH_PCRELIMM8BY2:
1314 insn += adjust / 2;
1315 if ((oinsn & 0xff00) != (insn & 0xff00))
1316 overflow = true;
1317 bfd_put_16 (abfd, insn, contents + nraddr);
1318 break;
1319
1320 case R_SH_PCDISP:
1321 insn += adjust / 2;
1322 if ((oinsn & 0xf000) != (insn & 0xf000))
1323 overflow = true;
1324 bfd_put_16 (abfd, insn, contents + nraddr);
1325 break;
1326
1327 case R_SH_PCRELIMM8BY4:
1328 BFD_ASSERT (adjust == count || count >= 4);
1329 if (count >= 4)
1330 insn += adjust / 4;
1331 else
1332 {
1333 if ((irel->r_vaddr & 3) == 0)
1334 ++insn;
1335 }
1336 if ((oinsn & 0xff00) != (insn & 0xff00))
1337 overflow = true;
1338 bfd_put_16 (abfd, insn, contents + nraddr);
1339 break;
1340
1341 case R_SH_SWITCH8:
1342 voff += adjust;
1343 if (voff < 0 || voff >= 0xff)
1344 overflow = true;
1345 bfd_put_8 (abfd, voff, contents + nraddr);
1346 break;
1347
1348 case R_SH_SWITCH16:
1349 voff += adjust;
1350 if (voff < - 0x8000 || voff >= 0x8000)
1351 overflow = true;
1352 bfd_put_signed_16 (abfd, voff, contents + nraddr);
1353 break;
1354
1355 case R_SH_SWITCH32:
1356 voff += adjust;
1357 bfd_put_signed_32 (abfd, voff, contents + nraddr);
1358 break;
1359
1360 case R_SH_USES:
1361 irel->r_offset += adjust;
1362 break;
1363 }
1364
1365 if (overflow)
1366 {
1367 ((*_bfd_error_handler)
1368 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
1369 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
1370 bfd_set_error (bfd_error_bad_value);
1371 return false;
1372 }
1373 }
1374
1375 irel->r_vaddr = nraddr + sec->vma;
1376 }
1377
1378 /* Look through all the other sections. If there contain any IMM32
1379 relocs against internal symbols which we are not going to adjust
1380 below, we may need to adjust the addends. */
1381 for (o = abfd->sections; o != NULL; o = o->next)
1382 {
1383 struct internal_reloc *internal_relocs;
1384 struct internal_reloc *irelscan, *irelscanend;
1385 bfd_byte *ocontents;
1386
1387 if (o == sec
1388 || (o->flags & SEC_RELOC) == 0
1389 || o->reloc_count == 0)
1390 continue;
1391
1392 /* We always cache the relocs. Perhaps, if info->keep_memory is
1393 false, we should free them, if we are permitted to, when we
1394 leave sh_coff_relax_section. */
1395 internal_relocs = (_bfd_coff_read_internal_relocs
1396 (abfd, o, true, (bfd_byte *) NULL, false,
1397 (struct internal_reloc *) NULL));
1398 if (internal_relocs == NULL)
1399 return false;
1400
1401 ocontents = NULL;
1402 irelscanend = internal_relocs + o->reloc_count;
1403 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1404 {
1405 struct internal_syment sym;
1406
1407 #ifdef COFF_WITH_PE
1408 if (irelscan->r_type != R_SH_IMM32
1409 && irelscan->r_type != R_SH_IMAGEBASE
1410 && irelscan->r_type != R_SH_IMM32CE)
1411 #else
1412 if (irelscan->r_type != R_SH_IMM32)
1413 #endif
1414 continue;
1415
1416 bfd_coff_swap_sym_in (abfd,
1417 ((bfd_byte *) obj_coff_external_syms (abfd)
1418 + (irelscan->r_symndx
1419 * bfd_coff_symesz (abfd))),
1420 &sym);
1421 if (sym.n_sclass != C_EXT
1422 && sym.n_scnum == sec->target_index
1423 && ((bfd_vma) sym.n_value <= addr
1424 || (bfd_vma) sym.n_value >= toaddr))
1425 {
1426 bfd_vma val;
1427
1428 if (ocontents == NULL)
1429 {
1430 if (coff_section_data (abfd, o)->contents != NULL)
1431 ocontents = coff_section_data (abfd, o)->contents;
1432 else
1433 {
1434 /* We always cache the section contents.
1435 Perhaps, if info->keep_memory is false, we
1436 should free them, if we are permitted to,
1437 when we leave sh_coff_relax_section. */
1438 ocontents = (bfd_byte *) bfd_malloc (o->_raw_size);
1439 if (ocontents == NULL)
1440 return false;
1441 if (! bfd_get_section_contents (abfd, o, ocontents,
1442 (file_ptr) 0,
1443 o->_raw_size))
1444 return false;
1445 coff_section_data (abfd, o)->contents = ocontents;
1446 }
1447 }
1448
1449 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1450 val += sym.n_value;
1451 if (val > addr && val < toaddr)
1452 bfd_put_32 (abfd, val - count,
1453 ocontents + irelscan->r_vaddr - o->vma);
1454
1455 coff_section_data (abfd, o)->keep_contents = true;
1456 }
1457 }
1458 }
1459
1460 /* Adjusting the internal symbols will not work if something has
1461 already retrieved the generic symbols. It would be possible to
1462 make this work by adjusting the generic symbols at the same time.
1463 However, this case should not arise in normal usage. */
1464 if (obj_symbols (abfd) != NULL
1465 || obj_raw_syments (abfd) != NULL)
1466 {
1467 ((*_bfd_error_handler)
1468 ("%s: fatal: generic symbols retrieved before relaxing",
1469 bfd_get_filename (abfd)));
1470 bfd_set_error (bfd_error_invalid_operation);
1471 return false;
1472 }
1473
1474 /* Adjust all the symbols. */
1475 sym_hash = obj_coff_sym_hashes (abfd);
1476 symesz = bfd_coff_symesz (abfd);
1477 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1478 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1479 while (esym < esymend)
1480 {
1481 struct internal_syment isym;
1482
1483 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1484
1485 if (isym.n_scnum == sec->target_index
1486 && (bfd_vma) isym.n_value > addr
1487 && (bfd_vma) isym.n_value < toaddr)
1488 {
1489 isym.n_value -= count;
1490
1491 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1492
1493 if (*sym_hash != NULL)
1494 {
1495 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1496 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1497 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1498 && (*sym_hash)->root.u.def.value < toaddr);
1499 (*sym_hash)->root.u.def.value -= count;
1500 }
1501 }
1502
1503 esym += (isym.n_numaux + 1) * symesz;
1504 sym_hash += isym.n_numaux + 1;
1505 }
1506
1507 /* See if we can move the ALIGN reloc forward. We have adjusted
1508 r_vaddr for it already. */
1509 if (irelalign != NULL)
1510 {
1511 bfd_vma alignto, alignaddr;
1512
1513 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1514 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1515 1 << irelalign->r_offset);
1516 if (alignto != alignaddr)
1517 {
1518 /* Tail recursion. */
1519 return sh_relax_delete_bytes (abfd, sec, alignaddr,
1520 alignto - alignaddr);
1521 }
1522 }
1523
1524 return true;
1525 }
1526 \f
1527 /* This is yet another version of the SH opcode table, used to rapidly
1528 get information about a particular instruction. */
1529
1530 /* The opcode map is represented by an array of these structures. The
1531 array is indexed by the high order four bits in the instruction. */
1532
1533 struct sh_major_opcode
1534 {
1535 /* A pointer to the instruction list. This is an array which
1536 contains all the instructions with this major opcode. */
1537 const struct sh_minor_opcode *minor_opcodes;
1538 /* The number of elements in minor_opcodes. */
1539 unsigned short count;
1540 };
1541
1542 /* This structure holds information for a set of SH opcodes. The
1543 instruction code is anded with the mask value, and the resulting
1544 value is used to search the order opcode list. */
1545
1546 struct sh_minor_opcode
1547 {
1548 /* The sorted opcode list. */
1549 const struct sh_opcode *opcodes;
1550 /* The number of elements in opcodes. */
1551 unsigned short count;
1552 /* The mask value to use when searching the opcode list. */
1553 unsigned short mask;
1554 };
1555
1556 /* This structure holds information for an SH instruction. An array
1557 of these structures is sorted in order by opcode. */
1558
1559 struct sh_opcode
1560 {
1561 /* The code for this instruction, after it has been anded with the
1562 mask value in the sh_major_opcode structure. */
1563 unsigned short opcode;
1564 /* Flags for this instruction. */
1565 unsigned long flags;
1566 };
1567
1568 /* Flag which appear in the sh_opcode structure. */
1569
1570 /* This instruction loads a value from memory. */
1571 #define LOAD (0x1)
1572
1573 /* This instruction stores a value to memory. */
1574 #define STORE (0x2)
1575
1576 /* This instruction is a branch. */
1577 #define BRANCH (0x4)
1578
1579 /* This instruction has a delay slot. */
1580 #define DELAY (0x8)
1581
1582 /* This instruction uses the value in the register in the field at
1583 mask 0x0f00 of the instruction. */
1584 #define USES1 (0x10)
1585 #define USES1_REG(x) ((x & 0x0f00) >> 8)
1586
1587 /* This instruction uses the value in the register in the field at
1588 mask 0x00f0 of the instruction. */
1589 #define USES2 (0x20)
1590 #define USES2_REG(x) ((x & 0x00f0) >> 4)
1591
1592 /* This instruction uses the value in register 0. */
1593 #define USESR0 (0x40)
1594
1595 /* This instruction sets the value in the register in the field at
1596 mask 0x0f00 of the instruction. */
1597 #define SETS1 (0x80)
1598 #define SETS1_REG(x) ((x & 0x0f00) >> 8)
1599
1600 /* This instruction sets the value in the register in the field at
1601 mask 0x00f0 of the instruction. */
1602 #define SETS2 (0x100)
1603 #define SETS2_REG(x) ((x & 0x00f0) >> 4)
1604
1605 /* This instruction sets register 0. */
1606 #define SETSR0 (0x200)
1607
1608 /* This instruction sets a special register. */
1609 #define SETSSP (0x400)
1610
1611 /* This instruction uses a special register. */
1612 #define USESSP (0x800)
1613
1614 /* This instruction uses the floating point register in the field at
1615 mask 0x0f00 of the instruction. */
1616 #define USESF1 (0x1000)
1617 #define USESF1_REG(x) ((x & 0x0f00) >> 8)
1618
1619 /* This instruction uses the floating point register in the field at
1620 mask 0x00f0 of the instruction. */
1621 #define USESF2 (0x2000)
1622 #define USESF2_REG(x) ((x & 0x00f0) >> 4)
1623
1624 /* This instruction uses floating point register 0. */
1625 #define USESF0 (0x4000)
1626
1627 /* This instruction sets the floating point register in the field at
1628 mask 0x0f00 of the instruction. */
1629 #define SETSF1 (0x8000)
1630 #define SETSF1_REG(x) ((x & 0x0f00) >> 8)
1631
1632 #define USESAS (0x10000)
1633 #define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1634 #define USESR8 (0x20000)
1635 #define SETSAS (0x40000)
1636 #define SETSAS_REG(x) USESAS_REG (x)
1637
1638 #ifndef COFF_IMAGE_WITH_PE
1639 static boolean sh_insn_uses_reg
1640 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1641 static boolean sh_insn_sets_reg
1642 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1643 static boolean sh_insn_uses_or_sets_reg
1644 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1645 static boolean sh_insn_uses_freg
1646 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1647 static boolean sh_insn_sets_freg
1648 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1649 static boolean sh_insn_uses_or_sets_freg
1650 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1651 static boolean sh_insns_conflict
1652 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1653 const struct sh_opcode *));
1654 static boolean sh_load_use
1655 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1656 const struct sh_opcode *));
1657 #endif
1658 /* The opcode maps. */
1659
1660 #define MAP(a) a, sizeof a / sizeof a[0]
1661
1662 static const struct sh_opcode sh_opcode00[] =
1663 {
1664 { 0x0008, SETSSP }, /* clrt */
1665 { 0x0009, 0 }, /* nop */
1666 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1667 { 0x0018, SETSSP }, /* sett */
1668 { 0x0019, SETSSP }, /* div0u */
1669 { 0x001b, 0 }, /* sleep */
1670 { 0x0028, SETSSP }, /* clrmac */
1671 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1672 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1673 { 0x0048, SETSSP }, /* clrs */
1674 { 0x0058, SETSSP } /* sets */
1675 };
1676
1677 static const struct sh_opcode sh_opcode01[] =
1678 {
1679 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1680 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
1681 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
1682 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1683 { 0x0029, SETS1 | USESSP }, /* movt rn */
1684 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
1685 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1686 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1687 { 0x0083, LOAD | USES1 }, /* pref @rn */
1688 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1689 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1690 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1691 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1692 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1693 };
1694
1695 /* These sixteen instructions can be handled with one table entry below. */
1696 #if 0
1697 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */
1698 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */
1699 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */
1700 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */
1701 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */
1702 { 0x0052, SETS1 | USESSP }, /* stc mod,rn */
1703 { 0x0062, SETS1 | USESSP }, /* stc rs,rn */
1704 { 0x0072, SETS1 | USESSP }, /* stc re,rn */
1705 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */
1706 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */
1707 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */
1708 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */
1709 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */
1710 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */
1711 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */
1712 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */
1713 #endif
1714
1715 static const struct sh_opcode sh_opcode02[] =
1716 {
1717 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
1718 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1719 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1720 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1721 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1722 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1723 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1724 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1725 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1726 };
1727
1728 static const struct sh_minor_opcode sh_opcode0[] =
1729 {
1730 { MAP (sh_opcode00), 0xffff },
1731 { MAP (sh_opcode01), 0xf0ff },
1732 { MAP (sh_opcode02), 0xf00f }
1733 };
1734
1735 static const struct sh_opcode sh_opcode10[] =
1736 {
1737 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1738 };
1739
1740 static const struct sh_minor_opcode sh_opcode1[] =
1741 {
1742 { MAP (sh_opcode10), 0xf000 }
1743 };
1744
1745 static const struct sh_opcode sh_opcode20[] =
1746 {
1747 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1748 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1749 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1750 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1751 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1752 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1753 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1754 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1755 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1756 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1757 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1758 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1759 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1760 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1761 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1762 };
1763
1764 static const struct sh_minor_opcode sh_opcode2[] =
1765 {
1766 { MAP (sh_opcode20), 0xf00f }
1767 };
1768
1769 static const struct sh_opcode sh_opcode30[] =
1770 {
1771 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1772 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1773 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1774 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1775 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1776 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1777 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1778 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1779 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1780 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1781 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1782 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1783 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1784 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1785 };
1786
1787 static const struct sh_minor_opcode sh_opcode3[] =
1788 {
1789 { MAP (sh_opcode30), 0xf00f }
1790 };
1791
1792 static const struct sh_opcode sh_opcode40[] =
1793 {
1794 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1795 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1796 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
1797 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1798 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1799 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
1800 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1801 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1802 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1803 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
1804 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1805 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1806 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
1807 { 0x4014, SETSSP | USES1 }, /* setrc rm */
1808 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1809 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
1810 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1811 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1812 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1813 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
1814 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1815 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1816 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
1817 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1818 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1819 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
1820 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1821 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1822 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1823 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
1824 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1825 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1826 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1827 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1828 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1829 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1830 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1831 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1832 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1833 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1834 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1835 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1836 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1837 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1838 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1839 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1840 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1841 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1842 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1843 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1844 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
1845 #if 0 /* These groups sixteen insns can be
1846 handled with one table entry each below. */
1847 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */
1848 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */
1849 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */
1850 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */
1851 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */
1852 { 0x4053, STORE | SETS1 | USES1 | USESSP }, /* stc.l mod,@-rn */
1853 { 0x4063, STORE | SETS1 | USES1 | USESSP }, /* stc.l rs,@-rn */
1854 { 0x4073, STORE | SETS1 | USES1 | USESSP }, /* stc.l re,@-rn */
1855 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l r0_bank,@-rn */
1856 ..
1857 { 0x40f3, STORE | SETS1 | USES1 | USESSP }, /* stc.l r7_bank,@-rn */
1858
1859 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */
1860 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */
1861 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */
1862 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */
1863 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */
1864 { 0x4057, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,mod */
1865 { 0x4067, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rs */
1866 { 0x4077, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,re */
1867 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r0_bank */
1868 ..
1869 { 0x40f7, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r7_bank */
1870
1871 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */
1872 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */
1873 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */
1874 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */
1875 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */
1876 { 0x405e, SETSSP | USES1 }, /* ldc rm,mod */
1877 { 0x406e, SETSSP | USES1 }, /* ldc rm,rs */
1878 { 0x407e, SETSSP | USES1 } /* ldc rm,re */
1879 { 0x408e, SETSSP | USES1 } /* ldc rm,r0_bank */
1880 ..
1881 { 0x40fe, SETSSP | USES1 } /* ldc rm,r7_bank */
1882 #endif
1883 };
1884
1885 static const struct sh_opcode sh_opcode41[] =
1886 {
1887 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1888 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1889 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1890 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1891 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
1892 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1893 };
1894
1895 static const struct sh_minor_opcode sh_opcode4[] =
1896 {
1897 { MAP (sh_opcode40), 0xf0ff },
1898 { MAP (sh_opcode41), 0xf00f }
1899 };
1900
1901 static const struct sh_opcode sh_opcode50[] =
1902 {
1903 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1904 };
1905
1906 static const struct sh_minor_opcode sh_opcode5[] =
1907 {
1908 { MAP (sh_opcode50), 0xf000 }
1909 };
1910
1911 static const struct sh_opcode sh_opcode60[] =
1912 {
1913 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1914 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1915 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1916 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1917 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1918 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1919 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1920 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1921 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1922 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1923 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1924 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1925 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1926 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1927 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1928 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1929 };
1930
1931 static const struct sh_minor_opcode sh_opcode6[] =
1932 {
1933 { MAP (sh_opcode60), 0xf00f }
1934 };
1935
1936 static const struct sh_opcode sh_opcode70[] =
1937 {
1938 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1939 };
1940
1941 static const struct sh_minor_opcode sh_opcode7[] =
1942 {
1943 { MAP (sh_opcode70), 0xf000 }
1944 };
1945
1946 static const struct sh_opcode sh_opcode80[] =
1947 {
1948 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1949 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
1950 { 0x8200, SETSSP }, /* setrc #imm */
1951 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1952 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1953 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1954 { 0x8900, BRANCH | USESSP }, /* bt label */
1955 { 0x8b00, BRANCH | USESSP }, /* bf label */
1956 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
1957 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
1958 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
1959 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1960 };
1961
1962 static const struct sh_minor_opcode sh_opcode8[] =
1963 {
1964 { MAP (sh_opcode80), 0xff00 }
1965 };
1966
1967 static const struct sh_opcode sh_opcode90[] =
1968 {
1969 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1970 };
1971
1972 static const struct sh_minor_opcode sh_opcode9[] =
1973 {
1974 { MAP (sh_opcode90), 0xf000 }
1975 };
1976
1977 static const struct sh_opcode sh_opcodea0[] =
1978 {
1979 { 0xa000, BRANCH | DELAY } /* bra label */
1980 };
1981
1982 static const struct sh_minor_opcode sh_opcodea[] =
1983 {
1984 { MAP (sh_opcodea0), 0xf000 }
1985 };
1986
1987 static const struct sh_opcode sh_opcodeb0[] =
1988 {
1989 { 0xb000, BRANCH | DELAY } /* bsr label */
1990 };
1991
1992 static const struct sh_minor_opcode sh_opcodeb[] =
1993 {
1994 { MAP (sh_opcodeb0), 0xf000 }
1995 };
1996
1997 static const struct sh_opcode sh_opcodec0[] =
1998 {
1999 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
2000 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
2001 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
2002 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
2003 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
2004 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
2005 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
2006 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
2007 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
2008 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
2009 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
2010 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
2011 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
2012 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
2013 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
2014 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
2015 };
2016
2017 static const struct sh_minor_opcode sh_opcodec[] =
2018 {
2019 { MAP (sh_opcodec0), 0xff00 }
2020 };
2021
2022 static const struct sh_opcode sh_opcoded0[] =
2023 {
2024 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
2025 };
2026
2027 static const struct sh_minor_opcode sh_opcoded[] =
2028 {
2029 { MAP (sh_opcoded0), 0xf000 }
2030 };
2031
2032 static const struct sh_opcode sh_opcodee0[] =
2033 {
2034 { 0xe000, SETS1 } /* mov #imm,rn */
2035 };
2036
2037 static const struct sh_minor_opcode sh_opcodee[] =
2038 {
2039 { MAP (sh_opcodee0), 0xf000 }
2040 };
2041
2042 static const struct sh_opcode sh_opcodef0[] =
2043 {
2044 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
2045 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
2046 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
2047 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
2048 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
2049 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
2050 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
2051 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
2052 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
2053 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
2054 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
2055 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
2056 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
2057 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
2058 };
2059
2060 static const struct sh_opcode sh_opcodef1[] =
2061 {
2062 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
2063 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
2064 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
2065 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
2066 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
2067 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
2068 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
2069 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
2070 { 0xf08d, SETSF1 }, /* fldi0 fn */
2071 { 0xf09d, SETSF1 } /* fldi1 fn */
2072 };
2073
2074 static const struct sh_minor_opcode sh_opcodef[] =
2075 {
2076 { MAP (sh_opcodef0), 0xf00f },
2077 { MAP (sh_opcodef1), 0xf0ff }
2078 };
2079
2080 #ifndef COFF_IMAGE_WITH_PE
2081 static struct sh_major_opcode sh_opcodes[] =
2082 {
2083 { MAP (sh_opcode0) },
2084 { MAP (sh_opcode1) },
2085 { MAP (sh_opcode2) },
2086 { MAP (sh_opcode3) },
2087 { MAP (sh_opcode4) },
2088 { MAP (sh_opcode5) },
2089 { MAP (sh_opcode6) },
2090 { MAP (sh_opcode7) },
2091 { MAP (sh_opcode8) },
2092 { MAP (sh_opcode9) },
2093 { MAP (sh_opcodea) },
2094 { MAP (sh_opcodeb) },
2095 { MAP (sh_opcodec) },
2096 { MAP (sh_opcoded) },
2097 { MAP (sh_opcodee) },
2098 { MAP (sh_opcodef) }
2099 };
2100 #endif
2101
2102 /* The double data transfer / parallel processing insns are not
2103 described here. This will cause sh_align_load_span to leave them alone. */
2104
2105 static const struct sh_opcode sh_dsp_opcodef0[] =
2106 {
2107 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2108 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2109 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2110 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2111 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2112 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2113 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2114 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2115 };
2116
2117 static const struct sh_minor_opcode sh_dsp_opcodef[] =
2118 {
2119 { MAP (sh_dsp_opcodef0), 0xfc0d }
2120 };
2121
2122 #ifndef COFF_IMAGE_WITH_PE
2123 /* Given an instruction, return a pointer to the corresponding
2124 sh_opcode structure. Return NULL if the instruction is not
2125 recognized. */
2126
2127 static const struct sh_opcode *
2128 sh_insn_info (insn)
2129 unsigned int insn;
2130 {
2131 const struct sh_major_opcode *maj;
2132 const struct sh_minor_opcode *min, *minend;
2133
2134 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2135 min = maj->minor_opcodes;
2136 minend = min + maj->count;
2137 for (; min < minend; min++)
2138 {
2139 unsigned int l;
2140 const struct sh_opcode *op, *opend;
2141
2142 l = insn & min->mask;
2143 op = min->opcodes;
2144 opend = op + min->count;
2145
2146 /* Since the opcodes tables are sorted, we could use a binary
2147 search here if the count were above some cutoff value. */
2148 for (; op < opend; op++)
2149 if (op->opcode == l)
2150 return op;
2151 }
2152
2153 return NULL;
2154 }
2155
2156 /* See whether an instruction uses or sets a general purpose register */
2157
2158 static boolean
2159 sh_insn_uses_or_sets_reg (insn, op, reg)
2160 unsigned int insn;
2161 const struct sh_opcode *op;
2162 unsigned int reg;
2163 {
2164 if (sh_insn_uses_reg (insn, op, reg))
2165 return true;
2166
2167 return sh_insn_sets_reg (insn, op, reg);
2168 }
2169
2170 /* See whether an instruction uses a general purpose register. */
2171
2172 static boolean
2173 sh_insn_uses_reg (insn, op, reg)
2174 unsigned int insn;
2175 const struct sh_opcode *op;
2176 unsigned int reg;
2177 {
2178 unsigned int f;
2179
2180 f = op->flags;
2181
2182 if ((f & USES1) != 0
2183 && USES1_REG (insn) == reg)
2184 return true;
2185 if ((f & USES2) != 0
2186 && USES2_REG (insn) == reg)
2187 return true;
2188 if ((f & USESR0) != 0
2189 && reg == 0)
2190 return true;
2191 if ((f & USESAS) && reg == USESAS_REG (insn))
2192 return true;
2193 if ((f & USESR8) && reg == 8)
2194 return true;
2195
2196 return false;
2197 }
2198
2199 /* See whether an instruction sets a general purpose register. */
2200
2201 static boolean
2202 sh_insn_sets_reg (insn, op, reg)
2203 unsigned int insn;
2204 const struct sh_opcode *op;
2205 unsigned int reg;
2206 {
2207 unsigned int f;
2208
2209 f = op->flags;
2210
2211 if ((f & SETS1) != 0
2212 && SETS1_REG (insn) == reg)
2213 return true;
2214 if ((f & SETS2) != 0
2215 && SETS2_REG (insn) == reg)
2216 return true;
2217 if ((f & SETSR0) != 0
2218 && reg == 0)
2219 return true;
2220 if ((f & SETSAS) && reg == SETSAS_REG (insn))
2221 return true;
2222
2223 return false;
2224 }
2225
2226 /* See whether an instruction uses or sets a floating point register */
2227
2228 static boolean
2229 sh_insn_uses_or_sets_freg (insn, op, reg)
2230 unsigned int insn;
2231 const struct sh_opcode *op;
2232 unsigned int reg;
2233 {
2234 if (sh_insn_uses_freg (insn, op, reg))
2235 return true;
2236
2237 return sh_insn_sets_freg (insn, op, reg);
2238 }
2239
2240 /* See whether an instruction uses a floating point register. */
2241
2242 static boolean
2243 sh_insn_uses_freg (insn, op, freg)
2244 unsigned int insn;
2245 const struct sh_opcode *op;
2246 unsigned int freg;
2247 {
2248 unsigned int f;
2249
2250 f = op->flags;
2251
2252 /* We can't tell if this is a double-precision insn, so just play safe
2253 and assume that it might be. So not only have we test FREG against
2254 itself, but also even FREG against FREG+1 - if the using insn uses
2255 just the low part of a double precision value - but also an odd
2256 FREG against FREG-1 - if the setting insn sets just the low part
2257 of a double precision value.
2258 So what this all boils down to is that we have to ignore the lowest
2259 bit of the register number. */
2260
2261 if ((f & USESF1) != 0
2262 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
2263 return true;
2264 if ((f & USESF2) != 0
2265 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
2266 return true;
2267 if ((f & USESF0) != 0
2268 && freg == 0)
2269 return true;
2270
2271 return false;
2272 }
2273
2274 /* See whether an instruction sets a floating point register. */
2275
2276 static boolean
2277 sh_insn_sets_freg (insn, op, freg)
2278 unsigned int insn;
2279 const struct sh_opcode *op;
2280 unsigned int freg;
2281 {
2282 unsigned int f;
2283
2284 f = op->flags;
2285
2286 /* We can't tell if this is a double-precision insn, so just play safe
2287 and assume that it might be. So not only have we test FREG against
2288 itself, but also even FREG against FREG+1 - if the using insn uses
2289 just the low part of a double precision value - but also an odd
2290 FREG against FREG-1 - if the setting insn sets just the low part
2291 of a double precision value.
2292 So what this all boils down to is that we have to ignore the lowest
2293 bit of the register number. */
2294
2295 if ((f & SETSF1) != 0
2296 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
2297 return true;
2298
2299 return false;
2300 }
2301
2302 /* See whether instructions I1 and I2 conflict, assuming I1 comes
2303 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
2304 This should return true if there is a conflict, or false if the
2305 instructions can be swapped safely. */
2306
2307 static boolean
2308 sh_insns_conflict (i1, op1, i2, op2)
2309 unsigned int i1;
2310 const struct sh_opcode *op1;
2311 unsigned int i2;
2312 const struct sh_opcode *op2;
2313 {
2314 unsigned int f1, f2;
2315
2316 f1 = op1->flags;
2317 f2 = op2->flags;
2318
2319 /* Load of fpscr conflicts with floating point operations.
2320 FIXME: shouldn't test raw opcodes here. */
2321 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2322 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
2323 return true;
2324
2325 if ((f1 & (BRANCH | DELAY)) != 0
2326 || (f2 & (BRANCH | DELAY)) != 0)
2327 return true;
2328
2329 if (((f1 | f2) & SETSSP)
2330 && (f1 & (SETSSP | USESSP))
2331 && (f2 & (SETSSP | USESSP)))
2332 return true;
2333
2334 if ((f1 & SETS1) != 0
2335 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
2336 return true;
2337 if ((f1 & SETS2) != 0
2338 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
2339 return true;
2340 if ((f1 & SETSR0) != 0
2341 && sh_insn_uses_or_sets_reg (i2, op2, 0))
2342 return true;
2343 if ((f1 & SETSAS)
2344 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
2345 return true;
2346 if ((f1 & SETSF1) != 0
2347 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
2348 return true;
2349
2350 if ((f2 & SETS1) != 0
2351 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
2352 return true;
2353 if ((f2 & SETS2) != 0
2354 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
2355 return true;
2356 if ((f2 & SETSR0) != 0
2357 && sh_insn_uses_or_sets_reg (i1, op1, 0))
2358 return true;
2359 if ((f2 & SETSAS)
2360 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
2361 return true;
2362 if ((f2 & SETSF1) != 0
2363 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
2364 return true;
2365
2366 /* The instructions do not conflict. */
2367 return false;
2368 }
2369
2370 /* I1 is a load instruction, and I2 is some other instruction. Return
2371 true if I1 loads a register which I2 uses. */
2372
2373 static boolean
2374 sh_load_use (i1, op1, i2, op2)
2375 unsigned int i1;
2376 const struct sh_opcode *op1;
2377 unsigned int i2;
2378 const struct sh_opcode *op2;
2379 {
2380 unsigned int f1;
2381
2382 f1 = op1->flags;
2383
2384 if ((f1 & LOAD) == 0)
2385 return false;
2386
2387 /* If both SETS1 and SETSSP are set, that means a load to a special
2388 register using postincrement addressing mode, which we don't care
2389 about here. */
2390 if ((f1 & SETS1) != 0
2391 && (f1 & SETSSP) == 0
2392 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
2393 return true;
2394
2395 if ((f1 & SETSR0) != 0
2396 && sh_insn_uses_reg (i2, op2, 0))
2397 return true;
2398
2399 if ((f1 & SETSF1) != 0
2400 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
2401 return true;
2402
2403 return false;
2404 }
2405
2406 /* Try to align loads and stores within a span of memory. This is
2407 called by both the ELF and the COFF sh targets. ABFD and SEC are
2408 the BFD and section we are examining. CONTENTS is the contents of
2409 the section. SWAP is the routine to call to swap two instructions.
2410 RELOCS is a pointer to the internal relocation information, to be
2411 passed to SWAP. PLABEL is a pointer to the current label in a
2412 sorted list of labels; LABEL_END is the end of the list. START and
2413 STOP are the range of memory to examine. If a swap is made,
2414 *PSWAPPED is set to true. */
2415
2416 #ifdef COFF_WITH_PE
2417 static
2418 #endif
2419 boolean
2420 _bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2421 plabel, label_end, start, stop, pswapped)
2422 bfd *abfd;
2423 asection *sec;
2424 bfd_byte *contents;
2425 boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
2426 PTR relocs;
2427 bfd_vma **plabel;
2428 bfd_vma *label_end;
2429 bfd_vma start;
2430 bfd_vma stop;
2431 boolean *pswapped;
2432 {
2433 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2434 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
2435 bfd_vma i;
2436
2437 /* The SH4 has a Harvard architecture, hence aligning loads is not
2438 desirable. In fact, it is counter-productive, since it interferes
2439 with the schedules generated by the compiler. */
2440 if (abfd->arch_info->mach == bfd_mach_sh4)
2441 return true;
2442
2443 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2444 instructions. */
2445 if (dsp)
2446 {
2447 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2448 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
2449 }
2450
2451 /* Instructions should be aligned on 2 byte boundaries. */
2452 if ((start & 1) == 1)
2453 ++start;
2454
2455 /* Now look through the unaligned addresses. */
2456 i = start;
2457 if ((i & 2) == 0)
2458 i += 2;
2459 for (; i < stop; i += 4)
2460 {
2461 unsigned int insn;
2462 const struct sh_opcode *op;
2463 unsigned int prev_insn = 0;
2464 const struct sh_opcode *prev_op = NULL;
2465
2466 insn = bfd_get_16 (abfd, contents + i);
2467 op = sh_insn_info (insn);
2468 if (op == NULL
2469 || (op->flags & (LOAD | STORE)) == 0)
2470 continue;
2471
2472 /* This is a load or store which is not on a four byte boundary. */
2473
2474 while (*plabel < label_end && **plabel < i)
2475 ++*plabel;
2476
2477 if (i > start)
2478 {
2479 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2480 /* If INSN is the field b of a parallel processing insn, it is not
2481 a load / store after all. Note that the test here might mistake
2482 the field_b of a pcopy insn for the starting code of a parallel
2483 processing insn; this might miss a swapping opportunity, but at
2484 least we're on the safe side. */
2485 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2486 continue;
2487
2488 /* Check if prev_insn is actually the field b of a parallel
2489 processing insn. Again, this can give a spurious match
2490 after a pcopy. */
2491 if (dsp && i - 2 > start)
2492 {
2493 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
2494
2495 if ((pprev_insn & 0xfc00) == 0xf800)
2496 prev_op = NULL;
2497 else
2498 prev_op = sh_insn_info (prev_insn);
2499 }
2500 else
2501 prev_op = sh_insn_info (prev_insn);
2502
2503 /* If the load/store instruction is in a delay slot, we
2504 can't swap. */
2505 if (prev_op == NULL
2506 || (prev_op->flags & DELAY) != 0)
2507 continue;
2508 }
2509 if (i > start
2510 && (*plabel >= label_end || **plabel != i)
2511 && prev_op != NULL
2512 && (prev_op->flags & (LOAD | STORE)) == 0
2513 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2514 {
2515 boolean ok;
2516
2517 /* The load/store instruction does not have a label, and
2518 there is a previous instruction; PREV_INSN is not
2519 itself a load/store instruction, and PREV_INSN and
2520 INSN do not conflict. */
2521
2522 ok = true;
2523
2524 if (i >= start + 4)
2525 {
2526 unsigned int prev2_insn;
2527 const struct sh_opcode *prev2_op;
2528
2529 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2530 prev2_op = sh_insn_info (prev2_insn);
2531
2532 /* If the instruction before PREV_INSN has a delay
2533 slot--that is, PREV_INSN is in a delay slot--we
2534 can not swap. */
2535 if (prev2_op == NULL
2536 || (prev2_op->flags & DELAY) != 0)
2537 ok = false;
2538
2539 /* If the instruction before PREV_INSN is a load,
2540 and it sets a register which INSN uses, then
2541 putting INSN immediately after PREV_INSN will
2542 cause a pipeline bubble, so there is no point to
2543 making the swap. */
2544 if (ok
2545 && (prev2_op->flags & LOAD) != 0
2546 && sh_load_use (prev2_insn, prev2_op, insn, op))
2547 ok = false;
2548 }
2549
2550 if (ok)
2551 {
2552 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
2553 return false;
2554 *pswapped = true;
2555 continue;
2556 }
2557 }
2558
2559 while (*plabel < label_end && **plabel < i + 2)
2560 ++*plabel;
2561
2562 if (i + 2 < stop
2563 && (*plabel >= label_end || **plabel != i + 2))
2564 {
2565 unsigned int next_insn;
2566 const struct sh_opcode *next_op;
2567
2568 /* There is an instruction after the load/store
2569 instruction, and it does not have a label. */
2570 next_insn = bfd_get_16 (abfd, contents + i + 2);
2571 next_op = sh_insn_info (next_insn);
2572 if (next_op != NULL
2573 && (next_op->flags & (LOAD | STORE)) == 0
2574 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2575 {
2576 boolean ok;
2577
2578 /* NEXT_INSN is not itself a load/store instruction,
2579 and it does not conflict with INSN. */
2580
2581 ok = true;
2582
2583 /* If PREV_INSN is a load, and it sets a register
2584 which NEXT_INSN uses, then putting NEXT_INSN
2585 immediately after PREV_INSN will cause a pipeline
2586 bubble, so there is no reason to make this swap. */
2587 if (prev_op != NULL
2588 && (prev_op->flags & LOAD) != 0
2589 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
2590 ok = false;
2591
2592 /* If INSN is a load, and it sets a register which
2593 the insn after NEXT_INSN uses, then doing the
2594 swap will cause a pipeline bubble, so there is no
2595 reason to make the swap. However, if the insn
2596 after NEXT_INSN is itself a load or store
2597 instruction, then it is misaligned, so
2598 optimistically hope that it will be swapped
2599 itself, and just live with the pipeline bubble if
2600 it isn't. */
2601 if (ok
2602 && i + 4 < stop
2603 && (op->flags & LOAD) != 0)
2604 {
2605 unsigned int next2_insn;
2606 const struct sh_opcode *next2_op;
2607
2608 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2609 next2_op = sh_insn_info (next2_insn);
2610 if ((next2_op->flags & (LOAD | STORE)) == 0
2611 && sh_load_use (insn, op, next2_insn, next2_op))
2612 ok = false;
2613 }
2614
2615 if (ok)
2616 {
2617 if (! (*swap) (abfd, sec, relocs, contents, i))
2618 return false;
2619 *pswapped = true;
2620 continue;
2621 }
2622 }
2623 }
2624 }
2625
2626 return true;
2627 }
2628 #endif /* not COFF_IMAGE_WITH_PE */
2629
2630 /* Look for loads and stores which we can align to four byte
2631 boundaries. See the longer comment above sh_relax_section for why
2632 this is desirable. This sets *PSWAPPED if some instruction was
2633 swapped. */
2634
2635 static boolean
2636 sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2637 bfd *abfd;
2638 asection *sec;
2639 struct internal_reloc *internal_relocs;
2640 bfd_byte *contents;
2641 boolean *pswapped;
2642 {
2643 struct internal_reloc *irel, *irelend;
2644 bfd_vma *labels = NULL;
2645 bfd_vma *label, *label_end;
2646
2647 *pswapped = false;
2648
2649 irelend = internal_relocs + sec->reloc_count;
2650
2651 /* Get all the addresses with labels on them. */
2652 labels = (bfd_vma *) bfd_malloc (sec->reloc_count * sizeof (bfd_vma));
2653 if (labels == NULL)
2654 goto error_return;
2655 label_end = labels;
2656 for (irel = internal_relocs; irel < irelend; irel++)
2657 {
2658 if (irel->r_type == R_SH_LABEL)
2659 {
2660 *label_end = irel->r_vaddr - sec->vma;
2661 ++label_end;
2662 }
2663 }
2664
2665 /* Note that the assembler currently always outputs relocs in
2666 address order. If that ever changes, this code will need to sort
2667 the label values and the relocs. */
2668
2669 label = labels;
2670
2671 for (irel = internal_relocs; irel < irelend; irel++)
2672 {
2673 bfd_vma start, stop;
2674
2675 if (irel->r_type != R_SH_CODE)
2676 continue;
2677
2678 start = irel->r_vaddr - sec->vma;
2679
2680 for (irel++; irel < irelend; irel++)
2681 if (irel->r_type == R_SH_DATA)
2682 break;
2683 if (irel < irelend)
2684 stop = irel->r_vaddr - sec->vma;
2685 else
2686 stop = sec->_cooked_size;
2687
2688 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2689 (PTR) internal_relocs, &label,
2690 label_end, start, stop, pswapped))
2691 goto error_return;
2692 }
2693
2694 free (labels);
2695
2696 return true;
2697
2698 error_return:
2699 if (labels != NULL)
2700 free (labels);
2701 return false;
2702 }
2703
2704 /* Swap two SH instructions. */
2705
2706 static boolean
2707 sh_swap_insns (abfd, sec, relocs, contents, addr)
2708 bfd *abfd;
2709 asection *sec;
2710 PTR relocs;
2711 bfd_byte *contents;
2712 bfd_vma addr;
2713 {
2714 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2715 unsigned short i1, i2;
2716 struct internal_reloc *irel, *irelend;
2717
2718 /* Swap the instructions themselves. */
2719 i1 = bfd_get_16 (abfd, contents + addr);
2720 i2 = bfd_get_16 (abfd, contents + addr + 2);
2721 bfd_put_16 (abfd, i2, contents + addr);
2722 bfd_put_16 (abfd, i1, contents + addr + 2);
2723
2724 /* Adjust all reloc addresses. */
2725 irelend = internal_relocs + sec->reloc_count;
2726 for (irel = internal_relocs; irel < irelend; irel++)
2727 {
2728 int type, add;
2729
2730 /* There are a few special types of relocs that we don't want to
2731 adjust. These relocs do not apply to the instruction itself,
2732 but are only associated with the address. */
2733 type = irel->r_type;
2734 if (type == R_SH_ALIGN
2735 || type == R_SH_CODE
2736 || type == R_SH_DATA
2737 || type == R_SH_LABEL)
2738 continue;
2739
2740 /* If an R_SH_USES reloc points to one of the addresses being
2741 swapped, we must adjust it. It would be incorrect to do this
2742 for a jump, though, since we want to execute both
2743 instructions after the jump. (We have avoided swapping
2744 around a label, so the jump will not wind up executing an
2745 instruction it shouldn't). */
2746 if (type == R_SH_USES)
2747 {
2748 bfd_vma off;
2749
2750 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2751 if (off == addr)
2752 irel->r_offset += 2;
2753 else if (off == addr + 2)
2754 irel->r_offset -= 2;
2755 }
2756
2757 if (irel->r_vaddr - sec->vma == addr)
2758 {
2759 irel->r_vaddr += 2;
2760 add = -2;
2761 }
2762 else if (irel->r_vaddr - sec->vma == addr + 2)
2763 {
2764 irel->r_vaddr -= 2;
2765 add = 2;
2766 }
2767 else
2768 add = 0;
2769
2770 if (add != 0)
2771 {
2772 bfd_byte *loc;
2773 unsigned short insn, oinsn;
2774 boolean overflow;
2775
2776 loc = contents + irel->r_vaddr - sec->vma;
2777 overflow = false;
2778 switch (type)
2779 {
2780 default:
2781 break;
2782
2783 case R_SH_PCDISP8BY2:
2784 case R_SH_PCRELIMM8BY2:
2785 insn = bfd_get_16 (abfd, loc);
2786 oinsn = insn;
2787 insn += add / 2;
2788 if ((oinsn & 0xff00) != (insn & 0xff00))
2789 overflow = true;
2790 bfd_put_16 (abfd, insn, loc);
2791 break;
2792
2793 case R_SH_PCDISP:
2794 insn = bfd_get_16 (abfd, loc);
2795 oinsn = insn;
2796 insn += add / 2;
2797 if ((oinsn & 0xf000) != (insn & 0xf000))
2798 overflow = true;
2799 bfd_put_16 (abfd, insn, loc);
2800 break;
2801
2802 case R_SH_PCRELIMM8BY4:
2803 /* This reloc ignores the least significant 3 bits of
2804 the program counter before adding in the offset.
2805 This means that if ADDR is at an even address, the
2806 swap will not affect the offset. If ADDR is an at an
2807 odd address, then the instruction will be crossing a
2808 four byte boundary, and must be adjusted. */
2809 if ((addr & 3) != 0)
2810 {
2811 insn = bfd_get_16 (abfd, loc);
2812 oinsn = insn;
2813 insn += add / 2;
2814 if ((oinsn & 0xff00) != (insn & 0xff00))
2815 overflow = true;
2816 bfd_put_16 (abfd, insn, loc);
2817 }
2818
2819 break;
2820 }
2821
2822 if (overflow)
2823 {
2824 ((*_bfd_error_handler)
2825 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
2826 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
2827 bfd_set_error (bfd_error_bad_value);
2828 return false;
2829 }
2830 }
2831 }
2832
2833 return true;
2834 }
2835 \f
2836 /* This is a modification of _bfd_coff_generic_relocate_section, which
2837 will handle SH relaxing. */
2838
2839 static boolean
2840 sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2841 relocs, syms, sections)
2842 bfd *output_bfd ATTRIBUTE_UNUSED;
2843 struct bfd_link_info *info;
2844 bfd *input_bfd;
2845 asection *input_section;
2846 bfd_byte *contents;
2847 struct internal_reloc *relocs;
2848 struct internal_syment *syms;
2849 asection **sections;
2850 {
2851 struct internal_reloc *rel;
2852 struct internal_reloc *relend;
2853
2854 rel = relocs;
2855 relend = rel + input_section->reloc_count;
2856 for (; rel < relend; rel++)
2857 {
2858 long symndx;
2859 struct coff_link_hash_entry *h;
2860 struct internal_syment *sym;
2861 bfd_vma addend;
2862 bfd_vma val;
2863 reloc_howto_type *howto;
2864 bfd_reloc_status_type rstat;
2865
2866 /* Almost all relocs have to do with relaxing. If any work must
2867 be done for them, it has been done in sh_relax_section. */
2868 if (rel->r_type != R_SH_IMM32
2869 #ifdef COFF_WITH_PE
2870 && rel->r_type != R_SH_IMM32CE
2871 && rel->r_type != R_SH_IMAGEBASE
2872 #endif
2873 && rel->r_type != R_SH_PCDISP)
2874 continue;
2875
2876 symndx = rel->r_symndx;
2877
2878 if (symndx == -1)
2879 {
2880 h = NULL;
2881 sym = NULL;
2882 }
2883 else
2884 {
2885 if (symndx < 0
2886 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2887 {
2888 (*_bfd_error_handler)
2889 ("%s: illegal symbol index %ld in relocs",
2890 bfd_get_filename (input_bfd), symndx);
2891 bfd_set_error (bfd_error_bad_value);
2892 return false;
2893 }
2894 h = obj_coff_sym_hashes (input_bfd)[symndx];
2895 sym = syms + symndx;
2896 }
2897
2898 if (sym != NULL && sym->n_scnum != 0)
2899 addend = - sym->n_value;
2900 else
2901 addend = 0;
2902
2903 if (rel->r_type == R_SH_PCDISP)
2904 addend -= 4;
2905
2906 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2907 howto = NULL;
2908 else
2909 howto = &sh_coff_howtos[rel->r_type];
2910
2911 if (howto == NULL)
2912 {
2913 bfd_set_error (bfd_error_bad_value);
2914 return false;
2915 }
2916
2917 #ifdef COFF_WITH_PE
2918 if (rel->r_type == R_SH_IMAGEBASE)
2919 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2920 #endif
2921
2922 val = 0;
2923
2924 if (h == NULL)
2925 {
2926 asection *sec;
2927
2928 /* There is nothing to do for an internal PCDISP reloc. */
2929 if (rel->r_type == R_SH_PCDISP)
2930 continue;
2931
2932 if (symndx == -1)
2933 {
2934 sec = bfd_abs_section_ptr;
2935 val = 0;
2936 }
2937 else
2938 {
2939 sec = sections[symndx];
2940 val = (sec->output_section->vma
2941 + sec->output_offset
2942 + sym->n_value
2943 - sec->vma);
2944 }
2945 }
2946 else
2947 {
2948 if (h->root.type == bfd_link_hash_defined
2949 || h->root.type == bfd_link_hash_defweak)
2950 {
2951 asection *sec;
2952
2953 sec = h->root.u.def.section;
2954 val = (h->root.u.def.value
2955 + sec->output_section->vma
2956 + sec->output_offset);
2957 }
2958 else if (! info->relocateable)
2959 {
2960 if (! ((*info->callbacks->undefined_symbol)
2961 (info, h->root.root.string, input_bfd, input_section,
2962 rel->r_vaddr - input_section->vma, true)))
2963 return false;
2964 }
2965 }
2966
2967 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2968 contents,
2969 rel->r_vaddr - input_section->vma,
2970 val, addend);
2971
2972 switch (rstat)
2973 {
2974 default:
2975 abort ();
2976 case bfd_reloc_ok:
2977 break;
2978 case bfd_reloc_overflow:
2979 {
2980 const char *name;
2981 char buf[SYMNMLEN + 1];
2982
2983 if (symndx == -1)
2984 name = "*ABS*";
2985 else if (h != NULL)
2986 name = h->root.root.string;
2987 else if (sym->_n._n_n._n_zeroes == 0
2988 && sym->_n._n_n._n_offset != 0)
2989 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2990 else
2991 {
2992 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2993 buf[SYMNMLEN] = '\0';
2994 name = buf;
2995 }
2996
2997 if (! ((*info->callbacks->reloc_overflow)
2998 (info, name, howto->name, (bfd_vma) 0, input_bfd,
2999 input_section, rel->r_vaddr - input_section->vma)))
3000 return false;
3001 }
3002 }
3003 }
3004
3005 return true;
3006 }
3007
3008 /* This is a version of bfd_generic_get_relocated_section_contents
3009 which uses sh_relocate_section. */
3010
3011 static bfd_byte *
3012 sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
3013 data, relocateable, symbols)
3014 bfd *output_bfd;
3015 struct bfd_link_info *link_info;
3016 struct bfd_link_order *link_order;
3017 bfd_byte *data;
3018 boolean relocateable;
3019 asymbol **symbols;
3020 {
3021 asection *input_section = link_order->u.indirect.section;
3022 bfd *input_bfd = input_section->owner;
3023 asection **sections = NULL;
3024 struct internal_reloc *internal_relocs = NULL;
3025 struct internal_syment *internal_syms = NULL;
3026
3027 /* We only need to handle the case of relaxing, or of having a
3028 particular set of section contents, specially. */
3029 if (relocateable
3030 || coff_section_data (input_bfd, input_section) == NULL
3031 || coff_section_data (input_bfd, input_section)->contents == NULL)
3032 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
3033 link_order, data,
3034 relocateable,
3035 symbols);
3036
3037 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
3038 input_section->_raw_size);
3039
3040 if ((input_section->flags & SEC_RELOC) != 0
3041 && input_section->reloc_count > 0)
3042 {
3043 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
3044 bfd_byte *esym, *esymend;
3045 struct internal_syment *isymp;
3046 asection **secpp;
3047
3048 if (! _bfd_coff_get_external_symbols (input_bfd))
3049 goto error_return;
3050
3051 internal_relocs = (_bfd_coff_read_internal_relocs
3052 (input_bfd, input_section, false, (bfd_byte *) NULL,
3053 false, (struct internal_reloc *) NULL));
3054 if (internal_relocs == NULL)
3055 goto error_return;
3056
3057 internal_syms = ((struct internal_syment *)
3058 bfd_malloc (obj_raw_syment_count (input_bfd)
3059 * sizeof (struct internal_syment)));
3060 if (internal_syms == NULL)
3061 goto error_return;
3062
3063 sections = (asection **) bfd_malloc (obj_raw_syment_count (input_bfd)
3064 * sizeof (asection *));
3065 if (sections == NULL)
3066 goto error_return;
3067
3068 isymp = internal_syms;
3069 secpp = sections;
3070 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
3071 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
3072 while (esym < esymend)
3073 {
3074 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
3075
3076 if (isymp->n_scnum != 0)
3077 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
3078 else
3079 {
3080 if (isymp->n_value == 0)
3081 *secpp = bfd_und_section_ptr;
3082 else
3083 *secpp = bfd_com_section_ptr;
3084 }
3085
3086 esym += (isymp->n_numaux + 1) * symesz;
3087 secpp += isymp->n_numaux + 1;
3088 isymp += isymp->n_numaux + 1;
3089 }
3090
3091 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
3092 input_section, data, internal_relocs,
3093 internal_syms, sections))
3094 goto error_return;
3095
3096 free (sections);
3097 sections = NULL;
3098 free (internal_syms);
3099 internal_syms = NULL;
3100 free (internal_relocs);
3101 internal_relocs = NULL;
3102 }
3103
3104 return data;
3105
3106 error_return:
3107 if (internal_relocs != NULL)
3108 free (internal_relocs);
3109 if (internal_syms != NULL)
3110 free (internal_syms);
3111 if (sections != NULL)
3112 free (sections);
3113 return NULL;
3114 }
3115
3116 /* The target vectors. */
3117
3118 #ifndef TARGET_SHL_SYM
3119 CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL)
3120 #endif
3121
3122 #ifdef TARGET_SHL_SYM
3123 #define TARGET_SYM TARGET_SHL_SYM
3124 #else
3125 #define TARGET_SYM shlcoff_vec
3126 #endif
3127
3128 #ifndef TARGET_SHL_NAME
3129 #define TARGET_SHL_NAME "coff-shl"
3130 #endif
3131
3132 #ifdef COFF_WITH_PE
3133 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3134 SEC_CODE | SEC_DATA, '_', NULL);
3135 #else
3136 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3137 0, '_', NULL)
3138 #endif
3139
3140 #ifndef TARGET_SHL_SYM
3141 static const bfd_target * coff_small_object_p PARAMS ((bfd *));
3142 static boolean coff_small_new_section_hook PARAMS ((bfd *, asection *));
3143 /* Some people want versions of the SH COFF target which do not align
3144 to 16 byte boundaries. We implement that by adding a couple of new
3145 target vectors. These are just like the ones above, but they
3146 change the default section alignment. To generate them in the
3147 assembler, use -small. To use them in the linker, use -b
3148 coff-sh{l}-small and -oformat coff-sh{l}-small.
3149
3150 Yes, this is a horrible hack. A general solution for setting
3151 section alignment in COFF is rather complex. ELF handles this
3152 correctly. */
3153
3154 /* Only recognize the small versions if the target was not defaulted.
3155 Otherwise we won't recognize the non default endianness. */
3156
3157 static const bfd_target *
3158 coff_small_object_p (abfd)
3159 bfd *abfd;
3160 {
3161 if (abfd->target_defaulted)
3162 {
3163 bfd_set_error (bfd_error_wrong_format);
3164 return NULL;
3165 }
3166 return coff_object_p (abfd);
3167 }
3168
3169 /* Set the section alignment for the small versions. */
3170
3171 static boolean
3172 coff_small_new_section_hook (abfd, section)
3173 bfd *abfd;
3174 asection *section;
3175 {
3176 if (! coff_new_section_hook (abfd, section))
3177 return false;
3178
3179 /* We must align to at least a four byte boundary, because longword
3180 accesses must be on a four byte boundary. */
3181 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3182 section->alignment_power = 2;
3183
3184 return true;
3185 }
3186
3187 /* This is copied from bfd_coff_std_swap_table so that we can change
3188 the default section alignment power. */
3189
3190 static const bfd_coff_backend_data bfd_coff_small_swap_table =
3191 {
3192 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3193 coff_swap_aux_out, coff_swap_sym_out,
3194 coff_swap_lineno_out, coff_swap_reloc_out,
3195 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3196 coff_swap_scnhdr_out,
3197 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
3198 #ifdef COFF_LONG_FILENAMES
3199 true,
3200 #else
3201 false,
3202 #endif
3203 #ifdef COFF_LONG_SECTION_NAMES
3204 true,
3205 #else
3206 false,
3207 #endif
3208 2,
3209 #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
3210 true,
3211 #else
3212 false,
3213 #endif
3214 #ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3215 4,
3216 #else
3217 2,
3218 #endif
3219 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3220 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3221 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3222 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3223 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
3224 coff_classify_symbol, coff_compute_section_file_positions,
3225 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3226 coff_adjust_symndx, coff_link_add_one_symbol,
3227 coff_link_output_has_begun, coff_final_link_postscript
3228 };
3229
3230 #define coff_small_close_and_cleanup \
3231 coff_close_and_cleanup
3232 #define coff_small_bfd_free_cached_info \
3233 coff_bfd_free_cached_info
3234 #define coff_small_get_section_contents \
3235 coff_get_section_contents
3236 #define coff_small_get_section_contents_in_window \
3237 coff_get_section_contents_in_window
3238
3239 extern const bfd_target shlcoff_small_vec;
3240
3241 const bfd_target shcoff_small_vec =
3242 {
3243 "coff-sh-small", /* name */
3244 bfd_target_coff_flavour,
3245 BFD_ENDIAN_BIG, /* data byte order is big */
3246 BFD_ENDIAN_BIG, /* header byte order is big */
3247
3248 (HAS_RELOC | EXEC_P | /* object flags */
3249 HAS_LINENO | HAS_DEBUG |
3250 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3251
3252 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3253 '_', /* leading symbol underscore */
3254 '/', /* ar_pad_char */
3255 15, /* ar_max_namelen */
3256 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3257 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3258 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3259 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3260 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3261 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3262
3263 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3264 bfd_generic_archive_p, _bfd_dummy_target},
3265 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3266 bfd_false},
3267 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3268 _bfd_write_archive_contents, bfd_false},
3269
3270 BFD_JUMP_TABLE_GENERIC (coff_small),
3271 BFD_JUMP_TABLE_COPY (coff),
3272 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3273 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3274 BFD_JUMP_TABLE_SYMBOLS (coff),
3275 BFD_JUMP_TABLE_RELOCS (coff),
3276 BFD_JUMP_TABLE_WRITE (coff),
3277 BFD_JUMP_TABLE_LINK (coff),
3278 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3279
3280 & shlcoff_small_vec,
3281
3282 (PTR) &bfd_coff_small_swap_table
3283 };
3284
3285 const bfd_target shlcoff_small_vec =
3286 {
3287 "coff-shl-small", /* name */
3288 bfd_target_coff_flavour,
3289 BFD_ENDIAN_LITTLE, /* data byte order is little */
3290 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3291
3292 (HAS_RELOC | EXEC_P | /* object flags */
3293 HAS_LINENO | HAS_DEBUG |
3294 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3295
3296 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3297 '_', /* leading symbol underscore */
3298 '/', /* ar_pad_char */
3299 15, /* ar_max_namelen */
3300 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3301 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3302 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3303 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3304 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3305 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3306
3307 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3308 bfd_generic_archive_p, _bfd_dummy_target},
3309 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3310 bfd_false},
3311 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3312 _bfd_write_archive_contents, bfd_false},
3313
3314 BFD_JUMP_TABLE_GENERIC (coff_small),
3315 BFD_JUMP_TABLE_COPY (coff),
3316 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3317 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3318 BFD_JUMP_TABLE_SYMBOLS (coff),
3319 BFD_JUMP_TABLE_RELOCS (coff),
3320 BFD_JUMP_TABLE_WRITE (coff),
3321 BFD_JUMP_TABLE_LINK (coff),
3322 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3323
3324 & shcoff_small_vec,
3325
3326 (PTR) &bfd_coff_small_swap_table
3327 };
3328 #endif
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