1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
18 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the @sc{mips} instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of @sc{mips} assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Opts:: Assembler options
26 * MIPS Object:: ECOFF object code
27 * MIPS Stabs:: Directives for debugging information
28 * MIPS ISA:: Directives to override the ISA level
29 * MIPS symbol sizes:: Directives to override the size of symbols
30 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
31 * MIPS insn:: Directive to mark data as an instruction
32 * MIPS option stack:: Directives to save and restore options
33 * MIPS ASE instruction generation overrides:: Directives to control
34 generation of MIPS ASE instructions
35 * MIPS floating-point:: Directives to override floating-point options
39 @section Assembler options
41 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
45 @cindex @code{-G} option (MIPS)
47 This option sets the largest size of an object that can be referenced
48 implicitly with the @code{gp} register. It is only accepted for targets
49 that use @sc{ecoff} format. The default value is 8.
51 @cindex @code{-EB} option (MIPS)
52 @cindex @code{-EL} option (MIPS)
53 @cindex MIPS big-endian output
54 @cindex MIPS little-endian output
55 @cindex big-endian output, MIPS
56 @cindex little-endian output, MIPS
59 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
60 little-endian output at run time (unlike the other @sc{gnu} development
61 tools, which must be configured for one or the other). Use @samp{-EB}
62 to select big-endian output, and @samp{-EL} for little-endian.
65 @cindex PIC selection, MIPS
66 @cindex @option{-KPIC} option, MIPS
67 Generate SVR4-style PIC. This option tells the assembler to generate
68 SVR4-style position-independent macro expansions. It also tells the
69 assembler to mark the output file as PIC.
72 @cindex @option{-mvxworks-pic} option, MIPS
73 Generate VxWorks PIC. This option tells the assembler to generate
74 VxWorks-style position-independent macro expansions.
76 @cindex MIPS architecture options
86 Generate code for a particular MIPS Instruction Set Architecture level.
87 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
88 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
89 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
90 @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
91 @samp{-mips64}, and @samp{-mips64r2}
93 @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
94 and @sc{MIPS64 Release 2}
95 ISA processors, respectively. You can also switch
96 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
97 override the ISA level}.
101 Some macros have different expansions for 32-bit and 64-bit registers.
102 The register sizes are normally inferred from the ISA and ABI, but these
103 flags force a certain group of registers to be treated as 32 bits wide at
104 all times. @samp{-mgp32} controls the size of general-purpose registers
105 and @samp{-mfp32} controls the size of floating-point registers.
107 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
108 of registers to be changed for parts of an object. The default value is
109 restored by @code{.set gp=default} and @code{.set fp=default}.
111 On some MIPS variants there is a 32-bit mode flag; when this flag is
112 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
113 save the 32-bit registers on a context switch, so it is essential never
114 to use the 64-bit registers.
118 Assume that 64-bit registers are available. This is provided in the
119 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
121 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
122 of registers to be changed for parts of an object. The default value is
123 restored by @code{.set gp=default} and @code{.set fp=default}.
127 Generate code for the MIPS 16 processor. This is equivalent to putting
128 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
129 turns off this option.
132 @itemx -mno-smartmips
133 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
134 provides a number of new instructions which target smartcard and
135 cryptographic applications. This is equivalent to putting
136 @code{.set smartmips} at the start of the assembly file.
137 @samp{-mno-smartmips} turns off this option.
141 Generate code for the MIPS-3D Application Specific Extension.
142 This tells the assembler to accept MIPS-3D instructions.
143 @samp{-no-mips3d} turns off this option.
147 Generate code for the MDMX Application Specific Extension.
148 This tells the assembler to accept MDMX instructions.
149 @samp{-no-mdmx} turns off this option.
153 Generate code for the DSP Release 1 Application Specific Extension.
154 This tells the assembler to accept DSP Release 1 instructions.
155 @samp{-mno-dsp} turns off this option.
159 Generate code for the DSP Release 2 Application Specific Extension.
160 This option implies -mdsp.
161 This tells the assembler to accept DSP Release 2 instructions.
162 @samp{-mno-dspr2} turns off this option.
166 Generate code for the MT Application Specific Extension.
167 This tells the assembler to accept MT instructions.
168 @samp{-mno-mt} turns off this option.
172 Cause nops to be inserted if the read of the destination register
173 of an mfhi or mflo instruction occurs in the following two instructions.
176 @itemx -no-mfix-vr4120
177 Insert nops to work around certain VR4120 errata. This option is
178 intended to be used on GCC-generated code: it is not designed to catch
179 all problems in hand-written assembler code.
182 @itemx -no-mfix-vr4130
183 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
187 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
188 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
189 etc.), and to not schedule @samp{nop} instructions around accesses to
190 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
195 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
196 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
197 instructions around accesses to the @samp{HI} and @samp{LO} registers.
198 @samp{-no-m4650} turns off this option.
204 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
205 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
206 specific to that chip, and to schedule for that chip's hazards.
208 @item -march=@var{cpu}
209 Generate code for a particular MIPS cpu. It is exactly equivalent to
210 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
211 understood. Valid @var{cpu} value are:
282 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
283 accepted as synonyms for @samp{@var{n}f1_1}. These values are
286 @item -mtune=@var{cpu}
287 Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
288 identical to @samp{-march=@var{cpu}}.
290 @item -mabi=@var{abi}
291 Record which ABI the source code uses. The recognized arguments
292 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
298 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
299 the beginning of the assembler input. @xref{MIPS symbol sizes}.
301 @cindex @code{-nocpp} ignored (MIPS)
303 This option is ignored. It is accepted for command-line compatibility with
304 other assemblers, which use it to turn off C style preprocessing. With
305 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
306 @sc{gnu} assembler itself never runs the C preprocessor.
310 Disable or enable floating-point instructions. Note that by default
311 floating-point instructions are always allowed even with CPU targets
312 that don't have support for these instructions.
315 @itemx -mdouble-float
316 Disable or enable double-precision floating-point operations. Note
317 that by default double-precision floating-point operations are always
318 allowed even with CPU targets that don't have support for these
321 @item --construct-floats
322 @itemx --no-construct-floats
323 The @code{--no-construct-floats} option disables the construction of
324 double width floating point constants by loading the two halves of the
325 value into the two single width floating point registers that make up
326 the double width register. This feature is useful if the processor
327 support the FR bit in its status register, and this bit is known (by
328 the programmer) to be set. This bit prevents the aliasing of the double
329 width register by the single width registers.
331 By default @code{--construct-floats} is selected, allowing construction
332 of these floating point constants.
336 @c FIXME! (1) reflect these options (next item too) in option summaries;
337 @c (2) stop teasing, say _which_ instructions expanded _how_.
338 @code{@value{AS}} automatically macro expands certain division and
339 multiplication instructions to check for overflow and division by zero. This
340 option causes @code{@value{AS}} to generate code to take a trap exception
341 rather than a break exception when an error is detected. The trap instructions
342 are only supported at Instruction Set Architecture level 2 and higher.
346 Generate code to take a break exception rather than a trap exception when an
347 error is detected. This is the default.
351 Control generation of @code{.pdr} sections. Off by default on IRIX, on
356 When generating code using the Unix calling conventions (selected by
357 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
358 which can go into a shared library. The @samp{-mno-shared} option
359 tells gas to generate code which uses the calling convention, but can
360 not go into a shared library. The resulting code is slightly more
361 efficient. This option only affects the handling of the
362 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
366 @section MIPS ECOFF object code
368 @cindex ECOFF sections
369 @cindex MIPS ECOFF sections
370 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
371 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
372 additional sections are @code{.rdata}, used for read-only data,
373 @code{.sdata}, used for small data, and @code{.sbss}, used for small
376 @cindex small objects, MIPS ECOFF
377 @cindex @code{gp} register, MIPS
378 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
379 register to form the address of a ``small object''. Any object in the
380 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
381 For external objects, or for objects in the @code{.bss} section, you can use
382 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
383 @code{$gp}; the default value is 8, meaning that a reference to any object
384 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
385 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
386 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
387 or @code{sbss} in any case). The size of an object in the @code{.bss} section
388 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
389 size of an external object may be set with the @code{.extern} directive. For
390 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
391 in length, whie leaving @code{sym} otherwise undefined.
393 Using small @sc{ecoff} objects requires linker support, and assumes that the
394 @code{$gp} register is correctly initialized (normally done automatically by
395 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
399 @section Directives for debugging information
401 @cindex MIPS debugging directives
402 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
403 generating debugging information which are not support by traditional @sc{mips}
404 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
405 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
406 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
407 generated by the three @code{.stab} directives can only be read by @sc{gdb},
408 not by traditional @sc{mips} debuggers (this enhancement is required to fully
409 support C++ debugging). These directives are primarily used by compilers, not
410 assembly language programmers!
412 @node MIPS symbol sizes
413 @section Directives to override the size of symbols
415 @cindex @code{.set sym32}
416 @cindex @code{.set nosym32}
417 The n64 ABI allows symbols to have any 64-bit value. Although this
418 provides a great deal of flexibility, it means that some macros have
419 much longer expansions than their 32-bit counterparts. For example,
420 the non-PIC expansion of @samp{dla $4,sym} is usually:
425 daddiu $4,$4,%higher(sym)
426 daddiu $1,$1,%lo(sym)
431 whereas the 32-bit expansion is simply:
435 daddiu $4,$4,%lo(sym)
438 n64 code is sometimes constructed in such a way that all symbolic
439 constants are known to have 32-bit values, and in such cases, it's
440 preferable to use the 32-bit expansion instead of the 64-bit
443 You can use the @code{.set sym32} directive to tell the assembler
444 that, from this point on, all expressions of the form
445 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
446 have 32-bit values. For example:
455 will cause the assembler to treat @samp{sym}, @code{sym+16} and
456 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
457 addresses is not affected.
459 The directive @code{.set nosym32} ends a @code{.set sym32} block and
460 reverts to the normal behavior. It is also possible to change the
461 symbol size using the command-line options @option{-msym32} and
464 These options and directives are always accepted, but at present,
465 they have no effect for anything other than n64.
468 @section Directives to override the ISA level
470 @cindex MIPS ISA override
471 @kindex @code{.set mips@var{n}}
472 @sc{gnu} @code{@value{AS}} supports an additional directive to change
473 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
474 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
476 The values other than 0 make the assembler accept instructions
477 for the corresponding @sc{isa} level, from that point on in the
478 assembly. @code{.set mips@var{n}} affects not only which instructions
479 are permitted, but also how certain macros are expanded. @code{.set
480 mips0} restores the @sc{isa} level to its original level: either the
481 level you selected with command line options, or the default for your
482 configuration. You can use this feature to permit specific @sc{mips3}
483 instructions while assembling in 32 bit mode. Use this directive with
486 @cindex MIPS CPU override
487 @kindex @code{.set arch=@var{cpu}}
488 The @code{.set arch=@var{cpu}} directive provides even finer control.
489 It changes the effective CPU target and allows the assembler to use
490 instructions specific to a particular CPU. All CPUs supported by the
491 @samp{-march} command line option are also selectable by this directive.
492 The original value is restored by @code{.set arch=default}.
494 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
495 in which it will assemble instructions for the MIPS 16 processor. Use
496 @code{.set nomips16} to return to normal 32 bit mode.
498 Traditional @sc{mips} assemblers do not support this directive.
500 @node MIPS autoextend
501 @section Directives for extending MIPS 16 bit instructions
503 @kindex @code{.set autoextend}
504 @kindex @code{.set noautoextend}
505 By default, MIPS 16 instructions are automatically extended to 32 bits
506 when necessary. The directive @code{.set noautoextend} will turn this
507 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
508 must be explicitly extended with the @code{.e} modifier (e.g.,
509 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
510 to once again automatically extend instructions when necessary.
512 This directive is only meaningful when in MIPS 16 mode. Traditional
513 @sc{mips} assemblers do not support this directive.
516 @section Directive to mark data as an instruction
519 The @code{.insn} directive tells @code{@value{AS}} that the following
520 data is actually instructions. This makes a difference in MIPS 16 mode:
521 when loading the address of a label which precedes instructions,
522 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
523 the loaded address will do the right thing.
525 @node MIPS option stack
526 @section Directives to save and restore options
528 @cindex MIPS option stack
529 @kindex @code{.set push}
530 @kindex @code{.set pop}
531 The directives @code{.set push} and @code{.set pop} may be used to save
532 and restore the current settings for all the options which are
533 controlled by @code{.set}. The @code{.set push} directive saves the
534 current settings on a stack. The @code{.set pop} directive pops the
535 stack and restores the settings.
537 These directives can be useful inside an macro which must change an
538 option such as the ISA level or instruction reordering but does not want
539 to change the state of the code which invoked the macro.
541 Traditional @sc{mips} assemblers do not support these directives.
543 @node MIPS ASE instruction generation overrides
544 @section Directives to control generation of MIPS ASE instructions
546 @cindex MIPS MIPS-3D instruction generation override
547 @kindex @code{.set mips3d}
548 @kindex @code{.set nomips3d}
549 The directive @code{.set mips3d} makes the assembler accept instructions
550 from the MIPS-3D Application Specific Extension from that point on
551 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
552 instructions from being accepted.
554 @cindex SmartMIPS instruction generation override
555 @kindex @code{.set smartmips}
556 @kindex @code{.set nosmartmips}
557 The directive @code{.set smartmips} makes the assembler accept
558 instructions from the SmartMIPS Application Specific Extension to the
559 MIPS32 @sc{isa} from that point on in the assembly. The
560 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
563 @cindex MIPS MDMX instruction generation override
564 @kindex @code{.set mdmx}
565 @kindex @code{.set nomdmx}
566 The directive @code{.set mdmx} makes the assembler accept instructions
567 from the MDMX Application Specific Extension from that point on
568 in the assembly. The @code{.set nomdmx} directive prevents MDMX
569 instructions from being accepted.
571 @cindex MIPS DSP Release 1 instruction generation override
572 @kindex @code{.set dsp}
573 @kindex @code{.set nodsp}
574 The directive @code{.set dsp} makes the assembler accept instructions
575 from the DSP Release 1 Application Specific Extension from that point
576 on in the assembly. The @code{.set nodsp} directive prevents DSP
577 Release 1 instructions from being accepted.
579 @cindex MIPS DSP Release 2 instruction generation override
580 @kindex @code{.set dspr2}
581 @kindex @code{.set nodspr2}
582 The directive @code{.set dspr2} makes the assembler accept instructions
583 from the DSP Release 2 Application Specific Extension from that point
584 on in the assembly. This dirctive implies @code{.set dsp}. The
585 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
588 @cindex MIPS MT instruction generation override
589 @kindex @code{.set mt}
590 @kindex @code{.set nomt}
591 The directive @code{.set mt} makes the assembler accept instructions
592 from the MT Application Specific Extension from that point on
593 in the assembly. The @code{.set nomt} directive prevents MT
594 instructions from being accepted.
596 Traditional @sc{mips} assemblers do not support these directives.
598 @node MIPS floating-point
599 @section Directives to override floating-point options
601 @cindex Disable floating-point instructions
602 @kindex @code{.set softfloat}
603 @kindex @code{.set hardfloat}
604 The directives @code{.set softfloat} and @code{.set hardfloat} provide
605 finer control of disabling and enabling float-point instructions.
606 These directives always override the default (that hard-float
607 instructions are accepted) or the command-line options
608 (@samp{-msoft-float} and @samp{-mhard-float}).
610 @cindex Disable single-precision floating-point operations
611 @kindex @code{.set softfloat}
612 @kindex @code{.set hardfloat}
613 The directives @code{.set singlefloat} and @code{.set doublefloat}
614 provide finer control of disabling and enabling double-precision
615 float-point operations. These directives always override the default
616 (that double-precision operations are accepted) or the command-line
617 options (@samp{-msingle-float} and @samp{-mdouble-float}).
619 Traditional @sc{mips} assemblers do not support these directives.