?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
bfd/
[binutils.git] / gas / config / tc-v850.c
blob69d4502904b23f22ac81a9a683d7003ac9cba377
1 /* tc-v850.c -- Assembler code for the NEC V850
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
3 2006, 2007, 2009, 2010 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "subsegs.h"
25 #include "opcode/v850.h"
26 #include "dwarf2dbg.h"
27
28 /* Sign-extend a 16-bit number. */
29 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000)
30
31 /* Temporarily holds the reloc in a cons expression. */
32 static bfd_reloc_code_real_type hold_cons_reloc = BFD_RELOC_UNUSED;
33
34 /* Set to TRUE if we want to be pedantic about signed overflows. */
35 static bfd_boolean warn_signed_overflows = FALSE;
36 static bfd_boolean warn_unsigned_overflows = FALSE;
37
38 /* Indicates the target BFD machine number. */
39 static int machine = -1;
40
41 /* Indicates the target processor(s) for the assemble. */
42 static int processor_mask = 0;
43 \f
44 /* Structure to hold information about predefined registers. */
45 struct reg_name
46 {
47 const char *name;
48 int value;
49 unsigned int processors;
50 };
51
52 /* Generic assembler global variables which must be defined by all
53 targets. */
54
55 /* Characters which always start a comment. */
56 const char comment_chars[] = "#";
57
58 /* Characters which start a comment at the beginning of a line. */
59 const char line_comment_chars[] = ";#";
60
61 /* Characters which may be used to separate multiple commands on a
62 single line. */
63 const char line_separator_chars[] = ";";
64
65 /* Characters which are used to indicate an exponent in a floating
66 point number. */
67 const char EXP_CHARS[] = "eE";
68
69 /* Characters which mean that a number is a floating point constant,
70 as in 0d1.0. */
71 const char FLT_CHARS[] = "dD";
72 \f
73 const relax_typeS md_relax_table[] =
74 {
75 /* Conditional branches.(V850/V850E, max 22bit) */
76 #define SUBYPTE_COND_9_22 0
77 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1},
78 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
79 /* Conditional branches.(V850/V850E, max 22bit) */
80 #define SUBYPTE_SA_9_22 2
81 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1},
82 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
83 /* Unconditional branches.(V850/V850E, max 22bit) */
84 #define SUBYPTE_UNCOND_9_22 4
85 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1},
86 {0x1ffffe, -0x200000, 4, 0},
87 /* Conditional branches.(V850E2, max 32bit) */
88 #define SUBYPTE_COND_9_22_32 6
89 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1},
90 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2},
91 {0x7ffffffe, -0x80000000, 8, 0},
92 /* Conditional branches.(V850E2, max 32bit) */
93 #define SUBYPTE_SA_9_22_32 9
94 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1},
95 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2},
96 {0x7ffffffe, -0x80000000, 10, 0},
97 /* Unconditional branches.(V850E2, max 32bit) */
98 #define SUBYPTE_UNCOND_9_22_32 12
99 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1},
100 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2},
101 {0x7ffffffe, -0x80000000, 6, 0},
102 /* Conditional branches.(V850E2R max 22bit) */
103 #define SUBYPTE_COND_9_17_22 15
104 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1},
105 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2},
106 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
107 /* Conditional branches.(V850E2R max 22bit) */
108 #define SUBYPTE_SA_9_17_22 18
109 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1},
110 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2},
111 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
112 /* Conditional branches.(V850E2R max 32bit) */
113 #define SUBYPTE_COND_9_17_22_32 21
114 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1},
115 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2},
116 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3},
117 {0x7ffffffe, -0x80000000, 8, 0},
118 /* Conditional branches.(V850E2R max 32bit) */
119 #define SUBYPTE_SA_9_17_22_32 25
120 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1},
121 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2},
122 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3},
123 {0x7ffffffe, -0x80000000, 10, 0},
124 };
125
126 static int v850_relax = 0;
127
128 /* Default branch disp size 22 or 32. */
129 static int default_disp_size = 22;
130
131 /* Default no using bcond17. */
132 static int no_bcond17 = 0;
133
134 /* Default no using ld/st 23bit offset. */
135 static int no_stld23 = 0;
136
137 /* Fixups. */
138 #define MAX_INSN_FIXUPS 5
139
140 struct v850_fixup
141 {
142 expressionS exp;
143 int opindex;
144 bfd_reloc_code_real_type reloc;
145 };
146
147 struct v850_fixup fixups[MAX_INSN_FIXUPS];
148 static int fc;
149
150 struct v850_seg_entry
151 {
152 segT s;
153 const char *name;
154 flagword flags;
155 };
156
157 struct v850_seg_entry v850_seg_table[] =
158 {
159 { NULL, ".sdata",
160 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
161 | SEC_SMALL_DATA },
162 { NULL, ".tdata",
163 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
164 { NULL, ".zdata",
165 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
166 { NULL, ".sbss",
167 SEC_ALLOC | SEC_SMALL_DATA },
168 { NULL, ".tbss",
169 SEC_ALLOC },
170 { NULL, ".zbss",
171 SEC_ALLOC},
172 { NULL, ".rosdata",
173 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
174 | SEC_HAS_CONTENTS | SEC_SMALL_DATA },
175 { NULL, ".rozdata",
176 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
177 | SEC_HAS_CONTENTS },
178 { NULL, ".scommon",
179 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
180 | SEC_SMALL_DATA | SEC_IS_COMMON },
181 { NULL, ".tcommon",
182 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
183 | SEC_IS_COMMON },
184 { NULL, ".zcommon",
185 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
186 | SEC_IS_COMMON },
187 { NULL, ".call_table_data",
188 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
189 { NULL, ".call_table_text",
190 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE
191 | SEC_HAS_CONTENTS},
192 { NULL, ".bss",
193 SEC_ALLOC }
194 };
195
196 #define SDATA_SECTION 0
197 #define TDATA_SECTION 1
198 #define ZDATA_SECTION 2
199 #define SBSS_SECTION 3
200 #define TBSS_SECTION 4
201 #define ZBSS_SECTION 5
202 #define ROSDATA_SECTION 6
203 #define ROZDATA_SECTION 7
204 #define SCOMMON_SECTION 8
205 #define TCOMMON_SECTION 9
206 #define ZCOMMON_SECTION 10
207 #define CALL_TABLE_DATA_SECTION 11
208 #define CALL_TABLE_TEXT_SECTION 12
209 #define BSS_SECTION 13
210
211 static void
212 do_v850_seg (int i, subsegT sub)
213 {
214 struct v850_seg_entry *seg = v850_seg_table + i;
215
216 obj_elf_section_change_hook ();
217
218 if (seg->s != NULL)
219 subseg_set (seg->s, sub);
220 else
221 {
222 seg->s = subseg_new (seg->name, sub);
223 bfd_set_section_flags (stdoutput, seg->s, seg->flags);
224 if ((seg->flags & SEC_LOAD) == 0)
225 seg_info (seg->s)->bss = 1;
226 }
227 }
228
229 static void
230 v850_seg (int i)
231 {
232 subsegT sub = get_absolute_expression ();
233
234 do_v850_seg (i, sub);
235 demand_empty_rest_of_line ();
236 }
237
238 static void
239 v850_offset (int ignore ATTRIBUTE_UNUSED)
240 {
241 char *pfrag;
242 int temp = get_absolute_expression ();
243
244 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0,
245 (offsetT) temp, (char *) 0);
246 *pfrag = 0;
247
248 demand_empty_rest_of_line ();
249 }
250
251 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */
252
253 static void
254 v850_comm (int area)
255 {
256 char *name;
257 char c;
258 char *p;
259 int temp;
260 unsigned int size;
261 symbolS *symbolP;
262 int have_align;
263
264 name = input_line_pointer;
265 c = get_symbol_end ();
266
267 /* Just after name is now '\0'. */
268 p = input_line_pointer;
269 *p = c;
270
271 SKIP_WHITESPACE ();
272
273 if (*input_line_pointer != ',')
274 {
275 as_bad (_("Expected comma after symbol-name"));
276 ignore_rest_of_line ();
277 return;
278 }
279
280 /* Skip ','. */
281 input_line_pointer++;
282
283 if ((temp = get_absolute_expression ()) < 0)
284 {
285 /* xgettext:c-format */
286 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp);
287 ignore_rest_of_line ();
288 return;
289 }
290
291 size = temp;
292 *p = 0;
293 symbolP = symbol_find_or_make (name);
294 *p = c;
295
296 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
297 {
298 as_bad (_("Ignoring attempt to re-define symbol"));
299 ignore_rest_of_line ();
300 return;
301 }
302
303 if (S_GET_VALUE (symbolP) != 0)
304 {
305 if (S_GET_VALUE (symbolP) != size)
306 /* xgettext:c-format */
307 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
308 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
309 }
310
311 know (symbol_get_frag (symbolP) == &zero_address_frag);
312
313 if (*input_line_pointer != ',')
314 have_align = 0;
315 else
316 {
317 have_align = 1;
318 input_line_pointer++;
319 SKIP_WHITESPACE ();
320 }
321
322 if (! have_align || *input_line_pointer != '"')
323 {
324 if (! have_align)
325 temp = 0;
326 else
327 {
328 temp = get_absolute_expression ();
329
330 if (temp < 0)
331 {
332 temp = 0;
333 as_warn (_("Common alignment negative; 0 assumed"));
334 }
335 }
336
337 if (symbol_get_obj (symbolP)->local)
338 {
339 segT old_sec;
340 int old_subsec;
341 char *pfrag;
342 int align;
343 flagword applicable;
344
345 old_sec = now_seg;
346 old_subsec = now_subseg;
347
348 applicable = bfd_applicable_section_flags (stdoutput);
349
350 applicable &= SEC_ALLOC;
351
352 switch (area)
353 {
354 case SCOMMON_SECTION:
355 do_v850_seg (SBSS_SECTION, 0);
356 break;
357
358 case ZCOMMON_SECTION:
359 do_v850_seg (ZBSS_SECTION, 0);
360 break;
361
362 case TCOMMON_SECTION:
363 do_v850_seg (TBSS_SECTION, 0);
364 break;
365 }
366
367 if (temp)
368 {
369 /* Convert to a power of 2 alignment. */
370 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align)
371 ;
372
373 if (temp != 1)
374 {
375 as_bad (_("Common alignment not a power of 2"));
376 ignore_rest_of_line ();
377 return;
378 }
379 }
380 else
381 align = 0;
382
383 record_alignment (now_seg, align);
384
385 if (align)
386 frag_align (align, 0, 0);
387
388 switch (area)
389 {
390 case SCOMMON_SECTION:
391 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s)
392 symbol_get_frag (symbolP)->fr_symbol = 0;
393 break;
394
395 case ZCOMMON_SECTION:
396 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s)
397 symbol_get_frag (symbolP)->fr_symbol = 0;
398 break;
399
400 case TCOMMON_SECTION:
401 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s)
402 symbol_get_frag (symbolP)->fr_symbol = 0;
403 break;
404
405 default:
406 abort ();
407 }
408
409 symbol_set_frag (symbolP, frag_now);
410 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
411 (offsetT) size, (char *) 0);
412 *pfrag = 0;
413 S_SET_SIZE (symbolP, size);
414
415 switch (area)
416 {
417 case SCOMMON_SECTION:
418 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s);
419 break;
420
421 case ZCOMMON_SECTION:
422 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s);
423 break;
424
425 case TCOMMON_SECTION:
426 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s);
427 break;
428
429 default:
430 abort ();
431 }
432
433 S_CLEAR_EXTERNAL (symbolP);
434 obj_elf_section_change_hook ();
435 subseg_set (old_sec, old_subsec);
436 }
437 else
438 {
439 segT old_sec;
440 int old_subsec;
441
442 allocate_common:
443 old_sec = now_seg;
444 old_subsec = now_subseg;
445
446 S_SET_VALUE (symbolP, (valueT) size);
447 S_SET_ALIGN (symbolP, temp);
448 S_SET_EXTERNAL (symbolP);
449
450 switch (area)
451 {
452 case SCOMMON_SECTION:
453 case ZCOMMON_SECTION:
454 case TCOMMON_SECTION:
455 do_v850_seg (area, 0);
456 S_SET_SEGMENT (symbolP, v850_seg_table[area].s);
457 break;
458
459 default:
460 abort ();
461 }
462
463 obj_elf_section_change_hook ();
464 subseg_set (old_sec, old_subsec);
465 }
466 }
467 else
468 {
469 input_line_pointer++;
470
471 /* @@ Some use the dot, some don't. Can we get some consistency?? */
472 if (*input_line_pointer == '.')
473 input_line_pointer++;
474
475 /* @@ Some say data, some say bss. */
476 if (strncmp (input_line_pointer, "bss\"", 4)
477 && strncmp (input_line_pointer, "data\"", 5))
478 {
479 while (*--input_line_pointer != '"')
480 ;
481 input_line_pointer--;
482 goto bad_common_segment;
483 }
484
485 while (*input_line_pointer++ != '"')
486 ;
487
488 goto allocate_common;
489 }
490
491 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
492
493 demand_empty_rest_of_line ();
494 return;
495
496 {
497 bad_common_segment:
498 p = input_line_pointer;
499 while (*p && *p != '\n')
500 p++;
501 c = *p;
502 *p = '\0';
503 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
504 *p = c;
505 input_line_pointer = p;
506 ignore_rest_of_line ();
507 return;
508 }
509 }
510
511 static void
512 set_machine (int number)
513 {
514 machine = number;
515 bfd_set_arch_mach (stdoutput, TARGET_ARCH, machine);
516
517 switch (machine)
518 {
519 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
520 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
521 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
522 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
523 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break;
524 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break;
525 }
526 }
527
528 static void
529 v850_longcode (int type)
530 {
531 expressionS ex;
532
533 if (! v850_relax)
534 {
535 if (type == 1)
536 as_warn (_(".longcall pseudo-op seen when not relaxing"));
537 else
538 as_warn (_(".longjump pseudo-op seen when not relaxing"));
539 }
540
541 expression (&ex);
542
543 if (ex.X_op != O_symbol || ex.X_add_number != 0)
544 {
545 as_bad (_("bad .longcall format"));
546 ignore_rest_of_line ();
547
548 return;
549 }
550
551 if (type == 1)
552 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
553 BFD_RELOC_V850_LONGCALL);
554 else
555 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
556 BFD_RELOC_V850_LONGJUMP);
557
558 demand_empty_rest_of_line ();
559 }
560
561 /* The target specific pseudo-ops which we support. */
562 const pseudo_typeS md_pseudo_table[] =
563 {
564 { "sdata", v850_seg, SDATA_SECTION },
565 { "tdata", v850_seg, TDATA_SECTION },
566 { "zdata", v850_seg, ZDATA_SECTION },
567 { "sbss", v850_seg, SBSS_SECTION },
568 { "tbss", v850_seg, TBSS_SECTION },
569 { "zbss", v850_seg, ZBSS_SECTION },
570 { "rosdata", v850_seg, ROSDATA_SECTION },
571 { "rozdata", v850_seg, ROZDATA_SECTION },
572 { "bss", v850_seg, BSS_SECTION },
573 { "offset", v850_offset, 0 },
574 { "word", cons, 4 },
575 { "zcomm", v850_comm, ZCOMMON_SECTION },
576 { "scomm", v850_comm, SCOMMON_SECTION },
577 { "tcomm", v850_comm, TCOMMON_SECTION },
578 { "v850", set_machine, 0 },
579 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION },
580 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION },
581 { "v850e", set_machine, bfd_mach_v850e },
582 { "v850e1", set_machine, bfd_mach_v850e1 },
583 { "v850e2", set_machine, bfd_mach_v850e2 },
584 { "v850e2v3", set_machine, bfd_mach_v850e2v3 },
585 { "longcall", v850_longcode, 1 },
586 { "longjump", v850_longcode, 2 },
587 { NULL, NULL, 0 }
588 };
589
590 /* Opcode hash table. */
591 static struct hash_control *v850_hash;
592
593 /* This table is sorted. Suitable for searching by a binary search. */
594 static const struct reg_name pre_defined_registers[] =
595 {
596 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */
597 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */
598 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */
599 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */
600 { "r0", 0, PROCESSOR_ALL },
601 { "r1", 1, PROCESSOR_ALL },
602 { "r10", 10, PROCESSOR_ALL },
603 { "r11", 11, PROCESSOR_ALL },
604 { "r12", 12, PROCESSOR_ALL },
605 { "r13", 13, PROCESSOR_ALL },
606 { "r14", 14, PROCESSOR_ALL },
607 { "r15", 15, PROCESSOR_ALL },
608 { "r16", 16, PROCESSOR_ALL },
609 { "r17", 17, PROCESSOR_ALL },
610 { "r18", 18, PROCESSOR_ALL },
611 { "r19", 19, PROCESSOR_ALL },
612 { "r2", 2, PROCESSOR_ALL },
613 { "r20", 20, PROCESSOR_ALL },
614 { "r21", 21, PROCESSOR_ALL },
615 { "r22", 22, PROCESSOR_ALL },
616 { "r23", 23, PROCESSOR_ALL },
617 { "r24", 24, PROCESSOR_ALL },
618 { "r25", 25, PROCESSOR_ALL },
619 { "r26", 26, PROCESSOR_ALL },
620 { "r27", 27, PROCESSOR_ALL },
621 { "r28", 28, PROCESSOR_ALL },
622 { "r29", 29, PROCESSOR_ALL },
623 { "r3", 3, PROCESSOR_ALL },
624 { "r30", 30, PROCESSOR_ALL },
625 { "r31", 31, PROCESSOR_ALL },
626 { "r4", 4, PROCESSOR_ALL },
627 { "r5", 5, PROCESSOR_ALL },
628 { "r6", 6, PROCESSOR_ALL },
629 { "r7", 7, PROCESSOR_ALL },
630 { "r8", 8, PROCESSOR_ALL },
631 { "r9", 9, PROCESSOR_ALL },
632 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */
633 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */
634 { "zero", 0, PROCESSOR_ALL },
635 };
636
637 #define REG_NAME_CNT \
638 (sizeof (pre_defined_registers) / sizeof (struct reg_name))
639
640 static const struct reg_name system_registers[] =
641 {
642 { "asid", 23, PROCESSOR_NOT_V850 },
643 { "bpam", 25, PROCESSOR_NOT_V850 },
644 { "bpav", 24, PROCESSOR_NOT_V850 },
645 { "bpc", 22, PROCESSOR_NOT_V850 },
646 { "bpdm", 27, PROCESSOR_NOT_V850 },
647 { "bpdv", 26, PROCESSOR_NOT_V850 },
648 { "bsel", 31, PROCESSOR_V850E2_ALL },
649 { "cfg", 7, PROCESSOR_V850E2V3 },
650 { "ctbp", 20, PROCESSOR_NOT_V850 },
651 { "ctpc", 16, PROCESSOR_NOT_V850 },
652 { "ctpsw", 17, PROCESSOR_NOT_V850 },
653 { "dbic", 15, PROCESSOR_V850E2_ALL },
654 { "dbpc", 18, PROCESSOR_NOT_V850 },
655 { "dbpsw", 19, PROCESSOR_NOT_V850 },
656 { "dbwr", 30, PROCESSOR_V850E2_ALL },
657 { "dir", 21, PROCESSOR_NOT_V850 },
658 { "dpa0l", 16, PROCESSOR_V850E2V3 },
659 { "dpa0u", 17, PROCESSOR_V850E2V3 },
660 { "dpa1l", 18, PROCESSOR_V850E2V3 },
661 { "dpa1u", 19, PROCESSOR_V850E2V3 },
662 { "dpa2l", 20, PROCESSOR_V850E2V3 },
663 { "dpa2u", 21, PROCESSOR_V850E2V3 },
664 { "dpa3l", 22, PROCESSOR_V850E2V3 },
665 { "dpa3u", 23, PROCESSOR_V850E2V3 },
666 { "dpa4l", 24, PROCESSOR_V850E2V3 },
667 { "dpa4u", 25, PROCESSOR_V850E2V3 },
668 { "dpa5l", 26, PROCESSOR_V850E2V3 },
669 { "dpa5u", 27, PROCESSOR_V850E2V3 },
670 { "ecr", 4, PROCESSOR_ALL },
671 { "eh_base", 3, PROCESSOR_V850E2V3 },
672 { "eh_cfg", 1, PROCESSOR_V850E2V3 },
673 { "eh_reset", 2, PROCESSOR_V850E2V3 },
674 { "eiic", 13, PROCESSOR_V850E2_ALL },
675 { "eipc", 0, PROCESSOR_ALL },
676 { "eipsw", 1, PROCESSOR_ALL },
677 { "eiwr", 28, PROCESSOR_V850E2_ALL },
678 { "feic", 14, PROCESSOR_V850E2_ALL },
679 { "fepc", 2, PROCESSOR_ALL },
680 { "fepsw", 3, PROCESSOR_ALL },
681 { "fewr", 29, PROCESSOR_V850E2_ALL },
682 { "fpcc", 9, PROCESSOR_V850E2V3 },
683 { "fpcfg", 10, PROCESSOR_V850E2V3 },
684 { "fpec", 11, PROCESSOR_V850E2V3 },
685 { "fpepc", 7, PROCESSOR_V850E2V3 },
686 { "fpspc", 27, PROCESSOR_V850E2V3 },
687 { "fpsr", 6, PROCESSOR_V850E2V3 },
688 { "fpst", 8, PROCESSOR_V850E2V3 },
689 { "ipa0l", 6, PROCESSOR_V850E2V3 },
690 { "ipa0u", 7, PROCESSOR_V850E2V3 },
691 { "ipa1l", 8, PROCESSOR_V850E2V3 },
692 { "ipa1u", 9, PROCESSOR_V850E2V3 },
693 { "ipa2l", 10, PROCESSOR_V850E2V3 },
694 { "ipa2u", 11, PROCESSOR_V850E2V3 },
695 { "ipa3l", 12, PROCESSOR_V850E2V3 },
696 { "ipa3u", 13, PROCESSOR_V850E2V3 },
697 { "ipa4l", 14, PROCESSOR_V850E2V3 },
698 { "ipa4u", 15, PROCESSOR_V850E2V3 },
699 { "mca", 24, PROCESSOR_V850E2V3 },
700 { "mcc", 26, PROCESSOR_V850E2V3 },
701 { "mcr", 27, PROCESSOR_V850E2V3 },
702 { "mcs", 25, PROCESSOR_V850E2V3 },
703 { "mpc", 1, PROCESSOR_V850E2V3 },
704 { "mpm", 0, PROCESSOR_V850E2V3 },
705 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3 },
706 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3 },
707 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3 },
708 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3 },
709 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3 },
710 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3 },
711 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3 },
712 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3 },
713 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3 },
714 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3 },
715 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3 },
716 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3 },
717 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3 },
718 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3 },
719 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3 },
720 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3 },
721 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3 },
722 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3 },
723 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3 },
724 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3 },
725 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3 },
726 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3 },
727 { "mpu10_mpc", 1, PROCESSOR_V850E2V3 },
728 { "mpu10_mpm", 0, PROCESSOR_V850E2V3 },
729 { "mpu10_tid", 2, PROCESSOR_V850E2V3 },
730 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3 },
731 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3 },
732 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3 },
733 { "pid", 6, PROCESSOR_V850E2V3 },
734 { "pmcr0", 4, PROCESSOR_V850E2V3 },
735 { "pmis2", 14, PROCESSOR_V850E2V3 },
736 { "psw", 5, PROCESSOR_ALL },
737 { "scbp", 12, PROCESSOR_V850E2V3 },
738 { "sccfg", 11, PROCESSOR_V850E2V3 },
739 { "sr0", 0, PROCESSOR_ALL },
740 { "sr1", 1, PROCESSOR_ALL },
741 { "sr10", 10, PROCESSOR_ALL },
742 { "sr11", 11, PROCESSOR_ALL },
743 { "sr12", 12, PROCESSOR_ALL },
744 { "sr13", 13, PROCESSOR_ALL },
745 { "sr14", 14, PROCESSOR_ALL },
746 { "sr15", 15, PROCESSOR_ALL },
747 { "sr16", 16, PROCESSOR_ALL },
748 { "sr17", 17, PROCESSOR_ALL },
749 { "sr18", 18, PROCESSOR_ALL },
750 { "sr19", 19, PROCESSOR_ALL },
751 { "sr2", 2, PROCESSOR_ALL },
752 { "sr20", 20, PROCESSOR_ALL },
753 { "sr21", 21, PROCESSOR_ALL },
754 { "sr22", 22, PROCESSOR_ALL },
755 { "sr23", 23, PROCESSOR_ALL },
756 { "sr24", 24, PROCESSOR_ALL },
757 { "sr25", 25, PROCESSOR_ALL },
758 { "sr26", 26, PROCESSOR_ALL },
759 { "sr27", 27, PROCESSOR_ALL },
760 { "sr28", 28, PROCESSOR_ALL },
761 { "sr29", 29, PROCESSOR_ALL },
762 { "sr3", 3, PROCESSOR_ALL },
763 { "sr30", 30, PROCESSOR_ALL },
764 { "sr31", 31, PROCESSOR_ALL },
765 { "sr4", 4, PROCESSOR_ALL },
766 { "sr5", 5, PROCESSOR_ALL },
767 { "sr6", 6, PROCESSOR_ALL },
768 { "sr7", 7, PROCESSOR_ALL },
769 { "sr8", 8, PROCESSOR_ALL },
770 { "sr9", 9, PROCESSOR_ALL },
771 { "sw_base", 3, PROCESSOR_V850E2V3 },
772 { "sw_cfg", 1, PROCESSOR_V850E2V3 },
773 { "sw_ctl", 0, PROCESSOR_V850E2V3 },
774 { "tid", 2, PROCESSOR_V850E2V3 },
775 { "vmadr", 6, PROCESSOR_V850E2V3 },
776 { "vmecr", 4, PROCESSOR_V850E2V3 },
777 { "vmtid", 5, PROCESSOR_V850E2V3 },
778 { "vsadr", 2, PROCESSOR_V850E2V3 },
779 { "vsecr", 0, PROCESSOR_V850E2V3 },
780 { "vstid", 1, PROCESSOR_V850E2V3 },
781 };
782
783 #define SYSREG_NAME_CNT \
784 (sizeof (system_registers) / sizeof (struct reg_name))
785
786
787 static const struct reg_name cc_names[] =
788 {
789 { "c", 0x1, PROCESSOR_ALL },
790 { "e", 0x2, PROCESSOR_ALL },
791 { "ge", 0xe, PROCESSOR_ALL },
792 { "gt", 0xf, PROCESSOR_ALL },
793 { "h", 0xb, PROCESSOR_ALL },
794 { "l", 0x1, PROCESSOR_ALL },
795 { "le", 0x7, PROCESSOR_ALL },
796 { "lt", 0x6, PROCESSOR_ALL },
797 { "n", 0x4, PROCESSOR_ALL },
798 { "nc", 0x9, PROCESSOR_ALL },
799 { "ne", 0xa, PROCESSOR_ALL },
800 { "nh", 0x3, PROCESSOR_ALL },
801 { "nl", 0x9, PROCESSOR_ALL },
802 { "ns", 0xc, PROCESSOR_ALL },
803 { "nv", 0x8, PROCESSOR_ALL },
804 { "nz", 0xa, PROCESSOR_ALL },
805 { "p", 0xc, PROCESSOR_ALL },
806 { "s", 0x4, PROCESSOR_ALL },
807 #define COND_SA_NUM 0xd
808 { "sa", COND_SA_NUM, PROCESSOR_ALL },
809 { "t", 0x5, PROCESSOR_ALL },
810 { "v", 0x0, PROCESSOR_ALL },
811 { "z", 0x2, PROCESSOR_ALL },
812 };
813
814 #define CC_NAME_CNT \
815 (sizeof (cc_names) / sizeof (struct reg_name))
816
817 static const struct reg_name float_cc_names[] =
818 {
819 { "eq", 0x2, PROCESSOR_V850E2V3 }, /* true. */
820 { "f", 0x0, PROCESSOR_V850E2V3 }, /* true. */
821 { "ge", 0xd, PROCESSOR_V850E2V3 }, /* false. */
822 { "gl", 0xb, PROCESSOR_V850E2V3 }, /* false. */
823 { "gle", 0x9, PROCESSOR_V850E2V3 }, /* false. */
824 { "gt", 0xf, PROCESSOR_V850E2V3 }, /* false. */
825 { "le", 0xe, PROCESSOR_V850E2V3 }, /* true. */
826 { "lt", 0xc, PROCESSOR_V850E2V3 }, /* true. */
827 { "neq", 0x2, PROCESSOR_V850E2V3 }, /* false. */
828 { "nge", 0xd, PROCESSOR_V850E2V3 }, /* true. */
829 { "ngl", 0xb, PROCESSOR_V850E2V3 }, /* true. */
830 { "ngle",0x9, PROCESSOR_V850E2V3 }, /* true. */
831 { "ngt", 0xf, PROCESSOR_V850E2V3 }, /* true. */
832 { "nle", 0xe, PROCESSOR_V850E2V3 }, /* false. */
833 { "nlt", 0xc, PROCESSOR_V850E2V3 }, /* false. */
834 { "oge", 0x5, PROCESSOR_V850E2V3 }, /* false. */
835 { "ogl", 0x3, PROCESSOR_V850E2V3 }, /* false. */
836 { "ogt", 0x7, PROCESSOR_V850E2V3 }, /* false. */
837 { "ole", 0x6, PROCESSOR_V850E2V3 }, /* true. */
838 { "olt", 0x4, PROCESSOR_V850E2V3 }, /* true. */
839 { "or", 0x1, PROCESSOR_V850E2V3 }, /* false. */
840 { "seq", 0xa, PROCESSOR_V850E2V3 }, /* true. */
841 { "sf", 0x8, PROCESSOR_V850E2V3 }, /* true. */
842 { "sne", 0xa, PROCESSOR_V850E2V3 }, /* false. */
843 { "st", 0x8, PROCESSOR_V850E2V3 }, /* false. */
844 { "t", 0x0, PROCESSOR_V850E2V3 }, /* false. */
845 { "ueq", 0x3, PROCESSOR_V850E2V3 }, /* true. */
846 { "uge", 0x4, PROCESSOR_V850E2V3 }, /* false. */
847 { "ugt", 0x6, PROCESSOR_V850E2V3 }, /* false. */
848 { "ule", 0x7, PROCESSOR_V850E2V3 }, /* true. */
849 { "ult", 0x5, PROCESSOR_V850E2V3 }, /* true. */
850 { "un", 0x1, PROCESSOR_V850E2V3 }, /* true. */
851 };
852
853 #define FLOAT_CC_NAME_CNT \
854 (sizeof (float_cc_names) / sizeof (struct reg_name))
855
856 /* Do a binary search of the given register table to see if NAME is a
857 valid regiter name. Return the register number from the array on
858 success, or -1 on failure. */
859
860 static int
861 reg_name_search (const struct reg_name *regs,
862 int regcount,
863 const char *name,
864 bfd_boolean accept_numbers)
865 {
866 int middle, low, high;
867 int cmp;
868 symbolS *symbolP;
869
870 /* If the register name is a symbol, then evaluate it. */
871 if ((symbolP = symbol_find (name)) != NULL)
872 {
873 /* If the symbol is an alias for another name then use that.
874 If the symbol is an alias for a number, then return the number. */
875 if (symbol_equated_p (symbolP))
876 name
877 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol);
878 else if (accept_numbers)
879 {
880 int reg = S_GET_VALUE (symbolP);
881 return reg;
882 }
883
884 /* Otherwise drop through and try parsing name normally. */
885 }
886
887 low = 0;
888 high = regcount - 1;
889
890 do
891 {
892 middle = (low + high) / 2;
893 cmp = strcasecmp (name, regs[middle].name);
894 if (cmp < 0)
895 high = middle - 1;
896 else if (cmp > 0)
897 low = middle + 1;
898 else
899 return ((regs[middle].processors & processor_mask)
900 ? regs[middle].value
901 : -1);
902 }
903 while (low <= high);
904 return -1;
905 }
906
907 /* Summary of register_name().
908
909 in: Input_line_pointer points to 1st char of operand.
910
911 out: An expressionS.
912 The operand may have been a register: in this case, X_op == O_register,
913 X_add_number is set to the register number, and truth is returned.
914 Input_line_pointer->(next non-blank) char after operand, or is in
915 its original state. */
916
917 static bfd_boolean
918 register_name (expressionS *expressionP)
919 {
920 int reg_number;
921 char *name;
922 char *start;
923 char c;
924
925 /* Find the spelling of the operand. */
926 start = name = input_line_pointer;
927
928 c = get_symbol_end ();
929
930 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT,
931 name, FALSE);
932
933 /* Put back the delimiting char. */
934 *input_line_pointer = c;
935
936 expressionP->X_add_symbol = NULL;
937 expressionP->X_op_symbol = NULL;
938
939 /* Look to see if it's in the register table. */
940 if (reg_number >= 0)
941 {
942 expressionP->X_op = O_register;
943 expressionP->X_add_number = reg_number;
944
945 return TRUE;
946 }
947
948 /* Reset the line as if we had not done anything. */
949 input_line_pointer = start;
950
951 expressionP->X_op = O_illegal;
952
953 return FALSE;
954 }
955
956 /* Summary of system_register_name().
957
958 in: INPUT_LINE_POINTER points to 1st char of operand.
959 EXPRESSIONP points to an expression structure to be filled in.
960 ACCEPT_NUMBERS is true iff numerical register names may be used.
961
962 out: An expressionS structure in expressionP.
963 The operand may have been a register: in this case, X_op == O_register,
964 X_add_number is set to the register number, and truth is returned.
965 Input_line_pointer->(next non-blank) char after operand, or is in
966 its original state. */
967
968 static bfd_boolean
969 system_register_name (expressionS *expressionP,
970 bfd_boolean accept_numbers)
971 {
972 int reg_number;
973 char *name;
974 char *start;
975 char c;
976
977 /* Find the spelling of the operand. */
978 start = name = input_line_pointer;
979
980 c = get_symbol_end ();
981 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name,
982 accept_numbers);
983
984 /* Put back the delimiting char. */
985 *input_line_pointer = c;
986
987 if (reg_number < 0
988 && accept_numbers)
989 {
990 /* Reset input_line pointer. */
991 input_line_pointer = start;
992
993 if (ISDIGIT (*input_line_pointer))
994 {
995 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
996 }
997 }
998
999 expressionP->X_add_symbol = NULL;
1000 expressionP->X_op_symbol = NULL;
1001
1002 /* Look to see if it's in the register table. */
1003 if (reg_number >= 0)
1004 {
1005 expressionP->X_op = O_register;
1006 expressionP->X_add_number = reg_number;
1007
1008 return TRUE;
1009 }
1010
1011 /* Reset the line as if we had not done anything. */
1012 input_line_pointer = start;
1013
1014 expressionP->X_op = O_illegal;
1015
1016 return FALSE;
1017 }
1018
1019 /* Summary of cc_name().
1020
1021 in: INPUT_LINE_POINTER points to 1st char of operand.
1022
1023 out: An expressionS.
1024 The operand may have been a register: in this case, X_op == O_register,
1025 X_add_number is set to the register number, and truth is returned.
1026 Input_line_pointer->(next non-blank) char after operand, or is in
1027 its original state. */
1028
1029 static bfd_boolean
1030 cc_name (expressionS *expressionP,
1031 bfd_boolean accept_numbers)
1032 {
1033 int reg_number;
1034 char *name;
1035 char *start;
1036 char c;
1037
1038 /* Find the spelling of the operand. */
1039 start = name = input_line_pointer;
1040
1041 c = get_symbol_end ();
1042 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers);
1043
1044 /* Put back the delimiting char. */
1045 *input_line_pointer = c;
1046
1047 if (reg_number < 0
1048 && accept_numbers)
1049 {
1050 /* Reset input_line pointer. */
1051 input_line_pointer = start;
1052
1053 if (ISDIGIT (*input_line_pointer))
1054 {
1055 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1056 }
1057 }
1058
1059 expressionP->X_add_symbol = NULL;
1060 expressionP->X_op_symbol = NULL;
1061
1062 /* Look to see if it's in the register table. */
1063 if (reg_number >= 0)
1064 {
1065 expressionP->X_op = O_constant;
1066 expressionP->X_add_number = reg_number;
1067
1068 return TRUE;
1069 }
1070
1071 /* Reset the line as if we had not done anything. */
1072 input_line_pointer = start;
1073
1074 expressionP->X_op = O_illegal;
1075 expressionP->X_add_number = 0;
1076
1077 return FALSE;
1078 }
1079
1080 static bfd_boolean
1081 float_cc_name (expressionS *expressionP,
1082 bfd_boolean accept_numbers)
1083 {
1084 int reg_number;
1085 char *name;
1086 char *start;
1087 char c;
1088
1089 /* Find the spelling of the operand. */
1090 start = name = input_line_pointer;
1091
1092 c = get_symbol_end ();
1093 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers);
1094
1095 /* Put back the delimiting char. */
1096 *input_line_pointer = c;
1097
1098 if (reg_number < 0
1099 && accept_numbers)
1100 {
1101 /* Reset input_line pointer. */
1102 input_line_pointer = start;
1103
1104 if (ISDIGIT (*input_line_pointer))
1105 {
1106 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1107 }
1108 }
1109
1110 expressionP->X_add_symbol = NULL;
1111 expressionP->X_op_symbol = NULL;
1112
1113 /* Look to see if it's in the register table. */
1114 if (reg_number >= 0)
1115 {
1116 expressionP->X_op = O_constant;
1117 expressionP->X_add_number = reg_number;
1118
1119 return TRUE;
1120 }
1121
1122 /* Reset the line as if we had not done anything. */
1123 input_line_pointer = start;
1124
1125 expressionP->X_op = O_illegal;
1126 expressionP->X_add_number = 0;
1127
1128 return FALSE;
1129 }
1130
1131 static void
1132 skip_white_space (void)
1133 {
1134 while (*input_line_pointer == ' '
1135 || *input_line_pointer == '\t')
1136 ++input_line_pointer;
1137 }
1138
1139 /* Summary of parse_register_list ().
1140
1141 in: INPUT_LINE_POINTER points to 1st char of a list of registers.
1142 INSN is the partially constructed instruction.
1143 OPERAND is the operand being inserted.
1144
1145 out: NULL if the parse completed successfully, otherwise a
1146 pointer to an error message is returned. If the parse
1147 completes the correct bit fields in the instruction
1148 will be filled in.
1149
1150 Parses register lists with the syntax:
1151
1152 { rX }
1153 { rX, rY }
1154 { rX - rY }
1155 { rX - rY, rZ }
1156 etc
1157
1158 and also parses constant expressions whoes bits indicate the
1159 registers in the lists. The LSB in the expression refers to
1160 the lowest numbered permissible register in the register list,
1161 and so on upwards. System registers are considered to be very
1162 high numbers. */
1163
1164 static char *
1165 parse_register_list (unsigned long *insn,
1166 const struct v850_operand *operand)
1167 {
1168 static int type1_regs[32] =
1169 {
1170 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1171 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
1172 };
1173
1174 int *regs;
1175 expressionS exp;
1176
1177 /* Select a register array to parse. */
1178 switch (operand->shift)
1179 {
1180 case 0xffe00001: regs = type1_regs; break;
1181 default:
1182 as_bad (_("unknown operand shift: %x\n"), operand->shift);
1183 return _("internal failure in parse_register_list");
1184 }
1185
1186 skip_white_space ();
1187
1188 /* If the expression starts with a curly brace it is a register list.
1189 Otherwise it is a constant expression, whoes bits indicate which
1190 registers are to be included in the list. */
1191 if (*input_line_pointer != '{')
1192 {
1193 int reg;
1194 int i;
1195
1196 expression (&exp);
1197
1198 if (exp.X_op != O_constant)
1199 return _("constant expression or register list expected");
1200
1201 if (regs == type1_regs)
1202 {
1203 if (exp.X_add_number & 0xFFFFF000)
1204 return _("high bits set in register list expression");
1205
1206 for (reg = 20; reg < 32; reg++)
1207 if (exp.X_add_number & (1 << (reg - 20)))
1208 {
1209 for (i = 0; i < 32; i++)
1210 if (regs[i] == reg)
1211 *insn |= (1 << i);
1212 }
1213 }
1214
1215 return NULL;
1216 }
1217
1218 input_line_pointer++;
1219
1220 /* Parse the register list until a terminator (closing curly brace or
1221 new-line) is found. */
1222 for (;;)
1223 {
1224 skip_white_space ();
1225
1226 if (register_name (&exp))
1227 {
1228 int i;
1229
1230 /* Locate the given register in the list, and if it is there,
1231 insert the corresponding bit into the instruction. */
1232 for (i = 0; i < 32; i++)
1233 {
1234 if (regs[i] == exp.X_add_number)
1235 {
1236 *insn |= (1 << i);
1237 break;
1238 }
1239 }
1240
1241 if (i == 32)
1242 return _("illegal register included in list");
1243 }
1244 else if (system_register_name (&exp, TRUE))
1245 {
1246 if (regs == type1_regs)
1247 {
1248 return _("system registers cannot be included in list");
1249 }
1250 }
1251
1252 if (*input_line_pointer == '}')
1253 {
1254 input_line_pointer++;
1255 break;
1256 }
1257 else if (*input_line_pointer == ',')
1258 {
1259 input_line_pointer++;
1260 continue;
1261 }
1262 else if (*input_line_pointer == '-')
1263 {
1264 /* We have encountered a range of registers: rX - rY. */
1265 int j;
1266 expressionS exp2;
1267
1268 /* Skip the dash. */
1269 ++input_line_pointer;
1270
1271 /* Get the second register in the range. */
1272 if (! register_name (&exp2))
1273 {
1274 return _("second register should follow dash in register list");
1275 }
1276
1277 if (exp.X_add_number > exp2.X_add_number)
1278 {
1279 return _("second register should greater tahn first register");
1280 }
1281
1282 /* Add the rest of the registers in the range. */
1283 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++)
1284 {
1285 int i;
1286
1287 /* Locate the given register in the list, and if it is there,
1288 insert the corresponding bit into the instruction. */
1289 for (i = 0; i < 32; i++)
1290 {
1291 if (regs[i] == j)
1292 {
1293 *insn |= (1 << i);
1294 break;
1295 }
1296 }
1297
1298 if (i == 32)
1299 return _("illegal register included in list");
1300 }
1301
1302 exp = exp2;
1303 }
1304 else
1305 break;
1306 }
1307
1308 return NULL;
1309 }
1310
1311 const char *md_shortopts = "m:";
1312
1313 struct option md_longopts[] =
1314 {
1315 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE)
1316 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22},
1317 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1)
1318 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
1319 {NULL, no_argument, NULL, 0}
1320 };
1321
1322 size_t md_longopts_size = sizeof (md_longopts);
1323
1324 void
1325 md_show_usage (FILE *stream)
1326 {
1327 fprintf (stream, _(" V850 options:\n"));
1328 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n"));
1329 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"));
1330 fprintf (stream, _(" -mv850 The code is targeted at the v850\n"));
1331 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n"));
1332 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n"));
1333 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n"));
1334 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n"));
1335 fprintf (stream, _(" -mrelax Enable relaxation\n"));
1336 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n"));
1337 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n"));
1338 fprintf (stream, _(" -mextension enable extension opcode support\n"));
1339 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n"));
1340 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n"));
1341 }
1342
1343 int
1344 md_parse_option (int c, char *arg)
1345 {
1346 if (c != 'm')
1347 {
1348 switch (c)
1349 {
1350 case OPTION_DISP_SIZE_DEFAULT_22:
1351 default_disp_size = 22;
1352 return 1;
1353
1354 case OPTION_DISP_SIZE_DEFAULT_32:
1355 default_disp_size = 32;
1356 return 1;
1357 }
1358 return 0;
1359 }
1360
1361 if (strcmp (arg, "warn-signed-overflow") == 0)
1362 warn_signed_overflows = TRUE;
1363
1364 else if (strcmp (arg, "warn-unsigned-overflow") == 0)
1365 warn_unsigned_overflows = TRUE;
1366
1367 else if (strcmp (arg, "v850") == 0)
1368 {
1369 machine = 0;
1370 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
1371 }
1372 else if (strcmp (arg, "v850e") == 0)
1373 {
1374 machine = bfd_mach_v850e;
1375 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
1376 }
1377 else if (strcmp (arg, "v850e1") == 0)
1378 {
1379 machine = bfd_mach_v850e1;
1380 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
1381 }
1382 else if (strcmp (arg, "v850e2") == 0)
1383 {
1384 machine = bfd_mach_v850e2;
1385 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1386 }
1387 else if (strcmp (arg, "v850e2v3") == 0)
1388 {
1389 machine = bfd_mach_v850e2v3;
1390 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1391 }
1392 else if (strcmp (arg, "extension") == 0)
1393 {
1394 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS;;
1395 }
1396 else if (strcmp (arg, "no-bcond17") == 0)
1397 {
1398 no_bcond17 = 1;
1399 }
1400 else if (strcmp (arg, "no-stld23") == 0)
1401 {
1402 no_stld23 = 1;
1403 }
1404 else if (strcmp (arg, "relax") == 0)
1405 v850_relax = 1;
1406 else
1407 return 0;
1408
1409 return 1;
1410 }
1411
1412 symbolS *
1413 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
1414 {
1415 return 0;
1416 }
1417
1418 char *
1419 md_atof (int type, char *litp, int *sizep)
1420 {
1421 return ieee_md_atof (type, litp, sizep, FALSE);
1422 }
1423
1424 /* Very gross. */
1425
1426 void
1427 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1428 asection *sec,
1429 fragS *fragP)
1430 {
1431 union u
1432 {
1433 bfd_reloc_code_real_type fx_r_type;
1434 char * fr_opcode;
1435 }
1436 opcode_converter;
1437 subseg_change (sec, 0);
1438
1439 opcode_converter.fr_opcode = fragP->fr_opcode;
1440
1441 subseg_change (sec, 0);
1442
1443 /* In range conditional or unconditional branch. */
1444 if (fragP->fr_subtype == SUBYPTE_COND_9_22
1445 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22
1446 || fragP->fr_subtype == SUBYPTE_COND_9_22_32
1447 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32
1448 || fragP->fr_subtype == SUBYPTE_COND_9_17_22
1449 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32
1450 || fragP->fr_subtype == SUBYPTE_SA_9_22
1451 || fragP->fr_subtype == SUBYPTE_SA_9_22_32
1452 || fragP->fr_subtype == SUBYPTE_SA_9_17_22
1453 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32)
1454
1455 {
1456 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
1457 fragP->fr_offset, 1,
1458 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
1459 fragP->fr_fix += 2;
1460 }
1461 /* V850e2r-v3 17bit conditional branch. */
1462 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1
1463 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1
1464 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1
1465 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1)
1466 {
1467 unsigned char *buffer =
1468 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1469
1470 buffer[0] &= 0x0f; /* Use condition. */
1471 buffer[0] |= 0xe0;
1472 buffer[1] = 0x07;
1473
1474 /* Now create the unconditional branch + fixup to the final
1475 target. */
1476 md_number_to_chars ((char *) buffer + 2, 0x0001, 2);
1477 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1478 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL);
1479 fragP->fr_fix += 4;
1480 }
1481 /* Out of range conditional branch. Emit a branch around a 22bit jump. */
1482 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1
1483 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1
1484 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2
1485 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2)
1486 {
1487 unsigned char *buffer =
1488 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1489
1490 /* Reverse the condition of the first branch. */
1491 buffer[0] ^= 0x08;
1492 /* Mask off all the displacement bits. */
1493 buffer[0] &= 0x8f;
1494 buffer[1] &= 0x07;
1495 /* Now set the displacement bits so that we branch
1496 around the unconditional branch. */
1497 buffer[0] |= 0x30;
1498
1499 /* Now create the unconditional branch + fixup to the final
1500 target. */
1501 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4);
1502 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol,
1503 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
1504 fragP->fr_fix += 6;
1505 }
1506 /* Out of range conditional branch. Emit a branch around a 32bit jump. */
1507 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2
1508 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3)
1509 {
1510 unsigned char *buffer =
1511 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1512
1513 /* Reverse the condition of the first branch. */
1514 buffer[0] ^= 0x08;
1515 /* Mask off all the displacement bits. */
1516 buffer[0] &= 0x8f;
1517 buffer[1] &= 0x07;
1518 /* Now set the displacement bits so that we branch
1519 around the unconditional branch. */
1520 buffer[0] |= 0x40;
1521
1522 /* Now create the unconditional branch + fixup to the final
1523 target. */
1524 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2);
1525 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1526 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1527 fragP->fr_fix += 8;
1528 }
1529 /* Out of range unconditional branch. Emit a 22bit jump. */
1530 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1
1531 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1)
1532 {
1533 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4);
1534 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1535 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
1536 fragP->fr_fix += 4;
1537 }
1538 /* Out of range unconditional branch. Emit a 32bit jump. */
1539 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2)
1540 {
1541 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2);
1542 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1543 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1544 fragP->fr_fix += 6;
1545 }
1546 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */
1547 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1
1548 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1
1549 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2
1550 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2)
1551 {
1552 unsigned char *buffer =
1553 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1554
1555 /* bsa .+4 */
1556 buffer[0] &= 0x8f;
1557 buffer[0] |= 0x20;
1558 buffer[1] &= 0x07;
1559
1560 /* br .+6 */
1561 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2);
1562
1563 /* Now create the unconditional branch + fixup to the final
1564 target. */
1565 /* jr SYM */
1566 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4);
1567 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1568 fragP->fr_offset, 1,
1569 BFD_RELOC_V850_22_PCREL);
1570 fragP->fr_fix += 8;
1571 }
1572 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */
1573 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2
1574 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3)
1575 {
1576 unsigned char *buffer =
1577 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1578
1579 /* bsa .+2 */
1580 buffer[0] &= 0x8f;
1581 buffer[0] |= 0x20;
1582 buffer[1] &= 0x07;
1583
1584 /* br .+8 */
1585 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2);
1586
1587 /* Now create the unconditional branch + fixup to the final
1588 target. */
1589 /* jr SYM */
1590 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2);
1591 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol,
1592 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1593
1594 fragP->fr_fix += 10;
1595 }
1596 else
1597 abort ();
1598 }
1599
1600 valueT
1601 md_section_align (asection *seg, valueT addr)
1602 {
1603 int align = bfd_get_section_alignment (stdoutput, seg);
1604 return ((addr + (1 << align) - 1) & (-1 << align));
1605 }
1606
1607 void
1608 md_begin (void)
1609 {
1610 char *prev_name = "";
1611 const struct v850_opcode *op;
1612
1613 if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0)
1614 {
1615 if (machine == -1)
1616 machine = bfd_mach_v850e2v3;
1617
1618 if (!processor_mask)
1619 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1620 }
1621 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0)
1622 {
1623 if (machine == -1)
1624 machine = bfd_mach_v850e2;
1625
1626 if (!processor_mask)
1627 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1628 }
1629 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0)
1630 {
1631 if (machine == -1)
1632 machine = bfd_mach_v850e1;
1633
1634 if (!processor_mask)
1635 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
1636 }
1637 else if (strncmp (TARGET_CPU, "v850e", 5) == 0)
1638 {
1639 if (machine == -1)
1640 machine = bfd_mach_v850e;
1641
1642 if (!processor_mask)
1643 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
1644 }
1645 else if (strncmp (TARGET_CPU, "v850", 4) == 0)
1646 {
1647 if (machine == -1)
1648 machine = 0;
1649
1650 if (!processor_mask)
1651 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
1652 }
1653 else
1654 /* xgettext:c-format */
1655 as_bad (_("Unable to determine default target processor from string: %s"),
1656 TARGET_CPU);
1657
1658 v850_hash = hash_new ();
1659
1660 /* Insert unique names into hash table. The V850 instruction set
1661 has many identical opcode names that have different opcodes based
1662 on the operands. This hash table then provides a quick index to
1663 the first opcode with a particular name in the opcode table. */
1664 op = v850_opcodes;
1665 while (op->name)
1666 {
1667 if (strcmp (prev_name, op->name))
1668 {
1669 prev_name = (char *) op->name;
1670 hash_insert (v850_hash, op->name, (char *) op);
1671 }
1672 op++;
1673 }
1674
1675 v850_seg_table[BSS_SECTION].s = bss_section;
1676 bfd_set_arch_mach (stdoutput, TARGET_ARCH, machine);
1677 }
1678
1679
1680 static bfd_reloc_code_real_type
1681 handle_hi016 (const struct v850_operand *operand, const char **errmsg)
1682 {
1683 if (operand == NULL)
1684 return BFD_RELOC_HI16;
1685
1686 if (operand->default_reloc == BFD_RELOC_HI16)
1687 return BFD_RELOC_HI16;
1688
1689 if (operand->default_reloc == BFD_RELOC_HI16_S)
1690 return BFD_RELOC_HI16;
1691
1692 if (operand->default_reloc == BFD_RELOC_16)
1693 return BFD_RELOC_HI16;
1694
1695 *errmsg = _("hi0() relocation used on an instruction which does "
1696 "not support it");
1697 return BFD_RELOC_64; /* Used to indicate an error condition. */
1698 }
1699
1700 static bfd_reloc_code_real_type
1701 handle_hi16 (const struct v850_operand *operand, const char **errmsg)
1702 {
1703 if (operand == NULL)
1704 return BFD_RELOC_HI16_S;
1705
1706 if (operand->default_reloc == BFD_RELOC_HI16_S)
1707 return BFD_RELOC_HI16_S;
1708
1709 if (operand->default_reloc == BFD_RELOC_HI16)
1710 return BFD_RELOC_HI16_S;
1711
1712 if (operand->default_reloc == BFD_RELOC_16)
1713 return BFD_RELOC_HI16_S;
1714
1715 *errmsg = _("hi() relocation used on an instruction which does "
1716 "not support it");
1717 return BFD_RELOC_64; /* Used to indicate an error condition. */
1718 }
1719
1720 static bfd_reloc_code_real_type
1721 handle_lo16 (const struct v850_operand *operand, const char **errmsg)
1722 {
1723 if (operand == NULL)
1724 return BFD_RELOC_LO16;
1725
1726 if (operand->default_reloc == BFD_RELOC_LO16)
1727 return BFD_RELOC_LO16;
1728
1729 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
1730 return BFD_RELOC_V850_LO16_SPLIT_OFFSET;
1731
1732 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
1733 return BFD_RELOC_V850_LO16_S1;
1734
1735 if (operand->default_reloc == BFD_RELOC_16)
1736 return BFD_RELOC_LO16;
1737
1738 *errmsg = _("lo() relocation used on an instruction which does "
1739 "not support it");
1740 return BFD_RELOC_64; /* Used to indicate an error condition. */
1741 }
1742
1743 static bfd_reloc_code_real_type
1744 handle_ctoff (const struct v850_operand *operand, const char **errmsg)
1745 {
1746 if (operand == NULL)
1747 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
1748
1749 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET)
1750 return operand->default_reloc;
1751
1752 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
1753 return BFD_RELOC_V850_CALLT_15_16_OFFSET;
1754
1755 if (operand->default_reloc == BFD_RELOC_16)
1756 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
1757
1758 *errmsg = _("ctoff() relocation used on an instruction which does not support it");
1759 return BFD_RELOC_64; /* Used to indicate an error condition. */
1760 }
1761
1762 static bfd_reloc_code_real_type
1763 handle_sdaoff (const struct v850_operand *operand, const char **errmsg)
1764 {
1765 if (operand == NULL)
1766 return BFD_RELOC_V850_SDA_16_16_OFFSET;
1767
1768 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
1769 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET;
1770
1771 if (operand->default_reloc == BFD_RELOC_16)
1772 return BFD_RELOC_V850_SDA_16_16_OFFSET;
1773
1774 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
1775 return BFD_RELOC_V850_SDA_15_16_OFFSET;
1776
1777 *errmsg = _("sdaoff() relocation used on an instruction which does not support it");
1778 return BFD_RELOC_64; /* Used to indicate an error condition. */
1779 }
1780
1781 static bfd_reloc_code_real_type
1782 handle_zdaoff (const struct v850_operand *operand, const char **errmsg)
1783 {
1784 if (operand == NULL)
1785 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
1786
1787 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
1788 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET;
1789
1790 if (operand->default_reloc == BFD_RELOC_16)
1791 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
1792
1793 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
1794 return BFD_RELOC_V850_ZDA_15_16_OFFSET;
1795
1796 *errmsg = _("zdaoff() relocation used on an instruction which does not support it");
1797 return BFD_RELOC_64; /* Used to indicate an error condition. */
1798 }
1799
1800 static bfd_reloc_code_real_type
1801 handle_tdaoff (const struct v850_operand *operand, const char **errmsg)
1802 {
1803 if (operand == NULL)
1804 /* Data item, not an instruction. */
1805 return BFD_RELOC_V850_TDA_16_16_OFFSET;
1806
1807 switch (operand->default_reloc)
1808 {
1809 /* sld.hu, operand: D5-4. */
1810 case BFD_RELOC_V850_TDA_4_5_OFFSET:
1811 /* sld.bu, operand: D4. */
1812 case BFD_RELOC_V850_TDA_4_4_OFFSET:
1813 /* sld.w/sst.w, operand: D8_6. */
1814 case BFD_RELOC_V850_TDA_6_8_OFFSET:
1815 /* sld.h/sst.h, operand: D8_7. */
1816 case BFD_RELOC_V850_TDA_7_8_OFFSET:
1817 /* sld.b/sst.b, operand: D7. */
1818 case BFD_RELOC_V850_TDA_7_7_OFFSET:
1819 return operand->default_reloc;
1820 default:
1821 break;
1822 }
1823
1824 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16)
1825 /* set1 & chums, operands: D16. */
1826 return BFD_RELOC_V850_TDA_16_16_OFFSET;
1827
1828 *errmsg = _("tdaoff() relocation used on an instruction which does not support it");
1829 /* Used to indicate an error condition. */
1830 return BFD_RELOC_64;
1831 }
1832
1833 /* Warning: The code in this function relies upon the definitions
1834 in the v850_operands[] array (defined in opcodes/v850-opc.c)
1835 matching the hard coded values contained herein. */
1836
1837 static bfd_reloc_code_real_type
1838 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg)
1839 {
1840 bfd_boolean paren_skipped = FALSE;
1841
1842 /* Skip leading opening parenthesis. */
1843 if (*input_line_pointer == '(')
1844 {
1845 ++input_line_pointer;
1846 paren_skipped = TRUE;
1847 }
1848
1849 #define CHECK_(name, reloc) \
1850 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \
1851 { \
1852 input_line_pointer += strlen (name); \
1853 return reloc; \
1854 }
1855
1856 CHECK_ ("hi0", handle_hi016(operand, errmsg) );
1857 CHECK_ ("hi", handle_hi16(operand, errmsg) );
1858 CHECK_ ("lo", handle_lo16 (operand, errmsg) );
1859 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg));
1860 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg));
1861 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg));
1862 CHECK_ ("hilo", BFD_RELOC_32);
1863 CHECK_ ("lo23", BFD_RELOC_V850_23);
1864 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) );
1865
1866 /* Restore skipped parenthesis. */
1867 if (paren_skipped)
1868 --input_line_pointer;
1869
1870 return BFD_RELOC_UNUSED;
1871 }
1872
1873 /* Insert an operand value into an instruction. */
1874
1875 static unsigned long
1876 v850_insert_operand (unsigned long insn,
1877 const struct v850_operand *operand,
1878 offsetT val,
1879 const char **errmsg)
1880 {
1881 if (operand->insert)
1882 {
1883 const char *message = NULL;
1884
1885 insn = operand->insert (insn, val, &message);
1886 if (message != NULL)
1887 {
1888 if ((operand->flags & V850_OPERAND_SIGNED)
1889 && ! warn_signed_overflows
1890 && v850_msg_is_out_of_range (message))
1891 {
1892 /* Skip warning... */
1893 }
1894 else if ((operand->flags & V850_OPERAND_SIGNED) == 0
1895 && ! warn_unsigned_overflows
1896 && v850_msg_is_out_of_range (message))
1897 {
1898 /* Skip warning... */
1899 }
1900 else
1901 {
1902 if (errmsg != NULL)
1903 *errmsg = message;
1904 }
1905 }
1906 }
1907 else if (operand->bits == -1
1908 || operand->flags & V850E_IMMEDIATE16
1909 || operand->flags & V850E_IMMEDIATE23
1910 || operand->flags & V850E_IMMEDIATE32)
1911 {
1912 abort ();
1913 }
1914 else
1915 {
1916 if (operand->bits < 32)
1917 {
1918 long min, max;
1919
1920 if ((operand->flags & V850_OPERAND_SIGNED) != 0)
1921 {
1922 if (! warn_signed_overflows)
1923 max = (1 << operand->bits) - 1;
1924 else
1925 max = (1 << (operand->bits - 1)) - 1;
1926
1927 min = -(1 << (operand->bits - 1));
1928 }
1929 else
1930 {
1931 max = (1 << operand->bits) - 1;
1932
1933 if (! warn_unsigned_overflows)
1934 min = -(1 << (operand->bits - 1));
1935 else
1936 min = 0;
1937 }
1938
1939 /* Some people write constants with the sign extension done by
1940 hand but only up to 32 bits. This shouldn't really be valid,
1941 but, to permit this code to assemble on a 64-bit host, we
1942 sign extend the 32-bit value to 64 bits if so doing makes the
1943 value valid. */
1944 if (val > max
1945 && (offsetT) (val - 0x80000000 - 0x80000000) >= min
1946 && (offsetT) (val - 0x80000000 - 0x80000000) <= max)
1947 val = val - 0x80000000 - 0x80000000;
1948
1949 /* Similarly, people write expressions like ~(1<<15), and expect
1950 this to be OK for a 32-bit unsigned value. */
1951 else if (val < min
1952 && (offsetT) (val + 0x80000000 + 0x80000000) >= min
1953 && (offsetT) (val + 0x80000000 + 0x80000000) <= max)
1954 val = val + 0x80000000 + 0x80000000;
1955
1956 else if (val < (offsetT) min || val > (offsetT) max)
1957 {
1958 char buf [128];
1959
1960 /* Restore min and mix to expected values for decimal ranges. */
1961 if ((operand->flags & V850_OPERAND_SIGNED)
1962 && ! warn_signed_overflows)
1963 max = (1 << (operand->bits - 1)) - 1;
1964
1965 if (! (operand->flags & V850_OPERAND_SIGNED)
1966 && ! warn_unsigned_overflows)
1967 min = 0;
1968
1969 sprintf (buf, _("operand out of range (%d is not between %d and %d)"),
1970 (int) val, (int) min, (int) max);
1971 *errmsg = buf;
1972 }
1973
1974 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift);
1975 }
1976 else
1977 {
1978 insn |= (((long) val) << operand->shift);
1979 }
1980 }
1981
1982 return insn;
1983 }
1984 \f
1985 static char copy_of_instruction[128];
1986
1987 void
1988 md_assemble (char *str)
1989 {
1990 char *s;
1991 char *start_of_operands;
1992 struct v850_opcode *opcode;
1993 struct v850_opcode *next_opcode;
1994 const unsigned char *opindex_ptr;
1995 int next_opindex;
1996 int relaxable = 0;
1997 unsigned long insn;
1998 unsigned long insn_size;
1999 char *f;
2000 int i;
2001 int match;
2002 bfd_boolean extra_data_after_insn = FALSE;
2003 unsigned extra_data_len = 0;
2004 unsigned long extra_data = 0;
2005 char *saved_input_line_pointer;
2006 char most_match_errmsg[1024];
2007 int most_match_count = -1;
2008
2009 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1);
2010 most_match_errmsg[0] = 0;
2011
2012 /* Get the opcode. */
2013 for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
2014 continue;
2015
2016 if (*s != '\0')
2017 *s++ = '\0';
2018
2019 /* Find the first opcode with the proper name. */
2020 opcode = (struct v850_opcode *) hash_find (v850_hash, str);
2021 if (opcode == NULL)
2022 {
2023 /* xgettext:c-format */
2024 as_bad (_("Unrecognized opcode: `%s'"), str);
2025 ignore_rest_of_line ();
2026 return;
2027 }
2028
2029 str = s;
2030 while (ISSPACE (*str))
2031 ++str;
2032
2033 start_of_operands = str;
2034
2035 saved_input_line_pointer = input_line_pointer;
2036
2037 for (;;)
2038 {
2039 const char *errmsg = NULL;
2040 const char *warningmsg = NULL;
2041
2042 match = 0;
2043 opindex_ptr = opcode->operands;
2044
2045 if (no_stld23)
2046 {
2047 if ((strncmp (opcode->name, "st.", 3) == 0
2048 && v850_operands[opcode->operands[1]].bits == 23)
2049 || (strncmp (opcode->name, "ld.", 3) == 0
2050 && v850_operands[opcode->operands[0]].bits == 23))
2051 {
2052 errmsg = _("st/ld offset 23 instruction was disabled .");
2053 goto error;
2054 }
2055 }
2056
2057 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0
2058 || (((opcode->processors & ~PROCESSOR_MASK) != 0)
2059 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0)))
2060 {
2061 errmsg = _("Target processor does not support this instruction.");
2062 goto error;
2063 }
2064
2065 relaxable = 0;
2066 fc = 0;
2067 next_opindex = 0;
2068 insn = opcode->opcode;
2069 extra_data_len = 0;
2070 extra_data_after_insn = FALSE;
2071
2072 input_line_pointer = str = start_of_operands;
2073
2074 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
2075 {
2076 const struct v850_operand *operand;
2077 char *hold;
2078 expressionS ex;
2079 bfd_reloc_code_real_type reloc;
2080
2081 if (next_opindex == 0)
2082 operand = &v850_operands[*opindex_ptr];
2083 else
2084 {
2085 operand = &v850_operands[next_opindex];
2086 next_opindex = 0;
2087 }
2088
2089 errmsg = NULL;
2090
2091 while (*str == ' ')
2092 ++str;
2093
2094 if (operand->flags & V850_OPERAND_BANG
2095 && *str == '!')
2096 ++str;
2097 else if (operand->flags & V850_OPERAND_PERCENT
2098 && *str == '%')
2099 ++str;
2100
2101 if (*str == ',' || *str == '[' || *str == ']')
2102 ++str;
2103
2104 while (*str == ' ')
2105 ++str;
2106
2107 if (operand->flags & V850_OPERAND_RELAX)
2108 relaxable = 1;
2109
2110 /* Gather the operand. */
2111 hold = input_line_pointer;
2112 input_line_pointer = str;
2113
2114 /* lo(), hi(), hi0(), etc... */
2115 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_UNUSED)
2116 {
2117 /* This is a fake reloc, used to indicate an error condition. */
2118 if (reloc == BFD_RELOC_64)
2119 {
2120 /* match = 1; */
2121 goto error;
2122 }
2123
2124 expression (&ex);
2125
2126 if (ex.X_op == O_constant)
2127 {
2128 switch (reloc)
2129 {
2130 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
2131 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
2132 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
2133 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]"
2134 and the like. */
2135 /* Fall through. */
2136
2137 case BFD_RELOC_LO16:
2138 case BFD_RELOC_V850_LO16_S1:
2139 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
2140 {
2141 /* Truncate, then sign extend the value. */
2142 ex.X_add_number = SEXT16 (ex.X_add_number);
2143 break;
2144 }
2145
2146 case BFD_RELOC_HI16:
2147 {
2148 /* Truncate, then sign extend the value. */
2149 ex.X_add_number = SEXT16 (ex.X_add_number >> 16);
2150 break;
2151 }
2152
2153 case BFD_RELOC_HI16_S:
2154 {
2155 /* Truncate, then sign extend the value. */
2156 int temp = (ex.X_add_number >> 16) & 0xffff;
2157
2158 temp += (ex.X_add_number >> 15) & 1;
2159
2160 ex.X_add_number = SEXT16 (temp);
2161 break;
2162 }
2163
2164 case BFD_RELOC_V850_23:
2165 if ((operand->flags & V850E_IMMEDIATE23) == 0)
2166 {
2167 errmsg = _("immediate operand is too large");
2168 goto error;
2169 }
2170 break;
2171
2172 case BFD_RELOC_32:
2173 case BFD_RELOC_V850_32_ABS:
2174 case BFD_RELOC_V850_32_PCREL:
2175 if ((operand->flags & V850E_IMMEDIATE32) == 0)
2176 {
2177 errmsg = _("immediate operand is too large");
2178 goto error;
2179 }
2180
2181 break;
2182
2183 default:
2184 fprintf (stderr, "reloc: %d\n", reloc);
2185 as_bad (_("AAARG -> unhandled constant reloc"));
2186 break;
2187 }
2188
2189 if (operand->flags & V850E_IMMEDIATE32)
2190 {
2191 extra_data_after_insn = TRUE;
2192 extra_data_len = 4;
2193 extra_data = 0;
2194 }
2195 else if (operand->flags & V850E_IMMEDIATE23)
2196 {
2197 if (reloc != BFD_RELOC_V850_23)
2198 {
2199 errmsg = _("immediate operand is too large");
2200 goto error;
2201 }
2202 extra_data_after_insn = TRUE;
2203 extra_data_len = 2;
2204 extra_data = 0;
2205 }
2206 else if ((operand->flags & V850E_IMMEDIATE16)
2207 || (operand->flags & V850E_IMMEDIATE16HI))
2208 {
2209 if (operand->flags & V850E_IMMEDIATE16HI
2210 && reloc != BFD_RELOC_HI16
2211 && reloc != BFD_RELOC_HI16_S)
2212 {
2213 errmsg = _("immediate operand is too large");
2214 goto error;
2215 }
2216 else if (operand->flags & V850E_IMMEDIATE16
2217 && reloc != BFD_RELOC_LO16)
2218 {
2219 errmsg = _("immediate operand is too large");
2220 goto error;
2221 }
2222
2223 extra_data_after_insn = TRUE;
2224 extra_data_len = 2;
2225 extra_data = 0;
2226 }
2227
2228 if (fc > MAX_INSN_FIXUPS)
2229 as_fatal (_("too many fixups"));
2230
2231 fixups[fc].exp = ex;
2232 fixups[fc].opindex = *opindex_ptr;
2233 fixups[fc].reloc = reloc;
2234 fc++;
2235 }
2236 else /* ex.X_op != O_constant. */
2237 {
2238 if ((reloc == BFD_RELOC_32
2239 || reloc == BFD_RELOC_V850_32_ABS
2240 || reloc == BFD_RELOC_V850_32_PCREL)
2241 && operand->bits < 32)
2242 {
2243 errmsg = _("immediate operand is too large");
2244 goto error;
2245 }
2246 else if (reloc == BFD_RELOC_V850_23
2247 && (operand->flags & V850E_IMMEDIATE23) == 0)
2248 {
2249 errmsg = _("immediate operand is too large");
2250 goto error;
2251 }
2252 else if ((reloc == BFD_RELOC_HI16
2253 || reloc == BFD_RELOC_HI16_S)
2254 && operand->bits < 16)
2255 {
2256 errmsg = _("immediate operand is too large");
2257 goto error;
2258 }
2259
2260 if (operand->flags & V850E_IMMEDIATE32)
2261 {
2262 extra_data_after_insn = TRUE;
2263 extra_data_len = 4;
2264 extra_data = 0;
2265 }
2266 else if (operand->flags & V850E_IMMEDIATE23)
2267 {
2268 if (reloc != BFD_RELOC_V850_23)
2269 {
2270 errmsg = _("immediate operand is too large");
2271 goto error;
2272 }
2273 extra_data_after_insn = TRUE;
2274 extra_data_len = 2;
2275 extra_data = 0;
2276 }
2277 else if ((operand->flags & V850E_IMMEDIATE16)
2278 || (operand->flags & V850E_IMMEDIATE16HI))
2279 {
2280 if (operand->flags & V850E_IMMEDIATE16HI
2281 && reloc != BFD_RELOC_HI16
2282 && reloc != BFD_RELOC_HI16_S)
2283 {
2284 errmsg = _("immediate operand is too large");
2285 goto error;
2286 }
2287 else if (operand->flags & V850E_IMMEDIATE16
2288 && reloc != BFD_RELOC_LO16)
2289 {
2290 errmsg = _("immediate operand is too large");
2291 goto error;
2292 }
2293
2294 extra_data_after_insn = TRUE;
2295 extra_data_len = 2;
2296 extra_data = 0;
2297 }
2298
2299 if (fc > MAX_INSN_FIXUPS)
2300 as_fatal (_("too many fixups"));
2301
2302 fixups[fc].exp = ex;
2303 fixups[fc].opindex = *opindex_ptr;
2304 fixups[fc].reloc = reloc;
2305 fc++;
2306 }
2307 }
2308 else if (operand->flags & V850E_IMMEDIATE16
2309 || operand->flags & V850E_IMMEDIATE16HI)
2310 {
2311 expression (&ex);
2312
2313 switch (ex.X_op)
2314 {
2315 case O_constant:
2316 if (operand->flags & V850E_IMMEDIATE16HI)
2317 {
2318 if (ex.X_add_number & 0xffff)
2319 {
2320 errmsg = _("constant too big to fit into instruction");
2321 goto error;
2322 }
2323
2324 ex.X_add_number >>= 16;
2325 }
2326 if (operand->flags & V850E_IMMEDIATE16)
2327 {
2328 if (ex.X_add_number & 0xffff0000)
2329 {
2330 errmsg = _("constant too big to fit into instruction");
2331 goto error;
2332 }
2333 }
2334 break;
2335
2336 case O_illegal:
2337 errmsg = _("illegal operand");
2338 goto error;
2339
2340 case O_absent:
2341 errmsg = _("missing operand");
2342 goto error;
2343
2344 default:
2345 if (fc >= MAX_INSN_FIXUPS)
2346 as_fatal (_("too many fixups"));
2347
2348 fixups[fc].exp = ex;
2349 fixups[fc].opindex = *opindex_ptr;
2350 fixups[fc].reloc = operand->default_reloc;
2351 ++fc;
2352
2353 ex.X_add_number = 0;
2354 break;
2355 }
2356
2357 extra_data_after_insn = TRUE;
2358 extra_data_len = 2;
2359 extra_data = ex.X_add_number;
2360 }
2361 else if (operand->flags & V850E_IMMEDIATE23)
2362 {
2363 expression (&ex);
2364
2365 switch (ex.X_op)
2366 {
2367 case O_constant:
2368 break;
2369
2370 case O_illegal:
2371 errmsg = _("illegal operand");
2372 goto error;
2373
2374 case O_absent:
2375 errmsg = _("missing operand");
2376 goto error;
2377
2378 default:
2379 break;
2380 }
2381
2382 if (fc >= MAX_INSN_FIXUPS)
2383 as_fatal (_("too many fixups"));
2384
2385 fixups[fc].exp = ex;
2386 fixups[fc].opindex = *opindex_ptr;
2387 fixups[fc].reloc = operand->default_reloc;
2388 ++fc;
2389
2390 extra_data_after_insn = TRUE;
2391 extra_data_len = 2;
2392 extra_data = 0;
2393 }
2394 else if (operand->flags & V850E_IMMEDIATE32)
2395 {
2396 expression (&ex);
2397
2398 switch (ex.X_op)
2399 {
2400 case O_constant:
2401 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS
2402 || operand->default_reloc == BFD_RELOC_V850_32_PCREL)
2403 && (ex.X_add_number & 1))
2404 {
2405 errmsg = _("odd number cannot be used here");
2406 goto error;
2407 }
2408 break;
2409
2410 case O_illegal:
2411 errmsg = _("illegal operand");
2412 goto error;
2413
2414 case O_absent:
2415 errmsg = _("missing operand");
2416 goto error;
2417
2418 default:
2419 if (fc >= MAX_INSN_FIXUPS)
2420 as_fatal (_("too many fixups"));
2421
2422 fixups[fc].exp = ex;
2423 fixups[fc].opindex = *opindex_ptr;
2424 fixups[fc].reloc = operand->default_reloc;
2425 ++fc;
2426
2427 ex.X_add_number = 0;
2428 break;
2429 }
2430
2431 extra_data_after_insn = TRUE;
2432 extra_data_len = 4;
2433 extra_data = ex.X_add_number;
2434 }
2435 else if (operand->flags & V850E_OPERAND_REG_LIST)
2436 {
2437 errmsg = parse_register_list (&insn, operand);
2438
2439 if (errmsg)
2440 goto error;
2441 }
2442 else
2443 {
2444 errmsg = NULL;
2445
2446 if ((operand->flags & V850_OPERAND_REG) != 0)
2447 {
2448 if (!register_name (&ex))
2449 {
2450 errmsg = _("invalid register name");
2451 }
2452
2453 if ((operand->flags & V850_NOT_R0)
2454 && ex.X_add_number == 0)
2455 {
2456 errmsg = _("register r0 cannot be used here");
2457 }
2458
2459 if (operand->flags & V850_REG_EVEN)
2460 {
2461 if (ex.X_add_number % 2)
2462 errmsg = _("odd register cannot be used here");
2463 ex.X_add_number = ex.X_add_number / 2;
2464 }
2465
2466 }
2467 else if ((operand->flags & V850_OPERAND_SRG) != 0)
2468 {
2469 if (!system_register_name (&ex, TRUE))
2470 {
2471 errmsg = _("invalid system register name");
2472 }
2473 }
2474 else if ((operand->flags & V850_OPERAND_EP) != 0)
2475 {
2476 char *start = input_line_pointer;
2477 char c = get_symbol_end ();
2478
2479 if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0)
2480 {
2481 /* Put things back the way we found them. */
2482 *input_line_pointer = c;
2483 input_line_pointer = start;
2484 errmsg = _("expected EP register");
2485 goto error;
2486 }
2487
2488 *input_line_pointer = c;
2489 str = input_line_pointer;
2490 input_line_pointer = hold;
2491
2492 while (*str == ' ' || *str == ','
2493 || *str == '[' || *str == ']')
2494 ++str;
2495 continue;
2496 }
2497 else if ((operand->flags & V850_OPERAND_CC) != 0)
2498 {
2499 if (!cc_name (&ex, TRUE))
2500 {
2501 errmsg = _("invalid condition code name");
2502 }
2503
2504 if ((operand->flags & V850_NOT_SA)
2505 && ex.X_add_number == COND_SA_NUM)
2506 {
2507 errmsg = _("condition sa cannot be used here");
2508 }
2509 }
2510 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0)
2511 {
2512 if (!float_cc_name (&ex, TRUE))
2513 {
2514 errmsg = _("invalid condition code name");
2515 }
2516 }
2517 else if ((register_name (&ex)
2518 && (operand->flags & V850_OPERAND_REG) == 0))
2519 {
2520 char c;
2521 int exists = 0;
2522
2523 /* It is possible that an alias has been defined that
2524 matches a register name. For example the code may
2525 include a ".set ZERO, 0" directive, which matches
2526 the register name "zero". Attempt to reparse the
2527 field as an expression, and only complain if we
2528 cannot generate a constant. */
2529
2530 input_line_pointer = str;
2531
2532 c = get_symbol_end ();
2533
2534 if (symbol_find (str) != NULL)
2535 exists = 1;
2536
2537 *input_line_pointer = c;
2538 input_line_pointer = str;
2539
2540 expression (&ex);
2541
2542 if (ex.X_op != O_constant)
2543 {
2544 /* If this register is actually occurring too early on
2545 the parsing of the instruction, (because another
2546 field is missing) then report this. */
2547 if (opindex_ptr[1] != 0
2548 && ((v850_operands[opindex_ptr[1]].flags
2549 & V850_OPERAND_REG)
2550 ||(v850_operands[opindex_ptr[1]].flags
2551 & V850_OPERAND_VREG)))
2552 errmsg = _("syntax error: value is missing before the register name");
2553 else
2554 errmsg = _("syntax error: register not expected");
2555
2556 /* If we created a symbol in the process of this
2557 test then delete it now, so that it will not
2558 be output with the real symbols... */
2559 if (exists == 0
2560 && ex.X_op == O_symbol)
2561 symbol_remove (ex.X_add_symbol,
2562 &symbol_rootP, &symbol_lastP);
2563 }
2564 }
2565 else if (system_register_name (&ex, FALSE)
2566 && (operand->flags & V850_OPERAND_SRG) == 0)
2567 {
2568 errmsg = _("syntax error: system register not expected");
2569 }
2570 else if (cc_name (&ex, FALSE)
2571 && (operand->flags & V850_OPERAND_CC) == 0)
2572 {
2573 errmsg = _("syntax error: condition code not expected");
2574 }
2575 else if (float_cc_name (&ex, FALSE)
2576 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0)
2577 {
2578 errmsg = _("syntax error: condition code not expected");
2579 }
2580 else
2581 {
2582 expression (&ex);
2583
2584 if ((operand->flags & V850_NOT_IMM0)
2585 && ex.X_op == O_constant
2586 && ex.X_add_number == 0)
2587 {
2588 errmsg = _("immediate 0 cannot be used here");
2589 }
2590
2591 /* Special case:
2592 If we are assembling a MOV/JARL/JR instruction and the immediate
2593 value does not fit into the bits available then create a
2594 fake error so that the next MOV/JARL/JR instruction will be
2595 selected. This one has a 32 bit immediate field. */
2596
2597 if ((strcmp (opcode->name, "mov") == 0
2598 || strcmp (opcode->name, "jarl") == 0
2599 || strcmp (opcode->name, "jr") == 0)
2600 && ex.X_op == O_constant
2601 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
2602 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
2603 {
2604 errmsg = _("immediate operand is too large");
2605 }
2606
2607 if ((strcmp (opcode->name, "jarl") == 0
2608 || strcmp (opcode->name, "jr") == 0)
2609 && ex.X_op != O_constant
2610 && operand->bits != default_disp_size)
2611 {
2612 errmsg = _("immediate operand is not match");
2613 }
2614 }
2615
2616 if (errmsg)
2617 goto error;
2618
2619 switch (ex.X_op)
2620 {
2621 case O_illegal:
2622 errmsg = _("illegal operand");
2623 goto error;
2624 case O_absent:
2625 errmsg = _("missing operand");
2626 goto error;
2627 case O_register:
2628 if ((operand->flags
2629 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0)
2630 {
2631 errmsg = _("invalid operand");
2632 goto error;
2633 }
2634
2635 insn = v850_insert_operand (insn, operand,
2636 ex.X_add_number,
2637 &warningmsg);
2638
2639 break;
2640
2641 case O_constant:
2642 insn = v850_insert_operand (insn, operand, ex.X_add_number,
2643 &warningmsg);
2644 break;
2645
2646 default:
2647 /* We need to generate a fixup for this expression. */
2648 if (fc >= MAX_INSN_FIXUPS)
2649 as_fatal (_("too many fixups"));
2650
2651 fixups[fc].exp = ex;
2652 fixups[fc].opindex = *opindex_ptr;
2653 fixups[fc].reloc = BFD_RELOC_UNUSED;
2654 ++fc;
2655 break;
2656 }
2657 }
2658
2659 str = input_line_pointer;
2660 input_line_pointer = hold;
2661
2662 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']'
2663 || *str == ')')
2664 ++str;
2665 }
2666
2667 while (ISSPACE (*str))
2668 ++str;
2669
2670 if (*str == '\0')
2671 match = 1;
2672
2673 error:
2674 if (match == 0)
2675 {
2676 if ((opindex_ptr - opcode->operands) >= most_match_count)
2677 {
2678 most_match_count = opindex_ptr - opcode->operands;
2679 if (errmsg != NULL)
2680 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1);
2681 }
2682
2683 next_opcode = opcode + 1;
2684 if (next_opcode->name != NULL
2685 && strcmp (next_opcode->name, opcode->name) == 0)
2686 {
2687 opcode = next_opcode;
2688
2689 /* Skip versions that are not supported by the target
2690 processor. */
2691 if ((opcode->processors & processor_mask) == 0)
2692 goto error;
2693
2694 continue;
2695 }
2696
2697 if (most_match_errmsg[0] == 0)
2698 /* xgettext:c-format. */
2699 as_bad (_("junk at end of line: `%s'"), str);
2700 else
2701 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg);
2702
2703 if (*input_line_pointer == ']')
2704 ++input_line_pointer;
2705
2706 ignore_rest_of_line ();
2707 input_line_pointer = saved_input_line_pointer;
2708 return;
2709 }
2710
2711 if (warningmsg != NULL)
2712 as_warn ("%s", warningmsg);
2713 break;
2714 }
2715
2716 input_line_pointer = str;
2717
2718 /* Tie dwarf2 debug info to the address at the start of the insn.
2719 We can't do this after the insn has been output as the current
2720 frag may have been closed off. eg. by frag_var. */
2721 dwarf2_emit_insn (0);
2722
2723 /* Write out the instruction. */
2724
2725 if (relaxable && fc > 0)
2726 {
2727 insn_size = 2;
2728 fc = 0;
2729
2730 if (strcmp (opcode->name, "br") == 0
2731 || strcmp (opcode->name, "jbr") == 0)
2732 {
2733 if ((processor_mask & PROCESSOR_V850E2_ALL) == 0 || default_disp_size == 22)
2734 {
2735 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22,
2736 fixups[0].exp.X_add_symbol,
2737 fixups[0].exp.X_add_number,
2738 (char *)(size_t) fixups[0].opindex);
2739 md_number_to_chars (f, insn, insn_size);
2740 md_number_to_chars (f + 2, 0, 2);
2741 }
2742 else
2743 {
2744 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32,
2745 fixups[0].exp.X_add_symbol,
2746 fixups[0].exp.X_add_number,
2747 (char *)(size_t) fixups[0].opindex);
2748 md_number_to_chars (f, insn, insn_size);
2749 md_number_to_chars (f + 2, 0, 4);
2750 }
2751 }
2752 else /* b<cond>, j<cond>. */
2753 {
2754 if (default_disp_size == 22
2755 || (processor_mask & PROCESSOR_V850E2_ALL) == 0)
2756 {
2757 if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17)
2758 {
2759 if (strcmp (opcode->name, "bsa") == 0)
2760 {
2761 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22,
2762 fixups[0].exp.X_add_symbol,
2763 fixups[0].exp.X_add_number,
2764 (char *)(size_t) fixups[0].opindex);
2765 md_number_to_chars (f, insn, insn_size);
2766 md_number_to_chars (f + 2, 0, 6);
2767 }
2768 else
2769 {
2770 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22,
2771 fixups[0].exp.X_add_symbol,
2772 fixups[0].exp.X_add_number,
2773 (char *)(size_t) fixups[0].opindex);
2774 md_number_to_chars (f, insn, insn_size);
2775 md_number_to_chars (f + 2, 0, 4);
2776 }
2777 }
2778 else
2779 {
2780 if (strcmp (opcode->name, "bsa") == 0)
2781 {
2782 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22,
2783 fixups[0].exp.X_add_symbol,
2784 fixups[0].exp.X_add_number,
2785 (char *)(size_t) fixups[0].opindex);
2786 md_number_to_chars (f, insn, insn_size);
2787 md_number_to_chars (f + 2, 0, 6);
2788 }
2789 else
2790 {
2791 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22,
2792 fixups[0].exp.X_add_symbol,
2793 fixups[0].exp.X_add_number,
2794 (char *)(size_t) fixups[0].opindex);
2795 md_number_to_chars (f, insn, insn_size);
2796 md_number_to_chars (f + 2, 0, 4);
2797 }
2798 }
2799 }
2800 else
2801 {
2802 if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17)
2803 {
2804 if (strcmp (opcode->name, "bsa") == 0)
2805 {
2806 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32,
2807 fixups[0].exp.X_add_symbol,
2808 fixups[0].exp.X_add_number,
2809 (char *)(size_t) fixups[0].opindex);
2810 md_number_to_chars (f, insn, insn_size);
2811 md_number_to_chars (f + 2, 0, 8);
2812 }
2813 else
2814 {
2815 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32,
2816 fixups[0].exp.X_add_symbol,
2817 fixups[0].exp.X_add_number,
2818 (char *)(size_t) fixups[0].opindex);
2819 md_number_to_chars (f, insn, insn_size);
2820 md_number_to_chars (f + 2, 0, 6);
2821 }
2822 }
2823 else
2824 {
2825 if (strcmp (opcode->name, "bsa") == 0)
2826 {
2827 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32,
2828 fixups[0].exp.X_add_symbol,
2829 fixups[0].exp.X_add_number,
2830 (char *)(size_t) fixups[0].opindex);
2831 md_number_to_chars (f, insn, insn_size);
2832 md_number_to_chars (f + 2, 0, 8);
2833 }
2834 else
2835 {
2836 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32,
2837 fixups[0].exp.X_add_symbol,
2838 fixups[0].exp.X_add_number,
2839 (char *)(size_t) fixups[0].opindex);
2840 md_number_to_chars (f, insn, insn_size);
2841 md_number_to_chars (f + 2, 0, 6);
2842 }
2843 }
2844 }
2845 }
2846 }
2847 else
2848 {
2849 /* Four byte insns have an opcode with the two high bits on. */
2850 if ((insn & 0x0600) == 0x0600)
2851 insn_size = 4;
2852 else
2853 insn_size = 2;
2854
2855 /* Special case: 32 bit MOV. */
2856 if ((insn & 0xffe0) == 0x0620)
2857 insn_size = 2;
2858
2859 /* Special case: 32 bit JARL,JMP,JR. */
2860 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */
2861 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */
2862 || (insn & 0x1ffff) == 0x2e0) /* JR. */
2863 insn_size = 2;
2864
2865 f = frag_more (insn_size);
2866 md_number_to_chars (f, insn, insn_size);
2867
2868 if (extra_data_after_insn)
2869 {
2870 f = frag_more (extra_data_len);
2871 md_number_to_chars (f, extra_data, extra_data_len);
2872
2873 extra_data_after_insn = FALSE;
2874 }
2875 }
2876
2877 /* Create any fixups. At this point we do not use a
2878 bfd_reloc_code_real_type, but instead just use the
2879 BFD_RELOC_UNUSED plus the operand index. This lets us easily
2880 handle fixups for any operand type, although that is admittedly
2881 not a very exciting feature. We pick a BFD reloc type in
2882 md_apply_fix. */
2883 for (i = 0; i < fc; i++)
2884 {
2885 const struct v850_operand *operand;
2886 bfd_reloc_code_real_type reloc;
2887
2888 operand = &v850_operands[fixups[i].opindex];
2889
2890 reloc = fixups[i].reloc;
2891
2892 if (reloc != BFD_RELOC_UNUSED)
2893 {
2894 reloc_howto_type *reloc_howto =
2895 bfd_reloc_type_lookup (stdoutput, reloc);
2896 int size;
2897 int address;
2898 fixS *fixP;
2899
2900 if (!reloc_howto)
2901 abort ();
2902
2903 size = bfd_get_reloc_size (reloc_howto);
2904
2905 /* XXX This will abort on an R_V850_8 reloc -
2906 is this reloc actually used? */
2907 if (size != 2 && size != 4)
2908 abort ();
2909
2910 if (extra_data_len == 0)
2911 {
2912 address = (f - frag_now->fr_literal) + insn_size - size;
2913 }
2914 else
2915 {
2916 address = (f - frag_now->fr_literal) + extra_data_len - size;
2917 }
2918
2919 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL))
2920 {
2921 fixups[i].exp.X_add_number += 2;
2922 }
2923 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
2924 {
2925 fixups[i].exp.X_add_number += 2;
2926 address += 2;
2927 }
2928
2929 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */
2930 fixP = fix_new_exp (frag_now, address, size,
2931 &fixups[i].exp,
2932 reloc_howto->pc_relative,
2933 reloc);
2934
2935 fixP->tc_fix_data = (void *) operand;
2936
2937 switch (reloc)
2938 {
2939 case BFD_RELOC_LO16:
2940 case BFD_RELOC_V850_LO16_S1:
2941 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
2942 case BFD_RELOC_HI16:
2943 case BFD_RELOC_HI16_S:
2944 fixP->fx_no_overflow = 1;
2945 break;
2946 default:
2947 break;
2948 }
2949 }
2950 else
2951 {
2952 fix_new_exp (frag_now,
2953 f - frag_now->fr_literal, 4,
2954 & fixups[i].exp,
2955 (operand->flags & V850_PCREL) != 0,
2956 (bfd_reloc_code_real_type) (fixups[i].opindex
2957 + (int) BFD_RELOC_UNUSED));
2958 }
2959 }
2960
2961 input_line_pointer = saved_input_line_pointer;
2962 }
2963
2964 /* If while processing a fixup, a reloc really needs to be created
2965 then it is done here. */
2966
2967 arelent *
2968 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
2969 {
2970 arelent *reloc;
2971
2972 reloc = xmalloc (sizeof (arelent));
2973 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
2974 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2975 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2976
2977 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
2978 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2979 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL
2980 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP
2981 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN)
2982 reloc->addend = fixp->fx_offset;
2983 else
2984 {
2985 #if 0
2986 if (fixp->fx_r_type == BFD_RELOC_32
2987 && fixp->fx_pcrel)
2988 fixp->fx_r_type = BFD_RELOC_32_PCREL;
2989 #endif
2990
2991 reloc->addend = fixp->fx_addnumber;
2992 }
2993
2994 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
2995
2996 if (reloc->howto == NULL)
2997 {
2998 as_bad_where (fixp->fx_file, fixp->fx_line,
2999 /* xgettext:c-format */
3000 _("reloc %d not supported by object file format"),
3001 (int) fixp->fx_r_type);
3002
3003 xfree (reloc);
3004
3005 return NULL;
3006 }
3007
3008 return reloc;
3009 }
3010
3011 void
3012 v850_handle_align (fragS * frag)
3013 {
3014 if (v850_relax
3015 && frag->fr_type == rs_align
3016 && frag->fr_address + frag->fr_fix > 0
3017 && frag->fr_offset > 1
3018 && now_seg != bss_section
3019 && now_seg != v850_seg_table[SBSS_SECTION].s
3020 && now_seg != v850_seg_table[TBSS_SECTION].s
3021 && now_seg != v850_seg_table[ZBSS_SECTION].s)
3022 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0,
3023 BFD_RELOC_V850_ALIGN);
3024 }
3025
3026 /* Return current size of variable part of frag. */
3027
3028 int
3029 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED)
3030 {
3031 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
3032 abort ();
3033
3034 return md_relax_table[fragp->fr_subtype].rlx_length;
3035 }
3036
3037 long
3038 v850_pcrel_from_section (fixS *fixp, segT section)
3039 {
3040 /* If the symbol is undefined, or in a section other than our own,
3041 or it is weak (in which case it may well be in another section,
3042 then let the linker figure it out. */
3043 if (fixp->fx_addsy != (symbolS *) NULL
3044 && (! S_IS_DEFINED (fixp->fx_addsy)
3045 || S_IS_WEAK (fixp->fx_addsy)
3046 || (S_GET_SEGMENT (fixp->fx_addsy) != section)))
3047 return 0;
3048
3049 return fixp->fx_frag->fr_address + fixp->fx_where;
3050 }
3051
3052 void
3053 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
3054 {
3055 valueT value = * valueP;
3056 char *where;
3057
3058 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3059 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3060 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP
3061 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3062 {
3063 fixP->fx_done = 0;
3064 return;
3065 }
3066
3067 if (fixP->fx_addsy == (symbolS *) NULL)
3068 fixP->fx_addnumber = value,
3069 fixP->fx_done = 1;
3070
3071 else if (fixP->fx_pcrel)
3072 fixP->fx_addnumber = fixP->fx_offset;
3073
3074 else
3075 {
3076 value = fixP->fx_offset;
3077 if (fixP->fx_subsy != (symbolS *) NULL)
3078 {
3079 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)
3080 value -= S_GET_VALUE (fixP->fx_subsy);
3081 else
3082 /* We don't actually support subtracting a symbol. */
3083 as_bad_where (fixP->fx_file, fixP->fx_line,
3084 _("expression too complex"));
3085 }
3086 fixP->fx_addnumber = value;
3087 }
3088
3089 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
3090 {
3091 int opindex;
3092 const struct v850_operand *operand;
3093 unsigned long insn;
3094 const char *errmsg = NULL;
3095
3096 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
3097 operand = &v850_operands[opindex];
3098
3099 /* Fetch the instruction, insert the fully resolved operand
3100 value, and stuff the instruction back again.
3101
3102 Note the instruction has been stored in little endian
3103 format! */
3104 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3105
3106 if (fixP->fx_size > 2)
3107 insn = bfd_getl32 ((unsigned char *) where);
3108 else
3109 insn = bfd_getl16 ((unsigned char *) where);
3110
3111 insn = v850_insert_operand (insn, operand, (offsetT) value,
3112 &errmsg);
3113 if (errmsg)
3114 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg);
3115
3116 if (fixP->fx_size > 2)
3117 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3118 else
3119 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
3120
3121 if (fixP->fx_done)
3122 /* Nothing else to do here. */
3123 return;
3124
3125 /* Determine a BFD reloc value based on the operand information.
3126 We are only prepared to turn a few of the operands into relocs. */
3127
3128 if (operand->default_reloc == BFD_RELOC_NONE)
3129 {
3130 as_bad_where (fixP->fx_file, fixP->fx_line,
3131 _("unresolved expression that must be resolved"));
3132 fixP->fx_done = 1;
3133 return;
3134 }
3135
3136 {
3137 fixP->fx_r_type = operand->default_reloc;
3138 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3139 {
3140 fixP->fx_where += 2;
3141 fixP->fx_size = 2;
3142 fixP->fx_addnumber += 2;
3143 }
3144 }
3145 }
3146 else if (fixP->fx_done)
3147 {
3148 /* We still have to insert the value into memory! */
3149 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3150
3151 if (fixP->tc_fix_data != NULL
3152 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL)
3153 {
3154 const char * message = NULL;
3155 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data;
3156 unsigned long insn;
3157
3158 /* The variable "where" currently points at the exact point inside
3159 the insn where we need to insert the value. But we need to
3160 extract the entire insn so we probably need to move "where"
3161 back a few bytes. */
3162
3163 if (fixP->fx_size == 2)
3164 where -= 2;
3165 else if (fixP->fx_size == 1)
3166 where -= 3;
3167
3168 insn = bfd_getl32 ((unsigned char *) where);
3169
3170 /* Use the operand's insertion procedure, if present, in order to
3171 make sure that the value is correctly stored in the insn. */
3172 insn = operand->insert (insn, (offsetT) value, & message);
3173 /* Ignore message even if it is set. */
3174
3175 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3176 }
3177 else
3178 {
3179 switch (fixP->fx_r_type)
3180 {
3181 case BFD_RELOC_V850_32_ABS:
3182 case BFD_RELOC_V850_32_PCREL:
3183 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where);
3184 break;
3185
3186 case BFD_RELOC_32:
3187 bfd_putl32 (value, (unsigned char *) where);
3188 break;
3189
3190 case BFD_RELOC_V850_23:
3191 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7))
3192 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))),
3193 (unsigned char *) where);
3194 break;
3195
3196 case BFD_RELOC_16:
3197 case BFD_RELOC_HI16:
3198 case BFD_RELOC_HI16_S:
3199 case BFD_RELOC_LO16:
3200 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
3201 case BFD_RELOC_V850_SDA_16_16_OFFSET:
3202 case BFD_RELOC_V850_TDA_16_16_OFFSET:
3203 case BFD_RELOC_V850_CALLT_16_16_OFFSET:
3204 bfd_putl16 (value & 0xffff, (unsigned char *) where);
3205 break;
3206
3207 case BFD_RELOC_8:
3208 *where = value & 0xff;
3209 break;
3210
3211 case BFD_RELOC_V850_9_PCREL:
3212 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3)
3213 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where);
3214 break;
3215
3216 case BFD_RELOC_V850_17_PCREL:
3217 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16)
3218 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where);
3219 break;
3220
3221 case BFD_RELOC_V850_16_PCREL:
3222 bfd_putl16 (-value & 0xfffe, (unsigned char *) where);
3223 break;
3224
3225 case BFD_RELOC_V850_22_PCREL:
3226 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)
3227 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where);
3228 break;
3229
3230 case BFD_RELOC_V850_16_S1:
3231 case BFD_RELOC_V850_LO16_S1:
3232 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
3233 case BFD_RELOC_V850_SDA_15_16_OFFSET:
3234 bfd_putl16 (value & 0xfffe, (unsigned char *) where);
3235 break;
3236
3237 case BFD_RELOC_V850_16_SPLIT_OFFSET:
3238 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
3239 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
3240 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET:
3241 bfd_putl32 (((value << 16) & 0xfffe0000)
3242 | ((value << 5) & 0x20)
3243 | (bfd_getl32 (where) & ~0xfffe0020), where);
3244 break;
3245
3246 case BFD_RELOC_V850_TDA_6_8_OFFSET:
3247 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e);
3248 break;
3249
3250 case BFD_RELOC_V850_TDA_7_8_OFFSET:
3251 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f);
3252 break;
3253
3254 case BFD_RELOC_V850_TDA_7_7_OFFSET:
3255 *where = (*where & ~0x7f) | (value & 0x7f);
3256 break;
3257
3258 case BFD_RELOC_V850_TDA_4_5_OFFSET:
3259 *where = (*where & ~0xf) | ((value >> 1) & 0xf);
3260 break;
3261
3262 case BFD_RELOC_V850_TDA_4_4_OFFSET:
3263 *where = (*where & ~0xf) | (value & 0xf);
3264 break;
3265
3266 case BFD_RELOC_V850_CALLT_6_7_OFFSET:
3267 *where = (*where & ~0x3f) | (value & 0x3f);
3268 break;
3269
3270 default:
3271 abort ();
3272 }
3273 }
3274 }
3275 }
3276
3277 /* Parse a cons expression. We have to handle hi(), lo(), etc
3278 on the v850. */
3279
3280 void
3281 parse_cons_expression_v850 (expressionS *exp)
3282 {
3283 const char *errmsg;
3284 /* See if there's a reloc prefix like hi() we have to handle. */
3285 hold_cons_reloc = v850_reloc_prefix (NULL, &errmsg);
3286
3287 /* Do normal expression parsing. */
3288 expression (exp);
3289 }
3290
3291 /* Create a fixup for a cons expression. If parse_cons_expression_v850
3292 found a reloc prefix, then we use that reloc, else we choose an
3293 appropriate one based on the size of the expression. */
3294
3295 void
3296 cons_fix_new_v850 (fragS *frag,
3297 int where,
3298 int size,
3299 expressionS *exp)
3300 {
3301 if (hold_cons_reloc == BFD_RELOC_UNUSED)
3302 {
3303 if (size == 4)
3304 hold_cons_reloc = BFD_RELOC_32;
3305 if (size == 2)
3306 hold_cons_reloc = BFD_RELOC_16;
3307 if (size == 1)
3308 hold_cons_reloc = BFD_RELOC_8;
3309 }
3310
3311 if (exp != NULL)
3312 fix_new_exp (frag, where, size, exp, 0, hold_cons_reloc);
3313 else
3314 fix_new (frag, where, size, NULL, 0, 0, hold_cons_reloc);
3315
3316 hold_cons_reloc = BFD_RELOC_UNUSED;
3317 }
3318
3319 bfd_boolean
3320 v850_fix_adjustable (fixS *fixP)
3321 {
3322 if (fixP->fx_addsy == NULL)
3323 return 1;
3324
3325 /* Don't adjust function names. */
3326 if (S_IS_FUNCTION (fixP->fx_addsy))
3327 return 0;
3328
3329 /* We need the symbol name for the VTABLE entries. */
3330 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3331 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3332 return 0;
3333
3334 return 1;
3335 }
3336
3337 int
3338 v850_force_relocation (struct fix *fixP)
3339 {
3340 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3341 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP)
3342 return 1;
3343
3344 if (v850_relax
3345 && (fixP->fx_pcrel
3346 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN
3347 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL
3348 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL
3349 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL
3350 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL
3351 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL
3352 || fixP->fx_r_type >= BFD_RELOC_UNUSED))
3353 return 1;
3354
3355 return generic_force_reloc (fixP);
3356 }
git-cvsimport of binutils cvsroot