1 2008-07-30 Alan Modra <amodra@bigpond.net.au>
3 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
5 2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
7 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
9 2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
11 * mips-opc.c (CP): New macro.
12 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
13 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
14 dmtc2 Octeon instructions.
16 2008-07-07 Stan Shebs <stan@codesourcery.com>
18 * dis-init.c (init_disassemble_info): Init endian_code field.
19 * arm-dis.c (print_insn): Disassemble code according to
20 setting of endian_code.
21 (print_insn_big_arm): Detect when BE8 extension flag has been set.
23 2008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
25 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
28 2008-06-25 Peter Bergner <bergner@vnet.ibm.com>
30 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
31 (print_ppc_disassembler_options): Likewise.
32 * ppc-opc.c (PPC464): Define.
33 (powerpc_opcodes): Add mfdcrux and mtdcrux.
35 2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
37 * configure: Regenerate.
39 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
41 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
43 (struct dis_private): New.
44 (POWERPC_DIALECT): New define.
45 (powerpc_dialect): Renamed to...
46 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
48 (print_insn_big_powerpc): Update for using structure in
50 (print_insn_little_powerpc): Likewise.
51 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
52 (skip_optional_operands): Likewise.
53 (print_insn_powerpc): Likewise. Remove initialization of dialect.
54 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
55 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
56 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
57 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
58 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
59 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
60 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
61 param to be of type ppc_cpu_t. Update prototype.
63 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
65 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
67 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
68 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
69 syncw, syncws, vm3mulu, vm0 and vmulu.
71 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
72 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
75 2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
77 * i386-opc.tbl: Add vmovd with 64bit operand.
78 * i386-tbl.h: Regenerated.
80 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
82 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
84 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
86 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
87 * i386-tbl.h: Regenerated.
89 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
93 into 32bit and 64bit. Remove Reg64|Qword and add
94 IgnoreSize|No_qSuf on 32bit version.
95 * i386-tbl.h: Regenerated.
97 2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
99 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
100 * i386-tbl.h: Regenerated.
102 2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
104 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
106 2008-05-14 Alan Modra <amodra@bigpond.net.au>
108 * Makefile.am: Run "make dep-am".
109 * Makefile.in: Regenerate.
111 2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
113 * i386-dis.c (MOVBE_Fixup): New.
115 (PREFIX_0F3880): Likewise.
116 (PREFIX_0F3881): Likewise.
117 (PREFIX_0F38F0): Updated.
118 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
119 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
120 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
122 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
124 (cpu_flags): Add CpuMovbe and CpuEPT.
126 * i386-opc.h (CpuMovbe): New.
129 (i386_cpu_flags): Add cpumovbe and cpuept.
131 * i386-opc.tbl: Add entries for movbe and EPT instructions.
132 * i386-init.h: Regenerated.
133 * i386-tbl.h: Likewise.
135 2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
137 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
138 the two drem and the two dremu macros.
140 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
142 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
143 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
144 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
145 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
147 2008-04-25 David S. Miller <davem@davemloft.net>
149 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
150 instead of %sys_tick_cmpr, as suggested in architecture manuals.
152 2008-04-23 Paolo Bonzini <bonzini@gnu.org>
154 * aclocal.m4: Regenerate.
155 * configure: Regenerate.
157 2008-04-23 David S. Miller <davem@davemloft.net>
159 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
161 (prefetch_table): Add missing values.
163 2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
165 * i386-gen.c (opcode_modifiers): Add NoAVX.
167 * i386-opc.h (NoAVX): New.
169 (i386_opcode_modifier): Add noavx.
171 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
172 instructions which don't have AVX equivalent.
173 * i386-tbl.h: Regenerated.
175 2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
177 * i386-dis.c (OP_VEX_FMA): New.
178 (OP_EX_VexImmW): Likewise.
180 (Vex128FMA): Likewise.
181 (EXVexImmW): Likewise.
182 (get_vex_imm8): Likewise.
183 (OP_EX_VexReg): Likewise.
184 (vex_i4_done): Renamed to ...
186 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
187 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
189 (print_insn): Updated.
190 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
191 (OP_REG_VexI4): Check invalid high registers.
193 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
194 Michael Meissner <michael.meissner@amd.com>
196 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
197 * i386-tbl.h: Regenerate from i386-opc.tbl.
199 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
201 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
202 accept Power E500MC instructions.
203 (print_ppc_disassembler_options): Document -Me500mc.
204 * ppc-opc.c (DUIS, DUI, T): New.
205 (XRT, XRTRA): Likewise.
207 (powerpc_opcodes): Add new Power E500MC instructions.
209 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
211 * s390-dis.c (init_disasm): Evaluate disassembler_options.
212 (print_s390_disassembler_options): New function.
213 * disassemble.c (disassembler_usage): Invoke
214 print_s390_disassembler_options.
216 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
218 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
219 of local variables used for mnemonic parsing: prefix, suffix and
222 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
224 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
225 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
226 (s390_crb_extensions): New extensions table.
227 (insertExpandedMnemonic): Handle '$' tag.
228 * s390-opc.txt: Remove conditional jump variants which can now
229 be expanded automatically.
230 Replace '*' tag with '$' in the compare and branch instructions.
232 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
234 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
235 (PREFIX_VEX_3AXX): Likewis.
237 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
239 * i386-opc.tbl: Remove 4 extra blank lines.
241 2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
243 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
244 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
245 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
246 * i386-opc.tbl: Likewise.
248 * i386-opc.h (CpuCLMUL): Renamed to ...
251 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
253 * i386-init.h: Regenerated.
255 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
257 * i386-dis.c (OP_E_register): New.
258 (OP_E_memory): Likewise.
260 (OP_EX_Vex): Likewise.
261 (OP_EX_VexW): Likewise.
262 (OP_XMM_Vex): Likewise.
263 (OP_XMM_VexW): Likewise.
264 (OP_REG_VexI4): Likewise.
265 (PCLMUL_Fixup): Likewise.
266 (VEXI4_Fixup): Likewise.
267 (VZERO_Fixup): Likewise.
268 (VCMP_Fixup): Likewise.
269 (VPERMIL2_Fixup): Likewise.
270 (rex_original): Likewise.
271 (rex_ignored): Likewise.
292 (VPERMIL2): Likewise.
293 (xmm_mode): Likewise.
294 (xmmq_mode): Likewise.
295 (ymmq_mode): Likewise.
296 (vex_mode): Likewise.
297 (vex128_mode): Likewise.
298 (vex256_mode): Likewise.
299 (USE_VEX_C4_TABLE): Likewise.
300 (USE_VEX_C5_TABLE): Likewise.
301 (USE_VEX_LEN_TABLE): Likewise.
302 (VEX_C4_TABLE): Likewise.
303 (VEX_C5_TABLE): Likewise.
304 (VEX_LEN_TABLE): Likewise.
305 (REG_VEX_XX): Likewise.
306 (MOD_VEX_XXX): Likewise.
307 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
308 (PREFIX_0F3A44): Likewise.
309 (PREFIX_0F3ADF): Likewise.
310 (PREFIX_VEX_XXX): Likewise.
312 (VEX_OF38): Likewise.
313 (VEX_OF3A): Likewise.
314 (VEX_LEN_XXX): Likewise.
316 (need_vex): Likewise.
317 (need_vex_reg): Likewise.
318 (vex_i4_done): Likewise.
319 (vex_table): Likewise.
320 (vex_len_table): Likewise.
321 (OP_REG_VexI4): Likewise.
322 (vex_cmp_op): Likewise.
323 (pclmul_op): Likewise.
324 (vpermil2_op): Likewise.
327 (PREFIX_0F38F0): Likewise.
328 (PREFIX_0F3A60): Likewise.
329 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
330 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
331 and PREFIX_VEX_XXX entries.
332 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
333 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
335 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
336 Add MOD_VEX_XXX entries.
337 (ckprefix): Initialize rex_original and rex_ignored. Store the
338 REX byte in rex_original.
339 (get_valid_dis386): Handle the implicit prefix in VEX prefix
340 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
341 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
342 calling get_valid_dis386. Use rex_original and rex_ignored when
344 (putop): Handle "XY".
345 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
347 (OP_E_extended): Updated to use OP_E_register and
349 (OP_XMM): Handle VEX.
351 (XMM_Fixup): Likewise.
352 (CMP_Fixup): Use ARRAY_SIZE.
354 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
355 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
356 (operand_type_init): Add OPERAND_TYPE_REGYMM and
357 OPERAND_TYPE_VEX_IMM4.
358 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
359 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
360 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
361 VexImmExt and SSE2AVX.
362 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
364 * i386-opc.h (CpuAVX): New.
366 (CpuCLMUL): Likewise.
377 (Vex3Sources): Likewise.
378 (VexImmExt): Likewise.
382 (Vex_Imm4): Likewise.
383 (Implicit1stXmm0): Likewise.
386 (ByteOkIntel): Likewise.
389 (Unspecified): Likewise.
391 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
392 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
393 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
394 vex3sources, veximmext and sse2avx.
395 (i386_operand_type): Add regymm, ymmword and vex_imm4.
397 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
399 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
401 * i386-init.h: Regenerated.
402 * i386-tbl.h: Likewise.
404 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
406 From Robin Getz <robin.getz@analog.com>
407 * bfin-dis.c (bu32): Typedef.
408 (enum const_forms_t): Add c_uimm32 and c_huimm32.
409 (constant_formats[]): Add uimm32 and huimm16.
414 (luimm16_val): Define.
415 (struct saved_state): Define.
416 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
417 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
418 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
420 (decode_LDIMMhalf_0): Print out the whole register value.
422 From Jie Zhang <jie.zhang@analog.com>
423 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
424 multiply and multiply-accumulate to data register instruction.
426 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
427 c_imm32, c_huimm32e): Define.
428 (constant_formats): Add flags for printing decimal, leading spaces, and
430 (comment, parallel): Add global flags in all disassembly.
431 (fmtconst): Take advantage of new flags, and print default in hex.
432 (fmtconst_val): Likewise.
433 (decode_macfunc): Be consistant with spaces, tabs, comments,
434 capitalization in disassembly, fix minor coding style issues.
435 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
436 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
437 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
438 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
439 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
440 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
441 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
442 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
443 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
444 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
445 _print_insn_bfin, print_insn_bfin): Likewise.
447 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
449 * aclocal.m4: Regenerate.
450 * configure: Likewise.
451 * Makefile.in: Likewise.
453 2008-03-13 Alan Modra <amodra@bigpond.net.au>
455 * Makefile.am: Run "make dep-am".
456 * Makefile.in: Regenerate.
457 * configure: Regenerate.
459 2008-03-07 Alan Modra <amodra@bigpond.net.au>
461 * ppc-opc.c (powerpc_opcodes): Order and format.
463 2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
465 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
466 * i386-tbl.h: Regenerated.
468 2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
470 * i386-opc.tbl: Disallow 16-bit near indirect branches for
472 * i386-tbl.h: Regenerated.
474 2008-02-21 Jan Beulich <jbeulich@novell.com>
476 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
477 and Fword for far indirect jmp. Allow Reg16 and Word for near
478 indirect jmp on x86-64. Disallow Fword for lcall.
479 * i386-tbl.h: Re-generate.
481 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
483 * cr16-opc.c (cr16_num_optab): Defined
485 2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
487 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
488 * i386-init.h: Regenerated.
490 2008-02-14 Nick Clifton <nickc@redhat.com>
493 * configure.in (SHARED_LIBADD): Select the correct host specific
494 file extension for shared libraries.
495 * configure: Regenerate.
497 2008-02-13 Jan Beulich <jbeulich@novell.com>
499 * i386-opc.h (RegFlat): New.
500 * i386-reg.tbl (flat): Add.
501 * i386-tbl.h: Re-generate.
503 2008-02-13 Jan Beulich <jbeulich@novell.com>
505 * i386-dis.c (a_mode): New.
506 (cond_jump_mode): Adjust.
507 (Ma): Change to a_mode.
508 (intel_operand_size): Handle a_mode.
509 * i386-opc.tbl: Allow Dword and Qword for bound.
510 * i386-tbl.h: Re-generate.
512 2008-02-13 Jan Beulich <jbeulich@novell.com>
514 * i386-gen.c (process_i386_registers): Process new fields.
515 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
516 unsigned char. Add dw2_regnum and Dw2Inval.
517 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
519 * i386-tbl.h: Re-generate.
521 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
523 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
524 * i386-init.h: Updated.
526 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
528 * i386-gen.c (cpu_flags): Add CpuXsave.
530 * i386-opc.h (CpuXsave): New.
532 (i386_cpu_flags): Add cpuxsave.
534 * i386-dis.c (MOD_0FAE_REG_4): New.
535 (RM_0F01_REG_2): Likewise.
536 (MOD_0FAE_REG_5): Updated.
537 (RM_0F01_REG_3): Likewise.
538 (reg_table): Use MOD_0FAE_REG_4.
539 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
541 (rm_table): Add RM_0F01_REG_2.
543 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
544 * i386-init.h: Regenerated.
545 * i386-tbl.h: Likewise.
547 2008-02-11 Jan Beulich <jbeulich@novell.com>
549 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
550 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
551 * i386-tbl.h: Re-generate.
553 2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
556 * configure: Regenerated.
558 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
560 * mips-dis.c: Update copyright.
561 (mips_arch_choices): Add Octeon.
562 * mips-opc.c: Update copyright.
564 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
566 2008-01-29 Alan Modra <amodra@bigpond.net.au>
568 * ppc-opc.c: Support optional L form mtmsr.
570 2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
572 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
574 2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
576 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
577 * i386-init.h: Regenerated.
579 2008-01-23 Tristan Gingold <gingold@adacore.com>
581 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
582 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
584 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
586 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
587 (cpu_flags): Likewise.
589 * i386-opc.h (CpuMMX2): Removed.
592 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
593 * i386-init.h: Regenerated.
594 * i386-tbl.h: Likewise.
596 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
598 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
600 * i386-init.h: Regenerated.
602 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
604 * i386-opc.tbl: Use Qword on movddup.
605 * i386-tbl.h: Regenerated.
607 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
609 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
610 * i386-tbl.h: Regenerated.
612 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
614 * i386-dis.c (Mx): New.
615 (PREFIX_0FC3): Likewise.
616 (PREFIX_0FC7_REG_6): Updated.
617 (dis386_twobyte): Use PREFIX_0FC3.
618 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
619 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
622 2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
624 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
625 (operand_types): Add Mem.
627 * i386-opc.h (IntelSyntax): New.
628 * i386-opc.h (Mem): New.
630 (Opcode_Modifier_Max): Updated.
631 (i386_opcode_modifier): Add intelsyntax.
632 (i386_operand_type): Add mem.
634 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
637 * i386-reg.tbl: Add size for accumulator.
639 * i386-init.h: Regenerated.
640 * i386-tbl.h: Likewise.
642 2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
644 * i386-opc.h (Byte): Fix a typo.
646 2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
649 * i386-gen.c (operand_type_init): Add Dword to
650 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
651 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
653 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
654 Xmmword, Unspecified and Anysize.
655 (set_bitfield): Make Mmword an alias of Qword. Make Oword
658 * i386-opc.h (CheckSize): Removed.
666 (i386_opcode_modifier): Remove checksize, byte, word, dword,
670 (Unspecified): Likewise.
672 (i386_operand_type): Add byte, word, dword, fword, qword,
673 tbyte xmmword, unspecified and anysize.
675 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
676 Tbyte, Xmmword, Unspecified and Anysize.
678 * i386-reg.tbl: Add size for accumulator.
680 * i386-init.h: Regenerated.
681 * i386-tbl.h: Likewise.
683 2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
685 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
687 (reg_table): Updated.
688 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
689 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
691 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
693 * i386-gen.c (set_bitfield): Use fail () on error.
695 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
697 * i386-gen.c (lineno): New.
698 (filename): Likewise.
699 (set_bitfield): Report filename and line numer on error.
700 (process_i386_opcodes): Set filename and update lineno.
701 (process_i386_registers): Likewise.
703 2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
705 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
708 * i386-opc.h (IntelMnemonic): Renamed to ..
710 (Opcode_Modifier_Max): Updated.
711 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
714 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
715 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
716 * i386-tbl.h: Regenerated.
718 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
720 * i386-gen.c: Update copyright to 2008.
721 * i386-opc.h: Likewise.
722 * i386-opc.tbl: Likewise.
724 * i386-init.h: Regenerated.
725 * i386-tbl.h: Likewise.
727 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
729 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
730 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
731 * i386-tbl.h: Regenerated.
733 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
735 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
737 (cpu_flags): Likewise.
739 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
740 (CpuSSE4_2_Or_ABM): Likewise.
742 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
744 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
745 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
746 and CpuPadLock, respectively.
747 * i386-init.h: Regenerated.
748 * i386-tbl.h: Likewise.
750 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
752 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
754 * i386-opc.h (No_xSuf): Removed.
755 (CheckSize): Updated.
757 * i386-tbl.h: Regenerated.
759 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
761 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
762 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
764 (cpu_flags): Add CpuSSE4_2_Or_ABM.
766 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
768 (i386_cpu_flags): Add cpusse4_2_or_abm.
770 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
771 CpuABM|CpuSSE4_2 on popcnt.
772 * i386-init.h: Regenerated.
773 * i386-tbl.h: Likewise.
775 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
777 * i386-opc.h: Update comments.
779 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
781 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
782 * i386-opc.h: Likewise.
783 * i386-opc.tbl: Likewise.
785 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
788 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
789 Byte, Word, Dword, QWord and Xmmword.
791 * i386-opc.h (No_xSuf): New.
792 (CheckSize): Likewise.
799 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
800 Dword, QWord and Xmmword.
802 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
804 * i386-tbl.h: Regenerated.
806 2008-01-02 Mark Kettenis <kettenis@gnu.org>
808 * m88k-dis.c (instructions): Fix fcvt.* instructions.
811 For older changes see ChangeLog-2007
817 version-control: never