opcodes/m32r-desc.c

   1 /* CPU data for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "m32r-desc.h"
  32 #include "m32r-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35
  36 /* Attributes.  */
  37
  38 static const CGEN_ATTR_ENTRY bool_attr[] =
  39 {
  40   { "#f", 0 },
  41   { "#t", 1 },
  42   { 0, 0 }
  43 };
  44
  45 static const CGEN_ATTR_ENTRY MACH_attr[] =
  46 {
  47   { "base", MACH_BASE },
  48   { "m32r", MACH_M32R },
  49   { "m32rx", MACH_M32RX },
  50   { "max", MACH_MAX },
  51   { 0, 0 }
  52 };
  53
  54 static const CGEN_ATTR_ENTRY ISA_attr[] =
  55 {
  56   { "m32r", ISA_M32R },
  57   { "max", ISA_MAX },
  58   { 0, 0 }
  59 };
  60
  61 static const CGEN_ATTR_ENTRY PIPE_attr[] =
  62 {
  63   { "NONE", PIPE_NONE },
  64   { "O", PIPE_O },
  65   { "S", PIPE_S },
  66   { "OS", PIPE_OS },
  67   { 0, 0 }
  68 };
  69
  70 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
  71 {
  72   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  73   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  74   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  75   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  76   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  77   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  78   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  79   { "RELOC", &bool_attr[0], &bool_attr[0] },
  80   { 0, 0, 0 }
  81 };
  82
  83 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
  84 {
  85   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  86   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  87   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  88   { "PC", &bool_attr[0], &bool_attr[0] },
  89   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  90   { 0, 0, 0 }
  91 };
  92
  93 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
  94 {
  95   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  96   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  97   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  98   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  99   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 100   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 101   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 102   { "RELAX", &bool_attr[0], &bool_attr[0] },
 103   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 104   { "RELOC", &bool_attr[0], &bool_attr[0] },
 105   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 106   { 0, 0, 0 }
 107 };
 108
 109 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 110 {
 111   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 112   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
 113   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 114   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 115   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 116   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 117   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 118   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 119   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 120   { "RELAX", &bool_attr[0], &bool_attr[0] },
 121   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 122   { "PBB", &bool_attr[0], &bool_attr[0] },
 123   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
 124   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
 125   { 0, 0, 0 }
 126 };
 127
 128 /* Instruction set variants.  */
 129
 130 static const CGEN_ISA m32r_cgen_isa_table[] = {
 131   { "m32r", 32, 32, 16, 32 },
 132   { 0, 0, 0, 0, 0 }
 133 };
 134
 135 /* Machine variants.  */
 136
 137 static const CGEN_MACH m32r_cgen_mach_table[] = {
 138   { "m32r", "m32r", MACH_M32R, 0 },
 139   { "m32rx", "m32rx", MACH_M32RX, 0 },
 140   { 0, 0, 0, 0 }
 141 };
 142
 143 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
 144 {
 145   { "fp", 13, {0, {0}}, 0, 0 },
 146   { "lr", 14, {0, {0}}, 0, 0 },
 147   { "sp", 15, {0, {0}}, 0, 0 },
 148   { "r0", 0, {0, {0}}, 0, 0 },
 149   { "r1", 1, {0, {0}}, 0, 0 },
 150   { "r2", 2, {0, {0}}, 0, 0 },
 151   { "r3", 3, {0, {0}}, 0, 0 },
 152   { "r4", 4, {0, {0}}, 0, 0 },
 153   { "r5", 5, {0, {0}}, 0, 0 },
 154   { "r6", 6, {0, {0}}, 0, 0 },
 155   { "r7", 7, {0, {0}}, 0, 0 },
 156   { "r8", 8, {0, {0}}, 0, 0 },
 157   { "r9", 9, {0, {0}}, 0, 0 },
 158   { "r10", 10, {0, {0}}, 0, 0 },
 159   { "r11", 11, {0, {0}}, 0, 0 },
 160   { "r12", 12, {0, {0}}, 0, 0 },
 161   { "r13", 13, {0, {0}}, 0, 0 },
 162   { "r14", 14, {0, {0}}, 0, 0 },
 163   { "r15", 15, {0, {0}}, 0, 0 }
 164 };
 165
 166 CGEN_KEYWORD m32r_cgen_opval_gr_names =
 167 {
 168   & m32r_cgen_opval_gr_names_entries[0],
 169   19,
 170   0, 0, 0, 0, ""
 171 };
 172
 173 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 174 {
 175   { "psw", 0, {0, {0}}, 0, 0 },
 176   { "cbr", 1, {0, {0}}, 0, 0 },
 177   { "spi", 2, {0, {0}}, 0, 0 },
 178   { "spu", 3, {0, {0}}, 0, 0 },
 179   { "bpc", 6, {0, {0}}, 0, 0 },
 180   { "bbpsw", 8, {0, {0}}, 0, 0 },
 181   { "bbpc", 14, {0, {0}}, 0, 0 },
 182   { "cr0", 0, {0, {0}}, 0, 0 },
 183   { "cr1", 1, {0, {0}}, 0, 0 },
 184   { "cr2", 2, {0, {0}}, 0, 0 },
 185   { "cr3", 3, {0, {0}}, 0, 0 },
 186   { "cr4", 4, {0, {0}}, 0, 0 },
 187   { "cr5", 5, {0, {0}}, 0, 0 },
 188   { "cr6", 6, {0, {0}}, 0, 0 },
 189   { "cr7", 7, {0, {0}}, 0, 0 },
 190   { "cr8", 8, {0, {0}}, 0, 0 },
 191   { "cr9", 9, {0, {0}}, 0, 0 },
 192   { "cr10", 10, {0, {0}}, 0, 0 },
 193   { "cr11", 11, {0, {0}}, 0, 0 },
 194   { "cr12", 12, {0, {0}}, 0, 0 },
 195   { "cr13", 13, {0, {0}}, 0, 0 },
 196   { "cr14", 14, {0, {0}}, 0, 0 },
 197   { "cr15", 15, {0, {0}}, 0, 0 }
 198 };
 199
 200 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 201 {
 202   & m32r_cgen_opval_cr_names_entries[0],
 203   23,
 204   0, 0, 0, 0, ""
 205 };
 206
 207 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 208 {
 209   { "a0", 0, {0, {0}}, 0, 0 },
 210   { "a1", 1, {0, {0}}, 0, 0 }
 211 };
 212
 213 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 214 {
 215   & m32r_cgen_opval_h_accums_entries[0],
 216   2,
 217   0, 0, 0, 0, ""
 218 };
 219
 220
 221 /* The hardware table.  */
 222
 223 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 224 #define A(a) (1 << CGEN_HW_##a)
 225 #else
 226 #define A(a) (1 << CGEN_HW_/**/a)
 227 #endif
 228
 229 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 230 {
 231   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 232   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 233   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 234   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 235   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 236   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
 237   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 238   { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 239   { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 240   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
 241   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
 242   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 243   { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
 244   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 245   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 246   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 247   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 248   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 249   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 250 };
 251
 252 #undef A
 253
 254
 255 /* The instruction field table.  */
 256
 257 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 258 #define A(a) (1 << CGEN_IFLD_##a)
 259 #else
 260 #define A(a) (1 << CGEN_IFLD_/**/a)
 261 #endif
 262
 263 const CGEN_IFLD m32r_cgen_ifld_table[] =
 264 {
 265   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 266   { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 267   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
 268   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 269   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 270   { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 271   { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 272   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 273   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
 274   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
 275   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 276   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
 277   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
 278   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 279   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 280   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 281   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 282   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 283   { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
 284   { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
 285   { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
 286   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
 287   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
 288   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
 289   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
 290   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
 291   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 292 };
 293
 294 #undef A
 295
 296
 297 /* The operand table.  */
 298
 299 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 300 #define A(a) (1 << CGEN_OPERAND_##a)
 301 #else
 302 #define A(a) (1 << CGEN_OPERAND_/**/a)
 303 #endif
 304 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 305 #define OPERAND(op) M32R_OPERAND_##op
 306 #else
 307 #define OPERAND(op) M32R_OPERAND_/**/op
 308 #endif
 309
 310 const CGEN_OPERAND m32r_cgen_operand_table[] =
 311 {
 312 /* pc: program counter */
 313   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
 314     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 315 /* sr: source register */
 316   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
 317     { 0, { (1<<MACH_BASE) } }  },
 318 /* dr: destination register */
 319   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
 320     { 0, { (1<<MACH_BASE) } }  },
 321 /* src1: source register 1 */
 322   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
 323     { 0, { (1<<MACH_BASE) } }  },
 324 /* src2: source register 2 */
 325   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
 326     { 0, { (1<<MACH_BASE) } }  },
 327 /* scr: source control register */
 328   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
 329     { 0, { (1<<MACH_BASE) } }  },
 330 /* dcr: destination control register */
 331   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
 332     { 0, { (1<<MACH_BASE) } }  },
 333 /* simm8: 8 bit signed immediate */
 334   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
 335     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 336 /* simm16: 16 bit signed immediate */
 337   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
 338     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 339 /* uimm4: 4 bit trap number */
 340   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
 341     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 342 /* uimm5: 5 bit shift count */
 343   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
 344     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 345 /* uimm16: 16 bit unsigned immediate */
 346   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
 347     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 348 /* imm1: 1 bit immediate */
 349   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
 350     { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
 351 /* accd: accumulator destination register */
 352   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
 353     { 0, { (1<<MACH_M32RX) } }  },
 354 /* accs: accumulator source register */
 355   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
 356     { 0, { (1<<MACH_M32RX) } }  },
 357 /* acc: accumulator reg (d) */
 358   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
 359     { 0, { (1<<MACH_M32RX) } }  },
 360 /* hash: # prefix */
 361   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
 362     { 0, { (1<<MACH_BASE) } }  },
 363 /* hi16: high 16 bit immediate, sign optional */
 364   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
 365     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 366 /* slo16: 16 bit signed immediate, for low() */
 367   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
 368     { 0, { (1<<MACH_BASE) } }  },
 369 /* ulo16: 16 bit unsigned immediate, for low() */
 370   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
 371     { 0, { (1<<MACH_BASE) } }  },
 372 /* uimm24: 24 bit address */
 373   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
 374     { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 375 /* disp8: 8 bit displacement */
 376   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
 377     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 378 /* disp16: 16 bit displacement */
 379   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
 380     { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 381 /* disp24: 24 bit displacement */
 382   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
 383     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 384 /* condbit: condition bit */
 385   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
 386     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 387 /* accum: accumulator */
 388   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
 389     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 390   { 0, 0, 0, 0, 0, {0, {0}} }
 391 };
 392
 393 #undef A
 394
 395
 396 /* The instruction table.  */
 397
 398 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 399 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 400 #define A(a) (1 << CGEN_INSN_##a)
 401 #else
 402 #define A(a) (1 << CGEN_INSN_/**/a)
 403 #endif
 404
 405 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 406 {
 407   /* Special null first entry.
 408      A `num' value of zero is thus invalid.
 409      Also, the special `invalid' insn resides here.  */
 410   { 0, 0, 0, 0, {0, {0}} },
 411 /* add $dr,$sr */
 412   {
 413     M32R_INSN_ADD, "add", "add", 16,
 414     { 0, { (1<<MACH_BASE), PIPE_OS } }
 415   },
 416 /* add3 $dr,$sr,$hash$slo16 */
 417   {
 418     M32R_INSN_ADD3, "add3", "add3", 32,
 419     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 420   },
 421 /* and $dr,$sr */
 422   {
 423     M32R_INSN_AND, "and", "and", 16,
 424     { 0, { (1<<MACH_BASE), PIPE_OS } }
 425   },
 426 /* and3 $dr,$sr,$uimm16 */
 427   {
 428     M32R_INSN_AND3, "and3", "and3", 32,
 429     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 430   },
 431 /* or $dr,$sr */
 432   {
 433     M32R_INSN_OR, "or", "or", 16,
 434     { 0, { (1<<MACH_BASE), PIPE_OS } }
 435   },
 436 /* or3 $dr,$sr,$hash$ulo16 */
 437   {
 438     M32R_INSN_OR3, "or3", "or3", 32,
 439     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 440   },
 441 /* xor $dr,$sr */
 442   {
 443     M32R_INSN_XOR, "xor", "xor", 16,
 444     { 0, { (1<<MACH_BASE), PIPE_OS } }
 445   },
 446 /* xor3 $dr,$sr,$uimm16 */
 447   {
 448     M32R_INSN_XOR3, "xor3", "xor3", 32,
 449     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 450   },
 451 /* addi $dr,$simm8 */
 452   {
 453     M32R_INSN_ADDI, "addi", "addi", 16,
 454     { 0, { (1<<MACH_BASE), PIPE_OS } }
 455   },
 456 /* addv $dr,$sr */
 457   {
 458     M32R_INSN_ADDV, "addv", "addv", 16,
 459     { 0, { (1<<MACH_BASE), PIPE_OS } }
 460   },
 461 /* addv3 $dr,$sr,$simm16 */
 462   {
 463     M32R_INSN_ADDV3, "addv3", "addv3", 32,
 464     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 465   },
 466 /* addx $dr,$sr */
 467   {
 468     M32R_INSN_ADDX, "addx", "addx", 16,
 469     { 0, { (1<<MACH_BASE), PIPE_OS } }
 470   },
 471 /* bc.s $disp8 */
 472   {
 473     M32R_INSN_BC8, "bc8", "bc.s", 16,
 474     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
 475   },
 476 /* bc.l $disp24 */
 477   {
 478     M32R_INSN_BC24, "bc24", "bc.l", 32,
 479     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 480   },
 481 /* beq $src1,$src2,$disp16 */
 482   {
 483     M32R_INSN_BEQ, "beq", "beq", 32,
 484     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 485   },
 486 /* beqz $src2,$disp16 */
 487   {
 488     M32R_INSN_BEQZ, "beqz", "beqz", 32,
 489     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 490   },
 491 /* bgez $src2,$disp16 */
 492   {
 493     M32R_INSN_BGEZ, "bgez", "bgez", 32,
 494     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 495   },
 496 /* bgtz $src2,$disp16 */
 497   {
 498     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
 499     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 500   },
 501 /* blez $src2,$disp16 */
 502   {
 503     M32R_INSN_BLEZ, "blez", "blez", 32,
 504     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 505   },
 506 /* bltz $src2,$disp16 */
 507   {
 508     M32R_INSN_BLTZ, "bltz", "bltz", 32,
 509     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 510   },
 511 /* bnez $src2,$disp16 */
 512   {
 513     M32R_INSN_BNEZ, "bnez", "bnez", 32,
 514     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 515   },
 516 /* bl.s $disp8 */
 517   {
 518     M32R_INSN_BL8, "bl8", "bl.s", 16,
 519     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 520   },
 521 /* bl.l $disp24 */
 522   {
 523     M32R_INSN_BL24, "bl24", "bl.l", 32,
 524     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 525   },
 526 /* bcl.s $disp8 */
 527   {
 528     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
 529     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 530   },
 531 /* bcl.l $disp24 */
 532   {
 533     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
 534     { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
 535   },
 536 /* bnc.s $disp8 */
 537   {
 538     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
 539     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
 540   },
 541 /* bnc.l $disp24 */
 542   {
 543     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
 544     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 545   },
 546 /* bne $src1,$src2,$disp16 */
 547   {
 548     M32R_INSN_BNE, "bne", "bne", 32,
 549     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 550   },
 551 /* bra.s $disp8 */
 552   {
 553     M32R_INSN_BRA8, "bra8", "bra.s", 16,
 554     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 555   },
 556 /* bra.l $disp24 */
 557   {
 558     M32R_INSN_BRA24, "bra24", "bra.l", 32,
 559     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 560   },
 561 /* bncl.s $disp8 */
 562   {
 563     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
 564     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 565   },
 566 /* bncl.l $disp24 */
 567   {
 568     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
 569     { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
 570   },
 571 /* cmp $src1,$src2 */
 572   {
 573     M32R_INSN_CMP, "cmp", "cmp", 16,
 574     { 0, { (1<<MACH_BASE), PIPE_OS } }
 575   },
 576 /* cmpi $src2,$simm16 */
 577   {
 578     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
 579     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 580   },
 581 /* cmpu $src1,$src2 */
 582   {
 583     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
 584     { 0, { (1<<MACH_BASE), PIPE_OS } }
 585   },
 586 /* cmpui $src2,$simm16 */
 587   {
 588     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
 589     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 590   },
 591 /* cmpeq $src1,$src2 */
 592   {
 593     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
 594     { 0, { (1<<MACH_M32RX), PIPE_OS } }
 595   },
 596 /* cmpz $src2 */
 597   {
 598     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
 599     { 0, { (1<<MACH_M32RX), PIPE_OS } }
 600   },
 601 /* div $dr,$sr */
 602   {
 603     M32R_INSN_DIV, "div", "div", 32,
 604     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 605   },
 606 /* divu $dr,$sr */
 607   {
 608     M32R_INSN_DIVU, "divu", "divu", 32,
 609     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 610   },
 611 /* rem $dr,$sr */
 612   {
 613     M32R_INSN_REM, "rem", "rem", 32,
 614     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 615   },
 616 /* remu $dr,$sr */
 617   {
 618     M32R_INSN_REMU, "remu", "remu", 32,
 619     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 620   },
 621 /* divh $dr,$sr */
 622   {
 623     M32R_INSN_DIVH, "divh", "divh", 32,
 624     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
 625   },
 626 /* jc $sr */
 627   {
 628     M32R_INSN_JC, "jc", "jc", 16,
 629     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 630   },
 631 /* jnc $sr */
 632   {
 633     M32R_INSN_JNC, "jnc", "jnc", 16,
 634     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 635   },
 636 /* jl $sr */
 637   {
 638     M32R_INSN_JL, "jl", "jl", 16,
 639     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 640   },
 641 /* jmp $sr */
 642   {
 643     M32R_INSN_JMP, "jmp", "jmp", 16,
 644     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 645   },
 646 /* ld $dr,@$sr */
 647   {
 648     M32R_INSN_LD, "ld", "ld", 16,
 649     { 0, { (1<<MACH_BASE), PIPE_O } }
 650   },
 651 /* ld $dr,@($slo16,$sr) */
 652   {
 653     M32R_INSN_LD_D, "ld-d", "ld", 32,
 654     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 655   },
 656 /* ldb $dr,@$sr */
 657   {
 658     M32R_INSN_LDB, "ldb", "ldb", 16,
 659     { 0, { (1<<MACH_BASE), PIPE_O } }
 660   },
 661 /* ldb $dr,@($slo16,$sr) */
 662   {
 663     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
 664     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 665   },
 666 /* ldh $dr,@$sr */
 667   {
 668     M32R_INSN_LDH, "ldh", "ldh", 16,
 669     { 0, { (1<<MACH_BASE), PIPE_O } }
 670   },
 671 /* ldh $dr,@($slo16,$sr) */
 672   {
 673     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
 674     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 675   },
 676 /* ldub $dr,@$sr */
 677   {
 678     M32R_INSN_LDUB, "ldub", "ldub", 16,
 679     { 0, { (1<<MACH_BASE), PIPE_O } }
 680   },
 681 /* ldub $dr,@($slo16,$sr) */
 682   {
 683     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
 684     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 685   },
 686 /* lduh $dr,@$sr */
 687   {
 688     M32R_INSN_LDUH, "lduh", "lduh", 16,
 689     { 0, { (1<<MACH_BASE), PIPE_O } }
 690   },
 691 /* lduh $dr,@($slo16,$sr) */
 692   {
 693     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
 694     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 695   },
 696 /* ld $dr,@$sr+ */
 697   {
 698     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
 699     { 0, { (1<<MACH_BASE), PIPE_O } }
 700   },
 701 /* ld24 $dr,$uimm24 */
 702   {
 703     M32R_INSN_LD24, "ld24", "ld24", 32,
 704     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 705   },
 706 /* ldi8 $dr,$simm8 */
 707   {
 708     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
 709     { 0, { (1<<MACH_BASE), PIPE_OS } }
 710   },
 711 /* ldi16 $dr,$hash$slo16 */
 712   {
 713     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
 714     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 715   },
 716 /* lock $dr,@$sr */
 717   {
 718     M32R_INSN_LOCK, "lock", "lock", 16,
 719     { 0, { (1<<MACH_BASE), PIPE_O } }
 720   },
 721 /* machi $src1,$src2 */
 722   {
 723     M32R_INSN_MACHI, "machi", "machi", 16,
 724     { 0, { (1<<MACH_M32R), PIPE_S } }
 725   },
 726 /* machi $src1,$src2,$acc */
 727   {
 728     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
 729     { 0, { (1<<MACH_M32RX), PIPE_S } }
 730   },
 731 /* maclo $src1,$src2 */
 732   {
 733     M32R_INSN_MACLO, "maclo", "maclo", 16,
 734     { 0, { (1<<MACH_M32R), PIPE_S } }
 735   },
 736 /* maclo $src1,$src2,$acc */
 737   {
 738     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
 739     { 0, { (1<<MACH_M32RX), PIPE_S } }
 740   },
 741 /* macwhi $src1,$src2 */
 742   {
 743     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
 744     { 0, { (1<<MACH_M32R), PIPE_S } }
 745   },
 746 /* macwhi $src1,$src2,$acc */
 747   {
 748     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
 749     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 750   },
 751 /* macwlo $src1,$src2 */
 752   {
 753     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
 754     { 0, { (1<<MACH_M32R), PIPE_S } }
 755   },
 756 /* macwlo $src1,$src2,$acc */
 757   {
 758     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
 759     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 760   },
 761 /* mul $dr,$sr */
 762   {
 763     M32R_INSN_MUL, "mul", "mul", 16,
 764     { 0, { (1<<MACH_BASE), PIPE_S } }
 765   },
 766 /* mulhi $src1,$src2 */
 767   {
 768     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
 769     { 0, { (1<<MACH_M32R), PIPE_S } }
 770   },
 771 /* mulhi $src1,$src2,$acc */
 772   {
 773     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
 774     { 0, { (1<<MACH_M32RX), PIPE_S } }
 775   },
 776 /* mullo $src1,$src2 */
 777   {
 778     M32R_INSN_MULLO, "mullo", "mullo", 16,
 779     { 0, { (1<<MACH_M32R), PIPE_S } }
 780   },
 781 /* mullo $src1,$src2,$acc */
 782   {
 783     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
 784     { 0, { (1<<MACH_M32RX), PIPE_S } }
 785   },
 786 /* mulwhi $src1,$src2 */
 787   {
 788     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
 789     { 0, { (1<<MACH_M32R), PIPE_S } }
 790   },
 791 /* mulwhi $src1,$src2,$acc */
 792   {
 793     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
 794     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 795   },
 796 /* mulwlo $src1,$src2 */
 797   {
 798     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
 799     { 0, { (1<<MACH_M32R), PIPE_S } }
 800   },
 801 /* mulwlo $src1,$src2,$acc */
 802   {
 803     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
 804     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 805   },
 806 /* mv $dr,$sr */
 807   {
 808     M32R_INSN_MV, "mv", "mv", 16,
 809     { 0, { (1<<MACH_BASE), PIPE_OS } }
 810   },
 811 /* mvfachi $dr */
 812   {
 813     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
 814     { 0, { (1<<MACH_M32R), PIPE_S } }
 815   },
 816 /* mvfachi $dr,$accs */
 817   {
 818     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
 819     { 0, { (1<<MACH_M32RX), PIPE_S } }
 820   },
 821 /* mvfaclo $dr */
 822   {
 823     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
 824     { 0, { (1<<MACH_M32R), PIPE_S } }
 825   },
 826 /* mvfaclo $dr,$accs */
 827   {
 828     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
 829     { 0, { (1<<MACH_M32RX), PIPE_S } }
 830   },
 831 /* mvfacmi $dr */
 832   {
 833     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
 834     { 0, { (1<<MACH_M32R), PIPE_S } }
 835   },
 836 /* mvfacmi $dr,$accs */
 837   {
 838     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
 839     { 0, { (1<<MACH_M32RX), PIPE_S } }
 840   },
 841 /* mvfc $dr,$scr */
 842   {
 843     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
 844     { 0, { (1<<MACH_BASE), PIPE_O } }
 845   },
 846 /* mvtachi $src1 */
 847   {
 848     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
 849     { 0, { (1<<MACH_M32R), PIPE_S } }
 850   },
 851 /* mvtachi $src1,$accs */
 852   {
 853     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
 854     { 0, { (1<<MACH_M32RX), PIPE_S } }
 855   },
 856 /* mvtaclo $src1 */
 857   {
 858     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
 859     { 0, { (1<<MACH_M32R), PIPE_S } }
 860   },
 861 /* mvtaclo $src1,$accs */
 862   {
 863     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
 864     { 0, { (1<<MACH_M32RX), PIPE_S } }
 865   },
 866 /* mvtc $sr,$dcr */
 867   {
 868     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
 869     { 0, { (1<<MACH_BASE), PIPE_O } }
 870   },
 871 /* neg $dr,$sr */
 872   {
 873     M32R_INSN_NEG, "neg", "neg", 16,
 874     { 0, { (1<<MACH_BASE), PIPE_OS } }
 875   },
 876 /* nop */
 877   {
 878     M32R_INSN_NOP, "nop", "nop", 16,
 879     { 0, { (1<<MACH_BASE), PIPE_OS } }
 880   },
 881 /* not $dr,$sr */
 882   {
 883     M32R_INSN_NOT, "not", "not", 16,
 884     { 0, { (1<<MACH_BASE), PIPE_OS } }
 885   },
 886 /* rac */
 887   {
 888     M32R_INSN_RAC, "rac", "rac", 16,
 889     { 0, { (1<<MACH_M32R), PIPE_S } }
 890   },
 891 /* rac $accd,$accs,$imm1 */
 892   {
 893     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
 894     { 0, { (1<<MACH_M32RX), PIPE_S } }
 895   },
 896 /* rach */
 897   {
 898     M32R_INSN_RACH, "rach", "rach", 16,
 899     { 0, { (1<<MACH_M32R), PIPE_S } }
 900   },
 901 /* rach $accd,$accs,$imm1 */
 902   {
 903     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
 904     { 0, { (1<<MACH_M32RX), PIPE_S } }
 905   },
 906 /* rte */
 907   {
 908     M32R_INSN_RTE, "rte", "rte", 16,
 909     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 910   },
 911 /* seth $dr,$hash$hi16 */
 912   {
 913     M32R_INSN_SETH, "seth", "seth", 32,
 914     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 915   },
 916 /* sll $dr,$sr */
 917   {
 918     M32R_INSN_SLL, "sll", "sll", 16,
 919     { 0, { (1<<MACH_BASE), PIPE_O } }
 920   },
 921 /* sll3 $dr,$sr,$simm16 */
 922   {
 923     M32R_INSN_SLL3, "sll3", "sll3", 32,
 924     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 925   },
 926 /* slli $dr,$uimm5 */
 927   {
 928     M32R_INSN_SLLI, "slli", "slli", 16,
 929     { 0, { (1<<MACH_BASE), PIPE_O } }
 930   },
 931 /* sra $dr,$sr */
 932   {
 933     M32R_INSN_SRA, "sra", "sra", 16,
 934     { 0, { (1<<MACH_BASE), PIPE_O } }
 935   },
 936 /* sra3 $dr,$sr,$simm16 */
 937   {
 938     M32R_INSN_SRA3, "sra3", "sra3", 32,
 939     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 940   },
 941 /* srai $dr,$uimm5 */
 942   {
 943     M32R_INSN_SRAI, "srai", "srai", 16,
 944     { 0, { (1<<MACH_BASE), PIPE_O } }
 945   },
 946 /* srl $dr,$sr */
 947   {
 948     M32R_INSN_SRL, "srl", "srl", 16,
 949     { 0, { (1<<MACH_BASE), PIPE_O } }
 950   },
 951 /* srl3 $dr,$sr,$simm16 */
 952   {
 953     M32R_INSN_SRL3, "srl3", "srl3", 32,
 954     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 955   },
 956 /* srli $dr,$uimm5 */
 957   {
 958     M32R_INSN_SRLI, "srli", "srli", 16,
 959     { 0, { (1<<MACH_BASE), PIPE_O } }
 960   },
 961 /* st $src1,@$src2 */
 962   {
 963     M32R_INSN_ST, "st", "st", 16,
 964     { 0, { (1<<MACH_BASE), PIPE_O } }
 965   },
 966 /* st $src1,@($slo16,$src2) */
 967   {
 968     M32R_INSN_ST_D, "st-d", "st", 32,
 969     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 970   },
 971 /* stb $src1,@$src2 */
 972   {
 973     M32R_INSN_STB, "stb", "stb", 16,
 974     { 0, { (1<<MACH_BASE), PIPE_O } }
 975   },
 976 /* stb $src1,@($slo16,$src2) */
 977   {
 978     M32R_INSN_STB_D, "stb-d", "stb", 32,
 979     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 980   },
 981 /* sth $src1,@$src2 */
 982   {
 983     M32R_INSN_STH, "sth", "sth", 16,
 984     { 0, { (1<<MACH_BASE), PIPE_O } }
 985   },
 986 /* sth $src1,@($slo16,$src2) */
 987   {
 988     M32R_INSN_STH_D, "sth-d", "sth", 32,
 989     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 990   },
 991 /* st $src1,@+$src2 */
 992   {
 993     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
 994     { 0, { (1<<MACH_BASE), PIPE_O } }
 995   },
 996 /* st $src1,@-$src2 */
 997   {
 998     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
 999     { 0, { (1<<MACH_BASE), PIPE_O } }
1000   },
1001 /* sub $dr,$sr */
1002   {
1003     M32R_INSN_SUB, "sub", "sub", 16,
1004     { 0, { (1<<MACH_BASE), PIPE_OS } }
1005   },
1006 /* subv $dr,$sr */
1007   {
1008     M32R_INSN_SUBV, "subv", "subv", 16,
1009     { 0, { (1<<MACH_BASE), PIPE_OS } }
1010   },
1011 /* subx $dr,$sr */
1012   {
1013     M32R_INSN_SUBX, "subx", "subx", 16,
1014     { 0, { (1<<MACH_BASE), PIPE_OS } }
1015   },
1016 /* trap $uimm4 */
1017   {
1018     M32R_INSN_TRAP, "trap", "trap", 16,
1019     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1020   },
1021 /* unlock $src1,@$src2 */
1022   {
1023     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1024     { 0, { (1<<MACH_BASE), PIPE_O } }
1025   },
1026 /* satb $dr,$sr */
1027   {
1028     M32R_INSN_SATB, "satb", "satb", 32,
1029     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1030   },
1031 /* sath $dr,$sr */
1032   {
1033     M32R_INSN_SATH, "sath", "sath", 32,
1034     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1035   },
1036 /* sat $dr,$sr */
1037   {
1038     M32R_INSN_SAT, "sat", "sat", 32,
1039     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
1040   },
1041 /* pcmpbz $src2 */
1042   {
1043     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1044     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
1045   },
1046 /* sadd */
1047   {
1048     M32R_INSN_SADD, "sadd", "sadd", 16,
1049     { 0, { (1<<MACH_M32RX), PIPE_S } }
1050   },
1051 /* macwu1 $src1,$src2 */
1052   {
1053     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1054     { 0, { (1<<MACH_M32RX), PIPE_S } }
1055   },
1056 /* msblo $src1,$src2 */
1057   {
1058     M32R_INSN_MSBLO, "msblo", "msblo", 16,
1059     { 0, { (1<<MACH_M32RX), PIPE_S } }
1060   },
1061 /* mulwu1 $src1,$src2 */
1062   {
1063     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1064     { 0, { (1<<MACH_M32RX), PIPE_S } }
1065   },
1066 /* maclh1 $src1,$src2 */
1067   {
1068     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1069     { 0, { (1<<MACH_M32RX), PIPE_S } }
1070   },
1071 /* sc */
1072   {
1073     M32R_INSN_SC, "sc", "sc", 16,
1074     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1075   },
1076 /* snc */
1077   {
1078     M32R_INSN_SNC, "snc", "snc", 16,
1079     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1080   },
1081 };
1082
1083 #undef OP
1084 #undef A
1085
1086 /* Initialize anything needed to be done once, before any cpu_open call.  */
1087 static void init_tables PARAMS ((void));
1088
1089 static void
1090 init_tables ()
1091 {
1092 }
1093
1094 static const CGEN_MACH * lookup_mach_via_bfd_name
1095   PARAMS ((const CGEN_MACH *, const char *));
1096 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
1097 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
1098 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1099 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
1100 static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1101
1102 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1103
1104 static const CGEN_MACH *
1105 lookup_mach_via_bfd_name (table, name)
1106      const CGEN_MACH *table;
1107      const char *name;
1108 {
1109   while (table->name)
1110     {
1111       if (strcmp (name, table->bfd_name) == 0)
1112         return table;
1113       ++table;
1114     }
1115   abort ();
1116 }
1117
1118 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1119
1120 static void
1121 build_hw_table (cd)
1122      CGEN_CPU_TABLE *cd;
1123 {
1124   int i;
1125   int machs = cd->machs;
1126   const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1127   /* MAX_HW is only an upper bound on the number of selected entries.
1128      However each entry is indexed by it's enum so there can be holes in
1129      the table.  */
1130   const CGEN_HW_ENTRY **selected =
1131     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1132
1133   cd->hw_table.init_entries = init;
1134   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1135   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1136   /* ??? For now we just use machs to determine which ones we want.  */
1137   for (i = 0; init[i].name != NULL; ++i)
1138     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1139         & machs)
1140       selected[init[i].type] = &init[i];
1141   cd->hw_table.entries = selected;
1142   cd->hw_table.num_entries = MAX_HW;
1143 }
1144
1145 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1146
1147 static void
1148 build_ifield_table (cd)
1149      CGEN_CPU_TABLE *cd;
1150 {
1151   cd->ifld_table = & m32r_cgen_ifld_table[0];
1152 }
1153
1154 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1155
1156 static void
1157 build_operand_table (cd)
1158      CGEN_CPU_TABLE *cd;
1159 {
1160   int i;
1161   int machs = cd->machs;
1162   const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1163   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1164      However each entry is indexed by it's enum so there can be holes in
1165      the table.  */
1166   const CGEN_OPERAND **selected =
1167     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1168
1169   cd->operand_table.init_entries = init;
1170   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1171   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1172   /* ??? For now we just use mach to determine which ones we want.  */
1173   for (i = 0; init[i].name != NULL; ++i)
1174     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1175         & machs)
1176       selected[init[i].type] = &init[i];
1177   cd->operand_table.entries = selected;
1178   cd->operand_table.num_entries = MAX_OPERANDS;
1179 }
1180
1181 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1182    ??? This could leave out insns not supported by the specified mach/isa,
1183    but that would cause errors like "foo only supported by bar" to become
1184    "unknown insn", so for now we include all insns and require the app to
1185    do the checking later.
1186    ??? On the other hand, parsing of such insns may require their hardware or
1187    operand elements to be in the table [which they mightn't be].  */
1188
1189 static void
1190 build_insn_table (cd)
1191      CGEN_CPU_TABLE *cd;
1192 {
1193   int i;
1194   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1195   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1196
1197   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1198   for (i = 0; i < MAX_INSNS; ++i)
1199     insns[i].base = &ib[i];
1200   cd->insn_table.init_entries = insns;
1201   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1202   cd->insn_table.num_init_entries = MAX_INSNS;
1203 }
1204
1205 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1206
1207 static void
1208 m32r_cgen_rebuild_tables (cd)
1209      CGEN_CPU_TABLE *cd;
1210 {
1211   int i;
1212   unsigned int isas = cd->isas;
1213   unsigned int machs = cd->machs;
1214
1215   cd->int_insn_p = CGEN_INT_INSN_P;
1216
1217   /* Data derived from the isa spec.  */
1218 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1219   cd->default_insn_bitsize = UNSET;
1220   cd->base_insn_bitsize = UNSET;
1221   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1222   cd->max_insn_bitsize = 0;
1223   for (i = 0; i < MAX_ISAS; ++i)
1224     if (((1 << i) & isas) != 0)
1225       {
1226         const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1227
1228         /* Default insn sizes of all selected isas must be equal or we set
1229            the result to 0, meaning "unknown".  */
1230         if (cd->default_insn_bitsize == UNSET)
1231           cd->default_insn_bitsize = isa->default_insn_bitsize;
1232         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1233           ; /* this is ok */
1234         else
1235           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1236
1237         /* Base insn sizes of all selected isas must be equal or we set
1238            the result to 0, meaning "unknown".  */
1239         if (cd->base_insn_bitsize == UNSET)
1240           cd->base_insn_bitsize = isa->base_insn_bitsize;
1241         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1242           ; /* this is ok */
1243         else
1244           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1245
1246         /* Set min,max insn sizes.  */
1247         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1248           cd->min_insn_bitsize = isa->min_insn_bitsize;
1249         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1250           cd->max_insn_bitsize = isa->max_insn_bitsize;
1251       }
1252
1253   /* Data derived from the mach spec.  */
1254   for (i = 0; i < MAX_MACHS; ++i)
1255     if (((1 << i) & machs) != 0)
1256       {
1257         const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1258
1259         if (mach->insn_chunk_bitsize != 0)
1260         {
1261           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1262             {
1263               fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1264                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1265               abort ();
1266             }
1267
1268           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1269         }
1270       }
1271
1272   /* Determine which hw elements are used by MACH.  */
1273   build_hw_table (cd);
1274
1275   /* Build the ifield table.  */
1276   build_ifield_table (cd);
1277
1278   /* Determine which operands are used by MACH/ISA.  */
1279   build_operand_table (cd);
1280
1281   /* Build the instruction table.  */
1282   build_insn_table (cd);
1283 }
1284
1285 /* Initialize a cpu table and return a descriptor.
1286    It's much like opening a file, and must be the first function called.
1287    The arguments are a set of (type/value) pairs, terminated with
1288    CGEN_CPU_OPEN_END.
1289
1290    Currently supported values:
1291    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1292    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1293    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1294    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1295    CGEN_CPU_OPEN_END:     terminates arguments
1296
1297    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1298    precluded.
1299
1300    ??? We only support ISO C stdargs here, not K&R.
1301    Laziness, plus experiment to see if anything requires K&R - eventually
1302    K&R will no longer be supported - e.g. GDB is currently trying this.  */
1303
1304 CGEN_CPU_DESC
1305 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1306 {
1307   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1308   static int init_p;
1309   unsigned int isas = 0;  /* 0 = "unspecified" */
1310   unsigned int machs = 0; /* 0 = "unspecified" */
1311   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1312   va_list ap;
1313
1314   if (! init_p)
1315     {
1316       init_tables ();
1317       init_p = 1;
1318     }
1319
1320   memset (cd, 0, sizeof (*cd));
1321
1322   va_start (ap, arg_type);
1323   while (arg_type != CGEN_CPU_OPEN_END)
1324     {
1325       switch (arg_type)
1326         {
1327         case CGEN_CPU_OPEN_ISAS :
1328           isas = va_arg (ap, unsigned int);
1329           break;
1330         case CGEN_CPU_OPEN_MACHS :
1331           machs = va_arg (ap, unsigned int);
1332           break;
1333         case CGEN_CPU_OPEN_BFDMACH :
1334           {
1335             const char *name = va_arg (ap, const char *);
1336             const CGEN_MACH *mach =
1337               lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1338
1339             machs |= 1 << mach->num;
1340             break;
1341           }
1342         case CGEN_CPU_OPEN_ENDIAN :
1343           endian = va_arg (ap, enum cgen_endian);
1344           break;
1345         default :
1346           fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1347                    arg_type);
1348           abort (); /* ??? return NULL? */
1349         }
1350       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1351     }
1352   va_end (ap);
1353
1354   /* mach unspecified means "all" */
1355   if (machs == 0)
1356     machs = (1 << MAX_MACHS) - 1;
1357   /* base mach is always selected */
1358   machs |= 1;
1359   /* isa unspecified means "all" */
1360   if (isas == 0)
1361     isas = (1 << MAX_ISAS) - 1;
1362   if (endian == CGEN_ENDIAN_UNKNOWN)
1363     {
1364       /* ??? If target has only one, could have a default.  */
1365       fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1366       abort ();
1367     }
1368
1369   cd->isas = isas;
1370   cd->machs = machs;
1371   cd->endian = endian;
1372   /* FIXME: for the sparc case we can determine insn-endianness statically.
1373      The worry here is where both data and insn endian can be independently
1374      chosen, in which case this function will need another argument.
1375      Actually, will want to allow for more arguments in the future anyway.  */
1376   cd->insn_endian = endian;
1377
1378   /* Table (re)builder.  */
1379   cd->rebuild_tables = m32r_cgen_rebuild_tables;
1380   m32r_cgen_rebuild_tables (cd);
1381
1382   /* Default to not allowing signed overflow.  */
1383   cd->signed_overflow_ok_p = 0;
1384
1385   return (CGEN_CPU_DESC) cd;
1386 }
1387
1388 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1389    MACH_NAME is the bfd name of the mach.  */
1390
1391 CGEN_CPU_DESC
1392 m32r_cgen_cpu_open_1 (mach_name, endian)
1393      const char *mach_name;
1394      enum cgen_endian endian;
1395 {
1396   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1397                                CGEN_CPU_OPEN_ENDIAN, endian,
1398                                CGEN_CPU_OPEN_END);
1399 }
1400
1401 /* Close a cpu table.
1402    ??? This can live in a machine independent file, but there's currently
1403    no place to put this file (there's no libcgen).  libopcodes is the wrong
1404    place as some simulator ports use this but they don't use libopcodes.  */
1405
1406 void
1407 m32r_cgen_cpu_close (cd)
1408      CGEN_CPU_DESC cd;
1409 {
1410   if (cd->insn_table.init_entries)
1411     free ((CGEN_INSN *) cd->insn_table.init_entries);
1412   if (cd->hw_table.entries)
1413     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1414   free (cd);
1415 }
1416