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[binutils.git] / opcodes / m32r-ibld.c
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1 /* Instruction building/extraction support for m32r. -*- C -*-
3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
6 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
25 Keep that in mind. */
27 #include "sysdep.h"
28 #include <stdio.h>
29 #include "ansidecl.h"
30 #include "dis-asm.h"
31 #include "bfd.h"
32 #include "symcat.h"
33 #include "m32r-desc.h"
34 #include "m32r-opc.h"
35 #include "opintl.h"
36 #include "safe-ctype.h"
38 #undef min
39 #define min(a,b) ((a) < (b) ? (a) : (b))
40 #undef max
41 #define max(a,b) ((a) > (b) ? (a) : (b))
43 /* Used by the ifield rtx function. */
44 #define FLD(f) (fields->f)
46 static const char * insert_normal
47 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
48 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
49 static const char * insert_insn_normal
50 (CGEN_CPU_DESC, const CGEN_INSN *,
51 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
52 static int extract_normal
53 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
54 unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int, bfd_vma, long *);
56 static int extract_insn_normal
57 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
58 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
59 #if CGEN_INT_INSN_P
60 static void put_insn_int_value
61 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
62 #endif
63 #if ! CGEN_INT_INSN_P
64 static CGEN_INLINE void insert_1
65 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
66 static CGEN_INLINE int fill_cache
67 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
68 static CGEN_INLINE long extract_1
69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
70 #endif
72 /* Operand insertion. */
74 #if ! CGEN_INT_INSN_P
76 /* Subroutine of insert_normal. */
78 static CGEN_INLINE void
79 insert_1 (CGEN_CPU_DESC cd,
80 unsigned long value,
81 int start,
82 int length,
83 int word_length,
84 unsigned char *bufp)
86 unsigned long x,mask;
87 int shift;
89 x = cgen_get_insn_value (cd, bufp, word_length);
91 /* Written this way to avoid undefined behaviour. */
92 mask = (((1L << (length - 1)) - 1) << 1) | 1;
93 if (CGEN_INSN_LSB0_P)
94 shift = (start + 1) - length;
95 else
96 shift = (word_length - (start + length));
97 x = (x & ~(mask << shift)) | ((value & mask) << shift);
99 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
102 #endif /* ! CGEN_INT_INSN_P */
104 /* Default insertion routine.
106 ATTRS is a mask of the boolean attributes.
107 WORD_OFFSET is the offset in bits from the start of the insn of the value.
108 WORD_LENGTH is the length of the word in bits in which the value resides.
109 START is the starting bit number in the word, architecture origin.
110 LENGTH is the length of VALUE in bits.
111 TOTAL_LENGTH is the total length of the insn in bits.
113 The result is an error message or NULL if success. */
115 /* ??? This duplicates functionality with bfd's howto table and
116 bfd_install_relocation. */
117 /* ??? This doesn't handle bfd_vma's. Create another function when
118 necessary. */
120 static const char *
121 insert_normal (CGEN_CPU_DESC cd,
122 long value,
123 unsigned int attrs,
124 unsigned int word_offset,
125 unsigned int start,
126 unsigned int length,
127 unsigned int word_length,
128 unsigned int total_length,
129 CGEN_INSN_BYTES_PTR buffer)
131 static char errbuf[100];
132 /* Written this way to avoid undefined behaviour. */
133 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
135 /* If LENGTH is zero, this operand doesn't contribute to the value. */
136 if (length == 0)
137 return NULL;
139 #if 0
140 if (CGEN_INT_INSN_P
141 && word_offset != 0)
142 abort ();
143 #endif
145 if (word_length > 32)
146 abort ();
148 /* For architectures with insns smaller than the base-insn-bitsize,
149 word_length may be too big. */
150 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
152 if (word_offset == 0
153 && word_length > total_length)
154 word_length = total_length;
157 /* Ensure VALUE will fit. */
158 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
160 long minval = - (1L << (length - 1));
161 unsigned long maxval = mask;
163 if ((value > 0 && (unsigned long) value > maxval)
164 || value < minval)
166 /* xgettext:c-format */
167 sprintf (errbuf,
168 _("operand out of range (%ld not between %ld and %lu)"),
169 value, minval, maxval);
170 return errbuf;
173 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
175 unsigned long maxval = mask;
177 if ((unsigned long) value > maxval)
179 /* xgettext:c-format */
180 sprintf (errbuf,
181 _("operand out of range (%lu not between 0 and %lu)"),
182 value, maxval);
183 return errbuf;
186 else
188 if (! cgen_signed_overflow_ok_p (cd))
190 long minval = - (1L << (length - 1));
191 long maxval = (1L << (length - 1)) - 1;
193 if (value < minval || value > maxval)
195 sprintf
196 /* xgettext:c-format */
197 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
198 value, minval, maxval);
199 return errbuf;
204 #if CGEN_INT_INSN_P
207 int shift;
209 if (CGEN_INSN_LSB0_P)
210 shift = (word_offset + start + 1) - length;
211 else
212 shift = total_length - (word_offset + start + length);
213 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
216 #else /* ! CGEN_INT_INSN_P */
219 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
221 insert_1 (cd, value, start, length, word_length, bufp);
224 #endif /* ! CGEN_INT_INSN_P */
226 return NULL;
229 /* Default insn builder (insert handler).
230 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
231 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
232 recorded in host byte order, otherwise BUFFER is an array of bytes
233 and the value is recorded in target byte order).
234 The result is an error message or NULL if success. */
236 static const char *
237 insert_insn_normal (CGEN_CPU_DESC cd,
238 const CGEN_INSN * insn,
239 CGEN_FIELDS * fields,
240 CGEN_INSN_BYTES_PTR buffer,
241 bfd_vma pc)
243 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
244 unsigned long value;
245 const CGEN_SYNTAX_CHAR_TYPE * syn;
247 CGEN_INIT_INSERT (cd);
248 value = CGEN_INSN_BASE_VALUE (insn);
250 /* If we're recording insns as numbers (rather than a string of bytes),
251 target byte order handling is deferred until later. */
253 #if CGEN_INT_INSN_P
255 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
256 CGEN_FIELDS_BITSIZE (fields), value);
258 #else
260 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
261 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
262 value);
264 #endif /* ! CGEN_INT_INSN_P */
266 /* ??? It would be better to scan the format's fields.
267 Still need to be able to insert a value based on the operand though;
268 e.g. storing a branch displacement that got resolved later.
269 Needs more thought first. */
271 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
273 const char *errmsg;
275 if (CGEN_SYNTAX_CHAR_P (* syn))
276 continue;
278 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
279 fields, buffer, pc);
280 if (errmsg)
281 return errmsg;
284 return NULL;
287 #if CGEN_INT_INSN_P
288 /* Cover function to store an insn value into an integral insn. Must go here
289 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
291 static void
292 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
293 CGEN_INSN_BYTES_PTR buf,
294 int length,
295 int insn_length,
296 CGEN_INSN_INT value)
298 /* For architectures with insns smaller than the base-insn-bitsize,
299 length may be too big. */
300 if (length > insn_length)
301 *buf = value;
302 else
304 int shift = insn_length - length;
305 /* Written this way to avoid undefined behaviour. */
306 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
307 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
310 #endif
312 /* Operand extraction. */
314 #if ! CGEN_INT_INSN_P
316 /* Subroutine of extract_normal.
317 Ensure sufficient bytes are cached in EX_INFO.
318 OFFSET is the offset in bytes from the start of the insn of the value.
319 BYTES is the length of the needed value.
320 Returns 1 for success, 0 for failure. */
322 static CGEN_INLINE int
323 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
324 CGEN_EXTRACT_INFO *ex_info,
325 int offset,
326 int bytes,
327 bfd_vma pc)
329 /* It's doubtful that the middle part has already been fetched so
330 we don't optimize that case. kiss. */
331 unsigned int mask;
332 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
334 /* First do a quick check. */
335 mask = (1 << bytes) - 1;
336 if (((ex_info->valid >> offset) & mask) == mask)
337 return 1;
339 /* Search for the first byte we need to read. */
340 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
341 if (! (mask & ex_info->valid))
342 break;
344 if (bytes)
346 int status;
348 pc += offset;
349 status = (*info->read_memory_func)
350 (pc, ex_info->insn_bytes + offset, bytes, info);
352 if (status != 0)
354 (*info->memory_error_func) (status, pc, info);
355 return 0;
358 ex_info->valid |= ((1 << bytes) - 1) << offset;
361 return 1;
364 /* Subroutine of extract_normal. */
366 static CGEN_INLINE long
367 extract_1 (CGEN_CPU_DESC cd,
368 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
369 int start,
370 int length,
371 int word_length,
372 unsigned char *bufp,
373 bfd_vma pc ATTRIBUTE_UNUSED)
375 unsigned long x;
376 int shift;
377 #if 0
378 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
379 #endif
380 x = cgen_get_insn_value (cd, bufp, word_length);
382 if (CGEN_INSN_LSB0_P)
383 shift = (start + 1) - length;
384 else
385 shift = (word_length - (start + length));
386 return x >> shift;
389 #endif /* ! CGEN_INT_INSN_P */
391 /* Default extraction routine.
393 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
394 or sometimes less for cases like the m32r where the base insn size is 32
395 but some insns are 16 bits.
396 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
397 but for generality we take a bitmask of all of them.
398 WORD_OFFSET is the offset in bits from the start of the insn of the value.
399 WORD_LENGTH is the length of the word in bits in which the value resides.
400 START is the starting bit number in the word, architecture origin.
401 LENGTH is the length of VALUE in bits.
402 TOTAL_LENGTH is the total length of the insn in bits.
404 Returns 1 for success, 0 for failure. */
406 /* ??? The return code isn't properly used. wip. */
408 /* ??? This doesn't handle bfd_vma's. Create another function when
409 necessary. */
411 static int
412 extract_normal (CGEN_CPU_DESC cd,
413 #if ! CGEN_INT_INSN_P
414 CGEN_EXTRACT_INFO *ex_info,
415 #else
416 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
417 #endif
418 CGEN_INSN_INT insn_value,
419 unsigned int attrs,
420 unsigned int word_offset,
421 unsigned int start,
422 unsigned int length,
423 unsigned int word_length,
424 unsigned int total_length,
425 #if ! CGEN_INT_INSN_P
426 bfd_vma pc,
427 #else
428 bfd_vma pc ATTRIBUTE_UNUSED,
429 #endif
430 long *valuep)
432 long value, mask;
434 /* If LENGTH is zero, this operand doesn't contribute to the value
435 so give it a standard value of zero. */
436 if (length == 0)
438 *valuep = 0;
439 return 1;
442 #if 0
443 if (CGEN_INT_INSN_P
444 && word_offset != 0)
445 abort ();
446 #endif
448 if (word_length > 32)
449 abort ();
451 /* For architectures with insns smaller than the insn-base-bitsize,
452 word_length may be too big. */
453 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
455 if (word_offset == 0
456 && word_length > total_length)
457 word_length = total_length;
460 /* Does the value reside in INSN_VALUE, and at the right alignment? */
462 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
464 if (CGEN_INSN_LSB0_P)
465 value = insn_value >> ((word_offset + start + 1) - length);
466 else
467 value = insn_value >> (total_length - ( word_offset + start + length));
470 #if ! CGEN_INT_INSN_P
472 else
474 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
476 if (word_length > 32)
477 abort ();
479 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
480 return 0;
482 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
485 #endif /* ! CGEN_INT_INSN_P */
487 /* Written this way to avoid undefined behaviour. */
488 mask = (((1L << (length - 1)) - 1) << 1) | 1;
490 value &= mask;
491 /* sign extend? */
492 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
493 && (value & (1L << (length - 1))))
494 value |= ~mask;
496 *valuep = value;
498 return 1;
501 /* Default insn extractor.
503 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
504 The extracted fields are stored in FIELDS.
505 EX_INFO is used to handle reading variable length insns.
506 Return the length of the insn in bits, or 0 if no match,
507 or -1 if an error occurs fetching data (memory_error_func will have
508 been called). */
510 static int
511 extract_insn_normal (CGEN_CPU_DESC cd,
512 const CGEN_INSN *insn,
513 CGEN_EXTRACT_INFO *ex_info,
514 CGEN_INSN_INT insn_value,
515 CGEN_FIELDS *fields,
516 bfd_vma pc)
518 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
519 const CGEN_SYNTAX_CHAR_TYPE *syn;
521 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
523 CGEN_INIT_EXTRACT (cd);
525 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
527 int length;
529 if (CGEN_SYNTAX_CHAR_P (*syn))
530 continue;
532 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
533 ex_info, insn_value, fields, pc);
534 if (length <= 0)
535 return length;
538 /* We recognized and successfully extracted this insn. */
539 return CGEN_INSN_BITSIZE (insn);
542 /* machine generated code added here */
544 const char * m32r_cgen_insert_operand
545 PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
547 /* Main entry point for operand insertion.
549 This function is basically just a big switch statement. Earlier versions
550 used tables to look up the function to use, but
551 - if the table contains both assembler and disassembler functions then
552 the disassembler contains much of the assembler and vice-versa,
553 - there's a lot of inlining possibilities as things grow,
554 - using a switch statement avoids the function call overhead.
556 This function could be moved into `parse_insn_normal', but keeping it
557 separate makes clear the interface between `parse_insn_normal' and each of
558 the handlers. It's also needed by GAS to insert operands that couldn't be
559 resolved during parsing. */
561 const char *
562 m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
563 CGEN_CPU_DESC cd;
564 int opindex;
565 CGEN_FIELDS * fields;
566 CGEN_INSN_BYTES_PTR buffer;
567 bfd_vma pc ATTRIBUTE_UNUSED;
569 const char * errmsg = NULL;
570 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
572 switch (opindex)
574 case M32R_OPERAND_ACC :
575 errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
576 break;
577 case M32R_OPERAND_ACCD :
578 errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
579 break;
580 case M32R_OPERAND_ACCS :
581 errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
582 break;
583 case M32R_OPERAND_DCR :
584 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
585 break;
586 case M32R_OPERAND_DISP16 :
588 long value = fields->f_disp16;
589 value = ((int) (((value) - (pc))) >> (2));
590 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
592 break;
593 case M32R_OPERAND_DISP24 :
595 long value = fields->f_disp24;
596 value = ((int) (((value) - (pc))) >> (2));
597 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
599 break;
600 case M32R_OPERAND_DISP8 :
602 long value = fields->f_disp8;
603 value = ((int) (((value) - (((pc) & (-4))))) >> (2));
604 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
606 break;
607 case M32R_OPERAND_DR :
608 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
609 break;
610 case M32R_OPERAND_HASH :
611 break;
612 case M32R_OPERAND_HI16 :
613 errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
614 break;
615 case M32R_OPERAND_IMM1 :
617 long value = fields->f_imm1;
618 value = ((value) - (1));
619 errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
621 break;
622 case M32R_OPERAND_SCR :
623 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
624 break;
625 case M32R_OPERAND_SIMM16 :
626 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
627 break;
628 case M32R_OPERAND_SIMM8 :
629 errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
630 break;
631 case M32R_OPERAND_SLO16 :
632 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
633 break;
634 case M32R_OPERAND_SR :
635 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
636 break;
637 case M32R_OPERAND_SRC1 :
638 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
639 break;
640 case M32R_OPERAND_SRC2 :
641 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
642 break;
643 case M32R_OPERAND_UIMM16 :
644 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
645 break;
646 case M32R_OPERAND_UIMM24 :
647 errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
648 break;
649 case M32R_OPERAND_UIMM4 :
650 errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
651 break;
652 case M32R_OPERAND_UIMM5 :
653 errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
654 break;
655 case M32R_OPERAND_ULO16 :
656 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
657 break;
659 default :
660 /* xgettext:c-format */
661 fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
662 opindex);
663 abort ();
666 return errmsg;
669 int m32r_cgen_extract_operand
670 PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
671 CGEN_FIELDS *, bfd_vma));
673 /* Main entry point for operand extraction.
674 The result is <= 0 for error, >0 for success.
675 ??? Actual values aren't well defined right now.
677 This function is basically just a big switch statement. Earlier versions
678 used tables to look up the function to use, but
679 - if the table contains both assembler and disassembler functions then
680 the disassembler contains much of the assembler and vice-versa,
681 - there's a lot of inlining possibilities as things grow,
682 - using a switch statement avoids the function call overhead.
684 This function could be moved into `print_insn_normal', but keeping it
685 separate makes clear the interface between `print_insn_normal' and each of
686 the handlers. */
689 m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
690 CGEN_CPU_DESC cd;
691 int opindex;
692 CGEN_EXTRACT_INFO *ex_info;
693 CGEN_INSN_INT insn_value;
694 CGEN_FIELDS * fields;
695 bfd_vma pc;
697 /* Assume success (for those operands that are nops). */
698 int length = 1;
699 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
701 switch (opindex)
703 case M32R_OPERAND_ACC :
704 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
705 break;
706 case M32R_OPERAND_ACCD :
707 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
708 break;
709 case M32R_OPERAND_ACCS :
710 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
711 break;
712 case M32R_OPERAND_DCR :
713 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
714 break;
715 case M32R_OPERAND_DISP16 :
717 long value;
718 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
719 value = ((((value) << (2))) + (pc));
720 fields->f_disp16 = value;
722 break;
723 case M32R_OPERAND_DISP24 :
725 long value;
726 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
727 value = ((((value) << (2))) + (pc));
728 fields->f_disp24 = value;
730 break;
731 case M32R_OPERAND_DISP8 :
733 long value;
734 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
735 value = ((((value) << (2))) + (((pc) & (-4))));
736 fields->f_disp8 = value;
738 break;
739 case M32R_OPERAND_DR :
740 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
741 break;
742 case M32R_OPERAND_HASH :
743 break;
744 case M32R_OPERAND_HI16 :
745 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
746 break;
747 case M32R_OPERAND_IMM1 :
749 long value;
750 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
751 value = ((value) + (1));
752 fields->f_imm1 = value;
754 break;
755 case M32R_OPERAND_SCR :
756 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
757 break;
758 case M32R_OPERAND_SIMM16 :
759 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
760 break;
761 case M32R_OPERAND_SIMM8 :
762 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
763 break;
764 case M32R_OPERAND_SLO16 :
765 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
766 break;
767 case M32R_OPERAND_SR :
768 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
769 break;
770 case M32R_OPERAND_SRC1 :
771 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
772 break;
773 case M32R_OPERAND_SRC2 :
774 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
775 break;
776 case M32R_OPERAND_UIMM16 :
777 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
778 break;
779 case M32R_OPERAND_UIMM24 :
780 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
781 break;
782 case M32R_OPERAND_UIMM4 :
783 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
784 break;
785 case M32R_OPERAND_UIMM5 :
786 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
787 break;
788 case M32R_OPERAND_ULO16 :
789 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
790 break;
792 default :
793 /* xgettext:c-format */
794 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
795 opindex);
796 abort ();
799 return length;
802 cgen_insert_fn * const m32r_cgen_insert_handlers[] =
804 insert_insn_normal,
807 cgen_extract_fn * const m32r_cgen_extract_handlers[] =
809 extract_insn_normal,
812 int m32r_cgen_get_int_operand
813 PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
814 bfd_vma m32r_cgen_get_vma_operand
815 PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
817 /* Getting values from cgen_fields is handled by a collection of functions.
818 They are distinguished by the type of the VALUE argument they return.
819 TODO: floating point, inlining support, remove cases where result type
820 not appropriate. */
823 m32r_cgen_get_int_operand (cd, opindex, fields)
824 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
825 int opindex;
826 const CGEN_FIELDS * fields;
828 int value;
830 switch (opindex)
832 case M32R_OPERAND_ACC :
833 value = fields->f_acc;
834 break;
835 case M32R_OPERAND_ACCD :
836 value = fields->f_accd;
837 break;
838 case M32R_OPERAND_ACCS :
839 value = fields->f_accs;
840 break;
841 case M32R_OPERAND_DCR :
842 value = fields->f_r1;
843 break;
844 case M32R_OPERAND_DISP16 :
845 value = fields->f_disp16;
846 break;
847 case M32R_OPERAND_DISP24 :
848 value = fields->f_disp24;
849 break;
850 case M32R_OPERAND_DISP8 :
851 value = fields->f_disp8;
852 break;
853 case M32R_OPERAND_DR :
854 value = fields->f_r1;
855 break;
856 case M32R_OPERAND_HASH :
857 value = 0;
858 break;
859 case M32R_OPERAND_HI16 :
860 value = fields->f_hi16;
861 break;
862 case M32R_OPERAND_IMM1 :
863 value = fields->f_imm1;
864 break;
865 case M32R_OPERAND_SCR :
866 value = fields->f_r2;
867 break;
868 case M32R_OPERAND_SIMM16 :
869 value = fields->f_simm16;
870 break;
871 case M32R_OPERAND_SIMM8 :
872 value = fields->f_simm8;
873 break;
874 case M32R_OPERAND_SLO16 :
875 value = fields->f_simm16;
876 break;
877 case M32R_OPERAND_SR :
878 value = fields->f_r2;
879 break;
880 case M32R_OPERAND_SRC1 :
881 value = fields->f_r1;
882 break;
883 case M32R_OPERAND_SRC2 :
884 value = fields->f_r2;
885 break;
886 case M32R_OPERAND_UIMM16 :
887 value = fields->f_uimm16;
888 break;
889 case M32R_OPERAND_UIMM24 :
890 value = fields->f_uimm24;
891 break;
892 case M32R_OPERAND_UIMM4 :
893 value = fields->f_uimm4;
894 break;
895 case M32R_OPERAND_UIMM5 :
896 value = fields->f_uimm5;
897 break;
898 case M32R_OPERAND_ULO16 :
899 value = fields->f_uimm16;
900 break;
902 default :
903 /* xgettext:c-format */
904 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
905 opindex);
906 abort ();
909 return value;
912 bfd_vma
913 m32r_cgen_get_vma_operand (cd, opindex, fields)
914 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
915 int opindex;
916 const CGEN_FIELDS * fields;
918 bfd_vma value;
920 switch (opindex)
922 case M32R_OPERAND_ACC :
923 value = fields->f_acc;
924 break;
925 case M32R_OPERAND_ACCD :
926 value = fields->f_accd;
927 break;
928 case M32R_OPERAND_ACCS :
929 value = fields->f_accs;
930 break;
931 case M32R_OPERAND_DCR :
932 value = fields->f_r1;
933 break;
934 case M32R_OPERAND_DISP16 :
935 value = fields->f_disp16;
936 break;
937 case M32R_OPERAND_DISP24 :
938 value = fields->f_disp24;
939 break;
940 case M32R_OPERAND_DISP8 :
941 value = fields->f_disp8;
942 break;
943 case M32R_OPERAND_DR :
944 value = fields->f_r1;
945 break;
946 case M32R_OPERAND_HASH :
947 value = 0;
948 break;
949 case M32R_OPERAND_HI16 :
950 value = fields->f_hi16;
951 break;
952 case M32R_OPERAND_IMM1 :
953 value = fields->f_imm1;
954 break;
955 case M32R_OPERAND_SCR :
956 value = fields->f_r2;
957 break;
958 case M32R_OPERAND_SIMM16 :
959 value = fields->f_simm16;
960 break;
961 case M32R_OPERAND_SIMM8 :
962 value = fields->f_simm8;
963 break;
964 case M32R_OPERAND_SLO16 :
965 value = fields->f_simm16;
966 break;
967 case M32R_OPERAND_SR :
968 value = fields->f_r2;
969 break;
970 case M32R_OPERAND_SRC1 :
971 value = fields->f_r1;
972 break;
973 case M32R_OPERAND_SRC2 :
974 value = fields->f_r2;
975 break;
976 case M32R_OPERAND_UIMM16 :
977 value = fields->f_uimm16;
978 break;
979 case M32R_OPERAND_UIMM24 :
980 value = fields->f_uimm24;
981 break;
982 case M32R_OPERAND_UIMM4 :
983 value = fields->f_uimm4;
984 break;
985 case M32R_OPERAND_UIMM5 :
986 value = fields->f_uimm5;
987 break;
988 case M32R_OPERAND_ULO16 :
989 value = fields->f_uimm16;
990 break;
992 default :
993 /* xgettext:c-format */
994 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
995 opindex);
996 abort ();
999 return value;
1002 void m32r_cgen_set_int_operand
1003 PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
1004 void m32r_cgen_set_vma_operand
1005 PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
1007 /* Stuffing values in cgen_fields is handled by a collection of functions.
1008 They are distinguished by the type of the VALUE argument they accept.
1009 TODO: floating point, inlining support, remove cases where argument type
1010 not appropriate. */
1012 void
1013 m32r_cgen_set_int_operand (cd, opindex, fields, value)
1014 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
1015 int opindex;
1016 CGEN_FIELDS * fields;
1017 int value;
1019 switch (opindex)
1021 case M32R_OPERAND_ACC :
1022 fields->f_acc = value;
1023 break;
1024 case M32R_OPERAND_ACCD :
1025 fields->f_accd = value;
1026 break;
1027 case M32R_OPERAND_ACCS :
1028 fields->f_accs = value;
1029 break;
1030 case M32R_OPERAND_DCR :
1031 fields->f_r1 = value;
1032 break;
1033 case M32R_OPERAND_DISP16 :
1034 fields->f_disp16 = value;
1035 break;
1036 case M32R_OPERAND_DISP24 :
1037 fields->f_disp24 = value;
1038 break;
1039 case M32R_OPERAND_DISP8 :
1040 fields->f_disp8 = value;
1041 break;
1042 case M32R_OPERAND_DR :
1043 fields->f_r1 = value;
1044 break;
1045 case M32R_OPERAND_HASH :
1046 break;
1047 case M32R_OPERAND_HI16 :
1048 fields->f_hi16 = value;
1049 break;
1050 case M32R_OPERAND_IMM1 :
1051 fields->f_imm1 = value;
1052 break;
1053 case M32R_OPERAND_SCR :
1054 fields->f_r2 = value;
1055 break;
1056 case M32R_OPERAND_SIMM16 :
1057 fields->f_simm16 = value;
1058 break;
1059 case M32R_OPERAND_SIMM8 :
1060 fields->f_simm8 = value;
1061 break;
1062 case M32R_OPERAND_SLO16 :
1063 fields->f_simm16 = value;
1064 break;
1065 case M32R_OPERAND_SR :
1066 fields->f_r2 = value;
1067 break;
1068 case M32R_OPERAND_SRC1 :
1069 fields->f_r1 = value;
1070 break;
1071 case M32R_OPERAND_SRC2 :
1072 fields->f_r2 = value;
1073 break;
1074 case M32R_OPERAND_UIMM16 :
1075 fields->f_uimm16 = value;
1076 break;
1077 case M32R_OPERAND_UIMM24 :
1078 fields->f_uimm24 = value;
1079 break;
1080 case M32R_OPERAND_UIMM4 :
1081 fields->f_uimm4 = value;
1082 break;
1083 case M32R_OPERAND_UIMM5 :
1084 fields->f_uimm5 = value;
1085 break;
1086 case M32R_OPERAND_ULO16 :
1087 fields->f_uimm16 = value;
1088 break;
1090 default :
1091 /* xgettext:c-format */
1092 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
1093 opindex);
1094 abort ();
1098 void
1099 m32r_cgen_set_vma_operand (cd, opindex, fields, value)
1100 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
1101 int opindex;
1102 CGEN_FIELDS * fields;
1103 bfd_vma value;
1105 switch (opindex)
1107 case M32R_OPERAND_ACC :
1108 fields->f_acc = value;
1109 break;
1110 case M32R_OPERAND_ACCD :
1111 fields->f_accd = value;
1112 break;
1113 case M32R_OPERAND_ACCS :
1114 fields->f_accs = value;
1115 break;
1116 case M32R_OPERAND_DCR :
1117 fields->f_r1 = value;
1118 break;
1119 case M32R_OPERAND_DISP16 :
1120 fields->f_disp16 = value;
1121 break;
1122 case M32R_OPERAND_DISP24 :
1123 fields->f_disp24 = value;
1124 break;
1125 case M32R_OPERAND_DISP8 :
1126 fields->f_disp8 = value;
1127 break;
1128 case M32R_OPERAND_DR :
1129 fields->f_r1 = value;
1130 break;
1131 case M32R_OPERAND_HASH :
1132 break;
1133 case M32R_OPERAND_HI16 :
1134 fields->f_hi16 = value;
1135 break;
1136 case M32R_OPERAND_IMM1 :
1137 fields->f_imm1 = value;
1138 break;
1139 case M32R_OPERAND_SCR :
1140 fields->f_r2 = value;
1141 break;
1142 case M32R_OPERAND_SIMM16 :
1143 fields->f_simm16 = value;
1144 break;
1145 case M32R_OPERAND_SIMM8 :
1146 fields->f_simm8 = value;
1147 break;
1148 case M32R_OPERAND_SLO16 :
1149 fields->f_simm16 = value;
1150 break;
1151 case M32R_OPERAND_SR :
1152 fields->f_r2 = value;
1153 break;
1154 case M32R_OPERAND_SRC1 :
1155 fields->f_r1 = value;
1156 break;
1157 case M32R_OPERAND_SRC2 :
1158 fields->f_r2 = value;
1159 break;
1160 case M32R_OPERAND_UIMM16 :
1161 fields->f_uimm16 = value;
1162 break;
1163 case M32R_OPERAND_UIMM24 :
1164 fields->f_uimm24 = value;
1165 break;
1166 case M32R_OPERAND_UIMM4 :
1167 fields->f_uimm4 = value;
1168 break;
1169 case M32R_OPERAND_UIMM5 :
1170 fields->f_uimm5 = value;
1171 break;
1172 case M32R_OPERAND_ULO16 :
1173 fields->f_uimm16 = value;
1174 break;
1176 default :
1177 /* xgettext:c-format */
1178 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1179 opindex);
1180 abort ();
1184 /* Function to call before using the instruction builder tables. */
1186 void
1187 m32r_cgen_init_ibld_table (cd)
1188 CGEN_CPU_DESC cd;
1190 cd->insert_handlers = & m32r_cgen_insert_handlers[0];
1191 cd->extract_handlers = & m32r_cgen_extract_handlers[0];
1193 cd->insert_operand = m32r_cgen_insert_operand;
1194 cd->extract_operand = m32r_cgen_extract_operand;
1196 cd->get_int_operand = m32r_cgen_get_int_operand;
1197 cd->set_int_operand = m32r_cgen_set_int_operand;
1198 cd->get_vma_operand = m32r_cgen_get_vma_operand;
1199 cd->set_vma_operand = m32r_cgen_set_vma_operand;