1 2010-07-27 DJ Delorie <dj@redhat.com>
3 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
5 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
6 Ina Pandit <ina.pandit@kpitcummins.com>
8 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
9 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
11 Remove PROCESSOR_V850EA support.
12 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
13 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
14 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
15 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
16 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
18 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
20 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
23 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
25 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
26 (MIPS16_INSN_BRANCH): Rename to...
27 (MIPS16_INSN_COND_BRANCH): ... this.
29 2010-07-03 Alan Modra <amodra@gmail.com>
31 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
32 Renumber other PPC_OPCODE defines.
34 2010-07-03 Alan Modra <amodra@gmail.com>
36 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
38 2010-06-29 Alan Modra <amodra@gmail.com>
40 * maxq.h: Delete file.
42 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
44 * ppc.h (PPC_OPCODE_E500): Define.
46 2010-05-26 Catherine Moore <clm@codesourcery.com>
48 * opcode/mips.h (INSN_MIPS16): Remove.
50 2010-04-21 Joseph Myers <joseph@codesourcery.com>
52 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
54 2010-04-15 Nick Clifton <nickc@redhat.com>
56 * alpha.h: Update copyright notice to use GPLv3.
76 * m68hc11.h: Likewise.
82 * mn10200.h: Likewise.
83 * mn10300.h: Likewise.
95 * score-datadep.h: Likewise.
96 * score-inst.h: Likewise.
98 * spu-insns.h: Likewise.
102 * tic54x.h: Likewise.
107 2010-03-25 Joseph Myers <joseph@codesourcery.com>
109 * tic6x-control-registers.h, tic6x-insn-formats.h,
110 tic6x-opcode-table.h, tic6x.h: New.
112 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
114 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
116 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
118 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
120 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
122 * ia64.h (ia64_find_opcode): Remove argument name.
123 (ia64_find_next_opcode): Likewise.
124 (ia64_dis_opcode): Likewise.
125 (ia64_free_opcode): Likewise.
126 (ia64_find_dependency): Likewise.
128 2009-11-22 Doug Evans <dje@sebabeach.org>
130 * cgen.h: Include bfd_stdint.h.
131 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
133 2009-11-18 Paul Brook <paul@codesourcery.com>
135 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
137 2009-11-17 Paul Brook <paul@codesourcery.com>
138 Daniel Jacobowitz <dan@codesourcery.com>
140 * arm.h (ARM_EXT_V6_DSP): Define.
141 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
142 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
144 2009-11-04 DJ Delorie <dj@redhat.com>
146 * rx.h (rx_decode_opcode) (mvtipl): Add.
147 (mvtcp, mvfcp, opecp): Remove.
149 2009-11-02 Paul Brook <paul@codesourcery.com>
151 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
152 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
153 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
154 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
155 FPU_ARCH_NEON_VFP_V4): Define.
157 2009-10-23 Doug Evans <dje@sebabeach.org>
159 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
160 * cgen.h: Update. Improve multi-inclusion macro name.
162 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
164 * ppc.h (PPC_OPCODE_476): Define.
166 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
168 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
170 2009-09-29 DJ Delorie <dj@redhat.com>
174 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
176 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
178 2009-09-21 Ben Elliston <bje@au.ibm.com>
180 * ppc.h (PPC_OPCODE_PPCA2): New.
182 2009-09-05 Martin Thuresson <martin@mtme.org>
184 * ia64.h (struct ia64_operand): Renamed member class to op_class.
186 2009-08-29 Martin Thuresson <martin@mtme.org>
188 * tic30.h (template): Rename type template to
189 insn_template. Updated code to use new name.
190 * tic54x.h (template): Rename type template to
193 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
195 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
197 2009-06-11 Anthony Green <green@moxielogic.com>
199 * moxie.h (MOXIE_F3_PCREL): Define.
200 (moxie_form3_opc_info): Grow.
202 2009-06-06 Anthony Green <green@moxielogic.com>
204 * moxie.h (MOXIE_F1_M): Define.
206 2009-04-15 Anthony Green <green@moxielogic.com>
210 2009-04-06 DJ Delorie <dj@redhat.com>
212 * h8300.h: Add relaxation attributes to MOVA opcodes.
214 2009-03-10 Alan Modra <amodra@bigpond.net.au>
216 * ppc.h (ppc_parse_cpu): Declare.
218 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
220 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
221 and _IMM11 for mbitclr and mbitset.
222 * score-datadep.h: Update dependency information.
224 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
226 * ppc.h (PPC_OPCODE_POWER7): New.
228 2009-02-06 Doug Evans <dje@google.com>
230 * i386.h: Add comment regarding sse* insns and prefixes.
232 2009-02-03 Sandip Matte <sandip@rmicorp.com>
234 * mips.h (INSN_XLR): Define.
235 (INSN_CHIP_MASK): Update.
237 (OPCODE_IS_MEMBER): Update.
238 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
240 2009-01-28 Doug Evans <dje@google.com>
242 * opcode/i386.h: Add multiple inclusion protection.
243 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
244 (EDI_REG_NUM): New macros.
245 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
246 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
247 (REX_PREFIX_P): New macro.
249 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
251 * ppc.h (struct powerpc_opcode): New field "deprecated".
252 (PPC_OPCODE_NOPOWER4): Delete.
254 2008-11-28 Joshua Kinard <kumba@gentoo.org>
256 * mips.h: Define CPU_R14000, CPU_R16000.
257 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
259 2008-11-18 Catherine Moore <clm@codesourcery.com>
261 * arm.h (FPU_NEON_FP16): New.
262 (FPU_ARCH_NEON_FP16): New.
264 2008-11-06 Chao-ying Fu <fu@mips.com>
266 * mips.h: Doucument '1' for 5-bit sync type.
268 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
270 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
273 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
275 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
277 2008-07-30 Michael J. Eager <eager@eagercon.com>
279 * ppc.h (PPC_OPCODE_405): Define.
280 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
282 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
284 * ppc.h (ppc_cpu_t): New typedef.
285 (struct powerpc_opcode <flags>): Use it.
286 (struct powerpc_operand <insert, extract>): Likewise.
287 (struct powerpc_macro <flags>): Likewise.
289 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
291 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
292 Update comment before MIPS16 field descriptors to mention MIPS16.
293 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
295 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
296 New bit masks and shift counts for cins and exts.
298 * mips.h: Document new field descriptors +Q.
299 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
301 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
303 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
304 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
306 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
308 * ppc.h: (PPC_OPCODE_E500MC): New.
310 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
312 * i386.h (MAX_OPERANDS): Set to 5.
313 (MAX_MNEM_SIZE): Changed to 20.
315 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
317 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
319 2008-03-09 Paul Brook <paul@codesourcery.com>
321 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
323 2008-03-04 Paul Brook <paul@codesourcery.com>
325 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
326 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
327 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
329 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
330 Nick Clifton <nickc@redhat.com>
333 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
334 with a 32-bit displacement but without the top bit of the 4th byte
337 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
339 * cr16.h (cr16_num_optab): Declared.
341 2008-02-14 Hakan Ardo <hakan@debian.org>
344 * avr.h (AVR_ISA_2xxe): Define.
346 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
348 * mips.h: Update copyright.
349 (INSN_CHIP_MASK): New macro.
350 (INSN_OCTEON): New macro.
351 (CPU_OCTEON): New macro.
352 (OPCODE_IS_MEMBER): Handle Octeon instructions.
354 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
356 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
358 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
360 * avr.h (AVR_ISA_USB162): Add new opcode set.
361 (AVR_ISA_AVR3): Likewise.
363 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
365 * mips.h (INSN_LOONGSON_2E): New.
366 (INSN_LOONGSON_2F): New.
367 (CPU_LOONGSON_2E): New.
368 (CPU_LOONGSON_2F): New.
369 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
371 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
373 * mips.h (INSN_ISA*): Redefine certain values as an
374 enumeration. Update comments.
375 (mips_isa_table): New.
376 (ISA_MIPS*): Redefine to match enumeration.
377 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
380 2007-08-08 Ben Elliston <bje@au.ibm.com>
382 * ppc.h (PPC_OPCODE_PPCPS): New.
384 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
386 * m68k.h: Document j K & E.
388 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
390 * cr16.h: New file for CR16 target.
392 2007-05-02 Alan Modra <amodra@bigpond.net.au>
394 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
396 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
398 * m68k.h (mcfisa_c): New.
399 (mcfusp, mcf_mask): Adjust.
401 2007-04-20 Alan Modra <amodra@bigpond.net.au>
403 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
404 (num_powerpc_operands): Declare.
405 (PPC_OPERAND_SIGNED et al): Redefine as hex.
406 (PPC_OPERAND_PLUS1): Define.
408 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
410 * i386.h (REX_MODE64): Renamed to ...
412 (REX_EXTX): Renamed to ...
414 (REX_EXTY): Renamed to ...
416 (REX_EXTZ): Renamed to ...
419 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
421 * i386.h: Add entries from config/tc-i386.h and move tables
422 to opcodes/i386-opc.h.
424 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
426 * i386.h (FloatDR): Removed.
427 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
429 2007-03-01 Alan Modra <amodra@bigpond.net.au>
431 * spu-insns.h: Add soma double-float insns.
433 2007-02-20 Thiemo Seufer <ths@mips.com>
434 Chao-Ying Fu <fu@mips.com>
436 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
437 (INSN_DSPR2): Add flag for DSP R2 instructions.
438 (M_BALIGN): New macro.
440 2007-02-14 Alan Modra <amodra@bigpond.net.au>
442 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
443 and Seg3ShortFrom with Shortform.
445 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
448 * i386.h (i386_optab): Put the real "test" before the pseudo
451 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
453 * m68k.h (m68010up): OR fido_a.
455 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
457 * m68k.h (fido_a): New.
459 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
461 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
462 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
465 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
467 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
469 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
471 * score-inst.h (enum score_insn_type): Add Insn_internal.
473 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
474 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
475 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
476 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
477 Alan Modra <amodra@bigpond.net.au>
479 * spu-insns.h: New file.
482 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
484 * ppc.h (PPC_OPCODE_CELL): Define.
486 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
488 * i386.h : Modify opcode to support for the change in POPCNT opcode
489 in amdfam10 architecture.
491 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
493 * i386.h: Replace CpuMNI with CpuSSSE3.
495 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
496 Joseph Myers <joseph@codesourcery.com>
497 Ian Lance Taylor <ian@wasabisystems.com>
498 Ben Elliston <bje@wasabisystems.com>
500 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
502 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
504 * score-datadep.h: New file.
505 * score-inst.h: New file.
507 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
509 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
510 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
513 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
514 Michael Meissner <michael.meissner@amd.com>
516 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
518 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
520 * i386.h (i386_optab): Add "nop" with memory reference.
522 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
524 * i386.h (i386_optab): Update comment for 64bit NOP.
526 2006-06-06 Ben Elliston <bje@au.ibm.com>
527 Anton Blanchard <anton@samba.org>
529 * ppc.h (PPC_OPCODE_POWER6): Define.
532 2006-06-05 Thiemo Seufer <ths@mips.com>
534 * mips.h: Improve description of MT flags.
536 2006-05-25 Richard Sandiford <richard@codesourcery.com>
538 * m68k.h (mcf_mask): Define.
540 2006-05-05 Thiemo Seufer <ths@mips.com>
541 David Ung <davidu@mips.com>
543 * mips.h (enum): Add macro M_CACHE_AB.
545 2006-05-04 Thiemo Seufer <ths@mips.com>
546 Nigel Stephens <nigel@mips.com>
547 David Ung <davidu@mips.com>
549 * mips.h: Add INSN_SMARTMIPS define.
551 2006-04-30 Thiemo Seufer <ths@mips.com>
552 David Ung <davidu@mips.com>
554 * mips.h: Defines udi bits and masks. Add description of
555 characters which may appear in the args field of udi
558 2006-04-26 Thiemo Seufer <ths@networkno.de>
560 * mips.h: Improve comments describing the bitfield instruction
563 2006-04-26 Julian Brown <julian@codesourcery.com>
565 * arm.h (FPU_VFP_EXT_V3): Define constant.
566 (FPU_NEON_EXT_V1): Likewise.
567 (FPU_VFP_HARD): Update.
568 (FPU_VFP_V3): Define macro.
569 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
571 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
573 * avr.h (AVR_ISA_PWMx): New.
575 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
577 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
578 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
579 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
580 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
581 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
583 2006-03-10 Paul Brook <paul@codesourcery.com>
585 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
587 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
589 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
590 first. Correct mask of bb "B" opcode.
592 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
594 * i386.h (i386_optab): Support Intel Merom New Instructions.
596 2006-02-24 Paul Brook <paul@codesourcery.com>
598 * arm.h: Add V7 feature bits.
600 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
602 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
604 2006-01-31 Paul Brook <paul@codesourcery.com>
605 Richard Earnshaw <rearnsha@arm.com>
607 * arm.h: Use ARM_CPU_FEATURE.
608 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
609 (arm_feature_set): Change to a structure.
610 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
611 ARM_FEATURE): New macros.
613 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
615 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
616 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
617 (ADD_PC_INCR_OPCODE): Don't define.
619 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
622 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
624 2005-11-14 David Ung <davidu@mips.com>
626 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
627 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
628 save/restore encoding of the args field.
630 2005-10-28 Dave Brolley <brolley@redhat.com>
632 Contribute the following changes:
633 2005-02-16 Dave Brolley <brolley@redhat.com>
635 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
636 cgen_isa_mask_* to cgen_bitset_*.
639 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
641 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
642 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
643 (CGEN_CPU_TABLE): Make isas a ponter.
645 2003-09-29 Dave Brolley <brolley@redhat.com>
647 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
648 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
649 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
651 2002-12-13 Dave Brolley <brolley@redhat.com>
653 * cgen.h (symcat.h): #include it.
654 (cgen-bitset.h): #include it.
655 (CGEN_ATTR_VALUE_TYPE): Now a union.
656 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
657 (CGEN_ATTR_ENTRY): 'value' now unsigned.
658 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
659 * cgen-bitset.h: New file.
661 2005-09-30 Catherine Moore <clm@cm00re.com>
665 2005-10-24 Jan Beulich <jbeulich@novell.com>
667 * ia64.h (enum ia64_opnd): Move memory operand out of set of
670 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
672 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
673 Add FLAG_STRICT to pa10 ftest opcode.
675 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
677 * hppa.h (pa_opcodes): Remove lha entries.
679 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
681 * hppa.h (FLAG_STRICT): Revise comment.
682 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
683 before corresponding pa11 opcodes. Add strict pa10 register-immediate
686 2005-09-30 Catherine Moore <clm@cm00re.com>
690 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
692 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
694 2005-09-06 Chao-ying Fu <fu@mips.com>
696 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
697 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
699 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
700 (INSN_ASE_MASK): Update to include INSN_MT.
701 (INSN_MT): New define for MT ASE.
703 2005-08-25 Chao-ying Fu <fu@mips.com>
705 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
706 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
707 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
708 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
709 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
710 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
712 (INSN_DSP): New define for DSP ASE.
714 2005-08-18 Alan Modra <amodra@bigpond.net.au>
718 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
720 * ppc.h (PPC_OPCODE_E300): Define.
722 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
724 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
726 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
729 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
732 2005-07-27 Jan Beulich <jbeulich@novell.com>
734 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
735 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
736 Add movq-s as 64-bit variants of movd-s.
738 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
740 * hppa.h: Fix punctuation in comment.
742 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
743 implicit space-register addressing. Set space-register bits on opcodes
744 using implicit space-register addressing. Add various missing pa20
745 long-immediate opcodes. Remove various opcodes using implicit 3-bit
746 space-register addressing. Use "fE" instead of "fe" in various
749 2005-07-18 Jan Beulich <jbeulich@novell.com>
751 * i386.h (i386_optab): Operands of aam and aad are unsigned.
753 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
755 * i386.h (i386_optab): Support Intel VMX Instructions.
757 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
759 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
761 2005-07-05 Jan Beulich <jbeulich@novell.com>
763 * i386.h (i386_optab): Add new insns.
765 2005-07-01 Nick Clifton <nickc@redhat.com>
767 * sparc.h: Add typedefs to structure declarations.
769 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
772 * i386.h (i386_optab): Update comments for 64bit addressing on
773 mov. Allow 64bit addressing for mov and movq.
775 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
777 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
778 respectively, in various floating-point load and store patterns.
780 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
782 * hppa.h (FLAG_STRICT): Correct comment.
783 (pa_opcodes): Update load and store entries to allow both PA 1.X and
784 PA 2.0 mneumonics when equivalent. Entries with cache control
785 completers now require PA 1.1. Adjust whitespace.
787 2005-05-19 Anton Blanchard <anton@samba.org>
789 * ppc.h (PPC_OPCODE_POWER5): Define.
791 2005-05-10 Nick Clifton <nickc@redhat.com>
793 * Update the address and phone number of the FSF organization in
794 the GPL notices in the following files:
795 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
796 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
797 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
798 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
799 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
800 tic54x.h, tic80.h, v850.h, vax.h
802 2005-05-09 Jan Beulich <jbeulich@novell.com>
804 * i386.h (i386_optab): Add ht and hnt.
806 2005-04-18 Mark Kettenis <kettenis@gnu.org>
808 * i386.h: Insert hyphens into selected VIA PadLock extensions.
809 Add xcrypt-ctr. Provide aliases without hyphens.
811 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
813 Moved from ../ChangeLog
815 2005-04-12 Paul Brook <paul@codesourcery.com>
816 * m88k.h: Rename psr macros to avoid conflicts.
818 2005-03-12 Zack Weinberg <zack@codesourcery.com>
819 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
820 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
823 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
824 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
825 Remove redundant instruction types.
826 (struct argument): X_op - new field.
827 (struct cst4_entry): Remove.
828 (no_op_insn): Declare.
830 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
831 * crx.h (enum argtype): Rename types, remove unused types.
833 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
834 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
835 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
836 (enum operand_type): Rearrange operands, edit comments.
837 replace us<N> with ui<N> for unsigned immediate.
838 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
839 displacements (respectively).
840 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
841 (instruction type): Add NO_TYPE_INS.
842 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
843 (operand_entry): New field - 'flags'.
844 (operand flags): New.
846 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
847 * crx.h (operand_type): Remove redundant types i3, i4,
849 Add new unsigned immediate types us3, us4, us5, us16.
851 2005-04-12 Mark Kettenis <kettenis@gnu.org>
853 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
854 adjust them accordingly.
856 2005-04-01 Jan Beulich <jbeulich@novell.com>
858 * i386.h (i386_optab): Add rdtscp.
860 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
862 * i386.h (i386_optab): Don't allow the `l' suffix for moving
863 between memory and segment register. Allow movq for moving between
864 general-purpose register and segment register.
866 2005-02-09 Jan Beulich <jbeulich@novell.com>
869 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
870 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
873 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
875 * m68k.h (m68008, m68ec030, m68882): Remove.
877 (cpu_m68k, cpu_cf): New.
878 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
879 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
881 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
883 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
884 * cgen.h (enum cgen_parse_operand_type): Add
885 CGEN_PARSE_OPERAND_SYMBOLIC.
887 2005-01-21 Fred Fish <fnf@specifixinc.com>
889 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
890 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
891 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
893 2005-01-19 Fred Fish <fnf@specifixinc.com>
895 * mips.h (struct mips_opcode): Add new pinfo2 member.
896 (INSN_ALIAS): New define for opcode table entries that are
897 specific instances of another entry, such as 'move' for an 'or'
899 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
900 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
902 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
904 * mips.h (CPU_RM9000): Define.
905 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
907 2004-11-25 Jan Beulich <jbeulich@novell.com>
909 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
910 to/from test registers are illegal in 64-bit mode. Add missing
911 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
912 (previously one had to explicitly encode a rex64 prefix). Re-enable
913 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
914 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
916 2004-11-23 Jan Beulich <jbeulich@novell.com>
918 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
919 available only with SSE2. Change the MMX additions introduced by SSE
920 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
921 instructions by their now designated identifier (since combining i686
922 and 3DNow! does not really imply 3DNow!A).
924 2004-11-19 Alan Modra <amodra@bigpond.net.au>
926 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
927 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
929 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
930 Vineet Sharma <vineets@noida.hcltech.com>
932 * maxq.h: New file: Disassembly information for the maxq port.
934 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
936 * i386.h (i386_optab): Put back "movzb".
938 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
940 * cris.h (enum cris_insn_version_usage): Tweak formatting and
941 comments. Remove member cris_ver_sim. Add members
942 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
943 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
944 (struct cris_support_reg, struct cris_cond15): New types.
945 (cris_conds15): Declare.
946 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
947 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
948 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
949 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
950 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
953 2004-11-04 Jan Beulich <jbeulich@novell.com>
955 * i386.h (sldx_Suf): Remove.
956 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
957 (q_FP): Define, implying no REX64.
958 (x_FP, sl_FP): Imply FloatMF.
959 (i386_optab): Split reg and mem forms of moving from segment registers
960 so that the memory forms can ignore the 16-/32-bit operand size
961 distinction. Adjust a few others for Intel mode. Remove *FP uses from
962 all non-floating-point instructions. Unite 32- and 64-bit forms of
963 movsx, movzx, and movd. Adjust floating point operations for the above
964 changes to the *FP macros. Add DefaultSize to floating point control
965 insns operating on larger memory ranges. Remove left over comments
966 hinting at certain insns being Intel-syntax ones where the ones
967 actually meant are already gone.
969 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
971 * crx.h: Add COPS_REG_INS - Coprocessor Special register
974 2004-09-30 Paul Brook <paul@codesourcery.com>
976 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
977 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
979 2004-09-11 Theodore A. Roth <troth@openavr.org>
981 * avr.h: Add support for
982 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
984 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
986 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
988 2004-08-24 Dmitry Diky <diwil@spec.ru>
990 * msp430.h (msp430_opc): Add new instructions.
991 (msp430_rcodes): Declare new instructions.
992 (msp430_hcodes): Likewise..
994 2004-08-13 Nick Clifton <nickc@redhat.com>
997 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1000 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1002 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1004 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1006 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1008 2004-07-21 Jan Beulich <jbeulich@novell.com>
1010 * i386.h: Adjust instruction descriptions to better match the
1013 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1015 * arm.h: Remove all old content. Replace with architecture defines
1016 from gas/config/tc-arm.c.
1018 2004-07-09 Andreas Schwab <schwab@suse.de>
1020 * m68k.h: Fix comment.
1022 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1026 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1028 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1030 2004-05-24 Peter Barada <peter@the-baradas.com>
1032 * m68k.h: Add 'size' to m68k_opcode.
1034 2004-05-05 Peter Barada <peter@the-baradas.com>
1036 * m68k.h: Switch from ColdFire chip name to core variant.
1038 2004-04-22 Peter Barada <peter@the-baradas.com>
1040 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1041 descriptions for new EMAC cases.
1042 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1043 handle Motorola MAC syntax.
1044 Allow disassembly of ColdFire V4e object files.
1046 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1048 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1050 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1052 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1054 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1056 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1058 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1060 * i386.h (i386_optab): Added xstore/xcrypt insns.
1062 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1064 * h8300.h (32bit ldc/stc): Add relaxing support.
1066 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1068 * h8300.h (BITOP): Pass MEMRELAX flag.
1070 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1072 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1075 For older changes see ChangeLog-9103
1081 version-control: never