1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright (c) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6 This file is part of GDB, GAS, and the GNU binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "opcode/mips.h"
27 /* FIXME: These are needed to figure out if the code is mips16 or
28 not. The low bit of the address is often a good indicator. No
29 symbol table is available when this code runs out in an embedded
30 system as when it is used for disassembler support in a monitor. */
32 #if !defined(EMBEDDED_ENV)
33 #define SYMTAB_AVAILABLE 1
38 static int print_insn_mips16
PARAMS ((bfd_vma
, struct disassemble_info
*));
39 static void print_mips16_insn_arg
40 PARAMS ((int, const struct mips_opcode
*, int, boolean
, int, bfd_vma
,
41 struct disassemble_info
*));
43 /* Mips instructions are never longer than this many bytes. */
46 static void print_insn_arg
PARAMS ((const char *, unsigned long, bfd_vma
,
47 struct disassemble_info
*));
48 static int _print_insn_mips
PARAMS ((bfd_vma
, unsigned long int,
49 struct disassemble_info
*));
52 /* FIXME: This should be shared with gdb somehow. */
53 #define STD_REGISTER_NAMES \
54 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
55 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
56 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
57 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
58 "sr", "lo", "hi", "bad", "cause","pc", \
59 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
60 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
61 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
62 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
63 "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
67 static CONST
char * CONST std_reg_names
[] = STD_REGISTER_NAMES
;
69 /* The mips16 register names. */
70 static const char * const mips16_reg_names
[] =
72 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
75 /* Scalar register names. set_mips_isa_type() decides which register name
77 static CONST
char * CONST
*reg_names
= NULL
;
81 print_insn_arg (d
, l
, pc
, info
)
83 register unsigned long int l
;
85 struct disassemble_info
*info
;
94 (*info
->fprintf_func
) (info
->stream
, "%c", *d
);
101 (*info
->fprintf_func
) (info
->stream
, "$%s",
102 reg_names
[(l
>> OP_SH_RS
) & OP_MASK_RS
]);
107 (*info
->fprintf_func
) (info
->stream
, "$%s",
108 reg_names
[(l
>> OP_SH_RT
) & OP_MASK_RT
]);
113 (*info
->fprintf_func
) (info
->stream
, "0x%x",
114 (l
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
);
117 case 'j': /* same as i, but sign-extended */
119 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
122 (*info
->fprintf_func
) (info
->stream
, "%d",
127 (*info
->fprintf_func
) (info
->stream
, "0x%x",
128 (unsigned int) ((l
>> OP_SH_PREFX
)
133 (*info
->fprintf_func
) (info
->stream
, "0x%x",
134 (unsigned int) ((l
>> OP_SH_CACHE
)
139 (*info
->print_address_func
)
140 (((pc
& ~ (bfd_vma
) 0x0fffffff)
141 | (((l
>> OP_SH_TARGET
) & OP_MASK_TARGET
) << 2)),
146 /* sign extend the displacement */
147 delta
= (l
>> OP_SH_DELTA
) & OP_MASK_DELTA
;
150 (*info
->print_address_func
)
151 ((delta
<< 2) + pc
+ 4,
156 (*info
->fprintf_func
) (info
->stream
, "$%s",
157 reg_names
[(l
>> OP_SH_RD
) & OP_MASK_RD
]);
161 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
165 (*info
->fprintf_func
) (info
->stream
, "0x%x",
166 (l
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
170 (*info
->fprintf_func
) (info
->stream
, "0x%x",
171 (l
>> OP_SH_CODE
) & OP_MASK_CODE
);
176 (*info
->fprintf_func
) (info
->stream
, "0x%x",
177 (l
>> OP_SH_CODE2
) & OP_MASK_CODE2
);
181 (*info
->fprintf_func
) (info
->stream
, "0x%x",
182 (l
>> OP_SH_COPZ
) & OP_MASK_COPZ
);
186 (*info
->fprintf_func
) (info
->stream
, "0x%x",
187 (l
>> OP_SH_SYSCALL
) & OP_MASK_SYSCALL
);
192 (*info
->fprintf_func
) (info
->stream
, "$f%d",
193 (l
>> OP_SH_FS
) & OP_MASK_FS
);
199 (*info
->fprintf_func
) (info
->stream
, "$f%d",
200 (l
>> OP_SH_FT
) & OP_MASK_FT
);
204 (*info
->fprintf_func
) (info
->stream
, "$f%d",
205 (l
>> OP_SH_FD
) & OP_MASK_FD
);
209 (*info
->fprintf_func
) (info
->stream
, "$f%d",
210 (l
>> OP_SH_FR
) & OP_MASK_FR
);
214 (*info
->fprintf_func
) (info
->stream
, "$%d",
215 (l
>> OP_SH_RT
) & OP_MASK_RT
);
219 (*info
->fprintf_func
) (info
->stream
, "$%d",
220 (l
>> OP_SH_RD
) & OP_MASK_RD
);
224 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
225 (l
>> OP_SH_BCC
) & OP_MASK_BCC
);
229 (*info
->fprintf_func
) (info
->stream
, "$fcc%d",
230 (l
>> OP_SH_CCC
) & OP_MASK_CCC
);
234 (*info
->fprintf_func
) (info
->stream
, "%d",
235 (l
>> OP_SH_PERFREG
) & OP_MASK_PERFREG
);
240 /* xgettext:c-format */
241 (*info
->fprintf_func
) (info
->stream
,
242 _("# internal error, undefined modifier(%c)"),
250 /* Figure out the MIPS ISA and CPU based on the machine number.
251 FIXME: What does this have to do with SYMTAB_AVAILABLE? */
254 set_mips_isa_type (mach
, isa
, cputype
)
259 int target_processor
= 0;
262 /* Use standard MIPS register names by default. */
263 reg_names
= std_reg_names
;
267 case bfd_mach_mips3000
:
268 target_processor
= 3000;
271 case bfd_mach_mips3900
:
272 target_processor
= 3900;
275 case bfd_mach_mips4000
:
276 target_processor
= 4000;
279 case bfd_mach_mips4010
:
280 target_processor
= 4010;
283 case bfd_mach_mips4100
:
284 target_processor
= 4100;
287 case bfd_mach_mips4111
:
288 target_processor
= 4100;
291 case bfd_mach_mips4300
:
292 target_processor
= 4300;
295 case bfd_mach_mips4400
:
296 target_processor
= 4400;
299 case bfd_mach_mips4600
:
300 target_processor
= 4600;
303 case bfd_mach_mips4650
:
304 target_processor
= 4650;
307 case bfd_mach_mips5000
:
308 target_processor
= 5000;
311 case bfd_mach_mips6000
:
312 target_processor
= 6000;
315 case bfd_mach_mips8000
:
316 target_processor
= 8000;
319 case bfd_mach_mips10000
:
320 target_processor
= 10000;
323 case bfd_mach_mips16
:
324 target_processor
= 16;
328 target_processor
= 3000;
335 *cputype
= target_processor
;
338 #endif /* SYMTAB_AVAILABLE */
340 /* Print the mips instruction at address MEMADDR in debugged memory,
341 on using INFO. Returns length of the instruction, in bytes, which is
342 always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if
343 this is little-endian code. */
346 _print_insn_mips (memaddr
, word
, info
)
348 unsigned long int word
;
349 struct disassemble_info
*info
;
351 register const struct mips_opcode
*op
;
352 int target_processor
, mips_isa
;
353 static boolean init
= 0;
354 static const struct mips_opcode
*mips_hash
[OP_MASK_OP
+ 1];
356 /* Build a hash table to shorten the search time. */
361 for (i
= 0; i
<= OP_MASK_OP
; i
++)
363 for (op
= mips_opcodes
; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
365 if (op
->pinfo
== INSN_MACRO
)
367 if (i
== ((op
->match
>> OP_SH_OP
) & OP_MASK_OP
))
378 #if ! SYMTAB_AVAILABLE
379 /* This is running out on a target machine, not in a host tool.
380 FIXME: Where does mips_target_info come from? */
381 target_processor
= mips_target_info
.processor
;
382 mips_isa
= mips_target_info
.isa
;
384 set_mips_isa_type (info
->mach
, &mips_isa
, &target_processor
);
387 info
->bytes_per_chunk
= 4;
388 info
->display_endian
= info
->endian
;
390 op
= mips_hash
[(word
>> OP_SH_OP
) & OP_MASK_OP
];
393 for (; op
< &mips_opcodes
[NUMOPCODES
]; op
++)
395 if (op
->pinfo
!= INSN_MACRO
&& (word
& op
->mask
) == op
->match
)
397 register const char *d
;
399 if (! OPCODE_IS_MEMBER (op
, mips_isa
, target_processor
, 0))
402 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
405 if (d
!= NULL
&& *d
!= '\0')
407 (*info
->fprintf_func
) (info
->stream
, "\t");
408 for (; *d
!= '\0'; d
++)
409 print_insn_arg (d
, word
, memaddr
, info
);
417 /* Handle undefined instructions. */
418 (*info
->fprintf_func
) (info
->stream
, "0x%x", word
);
423 /* In an environment where we do not know the symbol type of the
424 instruction we are forced to assume that the low order bit of the
425 instructions' address may mark it as a mips16 instruction. If we
426 are single stepping, or the pc is within the disassembled function,
427 this works. Otherwise, we need a clue. Sometimes. */
430 print_insn_big_mips (memaddr
, info
)
432 struct disassemble_info
*info
;
438 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
439 /* Only a few tools will work this way. */
441 return print_insn_mips16 (memaddr
, info
);
446 || (info
->flavour
== bfd_target_elf_flavour
447 && info
->symbols
!= NULL
448 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
450 return print_insn_mips16 (memaddr
, info
);
453 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
455 return _print_insn_mips (memaddr
, (unsigned long) bfd_getb32 (buffer
),
459 (*info
->memory_error_func
) (status
, memaddr
, info
);
465 print_insn_little_mips (memaddr
, info
)
467 struct disassemble_info
*info
;
475 return print_insn_mips16 (memaddr
, info
);
480 || (info
->flavour
== bfd_target_elf_flavour
481 && info
->symbols
!= NULL
482 && ((*(elf_symbol_type
**) info
->symbols
)->internal_elf_sym
.st_other
484 return print_insn_mips16 (memaddr
, info
);
487 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
489 return _print_insn_mips (memaddr
, (unsigned long) bfd_getl32 (buffer
),
493 (*info
->memory_error_func
) (status
, memaddr
, info
);
498 /* Disassemble mips16 instructions. */
501 print_insn_mips16 (memaddr
, info
)
503 struct disassemble_info
*info
;
511 const struct mips_opcode
*op
, *opend
;
513 info
->bytes_per_chunk
= 2;
514 info
->display_endian
= info
->endian
;
516 info
->insn_info_valid
= 1;
517 info
->branch_delay_insns
= 0;
519 info
->insn_type
= dis_nonbranch
;
523 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
526 (*info
->memory_error_func
) (status
, memaddr
, info
);
532 if (info
->endian
== BFD_ENDIAN_BIG
)
533 insn
= bfd_getb16 (buffer
);
535 insn
= bfd_getl16 (buffer
);
537 /* Handle the extend opcode specially. */
539 if ((insn
& 0xf800) == 0xf000)
542 extend
= insn
& 0x7ff;
546 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
549 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
550 (unsigned int) extend
);
551 (*info
->memory_error_func
) (status
, memaddr
, info
);
555 if (info
->endian
== BFD_ENDIAN_BIG
)
556 insn
= bfd_getb16 (buffer
);
558 insn
= bfd_getl16 (buffer
);
560 /* Check for an extend opcode followed by an extend opcode. */
561 if ((insn
& 0xf800) == 0xf000)
563 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
564 (unsigned int) extend
);
565 info
->insn_type
= dis_noninsn
;
572 /* FIXME: Should probably use a hash table on the major opcode here. */
574 opend
= mips16_opcodes
+ bfd_mips16_num_opcodes
;
575 for (op
= mips16_opcodes
; op
< opend
; op
++)
577 if (op
->pinfo
!= INSN_MACRO
&& (insn
& op
->mask
) == op
->match
)
581 if (strchr (op
->args
, 'a') != NULL
)
585 (*info
->fprintf_func
) (info
->stream
, "extend 0x%x",
586 (unsigned int) extend
);
587 info
->insn_type
= dis_noninsn
;
595 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2,
600 if (info
->endian
== BFD_ENDIAN_BIG
)
601 extend
= bfd_getb16 (buffer
);
603 extend
= bfd_getl16 (buffer
);
608 (*info
->fprintf_func
) (info
->stream
, "%s", op
->name
);
609 if (op
->args
[0] != '\0')
610 (*info
->fprintf_func
) (info
->stream
, "\t");
612 for (s
= op
->args
; *s
!= '\0'; s
++)
616 && (((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)
617 == ((insn
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
)))
619 /* Skip the register and the comma. */
625 && (((insn
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
)
626 == ((insn
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
)))
628 /* Skip the register and the comma. */
632 print_mips16_insn_arg (*s
, op
, insn
, use_extend
, extend
, memaddr
,
636 if ((op
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
638 info
->branch_delay_insns
= 1;
639 if (info
->insn_type
!= dis_jsr
)
640 info
->insn_type
= dis_branch
;
648 (*info
->fprintf_func
) (info
->stream
, "0x%x", extend
| 0xf000);
649 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn
);
650 info
->insn_type
= dis_noninsn
;
655 /* Disassemble an operand for a mips16 instruction. */
658 print_mips16_insn_arg (type
, op
, l
, use_extend
, extend
, memaddr
, info
)
660 const struct mips_opcode
*op
;
665 struct disassemble_info
*info
;
672 (*info
->fprintf_func
) (info
->stream
, "%c", type
);
677 (*info
->fprintf_func
) (info
->stream
, "$%s",
678 mips16_reg_names
[((l
>> MIPS16OP_SH_RY
)
679 & MIPS16OP_MASK_RY
)]);
684 (*info
->fprintf_func
) (info
->stream
, "$%s",
685 mips16_reg_names
[((l
>> MIPS16OP_SH_RX
)
686 & MIPS16OP_MASK_RX
)]);
690 (*info
->fprintf_func
) (info
->stream
, "$%s",
691 mips16_reg_names
[((l
>> MIPS16OP_SH_RZ
)
692 & MIPS16OP_MASK_RZ
)]);
696 (*info
->fprintf_func
) (info
->stream
, "$%s",
697 mips16_reg_names
[((l
>> MIPS16OP_SH_MOVE32Z
)
698 & MIPS16OP_MASK_MOVE32Z
)]);
702 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[0]);
706 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[29]);
710 (*info
->fprintf_func
) (info
->stream
, "$pc");
714 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[31]);
718 (*info
->fprintf_func
) (info
->stream
, "$%s",
719 reg_names
[((l
>> MIPS16OP_SH_REGR32
)
720 & MIPS16OP_MASK_REGR32
)]);
724 (*info
->fprintf_func
) (info
->stream
, "$%s",
725 reg_names
[MIPS16OP_EXTRACT_REG32R (l
)]);
751 int immed
, nbits
, shift
, signedp
, extbits
, pcrel
, extu
, branch
;
763 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
769 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
775 immed
= (l
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
781 immed
= (l
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
787 immed
= (l
>> MIPS16OP_SH_IMM4
) & MIPS16OP_MASK_IMM4
;
793 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
794 info
->insn_type
= dis_dref
;
800 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
801 info
->insn_type
= dis_dref
;
807 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
808 if ((op
->pinfo
& MIPS16_INSN_READ_PC
) == 0
809 && (op
->pinfo
& MIPS16_INSN_READ_SP
) == 0)
811 info
->insn_type
= dis_dref
;
818 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
819 info
->insn_type
= dis_dref
;
824 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
829 immed
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
833 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
838 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
839 /* FIXME: This might be lw, or it might be addiu to $sp or
840 $pc. We assume it's load. */
841 info
->insn_type
= dis_dref
;
847 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
848 info
->insn_type
= dis_dref
;
853 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
858 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
864 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
869 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
873 info
->insn_type
= dis_condbranch
;
877 immed
= (l
>> MIPS16OP_SH_IMM11
) & MIPS16OP_MASK_IMM11
;
881 info
->insn_type
= dis_branch
;
886 immed
= (l
>> MIPS16OP_SH_IMM8
) & MIPS16OP_MASK_IMM8
;
888 /* FIXME: This can be lw or la. We assume it is lw. */
889 info
->insn_type
= dis_dref
;
895 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
897 info
->insn_type
= dis_dref
;
903 immed
= (l
>> MIPS16OP_SH_IMM5
) & MIPS16OP_MASK_IMM5
;
912 if (signedp
&& immed
>= (1 << (nbits
- 1)))
915 if ((type
== '<' || type
== '>' || type
== '[' || type
== ']')
922 immed
|= ((extend
& 0x1f) << 11) | (extend
& 0x7e0);
923 else if (extbits
== 15)
924 immed
|= ((extend
& 0xf) << 11) | (extend
& 0x7f0);
926 immed
= ((extend
>> 6) & 0x1f) | (extend
& 0x20);
927 immed
&= (1 << extbits
) - 1;
928 if (! extu
&& immed
>= (1 << (extbits
- 1)))
929 immed
-= 1 << extbits
;
933 (*info
->fprintf_func
) (info
->stream
, "%d", immed
);
942 baseaddr
= memaddr
+ 2;
945 baseaddr
= memaddr
- 2;
953 /* If this instruction is in the delay slot of a jr
954 instruction, the base address is the address of the
955 jr instruction. If it is in the delay slot of jalr
956 instruction, the base address is the address of the
957 jalr instruction. This test is unreliable: we have
958 no way of knowing whether the previous word is
959 instruction or data. */
960 status
= (*info
->read_memory_func
) (memaddr
- 4, buffer
, 2,
963 && (((info
->endian
== BFD_ENDIAN_BIG
964 ? bfd_getb16 (buffer
)
965 : bfd_getl16 (buffer
))
966 & 0xf800) == 0x1800))
967 baseaddr
= memaddr
- 4;
970 status
= (*info
->read_memory_func
) (memaddr
- 2, buffer
,
973 && (((info
->endian
== BFD_ENDIAN_BIG
974 ? bfd_getb16 (buffer
)
975 : bfd_getl16 (buffer
))
976 & 0xf81f) == 0xe800))
977 baseaddr
= memaddr
- 2;
980 val
= (baseaddr
& ~ ((1 << shift
) - 1)) + immed
;
981 (*info
->print_address_func
) (val
, info
);
990 l
= ((l
& 0x1f) << 23) | ((l
& 0x3e0) << 13) | (extend
<< 2);
991 (*info
->print_address_func
) ((memaddr
& 0xf0000000) | l
, info
);
992 info
->insn_type
= dis_jsr
;
993 info
->target
= (memaddr
& 0xf0000000) | l
;
994 info
->branch_delay_insns
= 1;
1000 int need_comma
, amask
, smask
;
1004 l
= (l
>> MIPS16OP_SH_IMM6
) & MIPS16OP_MASK_IMM6
;
1006 amask
= (l
>> 3) & 7;
1008 if (amask
> 0 && amask
< 5)
1010 (*info
->fprintf_func
) (info
->stream
, "$%s", reg_names
[4]);
1012 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1013 reg_names
[amask
+ 3]);
1017 smask
= (l
>> 1) & 3;
1020 (*info
->fprintf_func
) (info
->stream
, "%s??",
1021 need_comma
? "," : "");
1026 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1027 need_comma
? "," : "",
1030 (*info
->fprintf_func
) (info
->stream
, "-$%s",
1031 reg_names
[smask
+ 15]);
1037 (*info
->fprintf_func
) (info
->stream
, "%s$%s",
1038 need_comma
? "," : "",
1043 if (amask
== 5 || amask
== 6)
1045 (*info
->fprintf_func
) (info
->stream
, "%s$f0",
1046 need_comma
? "," : "");
1048 (*info
->fprintf_func
) (info
->stream
, "-$f1");