1 /* Instruction printing code for the AMD 29000
2 Copyright (C) 1990, 93, 94, 95, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support. Written by Jim Kingdon.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 #include "opcode/a29k.h"
25 /* Print a symbolic representation of a general-purpose
26 register number NUM on STREAM.
27 NUM is a number as found in the instruction, not as found in
28 debugging symbols; it must be in the range 0-255. */
30 print_general (num
, info
)
32 struct disassemble_info
*info
;
35 (*info
->fprintf_func
) (info
->stream
, "gr%d", num
);
37 (*info
->fprintf_func
) (info
->stream
, "lr%d", num
- 128);
40 /* Like print_general but a special-purpose register.
42 The mnemonics used by the AMD assembler are not quite the same
43 as the ones in the User's Manual. We use the ones that the
46 print_special (num
, info
)
48 struct disassemble_info
*info
;
50 /* Register names of registers 0-SPEC0_NUM-1. */
51 static char *spec0_names
[] = {
52 "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
53 "pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1",
54 "spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc",
57 #define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0]))
59 /* Register names of registers 128-128+SPEC128_NUM-1. */
60 static char *spec128_names
[] = {
61 "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
63 #define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0]))
65 /* Register names of registers 160-160+SPEC160_NUM-1. */
66 static char *spec160_names
[] = {
67 "fpe", "inte", "fps", "sr163", "exop"
69 #define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0]))
72 (*info
->fprintf_func
) (info
->stream
, spec0_names
[num
]);
73 else if (num
>= 128 && num
< 128 + SPEC128_NUM
)
74 (*info
->fprintf_func
) (info
->stream
, spec128_names
[num
-128]);
75 else if (num
>= 160 && num
< 160 + SPEC160_NUM
)
76 (*info
->fprintf_func
) (info
->stream
, spec160_names
[num
-160]);
78 (*info
->fprintf_func
) (info
->stream
, "sr%d", num
);
81 /* Is an instruction with OPCODE a delayed branch? */
83 is_delayed_branch (opcode
)
86 return (opcode
== 0xa8 || opcode
== 0xa9 || opcode
== 0xa0 || opcode
== 0xa1
87 || opcode
== 0xa4 || opcode
== 0xa5
88 || opcode
== 0xb4 || opcode
== 0xb5
89 || opcode
== 0xc4 || opcode
== 0xc0
90 || opcode
== 0xac || opcode
== 0xad
94 /* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}. */
96 find_bytes_big (insn
, insn0
, insn8
, insn16
, insn24
)
100 unsigned char *insn16
;
101 unsigned char *insn24
;
110 find_bytes_little (insn
, insn0
, insn8
, insn16
, insn24
)
112 unsigned char *insn0
;
113 unsigned char *insn8
;
114 unsigned char *insn16
;
115 unsigned char *insn24
;
123 typedef void (*find_byte_func_type
)
124 PARAMS ((char *, unsigned char *, unsigned char *,
125 unsigned char *, unsigned char *));
127 /* Print one instruction from MEMADDR on INFO->STREAM.
128 Return the size of the instruction (always 4 on a29k). */
131 print_insn (memaddr
, info
)
133 struct disassemble_info
*info
;
135 /* The raw instruction. */
138 /* The four bytes of the instruction. */
139 unsigned char insn24
, insn16
, insn8
, insn0
;
141 find_byte_func_type find_byte_func
= (find_byte_func_type
)info
->private_data
;
143 struct a29k_opcode CONST
* opcode
;
147 (*info
->read_memory_func
) (memaddr
, (bfd_byte
*) &insn
[0], 4, info
);
150 (*info
->memory_error_func
) (status
, memaddr
, info
);
155 (*find_byte_func
) (insn
, &insn0
, &insn8
, &insn16
, &insn24
);
157 printf ("%02x%02x%02x%02x ", insn24
, insn16
, insn8
, insn0
);
159 /* Handle the nop (aseq 0x40,gr1,gr1) specially */
160 if ((insn24
==0x70) && (insn16
==0x40) && (insn8
==0x01) && (insn0
==0x01)) {
161 (*info
->fprintf_func
) (info
->stream
,"nop");
165 /* The opcode is always in insn24. */
166 for (opcode
= &a29k_opcodes
[0];
167 opcode
< &a29k_opcodes
[num_opcodes
];
170 if (((unsigned long) insn24
<< 24) == opcode
->opcode
)
174 (*info
->fprintf_func
) (info
->stream
, "%s ", opcode
->name
);
175 for (s
= opcode
->args
; *s
!= '\0'; ++s
)
180 print_general (insn8
, info
);
184 print_general (insn0
, info
);
188 print_general (insn16
, info
);
192 (*info
->fprintf_func
) (info
->stream
, "%d", insn0
);
196 (*info
->fprintf_func
) (info
->stream
, "0x%x", (insn16
<< 8) + insn0
);
200 /* This used to be %x for binutils. */
201 (*info
->fprintf_func
) (info
->stream
, "0x%x",
202 (insn16
<< 24) + (insn0
<< 16));
206 (*info
->fprintf_func
) (info
->stream
, "%d",
207 ((insn16
<< 8) + insn0
) | 0xffff0000);
211 /* This output looks just like absolute addressing, but
212 maybe that's OK (it's what the GDB m68k and EBMON
213 a29k disassemblers do). */
214 /* All the shifting is to sign-extend it. p*/
215 (*info
->print_address_func
)
217 (((int)((insn16
<< 10) + (insn0
<< 2)) << 14) >> 14),
222 (*info
->print_address_func
)
223 ((insn16
<< 10) + (insn0
<< 2), info
);
227 (*info
->fprintf_func
) (info
->stream
, "%d", insn16
>> 7);
231 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn16
& 0x7f);
235 (*info
->fprintf_func
) (info
->stream
, "0x%x", insn16
);
239 print_special (insn8
, info
);
243 (*info
->fprintf_func
) (info
->stream
, "%d", insn0
>> 7);
247 (*info
->fprintf_func
) (info
->stream
, "%d", (insn0
>> 4) & 7);
251 if ((insn16
& 3) != 0)
252 (*info
->fprintf_func
) (info
->stream
, "%d", insn16
& 3);
256 (*info
->fprintf_func
) (info
->stream
, "%d", (insn0
>> 2) & 3);
260 (*info
->fprintf_func
) (info
->stream
, "%d", insn0
& 3);
264 (*info
->fprintf_func
) (info
->stream
, "%d", (insn16
>> 2) & 15);
268 (*info
->fprintf_func
) (info
->stream
, "%d", insn16
& 3);
272 (*info
->fprintf_func
) (info
->stream
, "%c", *s
);
276 /* Now we look for a const,consth pair of instructions,
277 in which case we try to print the symbolic address. */
278 if (insn24
== 2) /* consth */
282 unsigned char prev_insn0
, prev_insn8
, prev_insn16
, prev_insn24
;
284 errcode
= (*info
->read_memory_func
) (memaddr
- 4,
285 (bfd_byte
*) &prev_insn
[0],
290 /* If it is a delayed branch, we need to look at the
291 instruction before the delayed brach to handle
298 (*find_byte_func
) (prev_insn
, &prev_insn0
, &prev_insn8
,
299 &prev_insn16
, &prev_insn24
);
300 if (is_delayed_branch (prev_insn24
))
302 errcode
= (*info
->read_memory_func
)
303 (memaddr
- 8, (bfd_byte
*) &prev_insn
[0], 4, info
);
304 (*find_byte_func
) (prev_insn
, &prev_insn0
, &prev_insn8
,
305 &prev_insn16
, &prev_insn24
);
309 /* If there was a problem reading memory, then assume
310 the previous instruction was not const. */
313 /* Is it const to the same register? */
315 && prev_insn8
== insn8
)
317 (*info
->fprintf_func
) (info
->stream
, "\t; ");
318 (*info
->print_address_func
)
319 (((insn16
<< 24) + (insn0
<< 16)
320 + (prev_insn16
<< 8) + (prev_insn0
)),
329 /* This used to be %8x for binutils. */
330 (*info
->fprintf_func
)
331 (info
->stream
, ".word 0x%08x",
332 (insn24
<< 24) + (insn16
<< 16) + (insn8
<< 8) + insn0
);
336 /* Disassemble an big-endian a29k instruction. */
338 print_insn_big_a29k (memaddr
, info
)
340 struct disassemble_info
*info
;
342 info
->private_data
= (PTR
) find_bytes_big
;
343 return print_insn (memaddr
, info
);
346 /* Disassemble a little-endian a29k instruction. */
348 print_insn_little_a29k (memaddr
, info
)
350 struct disassemble_info
*info
;
352 info
->private_data
= (PTR
) find_bytes_little
;
353 return print_insn (memaddr
, info
);