gas/config/m68k-parse.h

   1 /* m68k-parse.h -- header file for m68k assembler
   2    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
   3    2003, 2004, 2005 Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #ifndef M68K_PARSE_H
  23 #define M68K_PARSE_H
  24
  25 /* This header file defines things which are shared between the
  26    operand parser in m68k.y and the m68k assembler proper in
  27    tc-m68k.c.  */
  28
  29 /* The various m68k registers.  */
  30
  31 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
  32    0-7==data reg, 8-15==addr reg for operands that take both types.
  33
  34    We don't use forms like "ADDR0 = ADDR" here because this file is
  35    likely to be used on an Apollo, and the broken Apollo compiler
  36    gives an `undefined variable' error if we do that, according to
  37    troy@cbme.unsw.edu.au.  */
  38
  39 #define DATA DATA0
  40 #define ADDR ADDR0
  41 #define SP ADDR7
  42 #define BAD BAD0
  43 #define BAC BAC0
  44
  45 enum m68k_register
  46 {
  47   DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
  48   DATA1,
  49   DATA2,
  50   DATA3,
  51   DATA4,
  52   DATA5,
  53   DATA6,
  54   DATA7,
  55
  56   ADDR0,
  57   ADDR1,
  58   ADDR2,
  59   ADDR3,
  60   ADDR4,
  61   ADDR5,
  62   ADDR6,
  63   ADDR7,
  64
  65   FP0,                          /* Eight FP registers */
  66   FP1,
  67   FP2,
  68   FP3,
  69   FP4,
  70   FP5,
  71   FP6,
  72   FP7,
  73
  74   COP0,                         /* Co-processor #0-#7 */
  75   COP1,
  76   COP2,
  77   COP3,
  78   COP4,
  79   COP5,
  80   COP6,
  81   COP7,
  82
  83   PC,                           /* Program counter */
  84   ZPC,                          /* Hack for Program space, but 0 addressing */
  85   SR,                           /* Status Reg */
  86   CCR,                          /* Condition code Reg */
  87   ACC,                          /* Accumulator Reg0 (EMAC or ACC on MAC).  */
  88   ACC1,                         /* Accumulator Reg 1 (EMAC).  */
  89   ACC2,                         /* Accumulator Reg 2 (EMAC).  */
  90   ACC3,                         /* Accumulator Reg 3 (EMAC).  */
  91   ACCEXT01,                     /* Accumulator extension 0&1 (EMAC).  */
  92   ACCEXT23,                     /* Accumulator extension 2&3 (EMAC).  */
  93   MACSR,                        /* MAC Status Reg */
  94   MASK,                         /* Modulus Reg */
  95
  96   /* These have to be grouped together for the movec instruction to work.  */
  97   USP,                          /*  User Stack Pointer */
  98   ISP,                          /*  Interrupt stack pointer */
  99   SFC,
 100   DFC,
 101   CACR,
 102   VBR,
 103   CAAR,
 104   MSP,
 105   ITT0,
 106   ITT1,
 107   DTT0,
 108   DTT1,
 109   MMUSR,
 110   TC,
 111   SRP,
 112   URP,
 113   BUSCR,                        /* 68060 added these.  */
 114   PCR,
 115   ROMBAR,                       /* mcf5200 added these.  */
 116   RAMBAR0,
 117   RAMBAR1,
 118   MMUBAR,                       /* mcfv4e added these.  */
 119   ROMBAR1,                      /* mcfv4e added these.  */
 120   MPCR, EDRAMBAR, SECMBAR,      /* mcfv4e added these.  */
 121   PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
 122   PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
 123   PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
 124   MBAR0, MBAR1,                 /* mcfv4e added these.  */
 125   ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
 126   FLASHBAR, RAMBAR,             /* mcf528x added these.  */
 127   MBAR2,                        /* mcf5249 added this.  */
 128   MBAR,
 129   CAC,                          /* fido added this.  */
 130   MBB,
 131 #define last_movec_reg MBB
 132   /* End of movec ordering constraints.  */
 133
 134   FPI,
 135   FPS,
 136   FPC,
 137
 138   DRP,                          /* 68851 or 68030 MMU regs */
 139   CRP,
 140   CAL,
 141   VAL,
 142   SCC,
 143   AC,
 144   BAD0,
 145   BAD1,
 146   BAD2,
 147   BAD3,
 148   BAD4,
 149   BAD5,
 150   BAD6,
 151   BAD7,
 152   BAC0,
 153   BAC1,
 154   BAC2,
 155   BAC3,
 156   BAC4,
 157   BAC5,
 158   BAC6,
 159   BAC7,
 160   PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
 161                                    and ACUSR on 68ec030 */
 162   PCSR,
 163
 164   IC,                           /* instruction cache token */
 165   DC,                           /* data cache token */
 166   NC,                           /* no cache token */
 167   BC,                           /* both caches token */
 168
 169   TT0,                          /* 68030 access control unit regs */
 170   TT1,
 171
 172   ZDATA0,                       /* suppressed data registers.  */
 173   ZDATA1,
 174   ZDATA2,
 175   ZDATA3,
 176   ZDATA4,
 177   ZDATA5,
 178   ZDATA6,
 179   ZDATA7,
 180
 181   ZADDR0,                       /* suppressed address registers.  */
 182   ZADDR1,
 183   ZADDR2,
 184   ZADDR3,
 185   ZADDR4,
 186   ZADDR5,
 187   ZADDR6,
 188   ZADDR7,
 189
 190   /* Upper and lower half of data and address registers.  Order *must*
 191      be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
 192   DATA0L,                       /* lower half of data registers */
 193   DATA1L,
 194   DATA2L,
 195   DATA3L,
 196   DATA4L,
 197   DATA5L,
 198   DATA6L,
 199   DATA7L,
 200
 201   ADDR0L,                       /* lower half of address registers */
 202   ADDR1L,
 203   ADDR2L,
 204   ADDR3L,
 205   ADDR4L,
 206   ADDR5L,
 207   ADDR6L,
 208   ADDR7L,
 209
 210   DATA0U,                       /* upper half of data registers */
 211   DATA1U,
 212   DATA2U,
 213   DATA3U,
 214   DATA4U,
 215   DATA5U,
 216   DATA6U,
 217   DATA7U,
 218
 219   ADDR0U,                       /* upper half of address registers */
 220   ADDR1U,
 221   ADDR2U,
 222   ADDR3U,
 223   ADDR4U,
 224   ADDR5U,
 225   ADDR6U,
 226   ADDR7U,
 227 };
 228
 229 /* Size information.  */
 230
 231 enum m68k_size
 232 {
 233   /* Unspecified.  */
 234   SIZE_UNSPEC,
 235
 236   /* Byte.  */
 237   SIZE_BYTE,
 238
 239   /* Word (2 bytes).  */
 240   SIZE_WORD,
 241
 242   /* Longword (4 bytes).  */
 243   SIZE_LONG
 244 };
 245
 246 /* The structure used to hold information about an index register.  */
 247
 248 struct m68k_indexreg
 249 {
 250   /* The index register itself.  */
 251   enum m68k_register reg;
 252
 253   /* The size to use.  */
 254   enum m68k_size size;
 255
 256   /* The value to scale by.  */
 257   int scale;
 258 };
 259
 260 #ifdef OBJ_ELF
 261 /* The type of a PIC expression.  */
 262
 263 enum pic_relocation
 264 {
 265   pic_none,                     /* not pic */
 266   pic_plt_pcrel,                /* @PLTPC */
 267   pic_got_pcrel,                /* @GOTPC */
 268   pic_plt_off,                  /* @PLT */
 269   pic_got_off                   /* @GOT */
 270 };
 271 #endif
 272
 273 /* The structure used to hold information about an expression.  */
 274
 275 struct m68k_exp
 276 {
 277   /* The size to use.  */
 278   enum m68k_size size;
 279
 280 #ifdef OBJ_ELF
 281   /* The type of pic relocation if any.  */
 282   enum pic_relocation pic_reloc;
 283 #endif
 284
 285   /* The expression itself.  */
 286   expressionS exp;
 287 };
 288
 289 /* The operand modes.  */
 290
 291 enum m68k_operand_type
 292 {
 293   IMMED = 1,
 294   ABSL,
 295   DREG,
 296   AREG,
 297   FPREG,
 298   CONTROL,
 299   AINDR,
 300   AINC,
 301   ADEC,
 302   DISP,
 303   BASE,
 304   POST,
 305   PRE,
 306   LSH,  /* MAC/EMAC scalefactor '<<'.  */
 307   RSH,  /* MAC/EMAC scalefactor '>>'.  */
 308   REGLST
 309 };
 310
 311 /* The structure used to hold a parsed operand.  */
 312
 313 struct m68k_op
 314 {
 315   /* The type of operand.  */
 316   enum m68k_operand_type mode;
 317
 318   /* The main register.  */
 319   enum m68k_register reg;
 320
 321   /* The register mask for mode REGLST.  */
 322   unsigned long mask;
 323
 324   /* An error message.  */
 325   const char *error;
 326
 327   /* The index register.  */
 328   struct m68k_indexreg index;
 329
 330   /* The displacement.  */
 331   struct m68k_exp disp;
 332
 333   /* The outer displacement.  */
 334   struct m68k_exp odisp;
 335
 336   /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
 337   int trailing_ampersand;
 338 };
 339
 340 #endif /* ! defined (M68K_PARSE_H) */
 341
 342 /* The parsing function.  */
 343
 344 extern int m68k_ip_op (char *, struct m68k_op *);
 345
 346 /* Whether register prefixes are optional.  */
 347 extern int flag_reg_prefix_optional;