gas/config/m68k-parse.h

   1 /* m68k-parse.h -- header file for m68k assembler
   2    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
   3    2003, 2004, 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #ifndef M68K_PARSE_H
  23 #define M68K_PARSE_H
  24
  25 /* This header file defines things which are shared between the
  26    operand parser in m68k.y and the m68k assembler proper in
  27    tc-m68k.c.  */
  28
  29 /* The various m68k registers.  */
  30
  31 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
  32    0-7==data reg, 8-15==addr reg for operands that take both types.
  33
  34    We don't use forms like "ADDR0 = ADDR" here because this file is
  35    likely to be used on an Apollo, and the broken Apollo compiler
  36    gives an `undefined variable' error if we do that, according to
  37    troy@cbme.unsw.edu.au.  */
  38
  39 #define DATA DATA0
  40 #define ADDR ADDR0
  41 #define SP ADDR7
  42 #define BAD BAD0
  43 #define BAC BAC0
  44
  45 enum m68k_register
  46 {
  47   DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
  48   DATA1,
  49   DATA2,
  50   DATA3,
  51   DATA4,
  52   DATA5,
  53   DATA6,
  54   DATA7,
  55
  56   ADDR0,
  57   ADDR1,
  58   ADDR2,
  59   ADDR3,
  60   ADDR4,
  61   ADDR5,
  62   ADDR6,
  63   ADDR7,
  64
  65   FP0,                          /* Eight FP registers */
  66   FP1,
  67   FP2,
  68   FP3,
  69   FP4,
  70   FP5,
  71   FP6,
  72   FP7,
  73
  74   COP0,                         /* Co-processor #0-#7 */
  75   COP1,
  76   COP2,
  77   COP3,
  78   COP4,
  79   COP5,
  80   COP6,
  81   COP7,
  82
  83   PC,                           /* Program counter */
  84   ZPC,                          /* Hack for Program space, but 0 addressing */
  85   SR,                           /* Status Reg */
  86   CCR,                          /* Condition code Reg */
  87   ACC,                          /* Accumulator Reg0 (EMAC or ACC on MAC).  */
  88   ACC1,                         /* Accumulator Reg 1 (EMAC).  */
  89   ACC2,                         /* Accumulator Reg 2 (EMAC).  */
  90   ACC3,                         /* Accumulator Reg 3 (EMAC).  */
  91   ACCEXT01,                     /* Accumulator extension 0&1 (EMAC).  */
  92   ACCEXT23,                     /* Accumulator extension 2&3 (EMAC).  */
  93   MACSR,                        /* MAC Status Reg */
  94   MASK,                         /* Modulus Reg */
  95
  96   /* These have to be grouped together for the movec instruction to work.  */
  97   USP,                          /*  User Stack Pointer */
  98   ISP,                          /*  Interrupt stack pointer */
  99   SFC,
 100   DFC,
 101   CACR,
 102   VBR,
 103   CAAR,
 104   CPUCR,
 105   MSP,
 106   ITT0,
 107   ITT1,
 108   DTT0,
 109   DTT1,
 110   MMUSR,
 111   TC,
 112   SRP,
 113   URP,
 114   BUSCR,                        /* 68060 added these.  */
 115   PCR,
 116   ROMBAR,                       /* mcf5200 added these.  */
 117   RAMBAR_ALT,                   /* Some CF chips have RAMBAR using
 118                                    RAMBAR0's number */
 119   RAMBAR0,
 120   RAMBAR1,
 121   MMUBAR,                       /* mcfv4e added these.  */
 122   ROMBAR0,                      /* mcfv4e added these.  */
 123   ROMBAR1,                      /* mcfv4e added these.  */
 124   MPCR, EDRAMBAR, SECMBAR,      /* mcfv4e added these.  */
 125   PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
 126   PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
 127   PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
 128   MBAR0, MBAR1,                 /* mcfv4e added these.  */
 129   ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
 130   FLASHBAR, RAMBAR,             /* mcf528x added these.  */
 131   MBAR2,                        /* mcf5249 added this.  */
 132   MBAR,
 133   ASID,                         /* m5475.  */
 134   CAC,                          /* fido added this.  */
 135   MBO,
 136 #define last_movec_reg MBO
 137   /* End of movec ordering constraints.  */
 138
 139   FPI,
 140   FPS,
 141   FPC,
 142
 143   DRP,                          /* 68851 or 68030 MMU regs */
 144   CRP,
 145   CAL,
 146   VAL,
 147   SCC,
 148   AC,
 149   BAD0,
 150   BAD1,
 151   BAD2,
 152   BAD3,
 153   BAD4,
 154   BAD5,
 155   BAD6,
 156   BAD7,
 157   BAC0,
 158   BAC1,
 159   BAC2,
 160   BAC3,
 161   BAC4,
 162   BAC5,
 163   BAC6,
 164   BAC7,
 165   PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
 166                                    and ACUSR on 68ec030 */
 167   PCSR,
 168
 169   IC,                           /* instruction cache token */
 170   DC,                           /* data cache token */
 171   NC,                           /* no cache token */
 172   BC,                           /* both caches token */
 173
 174   TT0,                          /* 68030 access control unit regs */
 175   TT1,
 176
 177   ZDATA0,                       /* suppressed data registers.  */
 178   ZDATA1,
 179   ZDATA2,
 180   ZDATA3,
 181   ZDATA4,
 182   ZDATA5,
 183   ZDATA6,
 184   ZDATA7,
 185
 186   ZADDR0,                       /* suppressed address registers.  */
 187   ZADDR1,
 188   ZADDR2,
 189   ZADDR3,
 190   ZADDR4,
 191   ZADDR5,
 192   ZADDR6,
 193   ZADDR7,
 194
 195   /* Upper and lower half of data and address registers.  Order *must*
 196      be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
 197   DATA0L,                       /* lower half of data registers */
 198   DATA1L,
 199   DATA2L,
 200   DATA3L,
 201   DATA4L,
 202   DATA5L,
 203   DATA6L,
 204   DATA7L,
 205
 206   ADDR0L,                       /* lower half of address registers */
 207   ADDR1L,
 208   ADDR2L,
 209   ADDR3L,
 210   ADDR4L,
 211   ADDR5L,
 212   ADDR6L,
 213   ADDR7L,
 214
 215   DATA0U,                       /* upper half of data registers */
 216   DATA1U,
 217   DATA2U,
 218   DATA3U,
 219   DATA4U,
 220   DATA5U,
 221   DATA6U,
 222   DATA7U,
 223
 224   ADDR0U,                       /* upper half of address registers */
 225   ADDR1U,
 226   ADDR2U,
 227   ADDR3U,
 228   ADDR4U,
 229   ADDR5U,
 230   ADDR6U,
 231   ADDR7U,
 232 };
 233
 234 /* Size information.  */
 235
 236 enum m68k_size
 237 {
 238   /* Unspecified.  */
 239   SIZE_UNSPEC,
 240
 241   /* Byte.  */
 242   SIZE_BYTE,
 243
 244   /* Word (2 bytes).  */
 245   SIZE_WORD,
 246
 247   /* Longword (4 bytes).  */
 248   SIZE_LONG
 249 };
 250
 251 /* The structure used to hold information about an index register.  */
 252
 253 struct m68k_indexreg
 254 {
 255   /* The index register itself.  */
 256   enum m68k_register reg;
 257
 258   /* The size to use.  */
 259   enum m68k_size size;
 260
 261   /* The value to scale by.  */
 262   int scale;
 263 };
 264
 265 #ifdef OBJ_ELF
 266 /* The type of a PIC expression.  */
 267
 268 enum pic_relocation
 269 {
 270   pic_none,                     /* not pic */
 271   pic_plt_pcrel,                /* @PLTPC */
 272   pic_got_pcrel,                /* @GOTPC */
 273   pic_plt_off,                  /* @PLT */
 274   pic_got_off,                  /* @GOT */
 275   pic_tls_gd,                   /* @TLSGD */
 276   pic_tls_ldm,                  /* @TLSLDM */
 277   pic_tls_ldo,                  /* @TLSLDO */
 278   pic_tls_ie,                   /* @TLSIE */
 279   pic_tls_le                    /* @TLSLE */
 280 };
 281 #endif
 282
 283 /* The structure used to hold information about an expression.  */
 284
 285 struct m68k_exp
 286 {
 287   /* The size to use.  */
 288   enum m68k_size size;
 289
 290 #ifdef OBJ_ELF
 291   /* The type of pic relocation if any.  */
 292   enum pic_relocation pic_reloc;
 293 #endif
 294
 295   /* The expression itself.  */
 296   expressionS exp;
 297 };
 298
 299 /* The operand modes.  */
 300
 301 enum m68k_operand_type
 302 {
 303   IMMED = 1,
 304   ABSL,
 305   DREG,
 306   AREG,
 307   FPREG,
 308   CONTROL,
 309   AINDR,
 310   AINC,
 311   ADEC,
 312   DISP,
 313   BASE,
 314   POST,
 315   PRE,
 316   LSH,  /* MAC/EMAC scalefactor '<<'.  */
 317   RSH,  /* MAC/EMAC scalefactor '>>'.  */
 318   REGLST
 319 };
 320
 321 /* The structure used to hold a parsed operand.  */
 322
 323 struct m68k_op
 324 {
 325   /* The type of operand.  */
 326   enum m68k_operand_type mode;
 327
 328   /* The main register.  */
 329   enum m68k_register reg;
 330
 331   /* The register mask for mode REGLST.  */
 332   unsigned long mask;
 333
 334   /* An error message.  */
 335   const char *error;
 336
 337   /* The index register.  */
 338   struct m68k_indexreg index;
 339
 340   /* The displacement.  */
 341   struct m68k_exp disp;
 342
 343   /* The outer displacement.  */
 344   struct m68k_exp odisp;
 345
 346   /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
 347   int trailing_ampersand;
 348 };
 349
 350 #endif /* ! defined (M68K_PARSE_H) */
 351
 352 /* The parsing function.  */
 353
 354 extern int m68k_ip_op (char *, struct m68k_op *);
 355
 356 /* Whether register prefixes are optional.  */
 357 extern int flag_reg_prefix_optional;