1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
439 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
440 static void xtensa_mark_literal_pool_location (void);
441 static addressT
get_expanded_loop_offset (xtensa_opcode
);
442 static fragS
*get_literal_pool_location (segT
);
443 static void set_literal_pool_location (segT
, fragS
*);
444 static void xtensa_set_frag_assembly_state (fragS
*);
445 static void finish_vinsn (vliw_insn
*);
446 static bfd_boolean
emit_single_op (TInsn
*);
447 static int total_frag_text_expansion (fragS
*);
449 /* Alignment Functions. */
451 static int get_text_align_power (unsigned);
452 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
453 static int branch_align_power (segT
);
455 /* Helpers for xtensa_relax_frag(). */
457 static long relax_frag_add_nop (fragS
*);
459 /* Accessors for additional per-subsegment information. */
461 static unsigned get_last_insn_flags (segT
, subsegT
);
462 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
463 static float get_subseg_total_freq (segT
, subsegT
);
464 static float get_subseg_target_freq (segT
, subsegT
);
465 static void set_subseg_freq (segT
, subsegT
, float, float);
467 /* Segment list functions. */
469 static void xtensa_move_literals (void);
470 static void xtensa_reorder_segments (void);
471 static void xtensa_switch_to_literal_fragment (emit_state
*);
472 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
473 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
474 static void xtensa_restore_emit_state (emit_state
*);
475 static void cache_literal_section
476 (seg_list
*, const char *, segT
*, bfd_boolean
);
478 /* Import from elf32-xtensa.c in BFD library. */
480 extern char *xtensa_get_property_section_name (asection
*, const char *);
482 /* op_placement_info functions. */
484 static void init_op_placement_info_table (void);
485 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
486 static int xg_get_single_size (xtensa_opcode
);
487 static xtensa_format
xg_get_single_format (xtensa_opcode
);
489 /* TInsn and IStack functions. */
491 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
492 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
493 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
494 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
495 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
496 static void tinsn_from_chars (TInsn
*, char *, int);
497 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
498 static int get_num_stack_text_bytes (IStack
*);
499 static int get_num_stack_literal_bytes (IStack
*);
501 /* vliw_insn functions. */
503 static void xg_init_vinsn (vliw_insn
*);
504 static void xg_clear_vinsn (vliw_insn
*);
505 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
506 static void xg_free_vinsn (vliw_insn
*);
507 static bfd_boolean vinsn_to_insnbuf
508 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
509 static void vinsn_from_chars (vliw_insn
*, char *);
511 /* Expression Utilities. */
513 bfd_boolean
expr_is_const (const expressionS
*);
514 offsetT
get_expr_const (const expressionS
*);
515 void set_expr_const (expressionS
*, offsetT
);
516 bfd_boolean
expr_is_register (const expressionS
*);
517 offsetT
get_expr_register (const expressionS
*);
518 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
519 static void set_expr_symbol_offset_diff
520 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
521 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
522 static void copy_expr (expressionS
*, const expressionS
*);
524 /* Section renaming. */
526 static void build_section_rename (const char *);
529 /* ISA imported from bfd. */
530 extern xtensa_isa xtensa_default_isa
;
532 extern int target_big_endian
;
534 static xtensa_opcode xtensa_addi_opcode
;
535 static xtensa_opcode xtensa_addmi_opcode
;
536 static xtensa_opcode xtensa_call0_opcode
;
537 static xtensa_opcode xtensa_call4_opcode
;
538 static xtensa_opcode xtensa_call8_opcode
;
539 static xtensa_opcode xtensa_call12_opcode
;
540 static xtensa_opcode xtensa_callx0_opcode
;
541 static xtensa_opcode xtensa_callx4_opcode
;
542 static xtensa_opcode xtensa_callx8_opcode
;
543 static xtensa_opcode xtensa_callx12_opcode
;
544 static xtensa_opcode xtensa_const16_opcode
;
545 static xtensa_opcode xtensa_entry_opcode
;
546 static xtensa_opcode xtensa_movi_opcode
;
547 static xtensa_opcode xtensa_movi_n_opcode
;
548 static xtensa_opcode xtensa_isync_opcode
;
549 static xtensa_opcode xtensa_jx_opcode
;
550 static xtensa_opcode xtensa_l32r_opcode
;
551 static xtensa_opcode xtensa_loop_opcode
;
552 static xtensa_opcode xtensa_loopnez_opcode
;
553 static xtensa_opcode xtensa_loopgtz_opcode
;
554 static xtensa_opcode xtensa_nop_opcode
;
555 static xtensa_opcode xtensa_nop_n_opcode
;
556 static xtensa_opcode xtensa_or_opcode
;
557 static xtensa_opcode xtensa_ret_opcode
;
558 static xtensa_opcode xtensa_ret_n_opcode
;
559 static xtensa_opcode xtensa_retw_opcode
;
560 static xtensa_opcode xtensa_retw_n_opcode
;
561 static xtensa_opcode xtensa_rsr_lcount_opcode
;
562 static xtensa_opcode xtensa_waiti_opcode
;
565 /* Command-line Options. */
567 bfd_boolean use_literal_section
= TRUE
;
568 static bfd_boolean align_targets
= TRUE
;
569 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
570 static bfd_boolean has_a0_b_retw
= FALSE
;
571 static bfd_boolean workaround_a0_b_retw
= FALSE
;
572 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
573 static bfd_boolean workaround_short_loop
= FALSE
;
574 static bfd_boolean maybe_has_short_loop
= FALSE
;
575 static bfd_boolean workaround_close_loop_end
= FALSE
;
576 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
578 /* When workaround_short_loops is TRUE, all loops with early exits must
579 have at least 3 instructions. workaround_all_short_loops is a modifier
580 to the workaround_short_loop flag. In addition to the
581 workaround_short_loop actions, all straightline loopgtz and loopnez
582 must have at least 3 instructions. */
584 static bfd_boolean workaround_all_short_loops
= FALSE
;
588 xtensa_setup_hw_workarounds (int earliest
, int latest
)
590 if (earliest
> latest
)
591 as_fatal (_("illegal range of target hardware versions"));
593 /* Enable all workarounds for pre-T1050.0 hardware. */
594 if (earliest
< 105000 || latest
< 105000)
596 workaround_a0_b_retw
|= TRUE
;
597 workaround_b_j_loop_end
|= TRUE
;
598 workaround_short_loop
|= TRUE
;
599 workaround_close_loop_end
|= TRUE
;
600 workaround_all_short_loops
|= TRUE
;
607 option_density
= OPTION_MD_BASE
,
614 option_no_link_relax
,
622 option_text_section_literals
,
623 option_no_text_section_literals
,
625 option_absolute_literals
,
626 option_no_absolute_literals
,
628 option_align_targets
,
629 option_no_align_targets
,
631 option_warn_unaligned_targets
,
636 option_workaround_a0_b_retw
,
637 option_no_workaround_a0_b_retw
,
639 option_workaround_b_j_loop_end
,
640 option_no_workaround_b_j_loop_end
,
642 option_workaround_short_loop
,
643 option_no_workaround_short_loop
,
645 option_workaround_all_short_loops
,
646 option_no_workaround_all_short_loops
,
648 option_workaround_close_loop_end
,
649 option_no_workaround_close_loop_end
,
651 option_no_workarounds
,
653 option_rename_section_name
,
656 option_prefer_const16
,
658 option_target_hardware
661 const char *md_shortopts
= "";
663 struct option md_longopts
[] =
665 { "density", no_argument
, NULL
, option_density
},
666 { "no-density", no_argument
, NULL
, option_no_density
},
668 /* Both "relax" and "generics" are deprecated and treated as equivalent
669 to the "transform" option. */
670 { "relax", no_argument
, NULL
, option_relax
},
671 { "no-relax", no_argument
, NULL
, option_no_relax
},
672 { "generics", no_argument
, NULL
, option_generics
},
673 { "no-generics", no_argument
, NULL
, option_no_generics
},
675 { "transform", no_argument
, NULL
, option_transform
},
676 { "no-transform", no_argument
, NULL
, option_no_transform
},
677 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
678 { "no-text-section-literals", no_argument
, NULL
,
679 option_no_text_section_literals
},
680 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
681 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
682 /* This option was changed from -align-target to -target-align
683 because it conflicted with the "-al" option. */
684 { "target-align", no_argument
, NULL
, option_align_targets
},
685 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
686 { "warn-unaligned-targets", no_argument
, NULL
,
687 option_warn_unaligned_targets
},
688 { "longcalls", no_argument
, NULL
, option_longcalls
},
689 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
691 { "no-workaround-a0-b-retw", no_argument
, NULL
,
692 option_no_workaround_a0_b_retw
},
693 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
695 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
696 option_no_workaround_b_j_loop_end
},
697 { "workaround-b-j-loop-end", no_argument
, NULL
,
698 option_workaround_b_j_loop_end
},
700 { "no-workaround-short-loops", no_argument
, NULL
,
701 option_no_workaround_short_loop
},
702 { "workaround-short-loops", no_argument
, NULL
,
703 option_workaround_short_loop
},
705 { "no-workaround-all-short-loops", no_argument
, NULL
,
706 option_no_workaround_all_short_loops
},
707 { "workaround-all-short-loop", no_argument
, NULL
,
708 option_workaround_all_short_loops
},
710 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
711 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
713 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
715 { "no-workaround-close-loop-end", no_argument
, NULL
,
716 option_no_workaround_close_loop_end
},
717 { "workaround-close-loop-end", no_argument
, NULL
,
718 option_workaround_close_loop_end
},
720 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
722 { "link-relax", no_argument
, NULL
, option_link_relax
},
723 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
725 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
727 { NULL
, no_argument
, NULL
, 0 }
730 size_t md_longopts_size
= sizeof md_longopts
;
734 md_parse_option (int c
, char *arg
)
739 as_warn (_("--density option is ignored"));
741 case option_no_density
:
742 as_warn (_("--no-density option is ignored"));
744 case option_link_relax
:
747 case option_no_link_relax
:
750 case option_generics
:
751 as_warn (_("--generics is deprecated; use --transform instead"));
752 return md_parse_option (option_transform
, arg
);
753 case option_no_generics
:
754 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
755 return md_parse_option (option_no_transform
, arg
);
757 as_warn (_("--relax is deprecated; use --transform instead"));
758 return md_parse_option (option_transform
, arg
);
759 case option_no_relax
:
760 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
761 return md_parse_option (option_no_transform
, arg
);
762 case option_longcalls
:
763 directive_state
[directive_longcalls
] = TRUE
;
765 case option_no_longcalls
:
766 directive_state
[directive_longcalls
] = FALSE
;
768 case option_text_section_literals
:
769 use_literal_section
= FALSE
;
771 case option_no_text_section_literals
:
772 use_literal_section
= TRUE
;
774 case option_absolute_literals
:
775 if (!absolute_literals_supported
)
777 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
780 directive_state
[directive_absolute_literals
] = TRUE
;
782 case option_no_absolute_literals
:
783 directive_state
[directive_absolute_literals
] = FALSE
;
786 case option_workaround_a0_b_retw
:
787 workaround_a0_b_retw
= TRUE
;
789 case option_no_workaround_a0_b_retw
:
790 workaround_a0_b_retw
= FALSE
;
792 case option_workaround_b_j_loop_end
:
793 workaround_b_j_loop_end
= TRUE
;
795 case option_no_workaround_b_j_loop_end
:
796 workaround_b_j_loop_end
= FALSE
;
799 case option_workaround_short_loop
:
800 workaround_short_loop
= TRUE
;
802 case option_no_workaround_short_loop
:
803 workaround_short_loop
= FALSE
;
806 case option_workaround_all_short_loops
:
807 workaround_all_short_loops
= TRUE
;
809 case option_no_workaround_all_short_loops
:
810 workaround_all_short_loops
= FALSE
;
813 case option_workaround_close_loop_end
:
814 workaround_close_loop_end
= TRUE
;
816 case option_no_workaround_close_loop_end
:
817 workaround_close_loop_end
= FALSE
;
820 case option_no_workarounds
:
821 workaround_a0_b_retw
= FALSE
;
822 workaround_b_j_loop_end
= FALSE
;
823 workaround_short_loop
= FALSE
;
824 workaround_all_short_loops
= FALSE
;
825 workaround_close_loop_end
= FALSE
;
828 case option_align_targets
:
829 align_targets
= TRUE
;
831 case option_no_align_targets
:
832 align_targets
= FALSE
;
835 case option_warn_unaligned_targets
:
836 warn_unaligned_branch_targets
= TRUE
;
839 case option_rename_section_name
:
840 build_section_rename (arg
);
844 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
845 should be emitted or not. FIXME: Not implemented. */
848 case option_prefer_l32r
:
850 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
854 case option_prefer_const16
:
856 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
860 case option_target_hardware
:
862 int earliest
, latest
= 0;
863 if (*arg
== 0 || *arg
== '-')
864 as_fatal (_("invalid target hardware version"));
866 earliest
= strtol (arg
, &arg
, 0);
870 else if (*arg
== '-')
873 as_fatal (_("invalid target hardware version"));
874 latest
= strtol (arg
, &arg
, 0);
877 as_fatal (_("invalid target hardware version"));
879 xtensa_setup_hw_workarounds (earliest
, latest
);
883 case option_transform
:
884 /* This option has no affect other than to use the defaults,
885 which are already set. */
888 case option_no_transform
:
889 /* This option turns off all transformations of any kind.
890 However, because we want to preserve the state of other
891 directives, we only change its own field. Thus, before
892 you perform any transformation, always check if transform
893 is available. If you use the functions we provide for this
894 purpose, you will be ok. */
895 directive_state
[directive_transform
] = FALSE
;
905 md_show_usage (FILE *stream
)
909 --[no-]text-section-literals\n\
910 [Do not] put literals in the text section\n\
911 --[no-]absolute-literals\n\
912 [Do not] default to use non-PC-relative literals\n\
913 --[no-]target-align [Do not] try to align branch targets\n\
914 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
915 --[no-]transform [Do not] transform instructions\n\
916 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
920 /* Functions related to the list of current label symbols. */
923 xtensa_add_insn_label (symbolS
*sym
)
927 if (!free_insn_labels
)
928 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
931 l
= free_insn_labels
;
932 free_insn_labels
= l
->next
;
936 l
->next
= insn_labels
;
942 xtensa_clear_insn_labels (void)
946 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
953 /* The "loops_ok" argument is provided to allow ignoring labels that
954 define loop ends. This fixes a bug where the NOPs to align a
955 loop opcode were included in a previous zero-cost loop:
974 This argument is used to prevent moving the NOP to before the
975 loop-end label, which is what you want in this special case. */
978 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
982 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
984 symbolS
*lit_sym
= lit
->sym
;
985 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
987 S_SET_VALUE (lit_sym
, new_offset
);
988 symbol_set_frag (lit_sym
, new_frag
);
994 /* Directive data and functions. */
996 typedef struct state_stackS_struct
998 directiveE directive
;
1000 bfd_boolean old_state
;
1004 struct state_stackS_struct
*prev
;
1007 state_stackS
*directive_state_stack
;
1009 const pseudo_typeS md_pseudo_table
[] =
1011 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1012 { "literal_position", xtensa_literal_position
, 0 },
1013 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1014 { "long", xtensa_elf_cons
, 4 },
1015 { "word", xtensa_elf_cons
, 4 },
1016 { "short", xtensa_elf_cons
, 2 },
1017 { "begin", xtensa_begin_directive
, 0 },
1018 { "end", xtensa_end_directive
, 0 },
1019 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1020 { "literal", xtensa_literal_pseudo
, 0 },
1021 { "frequency", xtensa_frequency_pseudo
, 0 },
1027 use_transform (void)
1029 /* After md_end, you should be checking frag by frag, rather
1030 than state directives. */
1031 assert (!past_xtensa_end
);
1032 return directive_state
[directive_transform
];
1037 do_align_targets (void)
1039 /* Do not use this function after md_end; just look at align_targets
1040 instead. There is no target-align directive, so alignment is either
1041 enabled for all frags or not done at all. */
1042 assert (!past_xtensa_end
);
1043 return align_targets
&& use_transform ();
1048 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1052 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1054 as_where (&file
, &line
);
1056 stack
->directive
= directive
;
1057 stack
->negated
= negated
;
1058 stack
->old_state
= directive_state
[directive
];
1061 stack
->datum
= datum
;
1062 stack
->prev
= directive_state_stack
;
1063 directive_state_stack
= stack
;
1065 directive_state
[directive
] = !negated
;
1070 directive_pop (directiveE
*directive
,
1071 bfd_boolean
*negated
,
1076 state_stackS
*top
= directive_state_stack
;
1078 if (!directive_state_stack
)
1080 as_bad (_("unmatched end directive"));
1081 *directive
= directive_none
;
1085 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1086 *directive
= top
->directive
;
1087 *negated
= top
->negated
;
1090 *datum
= top
->datum
;
1091 directive_state_stack
= top
->prev
;
1097 directive_balance (void)
1099 while (directive_state_stack
)
1101 directiveE directive
;
1102 bfd_boolean negated
;
1107 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1108 as_warn_where ((char *) file
, line
,
1109 _(".begin directive with no matching .end directive"));
1115 inside_directive (directiveE dir
)
1117 state_stackS
*top
= directive_state_stack
;
1119 while (top
&& top
->directive
!= dir
)
1122 return (top
!= NULL
);
1127 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1131 char *directive_string
;
1133 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1138 input_line_pointer
+= 3;
1141 len
= strspn (input_line_pointer
,
1142 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1144 /* This code is a hack to make .begin [no-][generics|relax] exactly
1145 equivalent to .begin [no-]transform. We should remove it when
1146 we stop accepting those options. */
1148 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1150 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1151 directive_string
= "transform";
1153 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1155 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1156 directive_string
= "transform";
1159 directive_string
= input_line_pointer
;
1161 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1163 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1165 input_line_pointer
+= len
;
1166 *directive
= (directiveE
) i
;
1167 if (*negated
&& !directive_info
[i
].can_be_negated
)
1168 as_bad (_("directive %s cannot be negated"),
1169 directive_info
[i
].name
);
1174 as_bad (_("unknown directive"));
1175 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1180 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1182 directiveE directive
;
1183 bfd_boolean negated
;
1188 get_directive (&directive
, &negated
);
1189 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1191 discard_rest_of_line ();
1195 if (cur_vinsn
.inside_bundle
)
1196 as_bad (_("directives are not valid inside bundles"));
1200 case directive_literal
:
1201 if (!inside_directive (directive_literal
))
1203 /* Previous labels go with whatever follows this directive, not with
1204 the literal, so save them now. */
1205 saved_insn_labels
= insn_labels
;
1208 as_warn (_(".begin literal is deprecated; use .literal instead"));
1209 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1210 xtensa_switch_to_literal_fragment (state
);
1211 directive_push (directive_literal
, negated
, state
);
1214 case directive_literal_prefix
:
1215 /* Have to flush pending output because a movi relaxed to an l32r
1216 might produce a literal. */
1217 md_flush_pending_output ();
1218 /* Check to see if the current fragment is a literal
1219 fragment. If it is, then this operation is not allowed. */
1220 if (generating_literals
)
1222 as_bad (_("cannot set literal_prefix inside literal fragment"));
1226 /* Allocate the literal state for this section and push
1227 onto the directive stack. */
1228 ls
= xmalloc (sizeof (lit_state
));
1231 *ls
= default_lit_sections
;
1233 directive_push (directive_literal_prefix
, negated
, ls
);
1235 /* Parse the new prefix from the input_line_pointer. */
1237 len
= strspn (input_line_pointer
,
1238 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1239 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1241 /* Process the new prefix. */
1242 xtensa_literal_prefix (input_line_pointer
, len
);
1244 /* Skip the name in the input line. */
1245 input_line_pointer
+= len
;
1248 case directive_freeregs
:
1249 /* This information is currently unused, but we'll accept the statement
1250 and just discard the rest of the line. This won't check the syntax,
1251 but it will accept every correct freeregs directive. */
1252 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1253 directive_push (directive_freeregs
, negated
, 0);
1256 case directive_schedule
:
1257 md_flush_pending_output ();
1258 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1259 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1260 directive_push (directive_schedule
, negated
, 0);
1261 xtensa_set_frag_assembly_state (frag_now
);
1264 case directive_density
:
1265 as_warn (_(".begin [no-]density is ignored"));
1268 case directive_absolute_literals
:
1269 md_flush_pending_output ();
1270 if (!absolute_literals_supported
&& !negated
)
1272 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1275 xtensa_set_frag_assembly_state (frag_now
);
1276 directive_push (directive
, negated
, 0);
1280 md_flush_pending_output ();
1281 xtensa_set_frag_assembly_state (frag_now
);
1282 directive_push (directive
, negated
, 0);
1286 demand_empty_rest_of_line ();
1291 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1293 directiveE begin_directive
, end_directive
;
1294 bfd_boolean begin_negated
, end_negated
;
1298 emit_state
**state_ptr
;
1301 if (cur_vinsn
.inside_bundle
)
1302 as_bad (_("directives are not valid inside bundles"));
1304 get_directive (&end_directive
, &end_negated
);
1306 md_flush_pending_output ();
1308 switch (end_directive
)
1310 case (directiveE
) XTENSA_UNDEFINED
:
1311 discard_rest_of_line ();
1314 case directive_density
:
1315 as_warn (_(".end [no-]density is ignored"));
1316 demand_empty_rest_of_line ();
1319 case directive_absolute_literals
:
1320 if (!absolute_literals_supported
&& !end_negated
)
1322 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1323 demand_empty_rest_of_line ();
1332 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1333 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1334 (const void **) state_ptr
);
1336 if (begin_directive
!= directive_none
)
1338 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1340 as_bad (_("does not match begin %s%s at %s:%d"),
1341 begin_negated
? "no-" : "",
1342 directive_info
[begin_directive
].name
, file
, line
);
1346 switch (end_directive
)
1348 case directive_literal
:
1349 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1350 xtensa_restore_emit_state (state
);
1351 xtensa_set_frag_assembly_state (frag_now
);
1353 if (!inside_directive (directive_literal
))
1355 /* Restore the list of current labels. */
1356 xtensa_clear_insn_labels ();
1357 insn_labels
= saved_insn_labels
;
1361 case directive_literal_prefix
:
1362 /* Restore the default collection sections from saved state. */
1363 s
= (lit_state
*) state
;
1366 if (use_literal_section
)
1367 default_lit_sections
= *s
;
1369 /* free the state storage */
1373 case directive_schedule
:
1374 case directive_freeregs
:
1378 xtensa_set_frag_assembly_state (frag_now
);
1384 demand_empty_rest_of_line ();
1388 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1390 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1393 xtensa_dwarf2_directive_loc (int x
)
1395 xtensa_loc_directive_seen
= TRUE
;
1396 dwarf2_directive_loc (x
);
1401 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1403 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1405 xtensa_loc_directive_seen
= FALSE
;
1406 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1410 /* Place an aligned literal fragment at the current location. */
1413 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1415 md_flush_pending_output ();
1417 if (inside_directive (directive_literal
))
1418 as_warn (_(".literal_position inside literal directive; ignoring"));
1419 xtensa_mark_literal_pool_location ();
1421 demand_empty_rest_of_line ();
1422 xtensa_clear_insn_labels ();
1426 /* Support .literal label, expr, ... */
1429 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1432 char *p
, *base_name
;
1436 if (inside_directive (directive_literal
))
1438 as_bad (_(".literal not allowed inside .begin literal region"));
1439 ignore_rest_of_line ();
1443 md_flush_pending_output ();
1445 /* Previous labels go with whatever follows this directive, not with
1446 the literal, so save them now. */
1447 saved_insn_labels
= insn_labels
;
1450 /* If we are using text-section literals, then this is the right value... */
1453 base_name
= input_line_pointer
;
1455 xtensa_switch_to_literal_fragment (&state
);
1457 /* ...but if we aren't using text-section-literals, then we
1458 need to put them in the section we just switched to. */
1459 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1462 /* All literals are aligned to four-byte boundaries. */
1463 frag_align (2, 0, 0);
1464 record_alignment (now_seg
, 2);
1466 c
= get_symbol_end ();
1467 /* Just after name is now '\0'. */
1468 p
= input_line_pointer
;
1472 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1474 as_bad (_("expected comma or colon after symbol name; "
1475 "rest of line ignored"));
1476 ignore_rest_of_line ();
1477 xtensa_restore_emit_state (&state
);
1485 input_line_pointer
++; /* skip ',' or ':' */
1487 xtensa_elf_cons (4);
1489 xtensa_restore_emit_state (&state
);
1491 /* Restore the list of current labels. */
1492 xtensa_clear_insn_labels ();
1493 insn_labels
= saved_insn_labels
;
1498 xtensa_literal_prefix (char const *start
, int len
)
1500 char *name
, *linkonce_suffix
;
1501 char *newname
, *newname4
;
1502 size_t linkonce_len
;
1504 /* Get a null-terminated copy of the name. */
1505 name
= xmalloc (len
+ 1);
1508 strncpy (name
, start
, len
);
1511 /* Allocate the sections (interesting note: the memory pointing to
1512 the name is actually used for the name by the new section). */
1514 newname
= xmalloc (len
+ strlen (".literal") + 1);
1515 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1517 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1518 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1519 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1521 strcpy (newname
, ".gnu.linkonce.literal");
1522 strcpy (newname4
, ".gnu.linkonce.lit4");
1524 strcat (newname
, linkonce_suffix
);
1525 strcat (newname4
, linkonce_suffix
);
1529 int suffix_pos
= len
;
1531 /* If the section name ends with ".text", then replace that suffix
1532 instead of appending an additional suffix. */
1533 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1536 strcpy (newname
, name
);
1537 strcpy (newname4
, name
);
1539 strcpy (newname
+ suffix_pos
, ".literal");
1540 strcpy (newname4
+ suffix_pos
, ".lit4");
1543 /* Note that cache_literal_section does not create a segment if
1544 it already exists. */
1545 default_lit_sections
.lit_seg
= NULL
;
1546 default_lit_sections
.lit4_seg
= NULL
;
1548 /* Canonicalizing section names allows renaming literal
1549 sections to occur correctly. */
1550 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1551 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1557 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1560 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1562 float fall_through_f
, target_f
;
1564 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1565 if (fall_through_f
< 0)
1567 as_bad (_("fall through frequency must be greater than 0"));
1568 ignore_rest_of_line ();
1572 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1575 as_bad (_("branch target frequency must be greater than 0"));
1576 ignore_rest_of_line ();
1580 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1582 demand_empty_rest_of_line ();
1586 /* Like normal .long/.short/.word, except support @plt, etc.
1587 Clobbers input_line_pointer, checks end-of-line. */
1590 xtensa_elf_cons (int nbytes
)
1593 bfd_reloc_code_real_type reloc
;
1595 md_flush_pending_output ();
1597 if (cur_vinsn
.inside_bundle
)
1598 as_bad (_("directives are not valid inside bundles"));
1600 if (is_it_end_of_statement ())
1602 demand_empty_rest_of_line ();
1609 if (exp
.X_op
== O_symbol
1610 && *input_line_pointer
== '@'
1611 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1614 reloc_howto_type
*reloc_howto
=
1615 bfd_reloc_type_lookup (stdoutput
, reloc
);
1617 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1618 as_bad (_("unsupported relocation"));
1619 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1620 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1621 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1622 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1623 as_bad (_("opcode-specific %s relocation used outside "
1624 "an instruction"), reloc_howto
->name
);
1625 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1626 as_bad (_("%s relocations do not fit in %d bytes"),
1627 reloc_howto
->name
, nbytes
);
1630 char *p
= frag_more ((int) nbytes
);
1631 xtensa_set_frag_assembly_state (frag_now
);
1632 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1633 nbytes
, &exp
, 0, reloc
);
1637 emit_expr (&exp
, (unsigned int) nbytes
);
1639 while (*input_line_pointer
++ == ',');
1641 input_line_pointer
--; /* Put terminator back into stream. */
1642 demand_empty_rest_of_line ();
1646 /* Parsing and Idiom Translation. */
1648 /* Parse @plt, etc. and return the desired relocation. */
1649 static bfd_reloc_code_real_type
1650 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1656 bfd_reloc_code_real_type reloc
;
1664 struct map_bfd
*ptr
;
1666 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1668 static struct map_bfd mapping
[] =
1670 MAP ("l", BFD_RELOC_LO16
),
1671 MAP ("h", BFD_RELOC_HI16
),
1672 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1673 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1677 return BFD_RELOC_NONE
;
1679 for (ch
= *str
, str2
= ident
;
1680 (str2
< ident
+ sizeof (ident
) - 1
1681 && (ISALNUM (ch
) || ch
== '@'));
1684 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1691 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1692 if (ch
== ptr
->string
[0]
1693 && len
== ptr
->length
1694 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1696 /* Now check for "identifier@suffix+constant". */
1697 if (*str
== '-' || *str
== '+')
1699 char *orig_line
= input_line_pointer
;
1700 expressionS new_exp
;
1702 input_line_pointer
= str
;
1703 expression (&new_exp
);
1704 if (new_exp
.X_op
== O_constant
)
1706 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1707 str
= input_line_pointer
;
1710 if (&input_line_pointer
!= str_p
)
1711 input_line_pointer
= orig_line
;
1718 return BFD_RELOC_UNUSED
;
1723 expression_end (const char *name
)
1746 #define ERROR_REG_NUM ((unsigned) -1)
1749 tc_get_register (const char *prefix
)
1752 const char *next_expr
;
1753 const char *old_line_pointer
;
1756 old_line_pointer
= input_line_pointer
;
1758 if (*input_line_pointer
== '$')
1759 ++input_line_pointer
;
1761 /* Accept "sp" as a synonym for "a1". */
1762 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1763 && expression_end (input_line_pointer
+ 2))
1765 input_line_pointer
+= 2;
1766 return 1; /* AR[1] */
1769 while (*input_line_pointer
++ == *prefix
++)
1771 --input_line_pointer
;
1776 as_bad (_("bad register name: %s"), old_line_pointer
);
1777 return ERROR_REG_NUM
;
1780 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1782 as_bad (_("bad register number: %s"), input_line_pointer
);
1783 return ERROR_REG_NUM
;
1788 while (ISDIGIT ((int) *input_line_pointer
))
1789 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1791 if (!(next_expr
= expression_end (input_line_pointer
)))
1793 as_bad (_("bad register name: %s"), old_line_pointer
);
1794 return ERROR_REG_NUM
;
1797 input_line_pointer
= (char *) next_expr
;
1804 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1806 xtensa_isa isa
= xtensa_default_isa
;
1808 /* Check if this is an immediate operand. */
1809 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1811 bfd_reloc_code_real_type reloc
;
1812 segT t
= expression (tok
);
1813 if (t
== absolute_section
1814 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1816 assert (tok
->X_op
== O_constant
);
1817 tok
->X_op
= O_symbol
;
1818 tok
->X_add_symbol
= &abs_symbol
;
1821 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1822 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1823 && (reloc
!= BFD_RELOC_NONE
))
1828 case BFD_RELOC_UNUSED
:
1829 as_bad (_("unsupported relocation"));
1832 case BFD_RELOC_XTENSA_PLT
:
1833 tok
->X_op
= O_pltrel
;
1836 case BFD_RELOC_LO16
:
1837 if (tok
->X_op
== O_constant
)
1838 tok
->X_add_number
&= 0xffff;
1843 case BFD_RELOC_HI16
:
1844 if (tok
->X_op
== O_constant
)
1845 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1854 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1855 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1857 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1860 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1861 as_bad (_("register number out of range"));
1864 tok
->X_op
= O_register
;
1865 tok
->X_add_symbol
= 0;
1866 tok
->X_add_number
= reg
;
1871 /* Split up the arguments for an opcode or pseudo-op. */
1874 tokenize_arguments (char **args
, char *str
)
1876 char *old_input_line_pointer
;
1877 bfd_boolean saw_comma
= FALSE
;
1878 bfd_boolean saw_arg
= FALSE
;
1879 bfd_boolean saw_colon
= FALSE
;
1881 char *arg_end
, *arg
;
1884 /* Save and restore input_line_pointer around this function. */
1885 old_input_line_pointer
= input_line_pointer
;
1886 input_line_pointer
= str
;
1888 while (*input_line_pointer
)
1891 switch (*input_line_pointer
)
1898 input_line_pointer
++;
1899 if (saw_comma
|| saw_colon
|| !saw_arg
)
1905 input_line_pointer
++;
1906 if (saw_comma
|| saw_colon
|| !saw_arg
)
1912 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1915 arg_end
= input_line_pointer
+ 1;
1916 while (!expression_end (arg_end
))
1919 arg_len
= arg_end
- input_line_pointer
;
1920 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1921 args
[num_args
] = arg
;
1925 strncpy (arg
, input_line_pointer
, arg_len
);
1926 arg
[arg_len
] = '\0';
1928 input_line_pointer
= arg_end
;
1938 if (saw_comma
|| saw_colon
)
1940 input_line_pointer
= old_input_line_pointer
;
1945 as_bad (_("extra comma"));
1947 as_bad (_("extra colon"));
1949 as_bad (_("missing argument"));
1951 as_bad (_("missing comma or colon"));
1952 input_line_pointer
= old_input_line_pointer
;
1957 /* Parse the arguments to an opcode. Return TRUE on error. */
1960 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1962 expressionS
*tok
, *last_tok
;
1963 xtensa_opcode opcode
= insn
->opcode
;
1964 bfd_boolean had_error
= TRUE
;
1965 xtensa_isa isa
= xtensa_default_isa
;
1966 int n
, num_regs
= 0;
1967 int opcode_operand_count
;
1968 int opnd_cnt
, last_opnd_cnt
;
1969 unsigned int next_reg
= 0;
1970 char *old_input_line_pointer
;
1972 if (insn
->insn_type
== ITYPE_LITERAL
)
1973 opcode_operand_count
= 1;
1975 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1978 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1980 /* Save and restore input_line_pointer around this function. */
1981 old_input_line_pointer
= input_line_pointer
;
1987 /* Skip invisible operands. */
1988 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1994 for (n
= 0; n
< num_args
; n
++)
1996 input_line_pointer
= arg_strings
[n
];
1997 if (*input_line_pointer
== ':')
1999 xtensa_regfile opnd_rf
;
2000 input_line_pointer
++;
2003 assert (opnd_cnt
> 0);
2005 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2007 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2008 as_warn (_("incorrect register number, ignoring"));
2013 if (opnd_cnt
>= opcode_operand_count
)
2015 as_warn (_("too many arguments"));
2018 assert (opnd_cnt
< MAX_INSN_ARGS
);
2020 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2021 next_reg
= tok
->X_add_number
+ 1;
2023 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2025 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2027 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2028 /* minus 1 because we are seeing one right now */
2034 last_opnd_cnt
= opnd_cnt
;
2041 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2045 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2048 insn
->ntok
= tok
- insn
->tok
;
2052 input_line_pointer
= old_input_line_pointer
;
2058 get_invisible_operands (TInsn
*insn
)
2060 xtensa_isa isa
= xtensa_default_isa
;
2061 static xtensa_insnbuf slotbuf
= NULL
;
2063 xtensa_opcode opc
= insn
->opcode
;
2064 int slot
, opnd
, fmt_found
;
2068 slotbuf
= xtensa_insnbuf_alloc (isa
);
2070 /* Find format/slot where this can be encoded. */
2073 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2075 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2077 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2083 if (fmt_found
) break;
2088 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2092 /* First encode all the visible operands
2093 (to deal with shared field operands). */
2094 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2096 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2097 && (insn
->tok
[opnd
].X_op
== O_register
2098 || insn
->tok
[opnd
].X_op
== O_constant
))
2100 val
= insn
->tok
[opnd
].X_add_number
;
2101 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2102 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2106 /* Then pull out the values for the invisible ones. */
2107 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2109 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2111 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2112 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2113 insn
->tok
[opnd
].X_add_number
= val
;
2114 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2115 insn
->tok
[opnd
].X_op
= O_register
;
2117 insn
->tok
[opnd
].X_op
= O_constant
;
2126 xg_reverse_shift_count (char **cnt_argp
)
2128 char *cnt_arg
, *new_arg
;
2129 cnt_arg
= *cnt_argp
;
2131 /* replace the argument with "31-(argument)" */
2132 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2133 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2136 *cnt_argp
= new_arg
;
2140 /* If "arg" is a constant expression, return non-zero with the value
2144 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2147 char *save_ptr
= input_line_pointer
;
2149 input_line_pointer
= arg
;
2151 input_line_pointer
= save_ptr
;
2153 if (exp
.X_op
== O_constant
)
2155 *valp
= exp
.X_add_number
;
2164 xg_replace_opname (char **popname
, char *newop
)
2167 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2168 strcpy (*popname
, newop
);
2173 xg_check_num_args (int *pnum_args
,
2178 int num_args
= *pnum_args
;
2180 if (num_args
< expected_num
)
2182 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2183 num_args
, opname
, expected_num
);
2187 if (num_args
> expected_num
)
2189 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2190 num_args
, opname
, expected_num
);
2191 while (num_args
-- > expected_num
)
2193 free (arg_strings
[num_args
]);
2194 arg_strings
[num_args
] = 0;
2196 *pnum_args
= expected_num
;
2204 /* If the register is not specified as part of the opcode,
2205 then get it from the operand and move it to the opcode. */
2208 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2210 xtensa_isa isa
= xtensa_default_isa
;
2212 char *opname
, *new_opname
;
2213 const char *sr_name
;
2214 int is_user
, is_write
;
2215 bfd_boolean has_underbar
= FALSE
;
2220 has_underbar
= TRUE
;
2223 is_user
= (opname
[1] == 'u');
2224 is_write
= (opname
[0] == 'w');
2226 /* Opname == [rw]ur or [rwx]sr... */
2228 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2231 /* Check if the argument is a symbolic register name. */
2232 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2233 /* Handle WSR to "INTSET" as a special case. */
2234 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2235 && !strcasecmp (arg_strings
[1], "intset"))
2236 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2237 if (sr
== XTENSA_UNDEFINED
2238 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2240 /* Maybe it's a register number.... */
2242 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2244 as_bad (_("invalid register '%s' for '%s' instruction"),
2245 arg_strings
[1], opname
);
2248 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2249 if (sr
== XTENSA_UNDEFINED
)
2251 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2252 (long) val
, opname
);
2257 /* Remove the last argument, which is now part of the opcode. */
2258 free (arg_strings
[1]);
2262 /* Translate the opcode. */
2263 sr_name
= xtensa_sysreg_name (isa
, sr
);
2264 /* Another special case for "WSR.INTSET".... */
2265 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2267 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2268 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2271 *popname
= new_opname
;
2278 xtensa_translate_old_userreg_ops (char **popname
)
2280 xtensa_isa isa
= xtensa_default_isa
;
2282 char *opname
, *new_opname
;
2283 const char *sr_name
;
2284 bfd_boolean has_underbar
= FALSE
;
2287 if (opname
[0] == '_')
2289 has_underbar
= TRUE
;
2293 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2294 if (sr
!= XTENSA_UNDEFINED
)
2296 /* The new default name ("nnn") is different from the old default
2297 name ("URnnn"). The old default is handled below, and we don't
2298 want to recognize [RW]nnn, so do nothing if the name is the (new)
2300 static char namebuf
[10];
2301 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2302 if (strcmp (namebuf
, opname
+ 1) == 0)
2310 /* Only continue if the reg name is "URnnn". */
2311 if (opname
[1] != 'u' || opname
[2] != 'r')
2313 val
= strtoul (opname
+ 3, &end
, 10);
2317 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2318 if (sr
== XTENSA_UNDEFINED
)
2320 as_bad (_("invalid register number (%ld) for '%s'"),
2321 (long) val
, opname
);
2326 /* Translate the opcode. */
2327 sr_name
= xtensa_sysreg_name (isa
, sr
);
2328 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2329 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2330 opname
[0], sr_name
);
2332 *popname
= new_opname
;
2339 xtensa_translate_zero_immed (char *old_op
,
2349 assert (opname
[0] != '_');
2351 if (strcmp (opname
, old_op
) != 0)
2354 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2356 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2358 xg_replace_opname (popname
, new_op
);
2359 free (arg_strings
[1]);
2360 arg_strings
[1] = arg_strings
[2];
2369 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2370 Returns non-zero if an error was found. */
2373 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2375 char *opname
= *popname
;
2376 bfd_boolean has_underbar
= FALSE
;
2378 if (cur_vinsn
.inside_bundle
)
2383 has_underbar
= TRUE
;
2387 if (strcmp (opname
, "mov") == 0)
2389 if (use_transform () && !has_underbar
&& density_supported
)
2390 xg_replace_opname (popname
, "mov.n");
2393 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2395 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2396 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2397 strcpy (arg_strings
[2], arg_strings
[1]);
2403 if (strcmp (opname
, "bbsi.l") == 0)
2405 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2407 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2408 if (target_big_endian
)
2409 xg_reverse_shift_count (&arg_strings
[1]);
2413 if (strcmp (opname
, "bbci.l") == 0)
2415 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2417 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2418 if (target_big_endian
)
2419 xg_reverse_shift_count (&arg_strings
[1]);
2423 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2424 && strcmp (opname
, "nop") == 0)
2426 if (use_transform () && !has_underbar
&& density_supported
)
2427 xg_replace_opname (popname
, "nop.n");
2430 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2432 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2433 arg_strings
[0] = (char *) xmalloc (3);
2434 arg_strings
[1] = (char *) xmalloc (3);
2435 arg_strings
[2] = (char *) xmalloc (3);
2436 strcpy (arg_strings
[0], "a1");
2437 strcpy (arg_strings
[1], "a1");
2438 strcpy (arg_strings
[2], "a1");
2444 /* Recognize [RW]UR and [RWX]SR. */
2445 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2446 && (opname
[1] == 'u' || opname
[1] == 's'))
2447 || (opname
[0] == 'x' && opname
[1] == 's'))
2449 && opname
[3] == '\0')
2450 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2452 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2453 [RW]<name> if <name> is the non-default name of a user register. */
2454 if ((opname
[0] == 'r' || opname
[0] == 'w')
2455 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2456 return xtensa_translate_old_userreg_ops (popname
);
2458 /* Relax branches that don't allow comparisons against an immediate value
2459 of zero to the corresponding branches with implicit zero immediates. */
2460 if (!has_underbar
&& use_transform ())
2462 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2463 pnum_args
, arg_strings
))
2466 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2467 pnum_args
, arg_strings
))
2470 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2471 pnum_args
, arg_strings
))
2474 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2475 pnum_args
, arg_strings
))
2483 /* Functions for dealing with the Xtensa ISA. */
2485 /* Currently the assembler only allows us to use a single target per
2486 fragment. Because of this, only one operand for a given
2487 instruction may be symbolic. If there is a PC-relative operand,
2488 the last one is chosen. Otherwise, the result is the number of the
2489 last immediate operand, and if there are none of those, we fail and
2493 get_relaxable_immed (xtensa_opcode opcode
)
2495 int last_immed
= -1;
2498 if (opcode
== XTENSA_UNDEFINED
)
2501 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2502 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2504 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2506 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2508 if (last_immed
== -1
2509 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2516 static xtensa_opcode
2517 get_opcode_from_buf (const char *buf
, int slot
)
2519 static xtensa_insnbuf insnbuf
= NULL
;
2520 static xtensa_insnbuf slotbuf
= NULL
;
2521 xtensa_isa isa
= xtensa_default_isa
;
2526 insnbuf
= xtensa_insnbuf_alloc (isa
);
2527 slotbuf
= xtensa_insnbuf_alloc (isa
);
2530 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2531 fmt
= xtensa_format_decode (isa
, insnbuf
);
2532 if (fmt
== XTENSA_UNDEFINED
)
2533 return XTENSA_UNDEFINED
;
2535 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2536 return XTENSA_UNDEFINED
;
2538 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2539 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2543 #ifdef TENSILICA_DEBUG
2545 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2548 xtensa_print_insn_table (void)
2550 int num_opcodes
, num_operands
;
2551 xtensa_opcode opcode
;
2552 xtensa_isa isa
= xtensa_default_isa
;
2554 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2555 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2558 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2559 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2560 for (opn
= 0; opn
< num_operands
; opn
++)
2562 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2564 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2566 xtensa_regfile opnd_rf
=
2567 xtensa_operand_regfile (isa
, opcode
, opn
);
2568 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2570 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2571 fputs ("[lLr] ", stderr
);
2573 fputs ("i ", stderr
);
2575 fprintf (stderr
, "\n");
2581 print_vliw_insn (xtensa_insnbuf vbuf
)
2583 xtensa_isa isa
= xtensa_default_isa
;
2584 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2585 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2588 fprintf (stderr
, "format = %d\n", f
);
2590 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2592 xtensa_opcode opcode
;
2596 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2597 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2598 opname
= xtensa_opcode_name (isa
, opcode
);
2600 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2601 fprintf (stderr
, " operands = ");
2603 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2607 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2609 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2610 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2611 fprintf (stderr
, "%d ", val
);
2613 fprintf (stderr
, "\n");
2615 xtensa_insnbuf_free (isa
, sbuf
);
2618 #endif /* TENSILICA_DEBUG */
2622 is_direct_call_opcode (xtensa_opcode opcode
)
2624 xtensa_isa isa
= xtensa_default_isa
;
2625 int n
, num_operands
;
2627 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2630 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2631 for (n
= 0; n
< num_operands
; n
++)
2633 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2634 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2641 /* Convert from BFD relocation type code to slot and operand number.
2642 Returns non-zero on failure. */
2645 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2647 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2648 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2650 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2653 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2654 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2656 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2666 /* Convert from slot number to BFD relocation type code for the
2667 standard PC-relative relocations. Return BFD_RELOC_NONE on
2670 static bfd_reloc_code_real_type
2671 encode_reloc (int slot
)
2673 if (slot
< 0 || slot
> 14)
2674 return BFD_RELOC_NONE
;
2676 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2680 /* Convert from slot numbers to BFD relocation type code for the
2681 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2683 static bfd_reloc_code_real_type
2684 encode_alt_reloc (int slot
)
2686 if (slot
< 0 || slot
> 14)
2687 return BFD_RELOC_NONE
;
2689 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2694 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2697 xtensa_opcode opcode
,
2703 uint32 valbuf
= value
;
2705 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2707 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2709 as_bad_where ((char *) file
, line
,
2710 _("operand %d of '%s' has out of range value '%u'"),
2712 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2715 as_bad_where ((char *) file
, line
,
2716 _("operand %d of '%s' has invalid value '%u'"),
2718 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2723 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2729 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2732 xtensa_opcode opcode
,
2736 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2737 fmt
, slot
, slotbuf
, &val
);
2738 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2743 /* Checks for rules from xtensa-relax tables. */
2745 /* The routine xg_instruction_matches_option_term must return TRUE
2746 when a given option term is true. The meaning of all of the option
2747 terms is given interpretation by this function. This is needed when
2748 an option depends on the state of a directive, but there are no such
2749 options in use right now. */
2752 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2753 const ReqOrOption
*option
)
2755 if (strcmp (option
->option_name
, "realnop") == 0
2756 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2758 /* These conditions were evaluated statically when building the
2759 relaxation table. There's no need to reevaluate them now. */
2764 as_fatal (_("internal error: unknown option name '%s'"),
2765 option
->option_name
);
2771 xg_instruction_matches_or_options (TInsn
*insn
,
2772 const ReqOrOptionList
*or_option
)
2774 const ReqOrOption
*option
;
2775 /* Must match each of the AND terms. */
2776 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2778 if (xg_instruction_matches_option_term (insn
, option
))
2786 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2788 const ReqOption
*req_options
;
2789 /* Must match each of the AND terms. */
2790 for (req_options
= options
;
2791 req_options
!= NULL
;
2792 req_options
= req_options
->next
)
2794 /* Must match one of the OR clauses. */
2795 if (!xg_instruction_matches_or_options (insn
,
2796 req_options
->or_option_terms
))
2803 /* Return the transition rule that matches or NULL if none matches. */
2806 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2808 PreconditionList
*condition_l
;
2810 if (rule
->opcode
!= insn
->opcode
)
2813 for (condition_l
= rule
->conditions
;
2814 condition_l
!= NULL
;
2815 condition_l
= condition_l
->next
)
2819 Precondition
*cond
= condition_l
->precond
;
2824 /* The expression must be the constant. */
2825 assert (cond
->op_num
< insn
->ntok
);
2826 exp1
= &insn
->tok
[cond
->op_num
];
2827 if (expr_is_const (exp1
))
2832 if (get_expr_const (exp1
) != cond
->op_data
)
2836 if (get_expr_const (exp1
) == cond
->op_data
)
2843 else if (expr_is_register (exp1
))
2848 if (get_expr_register (exp1
) != cond
->op_data
)
2852 if (get_expr_register (exp1
) == cond
->op_data
)
2864 assert (cond
->op_num
< insn
->ntok
);
2865 assert (cond
->op_data
< insn
->ntok
);
2866 exp1
= &insn
->tok
[cond
->op_num
];
2867 exp2
= &insn
->tok
[cond
->op_data
];
2872 if (!expr_is_equal (exp1
, exp2
))
2876 if (expr_is_equal (exp1
, exp2
))
2888 if (!xg_instruction_matches_options (insn
, rule
->options
))
2896 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2898 bfd_boolean a_greater
= FALSE
;
2899 bfd_boolean b_greater
= FALSE
;
2901 ReqOptionList
*l_a
= a
->options
;
2902 ReqOptionList
*l_b
= b
->options
;
2904 /* We only care if they both are the same except for
2905 a const16 vs. an l32r. */
2907 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2909 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2910 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2911 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2913 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2915 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2917 /* This is the case we care about. */
2918 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2919 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2926 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2927 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2937 l_or_a
= l_or_a
->next
;
2938 l_or_b
= l_or_b
->next
;
2940 if (l_or_a
|| l_or_b
)
2949 /* Incomparable if the substitution was used differently in two cases. */
2950 if (a_greater
&& b_greater
)
2962 static TransitionRule
*
2963 xg_instruction_match (TInsn
*insn
)
2965 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2967 assert (insn
->opcode
< table
->num_opcodes
);
2969 /* Walk through all of the possible transitions. */
2970 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2972 TransitionRule
*rule
= l
->rule
;
2973 if (xg_instruction_matches_rule (insn
, rule
))
2980 /* Various Other Internal Functions. */
2983 is_unique_insn_expansion (TransitionRule
*r
)
2985 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2987 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2993 /* Check if there is exactly one relaxation for INSN that converts it to
2994 another instruction of equal or larger size. If so, and if TARG is
2995 non-null, go ahead and generate the relaxed instruction into TARG. If
2996 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2997 instruction, i.e., ignore relaxations that convert to an instruction of
2998 equal size. In some contexts where this function is used, only
2999 a single widening is allowed and the NARROW_ONLY argument is used to
3000 exclude cases like ADDI being "widened" to an ADDMI, which may
3001 later be relaxed to an ADDMI/ADDI pair. */
3004 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3006 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3008 TransitionRule
*match
= 0;
3010 assert (insn
->insn_type
== ITYPE_INSN
);
3011 assert (insn
->opcode
< table
->num_opcodes
);
3013 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3015 TransitionRule
*rule
= l
->rule
;
3017 if (xg_instruction_matches_rule (insn
, rule
)
3018 && is_unique_insn_expansion (rule
)
3019 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3020 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3031 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3036 /* Return the maximum number of bytes this opcode can expand to. */
3039 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3041 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3043 int max_size
= xg_get_single_size (opcode
);
3045 assert (opcode
< table
->num_opcodes
);
3047 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3049 TransitionRule
*rule
= l
->rule
;
3050 BuildInstr
*build_list
;
3055 build_list
= rule
->to_instr
;
3056 if (is_unique_insn_expansion (rule
))
3058 assert (build_list
->typ
== INSTR_INSTR
);
3059 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3062 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3064 switch (build_list
->typ
)
3067 this_size
+= xg_get_single_size (build_list
->opcode
);
3069 case INSTR_LITERAL_DEF
:
3070 case INSTR_LABEL_DEF
:
3075 if (this_size
> max_size
)
3076 max_size
= this_size
;
3082 /* Return the maximum number of literal bytes this opcode can generate. */
3085 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3087 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3091 assert (opcode
< table
->num_opcodes
);
3093 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3095 TransitionRule
*rule
= l
->rule
;
3096 BuildInstr
*build_list
;
3101 build_list
= rule
->to_instr
;
3102 if (is_unique_insn_expansion (rule
))
3104 assert (build_list
->typ
== INSTR_INSTR
);
3105 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3108 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3110 switch (build_list
->typ
)
3112 case INSTR_LITERAL_DEF
:
3113 /* Hard-coded 4-byte literal. */
3117 case INSTR_LABEL_DEF
:
3122 if (this_size
> max_size
)
3123 max_size
= this_size
;
3130 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3132 int steps_taken
= 0;
3133 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3136 assert (insn
->insn_type
== ITYPE_INSN
);
3137 assert (insn
->opcode
< table
->num_opcodes
);
3139 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3141 TransitionRule
*rule
= l
->rule
;
3143 if (xg_instruction_matches_rule (insn
, rule
))
3145 if (steps_taken
== lateral_steps
)
3155 get_special_literal_symbol (void)
3157 static symbolS
*sym
= NULL
;
3160 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3166 get_special_label_symbol (void)
3168 static symbolS
*sym
= NULL
;
3171 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3177 xg_valid_literal_expression (const expressionS
*exp
)
3194 /* This will check to see if the value can be converted into the
3195 operand type. It will return TRUE if it does not fit. */
3198 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3200 uint32 valbuf
= value
;
3201 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3207 /* Assumes: All immeds are constants. Check that all constants fit
3208 into their immeds; return FALSE if not. */
3211 xg_immeds_fit (const TInsn
*insn
)
3213 xtensa_isa isa
= xtensa_default_isa
;
3217 assert (insn
->insn_type
== ITYPE_INSN
);
3218 for (i
= 0; i
< n
; ++i
)
3220 const expressionS
*expr
= &insn
->tok
[i
];
3221 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3228 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3233 /* The symbol should have a fixup associated with it. */
3242 /* This should only be called after we have an initial
3243 estimate of the addresses. */
3246 xg_symbolic_immeds_fit (const TInsn
*insn
,
3252 xtensa_isa isa
= xtensa_default_isa
;
3260 assert (insn
->insn_type
== ITYPE_INSN
);
3262 for (i
= 0; i
< n
; ++i
)
3264 const expressionS
*expr
= &insn
->tok
[i
];
3265 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3272 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3278 /* Check for the worst case. */
3279 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3284 /* We only allow symbols for PC-relative references.
3285 If pc_frag == 0, then we don't have frag locations yet. */
3287 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3290 /* If it is a weak symbol, then assume it won't reach. */
3291 if (S_IS_WEAK (expr
->X_add_symbol
))
3294 if (is_direct_call_opcode (insn
->opcode
)
3295 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3297 /* If callee is undefined or in a different segment, be
3298 optimistic and assume it will be in range. */
3299 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3303 /* Only references within a segment can be known to fit in the
3304 operands at assembly time. */
3305 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3308 symbolP
= expr
->X_add_symbol
;
3309 sym_frag
= symbol_get_frag (symbolP
);
3310 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3311 pc
= pc_frag
->fr_address
+ pc_offset
;
3313 /* If frag has yet to be reached on this pass, assume it
3314 will move by STRETCH just as we did. If this is not so,
3315 it will be because some frag between grows, and that will
3316 force another pass. Beware zero-length frags. There
3317 should be a faster way to do this. */
3320 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3321 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3326 new_offset
= target
;
3327 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3328 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3333 /* The symbol should have a fixup associated with it. */
3342 /* Return TRUE on success. */
3345 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3350 memset (targ
, 0, sizeof (TInsn
));
3351 targ
->loc
= insn
->loc
;
3356 targ
->opcode
= bi
->opcode
;
3357 targ
->insn_type
= ITYPE_INSN
;
3358 targ
->is_specific_opcode
= FALSE
;
3360 for (; op
!= NULL
; op
= op
->next
)
3362 int op_num
= op
->op_num
;
3363 int op_data
= op
->op_data
;
3365 assert (op
->op_num
< MAX_INSN_ARGS
);
3367 if (targ
->ntok
<= op_num
)
3368 targ
->ntok
= op_num
+ 1;
3373 set_expr_const (&targ
->tok
[op_num
], op_data
);
3376 assert (op_data
< insn
->ntok
);
3377 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3380 sym
= get_special_literal_symbol ();
3381 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3384 sym
= get_special_label_symbol ();
3385 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3387 case OP_OPERAND_HI16U
:
3388 case OP_OPERAND_LOW16U
:
3389 assert (op_data
< insn
->ntok
);
3390 if (expr_is_const (&insn
->tok
[op_data
]))
3393 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3394 val
= xg_apply_userdef_op_fn (op
->typ
,
3397 targ
->tok
[op_num
].X_add_number
= val
;
3401 /* For const16 we can create relocations for these. */
3402 if (targ
->opcode
== XTENSA_UNDEFINED
3403 || (targ
->opcode
!= xtensa_const16_opcode
))
3405 assert (op_data
< insn
->ntok
);
3406 /* Need to build a O_lo16 or O_hi16. */
3407 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3408 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3410 if (op
->typ
== OP_OPERAND_HI16U
)
3411 targ
->tok
[op_num
].X_op
= O_hi16
;
3412 else if (op
->typ
== OP_OPERAND_LOW16U
)
3413 targ
->tok
[op_num
].X_op
= O_lo16
;
3420 /* currently handles:
3423 OP_OPERAND_F32MINUS */
3424 if (xg_has_userdef_op_fn (op
->typ
))
3426 assert (op_data
< insn
->ntok
);
3427 if (expr_is_const (&insn
->tok
[op_data
]))
3430 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3431 val
= xg_apply_userdef_op_fn (op
->typ
,
3434 targ
->tok
[op_num
].X_add_number
= val
;
3437 return FALSE
; /* We cannot use a relocation for this. */
3446 case INSTR_LITERAL_DEF
:
3448 targ
->opcode
= XTENSA_UNDEFINED
;
3449 targ
->insn_type
= ITYPE_LITERAL
;
3450 targ
->is_specific_opcode
= FALSE
;
3451 for (; op
!= NULL
; op
= op
->next
)
3453 int op_num
= op
->op_num
;
3454 int op_data
= op
->op_data
;
3455 assert (op
->op_num
< MAX_INSN_ARGS
);
3457 if (targ
->ntok
<= op_num
)
3458 targ
->ntok
= op_num
+ 1;
3463 assert (op_data
< insn
->ntok
);
3464 /* We can only pass resolvable literals through. */
3465 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3467 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3479 case INSTR_LABEL_DEF
:
3481 targ
->opcode
= XTENSA_UNDEFINED
;
3482 targ
->insn_type
= ITYPE_LABEL
;
3483 targ
->is_specific_opcode
= FALSE
;
3484 /* Literal with no ops is a label? */
3485 assert (op
== NULL
);
3496 /* Return TRUE on success. */
3499 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3501 for (; bi
!= NULL
; bi
= bi
->next
)
3503 TInsn
*next_insn
= istack_push_space (istack
);
3505 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3512 /* Return TRUE on valid expansion. */
3515 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3517 int stack_size
= istack
->ninsn
;
3518 int steps_taken
= 0;
3519 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3522 assert (insn
->insn_type
== ITYPE_INSN
);
3523 assert (insn
->opcode
< table
->num_opcodes
);
3525 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3527 TransitionRule
*rule
= l
->rule
;
3529 if (xg_instruction_matches_rule (insn
, rule
))
3531 if (lateral_steps
== steps_taken
)
3535 /* This is it. Expand the rule to the stack. */
3536 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3539 /* Check to see if it fits. */
3540 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3542 TInsn
*insn
= &istack
->insn
[i
];
3544 if (insn
->insn_type
== ITYPE_INSN
3545 && !tinsn_has_symbolic_operands (insn
)
3546 && !xg_immeds_fit (insn
))
3548 istack
->ninsn
= stack_size
;
3561 /* Relax the assembly instruction at least "min_steps".
3562 Return the number of steps taken. */
3565 xg_assembly_relax (IStack
*istack
,
3568 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3569 offsetT pc_offset
, /* offset in fragment */
3570 int min_steps
, /* minimum conversion steps */
3571 long stretch
) /* number of bytes stretched so far */
3573 int steps_taken
= 0;
3575 /* assert (has no symbolic operands)
3576 Some of its immeds don't fit.
3577 Try to build a relaxed version.
3578 This may go through a couple of stages
3579 of single instruction transformations before
3582 TInsn single_target
;
3584 int lateral_steps
= 0;
3585 int istack_size
= istack
->ninsn
;
3587 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3588 && steps_taken
>= min_steps
)
3590 istack_push (istack
, insn
);
3593 current_insn
= *insn
;
3595 /* Walk through all of the single instruction expansions. */
3596 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3598 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3602 if (steps_taken
>= min_steps
)
3604 istack_push (istack
, &single_target
);
3608 current_insn
= single_target
;
3611 /* Now check for a multi-instruction expansion. */
3612 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3614 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3617 if (steps_taken
>= min_steps
)
3619 istack_push (istack
, ¤t_insn
);
3624 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3626 if (steps_taken
>= min_steps
)
3630 istack
->ninsn
= istack_size
;
3633 /* It's not going to work -- use the original. */
3634 istack_push (istack
, insn
);
3640 xg_force_frag_space (int size
)
3642 /* This may have the side effect of creating a new fragment for the
3643 space to go into. I just do not like the name of the "frag"
3650 xg_finish_frag (char *last_insn
,
3651 enum xtensa_relax_statesE frag_state
,
3652 enum xtensa_relax_statesE slot0_state
,
3654 bfd_boolean is_insn
)
3656 /* Finish off this fragment so that it has at LEAST the desired
3657 max_growth. If it doesn't fit in this fragment, close this one
3658 and start a new one. In either case, return a pointer to the
3659 beginning of the growth area. */
3663 xg_force_frag_space (max_growth
);
3665 old_frag
= frag_now
;
3667 frag_now
->fr_opcode
= last_insn
;
3669 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3671 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3672 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3674 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3675 xtensa_set_frag_assembly_state (frag_now
);
3677 /* Just to make sure that we did not split it up. */
3678 assert (old_frag
->fr_next
== frag_now
);
3682 /* Return TRUE if the target frag is one of the next non-empty frags. */
3685 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3690 for (; fragP
; fragP
= fragP
->fr_next
)
3692 if (fragP
== target
)
3694 if (fragP
->fr_fix
!= 0)
3696 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3698 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3699 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3701 if (fragP
->fr_type
== rs_space
)
3709 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3711 xtensa_isa isa
= xtensa_default_isa
;
3713 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3718 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3719 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3722 for (i
= 0; i
< num_ops
; i
++)
3724 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3730 if (target_op
== -1)
3733 if (insn
->ntok
<= target_op
)
3736 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3739 sym
= insn
->tok
[target_op
].X_add_symbol
;
3743 if (insn
->tok
[target_op
].X_add_number
!= 0)
3746 target_frag
= symbol_get_frag (sym
);
3747 if (target_frag
== NULL
)
3750 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3751 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3759 xg_add_branch_and_loop_targets (TInsn
*insn
)
3761 xtensa_isa isa
= xtensa_default_isa
;
3762 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3764 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3767 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3768 && insn
->tok
[i
].X_op
== O_symbol
)
3769 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3773 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3774 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3778 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3780 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3781 && insn
->tok
[i
].X_op
== O_symbol
)
3783 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3784 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3785 if (S_IS_DEFINED (sym
))
3786 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3793 /* Return FALSE if no error. */
3796 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3801 switch (instr_spec
->typ
)
3804 new_insn
->insn_type
= ITYPE_INSN
;
3805 new_insn
->opcode
= instr_spec
->opcode
;
3806 new_insn
->is_specific_opcode
= FALSE
;
3807 new_insn
->loc
= old_insn
->loc
;
3809 case INSTR_LITERAL_DEF
:
3810 new_insn
->insn_type
= ITYPE_LITERAL
;
3811 new_insn
->opcode
= XTENSA_UNDEFINED
;
3812 new_insn
->is_specific_opcode
= FALSE
;
3813 new_insn
->loc
= old_insn
->loc
;
3815 case INSTR_LABEL_DEF
:
3816 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3820 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3823 const expressionS
*src_exp
;
3829 /* The expression must be the constant. */
3830 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3831 exp
= &new_insn
->tok
[b_op
->op_num
];
3832 set_expr_const (exp
, b_op
->op_data
);
3836 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3837 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3838 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3839 exp
= &new_insn
->tok
[b_op
->op_num
];
3840 copy_expr (exp
, src_exp
);
3845 as_bad (_("can't handle generation of literal/labels yet"));
3849 as_bad (_("can't handle undefined OP TYPE"));
3854 new_insn
->ntok
= num_ops
;
3859 /* Return TRUE if it was simplified. */
3862 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3864 TransitionRule
*rule
;
3865 BuildInstr
*insn_spec
;
3867 if (old_insn
->is_specific_opcode
|| !density_supported
)
3870 rule
= xg_instruction_match (old_insn
);
3874 insn_spec
= rule
->to_instr
;
3875 /* There should only be one. */
3876 assert (insn_spec
!= NULL
);
3877 assert (insn_spec
->next
== NULL
);
3878 if (insn_spec
->next
!= NULL
)
3881 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3887 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3888 l32i.n. (2) Check the number of operands. (3) Place the instruction
3889 tokens into the stack or relax it and place multiple
3890 instructions/literals onto the stack. Return FALSE if no error. */
3893 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3897 bfd_boolean do_expand
;
3899 memset (&new_insn
, 0, sizeof (TInsn
));
3901 /* Narrow it if we can. xg_simplify_insn now does all the
3902 appropriate checking (e.g., for the density option). */
3903 if (xg_simplify_insn (orig_insn
, &new_insn
))
3904 orig_insn
= &new_insn
;
3906 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3908 if (orig_insn
->ntok
< noperands
)
3910 as_bad (_("found %d operands for '%s': Expected %d"),
3912 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3916 if (orig_insn
->ntok
> noperands
)
3917 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3919 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3922 /* If there are not enough operands, we will assert above. If there
3923 are too many, just cut out the extras here. */
3924 orig_insn
->ntok
= noperands
;
3926 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3929 /* If the instruction will definitely need to be relaxed, it is better
3930 to expand it now for better scheduling. Decide whether to expand
3932 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3934 /* Calls should be expanded to longcalls only in the backend relaxation
3935 so that the assembly scheduler will keep the L32R/CALLX instructions
3937 if (is_direct_call_opcode (orig_insn
->opcode
))
3940 if (tinsn_has_symbolic_operands (orig_insn
))
3942 /* The values of symbolic operands are not known yet, so only expand
3943 now if an operand is "complex" (e.g., difference of symbols) and
3944 will have to be stored as a literal regardless of the value. */
3945 if (!tinsn_has_complex_operands (orig_insn
))
3948 else if (xg_immeds_fit (orig_insn
))
3952 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3954 istack_push (istack
, orig_insn
);
3960 /* Return TRUE if the section flags are marked linkonce
3961 or the name is .gnu.linkonce*. */
3964 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3966 flagword flags
, link_once_flags
;
3968 flags
= bfd_get_section_flags (abfd
, sec
);
3969 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3971 /* Flags might not be set yet. */
3972 if (!link_once_flags
)
3974 static size_t len
= sizeof ".gnu.linkonce.t.";
3976 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3977 link_once_flags
= SEC_LINK_ONCE
;
3979 return (link_once_flags
!= 0);
3984 xtensa_add_literal_sym (symbolS
*sym
)
3988 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3990 l
->next
= literal_syms
;
3996 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3998 static int lit_num
= 0;
3999 static char name
[256];
4002 sprintf (name
, ".L_lit_sym%d", lit_num
);
4004 /* Create a local symbol. If it is in a linkonce section, we have to
4005 be careful to make sure that if it is used in a relocation that the
4006 symbol will be in the output file. */
4007 if (get_is_linkonce_section (stdoutput
, sec
))
4009 symbolP
= symbol_new (name
, sec
, 0, frag
);
4010 S_CLEAR_EXTERNAL (symbolP
);
4011 /* symbolP->local = 1; */
4014 symbolP
= symbol_new (name
, sec
, 0, frag
);
4016 xtensa_add_literal_sym (symbolP
);
4018 frag
->tc_frag_data
.is_literal
= TRUE
;
4024 /* Currently all literals that are generated here are 32-bit L32R targets. */
4027 xg_assemble_literal (/* const */ TInsn
*insn
)
4030 symbolS
*lit_sym
= NULL
;
4032 /* size = 4 for L32R. It could easily be larger when we move to
4033 larger constants. Add a parameter later. */
4034 offsetT litsize
= 4;
4035 offsetT litalign
= 2; /* 2^2 = 4 */
4036 expressionS saved_loc
;
4037 expressionS
* emit_val
;
4039 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4041 assert (insn
->insn_type
== ITYPE_LITERAL
);
4042 assert (insn
->ntok
== 1); /* must be only one token here */
4044 xtensa_switch_to_literal_fragment (&state
);
4046 emit_val
= &insn
->tok
[0];
4047 if (emit_val
->X_op
== O_big
)
4049 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4052 /* This happens when someone writes a "movi a2, big_number". */
4053 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4054 _("invalid immediate"));
4055 xtensa_restore_emit_state (&state
);
4060 /* Force a 4-byte align here. Note that this opens a new frag, so all
4061 literals done with this function have a frag to themselves. That's
4062 important for the way text section literals work. */
4063 frag_align (litalign
, 0, 0);
4064 record_alignment (now_seg
, litalign
);
4066 if (emit_val
->X_op
== O_pltrel
)
4068 char *p
= frag_more (litsize
);
4069 xtensa_set_frag_assembly_state (frag_now
);
4070 if (emit_val
->X_add_symbol
)
4071 emit_val
->X_op
= O_symbol
;
4073 emit_val
->X_op
= O_constant
;
4074 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4075 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4078 emit_expr (emit_val
, litsize
);
4080 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4081 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4082 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4083 lit_sym
= frag_now
->fr_symbol
;
4084 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4087 xtensa_restore_emit_state (&state
);
4093 xg_assemble_literal_space (/* const */ int size
, int slot
)
4096 /* We might have to do something about this alignment. It only
4097 takes effect if something is placed here. */
4098 offsetT litalign
= 2; /* 2^2 = 4 */
4099 fragS
*lit_saved_frag
;
4101 assert (size
% 4 == 0);
4103 xtensa_switch_to_literal_fragment (&state
);
4105 /* Force a 4-byte align here. */
4106 frag_align (litalign
, 0, 0);
4107 record_alignment (now_seg
, litalign
);
4109 xg_force_frag_space (size
);
4111 lit_saved_frag
= frag_now
;
4112 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4113 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4114 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4115 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4118 xtensa_restore_emit_state (&state
);
4119 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4123 /* Put in a fixup record based on the opcode.
4124 Return TRUE on success. */
4127 xg_add_opcode_fix (TInsn
*tinsn
,
4135 xtensa_opcode opcode
= tinsn
->opcode
;
4136 bfd_reloc_code_real_type reloc
;
4137 reloc_howto_type
*howto
;
4141 reloc
= BFD_RELOC_NONE
;
4143 /* First try the special cases for "alternate" relocs. */
4144 if (opcode
== xtensa_l32r_opcode
)
4146 if (fragP
->tc_frag_data
.use_absolute_literals
)
4147 reloc
= encode_alt_reloc (slot
);
4149 else if (opcode
== xtensa_const16_opcode
)
4151 if (expr
->X_op
== O_lo16
)
4153 reloc
= encode_reloc (slot
);
4154 expr
->X_op
= O_symbol
;
4156 else if (expr
->X_op
== O_hi16
)
4158 reloc
= encode_alt_reloc (slot
);
4159 expr
->X_op
= O_symbol
;
4163 if (opnum
!= get_relaxable_immed (opcode
))
4165 as_bad (_("invalid relocation for operand %i of '%s'"),
4166 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4170 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4171 into the symbol table where the generic portions of the assembler
4172 won't know what to do with them. */
4173 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4175 as_bad (_("invalid expression for operand %i of '%s'"),
4176 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4180 /* Next try the generic relocs. */
4181 if (reloc
== BFD_RELOC_NONE
)
4182 reloc
= encode_reloc (slot
);
4183 if (reloc
== BFD_RELOC_NONE
)
4185 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4189 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4192 as_bad (_("undefined symbol for opcode \"%s\""),
4193 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4197 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4198 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4199 howto
->pc_relative
, reloc
);
4200 the_fix
->fx_no_overflow
= 1;
4202 if (expr
->X_add_symbol
4203 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4204 || S_IS_WEAK (expr
->X_add_symbol
)))
4205 the_fix
->fx_plt
= TRUE
;
4207 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4208 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4209 the_fix
->tc_fix_data
.slot
= slot
;
4216 xg_emit_insn_to_buf (TInsn
*tinsn
,
4221 bfd_boolean build_fix
)
4223 static xtensa_insnbuf insnbuf
= NULL
;
4224 bfd_boolean has_symbolic_immed
= FALSE
;
4225 bfd_boolean ok
= TRUE
;
4227 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4229 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4230 if (has_symbolic_immed
&& build_fix
)
4233 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4234 expressionS
*exp
= &tinsn
->tok
[opnum
];
4236 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4239 fragP
->tc_frag_data
.is_insn
= TRUE
;
4240 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4241 (unsigned char *) buf
, 0);
4247 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4249 symbolS
*sym
= get_special_literal_symbol ();
4253 assert (insn
->insn_type
== ITYPE_INSN
);
4254 for (i
= 0; i
< insn
->ntok
; i
++)
4255 if (insn
->tok
[i
].X_add_symbol
== sym
)
4256 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4262 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4264 symbolS
*sym
= get_special_label_symbol ();
4266 /* assert (!insn->is_literal); */
4267 for (i
= 0; i
< insn
->ntok
; i
++)
4268 if (insn
->tok
[i
].X_add_symbol
== sym
)
4269 insn
->tok
[i
].X_add_symbol
= label_sym
;
4274 /* Return TRUE if the instruction can write to the specified
4275 integer register. */
4278 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4282 xtensa_isa isa
= xtensa_default_isa
;
4284 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4286 for (i
= 0; i
< num_ops
; i
++)
4289 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4290 if ((inout
== 'o' || inout
== 'm')
4291 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4293 xtensa_regfile opnd_rf
=
4294 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4295 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4297 if ((insn
->tok
[i
].X_op
== O_register
)
4298 && (insn
->tok
[i
].X_add_number
== regnum
))
4308 is_bad_loopend_opcode (const TInsn
*tinsn
)
4310 xtensa_opcode opcode
= tinsn
->opcode
;
4312 if (opcode
== XTENSA_UNDEFINED
)
4315 if (opcode
== xtensa_call0_opcode
4316 || opcode
== xtensa_callx0_opcode
4317 || opcode
== xtensa_call4_opcode
4318 || opcode
== xtensa_callx4_opcode
4319 || opcode
== xtensa_call8_opcode
4320 || opcode
== xtensa_callx8_opcode
4321 || opcode
== xtensa_call12_opcode
4322 || opcode
== xtensa_callx12_opcode
4323 || opcode
== xtensa_isync_opcode
4324 || opcode
== xtensa_ret_opcode
4325 || opcode
== xtensa_ret_n_opcode
4326 || opcode
== xtensa_retw_opcode
4327 || opcode
== xtensa_retw_n_opcode
4328 || opcode
== xtensa_waiti_opcode
4329 || opcode
== xtensa_rsr_lcount_opcode
)
4336 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4337 This allows the debugger to add unaligned labels.
4338 Also, the assembler generates stabs labels that need
4339 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4342 is_unaligned_label (symbolS
*sym
)
4344 const char *name
= S_GET_NAME (sym
);
4345 static size_t fake_size
= 0;
4349 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4352 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4354 fake_size
= strlen (FAKE_LABEL_NAME
);
4357 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4358 && (name
[fake_size
] == 'F'
4359 || name
[fake_size
] == 'L'
4360 || (name
[fake_size
] == 'e'
4361 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4369 next_non_empty_frag (const fragS
*fragP
)
4371 fragS
*next_fragP
= fragP
->fr_next
;
4373 /* Sometimes an empty will end up here due storage allocation issues.
4374 So we have to skip until we find something legit. */
4375 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4376 next_fragP
= next_fragP
->fr_next
;
4378 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4386 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4388 xtensa_opcode out_opcode
;
4389 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4391 if (next_fragP
== NULL
)
4394 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4395 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4397 *opcode
= out_opcode
;
4405 frag_format_size (const fragS
*fragP
)
4407 static xtensa_insnbuf insnbuf
= NULL
;
4408 xtensa_isa isa
= xtensa_default_isa
;
4413 insnbuf
= xtensa_insnbuf_alloc (isa
);
4416 return XTENSA_UNDEFINED
;
4418 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4419 (unsigned char *) fragP
->fr_literal
, 0);
4421 fmt
= xtensa_format_decode (isa
, insnbuf
);
4422 if (fmt
== XTENSA_UNDEFINED
)
4423 return XTENSA_UNDEFINED
;
4424 fmt_size
= xtensa_format_length (isa
, fmt
);
4426 /* If the next format won't be changing due to relaxation, just
4427 return the length of the first format. */
4428 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4431 /* If during relaxation we have to pull an instruction out of a
4432 multi-slot instruction, we will return the more conservative
4433 number. This works because alignment on bigger instructions
4434 is more restrictive than alignment on smaller instructions.
4435 This is more conservative than we would like, but it happens
4438 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4441 /* If we aren't doing one of our own relaxations or it isn't
4442 slot-based, then the insn size won't change. */
4443 if (fragP
->fr_type
!= rs_machine_dependent
)
4445 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4448 /* If an instruction is about to grow, return the longer size. */
4449 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4450 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4453 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4454 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4461 next_frag_format_size (const fragS
*fragP
)
4463 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4464 return frag_format_size (next_fragP
);
4468 /* If the next legit fragment is an end-of-loop marker,
4469 switch its state so it will instantiate a NOP. */
4472 update_next_frag_state (fragS
*fragP
)
4474 fragS
*next_fragP
= fragP
->fr_next
;
4475 fragS
*new_target
= NULL
;
4479 /* We are guaranteed there will be one of these... */
4480 while (!(next_fragP
->fr_type
== rs_machine_dependent
4481 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4482 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4483 next_fragP
= next_fragP
->fr_next
;
4485 assert (next_fragP
->fr_type
== rs_machine_dependent
4486 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4487 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4489 /* ...and one of these. */
4490 new_target
= next_fragP
->fr_next
;
4491 while (!(new_target
->fr_type
== rs_machine_dependent
4492 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4493 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4494 new_target
= new_target
->fr_next
;
4496 assert (new_target
->fr_type
== rs_machine_dependent
4497 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4498 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4501 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4503 if (next_fragP
->fr_type
== rs_machine_dependent
4504 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4506 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4510 next_fragP
= next_fragP
->fr_next
;
4516 next_frag_is_branch_target (const fragS
*fragP
)
4518 /* Sometimes an empty will end up here due to storage allocation issues,
4519 so we have to skip until we find something legit. */
4520 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4522 if (fragP
->tc_frag_data
.is_branch_target
)
4524 if (fragP
->fr_fix
!= 0)
4532 next_frag_is_loop_target (const fragS
*fragP
)
4534 /* Sometimes an empty will end up here due storage allocation issues.
4535 So we have to skip until we find something legit. */
4536 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4538 if (fragP
->tc_frag_data
.is_loop_target
)
4540 if (fragP
->fr_fix
!= 0)
4548 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4550 const fragS
*next_fragp
= fragp
->fr_next
;
4551 xtensa_opcode next_opcode
;
4553 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4556 /* Sometimes an empty will end up here due to storage allocation issues,
4557 so we have to skip until we find something legit. */
4558 while (next_fragp
->fr_fix
== 0)
4559 next_fragp
= next_fragp
->fr_next
;
4561 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4564 /* There is some implicit knowledge encoded in here.
4565 The LOOP instructions that are NOT RELAX_IMMED have
4566 been relaxed. Note that we can assume that the LOOP
4567 instruction is in slot 0 because loops aren't bundleable. */
4568 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4569 return get_expanded_loop_offset (next_opcode
);
4575 /* Mark a location where we can later insert literal frags. Update
4576 the section's literal_pool_loc, so subsequent literals can be
4577 placed nearest to their use. */
4580 xtensa_mark_literal_pool_location (void)
4582 /* Any labels pointing to the current location need
4583 to be adjusted to after the literal pool. */
4585 fragS
*pool_location
;
4587 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4590 frag_align (2, 0, 0);
4591 record_alignment (now_seg
, 2);
4593 /* We stash info in these frags so we can later move the literal's
4594 fixes into this frchain's fix list. */
4595 pool_location
= frag_now
;
4596 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4597 frag_variant (rs_machine_dependent
, 0, 0,
4598 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4599 xtensa_set_frag_assembly_state (frag_now
);
4600 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4601 frag_variant (rs_machine_dependent
, 0, 0,
4602 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4603 xtensa_set_frag_assembly_state (frag_now
);
4605 /* Now put a frag into the literal pool that points to this location. */
4606 set_literal_pool_location (now_seg
, pool_location
);
4607 xtensa_switch_to_non_abs_literal_fragment (&s
);
4608 frag_align (2, 0, 0);
4609 record_alignment (now_seg
, 2);
4611 /* Close whatever frag is there. */
4612 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4613 xtensa_set_frag_assembly_state (frag_now
);
4614 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4615 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4616 xtensa_restore_emit_state (&s
);
4617 xtensa_set_frag_assembly_state (frag_now
);
4621 /* Build a nop of the correct size into tinsn. */
4624 build_nop (TInsn
*tinsn
, int size
)
4630 tinsn
->opcode
= xtensa_nop_n_opcode
;
4632 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4633 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4637 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4639 tinsn
->opcode
= xtensa_or_opcode
;
4640 set_expr_const (&tinsn
->tok
[0], 1);
4641 set_expr_const (&tinsn
->tok
[1], 1);
4642 set_expr_const (&tinsn
->tok
[2], 1);
4646 tinsn
->opcode
= xtensa_nop_opcode
;
4648 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4653 /* Assemble a NOP of the requested size in the buffer. User must have
4654 allocated "buf" with at least "size" bytes. */
4657 assemble_nop (int size
, char *buf
)
4659 static xtensa_insnbuf insnbuf
= NULL
;
4662 build_nop (&tinsn
, size
);
4665 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4667 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4668 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4669 (unsigned char *) buf
, 0);
4673 /* Return the number of bytes for the offset of the expanded loop
4674 instruction. This should be incorporated into the relaxation
4675 specification but is hard-coded here. This is used to auto-align
4676 the loop instruction. It is invalid to call this function if the
4677 configuration does not have loops or if the opcode is not a loop
4681 get_expanded_loop_offset (xtensa_opcode opcode
)
4683 /* This is the OFFSET of the loop instruction in the expanded loop.
4684 This MUST correspond directly to the specification of the loop
4685 expansion. It will be validated on fragment conversion. */
4686 assert (opcode
!= XTENSA_UNDEFINED
);
4687 if (opcode
== xtensa_loop_opcode
)
4689 if (opcode
== xtensa_loopnez_opcode
)
4691 if (opcode
== xtensa_loopgtz_opcode
)
4693 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4699 get_literal_pool_location (segT seg
)
4701 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4706 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4708 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4712 /* Set frag assembly state should be called when a new frag is
4713 opened and after a frag has been closed. */
4716 xtensa_set_frag_assembly_state (fragS
*fragP
)
4718 if (!density_supported
)
4719 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4721 /* This function is called from subsegs_finish, which is called
4722 after xtensa_end, so we can't use "use_transform" or
4723 "use_schedule" here. */
4724 if (!directive_state
[directive_transform
])
4725 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4726 if (directive_state
[directive_longcalls
])
4727 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4728 fragP
->tc_frag_data
.use_absolute_literals
=
4729 directive_state
[directive_absolute_literals
];
4730 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4735 relaxable_section (asection
*sec
)
4737 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4742 xtensa_find_unmarked_state_frags (void)
4746 /* Walk over each fragment of all of the current segments. For each
4747 unmarked fragment, mark it with the same info as the previous
4749 for (seclist
= &stdoutput
->sections
;
4750 seclist
&& *seclist
;
4751 seclist
= &(*seclist
)->next
)
4753 segT sec
= *seclist
;
4754 segment_info_type
*seginfo
;
4757 flags
= bfd_get_section_flags (stdoutput
, sec
);
4758 if (flags
& SEC_DEBUGGING
)
4760 if (!(flags
& SEC_ALLOC
))
4763 seginfo
= seg_info (sec
);
4764 if (seginfo
&& seginfo
->frchainP
)
4766 fragS
*last_fragP
= 0;
4767 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4768 fragP
= fragP
->fr_next
)
4770 if (fragP
->fr_fix
!= 0
4771 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4773 if (last_fragP
== 0)
4775 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4776 _("assembly state not set for first frag in section %s"),
4781 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4782 fragP
->tc_frag_data
.is_no_density
=
4783 last_fragP
->tc_frag_data
.is_no_density
;
4784 fragP
->tc_frag_data
.is_no_transform
=
4785 last_fragP
->tc_frag_data
.is_no_transform
;
4786 fragP
->tc_frag_data
.use_longcalls
=
4787 last_fragP
->tc_frag_data
.use_longcalls
;
4788 fragP
->tc_frag_data
.use_absolute_literals
=
4789 last_fragP
->tc_frag_data
.use_absolute_literals
;
4792 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4801 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4803 void *unused ATTRIBUTE_UNUSED
)
4805 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4806 segment_info_type
*seginfo
= seg_info (sec
);
4807 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4809 if (flags
& SEC_CODE
)
4811 xtensa_isa isa
= xtensa_default_isa
;
4812 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4813 while (frag
!= NULL
)
4815 if (frag
->tc_frag_data
.is_branch_target
)
4818 addressT branch_align
, frag_addr
;
4821 xtensa_insnbuf_from_chars
4822 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4823 fmt
= xtensa_format_decode (isa
, insnbuf
);
4824 op_size
= xtensa_format_length (isa
, fmt
);
4825 branch_align
= 1 << branch_align_power (sec
);
4826 frag_addr
= frag
->fr_address
% branch_align
;
4827 if (frag_addr
+ op_size
> branch_align
)
4828 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4829 _("unaligned branch target: %d bytes at 0x%lx"),
4830 op_size
, (long) frag
->fr_address
);
4832 frag
= frag
->fr_next
;
4834 xtensa_insnbuf_free (isa
, insnbuf
);
4840 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4842 void *unused ATTRIBUTE_UNUSED
)
4844 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4845 segment_info_type
*seginfo
= seg_info (sec
);
4846 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4847 xtensa_isa isa
= xtensa_default_isa
;
4849 if (flags
& SEC_CODE
)
4851 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4852 while (frag
!= NULL
)
4854 if (frag
->tc_frag_data
.is_first_loop_insn
)
4860 xtensa_insnbuf_from_chars
4861 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4862 fmt
= xtensa_format_decode (isa
, insnbuf
);
4863 op_size
= xtensa_format_length (isa
, fmt
);
4864 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4866 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4867 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4868 _("unaligned loop: %d bytes at 0x%lx"),
4869 op_size
, (long) frag
->fr_address
);
4871 frag
= frag
->fr_next
;
4873 xtensa_insnbuf_free (isa
, insnbuf
);
4879 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4881 xtensa_isa isa
= xtensa_default_isa
;
4882 static xtensa_insnbuf insnbuf
= NULL
;
4883 static xtensa_insnbuf slotbuf
= NULL
;
4886 bfd_boolean alt_reloc
;
4887 xtensa_opcode opcode
;
4888 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4890 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4892 as_fatal (_("unexpected fix"));
4896 insnbuf
= xtensa_insnbuf_alloc (isa
);
4897 slotbuf
= xtensa_insnbuf_alloc (isa
);
4900 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4901 fmt
= xtensa_format_decode (isa
, insnbuf
);
4902 if (fmt
== XTENSA_UNDEFINED
)
4903 as_fatal (_("undecodable fix"));
4904 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4905 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4906 if (opcode
== XTENSA_UNDEFINED
)
4907 as_fatal (_("undecodable fix"));
4909 /* CONST16 immediates are not PC-relative, despite the fact that we
4910 reuse the normal PC-relative operand relocations for the low part
4911 of a CONST16 operand. */
4912 if (opcode
== xtensa_const16_opcode
)
4915 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4916 get_relaxable_immed (opcode
), val
,
4917 fixP
->fx_file
, fixP
->fx_line
);
4919 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4920 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4926 /* External Functions and Other GAS Hooks. */
4929 xtensa_target_format (void)
4931 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4936 xtensa_file_arch_init (bfd
*abfd
)
4938 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4943 md_number_to_chars (char *buf
, valueT val
, int n
)
4945 if (target_big_endian
)
4946 number_to_chars_bigendian (buf
, val
, n
);
4948 number_to_chars_littleendian (buf
, val
, n
);
4952 /* This function is called once, at assembler startup time. It should
4953 set up all the tables, etc. that the MD part of the assembler will
4959 segT current_section
= now_seg
;
4960 int current_subsec
= now_subseg
;
4963 xtensa_default_isa
= xtensa_isa_init (0, 0);
4964 isa
= xtensa_default_isa
;
4968 /* Set up the .literal, .fini.literal and .init.literal sections. */
4969 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4970 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4971 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4972 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4973 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4975 subseg_set (current_section
, current_subsec
);
4977 xg_init_vinsn (&cur_vinsn
);
4979 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4980 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4981 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4982 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4983 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4984 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4985 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4986 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4987 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4988 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4989 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4990 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4991 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4992 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4993 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4994 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4995 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4996 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4997 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4998 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4999 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5000 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5001 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5002 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5003 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5004 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5005 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5006 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5007 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5009 init_op_placement_info_table ();
5011 /* Set up the assembly state. */
5012 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5013 xtensa_set_frag_assembly_state (frag_now
);
5017 /* TC_INIT_FIX_DATA hook */
5020 xtensa_init_fix_data (fixS
*x
)
5022 x
->tc_fix_data
.slot
= 0;
5023 x
->tc_fix_data
.X_add_symbol
= NULL
;
5024 x
->tc_fix_data
.X_add_number
= 0;
5028 /* tc_frob_label hook */
5031 xtensa_frob_label (symbolS
*sym
)
5035 if (cur_vinsn
.inside_bundle
)
5037 as_bad (_("labels are not valid inside bundles"));
5041 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5043 /* Since the label was already attached to a frag associated with the
5044 previous basic block, it now needs to be reset to the current frag. */
5045 symbol_set_frag (sym
, frag_now
);
5046 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5048 if (generating_literals
)
5049 xtensa_add_literal_sym (sym
);
5051 xtensa_add_insn_label (sym
);
5053 if (symbol_get_tc (sym
)->is_loop_target
)
5055 if ((get_last_insn_flags (now_seg
, now_subseg
)
5056 & FLAG_IS_BAD_LOOPEND
) != 0)
5057 as_bad (_("invalid last instruction for a zero-overhead loop"));
5059 xtensa_set_frag_assembly_state (frag_now
);
5060 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5061 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5063 xtensa_set_frag_assembly_state (frag_now
);
5064 xtensa_move_labels (frag_now
, 0, TRUE
);
5067 /* No target aligning in the absolute section. */
5068 if (now_seg
!= absolute_section
5069 && do_align_targets ()
5070 && !is_unaligned_label (sym
)
5071 && !generating_literals
)
5073 xtensa_set_frag_assembly_state (frag_now
);
5075 frag_var (rs_machine_dependent
,
5077 RELAX_DESIRE_ALIGN_IF_TARGET
,
5078 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5079 xtensa_set_frag_assembly_state (frag_now
);
5080 xtensa_move_labels (frag_now
, 0, TRUE
);
5083 /* We need to mark the following properties even if we aren't aligning. */
5085 /* If the label is already known to be a branch target, i.e., a
5086 forward branch, mark the frag accordingly. Backward branches
5087 are handled by xg_add_branch_and_loop_targets. */
5088 if (symbol_get_tc (sym
)->is_branch_target
)
5089 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5091 /* Loops only go forward, so they can be identified here. */
5092 if (symbol_get_tc (sym
)->is_loop_target
)
5093 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5095 dwarf2_emit_label (sym
);
5099 /* tc_unrecognized_line hook */
5102 xtensa_unrecognized_line (int ch
)
5107 if (cur_vinsn
.inside_bundle
== 0)
5109 /* PR8110: Cannot emit line number info inside a FLIX bundle
5110 when using --gstabs. Temporarily disable debug info. */
5111 generate_lineno_debug ();
5112 if (debug_type
== DEBUG_STABS
)
5114 xt_saved_debug_type
= debug_type
;
5115 debug_type
= DEBUG_NONE
;
5118 cur_vinsn
.inside_bundle
= 1;
5122 as_bad (_("extra opening brace"));
5128 if (cur_vinsn
.inside_bundle
)
5129 finish_vinsn (&cur_vinsn
);
5132 as_bad (_("extra closing brace"));
5137 as_bad (_("syntax error"));
5144 /* md_flush_pending_output hook */
5147 xtensa_flush_pending_output (void)
5149 if (cur_vinsn
.inside_bundle
)
5150 as_bad (_("missing closing brace"));
5152 /* If there is a non-zero instruction fragment, close it. */
5153 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5155 frag_wane (frag_now
);
5157 xtensa_set_frag_assembly_state (frag_now
);
5159 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5161 xtensa_clear_insn_labels ();
5165 /* We had an error while parsing an instruction. The string might look
5166 like this: "insn arg1, arg2 }". If so, we need to see the closing
5167 brace and reset some fields. Otherwise, the vinsn never gets closed
5168 and the num_slots field will grow past the end of the array of slots,
5169 and bad things happen. */
5172 error_reset_cur_vinsn (void)
5174 if (cur_vinsn
.inside_bundle
)
5176 if (*input_line_pointer
== '}'
5177 || *(input_line_pointer
- 1) == '}'
5178 || *(input_line_pointer
- 2) == '}')
5179 xg_clear_vinsn (&cur_vinsn
);
5185 md_assemble (char *str
)
5187 xtensa_isa isa
= xtensa_default_isa
;
5190 bfd_boolean has_underbar
= FALSE
;
5191 char *arg_strings
[MAX_INSN_ARGS
];
5193 TInsn orig_insn
; /* Original instruction from the input. */
5195 tinsn_init (&orig_insn
);
5197 /* Split off the opcode. */
5198 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5199 opname
= xmalloc (opnamelen
+ 1);
5200 memcpy (opname
, str
, opnamelen
);
5201 opname
[opnamelen
] = '\0';
5203 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5206 as_bad (_("syntax error"));
5210 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5213 /* Check for an underbar prefix. */
5216 has_underbar
= TRUE
;
5220 orig_insn
.insn_type
= ITYPE_INSN
;
5222 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5224 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5225 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5227 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5228 if (fmt
== XTENSA_UNDEFINED
)
5230 as_bad (_("unknown opcode or format name '%s'"), opname
);
5231 error_reset_cur_vinsn ();
5234 if (!cur_vinsn
.inside_bundle
)
5236 as_bad (_("format names only valid inside bundles"));
5237 error_reset_cur_vinsn ();
5240 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5241 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5243 cur_vinsn
.format
= fmt
;
5244 free (has_underbar
? opname
- 1 : opname
);
5245 error_reset_cur_vinsn ();
5249 /* Parse the arguments. */
5250 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5252 as_bad (_("syntax error"));
5253 error_reset_cur_vinsn ();
5257 /* Free the opcode and argument strings, now that they've been parsed. */
5258 free (has_underbar
? opname
- 1 : opname
);
5260 while (num_args
-- > 0)
5261 free (arg_strings
[num_args
]);
5263 /* Get expressions for invisible operands. */
5264 if (get_invisible_operands (&orig_insn
))
5266 error_reset_cur_vinsn ();
5270 /* Check for the right number and type of arguments. */
5271 if (tinsn_check_arguments (&orig_insn
))
5273 error_reset_cur_vinsn ();
5277 dwarf2_where (&orig_insn
.loc
);
5279 xg_add_branch_and_loop_targets (&orig_insn
);
5281 /* Special-case for "entry" instruction. */
5282 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5284 /* Check that the third opcode (#2) is >= 16. */
5285 if (orig_insn
.ntok
>= 3)
5287 expressionS
*exp
= &orig_insn
.tok
[2];
5291 if (exp
->X_add_number
< 16)
5292 as_warn (_("entry instruction with stack decrement < 16"));
5296 as_warn (_("entry instruction with non-constant decrement"));
5302 assemble_tokens (opcode, tok, ntok);
5303 expand the tokens from the orig_insn into the
5304 stack of instructions that will not expand
5305 unless required at relaxation time. */
5307 if (!cur_vinsn
.inside_bundle
)
5308 emit_single_op (&orig_insn
);
5309 else /* We are inside a bundle. */
5311 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5312 cur_vinsn
.num_slots
++;
5313 if (*input_line_pointer
== '}'
5314 || *(input_line_pointer
- 1) == '}'
5315 || *(input_line_pointer
- 2) == '}')
5316 finish_vinsn (&cur_vinsn
);
5319 /* We've just emitted a new instruction so clear the list of labels. */
5320 xtensa_clear_insn_labels ();
5324 /* HANDLE_ALIGN hook */
5326 /* For a .align directive, we mark the previous block with the alignment
5327 information. This will be placed in the object file in the
5328 property section corresponding to this section. */
5331 xtensa_handle_align (fragS
*fragP
)
5334 && ! fragP
->tc_frag_data
.is_literal
5335 && (fragP
->fr_type
== rs_align
5336 || fragP
->fr_type
== rs_align_code
)
5337 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5338 && fragP
->fr_offset
> 0
5339 && now_seg
!= bss_section
)
5341 fragP
->tc_frag_data
.is_align
= TRUE
;
5342 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5345 if (fragP
->fr_type
== rs_align_test
)
5348 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5350 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5351 _("unaligned entry instruction"));
5356 /* TC_FRAG_INIT hook */
5359 xtensa_frag_init (fragS
*frag
)
5361 xtensa_set_frag_assembly_state (frag
);
5366 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5372 /* Round up a section size to the appropriate boundary. */
5375 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5377 return size
; /* Byte alignment is fine. */
5382 md_pcrel_from (fixS
*fixP
)
5385 static xtensa_insnbuf insnbuf
= NULL
;
5386 static xtensa_insnbuf slotbuf
= NULL
;
5389 xtensa_opcode opcode
;
5392 xtensa_isa isa
= xtensa_default_isa
;
5393 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5394 bfd_boolean alt_reloc
;
5396 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5401 insnbuf
= xtensa_insnbuf_alloc (isa
);
5402 slotbuf
= xtensa_insnbuf_alloc (isa
);
5405 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5406 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5407 fmt
= xtensa_format_decode (isa
, insnbuf
);
5409 if (fmt
== XTENSA_UNDEFINED
)
5410 as_fatal (_("bad instruction format"));
5412 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5413 as_fatal (_("invalid relocation"));
5415 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5416 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5418 /* Check for "alternate" relocations (operand not specified). None
5419 of the current uses for these are really PC-relative. */
5420 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5422 if (opcode
!= xtensa_l32r_opcode
5423 && opcode
!= xtensa_const16_opcode
)
5424 as_fatal (_("invalid relocation for '%s' instruction"),
5425 xtensa_opcode_name (isa
, opcode
));
5429 opnum
= get_relaxable_immed (opcode
);
5431 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5432 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5434 as_bad_where (fixP
->fx_file
,
5436 _("invalid relocation for operand %d of '%s'"),
5437 opnum
, xtensa_opcode_name (isa
, opcode
));
5440 return 0 - opnd_value
;
5444 /* TC_FORCE_RELOCATION hook */
5447 xtensa_force_relocation (fixS
*fix
)
5449 switch (fix
->fx_r_type
)
5451 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5452 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5453 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5454 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5455 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5456 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5457 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5458 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5459 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5460 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5461 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5462 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5463 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5464 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5465 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5466 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5472 if (linkrelax
&& fix
->fx_addsy
5473 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5476 return generic_force_reloc (fix
);
5480 /* TC_VALIDATE_FIX_SUB hook */
5483 xtensa_validate_fix_sub (fixS
*fix
)
5485 segT add_symbol_segment
, sub_symbol_segment
;
5487 /* The difference of two symbols should be resolved by the assembler when
5488 linkrelax is not set. If the linker may relax the section containing
5489 the symbols, then an Xtensa DIFF relocation must be generated so that
5490 the linker knows to adjust the difference value. */
5491 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5494 /* Make sure both symbols are in the same segment, and that segment is
5495 "normal" and relaxable. If the segment is not "normal", then the
5496 fix is not valid. If the segment is not "relaxable", then the fix
5497 should have been handled earlier. */
5498 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5499 if (! SEG_NORMAL (add_symbol_segment
) ||
5500 ! relaxable_section (add_symbol_segment
))
5502 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5503 return (sub_symbol_segment
== add_symbol_segment
);
5507 /* NO_PSEUDO_DOT hook */
5509 /* This function has nothing to do with pseudo dots, but this is the
5510 nearest macro to where the check needs to take place. FIXME: This
5514 xtensa_check_inside_bundle (void)
5516 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5517 as_bad (_("directives are not valid inside bundles"));
5519 /* This function must always return FALSE because it is called via a
5520 macro that has nothing to do with bundling. */
5525 /* md_elf_section_change_hook */
5528 xtensa_elf_section_change_hook (void)
5530 /* Set up the assembly state. */
5531 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5532 xtensa_set_frag_assembly_state (frag_now
);
5536 /* tc_fix_adjustable hook */
5539 xtensa_fix_adjustable (fixS
*fixP
)
5541 /* An offset is not allowed in combination with the difference of two
5542 symbols, but that cannot be easily detected after a local symbol
5543 has been adjusted to a (section+offset) form. Return 0 so that such
5544 an fix will not be adjusted. */
5545 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5546 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5549 /* We need the symbol name for the VTABLE entries. */
5550 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5551 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5559 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5561 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5564 switch (fixP
->fx_r_type
)
5569 if (linkrelax
&& fixP
->fx_subsy
)
5571 switch (fixP
->fx_r_type
)
5574 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5577 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5580 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5586 /* An offset is only allowed when it results from adjusting a
5587 local symbol into a section-relative offset. If the offset
5588 came from the original expression, tc_fix_adjustable will have
5589 prevented the fix from being converted to a section-relative
5590 form so that we can flag the error here. */
5591 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5593 _("cannot represent subtraction with an offset"));
5595 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5596 - S_GET_VALUE (fixP
->fx_subsy
));
5598 /* The difference value gets written out, and the DIFF reloc
5599 identifies the address of the subtracted symbol (i.e., the one
5600 with the lowest address). */
5602 fixP
->fx_offset
-= val
;
5603 fixP
->fx_subsy
= NULL
;
5605 else if (! fixP
->fx_addsy
)
5612 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5613 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5616 case BFD_RELOC_XTENSA_SLOT0_OP
:
5617 case BFD_RELOC_XTENSA_SLOT1_OP
:
5618 case BFD_RELOC_XTENSA_SLOT2_OP
:
5619 case BFD_RELOC_XTENSA_SLOT3_OP
:
5620 case BFD_RELOC_XTENSA_SLOT4_OP
:
5621 case BFD_RELOC_XTENSA_SLOT5_OP
:
5622 case BFD_RELOC_XTENSA_SLOT6_OP
:
5623 case BFD_RELOC_XTENSA_SLOT7_OP
:
5624 case BFD_RELOC_XTENSA_SLOT8_OP
:
5625 case BFD_RELOC_XTENSA_SLOT9_OP
:
5626 case BFD_RELOC_XTENSA_SLOT10_OP
:
5627 case BFD_RELOC_XTENSA_SLOT11_OP
:
5628 case BFD_RELOC_XTENSA_SLOT12_OP
:
5629 case BFD_RELOC_XTENSA_SLOT13_OP
:
5630 case BFD_RELOC_XTENSA_SLOT14_OP
:
5633 /* Write the tentative value of a PC-relative relocation to a
5634 local symbol into the instruction. The value will be ignored
5635 by the linker, and it makes the object file disassembly
5636 readable when all branch targets are encoded in relocations. */
5638 assert (fixP
->fx_addsy
);
5639 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5640 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5642 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5643 - md_pcrel_from (fixP
));
5644 (void) xg_apply_fix_value (fixP
, val
);
5647 else if (! fixP
->fx_addsy
)
5650 if (xg_apply_fix_value (fixP
, val
))
5655 case BFD_RELOC_XTENSA_PLT
:
5656 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5657 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5658 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5659 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5660 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5661 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5662 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5663 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5664 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5665 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5666 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5667 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5668 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5669 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5670 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5671 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5672 /* These all need to be resolved at link-time. Do nothing now. */
5675 case BFD_RELOC_VTABLE_INHERIT
:
5676 case BFD_RELOC_VTABLE_ENTRY
:
5681 as_bad (_("unhandled local relocation fix %s"),
5682 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5688 md_atof (int type
, char *litP
, int *sizeP
)
5691 LITTLENUM_TYPE words
[4];
5707 return "bad call to md_atof";
5710 t
= atof_ieee (input_line_pointer
, type
, words
);
5712 input_line_pointer
= t
;
5716 for (i
= prec
- 1; i
>= 0; i
--)
5719 if (target_big_endian
)
5720 idx
= (prec
- 1 - i
);
5722 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5731 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5733 return total_frag_text_expansion (fragP
);
5737 /* Translate internal representation of relocation info to BFD target
5741 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5745 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5746 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5747 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5748 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5750 /* Make sure none of our internal relocations make it this far.
5751 They'd better have been fully resolved by this point. */
5752 assert ((int) fixp
->fx_r_type
> 0);
5754 reloc
->addend
= fixp
->fx_offset
;
5756 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5757 if (reloc
->howto
== NULL
)
5759 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5760 _("cannot represent `%s' relocation in object file"),
5761 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5762 free (reloc
->sym_ptr_ptr
);
5767 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5768 as_fatal (_("internal error? cannot generate `%s' relocation"),
5769 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5775 /* Checks for resource conflicts between instructions. */
5777 /* The func unit stuff could be implemented as bit-vectors rather
5778 than the iterative approach here. If it ends up being too
5779 slow, we will switch it. */
5782 new_resource_table (void *data
,
5785 unit_num_copies_func uncf
,
5786 opcode_num_units_func onuf
,
5787 opcode_funcUnit_use_unit_func ouuf
,
5788 opcode_funcUnit_use_stage_func ousf
)
5791 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5793 rt
->cycles
= cycles
;
5794 rt
->allocated_cycles
= cycles
;
5796 rt
->unit_num_copies
= uncf
;
5797 rt
->opcode_num_units
= onuf
;
5798 rt
->opcode_unit_use
= ouuf
;
5799 rt
->opcode_unit_stage
= ousf
;
5801 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5802 for (i
= 0; i
< cycles
; i
++)
5803 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5810 clear_resource_table (resource_table
*rt
)
5813 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5814 for (j
= 0; j
< rt
->num_units
; j
++)
5815 rt
->units
[i
][j
] = 0;
5819 /* We never shrink it, just fake it into thinking so. */
5822 resize_resource_table (resource_table
*rt
, int cycles
)
5826 rt
->cycles
= cycles
;
5827 if (cycles
<= rt
->allocated_cycles
)
5830 old_cycles
= rt
->allocated_cycles
;
5831 rt
->allocated_cycles
= cycles
;
5833 rt
->units
= xrealloc (rt
->units
,
5834 rt
->allocated_cycles
* sizeof (unsigned char *));
5835 for (i
= 0; i
< old_cycles
; i
++)
5836 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5837 rt
->num_units
* sizeof (unsigned char));
5838 for (i
= old_cycles
; i
< cycles
; i
++)
5839 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5844 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5847 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5849 for (i
= 0; i
< uses
; i
++)
5851 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5852 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5853 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5854 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5855 if (copies_in_use
>= copies
)
5863 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5866 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5868 for (i
= 0; i
< uses
; i
++)
5870 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5871 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5872 /* Note that this allows resources to be oversubscribed. That's
5873 essential to the way the optional scheduler works.
5874 resources_available reports when a resource is over-subscribed,
5875 so it's easy to tell. */
5876 rt
->units
[stage
+ cycle
][unit
]++;
5882 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5885 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5887 for (i
= 0; i
< uses
; i
++)
5889 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5890 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5891 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5892 rt
->units
[stage
+ cycle
][unit
]--;
5897 /* Wrapper functions make parameterized resource reservation
5901 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5903 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5909 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5911 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5916 /* Note that this function does not check issue constraints, but
5917 solely whether the hardware is available to execute the given
5918 instructions together. It also doesn't check if the tinsns
5919 write the same state, or access the same tieports. That is
5920 checked by check_t1_t2_reads_and_writes. */
5923 resources_conflict (vliw_insn
*vinsn
)
5926 static resource_table
*rt
= NULL
;
5928 /* This is the most common case by far. Optimize it. */
5929 if (vinsn
->num_slots
== 1)
5934 xtensa_isa isa
= xtensa_default_isa
;
5935 rt
= new_resource_table
5936 (isa
, xtensa_isa_num_pipe_stages (isa
),
5937 xtensa_isa_num_funcUnits (isa
),
5938 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5939 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5940 opcode_funcUnit_use_unit
,
5941 opcode_funcUnit_use_stage
);
5944 clear_resource_table (rt
);
5946 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5948 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5950 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5957 /* finish_vinsn, emit_single_op and helper functions. */
5959 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5960 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5961 static void bundle_single_op (TInsn
*);
5962 static void xg_assemble_vliw_tokens (vliw_insn
*);
5965 /* We have reached the end of a bundle; emit into the frag. */
5968 finish_vinsn (vliw_insn
*vinsn
)
5975 if (find_vinsn_conflicts (vinsn
))
5977 xg_clear_vinsn (vinsn
);
5981 /* First, find a format that works. */
5982 if (vinsn
->format
== XTENSA_UNDEFINED
)
5983 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5985 if (vinsn
->format
== XTENSA_UNDEFINED
)
5987 as_where (&file_name
, &line
);
5988 as_bad_where (file_name
, line
,
5989 _("couldn't find a valid instruction format"));
5990 fprintf (stderr
, _(" ops were: "));
5991 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5992 fprintf (stderr
, _(" %s;"),
5993 xtensa_opcode_name (xtensa_default_isa
,
5994 vinsn
->slots
[i
].opcode
));
5995 fprintf (stderr
, _("\n"));
5996 xg_clear_vinsn (vinsn
);
6000 if (vinsn
->num_slots
6001 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6003 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6004 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6005 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6007 xg_clear_vinsn (vinsn
);
6011 if (resources_conflict (vinsn
))
6013 as_where (&file_name
, &line
);
6014 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6015 fprintf (stderr
, " ops were: ");
6016 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6017 fprintf (stderr
, " %s;",
6018 xtensa_opcode_name (xtensa_default_isa
,
6019 vinsn
->slots
[i
].opcode
));
6020 fprintf (stderr
, "\n");
6021 xg_clear_vinsn (vinsn
);
6025 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6027 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6029 symbolS
*lit_sym
= NULL
;
6031 bfd_boolean e
= FALSE
;
6032 bfd_boolean saved_density
= density_supported
;
6034 /* We don't want to narrow ops inside multi-slot bundles. */
6035 if (vinsn
->num_slots
> 1)
6036 density_supported
= FALSE
;
6038 istack_init (&slotstack
);
6039 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6041 vinsn
->slots
[i
].opcode
=
6042 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6044 vinsn
->slots
[i
].ntok
= 0;
6047 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6053 density_supported
= saved_density
;
6057 xg_clear_vinsn (vinsn
);
6061 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6063 TInsn
*insn
= &slotstack
.insn
[j
];
6064 if (insn
->insn_type
== ITYPE_LITERAL
)
6066 assert (lit_sym
== NULL
);
6067 lit_sym
= xg_assemble_literal (insn
);
6071 assert (insn
->insn_type
== ITYPE_INSN
);
6073 xg_resolve_literals (insn
, lit_sym
);
6074 if (j
!= slotstack
.ninsn
- 1)
6075 emit_single_op (insn
);
6079 if (vinsn
->num_slots
> 1)
6081 if (opcode_fits_format_slot
6082 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6085 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6089 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6090 if (vinsn
->format
== XTENSA_UNDEFINED
)
6091 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6093 vinsn
->slots
[i
].opcode
6094 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6097 vinsn
->slots
[i
].ntok
= 0;
6102 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6103 vinsn
->format
= XTENSA_UNDEFINED
;
6108 /* Now check resource conflicts on the modified bundle. */
6109 if (resources_conflict (vinsn
))
6111 as_where (&file_name
, &line
);
6112 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6113 fprintf (stderr
, " ops were: ");
6114 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6115 fprintf (stderr
, " %s;",
6116 xtensa_opcode_name (xtensa_default_isa
,
6117 vinsn
->slots
[i
].opcode
));
6118 fprintf (stderr
, "\n");
6119 xg_clear_vinsn (vinsn
);
6123 /* First, find a format that works. */
6124 if (vinsn
->format
== XTENSA_UNDEFINED
)
6125 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6127 xg_assemble_vliw_tokens (vinsn
);
6129 xg_clear_vinsn (vinsn
);
6133 /* Given an vliw instruction, what conflicts are there in register
6134 usage and in writes to states and queues?
6136 This function does two things:
6137 1. Reports an error when a vinsn contains illegal combinations
6138 of writes to registers states or queues.
6139 2. Marks individual tinsns as not relaxable if the combination
6140 contains antidependencies.
6142 Job 2 handles things like swap semantics in instructions that need
6143 to be relaxed. For example,
6147 normally would be relaxed to
6152 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6154 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6156 then we can't relax it into
6159 { add a0, a1, a0 ; add a2, a0, a4 ; }
6161 because the value of a0 is trashed before the second add can read it. */
6163 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6166 find_vinsn_conflicts (vliw_insn
*vinsn
)
6170 xtensa_isa isa
= xtensa_default_isa
;
6172 assert (!past_xtensa_end
);
6174 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6176 TInsn
*op1
= &vinsn
->slots
[i
];
6177 if (op1
->is_specific_opcode
)
6178 op1
->keep_wide
= TRUE
;
6180 op1
->keep_wide
= FALSE
;
6183 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6185 TInsn
*op1
= &vinsn
->slots
[i
];
6187 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6190 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6194 TInsn
*op2
= &vinsn
->slots
[j
];
6195 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6196 switch (conflict_type
)
6199 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6200 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6201 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6204 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6205 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6206 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6209 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6210 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6211 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6214 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6215 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6216 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6219 /* Everything is OK. */
6222 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6223 || conflict_type
== 'a');
6230 as_bad (_("multiple branches or jumps in the same bundle"));
6238 /* Check how the state used by t1 and t2 relate.
6241 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6242 case B: no relationship between what is read and written (both could
6243 read the same reg though)
6244 case C: t1 writes a register t2 writes (a register conflict within a
6246 case D: t1 writes a state that t2 also writes
6247 case E: t1 writes a tie queue that t2 also writes
6248 case F: two volatile queue accesses
6252 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6254 xtensa_isa isa
= xtensa_default_isa
;
6255 xtensa_regfile t1_regfile
, t2_regfile
;
6257 int t1_base_reg
, t1_last_reg
;
6258 int t2_base_reg
, t2_last_reg
;
6259 char t1_inout
, t2_inout
;
6261 char conflict
= 'b';
6266 bfd_boolean t1_volatile
= FALSE
;
6267 bfd_boolean t2_volatile
= FALSE
;
6269 /* Check registers. */
6270 for (j
= 0; j
< t2
->ntok
; j
++)
6272 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6275 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6276 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6277 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6279 for (i
= 0; i
< t1
->ntok
; i
++)
6281 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6284 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6286 if (t1_regfile
!= t2_regfile
)
6289 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6290 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6292 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6293 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6295 if (t1_inout
== 'm' || t1_inout
== 'o'
6296 || t2_inout
== 'm' || t2_inout
== 'o')
6303 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6304 t1_last_reg
= (t1_base_reg
6305 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6307 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6309 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6311 if (t1_reg
!= t2_reg
)
6314 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6320 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6326 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6334 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6335 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6336 for (j
= 0; j
< t2_states
; j
++)
6338 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6339 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6340 for (i
= 0; i
< t1_states
; i
++)
6342 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6343 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6347 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6353 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6359 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6364 /* Check tieports. */
6365 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6366 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6367 for (j
= 0; j
< t2_interfaces
; j
++)
6369 xtensa_interface t2_int
6370 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6371 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6373 t2_inout
= xtensa_interface_inout (isa
, j
);
6374 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6377 for (i
= 0; i
< t1_interfaces
; i
++)
6379 xtensa_interface t1_int
6380 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6381 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6383 t1_inout
= xtensa_interface_inout (isa
, i
);
6384 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6387 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6390 if (t1_int
!= t2_int
)
6393 if (t2_inout
== 'i' && t1_inout
== 'o')
6399 if (t1_inout
== 'i' && t2_inout
== 'o')
6405 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6414 static xtensa_format
6415 xg_find_narrowest_format (vliw_insn
*vinsn
)
6417 /* Right now we assume that the ops within the vinsn are properly
6418 ordered for the slots that the programmer wanted them in. In
6419 other words, we don't rearrange the ops in hopes of finding a
6420 better format. The scheduler handles that. */
6422 xtensa_isa isa
= xtensa_default_isa
;
6423 xtensa_format format
;
6424 vliw_insn v_copy
= *vinsn
;
6425 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6427 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6430 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6434 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6436 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6438 v_copy
.slots
[slot
].opcode
=
6439 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6440 v_copy
.slots
[slot
].ntok
= 0;
6443 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6446 else if (v_copy
.num_slots
> 1)
6449 /* Try the widened version. */
6450 if (!v_copy
.slots
[slot
].keep_wide
6451 && !v_copy
.slots
[slot
].is_specific_opcode
6452 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6454 && opcode_fits_format_slot (widened
.opcode
,
6457 v_copy
.slots
[slot
] = widened
;
6462 if (fit
== v_copy
.num_slots
)
6465 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6466 vinsn
->format
= format
;
6472 if (format
== xtensa_isa_num_formats (isa
))
6473 return XTENSA_UNDEFINED
;
6479 /* Return the additional space needed in a frag
6480 for possible relaxations of any ops in a VLIW insn.
6481 Also fill out the relaxations that might be required of
6482 each tinsn in the vinsn. */
6485 relaxation_requirements (vliw_insn
*vinsn
)
6487 int extra_space
= 0;
6490 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6492 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6493 if (!tinsn_has_symbolic_operands (tinsn
))
6495 /* A narrow instruction could be widened later to help
6496 alignment issues. */
6497 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6498 && !tinsn
->is_specific_opcode
6499 && vinsn
->num_slots
== 1)
6501 /* Difference in bytes between narrow and wide insns... */
6503 tinsn
->subtype
= RELAX_NARROW
;
6504 tinsn
->record_fix
= TRUE
;
6509 tinsn
->record_fix
= FALSE
;
6510 /* No extra_space needed. */
6515 if (workaround_b_j_loop_end
6516 && tinsn
->opcode
== xtensa_jx_opcode
6517 && use_transform ())
6519 /* Add 2 of these. */
6520 extra_space
+= 3; /* for the nop size */
6521 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6524 /* Need to assemble it with space for the relocation. */
6525 if (xg_is_relaxable_insn (tinsn
, 0)
6526 && !tinsn
->is_specific_opcode
)
6528 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6529 int max_literal_size
=
6530 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6532 tinsn
->literal_space
= max_literal_size
;
6534 tinsn
->subtype
= RELAX_IMMED
;
6535 tinsn
->record_fix
= FALSE
;
6536 extra_space
+= max_size
;
6540 tinsn
->record_fix
= TRUE
;
6541 /* No extra space needed. */
6550 bundle_single_op (TInsn
*orig_insn
)
6552 xtensa_isa isa
= xtensa_default_isa
;
6557 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6558 assert (v
.format
!= XTENSA_UNDEFINED
);
6559 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6562 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6565 v
.slots
[slot
].opcode
=
6566 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6567 v
.slots
[slot
].ntok
= 0;
6568 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6571 v
.slots
[slot
] = *orig_insn
;
6574 for ( ; slot
< v
.num_slots
; slot
++)
6576 v
.slots
[slot
].opcode
=
6577 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6578 v
.slots
[slot
].ntok
= 0;
6579 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6588 emit_single_op (TInsn
*orig_insn
)
6591 IStack istack
; /* put instructions into here */
6592 symbolS
*lit_sym
= NULL
;
6593 symbolS
*label_sym
= NULL
;
6595 istack_init (&istack
);
6597 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6598 Because the scheduling and bundling characteristics of movi and
6599 l32r or const16 are so different, we can do much better if we relax
6600 it prior to scheduling and bundling, rather than after. */
6601 if ((orig_insn
->opcode
== xtensa_movi_opcode
6602 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6603 && !cur_vinsn
.inside_bundle
6604 && (orig_insn
->tok
[1].X_op
== O_symbol
6605 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6606 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6608 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6611 for (i
= 0; i
< istack
.ninsn
; i
++)
6613 TInsn
*insn
= &istack
.insn
[i
];
6614 switch (insn
->insn_type
)
6617 assert (lit_sym
== NULL
);
6618 lit_sym
= xg_assemble_literal (insn
);
6622 static int relaxed_sym_idx
= 0;
6623 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6624 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6626 assert (label_sym
== NULL
);
6627 label_sym
= symbol_find_or_make (label
);
6634 xg_resolve_literals (insn
, lit_sym
);
6636 xg_resolve_labels (insn
, label_sym
);
6637 bundle_single_op (insn
);
6649 total_frag_text_expansion (fragS
*fragP
)
6652 int total_expansion
= 0;
6654 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6655 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6657 return total_expansion
;
6661 /* Emit a vliw instruction to the current fragment. */
6664 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6666 bfd_boolean finish_frag
= FALSE
;
6667 bfd_boolean is_jump
= FALSE
;
6668 bfd_boolean is_branch
= FALSE
;
6669 xtensa_isa isa
= xtensa_default_isa
;
6675 struct dwarf2_line_info best_loc
;
6677 best_loc
.line
= INT_MAX
;
6679 if (generating_literals
)
6681 static int reported
= 0;
6683 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6684 _("cannot assemble into a literal fragment"));
6691 if (frag_now_fix () != 0
6692 && (! frag_now
->tc_frag_data
.is_insn
6693 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6694 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6695 || (directive_state
[directive_longcalls
]
6696 != frag_now
->tc_frag_data
.use_longcalls
)
6697 || (directive_state
[directive_absolute_literals
]
6698 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6700 frag_wane (frag_now
);
6702 xtensa_set_frag_assembly_state (frag_now
);
6705 if (workaround_a0_b_retw
6706 && vinsn
->num_slots
== 1
6707 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6708 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6709 && use_transform ())
6711 has_a0_b_retw
= TRUE
;
6713 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6714 After the first assembly pass we will check all of them and
6715 add a nop if needed. */
6716 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6717 frag_var (rs_machine_dependent
, 4, 4,
6718 RELAX_ADD_NOP_IF_A0_B_RETW
,
6719 frag_now
->fr_symbol
,
6720 frag_now
->fr_offset
,
6722 xtensa_set_frag_assembly_state (frag_now
);
6723 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6724 frag_var (rs_machine_dependent
, 4, 4,
6725 RELAX_ADD_NOP_IF_A0_B_RETW
,
6726 frag_now
->fr_symbol
,
6727 frag_now
->fr_offset
,
6729 xtensa_set_frag_assembly_state (frag_now
);
6732 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6734 /* See if the instruction implies an aligned section. */
6735 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6736 record_alignment (now_seg
, 2);
6738 /* Also determine the best line number for debug info. */
6739 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6740 ? vinsn
->slots
[i
].loc
: best_loc
;
6743 /* Special cases for instructions that force an alignment... */
6744 /* None of these opcodes are bundle-able. */
6745 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6749 xtensa_set_frag_assembly_state (frag_now
);
6750 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6752 max_fill
= get_text_align_max_fill_size
6753 (get_text_align_power (xtensa_fetch_width
),
6754 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6756 if (use_transform ())
6757 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6758 RELAX_ALIGN_NEXT_OPCODE
,
6759 frag_now
->fr_symbol
,
6760 frag_now
->fr_offset
,
6763 frag_var (rs_machine_dependent
, 0, 0,
6764 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6765 xtensa_set_frag_assembly_state (frag_now
);
6767 xtensa_move_labels (frag_now
, 0, FALSE
);
6770 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6771 && !vinsn
->slots
[0].is_specific_opcode
)
6773 xtensa_mark_literal_pool_location ();
6774 xtensa_move_labels (frag_now
, 0, TRUE
);
6775 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6778 if (vinsn
->num_slots
== 1)
6780 if (workaround_a0_b_retw
&& use_transform ())
6781 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6782 is_register_writer (&vinsn
->slots
[0], "a", 0));
6784 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6785 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6788 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6790 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6792 extra_space
= relaxation_requirements (vinsn
);
6794 /* vinsn_to_insnbuf will produce the error. */
6795 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6797 f
= frag_more (insn_size
+ extra_space
);
6798 xtensa_set_frag_assembly_state (frag_now
);
6799 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6802 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6803 if (vinsn
->format
== XTENSA_UNDEFINED
)
6806 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6808 xtensa_dwarf2_emit_insn (insn_size
+ extra_space
, &best_loc
);
6810 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6812 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6813 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6814 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6815 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6816 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6817 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6818 if (tinsn
->literal_space
!= 0)
6819 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6821 if (tinsn
->subtype
== RELAX_NARROW
)
6822 assert (vinsn
->num_slots
== 1);
6823 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6825 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6828 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6829 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6833 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6834 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6838 frag_variant (rs_machine_dependent
,
6839 extra_space
, extra_space
, RELAX_SLOTS
,
6840 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6841 xtensa_set_frag_assembly_state (frag_now
);
6844 /* Special cases for loops:
6845 close_loop_end should be inserted AFTER short_loop.
6846 Make sure that CLOSE loops are processed BEFORE short_loops
6847 when converting them. */
6849 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6850 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6851 && !vinsn
->slots
[0].is_specific_opcode
)
6853 if (workaround_short_loop
&& use_transform ())
6855 maybe_has_short_loop
= TRUE
;
6856 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6857 frag_var (rs_machine_dependent
, 4, 4,
6858 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6859 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6860 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6861 frag_var (rs_machine_dependent
, 4, 4,
6862 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6863 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6866 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6867 loop at least 12 bytes away from another loop's end. */
6868 if (workaround_close_loop_end
&& use_transform ())
6870 maybe_has_close_loop_end
= TRUE
;
6871 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6872 frag_var (rs_machine_dependent
, 12, 12,
6873 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6874 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6878 if (use_transform ())
6882 assert (finish_frag
);
6883 frag_var (rs_machine_dependent
,
6884 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6886 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6887 xtensa_set_frag_assembly_state (frag_now
);
6889 else if (is_branch
&& do_align_targets ())
6891 assert (finish_frag
);
6892 frag_var (rs_machine_dependent
,
6893 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6894 RELAX_MAYBE_UNREACHABLE
,
6895 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6896 xtensa_set_frag_assembly_state (frag_now
);
6897 frag_var (rs_machine_dependent
,
6899 RELAX_MAYBE_DESIRE_ALIGN
,
6900 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6901 xtensa_set_frag_assembly_state (frag_now
);
6905 /* Now, if the original opcode was a call... */
6906 if (do_align_targets ()
6907 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6909 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6910 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6911 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6912 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6913 xtensa_set_frag_assembly_state (frag_now
);
6916 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6918 frag_wane (frag_now
);
6920 xtensa_set_frag_assembly_state (frag_now
);
6925 /* xtensa_end and helper functions. */
6927 static void xtensa_cleanup_align_frags (void);
6928 static void xtensa_fix_target_frags (void);
6929 static void xtensa_mark_narrow_branches (void);
6930 static void xtensa_mark_zcl_first_insns (void);
6931 static void xtensa_fix_a0_b_retw_frags (void);
6932 static void xtensa_fix_b_j_loop_end_frags (void);
6933 static void xtensa_fix_close_loop_end_frags (void);
6934 static void xtensa_fix_short_loop_frags (void);
6935 static void xtensa_sanity_check (void);
6940 directive_balance ();
6941 xtensa_flush_pending_output ();
6943 past_xtensa_end
= TRUE
;
6945 xtensa_move_literals ();
6947 xtensa_reorder_segments ();
6948 xtensa_cleanup_align_frags ();
6949 xtensa_fix_target_frags ();
6950 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6951 xtensa_fix_a0_b_retw_frags ();
6952 if (workaround_b_j_loop_end
)
6953 xtensa_fix_b_j_loop_end_frags ();
6955 /* "close_loop_end" should be processed BEFORE "short_loop". */
6956 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6957 xtensa_fix_close_loop_end_frags ();
6959 if (workaround_short_loop
&& maybe_has_short_loop
)
6960 xtensa_fix_short_loop_frags ();
6961 xtensa_mark_narrow_branches ();
6962 xtensa_mark_zcl_first_insns ();
6964 xtensa_sanity_check ();
6969 xtensa_cleanup_align_frags (void)
6973 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
6976 /* Walk over all of the fragments in a subsection. */
6977 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6979 if ((fragP
->fr_type
== rs_align
6980 || fragP
->fr_type
== rs_align_code
6981 || (fragP
->fr_type
== rs_machine_dependent
6982 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6983 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6984 && fragP
->fr_fix
== 0)
6986 fragS
*next
= fragP
->fr_next
;
6989 && next
->fr_fix
== 0
6990 && next
->fr_type
== rs_machine_dependent
6991 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6994 next
= next
->fr_next
;
6997 /* If we don't widen branch targets, then they
6998 will be easier to align. */
6999 if (fragP
->tc_frag_data
.is_branch_target
7000 && fragP
->fr_opcode
== fragP
->fr_literal
7001 && fragP
->fr_type
== rs_machine_dependent
7002 && fragP
->fr_subtype
== RELAX_SLOTS
7003 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7005 if (fragP
->fr_type
== rs_machine_dependent
7006 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7007 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7013 /* Re-process all of the fragments looking to convert all of the
7014 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7015 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7016 Otherwise, convert to a .fill 0. */
7019 xtensa_fix_target_frags (void)
7023 /* When this routine is called, all of the subsections are still intact
7024 so we walk over subsections instead of sections. */
7025 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7029 /* Walk over all of the fragments in a subsection. */
7030 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7032 if (fragP
->fr_type
== rs_machine_dependent
7033 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7035 if (next_frag_is_branch_target (fragP
))
7036 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7045 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7048 xtensa_mark_narrow_branches (void)
7052 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7055 /* Walk over all of the fragments in a subsection. */
7056 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7058 if (fragP
->fr_type
== rs_machine_dependent
7059 && fragP
->fr_subtype
== RELAX_SLOTS
7060 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7063 const expressionS
*expr
;
7066 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7067 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7069 expr
= &vinsn
.slots
[0].tok
[1];
7070 symbolP
= expr
->X_add_symbol
;
7072 if (vinsn
.num_slots
== 1
7073 && xtensa_opcode_is_branch (xtensa_default_isa
,
7074 vinsn
.slots
[0].opcode
)
7075 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7076 && is_narrow_branch_guaranteed_in_range (fragP
,
7079 fragP
->fr_subtype
= RELAX_SLOTS
;
7080 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7088 /* A branch is typically widened only when its target is out of
7089 range. However, we would like to widen them to align a subsequent
7090 branch target when possible.
7092 Because the branch relaxation code is so convoluted, the optimal solution
7093 (combining the two cases) is difficult to get right in all circumstances.
7094 We therefore go with an "almost as good" solution, where we only
7095 use for alignment narrow branches that definitely will not expand to a
7096 jump and a branch. These functions find and mark these cases. */
7098 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7099 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7100 We start counting beginning with the frag after the 2-byte branch, so the
7101 maximum offset is (4 - 2) + 63 = 65. */
7102 #define MAX_IMMED6 65
7104 static offsetT
unrelaxed_frag_max_size (fragS
*);
7107 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7109 const expressionS
*expr
= &tinsn
->tok
[1];
7110 symbolS
*symbolP
= expr
->X_add_symbol
;
7111 fragS
*target_frag
= symbol_get_frag (symbolP
);
7112 offsetT max_distance
= expr
->X_add_number
;
7113 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7114 if (is_branch_jmp_to_next (tinsn
, fragP
))
7117 /* The branch doesn't branch over it's own frag,
7118 but over the subsequent ones. */
7119 fragP
= fragP
->fr_next
;
7120 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7122 max_distance
+= unrelaxed_frag_max_size (fragP
);
7123 fragP
= fragP
->fr_next
;
7125 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7132 xtensa_mark_zcl_first_insns (void)
7136 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7139 /* Walk over all of the fragments in a subsection. */
7140 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7142 if (fragP
->fr_type
== rs_machine_dependent
7143 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7144 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7146 /* Find the loop frag. */
7147 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7148 /* Find the first insn frag. */
7149 targ_frag
= next_non_empty_frag (targ_frag
);
7151 /* Of course, sometimes (mostly for toy test cases) a
7152 zero-cost loop instruction is the last in a section. */
7154 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7155 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7163 /* Re-process all of the fragments looking to convert all of the
7164 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7165 conditional branch or a retw/retw.n, convert this frag to one that
7166 will generate a NOP. In any case close it off with a .fill 0. */
7168 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7171 xtensa_fix_a0_b_retw_frags (void)
7175 /* When this routine is called, all of the subsections are still intact
7176 so we walk over subsections instead of sections. */
7177 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7181 /* Walk over all of the fragments in a subsection. */
7182 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7184 if (fragP
->fr_type
== rs_machine_dependent
7185 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7187 if (next_instrs_are_b_retw (fragP
))
7189 if (fragP
->tc_frag_data
.is_no_transform
)
7190 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7192 relax_frag_add_nop (fragP
);
7202 next_instrs_are_b_retw (fragS
*fragP
)
7204 xtensa_opcode opcode
;
7206 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7207 static xtensa_insnbuf insnbuf
= NULL
;
7208 static xtensa_insnbuf slotbuf
= NULL
;
7209 xtensa_isa isa
= xtensa_default_isa
;
7212 bfd_boolean branch_seen
= FALSE
;
7216 insnbuf
= xtensa_insnbuf_alloc (isa
);
7217 slotbuf
= xtensa_insnbuf_alloc (isa
);
7220 if (next_fragP
== NULL
)
7223 /* Check for the conditional branch. */
7224 xtensa_insnbuf_from_chars
7225 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7226 fmt
= xtensa_format_decode (isa
, insnbuf
);
7227 if (fmt
== XTENSA_UNDEFINED
)
7230 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7232 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7233 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7235 branch_seen
= (branch_seen
7236 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7242 offset
+= xtensa_format_length (isa
, fmt
);
7243 if (offset
== next_fragP
->fr_fix
)
7245 next_fragP
= next_non_empty_frag (next_fragP
);
7249 if (next_fragP
== NULL
)
7252 /* Check for the retw/retw.n. */
7253 xtensa_insnbuf_from_chars
7254 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7255 fmt
= xtensa_format_decode (isa
, insnbuf
);
7257 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7258 have no problems. */
7259 if (fmt
== XTENSA_UNDEFINED
7260 || xtensa_format_num_slots (isa
, fmt
) != 1)
7263 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7264 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7266 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7273 /* Re-process all of the fragments looking to convert all of the
7274 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7275 loop end label, convert this frag to one that will generate a NOP.
7276 In any case close it off with a .fill 0. */
7278 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7281 xtensa_fix_b_j_loop_end_frags (void)
7285 /* When this routine is called, all of the subsections are still intact
7286 so we walk over subsections instead of sections. */
7287 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7291 /* Walk over all of the fragments in a subsection. */
7292 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7294 if (fragP
->fr_type
== rs_machine_dependent
7295 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7297 if (next_instr_is_loop_end (fragP
))
7299 if (fragP
->tc_frag_data
.is_no_transform
)
7300 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7302 relax_frag_add_nop (fragP
);
7312 next_instr_is_loop_end (fragS
*fragP
)
7314 const fragS
*next_fragP
;
7316 if (next_frag_is_loop_target (fragP
))
7319 next_fragP
= next_non_empty_frag (fragP
);
7320 if (next_fragP
== NULL
)
7323 if (!next_frag_is_loop_target (next_fragP
))
7326 /* If the size is >= 3 then there is more than one instruction here.
7327 The hardware bug will not fire. */
7328 if (next_fragP
->fr_fix
> 3)
7335 /* Re-process all of the fragments looking to convert all of the
7336 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7337 not MY loop's loop end within 12 bytes, add enough nops here to
7338 make it at least 12 bytes away. In any case close it off with a
7341 static offsetT min_bytes_to_other_loop_end
7342 (fragS
*, fragS
*, offsetT
, offsetT
);
7345 xtensa_fix_close_loop_end_frags (void)
7349 /* When this routine is called, all of the subsections are still intact
7350 so we walk over subsections instead of sections. */
7351 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7355 fragS
*current_target
= NULL
;
7356 offsetT current_offset
= 0;
7358 /* Walk over all of the fragments in a subsection. */
7359 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7361 if (fragP
->fr_type
== rs_machine_dependent
7362 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7363 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7364 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7367 /* Read it. If the instruction is a loop, get the target. */
7369 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7370 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7371 t_insn
.opcode
) == 1)
7373 /* Get the current fragment target. */
7374 if (fragP
->tc_frag_data
.slot_symbols
[0])
7376 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7377 current_target
= symbol_get_frag (sym
);
7378 current_offset
= fragP
->fr_offset
;
7384 && fragP
->fr_type
== rs_machine_dependent
7385 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7388 int bytes_added
= 0;
7390 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7391 /* Max out at 12. */
7392 min_bytes
= min_bytes_to_other_loop_end
7393 (fragP
->fr_next
, current_target
, current_offset
,
7394 REQUIRED_LOOP_DIVIDING_BYTES
);
7396 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7398 if (fragP
->tc_frag_data
.is_no_transform
)
7399 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7402 while (min_bytes
+ bytes_added
7403 < REQUIRED_LOOP_DIVIDING_BYTES
)
7407 if (fragP
->fr_var
< length
)
7408 as_fatal (_("fr_var %lu < length %d"),
7409 (long) fragP
->fr_var
, length
);
7412 assemble_nop (length
,
7413 fragP
->fr_literal
+ fragP
->fr_fix
);
7414 fragP
->fr_fix
+= length
;
7415 fragP
->fr_var
-= length
;
7417 bytes_added
+= length
;
7423 assert (fragP
->fr_type
!= rs_machine_dependent
7424 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7430 static offsetT
unrelaxed_frag_min_size (fragS
*);
7433 min_bytes_to_other_loop_end (fragS
*fragP
,
7434 fragS
*current_target
,
7435 offsetT current_offset
,
7439 fragS
*current_fragP
;
7441 for (current_fragP
= fragP
;
7443 current_fragP
= current_fragP
->fr_next
)
7445 if (current_fragP
->tc_frag_data
.is_loop_target
7446 && current_fragP
!= current_target
)
7447 return offset
+ current_offset
;
7449 offset
+= unrelaxed_frag_min_size (current_fragP
);
7451 if (offset
+ current_offset
>= max_size
)
7459 unrelaxed_frag_min_size (fragS
*fragP
)
7461 offsetT size
= fragP
->fr_fix
;
7463 /* Add fill size. */
7464 if (fragP
->fr_type
== rs_fill
)
7465 size
+= fragP
->fr_offset
;
7472 unrelaxed_frag_max_size (fragS
*fragP
)
7474 offsetT size
= fragP
->fr_fix
;
7475 switch (fragP
->fr_type
)
7478 /* Empty frags created by the obstack allocation scheme
7479 end up with type 0. */
7484 size
+= fragP
->fr_offset
;
7492 /* No further adjustments needed. */
7494 case rs_machine_dependent
:
7495 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7496 size
+= fragP
->fr_var
;
7499 /* We had darn well better know how big it is. */
7508 /* Re-process all of the fragments looking to convert all
7509 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7512 1) the instruction size count to the loop end label
7513 is too short (<= 2 instructions),
7514 2) loop has a jump or branch in it
7517 1) workaround_all_short_loops is TRUE
7518 2) The generating loop was a 'loopgtz' or 'loopnez'
7519 3) the instruction size count to the loop end label is too short
7521 then convert this frag (and maybe the next one) to generate a NOP.
7522 In any case close it off with a .fill 0. */
7524 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7525 static bfd_boolean
branch_before_loop_end (fragS
*);
7528 xtensa_fix_short_loop_frags (void)
7532 /* When this routine is called, all of the subsections are still intact
7533 so we walk over subsections instead of sections. */
7534 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7537 fragS
*current_target
= NULL
;
7538 offsetT current_offset
= 0;
7539 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7541 /* Walk over all of the fragments in a subsection. */
7542 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7544 /* Check on the current loop. */
7545 if (fragP
->fr_type
== rs_machine_dependent
7546 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7547 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7548 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7553 /* Read it. If the instruction is a loop, get the target. */
7554 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7555 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7556 t_insn
.opcode
) == 1)
7558 /* Get the current fragment target. */
7559 if (fragP
->tc_frag_data
.slot_symbols
[0])
7561 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7562 current_target
= symbol_get_frag (sym
);
7563 current_offset
= fragP
->fr_offset
;
7564 current_opcode
= t_insn
.opcode
;
7569 if (fragP
->fr_type
== rs_machine_dependent
7570 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7572 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7573 && (branch_before_loop_end (fragP
->fr_next
)
7574 || (workaround_all_short_loops
7575 && current_opcode
!= XTENSA_UNDEFINED
7576 && current_opcode
!= xtensa_loop_opcode
)))
7578 if (fragP
->tc_frag_data
.is_no_transform
)
7579 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7581 relax_frag_add_nop (fragP
);
7590 static int unrelaxed_frag_min_insn_count (fragS
*);
7593 count_insns_to_loop_end (fragS
*base_fragP
,
7594 bfd_boolean count_relax_add
,
7597 fragS
*fragP
= NULL
;
7602 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7604 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7605 if (insn_count
>= max_count
)
7608 if (count_relax_add
)
7610 if (fragP
->fr_type
== rs_machine_dependent
7611 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7613 /* In order to add the appropriate number of
7614 NOPs, we count an instruction for downstream
7617 if (insn_count
>= max_count
)
7627 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7629 xtensa_isa isa
= xtensa_default_isa
;
7630 static xtensa_insnbuf insnbuf
= NULL
;
7634 if (!fragP
->tc_frag_data
.is_insn
)
7638 insnbuf
= xtensa_insnbuf_alloc (isa
);
7640 /* Decode the fixed instructions. */
7641 while (offset
< fragP
->fr_fix
)
7645 xtensa_insnbuf_from_chars
7646 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7647 fmt
= xtensa_format_decode (isa
, insnbuf
);
7649 if (fmt
== XTENSA_UNDEFINED
)
7651 as_fatal (_("undecodable instruction in instruction frag"));
7654 offset
+= xtensa_format_length (isa
, fmt
);
7662 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7665 branch_before_loop_end (fragS
*base_fragP
)
7669 for (fragP
= base_fragP
;
7670 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7671 fragP
= fragP
->fr_next
)
7673 if (unrelaxed_frag_has_b_j (fragP
))
7681 unrelaxed_frag_has_b_j (fragS
*fragP
)
7683 static xtensa_insnbuf insnbuf
= NULL
;
7684 xtensa_isa isa
= xtensa_default_isa
;
7687 if (!fragP
->tc_frag_data
.is_insn
)
7691 insnbuf
= xtensa_insnbuf_alloc (isa
);
7693 /* Decode the fixed instructions. */
7694 while (offset
< fragP
->fr_fix
)
7699 xtensa_insnbuf_from_chars
7700 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7701 fmt
= xtensa_format_decode (isa
, insnbuf
);
7702 if (fmt
== XTENSA_UNDEFINED
)
7705 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7707 xtensa_opcode opcode
=
7708 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7709 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7710 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7713 offset
+= xtensa_format_length (isa
, fmt
);
7719 /* Checks to be made after initial assembly but before relaxation. */
7721 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7722 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7725 xtensa_sanity_check (void)
7732 as_where (&file_name
, &line
);
7733 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7737 /* Walk over all of the fragments in a subsection. */
7738 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7740 /* Currently we only check for empty loops here. */
7741 if (fragP
->fr_type
== rs_machine_dependent
7742 && fragP
->fr_subtype
== RELAX_IMMED
)
7744 static xtensa_insnbuf insnbuf
= NULL
;
7747 if (fragP
->fr_opcode
!= NULL
)
7750 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7751 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7752 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7754 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7755 t_insn
.opcode
) == 1)
7757 if (is_empty_loop (&t_insn
, fragP
))
7759 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7760 as_bad (_("invalid empty loop"));
7762 if (!is_local_forward_loop (&t_insn
, fragP
))
7764 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7765 as_bad (_("loop target does not follow "
7766 "loop instruction in section"));
7773 new_logical_line (file_name
, line
);
7777 #define LOOP_IMMED_OPN 1
7779 /* Return TRUE if the loop target is the next non-zero fragment. */
7782 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7784 const expressionS
*expr
;
7788 if (insn
->insn_type
!= ITYPE_INSN
)
7791 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7794 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7797 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7799 if (expr
->X_op
!= O_symbol
)
7802 symbolP
= expr
->X_add_symbol
;
7806 if (symbol_get_frag (symbolP
) == NULL
)
7809 if (S_GET_VALUE (symbolP
) != 0)
7812 /* Walk through the zero-size fragments from this one. If we find
7813 the target fragment, then this is a zero-size loop. */
7815 for (next_fragP
= fragP
->fr_next
;
7817 next_fragP
= next_fragP
->fr_next
)
7819 if (next_fragP
== symbol_get_frag (symbolP
))
7821 if (next_fragP
->fr_fix
!= 0)
7829 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7831 const expressionS
*expr
;
7835 if (insn
->insn_type
!= ITYPE_INSN
)
7838 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7841 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7844 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7846 if (expr
->X_op
!= O_symbol
)
7849 symbolP
= expr
->X_add_symbol
;
7853 if (symbol_get_frag (symbolP
) == NULL
)
7856 /* Walk through fragments until we find the target.
7857 If we do not find the target, then this is an invalid loop. */
7859 for (next_fragP
= fragP
->fr_next
;
7861 next_fragP
= next_fragP
->fr_next
)
7863 if (next_fragP
== symbol_get_frag (symbolP
))
7871 /* Alignment Functions. */
7874 get_text_align_power (unsigned target_size
)
7879 assert (target_size
<= INT_MAX
);
7880 while (target_size
> power
)
7890 get_text_align_max_fill_size (int align_pow
,
7891 bfd_boolean use_nops
,
7892 bfd_boolean use_no_density
)
7895 return (1 << align_pow
);
7897 return 3 * (1 << align_pow
);
7899 return 1 + (1 << align_pow
);
7903 /* Calculate the minimum bytes of fill needed at "address" to align a
7904 target instruction of size "target_size" so that it does not cross a
7905 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7906 the fill can be an arbitrary number of bytes. Otherwise, the space must
7907 be filled by NOP instructions. */
7910 get_text_align_fill_size (addressT address
,
7913 bfd_boolean use_nops
,
7914 bfd_boolean use_no_density
)
7916 addressT alignment
, fill
, fill_limit
, fill_step
;
7917 bfd_boolean skip_one
= FALSE
;
7919 alignment
= (1 << align_pow
);
7920 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7924 fill_limit
= alignment
;
7927 else if (!use_no_density
)
7929 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7930 fill_limit
= alignment
* 2;
7936 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7937 fill_limit
= alignment
* 3;
7941 /* Try all fill sizes until finding one that works. */
7942 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7944 if (skip_one
&& fill
== 1)
7946 if ((address
+ fill
) >> align_pow
7947 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7956 branch_align_power (segT sec
)
7958 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7959 is aligned to at least an 8-byte boundary, then a branch target need
7960 only fit within an 8-byte aligned block of memory to avoid a stall.
7961 Otherwise, try to fit branch targets within 4-byte aligned blocks
7962 (which may be insufficient, e.g., if the section has no alignment, but
7963 it's good enough). */
7964 if (xtensa_fetch_width
== 8)
7966 if (get_recorded_alignment (sec
) >= 3)
7970 assert (xtensa_fetch_width
== 4);
7976 /* This will assert if it is not possible. */
7979 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7985 assert (fill_size
% 3 == 0);
7986 return (fill_size
/ 3);
7989 assert (fill_size
!= 1); /* Bad argument. */
7991 while (fill_size
> 1)
7994 if (fill_size
== 2 || fill_size
== 4)
7996 fill_size
-= insn_size
;
7999 assert (fill_size
!= 1); /* Bad algorithm. */
8005 get_text_align_nth_nop_size (offsetT fill_size
,
8007 bfd_boolean use_no_density
)
8014 assert (fill_size
!= 1); /* Bad argument. */
8016 while (fill_size
> 1)
8019 if (fill_size
== 2 || fill_size
== 4)
8021 fill_size
-= insn_size
;
8031 /* For the given fragment, find the appropriate address
8032 for it to begin at if we are using NOPs to align it. */
8035 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8037 /* The rule is: get next fragment's FIRST instruction. Find
8038 the smallest number of bytes that need to be added to
8039 ensure that the next fragment's FIRST instruction will fit
8042 E.G., 2 bytes : 0, 1, 2 mod 4
8045 If the FIRST instruction MIGHT be relaxed,
8046 assume that it will become a 3-byte instruction.
8048 Note again here that LOOP instructions are not bundleable,
8049 and this relaxation only applies to LOOP opcodes. */
8052 int first_insn_size
;
8054 addressT pre_opcode_bytes
;
8057 xtensa_opcode opcode
;
8058 bfd_boolean is_loop
;
8060 assert (fragP
->fr_type
== rs_machine_dependent
);
8061 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8063 /* Find the loop frag. */
8064 first_insn
= next_non_empty_frag (fragP
);
8065 /* Now find the first insn frag. */
8066 first_insn
= next_non_empty_frag (first_insn
);
8068 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8070 loop_insn_size
= xg_get_single_size (opcode
);
8072 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8073 pre_opcode_bytes
+= loop_insn_size
;
8075 /* For loops, the alignment depends on the size of the
8076 instruction following the loop, not the LOOP instruction. */
8078 if (first_insn
== NULL
)
8081 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8083 first_insn_size
= frag_format_size (first_insn
);
8085 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8086 first_insn_size
= 3; /* ISA specifies this */
8088 /* If it was 8, then we'll need a larger alignment for the section. */
8089 align_power
= get_text_align_power (first_insn_size
);
8090 record_alignment (now_seg
, align_power
);
8092 fill_size
= get_text_align_fill_size
8093 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8094 fragP
->tc_frag_data
.is_no_density
);
8096 return address
+ fill_size
;
8100 /* 3 mechanisms for relaxing an alignment:
8102 Align to a power of 2.
8103 Align so the next fragment's instruction does not cross a word boundary.
8104 Align the current instruction so that if the next instruction
8105 were 3 bytes, it would not cross a word boundary.
8109 zeros - This is easy; always insert zeros.
8110 nops - 3-byte and 2-byte instructions
8114 >=5 : 3-byte instruction + fn (n-3)
8115 widening - widen previous instructions. */
8118 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8120 addressT target_address
, loop_insn_offset
;
8122 xtensa_opcode loop_opcode
;
8123 bfd_boolean is_loop
;
8126 offsetT branch_align
;
8128 assert (fragP
->fr_type
== rs_machine_dependent
);
8129 switch (fragP
->fr_subtype
)
8131 case RELAX_DESIRE_ALIGN
:
8132 target_size
= next_frag_format_size (fragP
);
8133 if (target_size
== XTENSA_UNDEFINED
)
8135 align_power
= branch_align_power (now_seg
);
8136 branch_align
= 1 << align_power
;
8137 /* Don't count on the section alignment being as large as the target. */
8138 if (target_size
> branch_align
)
8139 target_size
= branch_align
;
8140 opt_diff
= get_text_align_fill_size (address
, align_power
,
8141 target_size
, FALSE
, FALSE
);
8143 *max_diff
= (opt_diff
+ branch_align
8144 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8145 assert (*max_diff
>= opt_diff
);
8148 case RELAX_ALIGN_NEXT_OPCODE
:
8149 target_size
= next_frag_format_size (fragP
);
8150 loop_insn_offset
= 0;
8151 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8154 /* If the loop has been expanded then the LOOP instruction
8155 could be at an offset from this fragment. */
8156 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8158 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8160 if (target_size
== 2)
8161 target_size
= 3; /* ISA specifies this */
8163 /* In an ideal world, which is what we are shooting for here,
8164 we wouldn't need to use any NOPs immediately prior to the
8165 LOOP instruction. If this approach fails, relax_frag_loop_align
8166 will call get_noop_aligned_address. */
8168 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8169 align_power
= get_text_align_power (target_size
),
8170 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8171 target_size
, FALSE
, FALSE
);
8173 *max_diff
= xtensa_fetch_width
8174 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8175 - target_size
+ opt_diff
;
8176 assert (*max_diff
>= opt_diff
);
8187 /* md_relax_frag Hook and Helper Functions. */
8189 static long relax_frag_loop_align (fragS
*, long);
8190 static long relax_frag_for_align (fragS
*, long);
8191 static long relax_frag_immed
8192 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8195 /* Return the number of bytes added to this fragment, given that the
8196 input has been stretched already by "stretch". */
8199 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8201 xtensa_isa isa
= xtensa_default_isa
;
8202 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8203 long new_stretch
= 0;
8207 static xtensa_insnbuf vbuf
= NULL
;
8208 int slot
, num_slots
;
8211 as_where (&file_name
, &line
);
8212 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8214 fragP
->tc_frag_data
.unreported_expansion
= 0;
8216 switch (fragP
->fr_subtype
)
8218 case RELAX_ALIGN_NEXT_OPCODE
:
8219 /* Always convert. */
8220 if (fragP
->tc_frag_data
.relax_seen
)
8221 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8224 case RELAX_LOOP_END
:
8228 case RELAX_LOOP_END_ADD_NOP
:
8229 /* Add a NOP and switch to .fill 0. */
8230 new_stretch
= relax_frag_add_nop (fragP
);
8234 case RELAX_DESIRE_ALIGN
:
8235 /* Do nothing. The narrowing before this frag will either align
8240 case RELAX_LITERAL_FINAL
:
8243 case RELAX_LITERAL_NR
:
8245 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8246 assert (unreported
== lit_size
);
8247 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8248 fragP
->fr_var
-= lit_size
;
8249 fragP
->fr_fix
+= lit_size
;
8255 vbuf
= xtensa_insnbuf_alloc (isa
);
8257 xtensa_insnbuf_from_chars
8258 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8259 fmt
= xtensa_format_decode (isa
, vbuf
);
8260 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8262 for (slot
= 0; slot
< num_slots
; slot
++)
8264 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8267 if (fragP
->tc_frag_data
.relax_seen
)
8268 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8272 case RELAX_IMMED_STEP1
:
8273 case RELAX_IMMED_STEP2
:
8274 /* Place the immediate. */
8275 new_stretch
+= relax_frag_immed
8276 (now_seg
, fragP
, stretch
,
8277 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8278 fmt
, slot
, stretched_p
, FALSE
);
8282 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8288 case RELAX_LITERAL_POOL_BEGIN
:
8289 case RELAX_LITERAL_POOL_END
:
8290 case RELAX_MAYBE_UNREACHABLE
:
8291 case RELAX_MAYBE_DESIRE_ALIGN
:
8292 /* No relaxation required. */
8295 case RELAX_FILL_NOP
:
8296 case RELAX_UNREACHABLE
:
8297 if (fragP
->tc_frag_data
.relax_seen
)
8298 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8302 as_bad (_("bad relaxation state"));
8305 /* Tell gas we need another relaxation pass. */
8306 if (! fragP
->tc_frag_data
.relax_seen
)
8308 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8312 new_logical_line (file_name
, line
);
8318 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8320 addressT old_address
, old_next_address
, old_size
;
8321 addressT new_address
, new_next_address
, new_size
;
8324 /* All the frags with relax_frag_for_alignment prior to this one in the
8325 section have been done, hopefully eliminating the need for a NOP here.
8326 But, this will put it in if necessary. */
8328 /* Calculate the old address of this fragment and the next fragment. */
8329 old_address
= fragP
->fr_address
- stretch
;
8330 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8331 fragP
->tc_frag_data
.text_expansion
[0]);
8332 old_size
= old_next_address
- old_address
;
8334 /* Calculate the new address of this fragment and the next fragment. */
8335 new_address
= fragP
->fr_address
;
8337 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8338 new_size
= new_next_address
- new_address
;
8340 growth
= new_size
- old_size
;
8342 /* Fix up the text_expansion field and return the new growth. */
8343 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8348 /* Add a NOP instruction. */
8351 relax_frag_add_nop (fragS
*fragP
)
8353 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8354 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8355 assemble_nop (length
, nop_buf
);
8356 fragP
->tc_frag_data
.is_insn
= TRUE
;
8358 if (fragP
->fr_var
< length
)
8360 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8364 fragP
->fr_fix
+= length
;
8365 fragP
->fr_var
-= length
;
8370 static long future_alignment_required (fragS
*, long);
8373 relax_frag_for_align (fragS
*fragP
, long stretch
)
8375 /* Overview of the relaxation procedure for alignment:
8376 We can widen with NOPs or by widening instructions or by filling
8377 bytes after jump instructions. Find the opportune places and widen
8378 them if necessary. */
8383 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8384 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8385 || (fragP
->fr_subtype
== RELAX_SLOTS
8386 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8388 stretch_me
= future_alignment_required (fragP
, stretch
);
8389 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8395 /* We expanded on a previous pass. Can we shrink now? */
8396 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8397 if (shrink
<= stretch
&& stretch
> 0)
8399 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8405 /* Below here, diff > 0. */
8406 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8412 /* Return the address of the next frag that should be aligned.
8414 By "address" we mean the address it _would_ be at if there
8415 is no action taken to align it between here and the target frag.
8416 In other words, if no narrows and no fill nops are used between
8417 here and the frag to align, _even_if_ some of the frags we use
8418 to align targets have already expanded on a previous relaxation
8421 Also, count each frag that may be used to help align the target.
8423 Return 0 if there are no frags left in the chain that need to be
8427 find_address_of_next_align_frag (fragS
**fragPP
,
8431 bfd_boolean
*paddable
)
8433 fragS
*fragP
= *fragPP
;
8434 addressT address
= fragP
->fr_address
;
8436 /* Do not reset the counts to 0. */
8440 /* Limit this to a small search. */
8446 address
+= fragP
->fr_fix
;
8448 if (fragP
->fr_type
== rs_fill
)
8449 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8450 else if (fragP
->fr_type
== rs_machine_dependent
)
8452 switch (fragP
->fr_subtype
)
8454 case RELAX_UNREACHABLE
:
8458 case RELAX_FILL_NOP
:
8460 if (!fragP
->tc_frag_data
.is_no_density
)
8465 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8470 address
+= total_frag_text_expansion (fragP
);;
8474 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8477 case RELAX_ALIGN_NEXT_OPCODE
:
8478 case RELAX_DESIRE_ALIGN
:
8482 case RELAX_MAYBE_UNREACHABLE
:
8483 case RELAX_MAYBE_DESIRE_ALIGN
:
8488 /* Just punt if we don't know the type. */
8495 /* Just punt if we don't know the type. */
8499 fragP
= fragP
->fr_next
;
8507 static long bytes_to_stretch (fragS
*, int, int, int, int);
8510 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8512 fragS
*this_frag
= fragP
;
8516 int narrow_nops
= 0;
8517 bfd_boolean paddable
= FALSE
;
8518 offsetT local_opt_diff
;
8521 int stretch_amount
= 0;
8522 int local_stretch_amount
;
8523 int global_stretch_amount
;
8525 address
= find_address_of_next_align_frag
8526 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8530 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8531 opt_diff
= local_opt_diff
;
8532 assert (opt_diff
>= 0);
8533 assert (max_diff
>= opt_diff
);
8538 fragP
= fragP
->fr_next
;
8540 while (fragP
&& opt_diff
< max_diff
&& address
)
8542 /* We only use these to determine if we can exit early
8543 because there will be plenty of ways to align future
8545 int glob_widens
= 0;
8548 bfd_boolean glob_pad
= 0;
8549 address
= find_address_of_next_align_frag
8550 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8551 /* If there is a padable portion, then skip. */
8552 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8557 offsetT next_m_diff
;
8558 offsetT next_o_diff
;
8560 /* Downrange frags haven't had stretch added to them yet. */
8563 /* The address also includes any text expansion from this
8564 frag in a previous pass, but we don't want that. */
8565 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8567 /* Assume we are going to move at least opt_diff. In
8568 reality, we might not be able to, but assuming that
8569 we will helps catch cases where moving opt_diff pushes
8570 the next target from aligned to unaligned. */
8571 address
+= opt_diff
;
8573 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8575 /* Now cleanup for the adjustments to address. */
8576 next_o_diff
+= opt_diff
;
8577 next_m_diff
+= opt_diff
;
8578 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8579 opt_diff
= next_o_diff
;
8580 if (next_m_diff
< max_diff
)
8581 max_diff
= next_m_diff
;
8582 fragP
= fragP
->fr_next
;
8586 /* If there are enough wideners in between, do it. */
8589 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8591 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8596 local_stretch_amount
8597 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8598 num_widens
, local_opt_diff
);
8599 global_stretch_amount
8600 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8601 num_widens
, opt_diff
);
8602 /* If the condition below is true, then the frag couldn't
8603 stretch the correct amount for the global case, so we just
8604 optimize locally. We'll rely on the subsequent frags to get
8605 the correct alignment in the global case. */
8606 if (global_stretch_amount
< local_stretch_amount
)
8607 stretch_amount
= local_stretch_amount
;
8609 stretch_amount
= global_stretch_amount
;
8611 if (this_frag
->fr_subtype
== RELAX_SLOTS
8612 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8613 assert (stretch_amount
<= 1);
8614 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8616 if (this_frag
->tc_frag_data
.is_no_density
)
8617 assert (stretch_amount
== 3 || stretch_amount
== 0);
8619 assert (stretch_amount
<= 3);
8622 return stretch_amount
;
8626 /* The idea: widen everything you can to get a target or loop aligned,
8627 then start using NOPs.
8629 When we must have a NOP, here is a table of how we decide
8630 (so you don't have to fight through the control flow below):
8632 wide_nops = the number of wide NOPs available for aligning
8633 narrow_nops = the number of narrow NOPs available for aligning
8634 (a subset of wide_nops)
8635 widens = the number of narrow instructions that should be widened
8642 b 0 1 1 (case 3a makes this case unnecessary)
8645 c 0 1 2 (case 4a makes this case unnecessary)
8648 c 0 2 1 (case 5b makes this case unnecessary)
8651 c 0 1 4 (case 6b makes this case unneccesary)
8652 d 1 1 1 (case 6a makes this case unnecessary)
8653 e 0 2 2 (case 6a makes this case unnecessary)
8654 f 0 3 0 (case 6a makes this case unnecessary)
8657 c 1 1 2 (case 7b makes this case unnecessary)
8658 d 0 1 5 (case 7a makes this case unnecessary)
8659 e 0 2 3 (case 7b makes this case unnecessary)
8660 f 0 3 1 (case 7b makes this case unnecessary)
8661 g 1 2 1 (case 7b makes this case unnecessary)
8665 bytes_to_stretch (fragS
*this_frag
,
8671 int bytes_short
= desired_diff
- num_widens
;
8673 assert (desired_diff
>= 0 && desired_diff
< 8);
8674 if (desired_diff
== 0)
8677 assert (wide_nops
> 0 || num_widens
> 0);
8679 /* Always prefer widening to NOP-filling. */
8680 if (bytes_short
< 0)
8682 /* There are enough RELAX_NARROW frags after this one
8683 to align the target without widening this frag in any way. */
8687 if (bytes_short
== 0)
8689 /* Widen every narrow between here and the align target
8690 and the align target will be properly aligned. */
8691 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8697 /* From here we will need at least one NOP to get an alignment.
8698 However, we may not be able to align at all, in which case,
8700 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8702 switch (desired_diff
)
8707 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8708 return 2; /* case 2 */
8714 return 3; /* case 3a */
8716 if (num_widens
>= 1 && wide_nops
== 1)
8717 return 3; /* case 4a */
8718 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8719 return 2; /* case 4b */
8722 if (num_widens
>= 2 && wide_nops
== 1)
8723 return 3; /* case 5a */
8724 /* We will need two nops. Are there enough nops
8725 between here and the align target? */
8726 if (wide_nops
< 2 || narrow_nops
== 0)
8728 /* Are there other nops closer that can serve instead? */
8729 if (wide_nops
> 2 && narrow_nops
> 1)
8731 /* Take the density one first, because there might not be
8732 another density one available. */
8733 if (!this_frag
->tc_frag_data
.is_no_density
)
8734 return 2; /* case 5b narrow */
8736 return 3; /* case 5b wide */
8740 return 3; /* case 6a */
8741 else if (num_widens
>= 3 && wide_nops
== 1)
8742 return 3; /* case 6b */
8745 if (wide_nops
== 1 && num_widens
>= 4)
8746 return 3; /* case 7a */
8747 else if (wide_nops
== 2 && num_widens
>= 1)
8748 return 3; /* case 7b */
8756 /* We will need a NOP no matter what, but should we widen
8757 this instruction to help?
8759 This is a RELAX_FRAG_NARROW frag. */
8760 switch (desired_diff
)
8769 if (wide_nops
>= 1 && num_widens
== 1)
8770 return 1; /* case 4a */
8773 if (wide_nops
>= 1 && num_widens
== 2)
8774 return 1; /* case 5a */
8778 return 0; /* case 6a */
8779 else if (wide_nops
>= 1 && num_widens
== 3)
8780 return 1; /* case 6b */
8783 if (wide_nops
>= 1 && num_widens
== 4)
8784 return 1; /* case 7a */
8785 else if (wide_nops
>= 2 && num_widens
== 1)
8786 return 1; /* case 7b */
8799 relax_frag_immed (segT segP
,
8806 bfd_boolean estimate_only
)
8809 vliw_insn orig_vinsn
;
8811 bfd_boolean negatable_branch
= FALSE
;
8812 bfd_boolean branch_jmp_to_next
= FALSE
;
8813 bfd_boolean wide_insn
= FALSE
;
8814 xtensa_isa isa
= xtensa_default_isa
;
8816 offsetT frag_offset
;
8819 int num_text_bytes
, num_literal_bytes
;
8820 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8822 assert (fragP
->fr_opcode
!= NULL
);
8824 xg_init_vinsn (&orig_vinsn
);
8825 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
8826 if (xtensa_format_num_slots (isa
, fmt
) > 1)
8829 tinsn
= orig_vinsn
.slots
[slot
];
8830 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8832 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8835 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8836 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8838 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8840 old_size
= xtensa_format_length (isa
, fmt
);
8842 /* Special case: replace a branch to the next instruction with a NOP.
8843 This is required to work around a hardware bug in T1040.0 and also
8844 serves as an optimization. */
8846 if (branch_jmp_to_next
8847 && ((old_size
== 2) || (old_size
== 3))
8848 && !next_frag_is_loop_target (fragP
))
8851 /* Here is the fun stuff: Get the immediate field from this
8852 instruction. If it fits, we are done. If not, find the next
8853 instruction sequence that fits. */
8855 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8856 istack_init (&istack
);
8857 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8858 min_steps
, stretch
);
8859 if (num_steps
< min_steps
)
8861 as_fatal (_("internal error: relaxation failed"));
8865 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8867 as_fatal (_("internal error: relaxation requires too many steps"));
8871 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8873 /* Figure out the number of bytes needed. */
8875 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8877 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8879 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8881 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8884 num_text_bytes
+= old_size
;
8885 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8886 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8888 total_text_diff
= num_text_bytes
- old_size
;
8889 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8891 /* It MUST get larger. If not, we could get an infinite loop. */
8892 assert (num_text_bytes
>= 0);
8893 assert (literal_diff
>= 0);
8894 assert (total_text_diff
>= 0);
8896 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8897 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8898 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8899 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8901 /* Find the associated expandable literal for this. */
8902 if (literal_diff
!= 0)
8904 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8907 assert (literal_diff
== 4);
8908 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8910 /* We expect that the literal section state has NOT been
8912 assert (lit_fragP
->fr_type
== rs_machine_dependent
8913 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8914 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8916 /* We need to mark this section for another iteration
8922 if (negatable_branch
&& istack
.ninsn
> 1)
8923 update_next_frag_state (fragP
);
8925 return this_text_diff
;
8929 /* md_convert_frag Hook and Helper Functions. */
8931 static void convert_frag_align_next_opcode (fragS
*);
8932 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8933 static void convert_frag_fill_nop (fragS
*);
8934 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8937 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8939 static xtensa_insnbuf vbuf
= NULL
;
8940 xtensa_isa isa
= xtensa_default_isa
;
8947 as_where (&file_name
, &line
);
8948 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8950 switch (fragp
->fr_subtype
)
8952 case RELAX_ALIGN_NEXT_OPCODE
:
8953 /* Always convert. */
8954 convert_frag_align_next_opcode (fragp
);
8957 case RELAX_DESIRE_ALIGN
:
8958 /* Do nothing. If not aligned already, too bad. */
8962 case RELAX_LITERAL_FINAL
:
8967 vbuf
= xtensa_insnbuf_alloc (isa
);
8969 xtensa_insnbuf_from_chars
8970 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8971 fmt
= xtensa_format_decode (isa
, vbuf
);
8972 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8974 for (slot
= 0; slot
< num_slots
; slot
++)
8976 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8979 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8983 case RELAX_IMMED_STEP1
:
8984 case RELAX_IMMED_STEP2
:
8985 /* Place the immediate. */
8988 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8993 /* This is OK because some slots could have
8994 relaxations and others have none. */
9000 case RELAX_UNREACHABLE
:
9001 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9002 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9003 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9007 case RELAX_MAYBE_UNREACHABLE
:
9008 case RELAX_MAYBE_DESIRE_ALIGN
:
9012 case RELAX_FILL_NOP
:
9013 convert_frag_fill_nop (fragp
);
9016 case RELAX_LITERAL_NR
:
9017 if (use_literal_section
)
9019 /* This should have been handled during relaxation. When
9020 relaxing a code segment, literals sometimes need to be
9021 added to the corresponding literal segment. If that
9022 literal segment has already been relaxed, then we end up
9023 in this situation. Marking the literal segments as data
9024 would make this happen less often (since GAS always relaxes
9025 code before data), but we could still get into trouble if
9026 there are instructions in a segment that is not marked as
9027 containing code. Until we can implement a better solution,
9028 cheat and adjust the addresses of all the following frags.
9029 This could break subsequent alignments, but the linker's
9030 literal coalescing will do that anyway. */
9033 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9034 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9035 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9038 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9042 as_bad (_("invalid relaxation fragment result"));
9047 new_logical_line (file_name
, line
);
9052 convert_frag_align_next_opcode (fragS
*fragp
)
9054 char *nop_buf
; /* Location for Writing. */
9055 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9056 addressT aligned_address
;
9060 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9062 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9063 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9064 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9066 for (nop
= 0; nop
< nop_count
; nop
++)
9069 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9071 assemble_nop (nop_size
, nop_buf
);
9072 nop_buf
+= nop_size
;
9075 fragp
->fr_fix
+= fill_size
;
9076 fragp
->fr_var
-= fill_size
;
9081 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9083 TInsn tinsn
, single_target
;
9084 xtensa_format single_fmt
;
9085 int size
, old_size
, diff
;
9086 offsetT frag_offset
;
9089 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9091 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9093 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9094 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9095 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9100 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9102 /* No conversion. */
9107 assert (fragP
->fr_opcode
!= NULL
);
9109 /* Frags in this relaxation state should only contain
9110 single instruction bundles. */
9111 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9113 /* Just convert it to a wide form.... */
9115 old_size
= xg_get_single_size (tinsn
.opcode
);
9117 tinsn_init (&single_target
);
9118 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9120 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9122 as_bad (_("unable to widen instruction"));
9126 size
= xg_get_single_size (single_target
.opcode
);
9127 single_fmt
= xg_get_single_format (single_target
.opcode
);
9129 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9130 fragP
, frag_offset
, TRUE
);
9132 diff
= size
- old_size
;
9134 assert (diff
<= fragP
->fr_var
);
9135 fragP
->fr_var
-= diff
;
9136 fragP
->fr_fix
+= diff
;
9144 convert_frag_fill_nop (fragS
*fragP
)
9146 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9147 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9148 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9149 - fragP
->fr_address
- fragP
->fr_fix
));
9152 /* No conversion. */
9156 assemble_nop (size
, loc
);
9157 fragP
->tc_frag_data
.is_insn
= TRUE
;
9158 fragP
->fr_var
-= size
;
9159 fragP
->fr_fix
+= size
;
9164 static fixS
*fix_new_exp_in_seg
9165 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9166 bfd_reloc_code_real_type
);
9167 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9170 convert_frag_immed (segT segP
,
9176 char *immed_instr
= fragP
->fr_opcode
;
9178 bfd_boolean expanded
= FALSE
;
9179 bfd_boolean branch_jmp_to_next
= FALSE
;
9180 char *fr_opcode
= fragP
->fr_opcode
;
9181 vliw_insn orig_vinsn
;
9182 xtensa_isa isa
= xtensa_default_isa
;
9183 bfd_boolean wide_insn
= FALSE
;
9185 bfd_boolean is_loop
;
9187 assert (fr_opcode
!= NULL
);
9189 xg_init_vinsn (&orig_vinsn
);
9191 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9192 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9195 orig_tinsn
= orig_vinsn
.slots
[slot
];
9196 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9198 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9200 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9201 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9203 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9205 /* Conversion just inserts a NOP and marks the fix as completed. */
9206 bytes
= xtensa_format_length (isa
, fmt
);
9209 orig_vinsn
.slots
[slot
].opcode
=
9210 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9211 orig_vinsn
.slots
[slot
].ntok
= 0;
9215 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9216 assert (bytes
== 2 || bytes
== 3);
9217 build_nop (&orig_vinsn
.slots
[0], bytes
);
9218 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9220 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9221 xtensa_insnbuf_to_chars
9222 (isa
, orig_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9227 /* Here is the fun stuff: Get the immediate field from this
9228 instruction. If it fits, we're done. If not, find the next
9229 instruction sequence that fits. */
9233 symbolS
*lit_sym
= NULL
;
9235 int target_offset
= 0;
9238 symbolS
*gen_label
= NULL
;
9239 offsetT frag_offset
;
9240 bfd_boolean first
= TRUE
;
9241 bfd_boolean last_is_jump
;
9243 /* It does not fit. Find something that does and
9244 convert immediately. */
9245 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9246 istack_init (&istack
);
9247 xg_assembly_relax (&istack
, &orig_tinsn
,
9248 segP
, fragP
, frag_offset
, min_steps
, 0);
9250 old_size
= xtensa_format_length (isa
, fmt
);
9252 /* Assemble this right inline. */
9254 /* First, create the mapping from a label name to the REAL label. */
9256 for (i
= 0; i
< istack
.ninsn
; i
++)
9258 TInsn
*tinsn
= &istack
.insn
[i
];
9261 switch (tinsn
->insn_type
)
9264 if (lit_sym
!= NULL
)
9265 as_bad (_("multiple literals in expansion"));
9266 /* First find the appropriate space in the literal pool. */
9267 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9268 if (lit_frag
== NULL
)
9269 as_bad (_("no registered fragment for literal"));
9270 if (tinsn
->ntok
!= 1)
9271 as_bad (_("number of literal tokens != 1"));
9273 /* Set the literal symbol and add a fixup. */
9274 lit_sym
= lit_frag
->fr_symbol
;
9278 if (align_targets
&& !is_loop
)
9280 fragS
*unreach
= fragP
->fr_next
;
9281 while (!(unreach
->fr_type
== rs_machine_dependent
9282 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9283 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9285 unreach
= unreach
->fr_next
;
9288 assert (unreach
->fr_type
== rs_machine_dependent
9289 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9290 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9292 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9294 assert (gen_label
== NULL
);
9295 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9296 fr_opcode
- fragP
->fr_literal
9297 + target_offset
, fragP
);
9301 if (first
&& wide_insn
)
9303 target_offset
+= xtensa_format_length (isa
, fmt
);
9305 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9306 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9309 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9316 last_is_jump
= FALSE
;
9317 for (i
= 0; i
< istack
.ninsn
; i
++)
9319 TInsn
*tinsn
= &istack
.insn
[i
];
9323 bfd_reloc_code_real_type reloc_type
;
9325 switch (tinsn
->insn_type
)
9328 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9329 /* Already checked. */
9330 assert (lit_frag
!= NULL
);
9331 assert (lit_sym
!= NULL
);
9332 assert (tinsn
->ntok
== 1);
9334 target_seg
= S_GET_SEGMENT (lit_sym
);
9335 assert (target_seg
);
9336 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9337 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9339 reloc_type
= BFD_RELOC_32
;
9340 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9341 &tinsn
->tok
[0], FALSE
, reloc_type
);
9348 xg_resolve_labels (tinsn
, gen_label
);
9349 xg_resolve_literals (tinsn
, lit_sym
);
9350 if (wide_insn
&& first
)
9353 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9355 tinsn
->record_fix
= TRUE
;
9356 orig_vinsn
.slots
[slot
] = *tinsn
;
9360 orig_vinsn
.slots
[slot
].opcode
=
9361 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9362 orig_vinsn
.slots
[slot
].ntok
= 0;
9363 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9365 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9366 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9367 (unsigned char *) immed_instr
, 0);
9368 fragP
->tc_frag_data
.is_insn
= TRUE
;
9369 size
= xtensa_format_length (isa
, fmt
);
9370 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9372 xtensa_format single_fmt
=
9373 xg_get_single_format (tinsn
->opcode
);
9376 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9377 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9378 size
+= xg_get_single_size (tinsn
->opcode
);
9383 xtensa_format single_format
;
9384 size
= xg_get_single_size (tinsn
->opcode
);
9385 single_format
= xg_get_single_format (tinsn
->opcode
);
9386 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9388 immed_instr
- fragP
->fr_literal
, TRUE
);
9390 immed_instr
+= size
;
9396 diff
= total_size
- old_size
;
9400 assert (diff
<= fragP
->fr_var
);
9401 fragP
->fr_var
-= diff
;
9402 fragP
->fr_fix
+= diff
;
9406 xg_free_vinsn (&orig_vinsn
);
9408 /* Check for undefined immediates in LOOP instructions. */
9412 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9413 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9415 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9418 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9419 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9421 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9426 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9427 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9429 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9431 /* Add an expansion note on the expanded instruction. */
9432 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9433 &orig_tinsn
.tok
[0], TRUE
,
9434 BFD_RELOC_XTENSA_ASM_EXPAND
);
9439 /* Add a new fix expression into the desired segment. We have to
9440 switch to that segment to do this. */
9443 fix_new_exp_in_seg (segT new_seg
,
9450 bfd_reloc_code_real_type r_type
)
9454 subsegT subseg
= now_subseg
;
9456 assert (new_seg
!= 0);
9457 subseg_set (new_seg
, new_subseg
);
9459 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9460 subseg_set (seg
, subseg
);
9465 /* Relax a loop instruction so that it can span loop >256 bytes.
9471 addi as, as, lo8 (label-.L1)
9472 addmi as, as, mid8 (label-.L1)
9483 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9488 unsigned long target
;
9489 static xtensa_insnbuf insnbuf
= NULL
;
9490 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9491 xtensa_isa isa
= xtensa_default_isa
;
9492 addressT loop_offset
;
9493 addressT addi_offset
= 9;
9494 addressT addmi_offset
= 12;
9499 insnbuf
= xtensa_insnbuf_alloc (isa
);
9501 /* Get the loop offset. */
9502 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9504 /* Validate that there really is a LOOP at the loop_offset. Because
9505 loops are not bundleable, we can assume that the instruction will be
9507 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9508 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9510 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9511 addi_offset
+= loop_offset
;
9512 addmi_offset
+= loop_offset
;
9514 assert (tinsn
->ntok
== 2);
9515 if (tinsn
->tok
[1].X_op
== O_constant
)
9516 target
= tinsn
->tok
[1].X_add_number
;
9517 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9519 /* Find the fragment. */
9520 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9521 assert (S_GET_SEGMENT (sym
) == segP
9522 || S_GET_SEGMENT (sym
) == absolute_section
);
9523 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9527 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9532 know (symbolP
->sy_frag
);
9533 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9534 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9536 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9537 loop_length_hi
= loop_length
& ~0x0ff;
9538 loop_length_lo
= loop_length
& 0x0ff;
9539 if (loop_length_lo
>= 128)
9541 loop_length_lo
-= 256;
9542 loop_length_hi
+= 256;
9545 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9546 32512. If the loop is larger than that, then we just fail. */
9547 if (loop_length_hi
> 32512)
9548 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9549 _("loop too long for LOOP instruction"));
9551 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9552 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9554 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9555 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9557 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9558 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9560 fragP
->tc_frag_data
.is_insn
= TRUE
;
9561 xtensa_insnbuf_to_chars
9562 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9564 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9565 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9566 xtensa_insnbuf_to_chars
9567 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9569 /* Walk through all of the frags from here to the loop end
9570 and mark them as no_transform to keep them from being modified
9571 by the linker. If we ever have a relocation for the
9572 addi/addmi of the difference of two symbols we can remove this. */
9575 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9576 next_fragP
= next_fragP
->fr_next
)
9578 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9579 if (next_fragP
->tc_frag_data
.is_loop_target
)
9581 if (target_count
== 2)
9587 /* A map that keeps information on a per-subsegment basis. This is
9588 maintained during initial assembly, but is invalid once the
9589 subsegments are smashed together. I.E., it cannot be used during
9592 typedef struct subseg_map_struct
9600 float total_freq
; /* fall-through + branch target frequency */
9601 float target_freq
; /* branch target frequency alone */
9603 struct subseg_map_struct
*next
;
9607 static subseg_map
*sseg_map
= NULL
;
9610 get_subseg_info (segT seg
, subsegT subseg
)
9612 subseg_map
*subseg_e
;
9614 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9616 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9624 add_subseg_info (segT seg
, subsegT subseg
)
9626 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9627 memset (subseg_e
, 0, sizeof (subseg_map
));
9628 subseg_e
->seg
= seg
;
9629 subseg_e
->subseg
= subseg
;
9630 subseg_e
->flags
= 0;
9631 /* Start off considering every branch target very important. */
9632 subseg_e
->target_freq
= 1.0;
9633 subseg_e
->total_freq
= 1.0;
9634 subseg_e
->next
= sseg_map
;
9635 sseg_map
= subseg_e
;
9641 get_last_insn_flags (segT seg
, subsegT subseg
)
9643 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9645 return subseg_e
->flags
;
9651 set_last_insn_flags (segT seg
,
9656 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9658 subseg_e
= add_subseg_info (seg
, subseg
);
9660 subseg_e
->flags
|= fl
;
9662 subseg_e
->flags
&= ~fl
;
9667 get_subseg_total_freq (segT seg
, subsegT subseg
)
9669 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9671 return subseg_e
->total_freq
;
9677 get_subseg_target_freq (segT seg
, subsegT subseg
)
9679 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9681 return subseg_e
->target_freq
;
9687 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9689 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9691 subseg_e
= add_subseg_info (seg
, subseg
);
9692 subseg_e
->total_freq
= total_f
;
9693 subseg_e
->target_freq
= target_f
;
9697 /* Segment Lists and emit_state Stuff. */
9700 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9705 segT literal_section
= head
->seg
;
9707 /* Move the literal section to the front of the section list. */
9708 assert (literal_section
);
9709 if (literal_section
!= stdoutput
->sections
)
9711 bfd_section_list_remove (stdoutput
, literal_section
);
9712 bfd_section_list_prepend (stdoutput
, literal_section
);
9719 static void mark_literal_frags (seg_list
*);
9722 xtensa_move_literals (void)
9725 frchainS
*frchain_from
, *frchain_to
;
9726 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9727 fragS
**frag_splice
;
9730 fixS
*fix
, *next_fix
, **fix_splice
;
9733 mark_literal_frags (literal_head
->next
);
9734 mark_literal_frags (init_literal_head
->next
);
9735 mark_literal_frags (fini_literal_head
->next
);
9737 if (use_literal_section
)
9740 segment
= literal_head
->next
;
9743 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9744 search_frag
= frchain_from
->frch_root
;
9745 literal_pool
= NULL
;
9747 frag_splice
= &(frchain_from
->frch_root
);
9749 while (!search_frag
->tc_frag_data
.literal_frag
)
9751 assert (search_frag
->fr_fix
== 0
9752 || search_frag
->fr_type
== rs_align
);
9753 search_frag
= search_frag
->fr_next
;
9756 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9757 == RELAX_LITERAL_POOL_BEGIN
);
9758 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9760 /* Make sure that all the frags in this series are closed, and
9761 that there is at least one left over of zero-size. This
9762 prevents us from making a segment with an frchain without any
9764 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9765 xtensa_set_frag_assembly_state (frag_now
);
9766 last_frag
= frag_now
;
9767 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9768 xtensa_set_frag_assembly_state (frag_now
);
9770 while (search_frag
!= frag_now
)
9772 next_frag
= search_frag
->fr_next
;
9774 /* First, move the frag out of the literal section and
9775 to the appropriate place. */
9776 if (search_frag
->tc_frag_data
.literal_frag
)
9778 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9779 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9780 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9781 assert (frchain_to
);
9783 insert_after
= literal_pool
;
9785 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9786 insert_after
= insert_after
->fr_next
;
9788 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9790 *frag_splice
= next_frag
;
9791 search_frag
->fr_next
= insert_after
->fr_next
;
9792 insert_after
->fr_next
= search_frag
;
9793 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9795 /* Now move any fixups associated with this frag to the
9797 fix
= frchain_from
->fix_root
;
9798 fix_splice
= &(frchain_from
->fix_root
);
9801 next_fix
= fix
->fx_next
;
9802 if (fix
->fx_frag
== search_frag
)
9804 *fix_splice
= next_fix
;
9805 fix
->fx_next
= frchain_to
->fix_root
;
9806 frchain_to
->fix_root
= fix
;
9807 if (frchain_to
->fix_tail
== NULL
)
9808 frchain_to
->fix_tail
= fix
;
9811 fix_splice
= &(fix
->fx_next
);
9814 search_frag
= next_frag
;
9817 if (frchain_from
->fix_root
!= NULL
)
9819 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9820 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9822 assert (frchain_from
->fix_root
== NULL
);
9824 frchain_from
->fix_tail
= NULL
;
9825 xtensa_restore_emit_state (&state
);
9826 segment
= segment
->next
;
9829 /* Now fix up the SEGMENT value for all the literal symbols. */
9830 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9832 symbolS
*lit_sym
= lit
->sym
;
9833 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9835 S_SET_SEGMENT (lit_sym
, dest_seg
);
9840 /* Walk over all the frags for segments in a list and mark them as
9841 containing literals. As clunky as this is, we can't rely on frag_var
9842 and frag_variant to get called in all situations. */
9845 mark_literal_frags (seg_list
*segment
)
9847 frchainS
*frchain_from
;
9852 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9853 search_frag
= frchain_from
->frch_root
;
9856 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9857 search_frag
= search_frag
->fr_next
;
9859 segment
= segment
->next
;
9865 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9867 /* Move all of the sections in the section list to come
9868 after "after" in the gnu segment list. */
9873 segT literal_section
= head
->seg
;
9875 /* Move the literal section after "after". */
9876 assert (literal_section
);
9877 if (literal_section
!= after
)
9879 bfd_section_list_remove (stdoutput
, literal_section
);
9880 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9888 /* Push all the literal segments to the end of the gnu list. */
9891 xtensa_reorder_segments (void)
9898 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9904 /* Now that we have the last section, push all the literal
9905 sections to the end. */
9906 xtensa_reorder_seg_list (literal_head
, last_sec
);
9907 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9908 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9910 /* Now perform the final error check. */
9911 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9913 assert (new_count
== old_count
);
9917 /* Change the emit state (seg, subseg, and frag related stuff) to the
9918 correct location. Return a emit_state which can be passed to
9919 xtensa_restore_emit_state to return to current fragment. */
9922 xtensa_switch_to_literal_fragment (emit_state
*result
)
9924 if (directive_state
[directive_absolute_literals
])
9926 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9927 &default_lit_sections
.lit4_seg
, FALSE
);
9928 xtensa_switch_section_emit_state (result
,
9929 default_lit_sections
.lit4_seg
, 0);
9932 xtensa_switch_to_non_abs_literal_fragment (result
);
9934 /* Do a 4-byte align here. */
9935 frag_align (2, 0, 0);
9936 record_alignment (now_seg
, 2);
9941 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9943 /* When we mark a literal pool location, we want to put a frag in
9944 the literal pool that points to it. But to do that, we want to
9945 switch_to_literal_fragment. But literal sections don't have
9946 literal pools, so their location is always null, so we would
9947 recurse forever. This is kind of hacky, but it works. */
9949 static bfd_boolean recursive
= FALSE
;
9950 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9951 bfd_boolean is_init
=
9952 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9954 bfd_boolean is_fini
=
9955 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9957 if (pool_location
== NULL
9958 && !use_literal_section
9960 && !is_init
&& ! is_fini
)
9962 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9964 xtensa_mark_literal_pool_location ();
9968 /* Special case: If we are in the ".fini" or ".init" section, then
9969 we will ALWAYS be generating to the ".fini.literal" and
9970 ".init.literal" sections. */
9974 cache_literal_section (init_literal_head
,
9975 default_lit_sections
.init_lit_seg_name
,
9976 &default_lit_sections
.init_lit_seg
, TRUE
);
9977 xtensa_switch_section_emit_state (result
,
9978 default_lit_sections
.init_lit_seg
, 0);
9982 cache_literal_section (fini_literal_head
,
9983 default_lit_sections
.fini_lit_seg_name
,
9984 &default_lit_sections
.fini_lit_seg
, TRUE
);
9985 xtensa_switch_section_emit_state (result
,
9986 default_lit_sections
.fini_lit_seg
, 0);
9990 cache_literal_section (literal_head
,
9991 default_lit_sections
.lit_seg_name
,
9992 &default_lit_sections
.lit_seg
, TRUE
);
9993 xtensa_switch_section_emit_state (result
,
9994 default_lit_sections
.lit_seg
, 0);
9997 if (!use_literal_section
9998 && !is_init
&& !is_fini
9999 && get_literal_pool_location (now_seg
) != pool_location
)
10001 /* Close whatever frag is there. */
10002 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10003 xtensa_set_frag_assembly_state (frag_now
);
10004 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10005 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10006 xtensa_set_frag_assembly_state (frag_now
);
10011 /* Call this function before emitting data into the literal section.
10012 This is a helper function for xtensa_switch_to_literal_fragment.
10013 This is similar to a .section new_now_seg subseg. */
10016 xtensa_switch_section_emit_state (emit_state
*state
,
10018 subsegT new_now_subseg
)
10020 state
->name
= now_seg
->name
;
10021 state
->now_seg
= now_seg
;
10022 state
->now_subseg
= now_subseg
;
10023 state
->generating_literals
= generating_literals
;
10024 generating_literals
++;
10025 subseg_set (new_now_seg
, new_now_subseg
);
10029 /* Use to restore the emitting into the normal place. */
10032 xtensa_restore_emit_state (emit_state
*state
)
10034 generating_literals
= state
->generating_literals
;
10035 subseg_set (state
->now_seg
, state
->now_subseg
);
10039 /* Get a segment of a given name. If the segment is already
10040 present, return it; otherwise, create a new one. */
10043 cache_literal_section (seg_list
*head
,
10046 bfd_boolean is_code
)
10048 segT current_section
= now_seg
;
10049 int current_subsec
= now_subseg
;
10055 /* Check if the named section exists. */
10056 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10058 if (!strcmp (segment_name (seg
), name
))
10064 /* Create a new literal section. */
10065 seg
= subseg_new (name
, (subsegT
) 0);
10068 /* Add the newly created literal segment to the specified list. */
10069 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10071 n
->next
= head
->next
;
10074 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10075 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10076 | (is_code
? SEC_CODE
: SEC_DATA
));
10077 bfd_set_section_alignment (stdoutput
, seg
, 2);
10081 subseg_set (current_section
, current_subsec
);
10085 /* Property Tables Stuff. */
10087 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10088 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10089 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10091 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10092 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10094 static bfd_boolean
get_frag_is_literal (const fragS
*);
10095 static void xtensa_create_property_segments
10096 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10097 static void xtensa_create_xproperty_segments
10098 (frag_flags_fn
, const char *, xt_section_type
);
10099 static segment_info_type
*retrieve_segment_info (segT
);
10100 static segT
retrieve_xtensa_section (char *);
10101 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10102 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10103 static void add_xt_block_frags
10104 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10105 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10106 static void xtensa_frag_flags_init (frag_flags
*);
10107 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10108 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10109 static void add_xt_prop_frags
10110 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10112 /* Set up property tables after relaxation. */
10115 xtensa_post_relax_hook (void)
10117 xtensa_move_seg_list_to_beginning (literal_head
);
10118 xtensa_move_seg_list_to_beginning (init_literal_head
);
10119 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10121 xtensa_find_unmarked_state_frags ();
10123 if (use_literal_section
)
10124 xtensa_create_property_segments (get_frag_is_literal
,
10126 XTENSA_LIT_SEC_NAME
,
10128 xtensa_create_xproperty_segments (get_frag_property_flags
,
10129 XTENSA_PROP_SEC_NAME
,
10132 if (warn_unaligned_branch_targets
)
10133 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10134 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10138 /* This function is only meaningful after xtensa_move_literals. */
10141 get_frag_is_literal (const fragS
*fragP
)
10143 assert (fragP
!= NULL
);
10144 return fragP
->tc_frag_data
.is_literal
;
10149 xtensa_create_property_segments (frag_predicate property_function
,
10150 frag_predicate end_property_function
,
10151 const char *section_name_base
,
10152 xt_section_type sec_type
)
10156 /* Walk over all of the current segments.
10157 Walk over each fragment
10158 For each non-empty fragment,
10159 Build a property record (append where possible). */
10161 for (seclist
= &stdoutput
->sections
;
10162 seclist
&& *seclist
;
10163 seclist
= &(*seclist
)->next
)
10165 segT sec
= *seclist
;
10168 flags
= bfd_get_section_flags (stdoutput
, sec
);
10169 if (flags
& SEC_DEBUGGING
)
10171 if (!(flags
& SEC_ALLOC
))
10174 if (section_has_property (sec
, property_function
))
10176 char *property_section_name
=
10177 xtensa_get_property_section_name (sec
, section_name_base
);
10178 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10179 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10180 xtensa_block_info
**xt_blocks
=
10181 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10182 /* Walk over all of the frchains here and add new sections. */
10183 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10184 end_property_function
);
10188 /* Now we fill them out.... */
10190 for (seclist
= &stdoutput
->sections
;
10191 seclist
&& *seclist
;
10192 seclist
= &(*seclist
)->next
)
10194 segment_info_type
*seginfo
;
10195 xtensa_block_info
*block
;
10196 segT sec
= *seclist
;
10198 seginfo
= seg_info (sec
);
10199 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10203 xtensa_block_info
*cur_block
;
10204 /* This is a section with some data. */
10206 bfd_size_type rec_size
;
10208 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10211 rec_size
= num_recs
* 8;
10212 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10214 /* In order to make this work with the assembler, we have to
10215 build some frags and then build the "fixups" for it. It
10216 would be easier to just set the contents then set the
10221 /* Allocate a fragment and leak it. */
10223 bfd_size_type frag_size
;
10225 frchainS
*frchainP
;
10229 frag_size
= sizeof (fragS
) + rec_size
;
10230 fragP
= (fragS
*) xmalloc (frag_size
);
10232 memset (fragP
, 0, frag_size
);
10233 fragP
->fr_address
= 0;
10234 fragP
->fr_next
= NULL
;
10235 fragP
->fr_fix
= rec_size
;
10237 fragP
->fr_type
= rs_fill
;
10238 /* The rest are zeros. */
10240 frchainP
= seginfo
->frchainP
;
10241 frchainP
->frch_root
= fragP
;
10242 frchainP
->frch_last
= fragP
;
10244 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10245 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10247 seginfo
->fix_root
= fixes
;
10248 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10250 frag_data
= &fragP
->fr_literal
[0];
10251 for (i
= 0; i
< num_recs
; i
++)
10253 fixS
*fix
= &fixes
[i
];
10254 assert (cur_block
);
10256 /* Write the fixup. */
10257 if (i
!= num_recs
- 1)
10258 fix
->fx_next
= &fixes
[i
+ 1];
10260 fix
->fx_next
= NULL
;
10263 fix
->fx_frag
= fragP
;
10264 fix
->fx_where
= i
* 8;
10265 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10266 fix
->fx_offset
= cur_block
->offset
;
10267 fix
->fx_r_type
= BFD_RELOC_32
;
10268 fix
->fx_file
= "Internal Assembly";
10271 /* Write the length. */
10272 md_number_to_chars (&frag_data
[4 + 8 * i
],
10273 cur_block
->size
, 4);
10274 cur_block
= cur_block
->next
;
10283 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10284 const char *section_name_base
,
10285 xt_section_type sec_type
)
10289 /* Walk over all of the current segments.
10290 Walk over each fragment.
10291 For each fragment that has instructions,
10292 build an instruction record (append where possible). */
10294 for (seclist
= &stdoutput
->sections
;
10295 seclist
&& *seclist
;
10296 seclist
= &(*seclist
)->next
)
10298 segT sec
= *seclist
;
10301 flags
= bfd_get_section_flags (stdoutput
, sec
);
10302 if ((flags
& SEC_DEBUGGING
)
10303 || !(flags
& SEC_ALLOC
)
10304 || (flags
& SEC_MERGE
))
10307 if (section_has_xproperty (sec
, flag_fn
))
10309 char *property_section_name
=
10310 xtensa_get_property_section_name (sec
, section_name_base
);
10311 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10312 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10313 xtensa_block_info
**xt_blocks
=
10314 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10315 /* Walk over all of the frchains here and add new sections. */
10316 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10320 /* Now we fill them out.... */
10322 for (seclist
= &stdoutput
->sections
;
10323 seclist
&& *seclist
;
10324 seclist
= &(*seclist
)->next
)
10326 segment_info_type
*seginfo
;
10327 xtensa_block_info
*block
;
10328 segT sec
= *seclist
;
10330 seginfo
= seg_info (sec
);
10331 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10335 xtensa_block_info
*cur_block
;
10336 /* This is a section with some data. */
10338 bfd_size_type rec_size
;
10340 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10343 rec_size
= num_recs
* (8 + 4);
10344 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10346 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10348 /* In order to make this work with the assembler, we have to build
10349 some frags then build the "fixups" for it. It would be easier to
10350 just set the contents then set the arlents. */
10354 /* Allocate a fragment and (unfortunately) leak it. */
10356 bfd_size_type frag_size
;
10358 frchainS
*frchainP
;
10362 frag_size
= sizeof (fragS
) + rec_size
;
10363 fragP
= (fragS
*) xmalloc (frag_size
);
10365 memset (fragP
, 0, frag_size
);
10366 fragP
->fr_address
= 0;
10367 fragP
->fr_next
= NULL
;
10368 fragP
->fr_fix
= rec_size
;
10370 fragP
->fr_type
= rs_fill
;
10371 /* The rest are zeros. */
10373 frchainP
= seginfo
->frchainP
;
10374 frchainP
->frch_root
= fragP
;
10375 frchainP
->frch_last
= fragP
;
10377 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10378 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10380 seginfo
->fix_root
= fixes
;
10381 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10383 frag_data
= &fragP
->fr_literal
[0];
10384 for (i
= 0; i
< num_recs
; i
++)
10386 fixS
*fix
= &fixes
[i
];
10387 assert (cur_block
);
10389 /* Write the fixup. */
10390 if (i
!= num_recs
- 1)
10391 fix
->fx_next
= &fixes
[i
+ 1];
10393 fix
->fx_next
= NULL
;
10396 fix
->fx_frag
= fragP
;
10397 fix
->fx_where
= i
* (8 + 4);
10398 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10399 fix
->fx_offset
= cur_block
->offset
;
10400 fix
->fx_r_type
= BFD_RELOC_32
;
10401 fix
->fx_file
= "Internal Assembly";
10404 /* Write the length. */
10405 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10406 cur_block
->size
, 4);
10407 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10408 frag_flags_to_number (&cur_block
->flags
),
10410 cur_block
= cur_block
->next
;
10418 static segment_info_type
*
10419 retrieve_segment_info (segT seg
)
10421 segment_info_type
*seginfo
;
10422 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10425 frchainS
*frchainP
;
10427 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10428 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10429 seginfo
->fix_root
= NULL
;
10430 seginfo
->fix_tail
= NULL
;
10431 seginfo
->bfd_section
= seg
;
10433 /* We will not be dealing with these, only our special ones. */
10434 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10436 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10437 frchainP
->frch_root
= NULL
;
10438 frchainP
->frch_last
= NULL
;
10439 frchainP
->frch_next
= NULL
;
10440 frchainP
->frch_seg
= seg
;
10441 frchainP
->frch_subseg
= 0;
10442 frchainP
->fix_root
= NULL
;
10443 frchainP
->fix_tail
= NULL
;
10444 /* Do not init the objstack. */
10445 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10446 /* frchainP->frch_frag_now = fragP; */
10447 frchainP
->frch_frag_now
= NULL
;
10449 seginfo
->frchainP
= frchainP
;
10457 retrieve_xtensa_section (char *sec_name
)
10459 bfd
*abfd
= stdoutput
;
10460 flagword flags
, out_flags
, link_once_flags
;
10463 flags
= bfd_get_section_flags (abfd
, now_seg
);
10464 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10465 if (link_once_flags
)
10466 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10467 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10469 s
= bfd_make_section_old_way (abfd
, sec_name
);
10471 as_bad (_("could not create section %s"), sec_name
);
10472 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10473 as_bad (_("invalid flag combination on section %s"), sec_name
);
10480 section_has_property (segT sec
, frag_predicate property_function
)
10482 segment_info_type
*seginfo
= seg_info (sec
);
10485 if (seginfo
&& seginfo
->frchainP
)
10487 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10489 if (property_function (fragP
)
10490 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10499 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10501 segment_info_type
*seginfo
= seg_info (sec
);
10504 if (seginfo
&& seginfo
->frchainP
)
10506 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10508 frag_flags prop_flags
;
10509 property_function (fragP
, &prop_flags
);
10510 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10518 /* Two types of block sections exist right now: literal and insns. */
10521 add_xt_block_frags (segT sec
,
10523 xtensa_block_info
**xt_block
,
10524 frag_predicate property_function
,
10525 frag_predicate end_property_function
)
10527 segment_info_type
*seg_info
;
10528 segment_info_type
*xt_seg_info
;
10529 bfd_vma seg_offset
;
10532 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10533 seg_info
= retrieve_segment_info (sec
);
10535 /* Build it if needed. */
10536 while (*xt_block
!= NULL
)
10537 xt_block
= &(*xt_block
)->next
;
10538 /* We are either at NULL at the beginning or at the end. */
10540 /* Walk through the frags. */
10543 if (seg_info
->frchainP
)
10545 for (fragP
= seg_info
->frchainP
->frch_root
;
10547 fragP
= fragP
->fr_next
)
10549 if (property_function (fragP
)
10550 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10552 if (*xt_block
!= NULL
)
10554 if ((*xt_block
)->offset
+ (*xt_block
)->size
10555 == fragP
->fr_address
)
10556 (*xt_block
)->size
+= fragP
->fr_fix
;
10558 xt_block
= &((*xt_block
)->next
);
10560 if (*xt_block
== NULL
)
10562 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10563 xmalloc (sizeof (xtensa_block_info
));
10564 new_block
->sec
= sec
;
10565 new_block
->offset
= fragP
->fr_address
;
10566 new_block
->size
= fragP
->fr_fix
;
10567 new_block
->next
= NULL
;
10568 xtensa_frag_flags_init (&new_block
->flags
);
10569 *xt_block
= new_block
;
10571 if (end_property_function
10572 && end_property_function (fragP
))
10574 xt_block
= &((*xt_block
)->next
);
10582 /* Break the encapsulation of add_xt_prop_frags here. */
10585 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10587 if (prop_flags
->is_literal
10588 || prop_flags
->is_insn
10589 || prop_flags
->is_data
10590 || prop_flags
->is_unreachable
)
10597 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10599 memset (prop_flags
, 0, sizeof (frag_flags
));
10604 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10606 xtensa_frag_flags_init (prop_flags
);
10607 if (fragP
->tc_frag_data
.is_literal
)
10608 prop_flags
->is_literal
= TRUE
;
10609 if (fragP
->tc_frag_data
.is_unreachable
)
10610 prop_flags
->is_unreachable
= TRUE
;
10611 else if (fragP
->tc_frag_data
.is_insn
)
10613 prop_flags
->is_insn
= TRUE
;
10614 if (fragP
->tc_frag_data
.is_loop_target
)
10615 prop_flags
->insn
.is_loop_target
= TRUE
;
10616 if (fragP
->tc_frag_data
.is_branch_target
)
10617 prop_flags
->insn
.is_branch_target
= TRUE
;
10618 if (fragP
->tc_frag_data
.is_specific_opcode
10619 || fragP
->tc_frag_data
.is_no_transform
)
10620 prop_flags
->insn
.is_no_transform
= TRUE
;
10621 if (fragP
->tc_frag_data
.is_no_density
)
10622 prop_flags
->insn
.is_no_density
= TRUE
;
10623 if (fragP
->tc_frag_data
.use_absolute_literals
)
10624 prop_flags
->insn
.is_abslit
= TRUE
;
10626 if (fragP
->tc_frag_data
.is_align
)
10628 prop_flags
->is_align
= TRUE
;
10629 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10630 if (xtensa_frag_flags_is_empty (prop_flags
))
10631 prop_flags
->is_data
= TRUE
;
10637 frag_flags_to_number (const frag_flags
*prop_flags
)
10640 if (prop_flags
->is_literal
)
10641 num
|= XTENSA_PROP_LITERAL
;
10642 if (prop_flags
->is_insn
)
10643 num
|= XTENSA_PROP_INSN
;
10644 if (prop_flags
->is_data
)
10645 num
|= XTENSA_PROP_DATA
;
10646 if (prop_flags
->is_unreachable
)
10647 num
|= XTENSA_PROP_UNREACHABLE
;
10648 if (prop_flags
->insn
.is_loop_target
)
10649 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10650 if (prop_flags
->insn
.is_branch_target
)
10652 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10653 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10656 if (prop_flags
->insn
.is_no_density
)
10657 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10658 if (prop_flags
->insn
.is_no_transform
)
10659 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10660 if (prop_flags
->insn
.is_no_reorder
)
10661 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10662 if (prop_flags
->insn
.is_abslit
)
10663 num
|= XTENSA_PROP_INSN_ABSLIT
;
10665 if (prop_flags
->is_align
)
10667 num
|= XTENSA_PROP_ALIGN
;
10668 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10676 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10677 const frag_flags
*prop_flags_2
)
10679 /* Cannot combine with an end marker. */
10681 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10683 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10685 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10688 if (prop_flags_1
->is_insn
)
10690 /* Properties of the beginning of the frag. */
10691 if (prop_flags_2
->insn
.is_loop_target
)
10693 if (prop_flags_2
->insn
.is_branch_target
)
10695 if (prop_flags_1
->insn
.is_no_density
!=
10696 prop_flags_2
->insn
.is_no_density
)
10698 if (prop_flags_1
->insn
.is_no_transform
!=
10699 prop_flags_2
->insn
.is_no_transform
)
10701 if (prop_flags_1
->insn
.is_no_reorder
!=
10702 prop_flags_2
->insn
.is_no_reorder
)
10704 if (prop_flags_1
->insn
.is_abslit
!=
10705 prop_flags_2
->insn
.is_abslit
)
10709 if (prop_flags_1
->is_align
)
10717 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10720 unsigned align_bits
;
10722 if (!xt_block
->flags
.is_align
)
10723 return xt_block
->size
;
10725 end_addr
= xt_block
->offset
+ xt_block
->size
;
10726 align_bits
= xt_block
->flags
.alignment
;
10727 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10728 return end_addr
- xt_block
->offset
;
10733 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10734 const xtensa_block_info
*xt_block_2
)
10736 if (xt_block
->sec
!= xt_block_2
->sec
)
10738 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10739 != xt_block_2
->offset
)
10742 if (xt_block_2
->size
== 0
10743 && (!xt_block_2
->flags
.is_unreachable
10744 || xt_block
->flags
.is_unreachable
))
10746 if (xt_block_2
->flags
.is_align
10747 && xt_block
->flags
.is_align
)
10749 /* Nothing needed. */
10750 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10755 if (xt_block_2
->flags
.is_align
)
10757 /* Push alignment to previous entry. */
10758 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10759 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10764 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10765 &xt_block_2
->flags
))
10768 xt_block
->size
+= xt_block_2
->size
;
10770 if (xt_block_2
->flags
.is_align
)
10772 xt_block
->flags
.is_align
= TRUE
;
10773 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10781 add_xt_prop_frags (segT sec
,
10783 xtensa_block_info
**xt_block
,
10784 frag_flags_fn property_function
)
10786 segment_info_type
*seg_info
;
10787 segment_info_type
*xt_seg_info
;
10788 bfd_vma seg_offset
;
10791 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10792 seg_info
= retrieve_segment_info (sec
);
10793 /* Build it if needed. */
10794 while (*xt_block
!= NULL
)
10796 xt_block
= &(*xt_block
)->next
;
10798 /* We are either at NULL at the beginning or at the end. */
10800 /* Walk through the frags. */
10803 if (seg_info
->frchainP
)
10805 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10806 fragP
= fragP
->fr_next
)
10808 xtensa_block_info tmp_block
;
10809 tmp_block
.sec
= sec
;
10810 tmp_block
.offset
= fragP
->fr_address
;
10811 tmp_block
.size
= fragP
->fr_fix
;
10812 tmp_block
.next
= NULL
;
10813 property_function (fragP
, &tmp_block
.flags
);
10815 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10816 /* && fragP->fr_fix != 0) */
10818 if ((*xt_block
) == NULL
10819 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10821 xtensa_block_info
*new_block
;
10822 if ((*xt_block
) != NULL
)
10823 xt_block
= &(*xt_block
)->next
;
10824 new_block
= (xtensa_block_info
*)
10825 xmalloc (sizeof (xtensa_block_info
));
10826 *new_block
= tmp_block
;
10827 *xt_block
= new_block
;
10835 /* op_placement_info_table */
10837 /* op_placement_info makes it easier to determine which
10838 ops can go in which slots. */
10841 init_op_placement_info_table (void)
10843 xtensa_isa isa
= xtensa_default_isa
;
10844 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10845 xtensa_opcode opcode
;
10848 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10850 op_placement_table
= (op_placement_info_table
)
10851 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10852 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10854 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10856 op_placement_info
*opi
= &op_placement_table
[opcode
];
10857 /* FIXME: Make tinsn allocation dynamic. */
10858 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10859 as_fatal (_("too many operands in instruction"));
10860 opi
->single
= XTENSA_UNDEFINED
;
10861 opi
->single_size
= 0;
10862 opi
->widest
= XTENSA_UNDEFINED
;
10863 opi
->widest_size
= 0;
10864 opi
->narrowest
= XTENSA_UNDEFINED
;
10865 opi
->narrowest_size
= 0x7F;
10867 opi
->num_formats
= 0;
10869 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10871 opi
->slots
[fmt
] = 0;
10872 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10874 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10876 int fmt_length
= xtensa_format_length (isa
, fmt
);
10878 set_bit (fmt
, opi
->formats
);
10879 set_bit (slot
, opi
->slots
[fmt
]);
10880 /* opi->slot_count[fmt]++; */
10881 if (fmt_length
< opi
->narrowest_size
)
10883 opi
->narrowest
= fmt
;
10884 opi
->narrowest_size
= fmt_length
;
10886 if (fmt_length
> opi
->widest_size
)
10889 opi
->widest_size
= fmt_length
;
10891 if (xtensa_format_num_slots (isa
, fmt
) == 1)
10893 if (opi
->single_size
== 0
10894 || fmt_length
< opi
->single_size
)
10897 opi
->single_size
= fmt_length
;
10903 opi
->num_formats
++;
10906 xtensa_insnbuf_free (isa
, ibuf
);
10911 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10913 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10917 /* If the opcode is available in a single slot format, return its size. */
10920 xg_get_single_size (xtensa_opcode opcode
)
10922 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
10923 return op_placement_table
[opcode
].single_size
;
10927 static xtensa_format
10928 xg_get_single_format (xtensa_opcode opcode
)
10930 return op_placement_table
[opcode
].single
;
10934 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10937 istack_init (IStack
*stack
)
10939 memset (stack
, 0, sizeof (IStack
));
10945 istack_empty (IStack
*stack
)
10947 return (stack
->ninsn
== 0);
10952 istack_full (IStack
*stack
)
10954 return (stack
->ninsn
== MAX_ISTACK
);
10958 /* Return a pointer to the top IStack entry.
10959 It is an error to call this if istack_empty () is TRUE. */
10962 istack_top (IStack
*stack
)
10964 int rec
= stack
->ninsn
- 1;
10965 assert (!istack_empty (stack
));
10966 return &stack
->insn
[rec
];
10970 /* Add a new TInsn to an IStack.
10971 It is an error to call this if istack_full () is TRUE. */
10974 istack_push (IStack
*stack
, TInsn
*insn
)
10976 int rec
= stack
->ninsn
;
10977 assert (!istack_full (stack
));
10978 stack
->insn
[rec
] = *insn
;
10983 /* Clear space for the next TInsn on the IStack and return a pointer
10984 to it. It is an error to call this if istack_full () is TRUE. */
10987 istack_push_space (IStack
*stack
)
10989 int rec
= stack
->ninsn
;
10991 assert (!istack_full (stack
));
10992 insn
= &stack
->insn
[rec
];
10993 memset (insn
, 0, sizeof (TInsn
));
10999 /* Remove the last pushed instruction. It is an error to call this if
11000 istack_empty () returns TRUE. */
11003 istack_pop (IStack
*stack
)
11005 int rec
= stack
->ninsn
- 1;
11006 assert (!istack_empty (stack
));
11008 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11012 /* TInsn functions. */
11015 tinsn_init (TInsn
*dst
)
11017 memset (dst
, 0, sizeof (TInsn
));
11021 /* Get the ``num''th token of the TInsn.
11022 It is illegal to call this if num > insn->ntoks. */
11025 tinsn_get_tok (TInsn
*insn
, int num
)
11027 assert (num
< insn
->ntok
);
11028 return &insn
->tok
[num
];
11032 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11035 tinsn_has_symbolic_operands (const TInsn
*insn
)
11038 int n
= insn
->ntok
;
11040 assert (insn
->insn_type
== ITYPE_INSN
);
11042 for (i
= 0; i
< n
; ++i
)
11044 switch (insn
->tok
[i
].X_op
)
11058 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11060 xtensa_isa isa
= xtensa_default_isa
;
11062 int n
= insn
->ntok
;
11064 assert (insn
->insn_type
== ITYPE_INSN
);
11066 for (i
= 0; i
< n
; ++i
)
11068 switch (insn
->tok
[i
].X_op
)
11076 /* Errors for these types are caught later. */
11081 /* Symbolic immediates are only allowed on the last immediate
11082 operand. At this time, CONST16 is the only opcode where we
11083 support non-PC-relative relocations. (It isn't necessary
11084 to complain about non-PC-relative relocations here, but
11085 otherwise, no error is reported until the relocations are
11086 generated, and the assembler won't get that far if there
11087 are any other errors. It's nice to see all the problems
11089 if (i
!= get_relaxable_immed (insn
->opcode
)
11090 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11091 && insn
->opcode
!= xtensa_const16_opcode
))
11093 as_bad (_("invalid symbolic operand %d on '%s'"),
11094 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11103 /* For assembly code with complex expressions (e.g. subtraction),
11104 we have to build them in the literal pool so that
11105 their results are calculated correctly after relaxation.
11106 The relaxation only handles expressions that
11107 boil down to SYMBOL + OFFSET. */
11110 tinsn_has_complex_operands (const TInsn
*insn
)
11113 int n
= insn
->ntok
;
11114 assert (insn
->insn_type
== ITYPE_INSN
);
11115 for (i
= 0; i
< n
; ++i
)
11117 switch (insn
->tok
[i
].X_op
)
11133 /* Convert the constant operands in the tinsn to insnbuf.
11134 Return TRUE if there is a symbol in the immediate field.
11136 Before this is called,
11137 1) the number of operands are correct
11138 2) the tinsn is a ITYPE_INSN
11139 3) ONLY the relaxable_ is built
11140 4) All operands are O_constant, O_symbol. All constants fit
11141 The return value tells whether there are any remaining O_symbols. */
11144 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11146 static xtensa_insnbuf slotbuf
= 0;
11147 xtensa_isa isa
= xtensa_default_isa
;
11148 xtensa_opcode opcode
= tinsn
->opcode
;
11149 xtensa_format fmt
= xg_get_single_format (opcode
);
11150 bfd_boolean has_fixup
= FALSE
;
11151 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11158 slotbuf
= xtensa_insnbuf_alloc (isa
);
11160 assert (tinsn
->insn_type
== ITYPE_INSN
);
11161 if (noperands
!= tinsn
->ntok
)
11162 as_fatal (_("operand number mismatch"));
11164 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11165 as_fatal (_("cannot encode opcode"));
11167 for (i
= 0; i
< noperands
; ++i
)
11169 expressionS
*expr
= &tinsn
->tok
[i
];
11170 switch (expr
->X_op
)
11173 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11175 /* The register number has already been checked in
11176 expression_maybe_register, so we don't need to check here. */
11177 opnd_value
= expr
->X_add_number
;
11178 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11179 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11180 slotbuf
, opnd_value
);
11184 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11186 as_where (&file_name
, &line
);
11187 /* It is a constant and we called this function,
11188 then we have to try to fit it. */
11189 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11190 expr
->X_add_number
, file_name
, line
);
11199 xtensa_format_encode (isa
, fmt
, insnbuf
);
11200 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11206 /* Convert the constant operands in the tinsn to slotbuf.
11207 Return TRUE if there is a symbol in the immediate field.
11208 (Eventually this should replace tinsn_to_insnbuf.) */
11210 /* Before this is called,
11211 1) the number of operands are correct
11212 2) the tinsn is a ITYPE_INSN
11213 3) ONLY the relaxable_ is built
11214 4) All operands are
11215 O_constant, O_symbol
11218 The return value tells whether there are any remaining O_symbols. */
11221 tinsn_to_slotbuf (xtensa_format fmt
,
11224 xtensa_insnbuf slotbuf
)
11226 xtensa_isa isa
= xtensa_default_isa
;
11227 xtensa_opcode opcode
= tinsn
->opcode
;
11228 bfd_boolean has_fixup
= FALSE
;
11229 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11232 *((int *) &slotbuf
[0]) = 0;
11233 *((int *) &slotbuf
[1]) = 0;
11234 assert (tinsn
->insn_type
== ITYPE_INSN
);
11235 if (noperands
!= tinsn
->ntok
)
11236 as_fatal (_("operand number mismatch"));
11238 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11240 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11241 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11245 for (i
= 0; i
< noperands
; i
++)
11247 expressionS
*expr
= &tinsn
->tok
[i
];
11253 switch (expr
->X_op
)
11256 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11258 /* The register number has already been checked in
11259 expression_maybe_register, so we don't need to check here. */
11260 opnd_value
= expr
->X_add_number
;
11261 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11262 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11265 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11269 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11271 as_where (&file_name
, &line
);
11272 /* It is a constant and we called this function
11273 then we have to try to fit it. */
11274 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11275 expr
->X_add_number
, file_name
, line
);
11288 /* Check the instruction arguments. Return TRUE on failure. */
11291 tinsn_check_arguments (const TInsn
*insn
)
11293 xtensa_isa isa
= xtensa_default_isa
;
11294 xtensa_opcode opcode
= insn
->opcode
;
11296 if (opcode
== XTENSA_UNDEFINED
)
11298 as_bad (_("invalid opcode"));
11302 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11304 as_bad (_("too few operands"));
11308 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11310 as_bad (_("too many operands"));
11317 /* Load an instruction from its encoded form. */
11320 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11324 xg_init_vinsn (&vinsn
);
11325 vinsn_from_chars (&vinsn
, f
);
11327 *tinsn
= vinsn
.slots
[slot
];
11328 xg_free_vinsn (&vinsn
);
11333 tinsn_from_insnbuf (TInsn
*tinsn
,
11334 xtensa_insnbuf slotbuf
,
11339 xtensa_isa isa
= xtensa_default_isa
;
11341 /* Find the immed. */
11342 tinsn_init (tinsn
);
11343 tinsn
->insn_type
= ITYPE_INSN
;
11344 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11345 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11346 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11347 for (i
= 0; i
< tinsn
->ntok
; i
++)
11349 set_expr_const (&tinsn
->tok
[i
],
11350 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11351 tinsn
->opcode
, i
));
11356 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11359 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11361 xtensa_opcode opcode
= tinsn
->opcode
;
11364 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11366 opnum
= get_relaxable_immed (opcode
);
11367 assert (opnum
>= 0);
11368 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11370 set_expr_symbol_offset_diff
11371 (&tinsn
->tok
[opnum
],
11372 fragP
->tc_frag_data
.slot_symbols
[slot
],
11373 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11374 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11378 set_expr_symbol_offset
11379 (&tinsn
->tok
[opnum
],
11380 fragP
->tc_frag_data
.slot_symbols
[slot
],
11381 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11388 get_num_stack_text_bytes (IStack
*istack
)
11391 int text_bytes
= 0;
11393 for (i
= 0; i
< istack
->ninsn
; i
++)
11395 TInsn
*tinsn
= &istack
->insn
[i
];
11396 if (tinsn
->insn_type
== ITYPE_INSN
)
11397 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11404 get_num_stack_literal_bytes (IStack
*istack
)
11409 for (i
= 0; i
< istack
->ninsn
; i
++)
11411 TInsn
*tinsn
= &istack
->insn
[i
];
11412 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11419 /* vliw_insn functions. */
11422 xg_init_vinsn (vliw_insn
*v
)
11425 xtensa_isa isa
= xtensa_default_isa
;
11427 xg_clear_vinsn (v
);
11429 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11430 if (v
->insnbuf
== NULL
)
11431 as_fatal (_("out of memory"));
11433 for (i
= 0; i
< MAX_SLOTS
; i
++)
11435 tinsn_init (&v
->slots
[i
]);
11436 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11437 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11438 if (v
->slotbuf
[i
] == NULL
)
11439 as_fatal (_("out of memory"));
11445 xg_clear_vinsn (vliw_insn
*v
)
11448 v
->format
= XTENSA_UNDEFINED
;
11450 v
->inside_bundle
= FALSE
;
11452 if (xt_saved_debug_type
!= DEBUG_NONE
)
11453 debug_type
= xt_saved_debug_type
;
11455 for (i
= 0; i
< MAX_SLOTS
; i
++)
11457 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11458 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11464 vinsn_has_specific_opcodes (vliw_insn
*v
)
11468 for (i
= 0; i
< v
->num_slots
; i
++)
11470 if (v
->slots
[i
].is_specific_opcode
)
11478 xg_free_vinsn (vliw_insn
*v
)
11481 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11482 for (i
= 0; i
< MAX_SLOTS
; i
++)
11483 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11487 /* Before this is called, we should have
11488 filled out the following fields:
11490 1) the number of operands for each opcode are correct
11491 2) the tinsn in the slots are ITYPE_INSN
11492 3) ONLY the relaxable_ is built
11493 4) All operands are
11494 O_constant, O_symbol
11497 The return value tells whether there are any remaining O_symbols. */
11500 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11503 bfd_boolean record_fixup
)
11505 xtensa_isa isa
= xtensa_default_isa
;
11506 xtensa_format fmt
= vinsn
->format
;
11507 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11509 bfd_boolean has_fixup
= FALSE
;
11511 xtensa_format_encode (isa
, fmt
, insnbuf
);
11513 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11515 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11516 bfd_boolean tinsn_has_fixup
=
11517 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11518 vinsn
->slotbuf
[slot
]);
11520 xtensa_format_set_slot (isa
, fmt
, slot
,
11521 insnbuf
, vinsn
->slotbuf
[slot
]);
11522 /* tinsn_has_fixup tracks if there is a fixup at all.
11523 record_fixup controls globally. I.E., we use this
11524 function from several places, some of which are after
11525 fixups have already been recorded. Finally,
11526 tinsn->record_fixup controls based on the individual ops,
11527 which may or may not need it based on the relaxation
11529 if (tinsn_has_fixup
&& record_fixup
)
11532 xtensa_opcode opcode
= tinsn
->opcode
;
11533 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11536 for (i
= 0; i
< noperands
; i
++)
11538 expressionS
* expr
= &tinsn
->tok
[i
];
11539 switch (expr
->X_op
)
11544 if (get_relaxable_immed (opcode
) == i
)
11546 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11548 if (!xg_add_opcode_fix
11549 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11550 frag_offset
- fragP
->fr_literal
))
11551 as_bad (_("instruction with constant operands does not fit"));
11555 tinsn
->symbol
= expr
->X_add_symbol
;
11556 tinsn
->offset
= expr
->X_add_number
;
11560 as_bad (_("invalid operand %d on '%s'"),
11561 i
, xtensa_opcode_name (isa
, opcode
));
11569 if (get_relaxable_immed (opcode
) == i
)
11571 if (tinsn
->record_fix
)
11572 as_bad (_("invalid subtract operand"));
11575 tinsn
->symbol
= expr
->X_add_symbol
;
11576 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11577 tinsn
->offset
= expr
->X_add_number
;
11581 as_bad (_("invalid operand %d on '%s'"),
11582 i
, xtensa_opcode_name (isa
, opcode
));
11586 as_bad (_("invalid expression for operand %d on '%s'"),
11587 i
, xtensa_opcode_name (isa
, opcode
));
11599 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11601 static xtensa_insnbuf insnbuf
= NULL
;
11602 static xtensa_insnbuf slotbuf
= NULL
;
11605 xtensa_isa isa
= xtensa_default_isa
;
11609 insnbuf
= xtensa_insnbuf_alloc (isa
);
11610 slotbuf
= xtensa_insnbuf_alloc (isa
);
11613 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11614 fmt
= xtensa_format_decode (isa
, insnbuf
);
11615 if (fmt
== XTENSA_UNDEFINED
)
11616 as_fatal (_("cannot decode instruction format"));
11617 vinsn
->format
= fmt
;
11618 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11620 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11622 TInsn
*tinsn
= &vinsn
->slots
[i
];
11623 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11624 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11629 /* Expression utilities. */
11631 /* Return TRUE if the expression is an integer constant. */
11634 expr_is_const (const expressionS
*s
)
11636 return (s
->X_op
== O_constant
);
11640 /* Get the expression constant.
11641 Calling this is illegal if expr_is_const () returns TRUE. */
11644 get_expr_const (const expressionS
*s
)
11646 assert (expr_is_const (s
));
11647 return s
->X_add_number
;
11651 /* Set the expression to a constant value. */
11654 set_expr_const (expressionS
*s
, offsetT val
)
11656 s
->X_op
= O_constant
;
11657 s
->X_add_number
= val
;
11658 s
->X_add_symbol
= NULL
;
11659 s
->X_op_symbol
= NULL
;
11664 expr_is_register (const expressionS
*s
)
11666 return (s
->X_op
== O_register
);
11670 /* Get the expression constant.
11671 Calling this is illegal if expr_is_const () returns TRUE. */
11674 get_expr_register (const expressionS
*s
)
11676 assert (expr_is_register (s
));
11677 return s
->X_add_number
;
11681 /* Set the expression to a symbol + constant offset. */
11684 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11686 s
->X_op
= O_symbol
;
11687 s
->X_add_symbol
= sym
;
11688 s
->X_op_symbol
= NULL
; /* unused */
11689 s
->X_add_number
= offset
;
11693 /* Set the expression to symbol - minus_sym + offset. */
11696 set_expr_symbol_offset_diff (expressionS
*s
,
11698 symbolS
*minus_sym
,
11701 s
->X_op
= O_subtract
;
11702 s
->X_add_symbol
= sym
;
11703 s
->X_op_symbol
= minus_sym
; /* unused */
11704 s
->X_add_number
= offset
;
11708 /* Return TRUE if the two expressions are equal. */
11711 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11713 if (s1
->X_op
!= s2
->X_op
)
11715 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11717 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11719 if (s1
->X_add_number
!= s2
->X_add_number
)
11726 copy_expr (expressionS
*dst
, const expressionS
*src
)
11728 memcpy (dst
, src
, sizeof (expressionS
));
11732 /* Support for the "--rename-section" option. */
11734 struct rename_section_struct
11738 struct rename_section_struct
*next
;
11741 static struct rename_section_struct
*section_rename
;
11744 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11745 entries to the section_rename list. Note: Specifying multiple
11746 renamings separated by colons is not documented and is retained only
11747 for backward compatibility. */
11750 build_section_rename (const char *arg
)
11752 struct rename_section_struct
*r
;
11753 char *this_arg
= NULL
;
11754 char *next_arg
= NULL
;
11756 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11758 char *old_name
, *new_name
;
11762 next_arg
= strchr (this_arg
, ':');
11770 old_name
= this_arg
;
11771 new_name
= strchr (this_arg
, '=');
11773 if (*old_name
== '\0')
11775 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11778 if (!new_name
|| new_name
[1] == '\0')
11780 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11787 /* Check for invalid section renaming. */
11788 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11790 if (strcmp (r
->old_name
, old_name
) == 0)
11791 as_bad (_("section %s renamed multiple times"), old_name
);
11792 if (strcmp (r
->new_name
, new_name
) == 0)
11793 as_bad (_("multiple sections remapped to output section %s"),
11798 r
= (struct rename_section_struct
*)
11799 xmalloc (sizeof (struct rename_section_struct
));
11800 r
->old_name
= xstrdup (old_name
);
11801 r
->new_name
= xstrdup (new_name
);
11802 r
->next
= section_rename
;
11803 section_rename
= r
;
11809 xtensa_section_rename (char *name
)
11811 struct rename_section_struct
*r
= section_rename
;
11813 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11815 if (strcmp (r
->old_name
, name
) == 0)
11816 return r
->new_name
;