2002-10-02 Nathanael Nerode <neroden@gcc.gnu.org>
[binutils.git] / gas / config / tc-sparc.c
blob1a24c2b127241b9a7437c968fd8712d2db5137f8
1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <stdio.h>
24 #include "as.h"
25 #include "safe-ctype.h"
26 #include "subsegs.h"
28 #include "opcode/sparc.h"
30 #ifdef OBJ_ELF
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
33 #endif
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
41 static struct sparc_arch *lookup_arch PARAMS ((char *));
42 static void init_default_arch PARAMS ((void));
43 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
44 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
45 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
46 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
47 static int sparc_ffs PARAMS ((unsigned int));
48 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
49 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
50 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
51 static bfd_vma BSR PARAMS ((bfd_vma, int));
52 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
53 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
54 static int parse_const_expr_arg PARAMS ((char **, int *));
55 static int get_expression PARAMS ((char *str));
57 /* Default architecture. */
58 /* ??? The default value should be V8, but sparclite support was added
59 by making it the default. GCC now passes -Asparclite, so maybe sometime in
60 the future we can set this to V8. */
61 #ifndef DEFAULT_ARCH
62 #define DEFAULT_ARCH "sparclite"
63 #endif
64 static char *default_arch = DEFAULT_ARCH;
66 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
67 have been set. */
68 static int default_init_p;
70 /* Current architecture. We don't bump up unless necessary. */
71 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
73 /* The maximum architecture level we can bump up to.
74 In a 32 bit environment, don't allow bumping up to v9 by default.
75 The native assembler works this way. The user is required to pass
76 an explicit argument before we'll create v9 object files. However, if
77 we don't see any v9 insns, a v8plus object file is not created. */
78 static enum sparc_opcode_arch_val max_architecture;
80 /* Either 32 or 64, selects file format. */
81 static int sparc_arch_size;
82 /* Initial (default) value, recorded separately in case a user option
83 changes the value before md_show_usage is called. */
84 static int default_arch_size;
86 #ifdef OBJ_ELF
87 /* The currently selected v9 memory model. Currently only used for
88 ELF. */
89 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
90 #endif
92 static int architecture_requested;
93 static int warn_on_bump;
95 /* If warn_on_bump and the needed architecture is higher than this
96 architecture, issue a warning. */
97 static enum sparc_opcode_arch_val warn_after_architecture;
99 /* Non-zero if as should generate error if an undeclared g[23] register
100 has been used in -64. */
101 static int no_undeclared_regs;
103 /* Non-zero if we should try to relax jumps and calls. */
104 static int sparc_relax;
106 /* Non-zero if we are generating PIC code. */
107 int sparc_pic_code;
109 /* Non-zero if we should give an error when misaligned data is seen. */
110 static int enforce_aligned_data;
112 extern int target_big_endian;
114 static int target_little_endian_data;
116 /* Symbols for global registers on v9. */
117 static symbolS *globals[8];
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127 #endif
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control *op_hash;
132 static int log2 PARAMS ((int));
133 static void s_data1 PARAMS ((void));
134 static void s_seg PARAMS ((int));
135 static void s_proc PARAMS ((int));
136 static void s_reserve PARAMS ((int));
137 static void s_common PARAMS ((int));
138 static void s_empty PARAMS ((int));
139 static void s_uacons PARAMS ((int));
140 static void s_ncons PARAMS ((int));
141 static void s_register PARAMS ((int));
143 const pseudo_typeS md_pseudo_table[] =
145 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
146 {"common", s_common, 0},
147 {"empty", s_empty, 0},
148 {"global", s_globl, 0},
149 {"half", cons, 2},
150 {"nword", s_ncons, 0},
151 {"optim", s_ignore, 0},
152 {"proc", s_proc, 0},
153 {"reserve", s_reserve, 0},
154 {"seg", s_seg, 0},
155 {"skip", s_space, 0},
156 {"word", cons, 4},
157 {"xword", cons, 8},
158 {"uahalf", s_uacons, 2},
159 {"uaword", s_uacons, 4},
160 {"uaxword", s_uacons, 8},
161 #ifdef OBJ_ELF
162 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
163 {"loc", dwarf2_directive_loc, 0},
164 /* These are specific to sparc/svr4. */
165 {"2byte", s_uacons, 2},
166 {"4byte", s_uacons, 4},
167 {"8byte", s_uacons, 8},
168 {"register", s_register, 0},
169 #endif
170 {NULL, 0, 0},
173 /* Size of relocation record. */
174 const int md_reloc_size = 12;
176 /* This array holds the chars that always start a comment. If the
177 pre-processor is disabled, these aren't very useful. */
178 const char comment_chars[] = "!"; /* JF removed '|' from
179 comment_chars. */
181 /* This array holds the chars that only start a comment at the beginning of
182 a line. If the line seems to have the form '# 123 filename'
183 .line and .file directives will appear in the pre-processed output. */
184 /* Note that input_file.c hand checks for '#' at the beginning of the
185 first line of the input file. This is because the compiler outputs
186 #NO_APP at the beginning of its output. */
187 /* Also note that comments started like this one will always
188 work if '/' isn't otherwise defined. */
189 const char line_comment_chars[] = "#";
191 const char line_separator_chars[] = ";";
193 /* Chars that can be used to separate mant from exp in floating point
194 nums. */
195 const char EXP_CHARS[] = "eE";
197 /* Chars that mean this number is a floating point constant.
198 As in 0f12.456
199 or 0d1.2345e12 */
200 const char FLT_CHARS[] = "rRsSfFdDxXpP";
202 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
203 changed in read.c. Ideally it shouldn't have to know about it at all,
204 but nothing is ideal around here. */
206 #define isoctal(c) ((unsigned) ((c) - '0') < '8')
208 struct sparc_it
210 char *error;
211 unsigned long opcode;
212 struct nlist *nlistp;
213 expressionS exp;
214 expressionS exp2;
215 int pcrel;
216 bfd_reloc_code_real_type reloc;
219 struct sparc_it the_insn, set_insn;
221 static void output_insn
222 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
224 /* Table of arguments to -A.
225 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
226 for this use. That table is for opcodes only. This table is for opcodes
227 and file formats. */
229 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
230 v8plusa, v9, v9a, v9b, v9_64};
232 static struct sparc_arch {
233 char *name;
234 char *opcode_arch;
235 enum sparc_arch_types arch_type;
236 /* Default word size, as specified during configuration.
237 A value of zero means can't be used to specify default architecture. */
238 int default_arch_size;
239 /* Allowable arg to -A? */
240 int user_option_p;
241 } sparc_arch_table[] = {
242 { "v6", "v6", v6, 0, 1 },
243 { "v7", "v7", v7, 0, 1 },
244 { "v8", "v8", v8, 32, 1 },
245 { "sparclet", "sparclet", sparclet, 32, 1 },
246 { "sparclite", "sparclite", sparclite, 32, 1 },
247 { "sparc86x", "sparclite", sparc86x, 32, 1 },
248 { "v8plus", "v9", v9, 0, 1 },
249 { "v8plusa", "v9a", v9, 0, 1 },
250 { "v8plusb", "v9b", v9, 0, 1 },
251 { "v9", "v9", v9, 0, 1 },
252 { "v9a", "v9a", v9, 0, 1 },
253 { "v9b", "v9b", v9, 0, 1 },
254 /* This exists to allow configure.in/Makefile.in to pass one
255 value to specify both the default machine and default word size. */
256 { "v9-64", "v9", v9, 64, 0 },
257 { NULL, NULL, v8, 0, 0 }
260 /* Variant of default_arch */
261 static enum sparc_arch_types default_arch_type;
263 static struct sparc_arch *
264 lookup_arch (name)
265 char *name;
267 struct sparc_arch *sa;
269 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
270 if (strcmp (sa->name, name) == 0)
271 break;
272 if (sa->name == NULL)
273 return NULL;
274 return sa;
277 /* Initialize the default opcode arch and word size from the default
278 architecture name. */
280 static void
281 init_default_arch ()
283 struct sparc_arch *sa = lookup_arch (default_arch);
285 if (sa == NULL
286 || sa->default_arch_size == 0)
287 as_fatal (_("Invalid default architecture, broken assembler."));
289 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
290 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
291 as_fatal (_("Bad opcode table, broken assembler."));
292 default_arch_size = sparc_arch_size = sa->default_arch_size;
293 default_init_p = 1;
294 default_arch_type = sa->arch_type;
297 /* Called by TARGET_FORMAT. */
299 const char *
300 sparc_target_format ()
302 /* We don't get a chance to initialize anything before we're called,
303 so handle that now. */
304 if (! default_init_p)
305 init_default_arch ();
307 #ifdef OBJ_AOUT
308 #ifdef TE_NetBSD
309 return "a.out-sparc-netbsd";
310 #else
311 #ifdef TE_SPARCAOUT
312 if (target_big_endian)
313 return "a.out-sunos-big";
314 else if (default_arch_type == sparc86x && target_little_endian_data)
315 return "a.out-sunos-big";
316 else
317 return "a.out-sparc-little";
318 #else
319 return "a.out-sunos-big";
320 #endif
321 #endif
322 #endif
324 #ifdef OBJ_BOUT
325 return "b.out.big";
326 #endif
328 #ifdef OBJ_COFF
329 #ifdef TE_LYNX
330 return "coff-sparc-lynx";
331 #else
332 return "coff-sparc";
333 #endif
334 #endif
336 #ifdef OBJ_ELF
337 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
338 #endif
340 abort ();
343 /* md_parse_option
344 * Invocation line includes a switch not recognized by the base assembler.
345 * See if it's a processor-specific option. These are:
347 * -bump
348 * Warn on architecture bumps. See also -A.
350 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
351 * Standard 32 bit architectures.
352 * -Av9, -Av9a, -Av9b
353 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
354 * This used to only mean 64 bits, but properly specifying it
355 * complicated gcc's ASM_SPECs, so now opcode selection is
356 * specified orthogonally to word size (except when specifying
357 * the default, but that is an internal implementation detail).
358 * -Av8plus, -Av8plusa, -Av8plusb
359 * Same as -Av9{,a,b}.
360 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
361 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
362 * assembler.
363 * -xarch=v9, -xarch=v9a, -xarch=v9b
364 * Same as -Av9{,a,b} -64, for compatibility with Sun's
365 * assembler.
367 * Select the architecture and possibly the file format.
368 * Instructions or features not supported by the selected
369 * architecture cause fatal errors.
371 * The default is to start at v6, and bump the architecture up
372 * whenever an instruction is seen at a higher level. In 32 bit
373 * environments, v9 is not bumped up to, the user must pass
374 * -Av8plus{,a,b}.
376 * If -bump is specified, a warning is printing when bumping to
377 * higher levels.
379 * If an architecture is specified, all instructions must match
380 * that architecture. Any higher level instructions are flagged
381 * as errors. Note that in the 32 bit environment specifying
382 * -Av8plus does not automatically create a v8plus object file, a
383 * v9 insn must be seen.
385 * If both an architecture and -bump are specified, the
386 * architecture starts at the specified level, but bumps are
387 * warnings. Note that we can't set `current_architecture' to
388 * the requested level in this case: in the 32 bit environment,
389 * we still must avoid creating v8plus object files unless v9
390 * insns are seen.
392 * Note:
393 * Bumping between incompatible architectures is always an
394 * error. For example, from sparclite to v9.
397 #ifdef OBJ_ELF
398 const char *md_shortopts = "A:K:VQ:sq";
399 #else
400 #ifdef OBJ_AOUT
401 const char *md_shortopts = "A:k";
402 #else
403 const char *md_shortopts = "A:";
404 #endif
405 #endif
406 struct option md_longopts[] = {
407 #define OPTION_BUMP (OPTION_MD_BASE)
408 {"bump", no_argument, NULL, OPTION_BUMP},
409 #define OPTION_SPARC (OPTION_MD_BASE + 1)
410 {"sparc", no_argument, NULL, OPTION_SPARC},
411 #define OPTION_XARCH (OPTION_MD_BASE + 2)
412 {"xarch", required_argument, NULL, OPTION_XARCH},
413 #ifdef OBJ_ELF
414 #define OPTION_32 (OPTION_MD_BASE + 3)
415 {"32", no_argument, NULL, OPTION_32},
416 #define OPTION_64 (OPTION_MD_BASE + 4)
417 {"64", no_argument, NULL, OPTION_64},
418 #define OPTION_TSO (OPTION_MD_BASE + 5)
419 {"TSO", no_argument, NULL, OPTION_TSO},
420 #define OPTION_PSO (OPTION_MD_BASE + 6)
421 {"PSO", no_argument, NULL, OPTION_PSO},
422 #define OPTION_RMO (OPTION_MD_BASE + 7)
423 {"RMO", no_argument, NULL, OPTION_RMO},
424 #endif
425 #ifdef SPARC_BIENDIAN
426 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
427 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
428 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
429 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
430 #endif
431 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
432 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
433 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
434 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
435 #ifdef OBJ_ELF
436 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
437 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
438 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
439 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
440 #endif
441 #define OPTION_RELAX (OPTION_MD_BASE + 14)
442 {"relax", no_argument, NULL, OPTION_RELAX},
443 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
444 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
445 {NULL, no_argument, NULL, 0}
448 size_t md_longopts_size = sizeof (md_longopts);
451 md_parse_option (c, arg)
452 int c;
453 char *arg;
455 /* We don't get a chance to initialize anything before we're called,
456 so handle that now. */
457 if (! default_init_p)
458 init_default_arch ();
460 switch (c)
462 case OPTION_BUMP:
463 warn_on_bump = 1;
464 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
465 break;
467 case OPTION_XARCH:
468 #ifdef OBJ_ELF
469 if (strncmp (arg, "v9", 2) != 0)
470 md_parse_option (OPTION_32, NULL);
471 else
472 md_parse_option (OPTION_64, NULL);
473 #endif
474 /* Fall through. */
476 case 'A':
478 struct sparc_arch *sa;
479 enum sparc_opcode_arch_val opcode_arch;
481 sa = lookup_arch (arg);
482 if (sa == NULL
483 || ! sa->user_option_p)
485 if (c == OPTION_XARCH)
486 as_bad (_("invalid architecture -xarch=%s"), arg);
487 else
488 as_bad (_("invalid architecture -A%s"), arg);
489 return 0;
492 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
493 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
494 as_fatal (_("Bad opcode table, broken assembler."));
496 max_architecture = opcode_arch;
497 architecture_requested = 1;
499 break;
501 case OPTION_SPARC:
502 /* Ignore -sparc, used by SunOS make default .s.o rule. */
503 break;
505 case OPTION_ENFORCE_ALIGNED_DATA:
506 enforce_aligned_data = 1;
507 break;
509 #ifdef SPARC_BIENDIAN
510 case OPTION_LITTLE_ENDIAN:
511 target_big_endian = 0;
512 if (default_arch_type != sparclet)
513 as_fatal ("This target does not support -EL");
514 break;
515 case OPTION_LITTLE_ENDIAN_DATA:
516 target_little_endian_data = 1;
517 target_big_endian = 0;
518 if (default_arch_type != sparc86x
519 && default_arch_type != v9)
520 as_fatal ("This target does not support --little-endian-data");
521 break;
522 case OPTION_BIG_ENDIAN:
523 target_big_endian = 1;
524 break;
525 #endif
527 #ifdef OBJ_AOUT
528 case 'k':
529 sparc_pic_code = 1;
530 break;
531 #endif
533 #ifdef OBJ_ELF
534 case OPTION_32:
535 case OPTION_64:
537 const char **list, **l;
539 sparc_arch_size = c == OPTION_32 ? 32 : 64;
540 list = bfd_target_list ();
541 for (l = list; *l != NULL; l++)
543 if (sparc_arch_size == 32)
545 if (strcmp (*l, "elf32-sparc") == 0)
546 break;
548 else
550 if (strcmp (*l, "elf64-sparc") == 0)
551 break;
554 if (*l == NULL)
555 as_fatal (_("No compiled in support for %d bit object file format"),
556 sparc_arch_size);
557 free (list);
559 break;
561 case OPTION_TSO:
562 sparc_memory_model = MM_TSO;
563 break;
565 case OPTION_PSO:
566 sparc_memory_model = MM_PSO;
567 break;
569 case OPTION_RMO:
570 sparc_memory_model = MM_RMO;
571 break;
573 case 'V':
574 print_version_id ();
575 break;
577 case 'Q':
578 /* Qy - do emit .comment
579 Qn - do not emit .comment. */
580 break;
582 case 's':
583 /* Use .stab instead of .stab.excl. */
584 break;
586 case 'q':
587 /* quick -- Native assembler does fewer checks. */
588 break;
590 case 'K':
591 if (strcmp (arg, "PIC") != 0)
592 as_warn (_("Unrecognized option following -K"));
593 else
594 sparc_pic_code = 1;
595 break;
597 case OPTION_NO_UNDECLARED_REGS:
598 no_undeclared_regs = 1;
599 break;
601 case OPTION_UNDECLARED_REGS:
602 no_undeclared_regs = 0;
603 break;
604 #endif
606 case OPTION_RELAX:
607 sparc_relax = 1;
608 break;
610 case OPTION_NO_RELAX:
611 sparc_relax = 0;
612 break;
614 default:
615 return 0;
618 return 1;
621 void
622 md_show_usage (stream)
623 FILE *stream;
625 const struct sparc_arch *arch;
626 int column;
628 /* We don't get a chance to initialize anything before we're called,
629 so handle that now. */
630 if (! default_init_p)
631 init_default_arch ();
633 fprintf (stream, _("SPARC options:\n"));
634 column = 0;
635 for (arch = &sparc_arch_table[0]; arch->name; arch++)
637 if (!arch->user_option_p)
638 continue;
639 if (arch != &sparc_arch_table[0])
640 fprintf (stream, " | ");
641 if (column + strlen (arch->name) > 70)
643 column = 0;
644 fputc ('\n', stream);
646 column += 5 + 2 + strlen (arch->name);
647 fprintf (stream, "-A%s", arch->name);
649 for (arch = &sparc_arch_table[0]; arch->name; arch++)
651 if (!arch->user_option_p)
652 continue;
653 fprintf (stream, " | ");
654 if (column + strlen (arch->name) > 65)
656 column = 0;
657 fputc ('\n', stream);
659 column += 5 + 7 + strlen (arch->name);
660 fprintf (stream, "-xarch=%s", arch->name);
662 fprintf (stream, _("\n\
663 specify variant of SPARC architecture\n\
664 -bump warn when assembler switches architectures\n\
665 -sparc ignored\n\
666 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
667 -relax relax jumps and branches (default)\n\
668 -no-relax avoid changing any jumps and branches\n"));
669 #ifdef OBJ_AOUT
670 fprintf (stream, _("\
671 -k generate PIC\n"));
672 #endif
673 #ifdef OBJ_ELF
674 fprintf (stream, _("\
675 -32 create 32 bit object file\n\
676 -64 create 64 bit object file\n"));
677 fprintf (stream, _("\
678 [default is %d]\n"), default_arch_size);
679 fprintf (stream, _("\
680 -TSO use Total Store Ordering\n\
681 -PSO use Partial Store Ordering\n\
682 -RMO use Relaxed Memory Ordering\n"));
683 fprintf (stream, _("\
684 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
685 fprintf (stream, _("\
686 -KPIC generate PIC\n\
687 -V print assembler version number\n\
688 -undeclared-regs ignore application global register usage without\n\
689 appropriate .register directive (default)\n\
690 -no-undeclared-regs force error on application global register usage\n\
691 without appropriate .register directive\n\
692 -q ignored\n\
693 -Qy, -Qn ignored\n\
694 -s ignored\n"));
695 #endif
696 #ifdef SPARC_BIENDIAN
697 fprintf (stream, _("\
698 -EL generate code for a little endian machine\n\
699 -EB generate code for a big endian machine\n\
700 --little-endian-data generate code for a machine having big endian\n\
701 instructions and little endian data.\n"));
702 #endif
705 /* Native operand size opcode translation. */
706 struct
708 char *name;
709 char *name32;
710 char *name64;
711 } native_op_table[] =
713 {"ldn", "ld", "ldx"},
714 {"ldna", "lda", "ldxa"},
715 {"stn", "st", "stx"},
716 {"stna", "sta", "stxa"},
717 {"slln", "sll", "sllx"},
718 {"srln", "srl", "srlx"},
719 {"sran", "sra", "srax"},
720 {"casn", "cas", "casx"},
721 {"casna", "casa", "casxa"},
722 {"clrn", "clr", "clrx"},
723 {NULL, NULL, NULL},
726 /* sparc64 priviledged registers. */
728 struct priv_reg_entry
730 char *name;
731 int regnum;
734 struct priv_reg_entry priv_reg_table[] =
736 {"tpc", 0},
737 {"tnpc", 1},
738 {"tstate", 2},
739 {"tt", 3},
740 {"tick", 4},
741 {"tba", 5},
742 {"pstate", 6},
743 {"tl", 7},
744 {"pil", 8},
745 {"cwp", 9},
746 {"cansave", 10},
747 {"canrestore", 11},
748 {"cleanwin", 12},
749 {"otherwin", 13},
750 {"wstate", 14},
751 {"fq", 15},
752 {"ver", 31},
753 {"", -1}, /* End marker. */
756 /* v9a specific asrs. */
758 struct priv_reg_entry v9a_asr_table[] =
760 {"tick_cmpr", 23},
761 {"sys_tick_cmpr", 25},
762 {"sys_tick", 24},
763 {"softint", 22},
764 {"set_softint", 20},
765 {"pic", 17},
766 {"pcr", 16},
767 {"gsr", 19},
768 {"dcr", 18},
769 {"clear_softint", 21},
770 {"", -1}, /* End marker. */
773 static int
774 cmp_reg_entry (parg, qarg)
775 const PTR parg;
776 const PTR qarg;
778 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
779 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
781 return strcmp (q->name, p->name);
784 /* This function is called once, at assembler startup time. It should
785 set up all the tables, etc. that the MD part of the assembler will
786 need. */
788 void
789 md_begin ()
791 register const char *retval = NULL;
792 int lose = 0;
793 register unsigned int i = 0;
795 /* We don't get a chance to initialize anything before md_parse_option
796 is called, and it may not be called, so handle default initialization
797 now if not already done. */
798 if (! default_init_p)
799 init_default_arch ();
801 op_hash = hash_new ();
803 while (i < (unsigned int) sparc_num_opcodes)
805 const char *name = sparc_opcodes[i].name;
806 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
807 if (retval != NULL)
809 as_bad (_("Internal error: can't hash `%s': %s\n"),
810 sparc_opcodes[i].name, retval);
811 lose = 1;
815 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
817 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
818 sparc_opcodes[i].name, sparc_opcodes[i].args);
819 lose = 1;
821 ++i;
823 while (i < (unsigned int) sparc_num_opcodes
824 && !strcmp (sparc_opcodes[i].name, name));
827 for (i = 0; native_op_table[i].name; i++)
829 const struct sparc_opcode *insn;
830 char *name = ((sparc_arch_size == 32)
831 ? native_op_table[i].name32
832 : native_op_table[i].name64);
833 insn = (struct sparc_opcode *) hash_find (op_hash, name);
834 if (insn == NULL)
836 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
837 name, native_op_table[i].name);
838 lose = 1;
840 else
842 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
843 if (retval != NULL)
845 as_bad (_("Internal error: can't hash `%s': %s\n"),
846 sparc_opcodes[i].name, retval);
847 lose = 1;
852 if (lose)
853 as_fatal (_("Broken assembler. No assembly attempted."));
855 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
856 sizeof (priv_reg_table[0]), cmp_reg_entry);
858 /* If -bump, record the architecture level at which we start issuing
859 warnings. The behaviour is different depending upon whether an
860 architecture was explicitly specified. If it wasn't, we issue warnings
861 for all upwards bumps. If it was, we don't start issuing warnings until
862 we need to bump beyond the requested architecture or when we bump between
863 conflicting architectures. */
865 if (warn_on_bump
866 && architecture_requested)
868 /* `max_architecture' records the requested architecture.
869 Issue warnings if we go above it. */
870 warn_after_architecture = max_architecture;
872 /* Find the highest architecture level that doesn't conflict with
873 the requested one. */
874 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
875 max_architecture > warn_after_architecture;
876 --max_architecture)
877 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
878 warn_after_architecture))
879 break;
883 /* Called after all assembly has been done. */
885 void
886 sparc_md_end ()
888 unsigned long mach = bfd_mach_sparc;
890 if (sparc_arch_size == 64)
891 switch (current_architecture)
893 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
894 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
895 default: mach = bfd_mach_sparc_v9; break;
897 else
898 switch (current_architecture)
900 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
901 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
902 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
903 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
904 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
905 be but for now it is (since that's the way it's always been
906 treated). */
907 default: break;
909 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
912 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
914 static INLINE int
915 in_signed_range (val, max)
916 bfd_signed_vma val, max;
918 if (max <= 0)
919 abort ();
920 /* Sign-extend the value from the architecture word size, so that
921 0xffffffff is always considered -1 on sparc32. */
922 if (sparc_arch_size == 32)
924 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
925 val = ((val & U0xffffffff) ^ sign) - sign;
927 if (val > max)
928 return 0;
929 if (val < ~max)
930 return 0;
931 return 1;
934 /* Return non-zero if VAL is in the range 0 to MAX. */
936 static INLINE int
937 in_unsigned_range (val, max)
938 bfd_vma val, max;
940 if (val > max)
941 return 0;
942 return 1;
945 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
946 (e.g. -15 to +31). */
948 static INLINE int
949 in_bitfield_range (val, max)
950 bfd_signed_vma val, max;
952 if (max <= 0)
953 abort ();
954 if (val > max)
955 return 0;
956 if (val < ~(max >> 1))
957 return 0;
958 return 1;
961 static int
962 sparc_ffs (mask)
963 unsigned int mask;
965 int i;
967 if (mask == 0)
968 return -1;
970 for (i = 0; (mask & 1) == 0; ++i)
971 mask >>= 1;
972 return i;
975 /* Implement big shift right. */
976 static bfd_vma
977 BSR (val, amount)
978 bfd_vma val;
979 int amount;
981 if (sizeof (bfd_vma) <= 4 && amount >= 32)
982 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
983 return val >> amount;
986 /* For communication between sparc_ip and get_expression. */
987 static char *expr_end;
989 /* Values for `special_case'.
990 Instructions that require wierd handling because they're longer than
991 4 bytes. */
992 #define SPECIAL_CASE_NONE 0
993 #define SPECIAL_CASE_SET 1
994 #define SPECIAL_CASE_SETSW 2
995 #define SPECIAL_CASE_SETX 3
996 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
997 #define SPECIAL_CASE_FDIV 4
999 /* Bit masks of various insns. */
1000 #define NOP_INSN 0x01000000
1001 #define OR_INSN 0x80100000
1002 #define XOR_INSN 0x80180000
1003 #define FMOVS_INSN 0x81A00020
1004 #define SETHI_INSN 0x01000000
1005 #define SLLX_INSN 0x81281000
1006 #define SRA_INSN 0x81380000
1008 /* The last instruction to be assembled. */
1009 static const struct sparc_opcode *last_insn;
1010 /* The assembled opcode of `last_insn'. */
1011 static unsigned long last_opcode;
1013 /* Handle the set and setuw synthetic instructions. */
1015 static void
1016 synthetize_setuw (insn)
1017 const struct sparc_opcode *insn;
1019 int need_hi22_p = 0;
1020 int rd = (the_insn.opcode & RD (~0)) >> 25;
1022 if (the_insn.exp.X_op == O_constant)
1024 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1026 if (sizeof (offsetT) > 4
1027 && (the_insn.exp.X_add_number < 0
1028 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1029 as_warn (_("set: number not in 0..4294967295 range"));
1031 else
1033 if (sizeof (offsetT) > 4
1034 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1035 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1036 as_warn (_("set: number not in -2147483648..4294967295 range"));
1037 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1041 /* See if operand is absolute and small; skip sethi if so. */
1042 if (the_insn.exp.X_op != O_constant
1043 || the_insn.exp.X_add_number >= (1 << 12)
1044 || the_insn.exp.X_add_number < -(1 << 12))
1046 the_insn.opcode = (SETHI_INSN | RD (rd)
1047 | ((the_insn.exp.X_add_number >> 10)
1048 & (the_insn.exp.X_op == O_constant
1049 ? 0x3fffff : 0)));
1050 the_insn.reloc = (the_insn.exp.X_op != O_constant
1051 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1052 output_insn (insn, &the_insn);
1053 need_hi22_p = 1;
1056 /* See if operand has no low-order bits; skip OR if so. */
1057 if (the_insn.exp.X_op != O_constant
1058 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1059 || ! need_hi22_p)
1061 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1062 | RD (rd) | IMMED
1063 | (the_insn.exp.X_add_number
1064 & (the_insn.exp.X_op != O_constant
1065 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1066 the_insn.reloc = (the_insn.exp.X_op != O_constant
1067 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1068 output_insn (insn, &the_insn);
1072 /* Handle the setsw synthetic instruction. */
1074 static void
1075 synthetize_setsw (insn)
1076 const struct sparc_opcode *insn;
1078 int low32, rd, opc;
1080 rd = (the_insn.opcode & RD (~0)) >> 25;
1082 if (the_insn.exp.X_op != O_constant)
1084 synthetize_setuw (insn);
1086 /* Need to sign extend it. */
1087 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1088 the_insn.reloc = BFD_RELOC_NONE;
1089 output_insn (insn, &the_insn);
1090 return;
1093 if (sizeof (offsetT) > 4
1094 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1095 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1096 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1098 low32 = the_insn.exp.X_add_number;
1100 if (low32 >= 0)
1102 synthetize_setuw (insn);
1103 return;
1106 opc = OR_INSN;
1108 the_insn.reloc = BFD_RELOC_NONE;
1109 /* See if operand is absolute and small; skip sethi if so. */
1110 if (low32 < -(1 << 12))
1112 the_insn.opcode = (SETHI_INSN | RD (rd)
1113 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1114 output_insn (insn, &the_insn);
1115 low32 = 0x1c00 | (low32 & 0x3ff);
1116 opc = RS1 (rd) | XOR_INSN;
1119 the_insn.opcode = (opc | RD (rd) | IMMED
1120 | (low32 & 0x1fff));
1121 output_insn (insn, &the_insn);
1124 /* Handle the setsw synthetic instruction. */
1126 static void
1127 synthetize_setx (insn)
1128 const struct sparc_opcode *insn;
1130 int upper32, lower32;
1131 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1132 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1133 int upper_dstreg;
1134 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1135 int need_xor10_p = 0;
1137 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1138 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1139 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1140 #undef SIGNEXT32
1142 upper_dstreg = tmpreg;
1143 /* The tmp reg should not be the dst reg. */
1144 if (tmpreg == dstreg)
1145 as_warn (_("setx: temporary register same as destination register"));
1147 /* ??? Obviously there are other optimizations we can do
1148 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1149 doing some of these. Later. If you do change things, try to
1150 change all of this to be table driven as well. */
1151 /* What to output depends on the number if it's constant.
1152 Compute that first, then output what we've decided upon. */
1153 if (the_insn.exp.X_op != O_constant)
1155 if (sparc_arch_size == 32)
1157 /* When arch size is 32, we want setx to be equivalent
1158 to setuw for anything but constants. */
1159 the_insn.exp.X_add_number &= 0xffffffff;
1160 synthetize_setuw (insn);
1161 return;
1163 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1164 lower32 = 0;
1165 upper32 = 0;
1167 else
1169 /* Reset X_add_number, we've extracted it as upper32/lower32.
1170 Otherwise fixup_segment will complain about not being able to
1171 write an 8 byte number in a 4 byte field. */
1172 the_insn.exp.X_add_number = 0;
1174 /* Only need hh22 if `or' insn can't handle constant. */
1175 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1176 need_hh22_p = 1;
1178 /* Does bottom part (after sethi) have bits? */
1179 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1180 /* No hh22, but does upper32 still have bits we can't set
1181 from lower32? */
1182 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1183 need_hm10_p = 1;
1185 /* If the lower half is all zero, we build the upper half directly
1186 into the dst reg. */
1187 if (lower32 != 0
1188 /* Need lower half if number is zero or 0xffffffff00000000. */
1189 || (! need_hh22_p && ! need_hm10_p))
1191 /* No need for sethi if `or' insn can handle constant. */
1192 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1193 /* Note that we can't use a negative constant in the `or'
1194 insn unless the upper 32 bits are all ones. */
1195 || (lower32 < 0 && upper32 != -1)
1196 || (lower32 >= 0 && upper32 == -1))
1197 need_hi22_p = 1;
1199 if (need_hi22_p && upper32 == -1)
1200 need_xor10_p = 1;
1202 /* Does bottom part (after sethi) have bits? */
1203 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1204 /* No sethi. */
1205 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1206 /* Need `or' if we didn't set anything else. */
1207 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1208 need_lo10_p = 1;
1210 else
1211 /* Output directly to dst reg if lower 32 bits are all zero. */
1212 upper_dstreg = dstreg;
1215 if (!upper_dstreg && dstreg)
1216 as_warn (_("setx: illegal temporary register g0"));
1218 if (need_hh22_p)
1220 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1221 | ((upper32 >> 10) & 0x3fffff));
1222 the_insn.reloc = (the_insn.exp.X_op != O_constant
1223 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1224 output_insn (insn, &the_insn);
1227 if (need_hi22_p)
1229 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1230 | (((need_xor10_p ? ~lower32 : lower32)
1231 >> 10) & 0x3fffff));
1232 the_insn.reloc = (the_insn.exp.X_op != O_constant
1233 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1234 output_insn (insn, &the_insn);
1237 if (need_hm10_p)
1239 the_insn.opcode = (OR_INSN
1240 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1241 | RD (upper_dstreg)
1242 | IMMED
1243 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1244 the_insn.reloc = (the_insn.exp.X_op != O_constant
1245 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1246 output_insn (insn, &the_insn);
1249 if (need_lo10_p)
1251 /* FIXME: One nice optimization to do here is to OR the low part
1252 with the highpart if hi22 isn't needed and the low part is
1253 positive. */
1254 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1255 | RD (dstreg)
1256 | IMMED
1257 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1258 the_insn.reloc = (the_insn.exp.X_op != O_constant
1259 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1260 output_insn (insn, &the_insn);
1263 /* If we needed to build the upper part, shift it into place. */
1264 if (need_hh22_p || need_hm10_p)
1266 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1267 | IMMED | 32);
1268 the_insn.reloc = BFD_RELOC_NONE;
1269 output_insn (insn, &the_insn);
1272 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1273 if (need_xor10_p)
1275 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1276 | 0x1c00 | (lower32 & 0x3ff));
1277 the_insn.reloc = BFD_RELOC_NONE;
1278 output_insn (insn, &the_insn);
1281 /* If we needed to build both upper and lower parts, OR them together. */
1282 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1284 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1285 | RD (dstreg));
1286 the_insn.reloc = BFD_RELOC_NONE;
1287 output_insn (insn, &the_insn);
1291 /* Main entry point to assemble one instruction. */
1293 void
1294 md_assemble (str)
1295 char *str;
1297 const struct sparc_opcode *insn;
1298 int special_case;
1300 know (str);
1301 special_case = sparc_ip (str, &insn);
1303 /* We warn about attempts to put a floating point branch in a delay slot,
1304 unless the delay slot has been annulled. */
1305 if (insn != NULL
1306 && last_insn != NULL
1307 && (insn->flags & F_FBR) != 0
1308 && (last_insn->flags & F_DELAYED) != 0
1309 /* ??? This test isn't completely accurate. We assume anything with
1310 F_{UNBR,CONDBR,FBR} set is annullable. */
1311 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1312 || (last_opcode & ANNUL) == 0))
1313 as_warn (_("FP branch in delay slot"));
1315 /* SPARC before v9 requires a nop instruction between a floating
1316 point instruction and a floating point branch. We insert one
1317 automatically, with a warning. */
1318 if (max_architecture < SPARC_OPCODE_ARCH_V9
1319 && insn != NULL
1320 && last_insn != NULL
1321 && (insn->flags & F_FBR) != 0
1322 && (last_insn->flags & F_FLOAT) != 0)
1324 struct sparc_it nop_insn;
1326 nop_insn.opcode = NOP_INSN;
1327 nop_insn.reloc = BFD_RELOC_NONE;
1328 output_insn (insn, &nop_insn);
1329 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1332 switch (special_case)
1334 case SPECIAL_CASE_NONE:
1335 /* Normal insn. */
1336 output_insn (insn, &the_insn);
1337 break;
1339 case SPECIAL_CASE_SETSW:
1340 synthetize_setsw (insn);
1341 break;
1343 case SPECIAL_CASE_SET:
1344 synthetize_setuw (insn);
1345 break;
1347 case SPECIAL_CASE_SETX:
1348 synthetize_setx (insn);
1349 break;
1351 case SPECIAL_CASE_FDIV:
1353 int rd = (the_insn.opcode >> 25) & 0x1f;
1355 output_insn (insn, &the_insn);
1357 /* According to information leaked from Sun, the "fdiv" instructions
1358 on early SPARC machines would produce incorrect results sometimes.
1359 The workaround is to add an fmovs of the destination register to
1360 itself just after the instruction. This was true on machines
1361 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1362 assert (the_insn.reloc == BFD_RELOC_NONE);
1363 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1364 output_insn (insn, &the_insn);
1365 return;
1368 default:
1369 as_fatal (_("failed special case insn sanity check"));
1373 /* Subroutine of md_assemble to do the actual parsing. */
1375 static int
1376 sparc_ip (str, pinsn)
1377 char *str;
1378 const struct sparc_opcode **pinsn;
1380 char *error_message = "";
1381 char *s;
1382 const char *args;
1383 char c;
1384 const struct sparc_opcode *insn;
1385 char *argsStart;
1386 unsigned long opcode;
1387 unsigned int mask = 0;
1388 int match = 0;
1389 int comma = 0;
1390 int v9_arg_p;
1391 int special_case = SPECIAL_CASE_NONE;
1393 s = str;
1394 if (ISLOWER (*s))
1397 ++s;
1398 while (ISLOWER (*s) || ISDIGIT (*s));
1401 switch (*s)
1403 case '\0':
1404 break;
1406 case ',':
1407 comma = 1;
1408 /* Fall through. */
1410 case ' ':
1411 *s++ = '\0';
1412 break;
1414 default:
1415 as_fatal (_("Unknown opcode: `%s'"), str);
1417 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1418 *pinsn = insn;
1419 if (insn == NULL)
1421 as_bad (_("Unknown opcode: `%s'"), str);
1422 return special_case;
1424 if (comma)
1426 *--s = ',';
1429 argsStart = s;
1430 for (;;)
1432 opcode = insn->match;
1433 memset (&the_insn, '\0', sizeof (the_insn));
1434 the_insn.reloc = BFD_RELOC_NONE;
1435 v9_arg_p = 0;
1437 /* Build the opcode, checking as we go to make sure that the
1438 operands match. */
1439 for (args = insn->args;; ++args)
1441 switch (*args)
1443 case 'K':
1445 int kmask = 0;
1447 /* Parse a series of masks. */
1448 if (*s == '#')
1450 while (*s == '#')
1452 int mask;
1454 if (! parse_keyword_arg (sparc_encode_membar, &s,
1455 &mask))
1457 error_message = _(": invalid membar mask name");
1458 goto error;
1460 kmask |= mask;
1461 while (*s == ' ')
1462 ++s;
1463 if (*s == '|' || *s == '+')
1464 ++s;
1465 while (*s == ' ')
1466 ++s;
1469 else
1471 if (! parse_const_expr_arg (&s, &kmask))
1473 error_message = _(": invalid membar mask expression");
1474 goto error;
1476 if (kmask < 0 || kmask > 127)
1478 error_message = _(": invalid membar mask number");
1479 goto error;
1483 opcode |= MEMBAR (kmask);
1484 continue;
1487 case '3':
1489 int smask = 0;
1491 if (! parse_const_expr_arg (&s, &smask))
1493 error_message = _(": invalid siam mode expression");
1494 goto error;
1496 if (smask < 0 || smask > 7)
1498 error_message = _(": invalid siam mode number");
1499 goto error;
1501 opcode |= smask;
1502 continue;
1505 case '*':
1507 int fcn = 0;
1509 /* Parse a prefetch function. */
1510 if (*s == '#')
1512 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1514 error_message = _(": invalid prefetch function name");
1515 goto error;
1518 else
1520 if (! parse_const_expr_arg (&s, &fcn))
1522 error_message = _(": invalid prefetch function expression");
1523 goto error;
1525 if (fcn < 0 || fcn > 31)
1527 error_message = _(": invalid prefetch function number");
1528 goto error;
1531 opcode |= RD (fcn);
1532 continue;
1535 case '!':
1536 case '?':
1537 /* Parse a sparc64 privileged register. */
1538 if (*s == '%')
1540 struct priv_reg_entry *p = priv_reg_table;
1541 unsigned int len = 9999999; /* Init to make gcc happy. */
1543 s += 1;
1544 while (p->name[0] > s[0])
1545 p++;
1546 while (p->name[0] == s[0])
1548 len = strlen (p->name);
1549 if (strncmp (p->name, s, len) == 0)
1550 break;
1551 p++;
1553 if (p->name[0] != s[0])
1555 error_message = _(": unrecognizable privileged register");
1556 goto error;
1558 if (*args == '?')
1559 opcode |= (p->regnum << 14);
1560 else
1561 opcode |= (p->regnum << 25);
1562 s += len;
1563 continue;
1565 else
1567 error_message = _(": unrecognizable privileged register");
1568 goto error;
1571 case '_':
1572 case '/':
1573 /* Parse a v9a/v9b ancillary state register. */
1574 if (*s == '%')
1576 struct priv_reg_entry *p = v9a_asr_table;
1577 unsigned int len = 9999999; /* Init to make gcc happy. */
1579 s += 1;
1580 while (p->name[0] > s[0])
1581 p++;
1582 while (p->name[0] == s[0])
1584 len = strlen (p->name);
1585 if (strncmp (p->name, s, len) == 0)
1586 break;
1587 p++;
1589 if (p->name[0] != s[0])
1591 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1592 goto error;
1594 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1596 error_message = _(": rd on write only ancillary state register");
1597 goto error;
1599 if (p->regnum >= 24
1600 && (insn->architecture
1601 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1603 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1604 error_message = _(": unrecognizable v9a ancillary state register");
1605 goto error;
1607 if (*args == '/')
1608 opcode |= (p->regnum << 14);
1609 else
1610 opcode |= (p->regnum << 25);
1611 s += len;
1612 continue;
1614 else
1616 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1617 goto error;
1620 case 'M':
1621 case 'm':
1622 if (strncmp (s, "%asr", 4) == 0)
1624 s += 4;
1626 if (ISDIGIT (*s))
1628 long num = 0;
1630 while (ISDIGIT (*s))
1632 num = num * 10 + *s - '0';
1633 ++s;
1636 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1638 if (num < 16 || 31 < num)
1640 error_message = _(": asr number must be between 16 and 31");
1641 goto error;
1644 else
1646 if (num < 0 || 31 < num)
1648 error_message = _(": asr number must be between 0 and 31");
1649 goto error;
1653 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1654 continue;
1656 else
1658 error_message = _(": expecting %asrN");
1659 goto error;
1661 } /* if %asr */
1662 break;
1664 case 'I':
1665 the_insn.reloc = BFD_RELOC_SPARC_11;
1666 goto immediate;
1668 case 'j':
1669 the_insn.reloc = BFD_RELOC_SPARC_10;
1670 goto immediate;
1672 case 'X':
1673 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1674 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1675 the_insn.reloc = BFD_RELOC_SPARC_5;
1676 else
1677 the_insn.reloc = BFD_RELOC_SPARC13;
1678 /* These fields are unsigned, but for upward compatibility,
1679 allow negative values as well. */
1680 goto immediate;
1682 case 'Y':
1683 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1684 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1685 the_insn.reloc = BFD_RELOC_SPARC_6;
1686 else
1687 the_insn.reloc = BFD_RELOC_SPARC13;
1688 /* These fields are unsigned, but for upward compatibility,
1689 allow negative values as well. */
1690 goto immediate;
1692 case 'k':
1693 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1694 the_insn.pcrel = 1;
1695 goto immediate;
1697 case 'G':
1698 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1699 the_insn.pcrel = 1;
1700 goto immediate;
1702 case 'N':
1703 if (*s == 'p' && s[1] == 'n')
1705 s += 2;
1706 continue;
1708 break;
1710 case 'T':
1711 if (*s == 'p' && s[1] == 't')
1713 s += 2;
1714 continue;
1716 break;
1718 case 'z':
1719 if (*s == ' ')
1721 ++s;
1723 if (strncmp (s, "%icc", 4) == 0)
1725 s += 4;
1726 continue;
1728 break;
1730 case 'Z':
1731 if (*s == ' ')
1733 ++s;
1735 if (strncmp (s, "%xcc", 4) == 0)
1737 s += 4;
1738 continue;
1740 break;
1742 case '6':
1743 if (*s == ' ')
1745 ++s;
1747 if (strncmp (s, "%fcc0", 5) == 0)
1749 s += 5;
1750 continue;
1752 break;
1754 case '7':
1755 if (*s == ' ')
1757 ++s;
1759 if (strncmp (s, "%fcc1", 5) == 0)
1761 s += 5;
1762 continue;
1764 break;
1766 case '8':
1767 if (*s == ' ')
1769 ++s;
1771 if (strncmp (s, "%fcc2", 5) == 0)
1773 s += 5;
1774 continue;
1776 break;
1778 case '9':
1779 if (*s == ' ')
1781 ++s;
1783 if (strncmp (s, "%fcc3", 5) == 0)
1785 s += 5;
1786 continue;
1788 break;
1790 case 'P':
1791 if (strncmp (s, "%pc", 3) == 0)
1793 s += 3;
1794 continue;
1796 break;
1798 case 'W':
1799 if (strncmp (s, "%tick", 5) == 0)
1801 s += 5;
1802 continue;
1804 break;
1806 case '\0': /* End of args. */
1807 if (*s == '\0')
1809 match = 1;
1811 break;
1813 case '+':
1814 if (*s == '+')
1816 ++s;
1817 continue;
1819 if (*s == '-')
1821 continue;
1823 break;
1825 case '[': /* These must match exactly. */
1826 case ']':
1827 case ',':
1828 case ' ':
1829 if (*s++ == *args)
1830 continue;
1831 break;
1833 case '#': /* Must be at least one digit. */
1834 if (ISDIGIT (*s++))
1836 while (ISDIGIT (*s))
1838 ++s;
1840 continue;
1842 break;
1844 case 'C': /* Coprocessor state register. */
1845 if (strncmp (s, "%csr", 4) == 0)
1847 s += 4;
1848 continue;
1850 break;
1852 case 'b': /* Next operand is a coprocessor register. */
1853 case 'c':
1854 case 'D':
1855 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
1857 mask = *s++;
1858 if (ISDIGIT (*s))
1860 mask = 10 * (mask - '0') + (*s++ - '0');
1861 if (mask >= 32)
1863 break;
1866 else
1868 mask -= '0';
1870 switch (*args)
1873 case 'b':
1874 opcode |= mask << 14;
1875 continue;
1877 case 'c':
1878 opcode |= mask;
1879 continue;
1881 case 'D':
1882 opcode |= mask << 25;
1883 continue;
1886 break;
1888 case 'r': /* next operand must be a register */
1889 case 'O':
1890 case '1':
1891 case '2':
1892 case 'd':
1893 if (*s++ == '%')
1895 switch (c = *s++)
1898 case 'f': /* frame pointer */
1899 if (*s++ == 'p')
1901 mask = 0x1e;
1902 break;
1904 goto error;
1906 case 'g': /* global register */
1907 c = *s++;
1908 if (isoctal (c))
1910 mask = c - '0';
1911 break;
1913 goto error;
1915 case 'i': /* in register */
1916 c = *s++;
1917 if (isoctal (c))
1919 mask = c - '0' + 24;
1920 break;
1922 goto error;
1924 case 'l': /* local register */
1925 c = *s++;
1926 if (isoctal (c))
1928 mask = (c - '0' + 16);
1929 break;
1931 goto error;
1933 case 'o': /* out register */
1934 c = *s++;
1935 if (isoctal (c))
1937 mask = (c - '0' + 8);
1938 break;
1940 goto error;
1942 case 's': /* stack pointer */
1943 if (*s++ == 'p')
1945 mask = 0xe;
1946 break;
1948 goto error;
1950 case 'r': /* any register */
1951 if (!ISDIGIT ((c = *s++)))
1953 goto error;
1955 /* FALLTHROUGH */
1956 case '0':
1957 case '1':
1958 case '2':
1959 case '3':
1960 case '4':
1961 case '5':
1962 case '6':
1963 case '7':
1964 case '8':
1965 case '9':
1966 if (ISDIGIT (*s))
1968 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1970 goto error;
1973 else
1975 c -= '0';
1977 mask = c;
1978 break;
1980 default:
1981 goto error;
1984 if ((mask & ~1) == 2 && sparc_arch_size == 64
1985 && no_undeclared_regs && ! globals[mask])
1986 as_bad (_("detected global register use not covered by .register pseudo-op"));
1988 /* Got the register, now figure out where
1989 it goes in the opcode. */
1990 switch (*args)
1992 case '1':
1993 opcode |= mask << 14;
1994 continue;
1996 case '2':
1997 opcode |= mask;
1998 continue;
2000 case 'd':
2001 opcode |= mask << 25;
2002 continue;
2004 case 'r':
2005 opcode |= (mask << 25) | (mask << 14);
2006 continue;
2008 case 'O':
2009 opcode |= (mask << 25) | (mask << 0);
2010 continue;
2013 break;
2015 case 'e': /* next operand is a floating point register */
2016 case 'v':
2017 case 'V':
2019 case 'f':
2020 case 'B':
2021 case 'R':
2023 case 'g':
2024 case 'H':
2025 case 'J':
2027 char format;
2029 if (*s++ == '%'
2030 && ((format = *s) == 'f')
2031 && ISDIGIT (*++s))
2033 for (mask = 0; ISDIGIT (*s); ++s)
2035 mask = 10 * mask + (*s - '0');
2036 } /* read the number */
2038 if ((*args == 'v'
2039 || *args == 'B'
2040 || *args == 'H')
2041 && (mask & 1))
2043 break;
2044 } /* register must be even numbered */
2046 if ((*args == 'V'
2047 || *args == 'R'
2048 || *args == 'J')
2049 && (mask & 3))
2051 break;
2052 } /* register must be multiple of 4 */
2054 if (mask >= 64)
2056 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2057 error_message = _(": There are only 64 f registers; [0-63]");
2058 else
2059 error_message = _(": There are only 32 f registers; [0-31]");
2060 goto error;
2061 } /* on error */
2062 else if (mask >= 32)
2064 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2066 v9_arg_p = 1;
2067 mask -= 31; /* wrap high bit */
2069 else
2071 error_message = _(": There are only 32 f registers; [0-31]");
2072 goto error;
2076 else
2078 break;
2079 } /* if not an 'f' register. */
2081 switch (*args)
2083 case 'v':
2084 case 'V':
2085 case 'e':
2086 opcode |= RS1 (mask);
2087 continue;
2089 case 'f':
2090 case 'B':
2091 case 'R':
2092 opcode |= RS2 (mask);
2093 continue;
2095 case 'g':
2096 case 'H':
2097 case 'J':
2098 opcode |= RD (mask);
2099 continue;
2100 } /* Pack it in. */
2102 know (0);
2103 break;
2104 } /* float arg */
2106 case 'F':
2107 if (strncmp (s, "%fsr", 4) == 0)
2109 s += 4;
2110 continue;
2112 break;
2114 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2115 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2116 goto immediate;
2118 case 'l': /* 22 bit PC relative immediate */
2119 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2120 the_insn.pcrel = 1;
2121 goto immediate;
2123 case 'L': /* 30 bit immediate */
2124 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2125 the_insn.pcrel = 1;
2126 goto immediate;
2128 case 'h':
2129 case 'n': /* 22 bit immediate */
2130 the_insn.reloc = BFD_RELOC_SPARC22;
2131 goto immediate;
2133 case 'i': /* 13 bit immediate */
2134 the_insn.reloc = BFD_RELOC_SPARC13;
2136 /* fallthrough */
2138 immediate:
2139 if (*s == ' ')
2140 s++;
2143 char *s1;
2144 char *op_arg = NULL;
2145 expressionS op_exp;
2146 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2148 /* Check for %hi, etc. */
2149 if (*s == '%')
2151 static const struct ops {
2152 /* The name as it appears in assembler. */
2153 char *name;
2154 /* strlen (name), precomputed for speed */
2155 int len;
2156 /* The reloc this pseudo-op translates to. */
2157 int reloc;
2158 /* Non-zero if for v9 only. */
2159 int v9_p;
2160 /* Non-zero if can be used in pc-relative contexts. */
2161 int pcrel_p;/*FIXME:wip*/
2162 } ops[] = {
2163 /* hix/lox must appear before hi/lo so %hix won't be
2164 mistaken for %hi. */
2165 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2166 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2167 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2168 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2169 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2170 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2171 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2172 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2173 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2174 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2175 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2176 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2177 { NULL, 0, 0, 0, 0 }
2179 const struct ops *o;
2181 for (o = ops; o->name; o++)
2182 if (strncmp (s + 1, o->name, o->len) == 0)
2183 break;
2184 if (o->name == NULL)
2185 break;
2187 if (s[o->len + 1] != '(')
2189 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2190 return special_case;
2193 op_arg = o->name;
2194 the_insn.reloc = o->reloc;
2195 s += o->len + 2;
2196 v9_arg_p = o->v9_p;
2199 /* Note that if the get_expression() fails, we will still
2200 have created U entries in the symbol table for the
2201 'symbols' in the input string. Try not to create U
2202 symbols for registers, etc. */
2204 /* This stuff checks to see if the expression ends in
2205 +%reg. If it does, it removes the register from
2206 the expression, and re-sets 's' to point to the
2207 right place. */
2209 if (op_arg)
2211 int npar = 0;
2213 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2214 if (*s1 == '(')
2215 npar++;
2216 else if (*s1 == ')')
2218 if (!npar)
2219 break;
2220 npar--;
2223 if (*s1 != ')')
2225 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2226 return special_case;
2229 *s1 = '\0';
2230 (void) get_expression (s);
2231 *s1 = ')';
2232 s = s1 + 1;
2233 if (*s == ',' || *s == ']' || !*s)
2234 continue;
2235 if (*s != '+' && *s != '-')
2237 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2238 return special_case;
2240 *s1 = '0';
2241 s = s1;
2242 op_exp = the_insn.exp;
2243 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2246 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2249 if (s1 != s && ISDIGIT (s1[-1]))
2251 if (s1[-2] == '%' && s1[-3] == '+')
2252 s1 -= 3;
2253 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2254 s1 -= 4;
2255 else
2256 s1 = NULL;
2257 if (s1)
2259 *s1 = '\0';
2260 if (op_arg && s1 == s + 1)
2261 the_insn.exp.X_op = O_absent;
2262 else
2263 (void) get_expression (s);
2264 *s1 = '+';
2265 if (op_arg)
2266 *s = ')';
2267 s = s1;
2270 else
2271 s1 = NULL;
2273 if (!s1)
2275 (void) get_expression (s);
2276 if (op_arg)
2277 *s = ')';
2278 s = expr_end;
2281 if (op_arg)
2283 the_insn.exp2 = the_insn.exp;
2284 the_insn.exp = op_exp;
2285 if (the_insn.exp2.X_op == O_absent)
2286 the_insn.exp2.X_op = O_illegal;
2287 else if (the_insn.exp.X_op == O_absent)
2289 the_insn.exp = the_insn.exp2;
2290 the_insn.exp2.X_op = O_illegal;
2292 else if (the_insn.exp.X_op == O_constant)
2294 valueT val = the_insn.exp.X_add_number;
2295 switch (the_insn.reloc)
2297 default:
2298 break;
2300 case BFD_RELOC_SPARC_HH22:
2301 val = BSR (val, 32);
2302 /* Fall through. */
2304 case BFD_RELOC_SPARC_LM22:
2305 case BFD_RELOC_HI22:
2306 val = (val >> 10) & 0x3fffff;
2307 break;
2309 case BFD_RELOC_SPARC_HM10:
2310 val = BSR (val, 32);
2311 /* Fall through. */
2313 case BFD_RELOC_LO10:
2314 val &= 0x3ff;
2315 break;
2317 case BFD_RELOC_SPARC_H44:
2318 val >>= 22;
2319 val &= 0x3fffff;
2320 break;
2322 case BFD_RELOC_SPARC_M44:
2323 val >>= 12;
2324 val &= 0x3ff;
2325 break;
2327 case BFD_RELOC_SPARC_L44:
2328 val &= 0xfff;
2329 break;
2331 case BFD_RELOC_SPARC_HIX22:
2332 val = ~val;
2333 val = (val >> 10) & 0x3fffff;
2334 break;
2336 case BFD_RELOC_SPARC_LOX10:
2337 val = (val & 0x3ff) | 0x1c00;
2338 break;
2340 the_insn.exp = the_insn.exp2;
2341 the_insn.exp.X_add_number += val;
2342 the_insn.exp2.X_op = O_illegal;
2343 the_insn.reloc = old_reloc;
2345 else if (the_insn.exp2.X_op != O_constant)
2347 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2348 return special_case;
2350 else
2352 if (old_reloc != BFD_RELOC_SPARC13
2353 || the_insn.reloc != BFD_RELOC_LO10
2354 || sparc_arch_size != 64
2355 || sparc_pic_code)
2357 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2358 return special_case;
2360 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2364 /* Check for constants that don't require emitting a reloc. */
2365 if (the_insn.exp.X_op == O_constant
2366 && the_insn.exp.X_add_symbol == 0
2367 && the_insn.exp.X_op_symbol == 0)
2369 /* For pc-relative call instructions, we reject
2370 constants to get better code. */
2371 if (the_insn.pcrel
2372 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2373 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2375 error_message = _(": PC-relative operand can't be a constant");
2376 goto error;
2379 /* Constants that won't fit are checked in md_apply_fix3
2380 and bfd_install_relocation.
2381 ??? It would be preferable to install the constants
2382 into the insn here and save having to create a fixS
2383 for each one. There already exists code to handle
2384 all the various cases (e.g. in md_apply_fix3 and
2385 bfd_install_relocation) so duplicating all that code
2386 here isn't right. */
2389 continue;
2391 case 'a':
2392 if (*s++ == 'a')
2394 opcode |= ANNUL;
2395 continue;
2397 break;
2399 case 'A':
2401 int asi = 0;
2403 /* Parse an asi. */
2404 if (*s == '#')
2406 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2408 error_message = _(": invalid ASI name");
2409 goto error;
2412 else
2414 if (! parse_const_expr_arg (&s, &asi))
2416 error_message = _(": invalid ASI expression");
2417 goto error;
2419 if (asi < 0 || asi > 255)
2421 error_message = _(": invalid ASI number");
2422 goto error;
2425 opcode |= ASI (asi);
2426 continue;
2427 } /* Alternate space. */
2429 case 'p':
2430 if (strncmp (s, "%psr", 4) == 0)
2432 s += 4;
2433 continue;
2435 break;
2437 case 'q': /* Floating point queue. */
2438 if (strncmp (s, "%fq", 3) == 0)
2440 s += 3;
2441 continue;
2443 break;
2445 case 'Q': /* Coprocessor queue. */
2446 if (strncmp (s, "%cq", 3) == 0)
2448 s += 3;
2449 continue;
2451 break;
2453 case 'S':
2454 if (strcmp (str, "set") == 0
2455 || strcmp (str, "setuw") == 0)
2457 special_case = SPECIAL_CASE_SET;
2458 continue;
2460 else if (strcmp (str, "setsw") == 0)
2462 special_case = SPECIAL_CASE_SETSW;
2463 continue;
2465 else if (strcmp (str, "setx") == 0)
2467 special_case = SPECIAL_CASE_SETX;
2468 continue;
2470 else if (strncmp (str, "fdiv", 4) == 0)
2472 special_case = SPECIAL_CASE_FDIV;
2473 continue;
2475 break;
2477 case 'o':
2478 if (strncmp (s, "%asi", 4) != 0)
2479 break;
2480 s += 4;
2481 continue;
2483 case 's':
2484 if (strncmp (s, "%fprs", 5) != 0)
2485 break;
2486 s += 5;
2487 continue;
2489 case 'E':
2490 if (strncmp (s, "%ccr", 4) != 0)
2491 break;
2492 s += 4;
2493 continue;
2495 case 't':
2496 if (strncmp (s, "%tbr", 4) != 0)
2497 break;
2498 s += 4;
2499 continue;
2501 case 'w':
2502 if (strncmp (s, "%wim", 4) != 0)
2503 break;
2504 s += 4;
2505 continue;
2507 case 'x':
2509 char *push = input_line_pointer;
2510 expressionS e;
2512 input_line_pointer = s;
2513 expression (&e);
2514 if (e.X_op == O_constant)
2516 int n = e.X_add_number;
2517 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2518 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2519 else
2520 opcode |= e.X_add_number << 5;
2522 else
2523 as_bad (_("non-immediate OPF operand, ignored"));
2524 s = input_line_pointer;
2525 input_line_pointer = push;
2526 continue;
2529 case 'y':
2530 if (strncmp (s, "%y", 2) != 0)
2531 break;
2532 s += 2;
2533 continue;
2535 case 'u':
2536 case 'U':
2538 /* Parse a sparclet cpreg. */
2539 int cpreg;
2540 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2542 error_message = _(": invalid cpreg name");
2543 goto error;
2545 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2546 continue;
2549 default:
2550 as_fatal (_("failed sanity check."));
2551 } /* switch on arg code. */
2553 /* Break out of for() loop. */
2554 break;
2555 } /* For each arg that we expect. */
2557 error:
2558 if (match == 0)
2560 /* Args don't match. */
2561 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2562 && (insn->name == insn[1].name
2563 || !strcmp (insn->name, insn[1].name)))
2565 ++insn;
2566 s = argsStart;
2567 continue;
2569 else
2571 as_bad (_("Illegal operands%s"), error_message);
2572 return special_case;
2575 else
2577 /* We have a match. Now see if the architecture is OK. */
2578 int needed_arch_mask = insn->architecture;
2580 if (v9_arg_p)
2582 needed_arch_mask &=
2583 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2584 if (! needed_arch_mask)
2585 needed_arch_mask =
2586 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2589 if (needed_arch_mask
2590 & SPARC_OPCODE_SUPPORTED (current_architecture))
2591 /* OK. */
2593 /* Can we bump up the architecture? */
2594 else if (needed_arch_mask
2595 & SPARC_OPCODE_SUPPORTED (max_architecture))
2597 enum sparc_opcode_arch_val needed_architecture =
2598 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2599 & needed_arch_mask);
2601 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2602 if (warn_on_bump
2603 && needed_architecture > warn_after_architecture)
2605 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2606 sparc_opcode_archs[current_architecture].name,
2607 sparc_opcode_archs[needed_architecture].name,
2608 str);
2609 warn_after_architecture = needed_architecture;
2611 current_architecture = needed_architecture;
2613 /* Conflict. */
2614 /* ??? This seems to be a bit fragile. What if the next entry in
2615 the opcode table is the one we want and it is supported?
2616 It is possible to arrange the table today so that this can't
2617 happen but what about tomorrow? */
2618 else
2620 int arch, printed_one_p = 0;
2621 char *p;
2622 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2624 /* Create a list of the architectures that support the insn. */
2625 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2626 p = required_archs;
2627 arch = sparc_ffs (needed_arch_mask);
2628 while ((1 << arch) <= needed_arch_mask)
2630 if ((1 << arch) & needed_arch_mask)
2632 if (printed_one_p)
2633 *p++ = '|';
2634 strcpy (p, sparc_opcode_archs[arch].name);
2635 p += strlen (p);
2636 printed_one_p = 1;
2638 ++arch;
2641 as_bad (_("Architecture mismatch on \"%s\"."), str);
2642 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2643 required_archs,
2644 sparc_opcode_archs[max_architecture].name);
2645 return special_case;
2647 } /* If no match. */
2649 break;
2650 } /* Forever looking for a match. */
2652 the_insn.opcode = opcode;
2653 return special_case;
2656 /* Parse an argument that can be expressed as a keyword.
2657 (eg: #StoreStore or %ccfr).
2658 The result is a boolean indicating success.
2659 If successful, INPUT_POINTER is updated. */
2661 static int
2662 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2663 int (*lookup_fn) PARAMS ((const char *));
2664 char **input_pointerP;
2665 int *valueP;
2667 int value;
2668 char c, *p, *q;
2670 p = *input_pointerP;
2671 for (q = p + (*p == '#' || *p == '%');
2672 ISALNUM (*q) || *q == '_';
2673 ++q)
2674 continue;
2675 c = *q;
2676 *q = 0;
2677 value = (*lookup_fn) (p);
2678 *q = c;
2679 if (value == -1)
2680 return 0;
2681 *valueP = value;
2682 *input_pointerP = q;
2683 return 1;
2686 /* Parse an argument that is a constant expression.
2687 The result is a boolean indicating success. */
2689 static int
2690 parse_const_expr_arg (input_pointerP, valueP)
2691 char **input_pointerP;
2692 int *valueP;
2694 char *save = input_line_pointer;
2695 expressionS exp;
2697 input_line_pointer = *input_pointerP;
2698 /* The next expression may be something other than a constant
2699 (say if we're not processing the right variant of the insn).
2700 Don't call expression unless we're sure it will succeed as it will
2701 signal an error (which we want to defer until later). */
2702 /* FIXME: It might be better to define md_operand and have it recognize
2703 things like %asi, etc. but continuing that route through to the end
2704 is a lot of work. */
2705 if (*input_line_pointer == '%')
2707 input_line_pointer = save;
2708 return 0;
2710 expression (&exp);
2711 *input_pointerP = input_line_pointer;
2712 input_line_pointer = save;
2713 if (exp.X_op != O_constant)
2714 return 0;
2715 *valueP = exp.X_add_number;
2716 return 1;
2719 /* Subroutine of sparc_ip to parse an expression. */
2721 static int
2722 get_expression (str)
2723 char *str;
2725 char *save_in;
2726 segT seg;
2728 save_in = input_line_pointer;
2729 input_line_pointer = str;
2730 seg = expression (&the_insn.exp);
2731 if (seg != absolute_section
2732 && seg != text_section
2733 && seg != data_section
2734 && seg != bss_section
2735 && seg != undefined_section)
2737 the_insn.error = _("bad segment");
2738 expr_end = input_line_pointer;
2739 input_line_pointer = save_in;
2740 return 1;
2742 expr_end = input_line_pointer;
2743 input_line_pointer = save_in;
2744 return 0;
2747 /* Subroutine of md_assemble to output one insn. */
2749 static void
2750 output_insn (insn, the_insn)
2751 const struct sparc_opcode *insn;
2752 struct sparc_it *the_insn;
2754 char *toP = frag_more (4);
2756 /* Put out the opcode. */
2757 if (INSN_BIG_ENDIAN)
2758 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2759 else
2760 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2762 /* Put out the symbol-dependent stuff. */
2763 if (the_insn->reloc != BFD_RELOC_NONE)
2765 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2766 (toP - frag_now->fr_literal), /* Where. */
2767 4, /* Size. */
2768 &the_insn->exp,
2769 the_insn->pcrel,
2770 the_insn->reloc);
2771 /* Turn off overflow checking in fixup_segment. We'll do our
2772 own overflow checking in md_apply_fix3. This is necessary because
2773 the insn size is 4 and fixup_segment will signal an overflow for
2774 large 8 byte quantities. */
2775 fixP->fx_no_overflow = 1;
2776 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2777 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2780 last_insn = insn;
2781 last_opcode = the_insn->opcode;
2783 #ifdef OBJ_ELF
2784 dwarf2_emit_insn (4);
2785 #endif
2788 /* This is identical to the md_atof in m68k.c. I think this is right,
2789 but I'm not sure.
2791 Turn a string in input_line_pointer into a floating point constant
2792 of type TYPE, and store the appropriate bytes in *LITP. The number
2793 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2794 returned, or NULL on OK. */
2796 /* Equal to MAX_PRECISION in atof-ieee.c. */
2797 #define MAX_LITTLENUMS 6
2799 char *
2800 md_atof (type, litP, sizeP)
2801 char type;
2802 char *litP;
2803 int *sizeP;
2805 int i, prec;
2806 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2807 char *t;
2809 switch (type)
2811 case 'f':
2812 case 'F':
2813 case 's':
2814 case 'S':
2815 prec = 2;
2816 break;
2818 case 'd':
2819 case 'D':
2820 case 'r':
2821 case 'R':
2822 prec = 4;
2823 break;
2825 case 'x':
2826 case 'X':
2827 prec = 6;
2828 break;
2830 case 'p':
2831 case 'P':
2832 prec = 6;
2833 break;
2835 default:
2836 *sizeP = 0;
2837 return _("Bad call to MD_ATOF()");
2840 t = atof_ieee (input_line_pointer, type, words);
2841 if (t)
2842 input_line_pointer = t;
2843 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2845 if (target_big_endian)
2847 for (i = 0; i < prec; i++)
2849 md_number_to_chars (litP, (valueT) words[i],
2850 sizeof (LITTLENUM_TYPE));
2851 litP += sizeof (LITTLENUM_TYPE);
2854 else
2856 for (i = prec - 1; i >= 0; i--)
2858 md_number_to_chars (litP, (valueT) words[i],
2859 sizeof (LITTLENUM_TYPE));
2860 litP += sizeof (LITTLENUM_TYPE);
2864 return 0;
2867 /* Write a value out to the object file, using the appropriate
2868 endianness. */
2870 void
2871 md_number_to_chars (buf, val, n)
2872 char *buf;
2873 valueT val;
2874 int n;
2876 if (target_big_endian)
2877 number_to_chars_bigendian (buf, val, n);
2878 else if (target_little_endian_data
2879 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2880 /* Output debug words, which are not in allocated sections, as big
2881 endian. */
2882 number_to_chars_bigendian (buf, val, n);
2883 else if (target_little_endian_data || ! target_big_endian)
2884 number_to_chars_littleendian (buf, val, n);
2887 /* Apply a fixS to the frags, now that we know the value it ought to
2888 hold. */
2890 void
2891 md_apply_fix3 (fixP, valP, segment)
2892 fixS *fixP;
2893 valueT *valP;
2894 segT segment;
2896 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2897 offsetT val = * (offsetT *) valP;
2898 long insn;
2900 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2902 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
2904 #ifdef OBJ_ELF
2905 /* SPARC ELF relocations don't use an addend in the data field. */
2906 if (fixP->fx_addsy != NULL)
2907 return;
2908 #endif
2910 /* This is a hack. There should be a better way to
2911 handle this. Probably in terms of howto fields, once
2912 we can look at these fixups in terms of howtos. */
2913 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2914 val += fixP->fx_where + fixP->fx_frag->fr_address;
2916 #ifdef OBJ_AOUT
2917 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2918 generate a reloc, then we just want to let the reloc addend set
2919 the value. We do not want to also stuff the addend into the
2920 object file. Including the addend in the object file works when
2921 doing a static link, because the linker will ignore the object
2922 file contents. However, the dynamic linker does not ignore the
2923 object file contents. */
2924 if (fixP->fx_addsy != NULL
2925 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2926 val = 0;
2928 /* When generating PIC code, we do not want an addend for a reloc
2929 against a local symbol. We adjust fx_addnumber to cancel out the
2930 value already included in val, and to also cancel out the
2931 adjustment which bfd_install_relocation will create. */
2932 if (sparc_pic_code
2933 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2934 && fixP->fx_addsy != NULL
2935 && ! S_IS_COMMON (fixP->fx_addsy)
2936 && symbol_section_p (fixP->fx_addsy))
2937 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2939 /* When generating PIC code, we need to fiddle to get
2940 bfd_install_relocation to do the right thing for a PC relative
2941 reloc against a local symbol which we are going to keep. */
2942 if (sparc_pic_code
2943 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2944 && fixP->fx_addsy != NULL
2945 && (S_IS_EXTERNAL (fixP->fx_addsy)
2946 || S_IS_WEAK (fixP->fx_addsy))
2947 && S_IS_DEFINED (fixP->fx_addsy)
2948 && ! S_IS_COMMON (fixP->fx_addsy))
2950 val = 0;
2951 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2953 #endif
2955 /* If this is a data relocation, just output VAL. */
2957 if (fixP->fx_r_type == BFD_RELOC_16
2958 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
2960 md_number_to_chars (buf, val, 2);
2962 else if (fixP->fx_r_type == BFD_RELOC_32
2963 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
2964 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2966 md_number_to_chars (buf, val, 4);
2968 else if (fixP->fx_r_type == BFD_RELOC_64
2969 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
2971 md_number_to_chars (buf, val, 8);
2973 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2974 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2976 fixP->fx_done = 0;
2977 return;
2979 else
2981 /* It's a relocation against an instruction. */
2983 if (INSN_BIG_ENDIAN)
2984 insn = bfd_getb32 ((unsigned char *) buf);
2985 else
2986 insn = bfd_getl32 ((unsigned char *) buf);
2988 switch (fixP->fx_r_type)
2990 case BFD_RELOC_32_PCREL_S2:
2991 val = val >> 2;
2992 /* FIXME: This increment-by-one deserves a comment of why it's
2993 being done! */
2994 if (! sparc_pic_code
2995 || fixP->fx_addsy == NULL
2996 || symbol_section_p (fixP->fx_addsy))
2997 ++val;
2999 insn |= val & 0x3fffffff;
3001 /* See if we have a delay slot. */
3002 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3004 #define G0 0
3005 #define O7 15
3006 #define XCC (2 << 20)
3007 #define COND(x) (((x)&0xf)<<25)
3008 #define CONDA COND(0x8)
3009 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3010 #define INSN_BA (F2(0,2) | CONDA)
3011 #define INSN_OR F3(2, 0x2, 0)
3012 #define INSN_NOP F2(0,4)
3014 long delay;
3016 /* If the instruction is a call with either:
3017 restore
3018 arithmetic instruction with rd == %o7
3019 where rs1 != %o7 and rs2 if it is register != %o7
3020 then we can optimize if the call destination is near
3021 by changing the call into a branch always. */
3022 if (INSN_BIG_ENDIAN)
3023 delay = bfd_getb32 ((unsigned char *) buf + 4);
3024 else
3025 delay = bfd_getl32 ((unsigned char *) buf + 4);
3026 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3027 break;
3028 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3029 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3030 || ((delay & RD (~0)) != RD (O7))))
3031 break;
3032 if ((delay & RS1 (~0)) == RS1 (O7)
3033 || ((delay & F3I (~0)) == 0
3034 && (delay & RS2 (~0)) == RS2 (O7)))
3035 break;
3036 /* Ensure the branch will fit into simm22. */
3037 if ((val & 0x3fe00000)
3038 && (val & 0x3fe00000) != 0x3fe00000)
3039 break;
3040 /* Check if the arch is v9 and branch will fit
3041 into simm19. */
3042 if (((val & 0x3c0000) == 0
3043 || (val & 0x3c0000) == 0x3c0000)
3044 && (sparc_arch_size == 64
3045 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3046 /* ba,pt %xcc */
3047 insn = INSN_BPA | (val & 0x7ffff);
3048 else
3049 /* ba */
3050 insn = INSN_BA | (val & 0x3fffff);
3051 if (fixP->fx_where >= 4
3052 && ((delay & (0xffffffff ^ RS1 (~0)))
3053 == (INSN_OR | RD (O7) | RS2 (G0))))
3055 long setter;
3056 int reg;
3058 if (INSN_BIG_ENDIAN)
3059 setter = bfd_getb32 ((unsigned char *) buf - 4);
3060 else
3061 setter = bfd_getl32 ((unsigned char *) buf - 4);
3062 if ((setter & (0xffffffff ^ RD (~0)))
3063 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3064 break;
3065 /* The sequence was
3066 or %o7, %g0, %rN
3067 call foo
3068 or %rN, %g0, %o7
3070 If call foo was replaced with ba, replace
3071 or %rN, %g0, %o7 with nop. */
3072 reg = (delay & RS1 (~0)) >> 14;
3073 if (reg != ((setter & RD (~0)) >> 25)
3074 || reg == G0 || reg == O7)
3075 break;
3077 if (INSN_BIG_ENDIAN)
3078 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3079 else
3080 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3083 break;
3085 case BFD_RELOC_SPARC_11:
3086 if (! in_signed_range (val, 0x7ff))
3087 as_bad_where (fixP->fx_file, fixP->fx_line,
3088 _("relocation overflow"));
3089 insn |= val & 0x7ff;
3090 break;
3092 case BFD_RELOC_SPARC_10:
3093 if (! in_signed_range (val, 0x3ff))
3094 as_bad_where (fixP->fx_file, fixP->fx_line,
3095 _("relocation overflow"));
3096 insn |= val & 0x3ff;
3097 break;
3099 case BFD_RELOC_SPARC_7:
3100 if (! in_bitfield_range (val, 0x7f))
3101 as_bad_where (fixP->fx_file, fixP->fx_line,
3102 _("relocation overflow"));
3103 insn |= val & 0x7f;
3104 break;
3106 case BFD_RELOC_SPARC_6:
3107 if (! in_bitfield_range (val, 0x3f))
3108 as_bad_where (fixP->fx_file, fixP->fx_line,
3109 _("relocation overflow"));
3110 insn |= val & 0x3f;
3111 break;
3113 case BFD_RELOC_SPARC_5:
3114 if (! in_bitfield_range (val, 0x1f))
3115 as_bad_where (fixP->fx_file, fixP->fx_line,
3116 _("relocation overflow"));
3117 insn |= val & 0x1f;
3118 break;
3120 case BFD_RELOC_SPARC_WDISP16:
3121 /* FIXME: simplify. */
3122 if (((val > 0) && (val & ~0x3fffc))
3123 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3124 as_bad_where (fixP->fx_file, fixP->fx_line,
3125 _("relocation overflow"));
3126 /* FIXME: The +1 deserves a comment. */
3127 val = (val >> 2) + 1;
3128 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3129 break;
3131 case BFD_RELOC_SPARC_WDISP19:
3132 /* FIXME: simplify. */
3133 if (((val > 0) && (val & ~0x1ffffc))
3134 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3135 as_bad_where (fixP->fx_file, fixP->fx_line,
3136 _("relocation overflow"));
3137 /* FIXME: The +1 deserves a comment. */
3138 val = (val >> 2) + 1;
3139 insn |= val & 0x7ffff;
3140 break;
3142 case BFD_RELOC_SPARC_HH22:
3143 val = BSR (val, 32);
3144 /* Fall through. */
3146 case BFD_RELOC_SPARC_LM22:
3147 case BFD_RELOC_HI22:
3148 if (!fixP->fx_addsy)
3149 insn |= (val >> 10) & 0x3fffff;
3150 else
3151 /* FIXME: Need comment explaining why we do this. */
3152 insn &= ~0xffff;
3153 break;
3155 case BFD_RELOC_SPARC22:
3156 if (val & ~0x003fffff)
3157 as_bad_where (fixP->fx_file, fixP->fx_line,
3158 _("relocation overflow"));
3159 insn |= (val & 0x3fffff);
3160 break;
3162 case BFD_RELOC_SPARC_HM10:
3163 val = BSR (val, 32);
3164 /* Fall through. */
3166 case BFD_RELOC_LO10:
3167 if (!fixP->fx_addsy)
3168 insn |= val & 0x3ff;
3169 else
3170 /* FIXME: Need comment explaining why we do this. */
3171 insn &= ~0xff;
3172 break;
3174 case BFD_RELOC_SPARC_OLO10:
3175 val &= 0x3ff;
3176 val += fixP->tc_fix_data;
3177 /* Fall through. */
3179 case BFD_RELOC_SPARC13:
3180 if (! in_signed_range (val, 0x1fff))
3181 as_bad_where (fixP->fx_file, fixP->fx_line,
3182 _("relocation overflow"));
3183 insn |= val & 0x1fff;
3184 break;
3186 case BFD_RELOC_SPARC_WDISP22:
3187 val = (val >> 2) + 1;
3188 /* Fall through. */
3189 case BFD_RELOC_SPARC_BASE22:
3190 insn |= val & 0x3fffff;
3191 break;
3193 case BFD_RELOC_SPARC_H44:
3194 if (!fixP->fx_addsy)
3196 bfd_vma tval = val;
3197 tval >>= 22;
3198 insn |= tval & 0x3fffff;
3200 break;
3202 case BFD_RELOC_SPARC_M44:
3203 if (!fixP->fx_addsy)
3204 insn |= (val >> 12) & 0x3ff;
3205 break;
3207 case BFD_RELOC_SPARC_L44:
3208 if (!fixP->fx_addsy)
3209 insn |= val & 0xfff;
3210 break;
3212 case BFD_RELOC_SPARC_HIX22:
3213 if (!fixP->fx_addsy)
3215 val ^= ~(offsetT) 0;
3216 insn |= (val >> 10) & 0x3fffff;
3218 break;
3220 case BFD_RELOC_SPARC_LOX10:
3221 if (!fixP->fx_addsy)
3222 insn |= 0x1c00 | (val & 0x3ff);
3223 break;
3225 case BFD_RELOC_NONE:
3226 default:
3227 as_bad_where (fixP->fx_file, fixP->fx_line,
3228 _("bad or unhandled relocation type: 0x%02x"),
3229 fixP->fx_r_type);
3230 break;
3233 if (INSN_BIG_ENDIAN)
3234 bfd_putb32 (insn, (unsigned char *) buf);
3235 else
3236 bfd_putl32 (insn, (unsigned char *) buf);
3239 /* Are we finished with this relocation now? */
3240 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3241 fixP->fx_done = 1;
3244 /* Translate internal representation of relocation info to BFD target
3245 format. */
3247 arelent **
3248 tc_gen_reloc (section, fixp)
3249 asection *section;
3250 fixS *fixp;
3252 static arelent *relocs[3];
3253 arelent *reloc;
3254 bfd_reloc_code_real_type code;
3256 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3257 relocs[1] = NULL;
3259 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3260 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3261 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3263 switch (fixp->fx_r_type)
3265 case BFD_RELOC_16:
3266 case BFD_RELOC_32:
3267 case BFD_RELOC_HI22:
3268 case BFD_RELOC_LO10:
3269 case BFD_RELOC_32_PCREL_S2:
3270 case BFD_RELOC_SPARC13:
3271 case BFD_RELOC_SPARC22:
3272 case BFD_RELOC_SPARC_BASE13:
3273 case BFD_RELOC_SPARC_WDISP16:
3274 case BFD_RELOC_SPARC_WDISP19:
3275 case BFD_RELOC_SPARC_WDISP22:
3276 case BFD_RELOC_64:
3277 case BFD_RELOC_SPARC_5:
3278 case BFD_RELOC_SPARC_6:
3279 case BFD_RELOC_SPARC_7:
3280 case BFD_RELOC_SPARC_10:
3281 case BFD_RELOC_SPARC_11:
3282 case BFD_RELOC_SPARC_HH22:
3283 case BFD_RELOC_SPARC_HM10:
3284 case BFD_RELOC_SPARC_LM22:
3285 case BFD_RELOC_SPARC_PC_HH22:
3286 case BFD_RELOC_SPARC_PC_HM10:
3287 case BFD_RELOC_SPARC_PC_LM22:
3288 case BFD_RELOC_SPARC_H44:
3289 case BFD_RELOC_SPARC_M44:
3290 case BFD_RELOC_SPARC_L44:
3291 case BFD_RELOC_SPARC_HIX22:
3292 case BFD_RELOC_SPARC_LOX10:
3293 case BFD_RELOC_SPARC_REV32:
3294 case BFD_RELOC_SPARC_OLO10:
3295 case BFD_RELOC_SPARC_UA16:
3296 case BFD_RELOC_SPARC_UA32:
3297 case BFD_RELOC_SPARC_UA64:
3298 case BFD_RELOC_8_PCREL:
3299 case BFD_RELOC_16_PCREL:
3300 case BFD_RELOC_32_PCREL:
3301 case BFD_RELOC_64_PCREL:
3302 case BFD_RELOC_SPARC_PLT32:
3303 case BFD_RELOC_SPARC_PLT64:
3304 case BFD_RELOC_VTABLE_ENTRY:
3305 case BFD_RELOC_VTABLE_INHERIT:
3306 code = fixp->fx_r_type;
3307 break;
3308 default:
3309 abort ();
3310 return NULL;
3313 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3314 /* If we are generating PIC code, we need to generate a different
3315 set of relocs. */
3317 #ifdef OBJ_ELF
3318 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3319 #else
3320 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3321 #endif
3323 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3325 if (sparc_pic_code)
3327 switch (code)
3329 case BFD_RELOC_32_PCREL_S2:
3330 if (S_FORCE_RELOC (fixp->fx_addsy))
3331 code = BFD_RELOC_SPARC_WPLT30;
3332 break;
3333 case BFD_RELOC_HI22:
3334 if (fixp->fx_addsy != NULL
3335 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3336 code = BFD_RELOC_SPARC_PC22;
3337 else
3338 code = BFD_RELOC_SPARC_GOT22;
3339 break;
3340 case BFD_RELOC_LO10:
3341 if (fixp->fx_addsy != NULL
3342 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3343 code = BFD_RELOC_SPARC_PC10;
3344 else
3345 code = BFD_RELOC_SPARC_GOT10;
3346 break;
3347 case BFD_RELOC_SPARC13:
3348 code = BFD_RELOC_SPARC_GOT13;
3349 break;
3350 default:
3351 break;
3354 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3356 if (code == BFD_RELOC_SPARC_OLO10)
3357 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3358 else
3359 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3360 if (reloc->howto == 0)
3362 as_bad_where (fixp->fx_file, fixp->fx_line,
3363 _("internal error: can't export reloc type %d (`%s')"),
3364 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3365 xfree (reloc);
3366 relocs[0] = NULL;
3367 return relocs;
3370 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3371 #ifdef OBJ_AOUT
3373 if (reloc->howto->pc_relative == 0
3374 || code == BFD_RELOC_SPARC_PC10
3375 || code == BFD_RELOC_SPARC_PC22)
3376 reloc->addend = fixp->fx_addnumber;
3377 else if (sparc_pic_code
3378 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3379 && fixp->fx_addsy != NULL
3380 && (S_IS_EXTERNAL (fixp->fx_addsy)
3381 || S_IS_WEAK (fixp->fx_addsy))
3382 && S_IS_DEFINED (fixp->fx_addsy)
3383 && ! S_IS_COMMON (fixp->fx_addsy))
3384 reloc->addend = fixp->fx_addnumber;
3385 else
3386 reloc->addend = fixp->fx_offset - reloc->address;
3388 #else /* elf or coff */
3390 if (code != BFD_RELOC_32_PCREL_S2
3391 && code != BFD_RELOC_SPARC_WDISP22
3392 && code != BFD_RELOC_SPARC_WDISP16
3393 && code != BFD_RELOC_SPARC_WDISP19
3394 && code != BFD_RELOC_SPARC_WPLT30)
3395 reloc->addend = fixp->fx_addnumber;
3396 else if (symbol_section_p (fixp->fx_addsy))
3397 reloc->addend = (section->vma
3398 + fixp->fx_addnumber
3399 + md_pcrel_from (fixp));
3400 else
3401 reloc->addend = fixp->fx_offset;
3402 #endif
3404 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3405 on the same location. */
3406 if (code == BFD_RELOC_SPARC_OLO10)
3408 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3409 relocs[2] = NULL;
3411 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3412 *reloc->sym_ptr_ptr
3413 = symbol_get_bfdsym (section_symbol (absolute_section));
3414 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3415 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3416 reloc->addend = fixp->tc_fix_data;
3419 return relocs;
3422 /* We have no need to default values of symbols. */
3424 symbolS *
3425 md_undefined_symbol (name)
3426 char *name ATTRIBUTE_UNUSED;
3428 return 0;
3431 /* Round up a section size to the appropriate boundary. */
3433 valueT
3434 md_section_align (segment, size)
3435 segT segment ATTRIBUTE_UNUSED;
3436 valueT size;
3438 #ifndef OBJ_ELF
3439 /* This is not right for ELF; a.out wants it, and COFF will force
3440 the alignment anyways. */
3441 valueT align = ((valueT) 1
3442 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3443 valueT newsize;
3445 /* Turn alignment value into a mask. */
3446 align--;
3447 newsize = (size + align) & ~align;
3448 return newsize;
3449 #else
3450 return size;
3451 #endif
3454 /* Exactly what point is a PC-relative offset relative TO?
3455 On the sparc, they're relative to the address of the offset, plus
3456 its size. This gets us to the following instruction.
3457 (??? Is this right? FIXME-SOON) */
3458 long
3459 md_pcrel_from (fixP)
3460 fixS *fixP;
3462 long ret;
3464 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3465 if (! sparc_pic_code
3466 || fixP->fx_addsy == NULL
3467 || symbol_section_p (fixP->fx_addsy))
3468 ret += fixP->fx_size;
3469 return ret;
3472 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3473 of two. */
3475 static int
3476 log2 (value)
3477 int value;
3479 int shift;
3481 if (value <= 0)
3482 return -1;
3484 for (shift = 0; (value & 1) == 0; value >>= 1)
3485 ++shift;
3487 return (value == 1) ? shift : -1;
3490 /* Sort of like s_lcomm. */
3492 #ifndef OBJ_ELF
3493 static int max_alignment = 15;
3494 #endif
3496 static void
3497 s_reserve (ignore)
3498 int ignore ATTRIBUTE_UNUSED;
3500 char *name;
3501 char *p;
3502 char c;
3503 int align;
3504 int size;
3505 int temp;
3506 symbolS *symbolP;
3508 name = input_line_pointer;
3509 c = get_symbol_end ();
3510 p = input_line_pointer;
3511 *p = c;
3512 SKIP_WHITESPACE ();
3514 if (*input_line_pointer != ',')
3516 as_bad (_("Expected comma after name"));
3517 ignore_rest_of_line ();
3518 return;
3521 ++input_line_pointer;
3523 if ((size = get_absolute_expression ()) < 0)
3525 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3526 ignore_rest_of_line ();
3527 return;
3528 } /* Bad length. */
3530 *p = 0;
3531 symbolP = symbol_find_or_make (name);
3532 *p = c;
3534 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3535 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3537 as_bad (_("bad .reserve segment -- expected BSS segment"));
3538 return;
3541 if (input_line_pointer[2] == '.')
3542 input_line_pointer += 7;
3543 else
3544 input_line_pointer += 6;
3545 SKIP_WHITESPACE ();
3547 if (*input_line_pointer == ',')
3549 ++input_line_pointer;
3551 SKIP_WHITESPACE ();
3552 if (*input_line_pointer == '\n')
3554 as_bad (_("missing alignment"));
3555 ignore_rest_of_line ();
3556 return;
3559 align = (int) get_absolute_expression ();
3561 #ifndef OBJ_ELF
3562 if (align > max_alignment)
3564 align = max_alignment;
3565 as_warn (_("alignment too large; assuming %d"), align);
3567 #endif
3569 if (align < 0)
3571 as_bad (_("negative alignment"));
3572 ignore_rest_of_line ();
3573 return;
3576 if (align != 0)
3578 temp = log2 (align);
3579 if (temp < 0)
3581 as_bad (_("alignment not a power of 2"));
3582 ignore_rest_of_line ();
3583 return;
3586 align = temp;
3589 record_alignment (bss_section, align);
3591 else
3592 align = 0;
3594 if (!S_IS_DEFINED (symbolP)
3595 #ifdef OBJ_AOUT
3596 && S_GET_OTHER (symbolP) == 0
3597 && S_GET_DESC (symbolP) == 0
3598 #endif
3601 if (! need_pass_2)
3603 char *pfrag;
3604 segT current_seg = now_seg;
3605 subsegT current_subseg = now_subseg;
3607 /* Switch to bss. */
3608 subseg_set (bss_section, 1);
3610 if (align)
3611 /* Do alignment. */
3612 frag_align (align, 0, 0);
3614 /* Detach from old frag. */
3615 if (S_GET_SEGMENT (symbolP) == bss_section)
3616 symbol_get_frag (symbolP)->fr_symbol = NULL;
3618 symbol_set_frag (symbolP, frag_now);
3619 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3620 (offsetT) size, (char *) 0);
3621 *pfrag = 0;
3623 S_SET_SEGMENT (symbolP, bss_section);
3625 subseg_set (current_seg, current_subseg);
3627 #ifdef OBJ_ELF
3628 S_SET_SIZE (symbolP, size);
3629 #endif
3632 else
3634 as_warn ("Ignoring attempt to re-define symbol %s",
3635 S_GET_NAME (symbolP));
3636 } /* if not redefining. */
3638 demand_empty_rest_of_line ();
3641 static void
3642 s_common (ignore)
3643 int ignore ATTRIBUTE_UNUSED;
3645 char *name;
3646 char c;
3647 char *p;
3648 int temp, size;
3649 symbolS *symbolP;
3651 name = input_line_pointer;
3652 c = get_symbol_end ();
3653 /* Just after name is now '\0'. */
3654 p = input_line_pointer;
3655 *p = c;
3656 SKIP_WHITESPACE ();
3657 if (*input_line_pointer != ',')
3659 as_bad (_("Expected comma after symbol-name"));
3660 ignore_rest_of_line ();
3661 return;
3664 /* Skip ','. */
3665 input_line_pointer++;
3667 if ((temp = get_absolute_expression ()) < 0)
3669 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3670 ignore_rest_of_line ();
3671 return;
3673 size = temp;
3674 *p = 0;
3675 symbolP = symbol_find_or_make (name);
3676 *p = c;
3677 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3679 as_bad (_("Ignoring attempt to re-define symbol"));
3680 ignore_rest_of_line ();
3681 return;
3683 if (S_GET_VALUE (symbolP) != 0)
3685 if (S_GET_VALUE (symbolP) != (valueT) size)
3687 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3688 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3691 else
3693 #ifndef OBJ_ELF
3694 S_SET_VALUE (symbolP, (valueT) size);
3695 S_SET_EXTERNAL (symbolP);
3696 #endif
3698 know (symbol_get_frag (symbolP) == &zero_address_frag);
3699 if (*input_line_pointer != ',')
3701 as_bad (_("Expected comma after common length"));
3702 ignore_rest_of_line ();
3703 return;
3705 input_line_pointer++;
3706 SKIP_WHITESPACE ();
3707 if (*input_line_pointer != '"')
3709 temp = get_absolute_expression ();
3711 #ifndef OBJ_ELF
3712 if (temp > max_alignment)
3714 temp = max_alignment;
3715 as_warn (_("alignment too large; assuming %d"), temp);
3717 #endif
3719 if (temp < 0)
3721 as_bad (_("negative alignment"));
3722 ignore_rest_of_line ();
3723 return;
3726 #ifdef OBJ_ELF
3727 if (symbol_get_obj (symbolP)->local)
3729 segT old_sec;
3730 int old_subsec;
3731 char *p;
3732 int align;
3734 old_sec = now_seg;
3735 old_subsec = now_subseg;
3737 if (temp == 0)
3738 align = 0;
3739 else
3740 align = log2 (temp);
3742 if (align < 0)
3744 as_bad (_("alignment not a power of 2"));
3745 ignore_rest_of_line ();
3746 return;
3749 record_alignment (bss_section, align);
3750 subseg_set (bss_section, 0);
3751 if (align)
3752 frag_align (align, 0, 0);
3753 if (S_GET_SEGMENT (symbolP) == bss_section)
3754 symbol_get_frag (symbolP)->fr_symbol = 0;
3755 symbol_set_frag (symbolP, frag_now);
3756 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3757 (offsetT) size, (char *) 0);
3758 *p = 0;
3759 S_SET_SEGMENT (symbolP, bss_section);
3760 S_CLEAR_EXTERNAL (symbolP);
3761 S_SET_SIZE (symbolP, size);
3762 subseg_set (old_sec, old_subsec);
3764 else
3765 #endif /* OBJ_ELF */
3767 allocate_common:
3768 S_SET_VALUE (symbolP, (valueT) size);
3769 #ifdef OBJ_ELF
3770 S_SET_ALIGN (symbolP, temp);
3771 S_SET_SIZE (symbolP, size);
3772 #endif
3773 S_SET_EXTERNAL (symbolP);
3774 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3777 else
3779 input_line_pointer++;
3780 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3781 if (*input_line_pointer == '.')
3782 input_line_pointer++;
3783 /* @@ Some say data, some say bss. */
3784 if (strncmp (input_line_pointer, "bss\"", 4)
3785 && strncmp (input_line_pointer, "data\"", 5))
3787 while (*--input_line_pointer != '"')
3789 input_line_pointer--;
3790 goto bad_common_segment;
3792 while (*input_line_pointer++ != '"')
3794 goto allocate_common;
3797 #ifdef BFD_ASSEMBLER
3798 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3799 #endif
3801 demand_empty_rest_of_line ();
3802 return;
3805 bad_common_segment:
3806 p = input_line_pointer;
3807 while (*p && *p != '\n')
3808 p++;
3809 c = *p;
3810 *p = '\0';
3811 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3812 *p = c;
3813 input_line_pointer = p;
3814 ignore_rest_of_line ();
3815 return;
3819 /* Handle the .empty pseudo-op. This supresses the warnings about
3820 invalid delay slot usage. */
3822 static void
3823 s_empty (ignore)
3824 int ignore ATTRIBUTE_UNUSED;
3826 /* The easy way to implement is to just forget about the last
3827 instruction. */
3828 last_insn = NULL;
3831 static void
3832 s_seg (ignore)
3833 int ignore ATTRIBUTE_UNUSED;
3836 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3838 input_line_pointer += 6;
3839 s_text (0);
3840 return;
3842 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3844 input_line_pointer += 6;
3845 s_data (0);
3846 return;
3848 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3850 input_line_pointer += 7;
3851 s_data1 ();
3852 return;
3854 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3856 input_line_pointer += 5;
3857 /* We only support 2 segments -- text and data -- for now, so
3858 things in the "bss segment" will have to go into data for now.
3859 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3860 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
3861 return;
3863 as_bad (_("Unknown segment type"));
3864 demand_empty_rest_of_line ();
3867 static void
3868 s_data1 ()
3870 subseg_set (data_section, 1);
3871 demand_empty_rest_of_line ();
3874 static void
3875 s_proc (ignore)
3876 int ignore ATTRIBUTE_UNUSED;
3878 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3880 ++input_line_pointer;
3882 ++input_line_pointer;
3885 /* This static variable is set by s_uacons to tell sparc_cons_align
3886 that the expession does not need to be aligned. */
3888 static int sparc_no_align_cons = 0;
3890 /* This static variable is set by sparc_cons to emit requested types
3891 of relocations in cons_fix_new_sparc. */
3893 static const char *sparc_cons_special_reloc;
3895 /* This handles the unaligned space allocation pseudo-ops, such as
3896 .uaword. .uaword is just like .word, but the value does not need
3897 to be aligned. */
3899 static void
3900 s_uacons (bytes)
3901 int bytes;
3903 /* Tell sparc_cons_align not to align this value. */
3904 sparc_no_align_cons = 1;
3905 cons (bytes);
3906 sparc_no_align_cons = 0;
3909 /* This handles the native word allocation pseudo-op .nword.
3910 For sparc_arch_size 32 it is equivalent to .word, for
3911 sparc_arch_size 64 it is equivalent to .xword. */
3913 static void
3914 s_ncons (bytes)
3915 int bytes ATTRIBUTE_UNUSED;
3917 cons (sparc_arch_size == 32 ? 4 : 8);
3920 #ifdef OBJ_ELF
3921 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3922 global register.
3923 The syntax is:
3925 .register %g[2367],{#scratch|symbolname|#ignore}
3928 static void
3929 s_register (ignore)
3930 int ignore ATTRIBUTE_UNUSED;
3932 char c;
3933 int reg;
3934 int flags;
3935 const char *regname;
3937 if (input_line_pointer[0] != '%'
3938 || input_line_pointer[1] != 'g'
3939 || ((input_line_pointer[2] & ~1) != '2'
3940 && (input_line_pointer[2] & ~1) != '6')
3941 || input_line_pointer[3] != ',')
3942 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3943 reg = input_line_pointer[2] - '0';
3944 input_line_pointer += 4;
3946 if (*input_line_pointer == '#')
3948 ++input_line_pointer;
3949 regname = input_line_pointer;
3950 c = get_symbol_end ();
3951 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3952 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3953 if (regname[0] == 'i')
3954 regname = NULL;
3955 else
3956 regname = "";
3958 else
3960 regname = input_line_pointer;
3961 c = get_symbol_end ();
3963 if (sparc_arch_size == 64)
3965 if (globals[reg])
3967 if ((regname && globals[reg] != (symbolS *) 1
3968 && strcmp (S_GET_NAME (globals[reg]), regname))
3969 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
3970 as_bad (_("redefinition of global register"));
3972 else
3974 if (regname == NULL)
3975 globals[reg] = (symbolS *) 1;
3976 else
3978 if (*regname)
3980 if (symbol_find (regname))
3981 as_bad (_("Register symbol %s already defined."),
3982 regname);
3984 globals[reg] = symbol_make (regname);
3985 flags = symbol_get_bfdsym (globals[reg])->flags;
3986 if (! *regname)
3987 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3988 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3989 flags |= BSF_GLOBAL;
3990 symbol_get_bfdsym (globals[reg])->flags = flags;
3991 S_SET_VALUE (globals[reg], (valueT) reg);
3992 S_SET_ALIGN (globals[reg], reg);
3993 S_SET_SIZE (globals[reg], 0);
3994 /* Although we actually want undefined_section here,
3995 we have to use absolute_section, because otherwise
3996 generic as code will make it a COM section.
3997 We fix this up in sparc_adjust_symtab. */
3998 S_SET_SEGMENT (globals[reg], absolute_section);
3999 S_SET_OTHER (globals[reg], 0);
4000 elf_symbol (symbol_get_bfdsym (globals[reg]))
4001 ->internal_elf_sym.st_info =
4002 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4003 elf_symbol (symbol_get_bfdsym (globals[reg]))
4004 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4009 *input_line_pointer = c;
4011 demand_empty_rest_of_line ();
4014 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4015 symbols which need it. */
4017 void
4018 sparc_adjust_symtab ()
4020 symbolS *sym;
4022 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4024 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4025 ->internal_elf_sym.st_info) != STT_REGISTER)
4026 continue;
4028 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4029 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4030 continue;
4032 S_SET_SEGMENT (sym, undefined_section);
4035 #endif
4037 /* If the --enforce-aligned-data option is used, we require .word,
4038 et. al., to be aligned correctly. We do it by setting up an
4039 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4040 no unexpected alignment was introduced.
4042 The SunOS and Solaris native assemblers enforce aligned data by
4043 default. We don't want to do that, because gcc can deliberately
4044 generate misaligned data if the packed attribute is used. Instead,
4045 we permit misaligned data by default, and permit the user to set an
4046 option to check for it. */
4048 void
4049 sparc_cons_align (nbytes)
4050 int nbytes;
4052 int nalign;
4053 char *p;
4055 /* Only do this if we are enforcing aligned data. */
4056 if (! enforce_aligned_data)
4057 return;
4059 /* Don't align if this is an unaligned pseudo-op. */
4060 if (sparc_no_align_cons)
4061 return;
4063 nalign = log2 (nbytes);
4064 if (nalign == 0)
4065 return;
4067 assert (nalign > 0);
4069 if (now_seg == absolute_section)
4071 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4072 as_bad (_("misaligned data"));
4073 return;
4076 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4077 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4079 record_alignment (now_seg, nalign);
4082 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4084 void
4085 sparc_handle_align (fragp)
4086 fragS *fragp;
4088 int count, fix;
4089 char *p;
4091 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4093 switch (fragp->fr_type)
4095 case rs_align_test:
4096 if (count != 0)
4097 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4098 break;
4100 case rs_align_code:
4101 p = fragp->fr_literal + fragp->fr_fix;
4102 fix = 0;
4104 if (count & 3)
4106 fix = count & 3;
4107 memset (p, 0, fix);
4108 p += fix;
4109 count -= fix;
4112 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4114 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4115 if (INSN_BIG_ENDIAN)
4116 number_to_chars_bigendian (p, wval, 4);
4117 else
4118 number_to_chars_littleendian (p, wval, 4);
4119 p += 4;
4120 count -= 4;
4121 fix += 4;
4124 if (INSN_BIG_ENDIAN)
4125 number_to_chars_bigendian (p, 0x01000000, 4);
4126 else
4127 number_to_chars_littleendian (p, 0x01000000, 4);
4129 fragp->fr_fix += fix;
4130 fragp->fr_var = 4;
4131 break;
4133 default:
4134 break;
4138 #ifdef OBJ_ELF
4139 /* Some special processing for a Sparc ELF file. */
4141 void
4142 sparc_elf_final_processing ()
4144 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4145 sort of BFD interface for this. */
4146 if (sparc_arch_size == 64)
4148 switch (sparc_memory_model)
4150 case MM_RMO:
4151 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4152 break;
4153 case MM_PSO:
4154 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4155 break;
4156 default:
4157 break;
4160 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4161 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4162 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4163 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4164 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4165 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4168 void
4169 sparc_cons (exp, size)
4170 expressionS *exp;
4171 int size;
4173 char *save;
4175 SKIP_WHITESPACE ();
4176 sparc_cons_special_reloc = NULL;
4177 save = input_line_pointer;
4178 if (input_line_pointer[0] == '%'
4179 && input_line_pointer[1] == 'r'
4180 && input_line_pointer[2] == '_')
4182 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4184 input_line_pointer += 7;
4185 sparc_cons_special_reloc = "disp";
4187 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4189 if (size != 4 && size != 8)
4190 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4191 else
4193 input_line_pointer += 6;
4194 sparc_cons_special_reloc = "plt";
4197 if (sparc_cons_special_reloc)
4199 int bad = 0;
4201 switch (size)
4203 case 1:
4204 if (*input_line_pointer != '8')
4205 bad = 1;
4206 input_line_pointer--;
4207 break;
4208 case 2:
4209 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4210 bad = 1;
4211 break;
4212 case 4:
4213 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4214 bad = 1;
4215 break;
4216 case 8:
4217 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4218 bad = 1;
4219 break;
4220 default:
4221 bad = 1;
4222 break;
4225 if (bad)
4227 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4228 sparc_cons_special_reloc, size * 8, size);
4230 else
4232 input_line_pointer += 2;
4233 if (*input_line_pointer != '(')
4235 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4236 sparc_cons_special_reloc, size * 8);
4237 bad = 1;
4241 if (bad)
4243 input_line_pointer = save;
4244 sparc_cons_special_reloc = NULL;
4246 else
4248 int c;
4249 char *end = ++input_line_pointer;
4250 int npar = 0;
4252 while (! is_end_of_line[(c = *end)])
4254 if (c == '(')
4255 npar++;
4256 else if (c == ')')
4258 if (!npar)
4259 break;
4260 npar--;
4262 end++;
4265 if (c != ')')
4266 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4267 sparc_cons_special_reloc, size * 8);
4268 else
4270 *end = '\0';
4271 expression (exp);
4272 *end = c;
4273 if (input_line_pointer != end)
4275 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4276 sparc_cons_special_reloc, size * 8);
4278 else
4280 input_line_pointer++;
4281 SKIP_WHITESPACE ();
4282 c = *input_line_pointer;
4283 if (! is_end_of_line[c] && c != ',')
4284 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4285 sparc_cons_special_reloc, size * 8);
4291 if (sparc_cons_special_reloc == NULL)
4292 expression (exp);
4295 #endif
4297 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4298 reloc for a cons. We could use the definition there, except that
4299 we want to handle little endian relocs specially. */
4301 void
4302 cons_fix_new_sparc (frag, where, nbytes, exp)
4303 fragS *frag;
4304 int where;
4305 unsigned int nbytes;
4306 expressionS *exp;
4308 bfd_reloc_code_real_type r;
4310 r = (nbytes == 1 ? BFD_RELOC_8 :
4311 (nbytes == 2 ? BFD_RELOC_16 :
4312 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4314 if (target_little_endian_data
4315 && nbytes == 4
4316 && now_seg->flags & SEC_ALLOC)
4317 r = BFD_RELOC_SPARC_REV32;
4319 if (sparc_cons_special_reloc)
4321 if (*sparc_cons_special_reloc == 'd')
4322 switch (nbytes)
4324 case 1: r = BFD_RELOC_8_PCREL; break;
4325 case 2: r = BFD_RELOC_16_PCREL; break;
4326 case 4: r = BFD_RELOC_32_PCREL; break;
4327 case 8: r = BFD_RELOC_64_PCREL; break;
4328 default: abort ();
4330 else
4331 switch (nbytes)
4333 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4334 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4337 else if (sparc_no_align_cons)
4339 switch (nbytes)
4341 case 2: r = BFD_RELOC_SPARC_UA16; break;
4342 case 4: r = BFD_RELOC_SPARC_UA32; break;
4343 case 8: r = BFD_RELOC_SPARC_UA64; break;
4344 default: abort ();
4348 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4351 #ifdef OBJ_ELF
4353 elf32_sparc_force_relocation (fixp)
4354 struct fix *fixp;
4356 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4357 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4358 return 1;
4360 return S_FORCE_RELOC (fixp->fx_addsy);
4362 #endif