gas/config/m68k-parse.h

   1 /* m68k-parse.h -- header file for m68k assembler
   2    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
   3    2003 Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #ifndef M68K_PARSE_H
  23 #define M68K_PARSE_H
  24
  25 /* This header file defines things which are shared between the
  26    operand parser in m68k.y and the m68k assembler proper in
  27    tc-m68k.c.  */
  28
  29 /* The various m68k registers.  */
  30
  31 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
  32    0-7==data reg, 8-15==addr reg for operands that take both types.
  33
  34    We don't use forms like "ADDR0 = ADDR" here because this file is
  35    likely to be used on an Apollo, and the broken Apollo compiler
  36    gives an `undefined variable' error if we do that, according to
  37    troy@cbme.unsw.edu.au.  */
  38
  39 #define DATA DATA0
  40 #define ADDR ADDR0
  41 #define SP ADDR7
  42 #define BAD BAD0
  43 #define BAC BAC0
  44
  45 enum m68k_register
  46 {
  47   DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
  48   DATA1,
  49   DATA2,
  50   DATA3,
  51   DATA4,
  52   DATA5,
  53   DATA6,
  54   DATA7,
  55
  56   ADDR0,
  57   ADDR1,
  58   ADDR2,
  59   ADDR3,
  60   ADDR4,
  61   ADDR5,
  62   ADDR6,
  63   ADDR7,
  64
  65   FP0,                          /* Eight FP registers */
  66   FP1,
  67   FP2,
  68   FP3,
  69   FP4,
  70   FP5,
  71   FP6,
  72   FP7,
  73
  74   COP0,                         /* Co-processor #0-#7 */
  75   COP1,
  76   COP2,
  77   COP3,
  78   COP4,
  79   COP5,
  80   COP6,
  81   COP7,
  82
  83   PC,                           /* Program counter */
  84   ZPC,                          /* Hack for Program space, but 0 addressing */
  85   SR,                           /* Status Reg */
  86   CCR,                          /* Condition code Reg */
  87   ACC,                          /* Accumulator Reg */
  88   MACSR,                        /* MAC Status Reg */
  89   MASK,                         /* Modulus Reg */
  90
  91   /* These have to be grouped together for the movec instruction to work.  */
  92   USP,                          /*  User Stack Pointer */
  93   ISP,                          /*  Interrupt stack pointer */
  94   SFC,
  95   DFC,
  96   CACR,
  97   VBR,
  98   CAAR,
  99   MSP,
 100   ITT0,
 101   ITT1,
 102   DTT0,
 103   DTT1,
 104   MMUSR,
 105   TC,
 106   SRP,
 107   URP,
 108   BUSCR,                        /* 68060 added these.  */
 109   PCR,
 110   ROMBAR,                       /* mcf5200 added these.  */
 111   RAMBAR0,
 112   RAMBAR1,
 113   MMUBAR,                       /* mcfv4e added these.  */
 114   ROMBAR1,                      /* mcfv4e added these.  */
 115   MPCR, EDRAMBAR, SECMBAR,      /* mcfv4e added these.  */
 116   PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
 117   PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
 118   PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
 119   MBAR0, MBAR1,                 /* mcfv4e added these.  */
 120   ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
 121   FLASHBAR, RAMBAR,             /* mcf528x added these.  */
 122   MBAR,
 123 #define last_movec_reg MBAR
 124   /* End of movec ordering constraints.  */
 125
 126   FPI,
 127   FPS,
 128   FPC,
 129
 130   DRP,                          /* 68851 or 68030 MMU regs */
 131   CRP,
 132   CAL,
 133   VAL,
 134   SCC,
 135   AC,
 136   BAD0,
 137   BAD1,
 138   BAD2,
 139   BAD3,
 140   BAD4,
 141   BAD5,
 142   BAD6,
 143   BAD7,
 144   BAC0,
 145   BAC1,
 146   BAC2,
 147   BAC3,
 148   BAC4,
 149   BAC5,
 150   BAC6,
 151   BAC7,
 152   PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
 153                                    and ACUSR on 68ec030 */
 154   PCSR,
 155
 156   IC,                           /* instruction cache token */
 157   DC,                           /* data cache token */
 158   NC,                           /* no cache token */
 159   BC,                           /* both caches token */
 160
 161   TT0,                          /* 68030 access control unit regs */
 162   TT1,
 163
 164   ZDATA0,                       /* suppressed data registers.  */
 165   ZDATA1,
 166   ZDATA2,
 167   ZDATA3,
 168   ZDATA4,
 169   ZDATA5,
 170   ZDATA6,
 171   ZDATA7,
 172
 173   ZADDR0,                       /* suppressed address registers.  */
 174   ZADDR1,
 175   ZADDR2,
 176   ZADDR3,
 177   ZADDR4,
 178   ZADDR5,
 179   ZADDR6,
 180   ZADDR7,
 181
 182   /* Upper and lower half of data and address registers.  Order *must*
 183      be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
 184   DATA0L,                       /* lower half of data registers */
 185   DATA1L,
 186   DATA2L,
 187   DATA3L,
 188   DATA4L,
 189   DATA5L,
 190   DATA6L,
 191   DATA7L,
 192
 193   ADDR0L,                       /* lower half of address registers */
 194   ADDR1L,
 195   ADDR2L,
 196   ADDR3L,
 197   ADDR4L,
 198   ADDR5L,
 199   ADDR6L,
 200   ADDR7L,
 201
 202   DATA0U,                       /* upper half of data registers */
 203   DATA1U,
 204   DATA2U,
 205   DATA3U,
 206   DATA4U,
 207   DATA5U,
 208   DATA6U,
 209   DATA7U,
 210
 211   ADDR0U,                       /* upper half of address registers */
 212   ADDR1U,
 213   ADDR2U,
 214   ADDR3U,
 215   ADDR4U,
 216   ADDR5U,
 217   ADDR6U,
 218   ADDR7U,
 219 };
 220
 221 /* Size information.  */
 222
 223 enum m68k_size
 224 {
 225   /* Unspecified.  */
 226   SIZE_UNSPEC,
 227
 228   /* Byte.  */
 229   SIZE_BYTE,
 230
 231   /* Word (2 bytes).  */
 232   SIZE_WORD,
 233
 234   /* Longword (4 bytes).  */
 235   SIZE_LONG
 236 };
 237
 238 /* The structure used to hold information about an index register.  */
 239
 240 struct m68k_indexreg
 241 {
 242   /* The index register itself.  */
 243   enum m68k_register reg;
 244
 245   /* The size to use.  */
 246   enum m68k_size size;
 247
 248   /* The value to scale by.  */
 249   int scale;
 250 };
 251
 252 #ifdef OBJ_ELF
 253 /* The type of a PIC expression.  */
 254
 255 enum pic_relocation
 256 {
 257   pic_none,                     /* not pic */
 258   pic_plt_pcrel,                /* @PLTPC */
 259   pic_got_pcrel,                /* @GOTPC */
 260   pic_plt_off,                  /* @PLT */
 261   pic_got_off                   /* @GOT */
 262 };
 263 #endif
 264
 265 /* The structure used to hold information about an expression.  */
 266
 267 struct m68k_exp
 268 {
 269   /* The size to use.  */
 270   enum m68k_size size;
 271
 272 #ifdef OBJ_ELF
 273   /* The type of pic relocation if any.  */
 274   enum pic_relocation pic_reloc;
 275 #endif
 276
 277   /* The expression itself.  */
 278   expressionS exp;
 279 };
 280
 281 /* The operand modes.  */
 282
 283 enum m68k_operand_type
 284 {
 285   IMMED = 1,
 286   ABSL,
 287   DREG,
 288   AREG,
 289   FPREG,
 290   CONTROL,
 291   AINDR,
 292   AINC,
 293   ADEC,
 294   DISP,
 295   BASE,
 296   POST,
 297   PRE,
 298   REGLST
 299 };
 300
 301 /* The structure used to hold a parsed operand.  */
 302
 303 struct m68k_op
 304 {
 305   /* The type of operand.  */
 306   enum m68k_operand_type mode;
 307
 308   /* The main register.  */
 309   enum m68k_register reg;
 310
 311   /* The register mask for mode REGLST.  */
 312   unsigned long mask;
 313
 314   /* An error message.  */
 315   const char *error;
 316
 317   /* The index register.  */
 318   struct m68k_indexreg index;
 319
 320   /* The displacement.  */
 321   struct m68k_exp disp;
 322
 323   /* The outer displacement.  */
 324   struct m68k_exp odisp;
 325 };
 326
 327 #endif /* ! defined (M68K_PARSE_H) */
 328
 329 /* The parsing function.  */
 330
 331 extern int m68k_ip_op PARAMS ((char *, struct m68k_op *));
 332
 333 /* Whether register prefixes are optional.  */
 334 extern int flag_reg_prefix_optional;