merge from gcc
[binutils.git] / opcodes / m32r-opc.c
bloba18d5ccefa8cf28b66e31395f827b35aa7b0d76e
1 /* Instruction opcode table for m32r.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #include "sysdep.h"
26 #include "ansidecl.h"
27 #include "bfd.h"
28 #include "symcat.h"
29 #include "m32r-desc.h"
30 #include "m32r-opc.h"
31 #include "libiberty.h"
33 /* -- opc.c */
34 unsigned int
35 m32r_cgen_dis_hash (buf, value)
36 const char * buf ATTRIBUTE_UNUSED;
37 CGEN_INSN_INT value;
39 unsigned int x;
41 if (value & 0xffff0000) /* 32bit instructions */
42 value = (value >> 16) & 0xffff;
44 x = (value>>8) & 0xf0;
45 if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
46 return x;
48 if (x == 0x70 || x == 0xf0)
49 return x | ((value>>8) & 0x0f);
51 if (x == 0x30)
52 return x | ((value & 0x70) >> 4);
53 else
54 return x | ((value & 0xf0) >> 4);
57 /* -- */
58 /* The hash functions are recorded here to help keep assembler code out of
59 the disassembler and vice versa. */
61 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
62 static unsigned int asm_hash_insn PARAMS ((const char *));
63 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
64 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
66 /* Instruction formats. */
68 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
69 #define F(f) & m32r_cgen_ifld_table[M32R_##f]
70 #else
71 #define F(f) & m32r_cgen_ifld_table[M32R_/**/f]
72 #endif
73 static const CGEN_IFMT ifmt_empty = {
74 0, 0, 0x0, { { 0 } }
77 static const CGEN_IFMT ifmt_add = {
78 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
81 static const CGEN_IFMT ifmt_add3 = {
82 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
85 static const CGEN_IFMT ifmt_and3 = {
86 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
89 static const CGEN_IFMT ifmt_or3 = {
90 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
93 static const CGEN_IFMT ifmt_addi = {
94 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
97 static const CGEN_IFMT ifmt_addv3 = {
98 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
101 static const CGEN_IFMT ifmt_bc8 = {
102 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
105 static const CGEN_IFMT ifmt_bc24 = {
106 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
109 static const CGEN_IFMT ifmt_beq = {
110 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
113 static const CGEN_IFMT ifmt_beqz = {
114 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
117 static const CGEN_IFMT ifmt_cmp = {
118 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
121 static const CGEN_IFMT ifmt_cmpi = {
122 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
125 static const CGEN_IFMT ifmt_cmpz = {
126 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
129 static const CGEN_IFMT ifmt_div = {
130 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
133 static const CGEN_IFMT ifmt_jc = {
134 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
137 static const CGEN_IFMT ifmt_ld24 = {
138 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } }
141 static const CGEN_IFMT ifmt_ldi16 = {
142 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
145 static const CGEN_IFMT ifmt_machi_a = {
146 16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } }
149 static const CGEN_IFMT ifmt_mvfachi = {
150 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
153 static const CGEN_IFMT ifmt_mvfachi_a = {
154 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
157 static const CGEN_IFMT ifmt_mvfc = {
158 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
161 static const CGEN_IFMT ifmt_mvtachi = {
162 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
165 static const CGEN_IFMT ifmt_mvtachi_a = {
166 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
169 static const CGEN_IFMT ifmt_mvtc = {
170 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
173 static const CGEN_IFMT ifmt_nop = {
174 16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
177 static const CGEN_IFMT ifmt_rac_dsi = {
178 16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
181 static const CGEN_IFMT ifmt_seth = {
182 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } }
185 static const CGEN_IFMT ifmt_slli = {
186 16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } }
189 static const CGEN_IFMT ifmt_st_d = {
190 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
193 static const CGEN_IFMT ifmt_trap = {
194 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } }
197 static const CGEN_IFMT ifmt_satb = {
198 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
201 static const CGEN_IFMT ifmt_clrpsw = {
202 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } }
205 static const CGEN_IFMT ifmt_bset = {
206 32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
209 static const CGEN_IFMT ifmt_btst = {
210 16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
213 #undef F
215 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
216 #define A(a) (1 << CGEN_INSN_##a)
217 #else
218 #define A(a) (1 << CGEN_INSN_/**/a)
219 #endif
220 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
221 #define OPERAND(op) M32R_OPERAND_##op
222 #else
223 #define OPERAND(op) M32R_OPERAND_/**/op
224 #endif
225 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
226 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
228 /* The instruction table. */
230 static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
232 /* Special null first entry.
233 A `num' value of zero is thus invalid.
234 Also, the special `invalid' insn resides here. */
235 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
236 /* add $dr,$sr */
238 { 0, 0, 0, 0 },
239 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
240 & ifmt_add, { 0xa0 }
242 /* add3 $dr,$sr,$hash$slo16 */
244 { 0, 0, 0, 0 },
245 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
246 & ifmt_add3, { 0x80a00000 }
248 /* and $dr,$sr */
250 { 0, 0, 0, 0 },
251 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
252 & ifmt_add, { 0xc0 }
254 /* and3 $dr,$sr,$uimm16 */
256 { 0, 0, 0, 0 },
257 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
258 & ifmt_and3, { 0x80c00000 }
260 /* or $dr,$sr */
262 { 0, 0, 0, 0 },
263 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
264 & ifmt_add, { 0xe0 }
266 /* or3 $dr,$sr,$hash$ulo16 */
268 { 0, 0, 0, 0 },
269 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
270 & ifmt_or3, { 0x80e00000 }
272 /* xor $dr,$sr */
274 { 0, 0, 0, 0 },
275 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
276 & ifmt_add, { 0xd0 }
278 /* xor3 $dr,$sr,$uimm16 */
280 { 0, 0, 0, 0 },
281 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
282 & ifmt_and3, { 0x80d00000 }
284 /* addi $dr,$simm8 */
286 { 0, 0, 0, 0 },
287 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
288 & ifmt_addi, { 0x4000 }
290 /* addv $dr,$sr */
292 { 0, 0, 0, 0 },
293 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
294 & ifmt_add, { 0x80 }
296 /* addv3 $dr,$sr,$simm16 */
298 { 0, 0, 0, 0 },
299 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
300 & ifmt_addv3, { 0x80800000 }
302 /* addx $dr,$sr */
304 { 0, 0, 0, 0 },
305 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
306 & ifmt_add, { 0x90 }
308 /* bc.s $disp8 */
310 { 0, 0, 0, 0 },
311 { { MNEM, ' ', OP (DISP8), 0 } },
312 & ifmt_bc8, { 0x7c00 }
314 /* bc.l $disp24 */
316 { 0, 0, 0, 0 },
317 { { MNEM, ' ', OP (DISP24), 0 } },
318 & ifmt_bc24, { 0xfc000000 }
320 /* beq $src1,$src2,$disp16 */
322 { 0, 0, 0, 0 },
323 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
324 & ifmt_beq, { 0xb0000000 }
326 /* beqz $src2,$disp16 */
328 { 0, 0, 0, 0 },
329 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
330 & ifmt_beqz, { 0xb0800000 }
332 /* bgez $src2,$disp16 */
334 { 0, 0, 0, 0 },
335 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
336 & ifmt_beqz, { 0xb0b00000 }
338 /* bgtz $src2,$disp16 */
340 { 0, 0, 0, 0 },
341 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
342 & ifmt_beqz, { 0xb0d00000 }
344 /* blez $src2,$disp16 */
346 { 0, 0, 0, 0 },
347 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
348 & ifmt_beqz, { 0xb0c00000 }
350 /* bltz $src2,$disp16 */
352 { 0, 0, 0, 0 },
353 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
354 & ifmt_beqz, { 0xb0a00000 }
356 /* bnez $src2,$disp16 */
358 { 0, 0, 0, 0 },
359 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
360 & ifmt_beqz, { 0xb0900000 }
362 /* bl.s $disp8 */
364 { 0, 0, 0, 0 },
365 { { MNEM, ' ', OP (DISP8), 0 } },
366 & ifmt_bc8, { 0x7e00 }
368 /* bl.l $disp24 */
370 { 0, 0, 0, 0 },
371 { { MNEM, ' ', OP (DISP24), 0 } },
372 & ifmt_bc24, { 0xfe000000 }
374 /* bcl.s $disp8 */
376 { 0, 0, 0, 0 },
377 { { MNEM, ' ', OP (DISP8), 0 } },
378 & ifmt_bc8, { 0x7800 }
380 /* bcl.l $disp24 */
382 { 0, 0, 0, 0 },
383 { { MNEM, ' ', OP (DISP24), 0 } },
384 & ifmt_bc24, { 0xf8000000 }
386 /* bnc.s $disp8 */
388 { 0, 0, 0, 0 },
389 { { MNEM, ' ', OP (DISP8), 0 } },
390 & ifmt_bc8, { 0x7d00 }
392 /* bnc.l $disp24 */
394 { 0, 0, 0, 0 },
395 { { MNEM, ' ', OP (DISP24), 0 } },
396 & ifmt_bc24, { 0xfd000000 }
398 /* bne $src1,$src2,$disp16 */
400 { 0, 0, 0, 0 },
401 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
402 & ifmt_beq, { 0xb0100000 }
404 /* bra.s $disp8 */
406 { 0, 0, 0, 0 },
407 { { MNEM, ' ', OP (DISP8), 0 } },
408 & ifmt_bc8, { 0x7f00 }
410 /* bra.l $disp24 */
412 { 0, 0, 0, 0 },
413 { { MNEM, ' ', OP (DISP24), 0 } },
414 & ifmt_bc24, { 0xff000000 }
416 /* bncl.s $disp8 */
418 { 0, 0, 0, 0 },
419 { { MNEM, ' ', OP (DISP8), 0 } },
420 & ifmt_bc8, { 0x7900 }
422 /* bncl.l $disp24 */
424 { 0, 0, 0, 0 },
425 { { MNEM, ' ', OP (DISP24), 0 } },
426 & ifmt_bc24, { 0xf9000000 }
428 /* cmp $src1,$src2 */
430 { 0, 0, 0, 0 },
431 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
432 & ifmt_cmp, { 0x40 }
434 /* cmpi $src2,$simm16 */
436 { 0, 0, 0, 0 },
437 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
438 & ifmt_cmpi, { 0x80400000 }
440 /* cmpu $src1,$src2 */
442 { 0, 0, 0, 0 },
443 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
444 & ifmt_cmp, { 0x50 }
446 /* cmpui $src2,$simm16 */
448 { 0, 0, 0, 0 },
449 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
450 & ifmt_cmpi, { 0x80500000 }
452 /* cmpeq $src1,$src2 */
454 { 0, 0, 0, 0 },
455 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
456 & ifmt_cmp, { 0x60 }
458 /* cmpz $src2 */
460 { 0, 0, 0, 0 },
461 { { MNEM, ' ', OP (SRC2), 0 } },
462 & ifmt_cmpz, { 0x70 }
464 /* div $dr,$sr */
466 { 0, 0, 0, 0 },
467 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
468 & ifmt_div, { 0x90000000 }
470 /* divu $dr,$sr */
472 { 0, 0, 0, 0 },
473 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
474 & ifmt_div, { 0x90100000 }
476 /* rem $dr,$sr */
478 { 0, 0, 0, 0 },
479 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
480 & ifmt_div, { 0x90200000 }
482 /* remu $dr,$sr */
484 { 0, 0, 0, 0 },
485 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
486 & ifmt_div, { 0x90300000 }
488 /* remh $dr,$sr */
490 { 0, 0, 0, 0 },
491 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
492 & ifmt_div, { 0x90200010 }
494 /* remuh $dr,$sr */
496 { 0, 0, 0, 0 },
497 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
498 & ifmt_div, { 0x90300010 }
500 /* remb $dr,$sr */
502 { 0, 0, 0, 0 },
503 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
504 & ifmt_div, { 0x90200018 }
506 /* remub $dr,$sr */
508 { 0, 0, 0, 0 },
509 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
510 & ifmt_div, { 0x90300018 }
512 /* divuh $dr,$sr */
514 { 0, 0, 0, 0 },
515 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
516 & ifmt_div, { 0x90100010 }
518 /* divb $dr,$sr */
520 { 0, 0, 0, 0 },
521 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
522 & ifmt_div, { 0x90000018 }
524 /* divub $dr,$sr */
526 { 0, 0, 0, 0 },
527 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
528 & ifmt_div, { 0x90100018 }
530 /* divh $dr,$sr */
532 { 0, 0, 0, 0 },
533 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
534 & ifmt_div, { 0x90000010 }
536 /* jc $sr */
538 { 0, 0, 0, 0 },
539 { { MNEM, ' ', OP (SR), 0 } },
540 & ifmt_jc, { 0x1cc0 }
542 /* jnc $sr */
544 { 0, 0, 0, 0 },
545 { { MNEM, ' ', OP (SR), 0 } },
546 & ifmt_jc, { 0x1dc0 }
548 /* jl $sr */
550 { 0, 0, 0, 0 },
551 { { MNEM, ' ', OP (SR), 0 } },
552 & ifmt_jc, { 0x1ec0 }
554 /* jmp $sr */
556 { 0, 0, 0, 0 },
557 { { MNEM, ' ', OP (SR), 0 } },
558 & ifmt_jc, { 0x1fc0 }
560 /* ld $dr,@$sr */
562 { 0, 0, 0, 0 },
563 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
564 & ifmt_add, { 0x20c0 }
566 /* ld $dr,@($slo16,$sr) */
568 { 0, 0, 0, 0 },
569 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
570 & ifmt_add3, { 0xa0c00000 }
572 /* ldb $dr,@$sr */
574 { 0, 0, 0, 0 },
575 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
576 & ifmt_add, { 0x2080 }
578 /* ldb $dr,@($slo16,$sr) */
580 { 0, 0, 0, 0 },
581 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
582 & ifmt_add3, { 0xa0800000 }
584 /* ldh $dr,@$sr */
586 { 0, 0, 0, 0 },
587 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
588 & ifmt_add, { 0x20a0 }
590 /* ldh $dr,@($slo16,$sr) */
592 { 0, 0, 0, 0 },
593 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
594 & ifmt_add3, { 0xa0a00000 }
596 /* ldub $dr,@$sr */
598 { 0, 0, 0, 0 },
599 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
600 & ifmt_add, { 0x2090 }
602 /* ldub $dr,@($slo16,$sr) */
604 { 0, 0, 0, 0 },
605 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
606 & ifmt_add3, { 0xa0900000 }
608 /* lduh $dr,@$sr */
610 { 0, 0, 0, 0 },
611 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
612 & ifmt_add, { 0x20b0 }
614 /* lduh $dr,@($slo16,$sr) */
616 { 0, 0, 0, 0 },
617 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
618 & ifmt_add3, { 0xa0b00000 }
620 /* ld $dr,@$sr+ */
622 { 0, 0, 0, 0 },
623 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
624 & ifmt_add, { 0x20e0 }
626 /* ld24 $dr,$uimm24 */
628 { 0, 0, 0, 0 },
629 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
630 & ifmt_ld24, { 0xe0000000 }
632 /* ldi8 $dr,$simm8 */
634 { 0, 0, 0, 0 },
635 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
636 & ifmt_addi, { 0x6000 }
638 /* ldi16 $dr,$hash$slo16 */
640 { 0, 0, 0, 0 },
641 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
642 & ifmt_ldi16, { 0x90f00000 }
644 /* lock $dr,@$sr */
646 { 0, 0, 0, 0 },
647 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
648 & ifmt_add, { 0x20d0 }
650 /* machi $src1,$src2 */
652 { 0, 0, 0, 0 },
653 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
654 & ifmt_cmp, { 0x3040 }
656 /* machi $src1,$src2,$acc */
658 { 0, 0, 0, 0 },
659 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
660 & ifmt_machi_a, { 0x3040 }
662 /* maclo $src1,$src2 */
664 { 0, 0, 0, 0 },
665 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
666 & ifmt_cmp, { 0x3050 }
668 /* maclo $src1,$src2,$acc */
670 { 0, 0, 0, 0 },
671 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
672 & ifmt_machi_a, { 0x3050 }
674 /* macwhi $src1,$src2 */
676 { 0, 0, 0, 0 },
677 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
678 & ifmt_cmp, { 0x3060 }
680 /* macwhi $src1,$src2,$acc */
682 { 0, 0, 0, 0 },
683 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
684 & ifmt_machi_a, { 0x3060 }
686 /* macwlo $src1,$src2 */
688 { 0, 0, 0, 0 },
689 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
690 & ifmt_cmp, { 0x3070 }
692 /* macwlo $src1,$src2,$acc */
694 { 0, 0, 0, 0 },
695 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
696 & ifmt_machi_a, { 0x3070 }
698 /* mul $dr,$sr */
700 { 0, 0, 0, 0 },
701 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
702 & ifmt_add, { 0x1060 }
704 /* mulhi $src1,$src2 */
706 { 0, 0, 0, 0 },
707 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
708 & ifmt_cmp, { 0x3000 }
710 /* mulhi $src1,$src2,$acc */
712 { 0, 0, 0, 0 },
713 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
714 & ifmt_machi_a, { 0x3000 }
716 /* mullo $src1,$src2 */
718 { 0, 0, 0, 0 },
719 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
720 & ifmt_cmp, { 0x3010 }
722 /* mullo $src1,$src2,$acc */
724 { 0, 0, 0, 0 },
725 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
726 & ifmt_machi_a, { 0x3010 }
728 /* mulwhi $src1,$src2 */
730 { 0, 0, 0, 0 },
731 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
732 & ifmt_cmp, { 0x3020 }
734 /* mulwhi $src1,$src2,$acc */
736 { 0, 0, 0, 0 },
737 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
738 & ifmt_machi_a, { 0x3020 }
740 /* mulwlo $src1,$src2 */
742 { 0, 0, 0, 0 },
743 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
744 & ifmt_cmp, { 0x3030 }
746 /* mulwlo $src1,$src2,$acc */
748 { 0, 0, 0, 0 },
749 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
750 & ifmt_machi_a, { 0x3030 }
752 /* mv $dr,$sr */
754 { 0, 0, 0, 0 },
755 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
756 & ifmt_add, { 0x1080 }
758 /* mvfachi $dr */
760 { 0, 0, 0, 0 },
761 { { MNEM, ' ', OP (DR), 0 } },
762 & ifmt_mvfachi, { 0x50f0 }
764 /* mvfachi $dr,$accs */
766 { 0, 0, 0, 0 },
767 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
768 & ifmt_mvfachi_a, { 0x50f0 }
770 /* mvfaclo $dr */
772 { 0, 0, 0, 0 },
773 { { MNEM, ' ', OP (DR), 0 } },
774 & ifmt_mvfachi, { 0x50f1 }
776 /* mvfaclo $dr,$accs */
778 { 0, 0, 0, 0 },
779 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
780 & ifmt_mvfachi_a, { 0x50f1 }
782 /* mvfacmi $dr */
784 { 0, 0, 0, 0 },
785 { { MNEM, ' ', OP (DR), 0 } },
786 & ifmt_mvfachi, { 0x50f2 }
788 /* mvfacmi $dr,$accs */
790 { 0, 0, 0, 0 },
791 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
792 & ifmt_mvfachi_a, { 0x50f2 }
794 /* mvfc $dr,$scr */
796 { 0, 0, 0, 0 },
797 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
798 & ifmt_mvfc, { 0x1090 }
800 /* mvtachi $src1 */
802 { 0, 0, 0, 0 },
803 { { MNEM, ' ', OP (SRC1), 0 } },
804 & ifmt_mvtachi, { 0x5070 }
806 /* mvtachi $src1,$accs */
808 { 0, 0, 0, 0 },
809 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
810 & ifmt_mvtachi_a, { 0x5070 }
812 /* mvtaclo $src1 */
814 { 0, 0, 0, 0 },
815 { { MNEM, ' ', OP (SRC1), 0 } },
816 & ifmt_mvtachi, { 0x5071 }
818 /* mvtaclo $src1,$accs */
820 { 0, 0, 0, 0 },
821 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
822 & ifmt_mvtachi_a, { 0x5071 }
824 /* mvtc $sr,$dcr */
826 { 0, 0, 0, 0 },
827 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
828 & ifmt_mvtc, { 0x10a0 }
830 /* neg $dr,$sr */
832 { 0, 0, 0, 0 },
833 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
834 & ifmt_add, { 0x30 }
836 /* nop */
838 { 0, 0, 0, 0 },
839 { { MNEM, 0 } },
840 & ifmt_nop, { 0x7000 }
842 /* not $dr,$sr */
844 { 0, 0, 0, 0 },
845 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
846 & ifmt_add, { 0xb0 }
848 /* rac */
850 { 0, 0, 0, 0 },
851 { { MNEM, 0 } },
852 & ifmt_nop, { 0x5090 }
854 /* rac $accd,$accs,$imm1 */
856 { 0, 0, 0, 0 },
857 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
858 & ifmt_rac_dsi, { 0x5090 }
860 /* rach */
862 { 0, 0, 0, 0 },
863 { { MNEM, 0 } },
864 & ifmt_nop, { 0x5080 }
866 /* rach $accd,$accs,$imm1 */
868 { 0, 0, 0, 0 },
869 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
870 & ifmt_rac_dsi, { 0x5080 }
872 /* rte */
874 { 0, 0, 0, 0 },
875 { { MNEM, 0 } },
876 & ifmt_nop, { 0x10d6 }
878 /* seth $dr,$hash$hi16 */
880 { 0, 0, 0, 0 },
881 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
882 & ifmt_seth, { 0xd0c00000 }
884 /* sll $dr,$sr */
886 { 0, 0, 0, 0 },
887 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
888 & ifmt_add, { 0x1040 }
890 /* sll3 $dr,$sr,$simm16 */
892 { 0, 0, 0, 0 },
893 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
894 & ifmt_addv3, { 0x90c00000 }
896 /* slli $dr,$uimm5 */
898 { 0, 0, 0, 0 },
899 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
900 & ifmt_slli, { 0x5040 }
902 /* sra $dr,$sr */
904 { 0, 0, 0, 0 },
905 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
906 & ifmt_add, { 0x1020 }
908 /* sra3 $dr,$sr,$simm16 */
910 { 0, 0, 0, 0 },
911 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
912 & ifmt_addv3, { 0x90a00000 }
914 /* srai $dr,$uimm5 */
916 { 0, 0, 0, 0 },
917 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
918 & ifmt_slli, { 0x5020 }
920 /* srl $dr,$sr */
922 { 0, 0, 0, 0 },
923 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
924 & ifmt_add, { 0x1000 }
926 /* srl3 $dr,$sr,$simm16 */
928 { 0, 0, 0, 0 },
929 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
930 & ifmt_addv3, { 0x90800000 }
932 /* srli $dr,$uimm5 */
934 { 0, 0, 0, 0 },
935 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
936 & ifmt_slli, { 0x5000 }
938 /* st $src1,@$src2 */
940 { 0, 0, 0, 0 },
941 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
942 & ifmt_cmp, { 0x2040 }
944 /* st $src1,@($slo16,$src2) */
946 { 0, 0, 0, 0 },
947 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
948 & ifmt_st_d, { 0xa0400000 }
950 /* stb $src1,@$src2 */
952 { 0, 0, 0, 0 },
953 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
954 & ifmt_cmp, { 0x2000 }
956 /* stb $src1,@($slo16,$src2) */
958 { 0, 0, 0, 0 },
959 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
960 & ifmt_st_d, { 0xa0000000 }
962 /* sth $src1,@$src2 */
964 { 0, 0, 0, 0 },
965 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
966 & ifmt_cmp, { 0x2020 }
968 /* sth $src1,@($slo16,$src2) */
970 { 0, 0, 0, 0 },
971 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
972 & ifmt_st_d, { 0xa0200000 }
974 /* st $src1,@+$src2 */
976 { 0, 0, 0, 0 },
977 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
978 & ifmt_cmp, { 0x2060 }
980 /* sth $src1,@$src2+ */
982 { 0, 0, 0, 0 },
983 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
984 & ifmt_cmp, { 0x2030 }
986 /* stb $src1,@$src2+ */
988 { 0, 0, 0, 0 },
989 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
990 & ifmt_cmp, { 0x2010 }
992 /* st $src1,@-$src2 */
994 { 0, 0, 0, 0 },
995 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
996 & ifmt_cmp, { 0x2070 }
998 /* sub $dr,$sr */
1000 { 0, 0, 0, 0 },
1001 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1002 & ifmt_add, { 0x20 }
1004 /* subv $dr,$sr */
1006 { 0, 0, 0, 0 },
1007 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1008 & ifmt_add, { 0x0 }
1010 /* subx $dr,$sr */
1012 { 0, 0, 0, 0 },
1013 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1014 & ifmt_add, { 0x10 }
1016 /* trap $uimm4 */
1018 { 0, 0, 0, 0 },
1019 { { MNEM, ' ', OP (UIMM4), 0 } },
1020 & ifmt_trap, { 0x10f0 }
1022 /* unlock $src1,@$src2 */
1024 { 0, 0, 0, 0 },
1025 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
1026 & ifmt_cmp, { 0x2050 }
1028 /* satb $dr,$sr */
1030 { 0, 0, 0, 0 },
1031 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1032 & ifmt_satb, { 0x80600300 }
1034 /* sath $dr,$sr */
1036 { 0, 0, 0, 0 },
1037 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1038 & ifmt_satb, { 0x80600200 }
1040 /* sat $dr,$sr */
1042 { 0, 0, 0, 0 },
1043 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1044 & ifmt_satb, { 0x80600000 }
1046 /* pcmpbz $src2 */
1048 { 0, 0, 0, 0 },
1049 { { MNEM, ' ', OP (SRC2), 0 } },
1050 & ifmt_cmpz, { 0x370 }
1052 /* sadd */
1054 { 0, 0, 0, 0 },
1055 { { MNEM, 0 } },
1056 & ifmt_nop, { 0x50e4 }
1058 /* macwu1 $src1,$src2 */
1060 { 0, 0, 0, 0 },
1061 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1062 & ifmt_cmp, { 0x50b0 }
1064 /* msblo $src1,$src2 */
1066 { 0, 0, 0, 0 },
1067 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1068 & ifmt_cmp, { 0x50d0 }
1070 /* mulwu1 $src1,$src2 */
1072 { 0, 0, 0, 0 },
1073 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1074 & ifmt_cmp, { 0x50a0 }
1076 /* maclh1 $src1,$src2 */
1078 { 0, 0, 0, 0 },
1079 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1080 & ifmt_cmp, { 0x50c0 }
1082 /* sc */
1084 { 0, 0, 0, 0 },
1085 { { MNEM, 0 } },
1086 & ifmt_nop, { 0x7401 }
1088 /* snc */
1090 { 0, 0, 0, 0 },
1091 { { MNEM, 0 } },
1092 & ifmt_nop, { 0x7501 }
1094 /* clrpsw $uimm8 */
1096 { 0, 0, 0, 0 },
1097 { { MNEM, ' ', OP (UIMM8), 0 } },
1098 & ifmt_clrpsw, { 0x7200 }
1100 /* setpsw $uimm8 */
1102 { 0, 0, 0, 0 },
1103 { { MNEM, ' ', OP (UIMM8), 0 } },
1104 & ifmt_clrpsw, { 0x7100 }
1106 /* bset $uimm3,@($slo16,$sr) */
1108 { 0, 0, 0, 0 },
1109 { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1110 & ifmt_bset, { 0xa0600000 }
1112 /* bclr $uimm3,@($slo16,$sr) */
1114 { 0, 0, 0, 0 },
1115 { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1116 & ifmt_bset, { 0xa0700000 }
1118 /* btst $uimm3,$sr */
1120 { 0, 0, 0, 0 },
1121 { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } },
1122 & ifmt_btst, { 0xf0 }
1126 #undef A
1127 #undef OPERAND
1128 #undef MNEM
1129 #undef OP
1131 /* Formats for ALIAS macro-insns. */
1133 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1134 #define F(f) & m32r_cgen_ifld_table[M32R_##f]
1135 #else
1136 #define F(f) & m32r_cgen_ifld_table[M32R_/**/f]
1137 #endif
1138 static const CGEN_IFMT ifmt_bc8r = {
1139 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1142 static const CGEN_IFMT ifmt_bc24r = {
1143 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1146 static const CGEN_IFMT ifmt_bl8r = {
1147 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1150 static const CGEN_IFMT ifmt_bl24r = {
1151 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1154 static const CGEN_IFMT ifmt_bcl8r = {
1155 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1158 static const CGEN_IFMT ifmt_bcl24r = {
1159 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1162 static const CGEN_IFMT ifmt_bnc8r = {
1163 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1166 static const CGEN_IFMT ifmt_bnc24r = {
1167 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1170 static const CGEN_IFMT ifmt_bra8r = {
1171 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1174 static const CGEN_IFMT ifmt_bra24r = {
1175 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1178 static const CGEN_IFMT ifmt_bncl8r = {
1179 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1182 static const CGEN_IFMT ifmt_bncl24r = {
1183 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1186 static const CGEN_IFMT ifmt_ld_2 = {
1187 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1190 static const CGEN_IFMT ifmt_ld_d2 = {
1191 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1194 static const CGEN_IFMT ifmt_ldb_2 = {
1195 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1198 static const CGEN_IFMT ifmt_ldb_d2 = {
1199 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1202 static const CGEN_IFMT ifmt_ldh_2 = {
1203 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1206 static const CGEN_IFMT ifmt_ldh_d2 = {
1207 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1210 static const CGEN_IFMT ifmt_ldub_2 = {
1211 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1214 static const CGEN_IFMT ifmt_ldub_d2 = {
1215 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1218 static const CGEN_IFMT ifmt_lduh_2 = {
1219 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1222 static const CGEN_IFMT ifmt_lduh_d2 = {
1223 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1226 static const CGEN_IFMT ifmt_pop = {
1227 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
1230 static const CGEN_IFMT ifmt_ldi8a = {
1231 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
1234 static const CGEN_IFMT ifmt_ldi16a = {
1235 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
1238 static const CGEN_IFMT ifmt_rac_d = {
1239 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1242 static const CGEN_IFMT ifmt_rac_ds = {
1243 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1246 static const CGEN_IFMT ifmt_rach_d = {
1247 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1250 static const CGEN_IFMT ifmt_rach_ds = {
1251 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1254 static const CGEN_IFMT ifmt_st_2 = {
1255 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1258 static const CGEN_IFMT ifmt_st_d2 = {
1259 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1262 static const CGEN_IFMT ifmt_stb_2 = {
1263 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1266 static const CGEN_IFMT ifmt_stb_d2 = {
1267 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1270 static const CGEN_IFMT ifmt_sth_2 = {
1271 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1274 static const CGEN_IFMT ifmt_sth_d2 = {
1275 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1278 static const CGEN_IFMT ifmt_push = {
1279 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1282 #undef F
1284 /* Each non-simple macro entry points to an array of expansion possibilities. */
1286 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1287 #define A(a) (1 << CGEN_INSN_##a)
1288 #else
1289 #define A(a) (1 << CGEN_INSN_/**/a)
1290 #endif
1291 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1292 #define OPERAND(op) M32R_OPERAND_##op
1293 #else
1294 #define OPERAND(op) M32R_OPERAND_/**/op
1295 #endif
1296 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1297 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1299 /* The macro instruction table. */
1301 static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
1303 /* bc $disp8 */
1305 -1, "bc8r", "bc", 16,
1306 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1308 /* bc $disp24 */
1310 -1, "bc24r", "bc", 32,
1311 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1313 /* bl $disp8 */
1315 -1, "bl8r", "bl", 16,
1316 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1318 /* bl $disp24 */
1320 -1, "bl24r", "bl", 32,
1321 { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1323 /* bcl $disp8 */
1325 -1, "bcl8r", "bcl", 16,
1326 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
1328 /* bcl $disp24 */
1330 -1, "bcl24r", "bcl", 32,
1331 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
1333 /* bnc $disp8 */
1335 -1, "bnc8r", "bnc", 16,
1336 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1338 /* bnc $disp24 */
1340 -1, "bnc24r", "bnc", 32,
1341 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1343 /* bra $disp8 */
1345 -1, "bra8r", "bra", 16,
1346 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1348 /* bra $disp24 */
1350 -1, "bra24r", "bra", 32,
1351 { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1353 /* bncl $disp8 */
1355 -1, "bncl8r", "bncl", 16,
1356 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
1358 /* bncl $disp24 */
1360 -1, "bncl24r", "bncl", 32,
1361 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
1363 /* ld $dr,@($sr) */
1365 -1, "ld-2", "ld", 16,
1366 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1368 /* ld $dr,@($sr,$slo16) */
1370 -1, "ld-d2", "ld", 32,
1371 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1373 /* ldb $dr,@($sr) */
1375 -1, "ldb-2", "ldb", 16,
1376 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1378 /* ldb $dr,@($sr,$slo16) */
1380 -1, "ldb-d2", "ldb", 32,
1381 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1383 /* ldh $dr,@($sr) */
1385 -1, "ldh-2", "ldh", 16,
1386 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1388 /* ldh $dr,@($sr,$slo16) */
1390 -1, "ldh-d2", "ldh", 32,
1391 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1393 /* ldub $dr,@($sr) */
1395 -1, "ldub-2", "ldub", 16,
1396 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1398 /* ldub $dr,@($sr,$slo16) */
1400 -1, "ldub-d2", "ldub", 32,
1401 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1403 /* lduh $dr,@($sr) */
1405 -1, "lduh-2", "lduh", 16,
1406 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1408 /* lduh $dr,@($sr,$slo16) */
1410 -1, "lduh-d2", "lduh", 32,
1411 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1413 /* pop $dr */
1415 -1, "pop", "pop", 16,
1416 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1418 /* ldi $dr,$simm8 */
1420 -1, "ldi8a", "ldi", 16,
1421 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
1423 /* ldi $dr,$hash$slo16 */
1425 -1, "ldi16a", "ldi", 32,
1426 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1428 /* rac $accd */
1430 -1, "rac-d", "rac", 16,
1431 { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
1433 /* rac $accd,$accs */
1435 -1, "rac-ds", "rac", 16,
1436 { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
1438 /* rach $accd */
1440 -1, "rach-d", "rach", 16,
1441 { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
1443 /* rach $accd,$accs */
1445 -1, "rach-ds", "rach", 16,
1446 { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
1448 /* st $src1,@($src2) */
1450 -1, "st-2", "st", 16,
1451 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1453 /* st $src1,@($src2,$slo16) */
1455 -1, "st-d2", "st", 32,
1456 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1458 /* stb $src1,@($src2) */
1460 -1, "stb-2", "stb", 16,
1461 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1463 /* stb $src1,@($src2,$slo16) */
1465 -1, "stb-d2", "stb", 32,
1466 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1468 /* sth $src1,@($src2) */
1470 -1, "sth-2", "sth", 16,
1471 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1473 /* sth $src1,@($src2,$slo16) */
1475 -1, "sth-d2", "sth", 32,
1476 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1478 /* push $src1 */
1480 -1, "push", "push", 16,
1481 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1485 /* The macro instruction opcode table. */
1487 static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
1489 /* bc $disp8 */
1491 { 0, 0, 0, 0 },
1492 { { MNEM, ' ', OP (DISP8), 0 } },
1493 & ifmt_bc8r, { 0x7c00 }
1495 /* bc $disp24 */
1497 { 0, 0, 0, 0 },
1498 { { MNEM, ' ', OP (DISP24), 0 } },
1499 & ifmt_bc24r, { 0xfc000000 }
1501 /* bl $disp8 */
1503 { 0, 0, 0, 0 },
1504 { { MNEM, ' ', OP (DISP8), 0 } },
1505 & ifmt_bl8r, { 0x7e00 }
1507 /* bl $disp24 */
1509 { 0, 0, 0, 0 },
1510 { { MNEM, ' ', OP (DISP24), 0 } },
1511 & ifmt_bl24r, { 0xfe000000 }
1513 /* bcl $disp8 */
1515 { 0, 0, 0, 0 },
1516 { { MNEM, ' ', OP (DISP8), 0 } },
1517 & ifmt_bcl8r, { 0x7800 }
1519 /* bcl $disp24 */
1521 { 0, 0, 0, 0 },
1522 { { MNEM, ' ', OP (DISP24), 0 } },
1523 & ifmt_bcl24r, { 0xf8000000 }
1525 /* bnc $disp8 */
1527 { 0, 0, 0, 0 },
1528 { { MNEM, ' ', OP (DISP8), 0 } },
1529 & ifmt_bnc8r, { 0x7d00 }
1531 /* bnc $disp24 */
1533 { 0, 0, 0, 0 },
1534 { { MNEM, ' ', OP (DISP24), 0 } },
1535 & ifmt_bnc24r, { 0xfd000000 }
1537 /* bra $disp8 */
1539 { 0, 0, 0, 0 },
1540 { { MNEM, ' ', OP (DISP8), 0 } },
1541 & ifmt_bra8r, { 0x7f00 }
1543 /* bra $disp24 */
1545 { 0, 0, 0, 0 },
1546 { { MNEM, ' ', OP (DISP24), 0 } },
1547 & ifmt_bra24r, { 0xff000000 }
1549 /* bncl $disp8 */
1551 { 0, 0, 0, 0 },
1552 { { MNEM, ' ', OP (DISP8), 0 } },
1553 & ifmt_bncl8r, { 0x7900 }
1555 /* bncl $disp24 */
1557 { 0, 0, 0, 0 },
1558 { { MNEM, ' ', OP (DISP24), 0 } },
1559 & ifmt_bncl24r, { 0xf9000000 }
1561 /* ld $dr,@($sr) */
1563 { 0, 0, 0, 0 },
1564 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1565 & ifmt_ld_2, { 0x20c0 }
1567 /* ld $dr,@($sr,$slo16) */
1569 { 0, 0, 0, 0 },
1570 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1571 & ifmt_ld_d2, { 0xa0c00000 }
1573 /* ldb $dr,@($sr) */
1575 { 0, 0, 0, 0 },
1576 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1577 & ifmt_ldb_2, { 0x2080 }
1579 /* ldb $dr,@($sr,$slo16) */
1581 { 0, 0, 0, 0 },
1582 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1583 & ifmt_ldb_d2, { 0xa0800000 }
1585 /* ldh $dr,@($sr) */
1587 { 0, 0, 0, 0 },
1588 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1589 & ifmt_ldh_2, { 0x20a0 }
1591 /* ldh $dr,@($sr,$slo16) */
1593 { 0, 0, 0, 0 },
1594 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1595 & ifmt_ldh_d2, { 0xa0a00000 }
1597 /* ldub $dr,@($sr) */
1599 { 0, 0, 0, 0 },
1600 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1601 & ifmt_ldub_2, { 0x2090 }
1603 /* ldub $dr,@($sr,$slo16) */
1605 { 0, 0, 0, 0 },
1606 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1607 & ifmt_ldub_d2, { 0xa0900000 }
1609 /* lduh $dr,@($sr) */
1611 { 0, 0, 0, 0 },
1612 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1613 & ifmt_lduh_2, { 0x20b0 }
1615 /* lduh $dr,@($sr,$slo16) */
1617 { 0, 0, 0, 0 },
1618 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1619 & ifmt_lduh_d2, { 0xa0b00000 }
1621 /* pop $dr */
1623 { 0, 0, 0, 0 },
1624 { { MNEM, ' ', OP (DR), 0 } },
1625 & ifmt_pop, { 0x20ef }
1627 /* ldi $dr,$simm8 */
1629 { 0, 0, 0, 0 },
1630 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1631 & ifmt_ldi8a, { 0x6000 }
1633 /* ldi $dr,$hash$slo16 */
1635 { 0, 0, 0, 0 },
1636 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1637 & ifmt_ldi16a, { 0x90f00000 }
1639 /* rac $accd */
1641 { 0, 0, 0, 0 },
1642 { { MNEM, ' ', OP (ACCD), 0 } },
1643 & ifmt_rac_d, { 0x5090 }
1645 /* rac $accd,$accs */
1647 { 0, 0, 0, 0 },
1648 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1649 & ifmt_rac_ds, { 0x5090 }
1651 /* rach $accd */
1653 { 0, 0, 0, 0 },
1654 { { MNEM, ' ', OP (ACCD), 0 } },
1655 & ifmt_rach_d, { 0x5080 }
1657 /* rach $accd,$accs */
1659 { 0, 0, 0, 0 },
1660 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1661 & ifmt_rach_ds, { 0x5080 }
1663 /* st $src1,@($src2) */
1665 { 0, 0, 0, 0 },
1666 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1667 & ifmt_st_2, { 0x2040 }
1669 /* st $src1,@($src2,$slo16) */
1671 { 0, 0, 0, 0 },
1672 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1673 & ifmt_st_d2, { 0xa0400000 }
1675 /* stb $src1,@($src2) */
1677 { 0, 0, 0, 0 },
1678 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1679 & ifmt_stb_2, { 0x2000 }
1681 /* stb $src1,@($src2,$slo16) */
1683 { 0, 0, 0, 0 },
1684 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1685 & ifmt_stb_d2, { 0xa0000000 }
1687 /* sth $src1,@($src2) */
1689 { 0, 0, 0, 0 },
1690 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1691 & ifmt_sth_2, { 0x2020 }
1693 /* sth $src1,@($src2,$slo16) */
1695 { 0, 0, 0, 0 },
1696 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1697 & ifmt_sth_d2, { 0xa0200000 }
1699 /* push $src1 */
1701 { 0, 0, 0, 0 },
1702 { { MNEM, ' ', OP (SRC1), 0 } },
1703 & ifmt_push, { 0x207f }
1707 #undef A
1708 #undef OPERAND
1709 #undef MNEM
1710 #undef OP
1712 #ifndef CGEN_ASM_HASH_P
1713 #define CGEN_ASM_HASH_P(insn) 1
1714 #endif
1716 #ifndef CGEN_DIS_HASH_P
1717 #define CGEN_DIS_HASH_P(insn) 1
1718 #endif
1720 /* Return non-zero if INSN is to be added to the hash table.
1721 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1723 static int
1724 asm_hash_insn_p (insn)
1725 const CGEN_INSN *insn ATTRIBUTE_UNUSED;
1727 return CGEN_ASM_HASH_P (insn);
1730 static int
1731 dis_hash_insn_p (insn)
1732 const CGEN_INSN *insn;
1734 /* If building the hash table and the NO-DIS attribute is present,
1735 ignore. */
1736 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
1737 return 0;
1738 return CGEN_DIS_HASH_P (insn);
1741 #ifndef CGEN_ASM_HASH
1742 #define CGEN_ASM_HASH_SIZE 127
1743 #ifdef CGEN_MNEMONIC_OPERANDS
1744 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1745 #else
1746 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1747 #endif
1748 #endif
1750 /* It doesn't make much sense to provide a default here,
1751 but while this is under development we do.
1752 BUFFER is a pointer to the bytes of the insn, target order.
1753 VALUE is the first base_insn_bitsize bits as an int in host order. */
1755 #ifndef CGEN_DIS_HASH
1756 #define CGEN_DIS_HASH_SIZE 256
1757 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1758 #endif
1760 /* The result is the hash value of the insn.
1761 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1763 static unsigned int
1764 asm_hash_insn (mnem)
1765 const char * mnem;
1767 return CGEN_ASM_HASH (mnem);
1770 /* BUF is a pointer to the bytes of the insn, target order.
1771 VALUE is the first base_insn_bitsize bits as an int in host order. */
1773 static unsigned int
1774 dis_hash_insn (buf, value)
1775 const char * buf ATTRIBUTE_UNUSED;
1776 CGEN_INSN_INT value ATTRIBUTE_UNUSED;
1778 return CGEN_DIS_HASH (buf, value);
1781 static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
1783 /* Set the recorded length of the insn in the CGEN_FIELDS struct. */
1785 static void
1786 set_fields_bitsize (fields, size)
1787 CGEN_FIELDS *fields;
1788 int size;
1790 CGEN_FIELDS_BITSIZE (fields) = size;
1793 /* Function to call before using the operand instance table.
1794 This plugs the opcode entries and macro instructions into the cpu table. */
1796 void
1797 m32r_cgen_init_opcode_table (cd)
1798 CGEN_CPU_DESC cd;
1800 int i;
1801 int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
1802 sizeof (m32r_cgen_macro_insn_table[0]));
1803 const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
1804 const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
1805 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
1806 memset (insns, 0, num_macros * sizeof (CGEN_INSN));
1807 for (i = 0; i < num_macros; ++i)
1809 insns[i].base = &ib[i];
1810 insns[i].opcode = &oc[i];
1811 m32r_cgen_build_insn_regex (& insns[i]);
1813 cd->macro_insn_table.init_entries = insns;
1814 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
1815 cd->macro_insn_table.num_init_entries = num_macros;
1817 oc = & m32r_cgen_insn_opcode_table[0];
1818 insns = (CGEN_INSN *) cd->insn_table.init_entries;
1819 for (i = 0; i < MAX_INSNS; ++i)
1821 insns[i].opcode = &oc[i];
1822 m32r_cgen_build_insn_regex (& insns[i]);
1825 cd->sizeof_fields = sizeof (CGEN_FIELDS);
1826 cd->set_fields_bitsize = set_fields_bitsize;
1828 cd->asm_hash_p = asm_hash_insn_p;
1829 cd->asm_hash = asm_hash_insn;
1830 cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
1832 cd->dis_hash_p = dis_hash_insn_p;
1833 cd->dis_hash = dis_hash_insn;
1834 cd->dis_hash_size = CGEN_DIS_HASH_SIZE;