include/opcode/m68k.h

   1 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
   3    2003, 2004, 2006 Free Software Foundation, Inc.
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    1, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 /* These are used as bit flags for the arch field in the m68k_opcode
  23    structure.  */
  24 #define _m68k_undef  0
  25 #define m68000   0x001
  26 #define m68010   0x002
  27 #define m68020   0x004
  28 #define m68030   0x008
  29 #define m68040   0x010
  30 #define m68060   0x020
  31 #define m68881   0x040
  32 #define m68851   0x080
  33 #define cpu32    0x100          /* e.g., 68332 */
  34 #define m68k_mask  0x1ff
  35
  36 #define mcfmac   0x200          /* ColdFire MAC. */
  37 #define mcfemac  0x400          /* ColdFire EMAC. */
  38 #define cfloat   0x800          /* ColdFire FPU.  */
  39 #define mcfhwdiv 0x1000         /* ColdFire hardware divide.  */
  40
  41 #define mcfisa_a 0x2000         /* ColdFire ISA_A.  */
  42 #define mcfisa_aa 0x4000        /* ColdFire ISA_A+.  */
  43 #define mcfisa_b 0x8000         /* ColdFire ISA_B.  */
  44 #define mcfusp   0x10000        /* ColdFire USP instructions.  */
  45 #define mcf_mask 0x1f200
  46
  47 /* Handy aliases.  */
  48 #define m68040up   (m68040 | m68060)
  49 #define m68030up   (m68030 | m68040up)
  50 #define m68020up   (m68020 | m68030up)
  51 #define m68010up   (m68010 | cpu32 | m68020up)
  52 #define m68000up   (m68000 | m68010up)
  53
  54 #define mfloat  (m68881 | m68040 | m68060)
  55 #define mmmu    (m68851 | m68030 | m68040 | m68060)
  56
  57 /* The structure used to hold information for an opcode.  */
  58
  59 struct m68k_opcode
  60 {
  61   /* The opcode name.  */
  62   const char *name;
  63   /* The pseudo-size of the instruction(in bytes).  Used to determine
  64      number of bytes necessary to disassemble the instruction.  */
  65   unsigned int size;
  66   /* The opcode itself.  */
  67   unsigned long opcode;
  68   /* The mask used by the disassembler.  */
  69   unsigned long match;
  70   /* The arguments.  */
  71   const char *args;
  72   /* The architectures which support this opcode.  */
  73   unsigned int arch;
  74 };
  75
  76 /* The structure used to hold information for an opcode alias.  */
  77
  78 struct m68k_opcode_alias
  79 {
  80   /* The alias name.  */
  81   const char *alias;
  82   /* The instruction for which this is an alias.  */
  83   const char *primary;
  84 };
  85
  86 /* We store four bytes of opcode for all opcodes because that is the
  87    most any of them need.  The actual length of an instruction is
  88    always at least 2 bytes, and is as much longer as necessary to hold
  89    the operands it has.
  90
  91    The match field is a mask saying which bits must match particular
  92    opcode in order for an instruction to be an instance of that
  93    opcode.
  94
  95    The args field is a string containing two characters for each
  96    operand of the instruction.  The first specifies the kind of
  97    operand; the second, the place it is stored.  */
  98
  99 /* Kinds of operands:
 100    Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
 101
 102    D  data register only.  Stored as 3 bits.
 103    A  address register only.  Stored as 3 bits.
 104    a  address register indirect only.  Stored as 3 bits.
 105    R  either kind of register.  Stored as 4 bits.
 106    r  either kind of register indirect only.  Stored as 4 bits.
 107       At the moment, used only for cas2 instruction.
 108    F  floating point coprocessor register only.   Stored as 3 bits.
 109    O  an offset (or width): immediate data 0-31 or data register.
 110       Stored as 6 bits in special format for BF... insns.
 111    +  autoincrement only.  Stored as 3 bits (number of the address register).
 112    -  autodecrement only.  Stored as 3 bits (number of the address register).
 113    Q  quick immediate data.  Stored as 3 bits.
 114       This matches an immediate operand only when value is in range 1 .. 8.
 115    M  moveq immediate data.  Stored as 8 bits.
 116       This matches an immediate operand only when value is in range -128..127
 117    T  trap vector immediate data.  Stored as 4 bits.
 118
 119    k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
 120       a three bit register offset, depending on the field type.
 121
 122    #  immediate data.  Stored in special places (b, w or l)
 123       which say how many bits to store.
 124    ^  immediate data for floating point instructions.   Special places
 125       are offset by 2 bytes from '#'...
 126    B  pc-relative address, converted to an offset
 127       that is treated as immediate data.
 128    d  displacement and register.  Stores the register as 3 bits
 129       and stores the displacement in the entire second word.
 130
 131    C  the CCR.  No need to store it; this is just for filtering validity.
 132    S  the SR.  No need to store, just as with CCR.
 133    U  the USP.  No need to store, just as with CCR.
 134    E  the MAC ACC.  No need to store, just as with CCR.
 135    e  the EMAC ACC[0123].
 136    G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
 137    g  the EMAC ACCEXT{01,23}.
 138    H  the MASK.  No need to store, just as with CCR.
 139    i  the MAC/EMAC scale factor.
 140
 141    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
 142       extracted from the 'd' field of word one, which means that an extended
 143       coprocessor opcode can be skipped using the 'i' place, if needed.
 144
 145    s  System Control register for the floating point coprocessor.
 146
 147    J  Misc register for movec instruction, stored in 'j' format.
 148         Possible values:
 149         0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
 150         0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
 151         0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
 152         0x003   TC      MMU Translation Control         [60, 40]
 153         0x004   ITT0    Instruction Transparent
 154                                 Translation reg 0       [60, 40]
 155         0x005   ITT1    Instruction Transparent
 156                                 Translation reg 1       [60, 40]
 157         0x006   DTT0    Data Transparent
 158                                 Translation reg 0       [60, 40]
 159         0x007   DTT1    Data Transparent
 160                                 Translation reg 1       [60, 40]
 161         0x008   BUSCR   Bus Control Register            [60]
 162         0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
 163         0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
 164         0x802   CAAR    Cache Address Register          [        30, 20]
 165         0x803   MSP     Master Stack Pointer            [    40, 30, 20]
 166         0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
 167         0x805   MMUSR   MMU Status reg                  [    40]
 168         0x806   URP     User Root Pointer               [60, 40]
 169         0x807   SRP     Supervisor Root Pointer         [60, 40]
 170         0x808   PCR     Processor Configuration reg     [60]
 171         0xC00   ROMBAR  ROM Base Address Register       [520X]
 172         0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
 173         0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
 174         0xC0F   MBAR0   RAM Base Address Register 0     [520X]
 175         0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
 176         0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
 177
 178     L  Register list of the type d0-d7/a0-a7 etc.
 179        (New!  Improved!  Can also hold fp0-fp7, as well!)
 180        The assembler tries to see if the registers match the insn by
 181        looking at where the insn wants them stored.
 182
 183     l  Register list like L, but with all the bits reversed.
 184        Used for going the other way. . .
 185
 186     c  cache identifier which may be "nc" for no cache, "ic"
 187        for instruction cache, "dc" for data cache, or "bc"
 188        for both caches.  Used in cinv and cpush.  Always
 189        stored in position "d".
 190
 191     u  Any register, with ``upper'' or ``lower'' specification.  Used
 192        in the mac instructions with size word.
 193
 194  The remainder are all stored as 6 bits using an address mode and a
 195  register number; they differ in which addressing modes they match.
 196
 197    *  all                                       (modes 0-6,7.0-4)
 198    ~  alterable memory                          (modes 2-6,7.0,7.1)
 199                                                 (not 0,1,7.2-4)
 200    %  alterable                                 (modes 0-6,7.0,7.1)
 201                                                 (not 7.2-4)
 202    ;  data                                      (modes 0,2-6,7.0-4)
 203                                                 (not 1)
 204    @  data, but not immediate                   (modes 0,2-6,7.0-3)
 205                                                 (not 1,7.4)
 206    !  control                                   (modes 2,5,6,7.0-3)
 207                                                 (not 0,1,3,4,7.4)
 208    &  alterable control                         (modes 2,5,6,7.0,7.1)
 209                                                 (not 0,1,3,4,7.2-4)
 210    $  alterable data                            (modes 0,2-6,7.0,7.1)
 211                                                 (not 1,7.2-4)
 212    ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
 213                                                 (not 1,3,4,7.2-4)
 214    /  control, or data register                 (modes 0,2,5,6,7.0-3)
 215                                                 (not 1,3,4,7.4)
 216    >  *save operands                            (modes 2,4,5,6,7.0,7.1)
 217                                                 (not 0,1,3,7.2-4)
 218    <  *restore operands                         (modes 2,3,5,6,7.0-3)
 219                                                 (not 0,1,4,7.4)
 220
 221    coldfire move operands:
 222    m                                            (modes 0-4)
 223    n                                            (modes 5,7.2)
 224    o                                            (modes 6,7.0,7.1,7.3,7.4)
 225    p                                            (modes 0-5)
 226
 227    coldfire bset/bclr/btst/mulsl/mulul operands:
 228    q                                            (modes 0,2-5)
 229    v                                            (modes 0,2-5,7.0,7.1)
 230    b                                            (modes 0,2-5,7.2)
 231    w                                            (modes 2-5,7.2)
 232    y                                            (modes 2,5)
 233    z                                            (modes 2,5,7.2)
 234    x  mov3q immediate operand.
 235    4                                            (modes 2,3,4,5)
 236   */
 237
 238 /* For the 68851:  */
 239 /* I didn't use much imagination in choosing the
 240    following codes, so many of them aren't very
 241    mnemonic. -rab
 242
 243    0  32 bit pmmu register
 244         Possible values:
 245         000     TC      Translation Control Register (68030, 68851)
 246
 247    1  16 bit pmmu register
 248         111     AC      Access Control (68851)
 249
 250    2  8 bit pmmu register
 251         100     CAL     Current Access Level (68851)
 252         101     VAL     Validate Access Level (68851)
 253         110     SCC     Stack Change Control (68851)
 254
 255    3  68030-only pmmu registers (32 bit)
 256         010     TT0     Transparent Translation reg 0
 257                         (aka Access Control reg 0 -- AC0 -- on 68ec030)
 258         011     TT1     Transparent Translation reg 1
 259                         (aka Access Control reg 1 -- AC1 -- on 68ec030)
 260
 261    W  wide pmmu registers
 262         Possible values:
 263         001     DRP     Dma Root Pointer (68851)
 264         010     SRP     Supervisor Root Pointer (68030, 68851)
 265         011     CRP     Cpu Root Pointer (68030, 68851)
 266
 267    f    function code register (68030, 68851)
 268         0       SFC
 269         1       DFC
 270
 271    V    VAL register only (68851)
 272
 273    X    BADx, BACx (16 bit)
 274         100     BAD     Breakpoint Acknowledge Data (68851)
 275         101     BAC     Breakpoint Acknowledge Control (68851)
 276
 277    Y    PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
 278    Z    PCSR (68851)
 279
 280    |    memory          (modes 2-6, 7.*)
 281
 282    t  address test level (68030 only)
 283       Stored as 3 bits, range 0-7.
 284       Also used for breakpoint instruction now.
 285
 286 */
 287
 288 /* Places to put an operand, for non-general operands:
 289    Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
 290
 291    s  source, low bits of first word.
 292    d  dest, shifted 9 in first word
 293    1  second word, shifted 12
 294    2  second word, shifted 6
 295    3  second word, shifted 0
 296    4  third word, shifted 12
 297    5  third word, shifted 6
 298    6  third word, shifted 0
 299    7  second word, shifted 7
 300    8  second word, shifted 10
 301    9  second word, shifted 5
 302    D  store in both place 1 and place 3; for divul and divsl.
 303    B  first word, low byte, for branch displacements
 304    W  second word (entire), for branch displacements
 305    L  second and third words (entire), for branch displacements
 306       (also overloaded for move16)
 307    b  second word, low byte
 308    w  second word (entire) [variable word/long branch offset for dbra]
 309    W  second word (entire) (must be signed 16 bit value)
 310    l  second and third word (entire)
 311    g  variable branch offset for bra and similar instructions.
 312       The place to store depends on the magnitude of offset.
 313    t  store in both place 7 and place 8; for floating point operations
 314    c  branch offset for cpBcc operations.
 315       The place to store is word two if bit six of word one is zero,
 316       and words two and three if bit six of word one is one.
 317    i  Increment by two, to skip over coprocessor extended operands.   Only
 318       works with the 'I' format.
 319    k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
 320       Also used for dynamic fmovem instruction.
 321    C  floating point coprocessor constant - 7 bits.  Also used for static
 322       K-factors...
 323    j  Movec register #, stored in 12 low bits of second word.
 324    m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
 325       and remaining 3 bits of register shifted 9 bits in first word.
 326       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 327       Use with `R' or `u' format.
 328    n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
 329       with MSB shifted 6 bits in first word and remaining 3 bits of
 330       register shifted 9 bits in first word.  No upper/lower
 331       indication is done.)  Use with `R' or `u' format.
 332    o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
 333       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 334       Use with `R' or `u' format.
 335    M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
 336       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 337       `R' or `u' format.
 338    N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
 339       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 340       `R' or `u' format.
 341    h  shift indicator (scale factor), 1 bit shifted 10 in second word
 342
 343  Places to put operand, for general operands:
 344    d  destination, shifted 6 bits in first word
 345    b  source, at low bit of first word, and immediate uses one byte
 346    w  source, at low bit of first word, and immediate uses two bytes
 347    l  source, at low bit of first word, and immediate uses four bytes
 348    s  source, at low bit of first word.
 349       Used sometimes in contexts where immediate is not allowed anyway.
 350    f  single precision float, low bit of 1st word, immediate uses 4 bytes
 351    F  double precision float, low bit of 1st word, immediate uses 8 bytes
 352    x  extended precision float, low bit of 1st word, immediate uses 12 bytes
 353    p  packed float, low bit of 1st word, immediate uses 12 bytes
 354    G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
 355    H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
 356    F  EMAC ACCx
 357    f  EMAC ACCy
 358    I  MAC/EMAC scale factor
 359    /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
 360    ]  first word, bit 10
 361 */
 362
 363 extern const struct m68k_opcode m68k_opcodes[];
 364 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
 365
 366 extern const int m68k_numopcodes, m68k_numaliases;
 367
 368 /* end of m68k-opcode.h */