gas/testsuite/gas/mips/vr4130.s

   1         .macro  check2 insn
   2         mflo    $2
   3         \insn   $3,$3
   4         .endm
   5
   6         .macro  check3 insn
   7         mfhi    $2
   8         \insn   $0,$3,$3
   9         .endm
  10
  11         .macro  main func
  12
  13         .ent    \func
  14         .type   \func,@function
  15 \func:
  16
  17         # PART A
  18         #
  19         # Check that mfhis and mflos in .set noreorder blocks are considered.
  20
  21         .set    noreorder
  22         mfhi    $2
  23         .set    reorder
  24         mult    $3,$3
  25
  26         .set    noreorder
  27         mflo    $2
  28         .set    reorder
  29         mult    $3,$3
  30
  31         # PART B
  32         #
  33         # Check for simple instances.
  34
  35         mfhi    $2
  36         mult    $3,$3   # 4 nops
  37
  38         mfhi    $2
  39         addiu   $3,1
  40         mult    $4,$4   # 3 nops
  41
  42         mfhi    $2
  43         addiu   $3,1
  44         addiu   $4,1
  45         mult    $5,$5   # 2 nops
  46
  47         mfhi    $2
  48         addiu   $3,1
  49         addiu   $4,1
  50         addiu   $5,1
  51         mult    $6,$6   # 1 nop
  52
  53         mfhi    $2
  54         addiu   $3,1
  55         addiu   $4,1
  56         addiu   $5,1
  57         addiu   $6,1
  58         mult    $7,$7   # 0 nops
  59
  60         # PART C
  61         #
  62         # Check that no nops are inserted after the result has been read.
  63
  64         mfhi    $2
  65         addiu   $2,1
  66         addiu   $3,1
  67         addiu   $4,1
  68         mult    $5,$5
  69
  70         mfhi    $2
  71         addiu   $3,1
  72         addiu   $2,1
  73         addiu   $4,1
  74         mult    $5,$5
  75
  76         mfhi    $2
  77         addiu   $3,1
  78         addiu   $4,1
  79         addiu   $2,1
  80         mult    $5,$5
  81
  82         mfhi    $2
  83         addiu   $3,1
  84         addiu   $4,1
  85         addiu   $5,1
  86         mult    $2,$2
  87
  88         # PART D
  89         #
  90         # Check that we still insert the usual interlocking nops in cases
  91         # where the VR4130 errata doesn't apply.
  92
  93         mfhi    $2
  94         mult    $2,$2   # 2 nops
  95
  96         mfhi    $2
  97         addiu   $2,1
  98         mult    $3,$3   # 1 nop
  99
 100         mfhi    $2
 101         addiu   $3,1
 102         mult    $2,$2   # 1 nop
 103
 104         # PART E
 105         #
 106         # Check for branches whose targets might be affected.
 107
 108         mfhi    $2
 109         bnez    $3,1f   # 2 nops for normal mode, 3 for mips16
 110
 111         mfhi    $2
 112         addiu   $3,1
 113         bnez    $3,1f   # 1 nop for normal mode, 2 for mips16
 114
 115         mfhi    $2
 116         addiu   $3,1
 117         addiu   $3,1
 118         bnez    $3,1f   # 0 nops for normal mode, 1 for mips16
 119
 120         mfhi    $2
 121         addiu   $3,1
 122         addiu   $3,1
 123         addiu   $3,1
 124         bnez    $3,1f   # 0 nops
 125
 126         # PART F
 127         #
 128         # As above, but with no dependencies between the branch and
 129         # the previous instruction.  The final branch can use the
 130         # preceding addiu as its delay slot.
 131
 132         mfhi    $2
 133         addiu   $3,1
 134         bnez    $4,1f   # 1 nop for normal mode, 2 for mips16
 135
 136         mfhi    $2
 137         addiu   $3,1
 138         addiu   $4,1
 139         bnez    $5,1f   # 0 nops for normal mode, 1 for mips16
 140
 141         mfhi    $2
 142         addiu   $3,1
 143         addiu   $4,1
 144         addiu   $5,1
 145         bnez    $6,1f   # 0 nops, fill delay slot in normal mode
 146 1:
 147
 148         # PART G
 149         #
 150         # Like part B, but check that intervening .set noreorders don't
 151         # affect the number of nops.
 152
 153         mfhi    $2
 154         .set    noreorder
 155         addiu   $3,1
 156         .set    reorder
 157         mult    $4,$4   # 3 nops
 158
 159         mfhi    $2
 160         .set    noreorder
 161         addiu   $3,1
 162         .set    reorder
 163         addiu   $4,1
 164         mult    $5,$5   # 2 nops
 165
 166         mfhi    $2
 167         addiu   $3,1
 168         .set    noreorder
 169         addiu   $4,1
 170         .set    reorder
 171         mult    $5,$5   # 2 nops
 172
 173         mfhi    $2
 174         .set    noreorder
 175         addiu   $3,1
 176         addiu   $4,1
 177         .set    reorder
 178         mult    $5,$5   # 2 nops
 179
 180         mfhi    $2
 181         addiu   $3,1
 182         .set    noreorder
 183         addiu   $4,1
 184         .set    reorder
 185         addiu   $5,1
 186         mult    $6,$6   # 1 nop
 187
 188         mfhi    $2
 189         .set    noreorder
 190         addiu   $3,1
 191         addiu   $4,1
 192         addiu   $5,1
 193         .set    reorder
 194         mult    $6,$6   # 1 nop
 195
 196         mfhi    $2
 197         .set    noreorder
 198         addiu   $3,1
 199         addiu   $4,1
 200         addiu   $5,1
 201         addiu   $6,1
 202         .set    reorder
 203         mult    $7,$7   # 0 nops
 204
 205         # PART H
 206         #
 207         # Like part B, but the mult occurs in a .set noreorder block.
 208
 209         mfhi    $2
 210         .set    noreorder
 211         mult    $3,$3   # 4 nops
 212         .set    reorder
 213
 214         mfhi    $2
 215         .set    noreorder
 216         addiu   $3,1
 217         mult    $4,$4   # 3 nops
 218         .set    reorder
 219
 220         mfhi    $2
 221         addiu   $3,1
 222         .set    noreorder
 223         addiu   $4,1
 224         mult    $5,$5   # 2 nops
 225         .set    reorder
 226
 227         mfhi    $2
 228         .set    noreorder
 229         addiu   $3,1
 230         addiu   $4,1
 231         addiu   $5,1
 232         mult    $6,$6   # 1 nop
 233         .set    reorder
 234
 235         mfhi    $2
 236         .set    noreorder
 237         addiu   $3,1
 238         addiu   $4,1
 239         addiu   $5,1
 240         addiu   $6,1
 241         mult    $7,$7   # 0 nops
 242         .set    reorder
 243
 244         # PART I
 245         #
 246         # Check every affected multiplication and division instruction.
 247
 248         check2  mult
 249         check2  multu
 250         check2  dmult
 251         check2  dmultu
 252
 253         check3  div
 254         check3  divu
 255         check3  ddiv
 256         check3  ddivu
 257
 258         .end    \func
 259         .endm
 260
 261         .set    nomips16
 262         main    foo
 263
 264         # PART J
 265         #
 266         # Check every affected multiply-accumulate instruction.
 267
 268         check3  macc
 269         check3  macchi
 270         check3  macchis
 271         check3  macchiu
 272         check3  macchius
 273         check3  maccs
 274         check3  maccu
 275         check3  maccus
 276
 277         check3  dmacc
 278         check3  dmacchi
 279         check3  dmacchis
 280         check3  dmacchiu
 281         check3  dmacchius
 282         check3  dmaccs
 283         check3  dmaccu
 284         check3  dmaccus
 285
 286         # PART K
 287         #
 288         # Check that mtlo and mthi are exempt from the VR4130 errata,
 289         # although the usual interlocking delay applies.
 290
 291         mflo    $2
 292         mtlo    $3
 293
 294         mflo    $2
 295         mthi    $3
 296
 297         mfhi    $2
 298         mtlo    $3
 299
 300         mfhi    $2
 301         mthi    $3
 302
 303         .set    mips16
 304         main    bar