opcodes/mcore-opc.h

   1 /* Assembler instructions for Motorolla's Mcore processor
   2    Copyright (C) 1999 Free Software Foundation, Inc.
   3
   4
   5 This program is free software; you can redistribute it and/or modify
   6 it under the terms of the GNU General Public License as published by
   7 the Free Software Foundation; either version 2 of the License, or
   8 (at your option) any later version.
   9
  10 This program is distributed in the hope that it will be useful,
  11 but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 GNU General Public License for more details.
  14
  15 You should have received a copy of the GNU General Public License
  16 along with this program; if not, write to the Free Software
  17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  18
  19 #include "ansidecl.h"
  20
  21 typedef enum
  22 {
  23   O0,    OT,   O1,   OC,   O2,    X1,    OI,    OB,
  24   OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
  25   RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
  26   O1R1,  OMb,  OMc,  SIa,
  27   JC,    JU,   JL,   RSI,  DO21,  OB2
  28 }
  29 mcore_opclass;
  30
  31 typedef struct inst
  32 {
  33   char *         name;
  34   mcore_opclass  opclass;
  35   unsigned char  transfer;
  36   unsigned short inst;
  37 }
  38 mcore_opcode_info;
  39
  40 #ifdef DEFINE_TABLE
  41 mcore_opcode_info mcore_table[] =
  42 {
  43   { "bkpt",     O0,     0,      0x0000 },
  44   { "sync",     O0,     0,      0x0001 },
  45   { "rte",      O0,     1,      0x0002 },
  46   { "rfe",      O0,     1,      0x0002 },
  47   { "rfi",      O0,     1,      0x0003 },
  48   { "stop",     O0,     0,      0x0004 },
  49   { "wait",     O0,     0,      0x0005 },
  50   { "doze",     O0,     0,      0x0006 },
  51   { "trap",     OT,     0,      0x0008 },
  52 /* SPACE:                       0x000C - 0x000F */
  53 /* SPACE:                       0x0010 - 0x001F */
  54   { "mvc",      O1,     0,      0x0020 },
  55   { "mvcv",     O1,     0,      0x0030 },
  56   { "ldq",      RQ,     0,      0x0040 },
  57   { "stq",      RQ,     0,      0x0050 },
  58   { "ldm",      RM,     0,      0x0060 },
  59   { "stm",      RM,     0,      0x0070 },
  60   { "dect",     O1,     0,      0x0080 },
  61   { "decf",     O1,     0,      0x0090 },
  62   { "inct",     O1,     0,      0x00A0 },
  63   { "incf",     O1,     0,      0x00B0 },
  64   { "jmp",      JMP,    2,      0x00C0 },
  65 #define MCORE_INST_JMP  0x00C0
  66   { "jsr",      JSR,    0,      0x00D0 },
  67 #define MCORE_INST_JSR  0x00E0
  68   { "ff1",      O1,     0,      0x00E0 },
  69   { "brev",     O1,     0,      0x00F0 },
  70   { "xtrb3",    X1,     0,      0x0100 },
  71   { "xtrb2",    X1,     0,      0x0110 },
  72   { "xtrb1",    X1,     0,      0x0120 },
  73   { "xtrb0",    X1,     0,      0x0130 },
  74   { "zextb",    O1,     0,      0x0140 },
  75   { "sextb",    O1,     0,      0x0150 },
  76   { "zexth",    O1,     0,      0x0160 },
  77   { "sexth",    O1,     0,      0x0170 },
  78   { "declt",    O1,     0,      0x0180 },
  79   { "tstnbz",   O1,     0,      0x0190 },
  80   { "decgt",    O1,     0,      0x01A0 },
  81   { "decne",    O1,     0,      0x01B0 },
  82   { "clrt",     O1,     0,      0x01C0 },
  83   { "clrf",     O1,     0,      0x01D0 },
  84   { "abs",      O1,     0,      0x01E0 },
  85   { "not",      O1,     0,      0x01F0 },
  86   { "movt",     O2,     0,      0x0200 },
  87   { "mult",     O2,     0,      0x0300 },
  88   { "loopt",    BL,     0,      0x0400 },
  89   { "subu",     O2,     0,      0x0500 },
  90   { "sub",      O2,     0,      0x0500 }, /* Official alias.  */
  91   { "addc",     O2,     0,      0x0600 },
  92   { "subc",     O2,     0,      0x0700 },
  93 /* SPACE: 0x0800-0x08ff for a diadic operation */
  94 /* SPACE: 0x0900-0x09ff for a diadic operation */
  95   { "movf",     O2,     0,      0x0A00 },
  96   { "lsr",      O2,     0,      0x0B00 },
  97   { "cmphs",    O2,     0,      0x0C00 },
  98   { "cmplt",    O2,     0,      0x0D00 },
  99   { "tst",      O2,     0,      0x0E00 },
 100   { "cmpne",    O2,     0,      0x0F00 },
 101   { "mfcr",     OC,     0,      0x1000 },
 102   { "mov",      O2,     0,      0x1200 },
 103   { "bgenr",    O2,     0,      0x1300 },
 104   { "rsub",     O2,     0,      0x1400 },
 105   { "ixw",      O2,     0,      0x1500 },
 106   { "and",      O2,     0,      0x1600 },
 107   { "xor",      O2,     0,      0x1700 },
 108   { "mtcr",     OC,     0,      0x1800 },
 109   { "asr",      O2,     0,      0x1A00 },
 110   { "lsl",      O2,     0,      0x1B00 },
 111   { "addu",     O2,     0,      0x1C00 },
 112   { "ixh",      O2,     0,      0x1D00 },
 113   { "or",       O2,     0,      0x1E00 },
 114   { "andn",     O2,     0,      0x1F00 },
 115   { "addi",     OI,     0,      0x2000 },
 116 #define MCORE_INST_ADDI 0x2000
 117   { "cmplti",   OI,     0,      0x2200 },
 118   { "subi",     OI,     0,      0x2400 },
 119 /* SPACE: 0x2600-0x27ff open for a register+immediate  operation */
 120   { "rsubi",    OB,     0,      0x2800 },
 121   { "cmpnei",   OB,     0,      0x2A00 },
 122   { "bmaski",   OMa,    0,      0x2C00 },
 123   { "divu",     O1R1,   0,      0x2C10 },
 124 /* SPACE:                       0x2c20 - 0x2c7f */
 125   { "bmaski",   OMb,    0,      0x2C80 },
 126   { "bmaski",   OMc,    0,      0x2D00 },
 127   { "andi",     OB,     0,      0x2E00 },
 128   { "bclri",    OB,     0,      0x3000 },
 129 /* SPACE:                       0x3200 - 0x320f */
 130   { "divs",     O1R1,   0,      0x3210 },
 131 /* SPACE:                       0x3220 - 0x326f */
 132   { "bgeni",    OBRa,   0,      0x3270 },
 133   { "bgeni",    OBRb,   0,      0x3280 },
 134   { "bgeni",    OBRc,   0,      0x3300 },
 135   { "bseti",    OB,     0,      0x3400 },
 136   { "btsti",    OB,     0,      0x3600 },
 137   { "xsr",      O1,     0,      0x3800 },
 138   { "rotli",    SIa,    0,      0x3800 },
 139   { "asrc",     O1,     0,      0x3A00 },
 140   { "asri",     SIa,    0,      0x3A00 },
 141   { "lslc",     O1,     0,      0x3C00 },
 142   { "lsli",     SIa,    0,      0x3C00 },
 143   { "lsrc",     O1,     0,      0x3E00 },
 144   { "lsri",     SIa,    0,      0x3E00 },
 145 /* SPACE:                       0x4000 - 0x5fff */
 146   { "movi",     I7,     0,      0x6000 },
 147 #define MCORE_INST_BMASKI_ALT   0x6000
 148 #define MCORE_INST_BGENI_ALT    0x6000
 149 /* SPACE:                       0x6900 - 0x6FFF */
 150   { "jmpi",     LJ,     1,      0x7000 },
 151   { "jsri",     LJ,     0,      0x7F00 },
 152 #define MCORE_INST_JMPI 0x7000
 153   { "lrw",      LR,     0,      0x7000 },
 154 #define MCORE_INST_JSRI 0x7F00
 155   { "ld",       LS,     0,      0x8000 },
 156   { "ldw",      LS,     0,      0x8000 },
 157   { "ld.w",     LS,     0,      0x8000 },
 158   { "st",       LS,     0,      0x9000 },
 159   { "stw",      LS,     0,      0x9000 },
 160   { "st.w",     LS,     0,      0x9000 },
 161   { "ldb",      LS,     0,      0xA000 },
 162   { "ld.b",     LS,     0,      0xA000 },
 163   { "stb",      LS,     0,      0xB000 },
 164   { "st.b",     LS,     0,      0xB000 },
 165   { "ldh",      LS,     0,      0xC000 },
 166   { "ld.h",     LS,     0,      0xC000 },
 167   { "sth",      LS,     0,      0xD000 },
 168   { "st.h",     LS,     0,      0xD000 },
 169   { "bt",       BR,     0,      0xE000 },
 170   { "bf",       BR,     0,      0xE800 },
 171   { "br",       BR,     1,      0xF000 },
 172 #define MCORE_INST_BR   0xF000
 173   { "bsr",      BR,     0,      0xF800 },
 174 #define MCORE_INST_BSR  0xF800
 175
 176 /* The following are relaxable branches */
 177   { "jbt",      JC,     0,      0xE000 },
 178   { "jbf",      JC,     0,      0xE800 },
 179   { "jbr",      JU,     1,      0xF000 },
 180   { "jbsr",     JL,     0,      0xF800 },
 181
 182 /* The following are aliases for other instructions */
 183   { "rts",      O0,     2,      0x00CF },  /* jmp r15 */
 184   { "rolc",     DO21,   0,      0x0600 },  /* addc rd,rd */
 185   { "rotlc",    DO21,   0,      0x0600 },  /* addc rd,rd */
 186   { "setc",     O0,     0,      0x0C00 },  /* cmphs r0,r0 */
 187   { "clrc",     O0,     0,      0x0F00 },  /* cmpne r0,r0 */
 188   { "tstle",    O1,     0,      0x2200 },  /* cmplti rd,1 */
 189   { "cmplei",   OB,     0,      0x2200 },  /* cmplei rd,X -> cmplti rd,X+1 */
 190   { "neg",      O1,     0,      0x2800 },  /* rsubi rd,0 */
 191   { "tstne",    O1,     0,      0x2A00 },  /* cmpnei rd,0 */
 192   { "tstlt",    O1,     0,      0x37F0 },  /* btsti rx,31 */
 193   { "mclri",    OB2,    0,      0x3000 },  /* bclri rx,log2(imm) */
 194   { "mgeni",    OBR2,   0,      0x3200 },  /* bgeni rx,log2(imm) */
 195   { "mseti",    OB2,    0,      0x3400 },  /* bseti rx,log2(imm) */
 196   { "mtsti",    OB2,    0,      0x3600 },  /* btsti rx,log2(imm) */
 197   { "rori",     RSI,    0,      0x3800 },
 198   { "rotri",    RSI,    0,      0x3800 },
 199   { "nop",      O0,     0,      0x1200 },  /* mov r0, r0 */
 200   { 0,          0,      0,      0 }
 201 };
 202 #endif