gas/config/m68k-parse.h

   1 /* m68k-parse.h -- header file for m68k assembler
   2    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #ifndef M68K_PARSE_H
  23 #define M68K_PARSE_H
  24
  25 /* This header file defines things which are shared between the
  26    operand parser in m68k.y and the m68k assembler proper in
  27    tc-m68k.c.  */
  28
  29 /* The various m68k registers.  */
  30
  31 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
  32    0-7==data reg, 8-15==addr reg for operands that take both types.
  33
  34    We don't use forms like "ADDR0 = ADDR" here because this file is
  35    likely to be used on an Apollo, and the broken Apollo compiler
  36    gives an `undefined variable' error if we do that, according to
  37    troy@cbme.unsw.edu.au.  */
  38
  39 #define DATA DATA0
  40 #define ADDR ADDR0
  41 #define SP ADDR7
  42 #define BAD BAD0
  43 #define BAC BAC0
  44
  45 enum m68k_register
  46 {
  47   DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
  48   DATA1,
  49   DATA2,
  50   DATA3,
  51   DATA4,
  52   DATA5,
  53   DATA6,
  54   DATA7,
  55
  56   ADDR0,
  57   ADDR1,
  58   ADDR2,
  59   ADDR3,
  60   ADDR4,
  61   ADDR5,
  62   ADDR6,
  63   ADDR7,
  64
  65   FP0,                          /* Eight FP registers */
  66   FP1,
  67   FP2,
  68   FP3,
  69   FP4,
  70   FP5,
  71   FP6,
  72   FP7,
  73
  74   COP0,                         /* Co-processor #0-#7 */
  75   COP1,
  76   COP2,
  77   COP3,
  78   COP4,
  79   COP5,
  80   COP6,
  81   COP7,
  82
  83   PC,                           /* Program counter */
  84   ZPC,                          /* Hack for Program space, but 0 addressing */
  85   SR,                           /* Status Reg */
  86   CCR,                          /* Condition code Reg */
  87   ACC,                          /* Accumulator Reg */
  88   MACSR,                        /* MAC Status Reg */
  89   MASK,                         /* Modulus Reg */
  90
  91   /* These have to be grouped together for the movec instruction to work.  */
  92   USP,                          /*  User Stack Pointer */
  93   ISP,                          /*  Interrupt stack pointer */
  94   SFC,
  95   DFC,
  96   CACR,
  97   VBR,
  98   CAAR,
  99   MSP,
 100   ITT0,
 101   ITT1,
 102   DTT0,
 103   DTT1,
 104   MMUSR,
 105   TC,
 106   SRP,
 107   URP,
 108   BUSCR,                        /* 68060 added these */
 109   PCR,
 110   ROMBAR,                       /* mcf5200 added these */
 111   RAMBAR0,
 112   RAMBAR1,
 113   MBAR,
 114 #define last_movec_reg MBAR
 115   /* end of movec ordering constraints */
 116
 117   FPI,
 118   FPS,
 119   FPC,
 120
 121   DRP,                          /* 68851 or 68030 MMU regs */
 122   CRP,
 123   CAL,
 124   VAL,
 125   SCC,
 126   AC,
 127   BAD0,
 128   BAD1,
 129   BAD2,
 130   BAD3,
 131   BAD4,
 132   BAD5,
 133   BAD6,
 134   BAD7,
 135   BAC0,
 136   BAC1,
 137   BAC2,
 138   BAC3,
 139   BAC4,
 140   BAC5,
 141   BAC6,
 142   BAC7,
 143   PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
 144                                    and ACUSR on 68ec030 */
 145   PCSR,
 146
 147   IC,                           /* instruction cache token */
 148   DC,                           /* data cache token */
 149   NC,                           /* no cache token */
 150   BC,                           /* both caches token */
 151
 152   TT0,                          /* 68030 access control unit regs */
 153   TT1,
 154
 155   ZDATA0,                       /* suppressed data registers.  */
 156   ZDATA1,
 157   ZDATA2,
 158   ZDATA3,
 159   ZDATA4,
 160   ZDATA5,
 161   ZDATA6,
 162   ZDATA7,
 163
 164   ZADDR0,                       /* suppressed address registers.  */
 165   ZADDR1,
 166   ZADDR2,
 167   ZADDR3,
 168   ZADDR4,
 169   ZADDR5,
 170   ZADDR6,
 171   ZADDR7,
 172
 173   /* Upper and lower half of data and address registers.  Order *must*
 174      be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
 175   DATA0L,                       /* lower half of data registers */
 176   DATA1L,
 177   DATA2L,
 178   DATA3L,
 179   DATA4L,
 180   DATA5L,
 181   DATA6L,
 182   DATA7L,
 183
 184   ADDR0L,                       /* lower half of address registers */
 185   ADDR1L,
 186   ADDR2L,
 187   ADDR3L,
 188   ADDR4L,
 189   ADDR5L,
 190   ADDR6L,
 191   ADDR7L,
 192
 193   DATA0U,                       /* upper half of data registers */
 194   DATA1U,
 195   DATA2U,
 196   DATA3U,
 197   DATA4U,
 198   DATA5U,
 199   DATA6U,
 200   DATA7U,
 201
 202   ADDR0U,                       /* upper half of address registers */
 203   ADDR1U,
 204   ADDR2U,
 205   ADDR3U,
 206   ADDR4U,
 207   ADDR5U,
 208   ADDR6U,
 209   ADDR7U,
 210 };
 211
 212 /* Size information.  */
 213
 214 enum m68k_size
 215 {
 216   /* Unspecified.  */
 217   SIZE_UNSPEC,
 218
 219   /* Byte.  */
 220   SIZE_BYTE,
 221
 222   /* Word (2 bytes).  */
 223   SIZE_WORD,
 224
 225   /* Longword (4 bytes).  */
 226   SIZE_LONG
 227 };
 228
 229 /* The structure used to hold information about an index register.  */
 230
 231 struct m68k_indexreg
 232 {
 233   /* The index register itself.  */
 234   enum m68k_register reg;
 235
 236   /* The size to use.  */
 237   enum m68k_size size;
 238
 239   /* The value to scale by.  */
 240   int scale;
 241 };
 242
 243 #ifdef OBJ_ELF
 244 /* The type of a PIC expression.  */
 245
 246 enum pic_relocation
 247 {
 248   pic_none,                     /* not pic */
 249   pic_plt_pcrel,                /* @PLTPC */
 250   pic_got_pcrel,                /* @GOTPC */
 251   pic_plt_off,                  /* @PLT */
 252   pic_got_off                   /* @GOT */
 253 };
 254 #endif
 255
 256 /* The structure used to hold information about an expression.  */
 257
 258 struct m68k_exp
 259 {
 260   /* The size to use.  */
 261   enum m68k_size size;
 262
 263 #ifdef OBJ_ELF
 264   /* The type of pic relocation if any.  */
 265   enum pic_relocation pic_reloc;
 266 #endif
 267
 268   /* The expression itself.  */
 269   expressionS exp;
 270 };
 271
 272 /* The operand modes.  */
 273
 274 enum m68k_operand_type
 275 {
 276   IMMED = 1,
 277   ABSL,
 278   DREG,
 279   AREG,
 280   FPREG,
 281   CONTROL,
 282   AINDR,
 283   AINC,
 284   ADEC,
 285   DISP,
 286   BASE,
 287   POST,
 288   PRE,
 289   REGLST
 290 };
 291
 292 /* The structure used to hold a parsed operand.  */
 293
 294 struct m68k_op
 295 {
 296   /* The type of operand.  */
 297   enum m68k_operand_type mode;
 298
 299   /* The main register.  */
 300   enum m68k_register reg;
 301
 302   /* The register mask for mode REGLST.  */
 303   unsigned long mask;
 304
 305   /* An error message.  */
 306   const char *error;
 307
 308   /* The index register.  */
 309   struct m68k_indexreg index;
 310
 311   /* The displacement.  */
 312   struct m68k_exp disp;
 313
 314   /* The outer displacement.  */
 315   struct m68k_exp odisp;
 316 };
 317
 318 #endif /* ! defined (M68K_PARSE_H) */
 319
 320 /* The parsing function.  */
 321
 322 extern int m68k_ip_op PARAMS ((char *, struct m68k_op *));
 323
 324 /* Whether register prefixes are optional.  */
 325 extern int flag_reg_prefix_optional;