1 /* Print Motorola 68k instructions.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "floatformat.h"
26 #include "libiberty.h"
29 #include "opcode/m68k.h"
31 /* Local function prototypes. */
33 const char * const fpcr_names
[] =
35 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
36 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
39 static char *const reg_names
[] =
41 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
42 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
46 /* Name of register halves for MAC/EMAC.
47 Seperate from reg_names since 'spu', 'fpl' look weird. */
48 static char *const reg_half_names
[] =
50 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
51 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
55 /* Sign-extend an (unsigned char). */
57 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
59 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
62 /* Get a 1 byte signed integer. */
63 #define NEXTBYTE(p, val) \
67 if (!FETCH_DATA (info, p)) \
69 val = COERCE_SIGNED_CHAR (p[-1]); \
73 /* Get a 2 byte signed integer. */
74 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
76 #define NEXTWORD(p, val, ret_val) \
80 if (!FETCH_DATA (info, p)) \
82 val = COERCE16 ((p[-2] << 8) + p[-1]); \
86 /* Get a 4 byte signed integer. */
87 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
89 #define NEXTLONG(p, val, ret_val) \
93 if (!FETCH_DATA (info, p)) \
95 val = COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \
99 /* Get a 4 byte unsigned integer. */
100 #define NEXTULONG(p, val) \
104 if (!FETCH_DATA (info, p)) \
106 val = (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \
110 /* Get a single precision float. */
111 #define NEXTSINGLE(val, p) \
115 if (!FETCH_DATA (info, p)) \
117 floatformat_to_double (& floatformat_ieee_single_big, \
118 (char *) p - 4, & val); \
122 /* Get a double precision float. */
123 #define NEXTDOUBLE(val, p) \
127 if (!FETCH_DATA (info, p)) \
129 floatformat_to_double (& floatformat_ieee_double_big, \
130 (char *) p - 8, & val); \
134 /* Get an extended precision float. */
135 #define NEXTEXTEND(val, p) \
139 if (!FETCH_DATA (info, p)) \
141 floatformat_to_double (& floatformat_m68881_ext, \
142 (char *) p - 12, & val); \
146 /* Need a function to convert from packed to double
147 precision. Actually, it's easier to print a
148 packed number than a double anyway, so maybe
149 there should be a special case to handle this... */
150 #define NEXTPACKED(p, val) \
154 if (!FETCH_DATA (info, p)) \
161 /* Maximum length of an instruction. */
168 /* Points to first byte not fetched. */
169 bfd_byte
*max_fetched
;
170 bfd_byte the_buffer
[MAXLEN
];
174 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
175 to ADDR (exclusive) are valid. Returns 1 for success, 0 on error. */
176 #define FETCH_DATA(info, addr) \
177 ((addr) <= ((struct private *) (info->private_data))->max_fetched \
178 ? 1 : fetch_data ((info), (addr)))
181 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
184 struct private *priv
= (struct private *)info
->private_data
;
185 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
187 status
= (*info
->read_memory_func
) (start
,
189 addr
- priv
->max_fetched
,
193 (*info
->memory_error_func
) (status
, start
, info
);
197 priv
->max_fetched
= addr
;
201 /* This function is used to print to the bit-bucket. */
203 dummy_printer (FILE *file ATTRIBUTE_UNUSED
,
204 const char *format ATTRIBUTE_UNUSED
,
211 dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED
,
212 struct disassemble_info
*info ATTRIBUTE_UNUSED
)
216 /* Fetch BITS bits from a position in the instruction specified by CODE.
217 CODE is a "place to put an argument", or 'x' for a destination
218 that is a general address (mode and register).
219 BUFFER contains the instruction.
220 Returns -1 on failure. */
223 fetch_arg (unsigned char *buffer
,
226 disassemble_info
*info
)
232 case '/': /* MAC/EMAC mask bit. */
233 val
= buffer
[3] >> 5;
236 case 'G': /* EMAC ACC load. */
237 val
= ((buffer
[3] >> 3) & 0x2) | ((~buffer
[1] >> 7) & 0x1);
240 case 'H': /* EMAC ACC !load. */
241 val
= ((buffer
[3] >> 3) & 0x2) | ((buffer
[1] >> 7) & 0x1);
244 case ']': /* EMAC ACCEXT bit. */
245 val
= buffer
[0] >> 2;
248 case 'I': /* MAC/EMAC scale factor. */
249 val
= buffer
[2] >> 1;
252 case 'F': /* EMAC ACCx. */
253 val
= buffer
[0] >> 1;
264 case 'd': /* Destination, for register or quick. */
265 val
= (buffer
[0] << 8) + buffer
[1];
269 case 'x': /* Destination, for general arg. */
270 val
= (buffer
[0] << 8) + buffer
[1];
275 if (! FETCH_DATA (info
, buffer
+ 3))
277 val
= (buffer
[3] >> 4);
281 if (! FETCH_DATA (info
, buffer
+ 3))
287 if (! FETCH_DATA (info
, buffer
+ 3))
289 val
= (buffer
[2] << 8) + buffer
[3];
294 if (! FETCH_DATA (info
, buffer
+ 3))
296 val
= (buffer
[2] << 8) + buffer
[3];
302 if (! FETCH_DATA (info
, buffer
+ 3))
304 val
= (buffer
[2] << 8) + buffer
[3];
308 if (! FETCH_DATA (info
, buffer
+ 5))
310 val
= (buffer
[4] << 8) + buffer
[5];
315 if (! FETCH_DATA (info
, buffer
+ 5))
317 val
= (buffer
[4] << 8) + buffer
[5];
322 if (! FETCH_DATA (info
, buffer
+ 5))
324 val
= (buffer
[4] << 8) + buffer
[5];
328 if (! FETCH_DATA (info
, buffer
+ 3))
330 val
= (buffer
[2] << 8) + buffer
[3];
335 if (! FETCH_DATA (info
, buffer
+ 3))
337 val
= (buffer
[2] << 8) + buffer
[3];
342 if (! FETCH_DATA (info
, buffer
+ 3))
344 val
= (buffer
[2] << 8) + buffer
[3];
349 val
= (buffer
[1] >> 6);
353 if (! FETCH_DATA (info
, buffer
+ 3))
355 val
= (buffer
[2] >> 1);
359 val
= (buffer
[1] & 0x40 ? 0x8 : 0)
360 | ((buffer
[0] >> 1) & 0x7)
361 | (buffer
[3] & 0x80 ? 0x10 : 0);
365 val
= (buffer
[1] & 0x40 ? 0x8 : 0) | ((buffer
[0] >> 1) & 0x7);
369 val
= (buffer
[2] >> 4) | (buffer
[3] & 0x80 ? 0x10 : 0);
373 val
= (buffer
[1] & 0xf) | (buffer
[3] & 0x40 ? 0x10 : 0);
377 val
= (buffer
[3] & 0xf) | (buffer
[3] & 0x40 ? 0x10 : 0);
381 val
= buffer
[2] >> 2;
388 /* bits is never too big. */
389 return val
& ((1 << bits
) - 1);
392 /* Check if an EA is valid for a particular code. This is required
393 for the EMAC instructions since the type of source address determines
394 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
395 is a non-load EMAC instruction and the bits mean register Ry.
396 A similar case exists for the movem instructions where the register
397 mask is interpreted differently for different EAs. */
400 m68k_valid_ea (char code
, int val
)
403 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
404 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
405 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
410 mask
= M (1,1,1,1,1,1,1,1,1,1,1,1);
413 mask
= M (0,0,1,1,1,1,1,1,1,0,0,0);
416 mask
= M (1,1,1,1,1,1,1,1,1,0,0,0);
419 mask
= M (1,0,1,1,1,1,1,1,1,1,1,1);
422 mask
= M (1,0,1,1,1,1,1,1,1,1,1,0);
425 mask
= M (0,0,1,0,0,1,1,1,1,1,1,0);
428 mask
= M (0,0,1,0,0,1,1,1,1,0,0,0);
431 mask
= M (1,0,1,1,1,1,1,1,1,0,0,0);
434 mask
= M (1,0,1,0,0,1,1,1,1,0,0,0);
437 mask
= M (1,0,1,0,0,1,1,1,1,1,1,0);
440 mask
= M (0,0,1,0,0,1,1,1,1,1,1,0);
443 mask
= M (0,0,1,0,1,1,1,1,1,0,0,0);
446 mask
= M (0,0,1,1,0,1,1,1,1,1,1,0);
449 mask
= M (1,1,1,1,1,0,0,0,0,0,0,0);
452 mask
= M (0,0,0,0,0,1,0,0,0,1,0,0);
455 mask
= M (0,0,0,0,0,0,1,1,1,0,1,1);
458 mask
= M (1,1,1,1,1,1,0,0,0,0,0,0);
461 mask
= M (1,0,1,1,1,1,0,0,0,0,0,0);
464 mask
= M (1,0,1,1,1,1,0,1,1,0,0,0);
467 mask
= M (1,0,1,1,1,1,0,0,0,1,0,0);
470 mask
= M (0,0,1,1,1,1,0,0,0,1,0,0);
473 mask
= M (0,0,1,0,0,1,0,0,0,0,0,0);
476 mask
= M (0,0,1,0,0,1,0,0,0,1,0,0);
479 mask
= M (0,0,1,1,1,1,0,0,0,0,0,0);
486 mode
= (val
>> 3) & 7;
489 return (mask
& (1 << mode
)) != 0;
492 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
493 REGNO = -1 for pc, -2 for none (suppressed). */
496 print_base (int regno
, bfd_vma disp
, disassemble_info
*info
)
500 (*info
->fprintf_func
) (info
->stream
, "%%pc@(");
501 (*info
->print_address_func
) (disp
, info
);
508 (*info
->fprintf_func
) (info
->stream
, "@(");
509 else if (regno
== -3)
510 (*info
->fprintf_func
) (info
->stream
, "%%zpc@(");
512 (*info
->fprintf_func
) (info
->stream
, "%s@(", reg_names
[regno
]);
514 sprintf_vma (buf
, disp
);
515 (*info
->fprintf_func
) (info
->stream
, "%s", buf
);
519 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
520 P points to extension word, in buffer.
521 ADDR is the nominal core address of that extension word.
522 Returns NULL upon error. */
524 static unsigned char *
525 print_indexed (int basereg
,
528 disassemble_info
*info
)
531 static char *const scales
[] = { "", ":2", ":4", ":8" };
537 NEXTWORD (p
, word
, NULL
);
539 /* Generate the text for the index register.
540 Where this will be output is not yet determined. */
541 sprintf (buf
, "%s:%c%s",
542 reg_names
[(word
>> 12) & 0xf],
543 (word
& 0x800) ? 'l' : 'w',
544 scales
[(word
>> 9) & 3]);
546 /* Handle the 68000 style of indexing. */
548 if ((word
& 0x100) == 0)
550 base_disp
= word
& 0xff;
551 if ((base_disp
& 0x80) != 0)
555 print_base (basereg
, base_disp
, info
);
556 (*info
->fprintf_func
) (info
->stream
, ",%s)", buf
);
560 /* Handle the generalized kind. */
561 /* First, compute the displacement to add to the base register. */
572 switch ((word
>> 4) & 3)
575 NEXTWORD (p
, base_disp
, NULL
);
578 NEXTLONG (p
, base_disp
, NULL
);
583 /* Handle single-level case (not indirect). */
586 print_base (basereg
, base_disp
, info
);
588 (*info
->fprintf_func
) (info
->stream
, ",%s", buf
);
589 (*info
->fprintf_func
) (info
->stream
, ")");
593 /* Two level. Compute displacement to add after indirection. */
598 NEXTWORD (p
, outer_disp
, NULL
);
601 NEXTLONG (p
, outer_disp
, NULL
);
604 print_base (basereg
, base_disp
, info
);
605 if ((word
& 4) == 0 && buf
[0] != '\0')
607 (*info
->fprintf_func
) (info
->stream
, ",%s", buf
);
610 sprintf_vma (vmabuf
, outer_disp
);
611 (*info
->fprintf_func
) (info
->stream
, ")@(%s", vmabuf
);
613 (*info
->fprintf_func
) (info
->stream
, ",%s", buf
);
614 (*info
->fprintf_func
) (info
->stream
, ")");
619 #define FETCH_ARG(size, val) \
622 val = fetch_arg (buffer, place, size, info); \
628 /* Returns number of bytes "eaten" by the operand, or
629 return -1 if an invalid operand was found, or -2 if
630 an opcode tabe error was found or -3 to simply abort.
631 ADDR is the pc for this arg to be relative to. */
634 print_insn_arg (const char *d
,
635 unsigned char *buffer
,
638 disassemble_info
*info
)
642 unsigned char *p
= p0
;
653 case 'c': /* Cache identifier. */
655 static char *const cacheFieldName
[] = { "nc", "dc", "ic", "bc" };
657 (*info
->fprintf_func
) (info
->stream
, cacheFieldName
[val
]);
661 case 'a': /* Address register indirect only. Cf. case '+'. */
664 (*info
->fprintf_func
) (info
->stream
, "%s@", reg_names
[val
+ 8]);
668 case '_': /* 32-bit absolute address for move16. */
671 (*info
->print_address_func
) (uval
, info
);
676 (*info
->fprintf_func
) (info
->stream
, "%%ccr");
680 (*info
->fprintf_func
) (info
->stream
, "%%sr");
684 (*info
->fprintf_func
) (info
->stream
, "%%usp");
688 (*info
->fprintf_func
) (info
->stream
, "%%acc");
692 (*info
->fprintf_func
) (info
->stream
, "%%macsr");
696 (*info
->fprintf_func
) (info
->stream
, "%%mask");
701 /* FIXME: There's a problem here, different m68k processors call the
702 same address different names. This table can't get it right
703 because it doesn't know which processor it's disassembling for. */
704 static const struct { char *name
; int value
; } names
[]
705 = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
706 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
707 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
708 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
709 {"%msp", 0x803}, {"%isp", 0x804},
710 /* reg c04 is sometimes called flashbar or rambar.
711 rec c05 is also sometimes called rambar. */
712 {"%rambar0", 0xc04}, {"%rambar1", 0xc05},
714 /* Should we be calling this psr like we do in case 'Y'? */
717 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808},
719 /* Fido added these. */
720 {"%cac", 0xffe}, {"%mbo", 0xfff}};
723 for (regno
= sizeof names
/ sizeof names
[0] - 1; regno
>= 0; regno
--)
724 if (names
[regno
].value
== val
)
726 (*info
->fprintf_func
) (info
->stream
, "%s", names
[regno
].name
);
730 (*info
->fprintf_func
) (info
->stream
, "%d", val
);
736 /* 0 means 8, except for the bkpt instruction... */
737 if (val
== 0 && d
[1] != 's')
739 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
747 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
752 (*info
->fprintf_func
) (info
->stream
, "#%d", val
+1);
757 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
763 static char *const scalefactor_name
[] = { "<<", ">>" };
766 (*info
->fprintf_func
) (info
->stream
, scalefactor_name
[val
]);
773 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
779 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
784 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
]);
789 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
+ 010]);
794 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
]);
798 FETCH_ARG (4, regno
);
800 (*info
->fprintf_func
) (info
->stream
, "%s@", reg_names
[regno
]);
802 (*info
->fprintf_func
) (info
->stream
, "@(%s)", reg_names
[regno
]);
807 (*info
->fprintf_func
) (info
->stream
, "%%fp%d", val
);
813 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
& 7]);
815 (*info
->fprintf_func
) (info
->stream
, "%d", val
);
820 (*info
->fprintf_func
) (info
->stream
, "%s@+", reg_names
[val
+ 8]);
825 (*info
->fprintf_func
) (info
->stream
, "%s@-", reg_names
[val
+ 8]);
832 (*info
->fprintf_func
) (info
->stream
, "{%s}", reg_names
[val
]);
834 else if (place
== 'C')
837 if (val
> 63) /* This is a signed constant. */
839 (*info
->fprintf_func
) (info
->stream
, "{#%d}", val
);
847 p1
= buffer
+ (*d
== '#' ? 2 : 4);
850 else if (place
== 'C')
852 else if (place
== '8')
854 else if (place
== '3')
856 else if (place
== 'b')
858 else if (place
== 'w' || place
== 'W')
859 NEXTWORD (p1
, val
, -3);
860 else if (place
== 'l')
861 NEXTLONG (p1
, val
, -3);
865 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
871 else if (place
== 'B')
872 disp
= COERCE_SIGNED_CHAR (buffer
[1]);
873 else if (place
== 'w' || place
== 'W')
874 NEXTWORD (p
, disp
, -3);
875 else if (place
== 'l' || place
== 'L' || place
== 'C')
876 NEXTLONG (p
, disp
, -3);
877 else if (place
== 'g')
879 NEXTBYTE (buffer
, disp
);
881 NEXTWORD (p
, disp
, -3);
883 NEXTLONG (p
, disp
, -3);
885 else if (place
== 'c')
887 if (buffer
[1] & 0x40) /* If bit six is one, long offset. */
888 NEXTLONG (p
, disp
, -3);
890 NEXTWORD (p
, disp
, -3);
895 (*info
->print_address_func
) (addr
+ disp
, info
);
902 NEXTWORD (p
, val
, -3);
904 (*info
->fprintf_func
) (info
->stream
, "%s@(%d)", reg_names
[val1
+ 8], val
);
910 (*info
->fprintf_func
) (info
->stream
, "%s", fpcr_names
[val
]);
915 (*info
->fprintf_func
) (info
->stream
, "%%acc%d", val
);
920 (*info
->fprintf_func
) (info
->stream
, "%%accext%s", val
== 0 ? "01" : "23");
926 (*info
->fprintf_func
) (info
->stream
, "<<");
928 (*info
->fprintf_func
) (info
->stream
, ">>");
934 /* Get coprocessor ID... */
935 val
= fetch_arg (buffer
, 'd', 3, info
);
938 if (val
!= 1) /* Unusual coprocessor ID? */
939 (*info
->fprintf_func
) (info
->stream
, "(cpid=%d) ", val
);
968 val
= fetch_arg (buffer
, 'x', 6, info
);
971 val
= ((val
& 7) << 3) + ((val
>> 3) & 7);
975 val
= fetch_arg (buffer
, 's', 6, info
);
980 /* If the <ea> is invalid for *d, then reject this match. */
981 if (!m68k_valid_ea (*d
, val
))
984 /* Get register number assuming address register. */
985 regno
= (val
& 7) + 8;
986 regname
= reg_names
[regno
];
990 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[val
]);
994 (*info
->fprintf_func
) (info
->stream
, "%s", regname
);
998 (*info
->fprintf_func
) (info
->stream
, "%s@", regname
);
1002 (*info
->fprintf_func
) (info
->stream
, "%s@+", regname
);
1006 (*info
->fprintf_func
) (info
->stream
, "%s@-", regname
);
1010 NEXTWORD (p
, val
, -3);
1011 (*info
->fprintf_func
) (info
->stream
, "%s@(%d)", regname
, val
);
1015 p
= print_indexed (regno
, p
, addr
, info
);
1024 NEXTWORD (p
, val
, -3);
1025 (*info
->print_address_func
) (val
, info
);
1029 NEXTULONG (p
, uval
);
1030 (*info
->print_address_func
) (uval
, info
);
1034 NEXTWORD (p
, val
, -3);
1035 (*info
->fprintf_func
) (info
->stream
, "%%pc@(");
1036 (*info
->print_address_func
) (addr
+ val
, info
);
1037 (*info
->fprintf_func
) (info
->stream
, ")");
1041 p
= print_indexed (-1, p
, addr
, info
);
1047 flt_p
= 1; /* Assume it's a float... */
1056 NEXTWORD (p
, val
, -3);
1061 NEXTLONG (p
, val
, -3);
1066 NEXTSINGLE (flval
, p
);
1070 NEXTDOUBLE (flval
, p
);
1074 NEXTEXTEND (flval
, p
);
1078 NEXTPACKED (p
, flval
);
1084 if (flt_p
) /* Print a float? */
1085 (*info
->fprintf_func
) (info
->stream
, "#%g", flval
);
1087 (*info
->fprintf_func
) (info
->stream
, "#%d", val
);
1095 /* If place is '/', then this is the case of the mask bit for
1096 mac/emac loads. Now that the arg has been printed, grab the
1097 mask bit and if set, add a '&' to the arg. */
1102 info
->fprintf_func (info
->stream
, "&");
1112 NEXTWORD (p1
, val
, -3);
1113 /* Move the pointer ahead if this point is farther ahead
1115 p
= p1
> p
? p1
: p
;
1118 (*info
->fprintf_func
) (info
->stream
, "#0");
1125 for (regno
= 0; regno
< 16; ++regno
)
1126 if (val
& (0x8000 >> regno
))
1127 newval
|= 1 << regno
;
1132 for (regno
= 0; regno
< 16; ++regno
)
1133 if (val
& (1 << regno
))
1138 (*info
->fprintf_func
) (info
->stream
, "/");
1140 (*info
->fprintf_func
) (info
->stream
, "%s", reg_names
[regno
]);
1141 first_regno
= regno
;
1142 while (val
& (1 << (regno
+ 1)))
1144 if (regno
> first_regno
)
1145 (*info
->fprintf_func
) (info
->stream
, "-%s",
1149 else if (place
== '3')
1151 /* `fmovem' insn. */
1157 (*info
->fprintf_func
) (info
->stream
, "#0");
1164 for (regno
= 0; regno
< 8; ++regno
)
1165 if (val
& (0x80 >> regno
))
1166 newval
|= 1 << regno
;
1171 for (regno
= 0; regno
< 8; ++regno
)
1172 if (val
& (1 << regno
))
1176 (*info
->fprintf_func
) (info
->stream
, "/");
1178 (*info
->fprintf_func
) (info
->stream
, "%%fp%d", regno
);
1179 first_regno
= regno
;
1180 while (val
& (1 << (regno
+ 1)))
1182 if (regno
> first_regno
)
1183 (*info
->fprintf_func
) (info
->stream
, "-%%fp%d", regno
);
1186 else if (place
== '8')
1189 /* fmoveml for FP status registers. */
1190 (*info
->fprintf_func
) (info
->stream
, "%s", fpcr_names
[val
]);
1212 case 2: name
= "%tt0"; break;
1213 case 3: name
= "%tt1"; break;
1214 case 0x10: name
= "%tc"; break;
1215 case 0x11: name
= "%drp"; break;
1216 case 0x12: name
= "%srp"; break;
1217 case 0x13: name
= "%crp"; break;
1218 case 0x14: name
= "%cal"; break;
1219 case 0x15: name
= "%val"; break;
1220 case 0x16: name
= "%scc"; break;
1221 case 0x17: name
= "%ac"; break;
1222 case 0x18: name
= "%psr"; break;
1223 case 0x19: name
= "%pcsr"; break;
1227 int break_reg
= ((buffer
[3] >> 2) & 7);
1229 (*info
->fprintf_func
)
1230 (info
->stream
, val
== 0x1c ? "%%bad%d" : "%%bac%d",
1235 (*info
->fprintf_func
) (info
->stream
, "<mmu register %d>", val
);
1238 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
1248 (*info
->fprintf_func
) (info
->stream
, "%%dfc");
1250 (*info
->fprintf_func
) (info
->stream
, "%%sfc");
1252 /* xgettext:c-format */
1253 (*info
->fprintf_func
) (info
->stream
, _("<function code %d>"), fc
);
1258 (*info
->fprintf_func
) (info
->stream
, "%%val");
1265 FETCH_ARG (3, level
);
1266 (*info
->fprintf_func
) (info
->stream
, "%d", level
);
1281 (*info
->fprintf_func
) (info
->stream
, "%s%s",
1282 reg_half_names
[reg
],
1283 is_upper
? "u" : "l");
1294 /* Try to match the current instruction to best and if so, return the
1295 number of bytes consumed from the instruction stream, else zero. */
1298 match_insn_m68k (bfd_vma memaddr
,
1299 disassemble_info
* info
,
1300 const struct m68k_opcode
* best
)
1302 unsigned char *save_p
;
1305 const char *args
= best
->args
;
1307 struct private *priv
= (struct private *) info
->private_data
;
1308 bfd_byte
*buffer
= priv
->the_buffer
;
1309 fprintf_ftype save_printer
= info
->fprintf_func
;
1310 void (* save_print_address
) (bfd_vma
, struct disassemble_info
*)
1311 = info
->print_address_func
;
1316 /* Point at first word of argument data,
1317 and at descriptor for first argument. */
1320 /* Figure out how long the fixed-size portion of the instruction is.
1321 The only place this is stored in the opcode table is
1322 in the arguments--look for arguments which specify fields in the 2nd
1323 or 3rd words of the instruction. */
1324 for (d
= args
; *d
; d
+= 2)
1326 /* I don't think it is necessary to be checking d[0] here;
1327 I suspect all this could be moved to the case statement below. */
1330 if (d
[1] == 'l' && p
- buffer
< 6)
1332 else if (p
- buffer
< 4 && d
[1] != 'C' && d
[1] != '8')
1336 if ((d
[0] == 'L' || d
[0] == 'l') && d
[1] == 'w' && p
- buffer
< 4)
1362 /* pflusha is an exceptions. It takes no arguments but is two words
1363 long. Recognize it by looking at the lower 16 bits of the mask. */
1364 if (p
- buffer
< 4 && (best
->match
& 0xFFFF) != 0)
1367 /* lpstop is another exception. It takes a one word argument but is
1368 three words long. */
1370 && (best
->match
& 0xffff) == 0xffff
1374 /* Copy the one word argument into the usual location for a one
1375 word argument, to simplify printing it. We can get away with
1376 this because we know exactly what the second word is, and we
1377 aren't going to print anything based on it. */
1379 FETCH_DATA (info
, p
);
1380 buffer
[2] = buffer
[4];
1381 buffer
[3] = buffer
[5];
1384 FETCH_DATA (info
, p
);
1387 info
->print_address_func
= dummy_print_address
;
1388 info
->fprintf_func
= (fprintf_ftype
) dummy_printer
;
1390 /* We scan the operands twice. The first time we don't print anything,
1391 but look for errors. */
1392 for (d
= args
; *d
; d
+= 2)
1394 int eaten
= print_insn_arg (d
, buffer
, p
, memaddr
+ (p
- buffer
), info
);
1398 else if (eaten
== -1 || eaten
== -3)
1400 info
->fprintf_func
= save_printer
;
1401 info
->print_address_func
= save_print_address
;
1406 /* We must restore the print functions before trying to print the
1408 info
->fprintf_func
= save_printer
;
1409 info
->print_address_func
= save_print_address
;
1410 info
->fprintf_func (info
->stream
,
1411 /* xgettext:c-format */
1412 _("<internal error in opcode table: %s %s>\n"),
1413 best
->name
, best
->args
);
1419 info
->fprintf_func
= save_printer
;
1420 info
->print_address_func
= save_print_address
;
1424 info
->fprintf_func (info
->stream
, "%s", best
->name
);
1427 info
->fprintf_func (info
->stream
, " ");
1431 p
+= print_insn_arg (d
, buffer
, p
, memaddr
+ (p
- buffer
), info
);
1434 if (*d
&& *(d
- 2) != 'I' && *d
!= 'k')
1435 info
->fprintf_func (info
->stream
, ",");
1441 /* Try to interpret the instruction at address MEMADDR as one that
1442 can execute on a processor with the features given by ARCH_MASK.
1443 If successful, print the instruction to INFO->STREAM and return
1444 its length in bytes. Return 0 otherwise. */
1447 m68k_scan_mask (bfd_vma memaddr
, disassemble_info
*info
,
1448 unsigned int arch_mask
)
1452 static const struct m68k_opcode
**opcodes
[16];
1453 static int numopcodes
[16];
1457 struct private *priv
= (struct private *) info
->private_data
;
1458 bfd_byte
*buffer
= priv
->the_buffer
;
1462 /* Speed up the matching by sorting the opcode
1463 table on the upper four bits of the opcode. */
1464 const struct m68k_opcode
**opc_pointer
[16];
1466 /* First count how many opcodes are in each of the sixteen buckets. */
1467 for (i
= 0; i
< m68k_numopcodes
; i
++)
1468 numopcodes
[(m68k_opcodes
[i
].opcode
>> 28) & 15]++;
1470 /* Then create a sorted table of pointers
1471 that point into the unsorted table. */
1472 opc_pointer
[0] = xmalloc (sizeof (struct m68k_opcode
*)
1474 opcodes
[0] = opc_pointer
[0];
1476 for (i
= 1; i
< 16; i
++)
1478 opc_pointer
[i
] = opc_pointer
[i
- 1] + numopcodes
[i
- 1];
1479 opcodes
[i
] = opc_pointer
[i
];
1482 for (i
= 0; i
< m68k_numopcodes
; i
++)
1483 *opc_pointer
[(m68k_opcodes
[i
].opcode
>> 28) & 15]++ = &m68k_opcodes
[i
];
1486 FETCH_DATA (info
, buffer
+ 2);
1487 major_opcode
= (buffer
[0] >> 4) & 15;
1489 for (i
= 0; i
< numopcodes
[major_opcode
]; i
++)
1491 const struct m68k_opcode
*opc
= opcodes
[major_opcode
][i
];
1492 unsigned long opcode
= opc
->opcode
;
1493 unsigned long match
= opc
->match
;
1494 const char *args
= opc
->args
;
1499 if (((0xff & buffer
[0] & (match
>> 24)) == (0xff & (opcode
>> 24)))
1500 && ((0xff & buffer
[1] & (match
>> 16)) == (0xff & (opcode
>> 16)))
1501 /* Only fetch the next two bytes if we need to. */
1502 && (((0xffff & match
) == 0)
1504 (FETCH_DATA (info
, buffer
+ 4)
1505 && ((0xff & buffer
[2] & (match
>> 8)) == (0xff & (opcode
>> 8)))
1506 && ((0xff & buffer
[3] & match
) == (0xff & opcode
)))
1508 && (opc
->arch
& arch_mask
) != 0)
1510 /* Don't use for printout the variants of divul and divsl
1511 that have the same register number in two places.
1512 The more general variants will match instead. */
1513 for (d
= args
; *d
; d
+= 2)
1517 /* Don't use for printout the variants of most floating
1518 point coprocessor instructions which use the same
1519 register number in two places, as above. */
1521 for (d
= args
; *d
; d
+= 2)
1525 /* Don't match fmovel with more than one register;
1526 wait for fmoveml. */
1529 for (d
= args
; *d
; d
+= 2)
1531 if (d
[0] == 's' && d
[1] == '8')
1533 val
= fetch_arg (buffer
, d
[1], 3, info
);
1536 if ((val
& (val
- 1)) != 0)
1542 /* Don't match FPU insns with non-default coprocessor ID. */
1545 for (d
= args
; *d
; d
+= 2)
1549 val
= fetch_arg (buffer
, 'd', 3, info
);
1557 if ((val
= match_insn_m68k (memaddr
, info
, opc
)))
1564 /* Print the m68k instruction at address MEMADDR in debugged memory,
1565 on INFO->STREAM. Returns length of the instruction, in bytes. */
1568 print_insn_m68k (bfd_vma memaddr
, disassemble_info
*info
)
1570 unsigned int arch_mask
;
1571 struct private priv
;
1574 bfd_byte
*buffer
= priv
.the_buffer
;
1576 info
->private_data
= & priv
;
1577 /* Tell objdump to use two bytes per chunk
1578 and six bytes per line for displaying raw data. */
1579 info
->bytes_per_chunk
= 2;
1580 info
->bytes_per_line
= 6;
1581 info
->display_endian
= BFD_ENDIAN_BIG
;
1582 priv
.max_fetched
= priv
.the_buffer
;
1583 priv
.insn_start
= memaddr
;
1585 arch_mask
= bfd_m68k_mach_to_features (info
->mach
);
1588 /* First try printing an m680x0 instruction. Try printing a Coldfire
1589 one if that fails. */
1590 val
= m68k_scan_mask (memaddr
, info
, m68k_mask
);
1592 val
= m68k_scan_mask (memaddr
, info
, mcf_mask
);
1596 val
= m68k_scan_mask (memaddr
, info
, arch_mask
);
1600 /* Handle undefined instructions. */
1601 info
->fprintf_func (info
->stream
, "0%o", (buffer
[0] << 8) + buffer
[1]);
1603 return val
? val
: 2;