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2008-06-12 David Edelsohn <edelsohn@gnu.org>
[binutils.git] / opcodes / mips-dis.c
blob4202b7d1dba7a7888a5c9c0ec725b168bc585257
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_r3000[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
137 };
138
139 static const char * const mips_cp0_names_r4000[32] =
140 {
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
149 };
150
151 static const char * const mips_cp0_names_mips3264[32] =
152 {
153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
161 };
162
163 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164 {
165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
194 };
195
196 static const char * const mips_cp0_names_mips3264r2[32] =
197 {
198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
206 };
207
208 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209 {
210 { 4, 1, "c0_contextconfig" },
211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
227 { 5, 1, "c0_pagegrain" },
228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
282 };
283
284 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
285 static const char * const mips_cp0_names_sb1[32] =
286 {
287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
295 };
296
297 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298 {
299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
320 };
321
322 static const char * const mips_hwr_names_numeric[32] =
323 {
324 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
325 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
326 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
327 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
328 };
329
330 static const char * const mips_hwr_names_mips3264r2[32] =
331 {
332 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
333 "$4", "$5", "$6", "$7",
334 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
335 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
336 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
337 };
338
339 struct mips_abi_choice
340 {
341 const char * name;
342 const char * const *gpr_names;
343 const char * const *fpr_names;
344 };
345
346 struct mips_abi_choice mips_abi_choices[] =
347 {
348 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
349 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
350 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
351 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
352 };
353
354 struct mips_arch_choice
355 {
356 const char *name;
357 int bfd_mach_valid;
358 unsigned long bfd_mach;
359 int processor;
360 int isa;
361 const char * const *cp0_names;
362 const struct mips_cp0sel_name *cp0sel_names;
363 unsigned int cp0sel_names_len;
364 const char * const *hwr_names;
365 };
366
367 const struct mips_arch_choice mips_arch_choices[] =
368 {
369 { "numeric", 0, 0, 0, 0,
370 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
371
372 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
373 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
374 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
377 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
378 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
389 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
390 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
391 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
392 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
393 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
394 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
395 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
396 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
397 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
398 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
399 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
400 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
401 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
402 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
403 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
404 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
405 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
406 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
407 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
408 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
409 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
410 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
411 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
412 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
413 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
414
415 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
416 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
417 _MIPS32 Architecture For Programmers Volume I: Introduction to the
418 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
419 page 1. */
420 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
421 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
422 mips_cp0_names_mips3264,
423 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
424 mips_hwr_names_numeric },
425
426 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
427 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
428 | INSN_MIPS3D | INSN_MT),
429 mips_cp0_names_mips3264r2,
430 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
431 mips_hwr_names_mips3264r2 },
432
433 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
434 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
435 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
436 mips_cp0_names_mips3264,
437 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
438 mips_hwr_names_numeric },
439
440 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
441 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
442 | INSN_DSP64 | INSN_MT | INSN_MDMX),
443 mips_cp0_names_mips3264r2,
444 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
445 mips_hwr_names_mips3264r2 },
446
447 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
448 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
449 mips_cp0_names_sb1,
450 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
451 mips_hwr_names_numeric },
452
453 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
454 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
455 NULL, 0, mips_hwr_names_numeric },
456
457 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
458 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
459 NULL, 0, mips_hwr_names_numeric },
460
461 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
462 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
463 mips_hwr_names_numeric },
464
465 /* This entry, mips16, is here only for ISA/processor selection; do
466 not print its name. */
467 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
468 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
469 };
470
471 /* ISA and processor type to disassemble for, and register names to use.
472 set_default_mips_dis_options and parse_mips_dis_options fill in these
473 values. */
474 static int mips_processor;
475 static int mips_isa;
476 static const char * const *mips_gpr_names;
477 static const char * const *mips_fpr_names;
478 static const char * const *mips_cp0_names;
479 static const struct mips_cp0sel_name *mips_cp0sel_names;
480 static int mips_cp0sel_names_len;
481 static const char * const *mips_hwr_names;
482
483 /* Other options */
484 static int no_aliases; /* If set disassemble as most general inst. */
485 \f
486 static const struct mips_abi_choice *
487 choose_abi_by_name (const char *name, unsigned int namelen)
488 {
489 const struct mips_abi_choice *c;
490 unsigned int i;
491
492 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
493 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
494 && strlen (mips_abi_choices[i].name) == namelen)
495 c = &mips_abi_choices[i];
496
497 return c;
498 }
499
500 static const struct mips_arch_choice *
501 choose_arch_by_name (const char *name, unsigned int namelen)
502 {
503 const struct mips_arch_choice *c = NULL;
504 unsigned int i;
505
506 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
507 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
508 && strlen (mips_arch_choices[i].name) == namelen)
509 c = &mips_arch_choices[i];
510
511 return c;
512 }
513
514 static const struct mips_arch_choice *
515 choose_arch_by_number (unsigned long mach)
516 {
517 static unsigned long hint_bfd_mach;
518 static const struct mips_arch_choice *hint_arch_choice;
519 const struct mips_arch_choice *c;
520 unsigned int i;
521
522 /* We optimize this because even if the user specifies no
523 flags, this will be done for every instruction! */
524 if (hint_bfd_mach == mach
525 && hint_arch_choice != NULL
526 && hint_arch_choice->bfd_mach == hint_bfd_mach)
527 return hint_arch_choice;
528
529 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
530 {
531 if (mips_arch_choices[i].bfd_mach_valid
532 && mips_arch_choices[i].bfd_mach == mach)
533 {
534 c = &mips_arch_choices[i];
535 hint_bfd_mach = mach;
536 hint_arch_choice = c;
537 }
538 }
539 return c;
540 }
541
542 /* Check if the object uses NewABI conventions. */
543
544 static int
545 is_newabi (Elf_Internal_Ehdr *header)
546 {
547 /* There are no old-style ABIs which use 64-bit ELF. */
548 if (header->e_ident[EI_CLASS] == ELFCLASS64)
549 return 1;
550
551 /* If a 32-bit ELF file, n32 is a new-style ABI. */
552 if ((header->e_flags & EF_MIPS_ABI2) != 0)
553 return 1;
554
555 return 0;
556 }
557
558 static void
559 set_default_mips_dis_options (struct disassemble_info *info)
560 {
561 const struct mips_arch_choice *chosen_arch;
562
563 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
564 and numeric FPR, CP0 register, and HWR names. */
565 mips_isa = ISA_MIPS3;
566 mips_processor = CPU_R3000;
567 mips_gpr_names = mips_gpr_names_oldabi;
568 mips_fpr_names = mips_fpr_names_numeric;
569 mips_cp0_names = mips_cp0_names_numeric;
570 mips_cp0sel_names = NULL;
571 mips_cp0sel_names_len = 0;
572 mips_hwr_names = mips_hwr_names_numeric;
573 no_aliases = 0;
574
575 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
576 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
577 {
578 Elf_Internal_Ehdr *header;
579
580 header = elf_elfheader (info->section->owner);
581 if (is_newabi (header))
582 mips_gpr_names = mips_gpr_names_newabi;
583 }
584
585 /* Set ISA, architecture, and cp0 register names as best we can. */
586 #if ! SYMTAB_AVAILABLE
587 /* This is running out on a target machine, not in a host tool.
588 FIXME: Where does mips_target_info come from? */
589 target_processor = mips_target_info.processor;
590 mips_isa = mips_target_info.isa;
591 #else
592 chosen_arch = choose_arch_by_number (info->mach);
593 if (chosen_arch != NULL)
594 {
595 mips_processor = chosen_arch->processor;
596 mips_isa = chosen_arch->isa;
597 mips_cp0_names = chosen_arch->cp0_names;
598 mips_cp0sel_names = chosen_arch->cp0sel_names;
599 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
600 mips_hwr_names = chosen_arch->hwr_names;
601 }
602 #endif
603 }
604
605 static void
606 parse_mips_dis_option (const char *option, unsigned int len)
607 {
608 unsigned int i, optionlen, vallen;
609 const char *val;
610 const struct mips_abi_choice *chosen_abi;
611 const struct mips_arch_choice *chosen_arch;
612
613 /* Try to match options that are simple flags */
614 if (CONST_STRNEQ (option, "no-aliases"))
615 {
616 no_aliases = 1;
617 return;
618 }
619
620 /* Look for the = that delimits the end of the option name. */
621 for (i = 0; i < len; i++)
622 if (option[i] == '=')
623 break;
624
625 if (i == 0) /* Invalid option: no name before '='. */
626 return;
627 if (i == len) /* Invalid option: no '='. */
628 return;
629 if (i == (len - 1)) /* Invalid option: no value after '='. */
630 return;
631
632 optionlen = i;
633 val = option + (optionlen + 1);
634 vallen = len - (optionlen + 1);
635
636 if (strncmp ("gpr-names", option, optionlen) == 0
637 && strlen ("gpr-names") == optionlen)
638 {
639 chosen_abi = choose_abi_by_name (val, vallen);
640 if (chosen_abi != NULL)
641 mips_gpr_names = chosen_abi->gpr_names;
642 return;
643 }
644
645 if (strncmp ("fpr-names", option, optionlen) == 0
646 && strlen ("fpr-names") == optionlen)
647 {
648 chosen_abi = choose_abi_by_name (val, vallen);
649 if (chosen_abi != NULL)
650 mips_fpr_names = chosen_abi->fpr_names;
651 return;
652 }
653
654 if (strncmp ("cp0-names", option, optionlen) == 0
655 && strlen ("cp0-names") == optionlen)
656 {
657 chosen_arch = choose_arch_by_name (val, vallen);
658 if (chosen_arch != NULL)
659 {
660 mips_cp0_names = chosen_arch->cp0_names;
661 mips_cp0sel_names = chosen_arch->cp0sel_names;
662 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
663 }
664 return;
665 }
666
667 if (strncmp ("hwr-names", option, optionlen) == 0
668 && strlen ("hwr-names") == optionlen)
669 {
670 chosen_arch = choose_arch_by_name (val, vallen);
671 if (chosen_arch != NULL)
672 mips_hwr_names = chosen_arch->hwr_names;
673 return;
674 }
675
676 if (strncmp ("reg-names", option, optionlen) == 0
677 && strlen ("reg-names") == optionlen)
678 {
679 /* We check both ABI and ARCH here unconditionally, so
680 that "numeric" will do the desirable thing: select
681 numeric register names for all registers. Other than
682 that, a given name probably won't match both. */
683 chosen_abi = choose_abi_by_name (val, vallen);
684 if (chosen_abi != NULL)
685 {
686 mips_gpr_names = chosen_abi->gpr_names;
687 mips_fpr_names = chosen_abi->fpr_names;
688 }
689 chosen_arch = choose_arch_by_name (val, vallen);
690 if (chosen_arch != NULL)
691 {
692 mips_cp0_names = chosen_arch->cp0_names;
693 mips_cp0sel_names = chosen_arch->cp0sel_names;
694 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
695 mips_hwr_names = chosen_arch->hwr_names;
696 }
697 return;
698 }
699
700 /* Invalid option. */
701 }
702
703 static void
704 parse_mips_dis_options (const char *options)
705 {
706 const char *option_end;
707
708 if (options == NULL)
709 return;
710
711 while (*options != '\0')
712 {
713 /* Skip empty options. */
714 if (*options == ',')
715 {
716 options++;
717 continue;
718 }
719
720 /* We know that *options is neither NUL or a comma. */
721 option_end = options + 1;
722 while (*option_end != ',' && *option_end != '\0')
723 option_end++;
724
725 parse_mips_dis_option (options, option_end - options);
726
727 /* Go on to the next one. If option_end points to a comma, it
728 will be skipped above. */
729 options = option_end;
730 }
731 }
732
733 static const struct mips_cp0sel_name *
734 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
735 unsigned int len,
736 unsigned int cp0reg,
737 unsigned int sel)
738 {
739 unsigned int i;
740
741 for (i = 0; i < len; i++)
742 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
743 return &names[i];
744 return NULL;
745 }
746 \f
747 /* Print insn arguments for 32/64-bit code. */
748
749 static void
750 print_insn_args (const char *d,
751 register unsigned long int l,
752 bfd_vma pc,
753 struct disassemble_info *info,
754 const struct mips_opcode *opp)
755 {
756 int op, delta;
757 unsigned int lsb, msb, msbd;
758
759 lsb = 0;
760
761 for (; *d != '\0'; d++)
762 {
763 switch (*d)
764 {
765 case ',':
766 case '(':
767 case ')':
768 case '[':
769 case ']':
770 (*info->fprintf_func) (info->stream, "%c", *d);
771 break;
772
773 case '+':
774 /* Extension character; switch for second char. */
775 d++;
776 switch (*d)
777 {
778 case '\0':
779 /* xgettext:c-format */
780 (*info->fprintf_func) (info->stream,
781 _("# internal error, incomplete extension sequence (+)"));
782 return;
783
784 case 'A':
785 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
786 (*info->fprintf_func) (info->stream, "0x%x", lsb);
787 break;
788
789 case 'B':
790 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
791 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
792 break;
793
794 case '1':
795 (*info->fprintf_func) (info->stream, "0x%lx",
796 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
797 break;
798
799 case '2':
800 (*info->fprintf_func) (info->stream, "0x%lx",
801 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
802 break;
803
804 case '3':
805 (*info->fprintf_func) (info->stream, "0x%lx",
806 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
807 break;
808
809 case '4':
810 (*info->fprintf_func) (info->stream, "0x%lx",
811 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
812 break;
813
814 case 'C':
815 case 'H':
816 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
817 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
818 break;
819
820 case 'D':
821 {
822 const struct mips_cp0sel_name *n;
823 unsigned int cp0reg, sel;
824
825 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
826 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
827
828 /* CP0 register including 'sel' code for mtcN (et al.), to be
829 printed textually if known. If not known, print both
830 CP0 register name and sel numerically since CP0 register
831 with sel 0 may have a name unrelated to register being
832 printed. */
833 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
834 mips_cp0sel_names_len, cp0reg, sel);
835 if (n != NULL)
836 (*info->fprintf_func) (info->stream, "%s", n->name);
837 else
838 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
839 break;
840 }
841
842 case 'E':
843 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
844 (*info->fprintf_func) (info->stream, "0x%x", lsb);
845 break;
846
847 case 'F':
848 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
849 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
850 break;
851
852 case 'G':
853 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
854 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
855 break;
856
857 case 't': /* Coprocessor 0 reg name */
858 (*info->fprintf_func) (info->stream, "%s",
859 mips_cp0_names[(l >> OP_SH_RT) &
860 OP_MASK_RT]);
861 break;
862
863 case 'T': /* Coprocessor 0 reg name */
864 {
865 const struct mips_cp0sel_name *n;
866 unsigned int cp0reg, sel;
867
868 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
869 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
870
871 /* CP0 register including 'sel' code for mftc0, to be
872 printed textually if known. If not known, print both
873 CP0 register name and sel numerically since CP0 register
874 with sel 0 may have a name unrelated to register being
875 printed. */
876 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
877 mips_cp0sel_names_len, cp0reg, sel);
878 if (n != NULL)
879 (*info->fprintf_func) (info->stream, "%s", n->name);
880 else
881 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
882 break;
883 }
884
885 case 'x': /* bbit bit index */
886 (*info->fprintf_func) (info->stream, "0x%lx",
887 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
888 break;
889
890 case 'p': /* cins, cins32, exts and exts32 position */
891 (*info->fprintf_func) (info->stream, "0x%lx",
892 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
893 break;
894
895 case 's': /* cins and exts length-minus-one */
896 (*info->fprintf_func) (info->stream, "0x%lx",
897 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
898 break;
899
900 case 'S': /* cins32 and exts32 length-minus-one field */
901 (*info->fprintf_func) (info->stream, "0x%lx",
902 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
903 break;
904
905 default:
906 /* xgettext:c-format */
907 (*info->fprintf_func) (info->stream,
908 _("# internal error, undefined extension sequence (+%c)"),
909 *d);
910 return;
911 }
912 break;
913
914 case '2':
915 (*info->fprintf_func) (info->stream, "0x%lx",
916 (l >> OP_SH_BP) & OP_MASK_BP);
917 break;
918
919 case '3':
920 (*info->fprintf_func) (info->stream, "0x%lx",
921 (l >> OP_SH_SA3) & OP_MASK_SA3);
922 break;
923
924 case '4':
925 (*info->fprintf_func) (info->stream, "0x%lx",
926 (l >> OP_SH_SA4) & OP_MASK_SA4);
927 break;
928
929 case '5':
930 (*info->fprintf_func) (info->stream, "0x%lx",
931 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
932 break;
933
934 case '6':
935 (*info->fprintf_func) (info->stream, "0x%lx",
936 (l >> OP_SH_RS) & OP_MASK_RS);
937 break;
938
939 case '7':
940 (*info->fprintf_func) (info->stream, "$ac%ld",
941 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
942 break;
943
944 case '8':
945 (*info->fprintf_func) (info->stream, "0x%lx",
946 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
947 break;
948
949 case '9':
950 (*info->fprintf_func) (info->stream, "$ac%ld",
951 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
952 break;
953
954 case '0': /* dsp 6-bit signed immediate in bit 20 */
955 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
956 if (delta & 0x20) /* test sign bit */
957 delta |= ~OP_MASK_DSPSFT;
958 (*info->fprintf_func) (info->stream, "%d", delta);
959 break;
960
961 case ':': /* dsp 7-bit signed immediate in bit 19 */
962 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
963 if (delta & 0x40) /* test sign bit */
964 delta |= ~OP_MASK_DSPSFT_7;
965 (*info->fprintf_func) (info->stream, "%d", delta);
966 break;
967
968 case '\'':
969 (*info->fprintf_func) (info->stream, "0x%lx",
970 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
971 break;
972
973 case '@': /* dsp 10-bit signed immediate in bit 16 */
974 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
975 if (delta & 0x200) /* test sign bit */
976 delta |= ~OP_MASK_IMM10;
977 (*info->fprintf_func) (info->stream, "%d", delta);
978 break;
979
980 case '!':
981 (*info->fprintf_func) (info->stream, "%ld",
982 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
983 break;
984
985 case '$':
986 (*info->fprintf_func) (info->stream, "%ld",
987 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
988 break;
989
990 case '*':
991 (*info->fprintf_func) (info->stream, "$ac%ld",
992 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
993 break;
994
995 case '&':
996 (*info->fprintf_func) (info->stream, "$ac%ld",
997 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
998 break;
999
1000 case 'g':
1001 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1002 (*info->fprintf_func) (info->stream, "$%ld",
1003 (l >> OP_SH_RD) & OP_MASK_RD);
1004 break;
1005
1006 case 's':
1007 case 'b':
1008 case 'r':
1009 case 'v':
1010 (*info->fprintf_func) (info->stream, "%s",
1011 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1012 break;
1013
1014 case 't':
1015 case 'w':
1016 (*info->fprintf_func) (info->stream, "%s",
1017 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1018 break;
1019
1020 case 'i':
1021 case 'u':
1022 (*info->fprintf_func) (info->stream, "0x%lx",
1023 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1024 break;
1025
1026 case 'j': /* Same as i, but sign-extended. */
1027 case 'o':
1028 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1029 if (delta & 0x8000)
1030 delta |= ~0xffff;
1031 (*info->fprintf_func) (info->stream, "%d",
1032 delta);
1033 break;
1034
1035 case 'h':
1036 (*info->fprintf_func) (info->stream, "0x%x",
1037 (unsigned int) ((l >> OP_SH_PREFX)
1038 & OP_MASK_PREFX));
1039 break;
1040
1041 case 'k':
1042 (*info->fprintf_func) (info->stream, "0x%x",
1043 (unsigned int) ((l >> OP_SH_CACHE)
1044 & OP_MASK_CACHE));
1045 break;
1046
1047 case 'a':
1048 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1049 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1050 /* For gdb disassembler, force odd address on jalx. */
1051 if (info->flavour == bfd_target_unknown_flavour
1052 && strcmp (opp->name, "jalx") == 0)
1053 info->target |= 1;
1054 (*info->print_address_func) (info->target, info);
1055 break;
1056
1057 case 'p':
1058 /* Sign extend the displacement. */
1059 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1060 if (delta & 0x8000)
1061 delta |= ~0xffff;
1062 info->target = (delta << 2) + pc + INSNLEN;
1063 (*info->print_address_func) (info->target, info);
1064 break;
1065
1066 case 'd':
1067 (*info->fprintf_func) (info->stream, "%s",
1068 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1069 break;
1070
1071 case 'U':
1072 {
1073 /* First check for both rd and rt being equal. */
1074 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1075 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1076 (*info->fprintf_func) (info->stream, "%s",
1077 mips_gpr_names[reg]);
1078 else
1079 {
1080 /* If one is zero use the other. */
1081 if (reg == 0)
1082 (*info->fprintf_func) (info->stream, "%s",
1083 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1084 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1085 (*info->fprintf_func) (info->stream, "%s",
1086 mips_gpr_names[reg]);
1087 else /* Bogus, result depends on processor. */
1088 (*info->fprintf_func) (info->stream, "%s or %s",
1089 mips_gpr_names[reg],
1090 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1091 }
1092 }
1093 break;
1094
1095 case 'z':
1096 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1097 break;
1098
1099 case '<':
1100 (*info->fprintf_func) (info->stream, "0x%lx",
1101 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1102 break;
1103
1104 case 'c':
1105 (*info->fprintf_func) (info->stream, "0x%lx",
1106 (l >> OP_SH_CODE) & OP_MASK_CODE);
1107 break;
1108
1109 case 'q':
1110 (*info->fprintf_func) (info->stream, "0x%lx",
1111 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1112 break;
1113
1114 case 'C':
1115 (*info->fprintf_func) (info->stream, "0x%lx",
1116 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1117 break;
1118
1119 case 'B':
1120 (*info->fprintf_func) (info->stream, "0x%lx",
1121
1122 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1123 break;
1124
1125 case 'J':
1126 (*info->fprintf_func) (info->stream, "0x%lx",
1127 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1128 break;
1129
1130 case 'S':
1131 case 'V':
1132 (*info->fprintf_func) (info->stream, "%s",
1133 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1134 break;
1135
1136 case 'T':
1137 case 'W':
1138 (*info->fprintf_func) (info->stream, "%s",
1139 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1140 break;
1141
1142 case 'D':
1143 (*info->fprintf_func) (info->stream, "%s",
1144 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1145 break;
1146
1147 case 'R':
1148 (*info->fprintf_func) (info->stream, "%s",
1149 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1150 break;
1151
1152 case 'E':
1153 /* Coprocessor register for lwcN instructions, et al.
1154
1155 Note that there is no load/store cp0 instructions, and
1156 that FPU (cp1) instructions disassemble this field using
1157 'T' format. Therefore, until we gain understanding of
1158 cp2 register names, we can simply print the register
1159 numbers. */
1160 (*info->fprintf_func) (info->stream, "$%ld",
1161 (l >> OP_SH_RT) & OP_MASK_RT);
1162 break;
1163
1164 case 'G':
1165 /* Coprocessor register for mtcN instructions, et al. Note
1166 that FPU (cp1) instructions disassemble this field using
1167 'S' format. Therefore, we only need to worry about cp0,
1168 cp2, and cp3. */
1169 op = (l >> OP_SH_OP) & OP_MASK_OP;
1170 if (op == OP_OP_COP0)
1171 (*info->fprintf_func) (info->stream, "%s",
1172 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1173 else
1174 (*info->fprintf_func) (info->stream, "$%ld",
1175 (l >> OP_SH_RD) & OP_MASK_RD);
1176 break;
1177
1178 case 'K':
1179 (*info->fprintf_func) (info->stream, "%s",
1180 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1181 break;
1182
1183 case 'N':
1184 (*info->fprintf_func) (info->stream,
1185 ((opp->pinfo & (FP_D | FP_S)) != 0
1186 ? "$fcc%ld" : "$cc%ld"),
1187 (l >> OP_SH_BCC) & OP_MASK_BCC);
1188 break;
1189
1190 case 'M':
1191 (*info->fprintf_func) (info->stream, "$fcc%ld",
1192 (l >> OP_SH_CCC) & OP_MASK_CCC);
1193 break;
1194
1195 case 'P':
1196 (*info->fprintf_func) (info->stream, "%ld",
1197 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1198 break;
1199
1200 case 'e':
1201 (*info->fprintf_func) (info->stream, "%ld",
1202 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1203 break;
1204
1205 case '%':
1206 (*info->fprintf_func) (info->stream, "%ld",
1207 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1208 break;
1209
1210 case 'H':
1211 (*info->fprintf_func) (info->stream, "%ld",
1212 (l >> OP_SH_SEL) & OP_MASK_SEL);
1213 break;
1214
1215 case 'O':
1216 (*info->fprintf_func) (info->stream, "%ld",
1217 (l >> OP_SH_ALN) & OP_MASK_ALN);
1218 break;
1219
1220 case 'Q':
1221 {
1222 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1223
1224 if ((vsel & 0x10) == 0)
1225 {
1226 int fmt;
1227
1228 vsel &= 0x0f;
1229 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1230 if ((vsel & 1) == 0)
1231 break;
1232 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1233 (l >> OP_SH_FT) & OP_MASK_FT,
1234 vsel >> 1);
1235 }
1236 else if ((vsel & 0x08) == 0)
1237 {
1238 (*info->fprintf_func) (info->stream, "$v%ld",
1239 (l >> OP_SH_FT) & OP_MASK_FT);
1240 }
1241 else
1242 {
1243 (*info->fprintf_func) (info->stream, "0x%lx",
1244 (l >> OP_SH_FT) & OP_MASK_FT);
1245 }
1246 }
1247 break;
1248
1249 case 'X':
1250 (*info->fprintf_func) (info->stream, "$v%ld",
1251 (l >> OP_SH_FD) & OP_MASK_FD);
1252 break;
1253
1254 case 'Y':
1255 (*info->fprintf_func) (info->stream, "$v%ld",
1256 (l >> OP_SH_FS) & OP_MASK_FS);
1257 break;
1258
1259 case 'Z':
1260 (*info->fprintf_func) (info->stream, "$v%ld",
1261 (l >> OP_SH_FT) & OP_MASK_FT);
1262 break;
1263
1264 default:
1265 /* xgettext:c-format */
1266 (*info->fprintf_func) (info->stream,
1267 _("# internal error, undefined modifier (%c)"),
1268 *d);
1269 return;
1270 }
1271 }
1272 }
1273 \f
1274 /* Print the mips instruction at address MEMADDR in debugged memory,
1275 on using INFO. Returns length of the instruction, in bytes, which is
1276 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1277 this is little-endian code. */
1278
1279 static int
1280 print_insn_mips (bfd_vma memaddr,
1281 unsigned long int word,
1282 struct disassemble_info *info)
1283 {
1284 const struct mips_opcode *op;
1285 static bfd_boolean init = 0;
1286 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1287
1288 /* Build a hash table to shorten the search time. */
1289 if (! init)
1290 {
1291 unsigned int i;
1292
1293 for (i = 0; i <= OP_MASK_OP; i++)
1294 {
1295 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1296 {
1297 if (op->pinfo == INSN_MACRO
1298 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1299 continue;
1300 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1301 {
1302 mips_hash[i] = op;
1303 break;
1304 }
1305 }
1306 }
1307
1308 init = 1;
1309 }
1310
1311 info->bytes_per_chunk = INSNLEN;
1312 info->display_endian = info->endian;
1313 info->insn_info_valid = 1;
1314 info->branch_delay_insns = 0;
1315 info->data_size = 0;
1316 info->insn_type = dis_nonbranch;
1317 info->target = 0;
1318 info->target2 = 0;
1319
1320 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1321 if (op != NULL)
1322 {
1323 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1324 {
1325 if (op->pinfo != INSN_MACRO
1326 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1327 && (word & op->mask) == op->match)
1328 {
1329 const char *d;
1330
1331 /* We always allow to disassemble the jalx instruction. */
1332 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1333 && strcmp (op->name, "jalx"))
1334 continue;
1335
1336 /* Figure out instruction type and branch delay information. */
1337 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1338 {
1339 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1340 info->insn_type = dis_jsr;
1341 else
1342 info->insn_type = dis_branch;
1343 info->branch_delay_insns = 1;
1344 }
1345 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1346 | INSN_COND_BRANCH_LIKELY)) != 0)
1347 {
1348 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1349 info->insn_type = dis_condjsr;
1350 else
1351 info->insn_type = dis_condbranch;
1352 info->branch_delay_insns = 1;
1353 }
1354 else if ((op->pinfo & (INSN_STORE_MEMORY
1355 | INSN_LOAD_MEMORY_DELAY)) != 0)
1356 info->insn_type = dis_dref;
1357
1358 (*info->fprintf_func) (info->stream, "%s", op->name);
1359
1360 d = op->args;
1361 if (d != NULL && *d != '\0')
1362 {
1363 (*info->fprintf_func) (info->stream, "\t");
1364 print_insn_args (d, word, memaddr, info, op);
1365 }
1366
1367 return INSNLEN;
1368 }
1369 }
1370 }
1371
1372 /* Handle undefined instructions. */
1373 info->insn_type = dis_noninsn;
1374 (*info->fprintf_func) (info->stream, "0x%lx", word);
1375 return INSNLEN;
1376 }
1377 \f
1378 /* Disassemble an operand for a mips16 instruction. */
1379
1380 static void
1381 print_mips16_insn_arg (char type,
1382 const struct mips_opcode *op,
1383 int l,
1384 bfd_boolean use_extend,
1385 int extend,
1386 bfd_vma memaddr,
1387 struct disassemble_info *info)
1388 {
1389 switch (type)
1390 {
1391 case ',':
1392 case '(':
1393 case ')':
1394 (*info->fprintf_func) (info->stream, "%c", type);
1395 break;
1396
1397 case 'y':
1398 case 'w':
1399 (*info->fprintf_func) (info->stream, "%s",
1400 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1401 & MIPS16OP_MASK_RY)));
1402 break;
1403
1404 case 'x':
1405 case 'v':
1406 (*info->fprintf_func) (info->stream, "%s",
1407 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1408 & MIPS16OP_MASK_RX)));
1409 break;
1410
1411 case 'z':
1412 (*info->fprintf_func) (info->stream, "%s",
1413 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1414 & MIPS16OP_MASK_RZ)));
1415 break;
1416
1417 case 'Z':
1418 (*info->fprintf_func) (info->stream, "%s",
1419 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1420 & MIPS16OP_MASK_MOVE32Z)));
1421 break;
1422
1423 case '0':
1424 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1425 break;
1426
1427 case 'S':
1428 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1429 break;
1430
1431 case 'P':
1432 (*info->fprintf_func) (info->stream, "$pc");
1433 break;
1434
1435 case 'R':
1436 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1437 break;
1438
1439 case 'X':
1440 (*info->fprintf_func) (info->stream, "%s",
1441 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1442 & MIPS16OP_MASK_REGR32)]);
1443 break;
1444
1445 case 'Y':
1446 (*info->fprintf_func) (info->stream, "%s",
1447 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1448 break;
1449
1450 case '<':
1451 case '>':
1452 case '[':
1453 case ']':
1454 case '4':
1455 case '5':
1456 case 'H':
1457 case 'W':
1458 case 'D':
1459 case 'j':
1460 case '6':
1461 case '8':
1462 case 'V':
1463 case 'C':
1464 case 'U':
1465 case 'k':
1466 case 'K':
1467 case 'p':
1468 case 'q':
1469 case 'A':
1470 case 'B':
1471 case 'E':
1472 {
1473 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1474
1475 shift = 0;
1476 signedp = 0;
1477 extbits = 16;
1478 pcrel = 0;
1479 extu = 0;
1480 branch = 0;
1481 switch (type)
1482 {
1483 case '<':
1484 nbits = 3;
1485 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1486 extbits = 5;
1487 extu = 1;
1488 break;
1489 case '>':
1490 nbits = 3;
1491 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1492 extbits = 5;
1493 extu = 1;
1494 break;
1495 case '[':
1496 nbits = 3;
1497 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1498 extbits = 6;
1499 extu = 1;
1500 break;
1501 case ']':
1502 nbits = 3;
1503 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1504 extbits = 6;
1505 extu = 1;
1506 break;
1507 case '4':
1508 nbits = 4;
1509 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1510 signedp = 1;
1511 extbits = 15;
1512 break;
1513 case '5':
1514 nbits = 5;
1515 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1516 info->insn_type = dis_dref;
1517 info->data_size = 1;
1518 break;
1519 case 'H':
1520 nbits = 5;
1521 shift = 1;
1522 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1523 info->insn_type = dis_dref;
1524 info->data_size = 2;
1525 break;
1526 case 'W':
1527 nbits = 5;
1528 shift = 2;
1529 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1530 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1531 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1532 {
1533 info->insn_type = dis_dref;
1534 info->data_size = 4;
1535 }
1536 break;
1537 case 'D':
1538 nbits = 5;
1539 shift = 3;
1540 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1541 info->insn_type = dis_dref;
1542 info->data_size = 8;
1543 break;
1544 case 'j':
1545 nbits = 5;
1546 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1547 signedp = 1;
1548 break;
1549 case '6':
1550 nbits = 6;
1551 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1552 break;
1553 case '8':
1554 nbits = 8;
1555 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1556 break;
1557 case 'V':
1558 nbits = 8;
1559 shift = 2;
1560 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1561 /* FIXME: This might be lw, or it might be addiu to $sp or
1562 $pc. We assume it's load. */
1563 info->insn_type = dis_dref;
1564 info->data_size = 4;
1565 break;
1566 case 'C':
1567 nbits = 8;
1568 shift = 3;
1569 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1570 info->insn_type = dis_dref;
1571 info->data_size = 8;
1572 break;
1573 case 'U':
1574 nbits = 8;
1575 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1576 extu = 1;
1577 break;
1578 case 'k':
1579 nbits = 8;
1580 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1581 signedp = 1;
1582 break;
1583 case 'K':
1584 nbits = 8;
1585 shift = 3;
1586 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1587 signedp = 1;
1588 break;
1589 case 'p':
1590 nbits = 8;
1591 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1592 signedp = 1;
1593 pcrel = 1;
1594 branch = 1;
1595 info->insn_type = dis_condbranch;
1596 break;
1597 case 'q':
1598 nbits = 11;
1599 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1600 signedp = 1;
1601 pcrel = 1;
1602 branch = 1;
1603 info->insn_type = dis_branch;
1604 break;
1605 case 'A':
1606 nbits = 8;
1607 shift = 2;
1608 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1609 pcrel = 1;
1610 /* FIXME: This can be lw or la. We assume it is lw. */
1611 info->insn_type = dis_dref;
1612 info->data_size = 4;
1613 break;
1614 case 'B':
1615 nbits = 5;
1616 shift = 3;
1617 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1618 pcrel = 1;
1619 info->insn_type = dis_dref;
1620 info->data_size = 8;
1621 break;
1622 case 'E':
1623 nbits = 5;
1624 shift = 2;
1625 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1626 pcrel = 1;
1627 break;
1628 default:
1629 abort ();
1630 }
1631
1632 if (! use_extend)
1633 {
1634 if (signedp && immed >= (1 << (nbits - 1)))
1635 immed -= 1 << nbits;
1636 immed <<= shift;
1637 if ((type == '<' || type == '>' || type == '[' || type == ']')
1638 && immed == 0)
1639 immed = 8;
1640 }
1641 else
1642 {
1643 if (extbits == 16)
1644 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1645 else if (extbits == 15)
1646 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1647 else
1648 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1649 immed &= (1 << extbits) - 1;
1650 if (! extu && immed >= (1 << (extbits - 1)))
1651 immed -= 1 << extbits;
1652 }
1653
1654 if (! pcrel)
1655 (*info->fprintf_func) (info->stream, "%d", immed);
1656 else
1657 {
1658 bfd_vma baseaddr;
1659
1660 if (branch)
1661 {
1662 immed *= 2;
1663 baseaddr = memaddr + 2;
1664 }
1665 else if (use_extend)
1666 baseaddr = memaddr - 2;
1667 else
1668 {
1669 int status;
1670 bfd_byte buffer[2];
1671
1672 baseaddr = memaddr;
1673
1674 /* If this instruction is in the delay slot of a jr
1675 instruction, the base address is the address of the
1676 jr instruction. If it is in the delay slot of jalr
1677 instruction, the base address is the address of the
1678 jalr instruction. This test is unreliable: we have
1679 no way of knowing whether the previous word is
1680 instruction or data. */
1681 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1682 info);
1683 if (status == 0
1684 && (((info->endian == BFD_ENDIAN_BIG
1685 ? bfd_getb16 (buffer)
1686 : bfd_getl16 (buffer))
1687 & 0xf800) == 0x1800))
1688 baseaddr = memaddr - 4;
1689 else
1690 {
1691 status = (*info->read_memory_func) (memaddr - 2, buffer,
1692 2, info);
1693 if (status == 0
1694 && (((info->endian == BFD_ENDIAN_BIG
1695 ? bfd_getb16 (buffer)
1696 : bfd_getl16 (buffer))
1697 & 0xf81f) == 0xe800))
1698 baseaddr = memaddr - 2;
1699 }
1700 }
1701 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1702 if (pcrel && branch
1703 && info->flavour == bfd_target_unknown_flavour)
1704 /* For gdb disassembler, maintain odd address. */
1705 info->target |= 1;
1706 (*info->print_address_func) (info->target, info);
1707 }
1708 }
1709 break;
1710
1711 case 'a':
1712 {
1713 int jalx = l & 0x400;
1714
1715 if (! use_extend)
1716 extend = 0;
1717 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1718 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1719 /* For gdb disassembler, maintain odd address. */
1720 l |= 1;
1721 }
1722 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1723 (*info->print_address_func) (info->target, info);
1724 info->insn_type = dis_jsr;
1725 info->branch_delay_insns = 1;
1726 break;
1727
1728 case 'l':
1729 case 'L':
1730 {
1731 int need_comma, amask, smask;
1732
1733 need_comma = 0;
1734
1735 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1736
1737 amask = (l >> 3) & 7;
1738
1739 if (amask > 0 && amask < 5)
1740 {
1741 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1742 if (amask > 1)
1743 (*info->fprintf_func) (info->stream, "-%s",
1744 mips_gpr_names[amask + 3]);
1745 need_comma = 1;
1746 }
1747
1748 smask = (l >> 1) & 3;
1749 if (smask == 3)
1750 {
1751 (*info->fprintf_func) (info->stream, "%s??",
1752 need_comma ? "," : "");
1753 need_comma = 1;
1754 }
1755 else if (smask > 0)
1756 {
1757 (*info->fprintf_func) (info->stream, "%s%s",
1758 need_comma ? "," : "",
1759 mips_gpr_names[16]);
1760 if (smask > 1)
1761 (*info->fprintf_func) (info->stream, "-%s",
1762 mips_gpr_names[smask + 15]);
1763 need_comma = 1;
1764 }
1765
1766 if (l & 1)
1767 {
1768 (*info->fprintf_func) (info->stream, "%s%s",
1769 need_comma ? "," : "",
1770 mips_gpr_names[31]);
1771 need_comma = 1;
1772 }
1773
1774 if (amask == 5 || amask == 6)
1775 {
1776 (*info->fprintf_func) (info->stream, "%s$f0",
1777 need_comma ? "," : "");
1778 if (amask == 6)
1779 (*info->fprintf_func) (info->stream, "-$f1");
1780 }
1781 }
1782 break;
1783
1784 case 'm':
1785 case 'M':
1786 /* MIPS16e save/restore. */
1787 {
1788 int need_comma = 0;
1789 int amask, args, statics;
1790 int nsreg, smask;
1791 int framesz;
1792 int i, j;
1793
1794 l = l & 0x7f;
1795 if (use_extend)
1796 l |= extend << 16;
1797
1798 amask = (l >> 16) & 0xf;
1799 if (amask == MIPS16_ALL_ARGS)
1800 {
1801 args = 4;
1802 statics = 0;
1803 }
1804 else if (amask == MIPS16_ALL_STATICS)
1805 {
1806 args = 0;
1807 statics = 4;
1808 }
1809 else
1810 {
1811 args = amask >> 2;
1812 statics = amask & 3;
1813 }
1814
1815 if (args > 0) {
1816 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1817 if (args > 1)
1818 (*info->fprintf_func) (info->stream, "-%s",
1819 mips_gpr_names[4 + args - 1]);
1820 need_comma = 1;
1821 }
1822
1823 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1824 if (framesz == 0 && !use_extend)
1825 framesz = 128;
1826
1827 (*info->fprintf_func) (info->stream, "%s%d",
1828 need_comma ? "," : "",
1829 framesz);
1830
1831 if (l & 0x40) /* $ra */
1832 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1833
1834 nsreg = (l >> 24) & 0x7;
1835 smask = 0;
1836 if (l & 0x20) /* $s0 */
1837 smask |= 1 << 0;
1838 if (l & 0x10) /* $s1 */
1839 smask |= 1 << 1;
1840 if (nsreg > 0) /* $s2-$s8 */
1841 smask |= ((1 << nsreg) - 1) << 2;
1842
1843 /* Find first set static reg bit. */
1844 for (i = 0; i < 9; i++)
1845 {
1846 if (smask & (1 << i))
1847 {
1848 (*info->fprintf_func) (info->stream, ",%s",
1849 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1850 /* Skip over string of set bits. */
1851 for (j = i; smask & (2 << j); j++)
1852 continue;
1853 if (j > i)
1854 (*info->fprintf_func) (info->stream, "-%s",
1855 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1856 i = j + 1;
1857 }
1858 }
1859
1860 /* Statics $ax - $a3. */
1861 if (statics == 1)
1862 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1863 else if (statics > 0)
1864 (*info->fprintf_func) (info->stream, ",%s-%s",
1865 mips_gpr_names[7 - statics + 1],
1866 mips_gpr_names[7]);
1867 }
1868 break;
1869
1870 default:
1871 /* xgettext:c-format */
1872 (*info->fprintf_func)
1873 (info->stream,
1874 _("# internal disassembler error, unrecognised modifier (%c)"),
1875 type);
1876 abort ();
1877 }
1878 }
1879
1880 /* Disassemble mips16 instructions. */
1881
1882 static int
1883 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1884 {
1885 int status;
1886 bfd_byte buffer[2];
1887 int length;
1888 int insn;
1889 bfd_boolean use_extend;
1890 int extend = 0;
1891 const struct mips_opcode *op, *opend;
1892
1893 info->bytes_per_chunk = 2;
1894 info->display_endian = info->endian;
1895 info->insn_info_valid = 1;
1896 info->branch_delay_insns = 0;
1897 info->data_size = 0;
1898 info->insn_type = dis_nonbranch;
1899 info->target = 0;
1900 info->target2 = 0;
1901
1902 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1903 if (status != 0)
1904 {
1905 (*info->memory_error_func) (status, memaddr, info);
1906 return -1;
1907 }
1908
1909 length = 2;
1910
1911 if (info->endian == BFD_ENDIAN_BIG)
1912 insn = bfd_getb16 (buffer);
1913 else
1914 insn = bfd_getl16 (buffer);
1915
1916 /* Handle the extend opcode specially. */
1917 use_extend = FALSE;
1918 if ((insn & 0xf800) == 0xf000)
1919 {
1920 use_extend = TRUE;
1921 extend = insn & 0x7ff;
1922
1923 memaddr += 2;
1924
1925 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1926 if (status != 0)
1927 {
1928 (*info->fprintf_func) (info->stream, "extend 0x%x",
1929 (unsigned int) extend);
1930 (*info->memory_error_func) (status, memaddr, info);
1931 return -1;
1932 }
1933
1934 if (info->endian == BFD_ENDIAN_BIG)
1935 insn = bfd_getb16 (buffer);
1936 else
1937 insn = bfd_getl16 (buffer);
1938
1939 /* Check for an extend opcode followed by an extend opcode. */
1940 if ((insn & 0xf800) == 0xf000)
1941 {
1942 (*info->fprintf_func) (info->stream, "extend 0x%x",
1943 (unsigned int) extend);
1944 info->insn_type = dis_noninsn;
1945 return length;
1946 }
1947
1948 length += 2;
1949 }
1950
1951 /* FIXME: Should probably use a hash table on the major opcode here. */
1952
1953 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1954 for (op = mips16_opcodes; op < opend; op++)
1955 {
1956 if (op->pinfo != INSN_MACRO
1957 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1958 && (insn & op->mask) == op->match)
1959 {
1960 const char *s;
1961
1962 if (strchr (op->args, 'a') != NULL)
1963 {
1964 if (use_extend)
1965 {
1966 (*info->fprintf_func) (info->stream, "extend 0x%x",
1967 (unsigned int) extend);
1968 info->insn_type = dis_noninsn;
1969 return length - 2;
1970 }
1971
1972 use_extend = FALSE;
1973
1974 memaddr += 2;
1975
1976 status = (*info->read_memory_func) (memaddr, buffer, 2,
1977 info);
1978 if (status == 0)
1979 {
1980 use_extend = TRUE;
1981 if (info->endian == BFD_ENDIAN_BIG)
1982 extend = bfd_getb16 (buffer);
1983 else
1984 extend = bfd_getl16 (buffer);
1985 length += 2;
1986 }
1987 }
1988
1989 (*info->fprintf_func) (info->stream, "%s", op->name);
1990 if (op->args[0] != '\0')
1991 (*info->fprintf_func) (info->stream, "\t");
1992
1993 for (s = op->args; *s != '\0'; s++)
1994 {
1995 if (*s == ','
1996 && s[1] == 'w'
1997 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1998 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1999 {
2000 /* Skip the register and the comma. */
2001 ++s;
2002 continue;
2003 }
2004 if (*s == ','
2005 && s[1] == 'v'
2006 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2007 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2008 {
2009 /* Skip the register and the comma. */
2010 ++s;
2011 continue;
2012 }
2013 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2014 info);
2015 }
2016
2017 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2018 {
2019 info->branch_delay_insns = 1;
2020 if (info->insn_type != dis_jsr)
2021 info->insn_type = dis_branch;
2022 }
2023
2024 return length;
2025 }
2026 }
2027
2028 if (use_extend)
2029 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2030 (*info->fprintf_func) (info->stream, "0x%x", insn);
2031 info->insn_type = dis_noninsn;
2032
2033 return length;
2034 }
2035
2036 /* In an environment where we do not know the symbol type of the
2037 instruction we are forced to assume that the low order bit of the
2038 instructions' address may mark it as a mips16 instruction. If we
2039 are single stepping, or the pc is within the disassembled function,
2040 this works. Otherwise, we need a clue. Sometimes. */
2041
2042 static int
2043 _print_insn_mips (bfd_vma memaddr,
2044 struct disassemble_info *info,
2045 enum bfd_endian endianness)
2046 {
2047 bfd_byte buffer[INSNLEN];
2048 int status;
2049
2050 set_default_mips_dis_options (info);
2051 parse_mips_dis_options (info->disassembler_options);
2052
2053 #if 1
2054 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2055 /* Only a few tools will work this way. */
2056 if (memaddr & 0x01)
2057 return print_insn_mips16 (memaddr, info);
2058 #endif
2059
2060 #if SYMTAB_AVAILABLE
2061 if (info->mach == bfd_mach_mips16
2062 || (info->flavour == bfd_target_elf_flavour
2063 && info->symbols != NULL
2064 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
2065 == STO_MIPS16)))
2066 return print_insn_mips16 (memaddr, info);
2067 #endif
2068
2069 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2070 if (status == 0)
2071 {
2072 unsigned long insn;
2073
2074 if (endianness == BFD_ENDIAN_BIG)
2075 insn = (unsigned long) bfd_getb32 (buffer);
2076 else
2077 insn = (unsigned long) bfd_getl32 (buffer);
2078
2079 return print_insn_mips (memaddr, insn, info);
2080 }
2081 else
2082 {
2083 (*info->memory_error_func) (status, memaddr, info);
2084 return -1;
2085 }
2086 }
2087
2088 int
2089 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2090 {
2091 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2092 }
2093
2094 int
2095 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2096 {
2097 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2098 }
2099 \f
2100 void
2101 print_mips_disassembler_options (FILE *stream)
2102 {
2103 unsigned int i;
2104
2105 fprintf (stream, _("\n\
2106 The following MIPS specific disassembler options are supported for use\n\
2107 with the -M switch (multiple options should be separated by commas):\n"));
2108
2109 fprintf (stream, _("\n\
2110 gpr-names=ABI Print GPR names according to specified ABI.\n\
2111 Default: based on binary being disassembled.\n"));
2112
2113 fprintf (stream, _("\n\
2114 fpr-names=ABI Print FPR names according to specified ABI.\n\
2115 Default: numeric.\n"));
2116
2117 fprintf (stream, _("\n\
2118 cp0-names=ARCH Print CP0 register names according to\n\
2119 specified architecture.\n\
2120 Default: based on binary being disassembled.\n"));
2121
2122 fprintf (stream, _("\n\
2123 hwr-names=ARCH Print HWR names according to specified \n\
2124 architecture.\n\
2125 Default: based on binary being disassembled.\n"));
2126
2127 fprintf (stream, _("\n\
2128 reg-names=ABI Print GPR and FPR names according to\n\
2129 specified ABI.\n"));
2130
2131 fprintf (stream, _("\n\
2132 reg-names=ARCH Print CP0 register and HWR names according to\n\
2133 specified architecture.\n"));
2134
2135 fprintf (stream, _("\n\
2136 For the options above, the following values are supported for \"ABI\":\n\
2137 "));
2138 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2139 fprintf (stream, " %s", mips_abi_choices[i].name);
2140 fprintf (stream, _("\n"));
2141
2142 fprintf (stream, _("\n\
2143 For the options above, The following values are supported for \"ARCH\":\n\
2144 "));
2145 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2146 if (*mips_arch_choices[i].name != '\0')
2147 fprintf (stream, " %s", mips_arch_choices[i].name);
2148 fprintf (stream, _("\n"));
2149
2150 fprintf (stream, _("\n"));
2151 }
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