opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2024 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #include <limits.h>
  23 #ifndef CHAR_BIT
  24 #define CHAR_BIT 8
  25 #endif
  26
  27 /* Position of cpu flags bitfiled.  */
  28
  29 enum i386_cpu
  30 {
  31   /* i186 or better required */
  32   Cpu186 = 0,
  33   /* i286 or better required */
  34   Cpu286,
  35   /* i386 or better required */
  36   Cpu386,
  37   /* i486 or better required */
  38   Cpu486,
  39   /* i585 or better required */
  40   Cpu586,
  41   /* i686 or better required */
  42   Cpu686,
  43   /* CMOV Instruction support required */
  44   CpuCMOV,
  45   /* FXSR Instruction support required */
  46   CpuFXSR,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i686 and floating point support required */
  56   Cpu687,
  57   /* SSE3 and floating point support required */
  58   CpuFISTTP,
  59   /* MMX support required */
  60   CpuMMX,
  61   /* SSE support required */
  62   CpuSSE,
  63   /* SSE2 support required */
  64   CpuSSE2,
  65   /* SSE3 support required */
  66   CpuSSE3,
  67   /* VIA PadLock required */
  68   CpuPadLock,
  69   /* AMD Secure Virtual Machine Ext-s required */
  70   CpuSVME,
  71   /* VMX Instructions required */
  72   CpuVMX,
  73   /* SMX Instructions required */
  74   CpuSMX,
  75   /* SSSE3 support required */
  76   CpuSSSE3,
  77   /* SSE4a support required */
  78   CpuSSE4a,
  79   /* LZCNT support required */
  80   CpuLZCNT,
  81   /* POPCNT support required */
  82   CpuPOPCNT,
  83   /* MONITOR support required */
  84   CpuMONITOR,
  85   /* SSE4.1 support required */
  86   CpuSSE4_1,
  87   /* SSE4.2 support required */
  88   CpuSSE4_2,
  89   /* AVX2 support required */
  90   CpuAVX2,
  91   /* Intel AVX-512 Conflict Detection Instructions support required */
  92   CpuAVX512CD,
  93   /* Intel AVX-512 Exponential and Reciprocal Instructions support
  94      required */
  95   CpuAVX512ER,
  96   /* Intel AVX-512 Prefetch Instructions support required */
  97   CpuAVX512PF,
  98   /* Intel AVX-512 DQ Instructions support required.  */
  99   CpuAVX512DQ,
 100   /* Intel AVX-512 BW Instructions support required.  */
 101   CpuAVX512BW,
 102   /* Intel IAMCU support required */
 103   CpuIAMCU,
 104   /* Xsave/xrstor New Instructions support required */
 105   CpuXsave,
 106   /* Xsaveopt New Instructions support required */
 107   CpuXsaveopt,
 108   /* AES support required */
 109   CpuAES,
 110   /* PCLMULQDQ support required */
 111   CpuPCLMULQDQ,
 112   /* FMA support required */
 113   CpuFMA,
 114   /* FMA4 support required */
 115   CpuFMA4,
 116   /* XOP support required */
 117   CpuXOP,
 118   /* LWP support required */
 119   CpuLWP,
 120   /* BMI support required */
 121   CpuBMI,
 122   /* TBM support required */
 123   CpuTBM,
 124   /* MOVBE Instruction support required */
 125   CpuMovbe,
 126   /* CMPXCHG16B instruction support required.  */
 127   CpuCX16,
 128   /* LAHF/SAHF instruction support required (in 64-bit mode).  */
 129   CpuLAHF_SAHF,
 130   /* EPT Instructions required */
 131   CpuEPT,
 132   /* RDTSCP Instruction support required */
 133   CpuRdtscp,
 134   /* FSGSBASE Instructions required */
 135   CpuFSGSBase,
 136   /* RDRND Instructions required */
 137   CpuRdRnd,
 138   /* F16C Instructions required */
 139   CpuF16C,
 140   /* Intel BMI2 support required */
 141   CpuBMI2,
 142   /* RTM support required */
 143   CpuRTM,
 144   /* INVPCID Instructions required */
 145   CpuINVPCID,
 146   /* VMFUNC Instruction required */
 147   CpuVMFUNC,
 148   /* Intel MPX Instructions required  */
 149   CpuMPX,
 150   /* RDRSEED instruction required.  */
 151   CpuRDSEED,
 152   /* Multi-presisionn add-carry instructions are required.  */
 153   CpuADX,
 154   /* Supports prefetchw and prefetch instructions.  */
 155   CpuPRFCHW,
 156   /* SMAP instructions required.  */
 157   CpuSMAP,
 158   /* SHA instructions required.  */
 159   CpuSHA,
 160   /* SHA512 instructions required.  */
 161   CpuSHA512,
 162   /* SM3 instructions required.  */
 163   CpuSM3,
 164   /* SM4 instructions required.  */
 165   CpuSM4,
 166   /* CLFLUSHOPT instruction required */
 167   CpuClflushOpt,
 168   /* XSAVES/XRSTORS instruction required */
 169   CpuXSAVES,
 170   /* XSAVEC instruction required */
 171   CpuXSAVEC,
 172   /* PREFETCHWT1 instruction required */
 173   CpuPREFETCHWT1,
 174   /* SE1 instruction required */
 175   CpuSE1,
 176   /* CLWB instruction required */
 177   CpuCLWB,
 178   /* Intel AVX-512 IFMA Instructions support required.  */
 179   CpuAVX512IFMA,
 180   /* Intel AVX-512 VBMI Instructions support required.  */
 181   CpuAVX512VBMI,
 182   /* Intel AVX-512 4FMAPS Instructions support required.  */
 183   CpuAVX512_4FMAPS,
 184   /* Intel AVX-512 4VNNIW Instructions support required.  */
 185   CpuAVX512_4VNNIW,
 186   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 187   CpuAVX512_VPOPCNTDQ,
 188   /* Intel AVX-512 VBMI2 Instructions support required.  */
 189   CpuAVX512_VBMI2,
 190   /* Intel AVX-512 VNNI Instructions support required.  */
 191   CpuAVX512_VNNI,
 192   /* Intel AVX-512 BITALG Instructions support required.  */
 193   CpuAVX512_BITALG,
 194   /* Intel AVX-512 BF16 Instructions support required.  */
 195   CpuAVX512_BF16,
 196   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 197   CpuAVX512_VP2INTERSECT,
 198   /* TDX Instructions support required.  */
 199   CpuTDX,
 200   /* Intel AVX VNNI Instructions support required.  */
 201   CpuAVX_VNNI,
 202   /* Intel AVX-512 FP16 Instructions support required.  */
 203   CpuAVX512_FP16,
 204   /* PREFETCHI instruction required */
 205   CpuPREFETCHI,
 206   /* Intel AVX IFMA Instructions support required.  */
 207   CpuAVX_IFMA,
 208   /* Intel AVX VNNI-INT8 Instructions support required.  */
 209   CpuAVX_VNNI_INT8,
 210   /* Intel AVX VNNI-INT16 Instructions support required.  */
 211   CpuAVX_VNNI_INT16,
 212   /* Intel CMPccXADD instructions support required.  */
 213   CpuCMPCCXADD,
 214   /* Intel WRMSRNS Instructions support required */
 215   CpuWRMSRNS,
 216   /* Intel MSRLIST Instructions support required.  */
 217   CpuMSRLIST,
 218   /* Intel AVX NE CONVERT Instructions support required.  */
 219   CpuAVX_NE_CONVERT,
 220   /* Intel RAO INT Instructions support required.  */
 221   CpuRAO_INT,
 222   /* fred instruction required */
 223   CpuFRED,
 224   /* lkgs instruction required */
 225   CpuLKGS,
 226   /* Intel USER_MSR Instruction support required.  */
 227   CpuUSER_MSR,
 228   /* mwaitx instruction required */
 229   CpuMWAITX,
 230   /* Clzero instruction required */
 231   CpuCLZERO,
 232   /* OSPKE instruction required */
 233   CpuOSPKE,
 234   /* RDPID instruction required */
 235   CpuRDPID,
 236   /* PTWRITE instruction required */
 237   CpuPTWRITE,
 238   /* CET instructions support required */
 239   CpuIBT,
 240   CpuSHSTK,
 241   /* AMX-INT8 instructions required */
 242   CpuAMX_INT8,
 243   /* AMX-BF16 instructions required */
 244   CpuAMX_BF16,
 245   /* AMX-FP16 instructions required */
 246   CpuAMX_FP16,
 247   /* AMX-COMPLEX instructions required.  */
 248   CpuAMX_COMPLEX,
 249   /* AMX-TILE instructions required */
 250   CpuAMX_TILE,
 251   /* GFNI instructions required */
 252   CpuGFNI,
 253   /* VAES instructions required */
 254   CpuVAES,
 255   /* VPCLMULQDQ instructions required */
 256   CpuVPCLMULQDQ,
 257   /* WBNOINVD instructions required */
 258   CpuWBNOINVD,
 259   /* PCONFIG instructions required */
 260   CpuPCONFIG,
 261   /* PBNDKB instructions required.  */
 262   CpuPBNDKB,
 263   /* WAITPKG instructions required */
 264   CpuWAITPKG,
 265   /* UINTR instructions required */
 266   CpuUINTR,
 267   /* CLDEMOTE instruction required */
 268   CpuCLDEMOTE,
 269   /* MOVDIRI instruction support required */
 270   CpuMOVDIRI,
 271   /* MOVDIRR64B instruction required */
 272   CpuMOVDIR64B,
 273   /* ENQCMD instruction required */
 274   CpuENQCMD,
 275   /* SERIALIZE instruction required */
 276   CpuSERIALIZE,
 277   /* RDPRU instruction required */
 278   CpuRDPRU,
 279   /* MCOMMIT instruction required */
 280   CpuMCOMMIT,
 281   /* SEV-ES instruction(s) required */
 282   CpuSEV_ES,
 283   /* TSXLDTRK instruction required */
 284   CpuTSXLDTRK,
 285   /* KL instruction support required */
 286   CpuKL,
 287   /* WideKL instruction support required */
 288   CpuWideKL,
 289   /* HRESET instruction required */
 290   CpuHRESET,
 291   /* INVLPGB instructions required */
 292   CpuINVLPGB,
 293   /* TLBSYNC instructions required */
 294   CpuTLBSYNC,
 295   /* SNP instructions required */
 296   CpuSNP,
 297   /* RMPQUERY instruction required */
 298   CpuRMPQUERY,
 299
 300   /* NOTE: These items, which can be combined with other ISA flags above, need
 301      to remain second to last and in sync with CPU_FLAGS_COMMON. */
 302
 303   /* i287 support required */
 304   Cpu287,
 305   CpuAttrEnums = Cpu287,
 306   /* i387 support required */
 307   Cpu387,
 308   /* 3dnow! support required */
 309   Cpu3dnow,
 310   /* 3dnow! Extensions support required */
 311   Cpu3dnowA,
 312   /* 64bit support required  */
 313   Cpu64,
 314   /* AVX support required */
 315   CpuAVX,
 316   /* HLE support required */
 317   CpuHLE,
 318   /* Intel AVX-512 Foundation Instructions support required */
 319   CpuAVX512F,
 320   /* Intel AVX-512 VL Instructions support required.  */
 321   CpuAVX512VL,
 322   /* Intel APX_F Instructions support required.  */
 323   CpuAPX_F,
 324   /* Not supported in the 64bit mode  */
 325   CpuNo64,
 326
 327   /* NOTE: This item needs to remain last. */
 328
 329   /* The last bitfield in i386_cpu_flags.  */
 330   CpuMax = CpuNo64
 331 };
 332
 333 #define CpuNumOfUints \
 334   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 335 #define CpuNumOfBits \
 336   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 337
 338 #define CpuIsaBits 8
 339 #define CpuAttrNumOfUints \
 340   ((CpuIsaBits + CpuMax - CpuAttrEnums) / sizeof (unsigned int) / CHAR_BIT + 1)
 341 #define CpuAttrNumOfBits \
 342   (CpuAttrNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 343
 344 /* If you get a compiler error for zero width of an unused field,
 345    comment the respective one out.  */
 346 #define CpuUnused       (CpuMax + 1)
 347 #define CpuAttrUnused   (CpuIsaBits + CpuMax + 1 - CpuAttrEnums)
 348
 349 #define CPU_FLAGS_COMMON \
 350       unsigned int cpu287:1, \
 351                    cpu387:1, \
 352                    cpu3dnow:1, \
 353                    cpu3dnowa:1, \
 354                    cpu64:1, \
 355                    cpuavx:1, \
 356                    cpuhle:1, \
 357                    cpuavx512f:1, \
 358                    cpuavx512vl:1, \
 359                    cpuapx_f:1, \
 360       /* NOTE: This field needs to remain last. */ \
 361                    cpuno64:1
 362
 363 typedef union i386_cpu_attr
 364 {
 365   struct
 366     {
 367       unsigned int isa:CpuIsaBits;
 368       CPU_FLAGS_COMMON;
 369 #ifdef CpuAttrUnused
 370       unsigned int unused:(CpuAttrNumOfBits - CpuAttrUnused);
 371 #endif
 372     } bitfield;
 373   unsigned int array[CpuAttrNumOfUints];
 374 } i386_cpu_attr;
 375
 376 /* We can check if an instruction is available with array instead
 377    of bitfield. */
 378 typedef union i386_cpu_flags
 379 {
 380   struct
 381     {
 382       unsigned int cpui186:1;
 383       unsigned int cpui286:1;
 384       unsigned int cpui386:1;
 385       unsigned int cpui486:1;
 386       unsigned int cpui586:1;
 387       unsigned int cpui686:1;
 388       unsigned int cpucmov:1;
 389       unsigned int cpufxsr:1;
 390       unsigned int cpuclflush:1;
 391       unsigned int cpunop:1;
 392       unsigned int cpusyscall:1;
 393       unsigned int cpu8087:1;
 394       unsigned int cpu687:1;
 395       unsigned int cpufisttp:1;
 396       unsigned int cpummx:1;
 397       unsigned int cpusse:1;
 398       unsigned int cpusse2:1;
 399       unsigned int cpusse3:1;
 400       unsigned int cpupadlock:1;
 401       unsigned int cpusvme:1;
 402       unsigned int cpuvmx:1;
 403       unsigned int cpusmx:1;
 404       unsigned int cpussse3:1;
 405       unsigned int cpusse4a:1;
 406       unsigned int cpulzcnt:1;
 407       unsigned int cpupopcnt:1;
 408       unsigned int cpumonitor:1;
 409       unsigned int cpusse4_1:1;
 410       unsigned int cpusse4_2:1;
 411       unsigned int cpuavx2:1;
 412       unsigned int cpuavx512cd:1;
 413       unsigned int cpuavx512er:1;
 414       unsigned int cpuavx512pf:1;
 415       unsigned int cpuavx512dq:1;
 416       unsigned int cpuavx512bw:1;
 417       unsigned int cpuiamcu:1;
 418       unsigned int cpuxsave:1;
 419       unsigned int cpuxsaveopt:1;
 420       unsigned int cpuaes:1;
 421       unsigned int cpupclmulqdq:1;
 422       unsigned int cpufma:1;
 423       unsigned int cpufma4:1;
 424       unsigned int cpuxop:1;
 425       unsigned int cpulwp:1;
 426       unsigned int cpubmi:1;
 427       unsigned int cputbm:1;
 428       unsigned int cpumovbe:1;
 429       unsigned int cpucx16:1;
 430       unsigned int cpulahf_sahf:1;
 431       unsigned int cpuept:1;
 432       unsigned int cpurdtscp:1;
 433       unsigned int cpufsgsbase:1;
 434       unsigned int cpurdrnd:1;
 435       unsigned int cpuf16c:1;
 436       unsigned int cpubmi2:1;
 437       unsigned int cpurtm:1;
 438       unsigned int cpuinvpcid:1;
 439       unsigned int cpuvmfunc:1;
 440       unsigned int cpumpx:1;
 441       unsigned int cpurdseed:1;
 442       unsigned int cpuadx:1;
 443       unsigned int cpuprfchw:1;
 444       unsigned int cpusmap:1;
 445       unsigned int cpusha:1;
 446       unsigned int cpusha512:1;
 447       unsigned int cpusm3:1;
 448       unsigned int cpusm4:1;
 449       unsigned int cpuclflushopt:1;
 450       unsigned int cpuxsaves:1;
 451       unsigned int cpuxsavec:1;
 452       unsigned int cpuprefetchwt1:1;
 453       unsigned int cpuse1:1;
 454       unsigned int cpuclwb:1;
 455       unsigned int cpuavx512ifma:1;
 456       unsigned int cpuavx512vbmi:1;
 457       unsigned int cpuavx512_4fmaps:1;
 458       unsigned int cpuavx512_4vnniw:1;
 459       unsigned int cpuavx512_vpopcntdq:1;
 460       unsigned int cpuavx512_vbmi2:1;
 461       unsigned int cpuavx512_vnni:1;
 462       unsigned int cpuavx512_bitalg:1;
 463       unsigned int cpuavx512_bf16:1;
 464       unsigned int cpuavx512_vp2intersect:1;
 465       unsigned int cputdx:1;
 466       unsigned int cpuavx_vnni:1;
 467       unsigned int cpuavx512_fp16:1;
 468       unsigned int cpuprefetchi:1;
 469       unsigned int cpuavx_ifma:1;
 470       unsigned int cpuavx_vnni_int8:1;
 471       unsigned int cpuavx_vnni_int16:1;
 472       unsigned int cpucmpccxadd:1;
 473       unsigned int cpuwrmsrns:1;
 474       unsigned int cpumsrlist:1;
 475       unsigned int cpuavx_ne_convert:1;
 476       unsigned int cpurao_int:1;
 477       unsigned int cpufred:1;
 478       unsigned int cpulkgs:1;
 479       unsigned int cpuuser_msr:1;
 480       unsigned int cpumwaitx:1;
 481       unsigned int cpuclzero:1;
 482       unsigned int cpuospke:1;
 483       unsigned int cpurdpid:1;
 484       unsigned int cpuptwrite:1;
 485       unsigned int cpuibt:1;
 486       unsigned int cpushstk:1;
 487       unsigned int cpuamx_int8:1;
 488       unsigned int cpuamx_bf16:1;
 489       unsigned int cpuamx_fp16:1;
 490       unsigned int cpuamx_complex:1;
 491       unsigned int cpuamx_tile:1;
 492       unsigned int cpugfni:1;
 493       unsigned int cpuvaes:1;
 494       unsigned int cpuvpclmulqdq:1;
 495       unsigned int cpuwbnoinvd:1;
 496       unsigned int cpupconfig:1;
 497       unsigned int cpupbndkb:1;
 498       unsigned int cpuwaitpkg:1;
 499       unsigned int cpuuintr:1;
 500       unsigned int cpucldemote:1;
 501       unsigned int cpumovdiri:1;
 502       unsigned int cpumovdir64b:1;
 503       unsigned int cpuenqcmd:1;
 504       unsigned int cpuserialize:1;
 505       unsigned int cpurdpru:1;
 506       unsigned int cpumcommit:1;
 507       unsigned int cpusev_es:1;
 508       unsigned int cputsxldtrk:1;
 509       unsigned int cpukl:1;
 510       unsigned int cpuwidekl:1;
 511       unsigned int cpuhreset:1;
 512       unsigned int cpuinvlpgb:1;
 513       unsigned int cputlbsync:1;
 514       unsigned int cpusnp:1;
 515       unsigned int cpurmpquery:1;
 516       CPU_FLAGS_COMMON;
 517 #ifdef CpuUnused
 518       unsigned int unused:(CpuNumOfBits - CpuUnused);
 519 #endif
 520     } bitfield;
 521   unsigned int array[CpuNumOfUints];
 522 } i386_cpu_flags;
 523
 524 /* Position of opcode_modifier bits.  */
 525
 526 enum
 527 {
 528   /* has direction bit. */
 529   D = 0,
 530   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 531      canonical way; the base_opcode field should hold the encoding for byte
 532      operands  */
 533   W,
 534   /* load form instruction. Must be placed before store form.  */
 535   Load,
 536   /* insn has a modrm byte. */
 537   Modrm,
 538   /* special case for jump insns; value has to be 1 */
 539 #define JUMP 1
 540   /* call and jump */
 541 #define JUMP_DWORD 2
 542   /* loop and jecxz */
 543 #define JUMP_BYTE 3
 544   /* special case for intersegment leaps/calls */
 545 #define JUMP_INTERSEGMENT 4
 546   /* absolute address for jump */
 547 #define JUMP_ABSOLUTE 5
 548   Jump,
 549   /* FP insn memory format bit, sized by 0x4 */
 550   FloatMF,
 551   /* needs size prefix if in 32-bit mode */
 552 #define SIZE16 1
 553   /* needs size prefix if in 16-bit mode */
 554 #define SIZE32 2
 555   /* needs size prefix if in 64-bit mode */
 556 #define SIZE64 3
 557   Size,
 558   /* Check that operand sizes match.  */
 559   CheckOperandSize,
 560   /* any memory size */
 561 #define ANY_SIZE 1
 562   /* fake an extra reg operand for clr, imul and special register
 563      processing for some instructions.  */
 564 #define REG_KLUDGE 2
 565   /* deprecated fp insn, gets a warning */
 566 #define UGH 3
 567   /* An implicit xmm0 as the first operand */
 568 #define IMPLICIT_1ST_XMM0 4
 569   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 570      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 571    */
 572 #define IMPLICIT_QUAD_GROUP 5
 573   /* Two source operands are swapped.  */
 574 #define SWAP_SOURCES 6
 575   /* Default mask isn't allowed.  */
 576 #define NO_DEFAULT_MASK 7
 577   /* Address prefix changes register operand */
 578 #define ADDR_PREFIX_OP_REG 8
 579   /* Instrucion requires that destination must be distinct from source
 580      registers.  */
 581 #define DISTINCT_DEST 9
 582   /* Instrucion requires REX2 prefix.  */
 583 #define REX2_REQUIRED 10
 584   OperandConstraint,
 585   /* instruction ignores operand size prefix and in Intel mode ignores
 586      mnemonic size suffix check.  */
 587 #define IGNORESIZE      1
 588   /* default insn size depends on mode */
 589 #define DEFAULTSIZE     2
 590   MnemonicSize,
 591   /* b suffix on instruction illegal */
 592   No_bSuf,
 593   /* w suffix on instruction illegal */
 594   No_wSuf,
 595   /* l suffix on instruction illegal */
 596   No_lSuf,
 597   /* s suffix on instruction illegal */
 598   No_sSuf,
 599   /* q suffix on instruction illegal */
 600   No_qSuf,
 601   /* instruction needs FWAIT */
 602   FWait,
 603   /* IsString provides for a quick test for string instructions, and
 604      its actual value also indicates which of the operands (if any)
 605      requires use of the %es segment.  */
 606 #define IS_STRING_ES_OP0 2
 607 #define IS_STRING_ES_OP1 3
 608   IsString,
 609   /* RegMem is for instructions with a modrm byte where the register
 610      destination operand should be encoded in the mod and regmem fields.
 611      Normally, it will be encoded in the reg field. We add a RegMem
 612      flag to indicate that it should be encoded in the regmem field.  */
 613   RegMem,
 614   /* quick test if branch instruction is MPX supported */
 615   BNDPrefixOk,
 616 #define PrefixNone              0
 617 #define PrefixRep               1
 618 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 619 #define PrefixNoTrack           3
 620   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 621      to come before.  */
 622 #define PrefixLock              4
 623 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 624 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 625   PrefixOk,
 626   /* opcode is a prefix */
 627   IsPrefix,
 628   /* instruction has extension in 8 bit imm */
 629   ImmExt,
 630   /* instruction don't need Rex64 prefix.  */
 631   NoRex64,
 632   /* insn has VEX prefix:
 633         1: 128bit VEX prefix (or operand dependent).
 634         2: 256bit VEX prefix.
 635         3: Scalar VEX prefix.
 636    */
 637 #define VEX128          1
 638 #define VEX256          2
 639 #define VEXScalar       3
 640   Vex,
 641   /* How to encode VEX.vvvv:
 642      0: VEX.vvvv must be 1111b.
 643      1: VEX.vvvv encodes one of the src register operands.
 644      2: VEX.vvvv encodes the dest register operand.
 645    */
 646 #define VexVVVV_DST   2
 647   VexVVVV,
 648   /* How the VEX.W bit is used:
 649      0: Set by the REX.W bit.
 650      1: VEX.W0.  Should always be 0.
 651      2: VEX.W1.  Should always be 1.
 652      3: VEX.WIG. The VEX.W bit is ignored.
 653    */
 654 #define VEXW0   1
 655 #define VEXW1   2
 656 #define VEXWIG  3
 657   VexW,
 658   /* Opcode prefix (values chosen to be usable directly in
 659      VEX/XOP/EVEX pp fields):
 660      0: None
 661      1: Add 0x66 opcode prefix.
 662      2: Add 0xf3 opcode prefix.
 663      3: Add 0xf2 opcode prefix.
 664    */
 665 #define PREFIX_NONE     0
 666 #define PREFIX_0X66     1
 667 #define PREFIX_0XF3     2
 668 #define PREFIX_0XF2     3
 669   OpcodePrefix,
 670   /* Instruction with a mandatory SIB byte:
 671         1: 128bit vector register.
 672         2: 256bit vector register.
 673         3: 512bit vector register.
 674    */
 675 #define VECSIB128       1
 676 #define VECSIB256       2
 677 #define VECSIB512       3
 678 #define SIBMEM          4
 679   SIB,
 680
 681   /* SSE to AVX support required */
 682   SSE2AVX,
 683
 684   /* insn has EVEX prefix:
 685         1: 512bit EVEX prefix.
 686         2: 128bit EVEX prefix.
 687         3: 256bit EVEX prefix.
 688         4: Length-ignored (LIG) EVEX prefix.
 689         5: Length determined from actual operands.
 690         6: L'L = 3 (reserved, .insn only)
 691    */
 692 #define EVEX512                1
 693 #define EVEX128                2
 694 #define EVEX256                3
 695 #define EVEXLIG                4
 696 #define EVEXDYN                5
 697 #define EVEX_L3                6
 698   EVex,
 699
 700   /* AVX512 masking support */
 701   Masking,
 702
 703   /* AVX512 broadcast support.  The number of bytes to broadcast is
 704      1 << (Broadcast - 1):
 705         1: Byte broadcast.
 706         2: Word broadcast.
 707         3: Dword broadcast.
 708         4: Qword broadcast.
 709    */
 710 #define BYTE_BROADCAST  1
 711 #define WORD_BROADCAST  2
 712 #define DWORD_BROADCAST 3
 713 #define QWORD_BROADCAST 4
 714   Broadcast,
 715
 716   /* Static rounding control is supported.  */
 717   StaticRounding,
 718
 719   /* Supress All Exceptions is supported.  */
 720   SAE,
 721
 722   /* Compressed Disp8*N attribute.  */
 723 #define DISP8_SHIFT_VL 7
 724   Disp8MemShift,
 725
 726   /* Support encoding optimization.  */
 727   Optimize,
 728
 729   /* Language dialect.  NOTE: Order matters!  */
 730 #define INTEL_SYNTAX 1
 731 #define ATT_SYNTAX   2
 732 #define ATT_MNEMONIC 3
 733   Dialect,
 734
 735   /* ISA64: Don't change the order without other code adjustments.
 736         0: Common to AMD64 and Intel64.
 737         1: AMD64.
 738         2: Intel64.
 739         3: Only in Intel64.
 740    */
 741 #define AMD64           1
 742 #define INTEL64         2
 743 #define INTEL64ONLY     3
 744   ISA64,
 745
 746   /* egprs (r16-r31) on instruction illegal. We also use it to judge
 747      whether the instruction supports pseudo-prefix {rex2}.  */
 748   NoEgpr,
 749
 750   /* No CSPAZO flags update indication.  */
 751   NF,
 752
 753   /* The last bitfield in i386_opcode_modifier.  */
 754   Opcode_Modifier_Num
 755 };
 756
 757 typedef struct i386_opcode_modifier
 758 {
 759   unsigned int d:1;
 760   unsigned int w:1;
 761   unsigned int load:1;
 762   unsigned int modrm:1;
 763   unsigned int jump:3;
 764   unsigned int floatmf:1;
 765   unsigned int size:2;
 766   unsigned int checkoperandsize:1;
 767   unsigned int operandconstraint:4;
 768   unsigned int mnemonicsize:2;
 769   unsigned int no_bsuf:1;
 770   unsigned int no_wsuf:1;
 771   unsigned int no_lsuf:1;
 772   unsigned int no_ssuf:1;
 773   unsigned int no_qsuf:1;
 774   unsigned int fwait:1;
 775   unsigned int isstring:2;
 776   unsigned int regmem:1;
 777   unsigned int bndprefixok:1;
 778   unsigned int prefixok:3;
 779   unsigned int isprefix:1;
 780   unsigned int immext:1;
 781   unsigned int norex64:1;
 782   unsigned int vex:2;
 783   unsigned int vexvvvv:2;
 784   unsigned int vexw:2;
 785   unsigned int opcodeprefix:2;
 786   unsigned int sib:3;
 787   unsigned int sse2avx:1;
 788   unsigned int evex:3;
 789   unsigned int masking:1;
 790   unsigned int broadcast:3;
 791   unsigned int staticrounding:1;
 792   unsigned int sae:1;
 793   unsigned int disp8memshift:3;
 794   unsigned int optimize:1;
 795   unsigned int dialect:2;
 796   unsigned int isa64:2;
 797   unsigned int noegpr:1;
 798   unsigned int nf:1;
 799 } i386_opcode_modifier;
 800
 801 /* Operand classes.  */
 802
 803 #define CLASS_WIDTH 4
 804 enum operand_class
 805 {
 806   ClassNone,
 807   Reg, /* GPRs and FP regs, distinguished by operand size */
 808   SReg, /* Segment register */
 809   RegCR, /* Control register */
 810   RegDR, /* Debug register */
 811   RegTR, /* Test register */
 812   RegMMX, /* MMX register */
 813   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 814   RegMask, /* Vector Mask register */
 815   RegBND, /* Bound register */
 816 };
 817
 818 /* Special operand instances.  */
 819
 820 #define INSTANCE_WIDTH 3
 821 enum operand_instance
 822 {
 823   InstanceNone,
 824   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 825   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 826   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 827   RegB,  /* %bl / %bx / %ebx / %rbx */
 828 };
 829
 830 /* Position of operand_type bits.  */
 831
 832 enum
 833 {
 834   /* Class and Instance */
 835   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 836   /* 1 bit immediate */
 837   Imm1,
 838   /* 8 bit immediate */
 839   Imm8,
 840   /* 8 bit immediate sign extended */
 841   Imm8S,
 842   /* 16 bit immediate */
 843   Imm16,
 844   /* 32 bit immediate */
 845   Imm32,
 846   /* 32 bit immediate sign extended */
 847   Imm32S,
 848   /* 64 bit immediate */
 849   Imm64,
 850   /* 8bit/16bit/32bit displacements are used in different ways,
 851      depending on the instruction.  For jumps, they specify the
 852      size of the PC relative displacement, for instructions with
 853      memory operand, they specify the size of the offset relative
 854      to the base register, and for instructions with memory offset
 855      such as `mov 1234,%al' they specify the size of the offset
 856      relative to the segment base.  */
 857   /* 8 bit displacement */
 858   Disp8,
 859   /* 16 bit displacement */
 860   Disp16,
 861   /* 32 bit displacement (64-bit: sign-extended) */
 862   Disp32,
 863   /* 64 bit displacement */
 864   Disp64,
 865   /* Register which can be used for base or index in memory operand.  */
 866   BaseIndex,
 867   /* BYTE size. */
 868   Byte,
 869   /* WORD size. 2 byte */
 870   Word,
 871   /* DWORD size. 4 byte */
 872   Dword,
 873   /* FWORD size. 6 byte */
 874   Fword,
 875   /* QWORD size. 8 byte */
 876   Qword,
 877   /* TBYTE size. 10 byte */
 878   Tbyte,
 879   /* XMMWORD size. */
 880   Xmmword,
 881   /* YMMWORD size. */
 882   Ymmword,
 883   /* ZMMWORD size.  */
 884   Zmmword,
 885   /* TMMWORD size.  */
 886   Tmmword,
 887   /* Unspecified memory size.  */
 888   Unspecified,
 889
 890   /* The number of bits in i386_operand_type.  */
 891   OTNum
 892 };
 893
 894 #define OTNumOfUints \
 895   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 896 #define OTNumOfBits \
 897   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 898
 899 /* If you get a compiler error for zero width of the unused field,
 900    comment it out.  */
 901 #define OTUnused                OTNum
 902
 903 typedef union i386_operand_type
 904 {
 905   struct
 906     {
 907       unsigned int class:CLASS_WIDTH;
 908       unsigned int instance:INSTANCE_WIDTH;
 909       unsigned int imm1:1;
 910       unsigned int imm8:1;
 911       unsigned int imm8s:1;
 912       unsigned int imm16:1;
 913       unsigned int imm32:1;
 914       unsigned int imm32s:1;
 915       unsigned int imm64:1;
 916       unsigned int disp8:1;
 917       unsigned int disp16:1;
 918       unsigned int disp32:1;
 919       unsigned int disp64:1;
 920       unsigned int baseindex:1;
 921       unsigned int byte:1;
 922       unsigned int word:1;
 923       unsigned int dword:1;
 924       unsigned int fword:1;
 925       unsigned int qword:1;
 926       unsigned int tbyte:1;
 927       unsigned int xmmword:1;
 928       unsigned int ymmword:1;
 929       unsigned int zmmword:1;
 930       unsigned int tmmword:1;
 931       unsigned int unspecified:1;
 932 #ifdef OTUnused
 933       unsigned int unused:(OTNumOfBits - OTUnused);
 934 #endif
 935     } bitfield;
 936   unsigned int array[OTNumOfUints];
 937 } i386_operand_type;
 938
 939 typedef struct insn_template
 940 {
 941   /* instruction name sans width suffix ("mov" for movl insns) */
 942   unsigned int mnem_off;
 943
 944   /* Bitfield arrangement is such that individual fields can be easily
 945      extracted (in native builds at least) - either by at most a masking
 946      operation (base_opcode, operands), or by just a (signed) right shift
 947      (extension_opcode).  Please try to maintain this property.  */
 948
 949   /* base_opcode is the fundamental opcode byte without optional
 950      prefix(es).  */
 951   unsigned int base_opcode:16;
 952 #define Opcode_D        0x2 /* Direction bit:
 953                                set if Reg --> Regmem;
 954                                unset if Regmem --> Reg. */
 955 #define Opcode_FloatR   0x8 /* ModR/M bit to swap src/dest for float insns. */
 956 #define Opcode_FloatD   0x4 /* Direction bit for float insns. */
 957 #define Opcode_ExtD     0x1 /* Direction bit for extended opcode space insns. */
 958 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 959 /* The next value is arbitrary, as long as it's non-zero and distinct
 960    from all other values above.  */
 961 #define Opcode_VexW     0xf /* Operand order controlled by VEX.W. */
 962
 963   /* how many operands */
 964   unsigned int operands:3;
 965
 966   /* opcode space */
 967   unsigned int opcode_space:4;
 968   /* Opcode encoding space (values chosen to be usable directly in
 969      VEX/XOP mmmmm and EVEX mm fields):
 970      0: Base opcode space.
 971      1: 0F opcode prefix / space.
 972      2: 0F38 opcode prefix / space.
 973      3: 0F3A opcode prefix / space.
 974      4: EVEXMAP4 opcode prefix / space.
 975      5: EVEXMAP5 opcode prefix / space.
 976      6: EVEXMAP6 opcode prefix / space.
 977      7: VEXMAP7 opcode prefix / space.
 978      8: XOP 08 opcode space.
 979      9: XOP 09 opcode space.
 980      A: XOP 0A opcode space.
 981    */
 982 #define SPACE_BASE      0
 983 #define SPACE_0F        1
 984 #define SPACE_0F38      2
 985 #define SPACE_0F3A      3
 986 #define SPACE_EVEXMAP4  4
 987 #define SPACE_EVEXMAP5  5
 988 #define SPACE_EVEXMAP6  6
 989 #define SPACE_VEXMAP7   7
 990 #define SPACE_XOP08     8
 991 #define SPACE_XOP09     9
 992 #define SPACE_XOP0A     0xA
 993
 994 /* (Fake) base opcode value for pseudo prefixes.  */
 995 #define PSEUDO_PREFIX 0
 996
 997   /* extension_opcode is the 3 bit extension for group <n> insns.
 998      This field is also used to store the 8-bit opcode suffix for the
 999      AMD 3DNow! instructions.
1000      If this template has no extension opcode (the usual case) use None
1001      Instructions */
1002   signed int extension_opcode:9;
1003 #define None (-1)               /* If no extension_opcode is possible.  */
1004
1005 /* Pseudo prefixes.  */
1006 #define Prefix_Disp8            0       /* {disp8} */
1007 #define Prefix_Disp16           1       /* {disp16} */
1008 #define Prefix_Disp32           2       /* {disp32} */
1009 #define Prefix_Load             3       /* {load} */
1010 #define Prefix_Store            4       /* {store} */
1011 #define Prefix_VEX              5       /* {vex} */
1012 #define Prefix_VEX3             6       /* {vex3} */
1013 #define Prefix_EVEX             7       /* {evex} */
1014 #define Prefix_REX              8       /* {rex} */
1015 #define Prefix_REX2             9       /* {rex2} */
1016 #define Prefix_NoOptimize       10      /* {nooptimize} */
1017
1018   /* the bits in opcode_modifier are used to generate the final opcode from
1019      the base_opcode.  These bits also are used to detect alternate forms of
1020      the same instruction */
1021   i386_opcode_modifier opcode_modifier;
1022
1023   /* cpu feature attributes */
1024   i386_cpu_attr cpu, cpu_any;
1025
1026   /* operand_types[i] describes the type of operand i.  This is made
1027      by OR'ing together all of the possible type masks.  (e.g.
1028      'operand_types[i] = Reg|Imm' specifies that operand i can be
1029      either a register or an immediate operand.  */
1030   i386_operand_type operand_types[MAX_OPERANDS];
1031 }
1032 insn_template;
1033
1034 /* these are for register name --> number & type hash lookup */
1035 typedef struct
1036 {
1037   char reg_name[8];
1038   i386_operand_type reg_type;
1039   unsigned char reg_flags;
1040 #define RegRex      0x1  /* Extended register.  */
1041 #define RegRex64    0x2  /* Extended 8 bit register.  */
1042 #define RegVRex     0x4  /* Extended vector register.  */
1043 #define RegRex2     0x8  /* Extended GPRs R16–R31 register.  */
1044   unsigned char reg_num;
1045 #define RegIP   ((unsigned char ) ~0)
1046 /* EIZ and RIZ are fake index registers.  */
1047 #define RegIZ   (RegIP - 1)
1048 /* FLAT is a fake segment register (Intel mode).  */
1049 #define RegFlat     ((unsigned char) ~0)
1050   signed char dw2_regnum[2];
1051 #define Dw2Inval (-1)
1052 }
1053 reg_entry;