| blob | 2e5084978e2c08c34516a39ccf33b9a0aa6083a4 |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2023 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
60 #define elf_info_to_howto NULL
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
79 {
80 /* No relocation. */
109 /* 32 bit absolute */
124 /* standard 32bit pc-relative reloc */
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
154 /* 16 bit absolute */
169 /* 12 bit absolute */
198 /* 8 bit absolute */
297 /* BLX instruction for the ARM. */
312 /* BLX instruction for the Thumb. */
327 /* Dynamic TLS relocations. */
371 /* Relocs used in ARM Linux */
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
894 /* Group relocations. */
1274 /* End of group relocations. */
1488 /* GNU extension to record C++ vtable member usage */
1503 /* GNU extension to record C++ vtable hierarchy */
1546 /* TLS relocations */
1659 /* 112-127 private relocations. */
1677 /* R_ARM_ME_TOO, obsolete. */
1747 /* Relocations for Armv8.1-M Mainline. */
1787 };
1789 /* 160 onwards: */
1791 {
1896 };
1898 /* 249-255 extended, currently unused, relocations: */
1900 {
1956 };
1960 {
1973 }
1975 static bool
1978 {
1983 {
1984 /* xgettext:c-format */
1989 }
1991 }
1993 struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
1997 };
1999 /* All entries in this list must also be present in elf32_arm_howto_table. */
2001 {
2102 };
2106 bfd_reloc_code_real_type code)
2107 {
2115 }
2120 {
2139 }
2141 /* Support for core dump NOTE sections. */
2143 static bool
2145 {
2150 {
2155 /* pr_cursig */
2158 /* pr_pid */
2161 /* pr_reg */
2166 }
2168 /* Make a ".reg/999" section. */
2171 }
2173 static bool
2175 {
2177 {
2188 }
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
2193 {
2199 }
2202 }
2207 {
2209 {
2214 {
2221 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2222 DIAGNOSTIC_PUSH;
2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228 #endif
2230 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2231 DIAGNOSTIC_POP;
2232 #endif
2237 }
2240 {
2259 }
2260 }
2261 }
2263 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2265 #define TARGET_BIG_SYM arm_elf32_be_vec
2268 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2270 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2275 /* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
2277 #define INTERWORK_FLAG(abfd) \
2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
2282 /* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
2285 name can be changed. The only requirement is the %s be present. */
2307 /* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2311 /* FDPIC default stack size. */
2312 #define DEFAULT_STACK_SIZE 0x8000
2315 {
2319 };
2322 {
2330 + dl_tlsdesc_lazy_resolver(GOT) */
2332 };
2334 /* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2339 /* ARM FDPIC PLT entry. */
2340 /* The last 5 words contain PLT lazy fragment code and data. */
2342 {
2353 };
2355 /* Thumb FDPIC PLT entry. */
2356 /* The last 5 words contain PLT lazy fragment code and data. */
2358 {
2369 };
2371 #ifdef FOUR_WORD_PLT
2373 /* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
2375 called before the relocation has been set up calls the dynamic
2376 linker first. */
2378 {
2383 };
2385 /* Subsequent entries in a procedure linkage table look like
2386 this. */
2388 {
2393 };
2397 /* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
2402 {
2408 };
2410 /* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2413 {
2417 };
2419 /* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2422 {
2427 };
2433 /* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2437 {
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
2442 /* add lr, pc */
2445 };
2447 /* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2450 {
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
2457 /* b .-4 */
2458 };
2460 /* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2463 {
2468 };
2470 /* The format of subsequent entries in a VxWorks executable. */
2472 {
2479 };
2481 /* The format of entries in a VxWorks shared library. */
2483 {
2490 };
2492 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2493 #define PLT_THUMB_STUB_SIZE 4
2495 {
2498 };
2500 /* The first entry in a procedure linkage table looks like
2501 this. It is set up so that any shared library function that is
2502 called before the relocation has been set up calls the dynamic
2503 linker first. */
2505 {
2506 /* First bundle: */
2511 /* Second bundle: */
2516 /* Third bundle: */
2520 /* .Lplt_tail: */
2522 /* Fourth bundle: */
2527 };
2528 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2530 /* Subsequent entries in a procedure linkage table look like this. */
2532 {
2537 };
2539 /* PR 28924:
2540 There was a bug due to too high values of THM_MAX_FWD_BRANCH_OFFSET and
2541 THM2_MAX_FWD_BRANCH_OFFSET. The first macro concerns the case when Thumb-2
2542 is not available, and second macro when Thumb-2 is available. Among other
2543 things, they affect the range of branches represented as BLX instructions
2544 in Encoding T2 defined in Section A8.8.25 of the ARM Architecture
2545 Reference Manual ARMv7-A and ARMv7-R edition issue C.d. Such branches are
2546 specified there to have a maximum forward offset that is a multiple of 4.
2547 Previously, the respective values defined here were multiples of 2 but not
2548 4 and they are included in comments for reference. */
2549 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2550 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2551 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 4 + 4)
2552 /* #def THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 2 + 4) */
2553 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2554 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 4) + 4)
2555 /* #def THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4) */
2556 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2557 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2558 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2560 enum stub_insn_type
2561 {
2563 THUMB32_TYPE,
2564 ARM_TYPE,
2565 DATA_TYPE
2566 };
2568 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2569 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2570 is inserted in arm_build_one_stub(). */
2571 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2572 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2573 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2574 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2575 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2576 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2577 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2578 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2581 {
2582 bfd_vma data;
2588 /* See note [Thumb nop sequence] when adding a veneer. */
2590 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2591 to reach the stub if necessary. */
2593 {
2596 };
2598 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2599 available. */
2601 {
2605 };
2607 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2609 {
2617 };
2619 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2621 {
2624 };
2626 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2627 M-profile architectures. */
2629 {
2633 };
2635 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2636 allowed. */
2638 {
2644 };
2646 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2647 available. */
2649 {
2654 };
2656 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2657 one, when the destination is close enough. */
2659 {
2663 };
2665 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2666 blx to reach the stub if necessary. */
2668 {
2672 };
2674 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2675 blx to reach the stub if necessary. We can not add into pc;
2676 it is not guaranteed to mode switch (different in ARMv6 and
2677 ARMv7). */
2679 {
2684 };
2686 /* V4T ARM -> ARM long branch stub, PIC. */
2688 {
2693 };
2695 /* V4T Thumb -> ARM long branch stub, PIC. */
2697 {
2703 };
2705 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2706 architectures. */
2708 {
2716 };
2718 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2719 allowed. */
2721 {
2728 };
2730 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2731 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2733 {
2737 };
2739 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2740 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2742 {
2748 };
2750 /* NaCl ARM -> ARM long branch stub. */
2752 {
2761 };
2763 /* NaCl ARM -> ARM long branch stub, PIC. */
2765 {
2774 };
2776 /* Stub used for transition to secure state (aka SG veneer). */
2778 {
2781 };
2784 /* Cortex-A8 erratum-workaround stubs. */
2786 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2787 can't use a conditional branch to reach this stub). */
2790 {
2794 };
2796 /* Stub used for b.w and bl.w instructions. */
2799 {
2801 };
2804 {
2806 };
2808 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2809 instruction (which switches to ARM mode) to point to this stub. Jump to the
2810 real destination using an ARM-mode branch. */
2813 {
2815 };
2817 /* For each section group there can be a specially created linker section
2818 to hold the stubs for that group. The name of the stub section is based
2819 upon the name of another section within that group with the suffix below
2820 applied.
2822 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2823 create what appeared to be a linker stub section when it actually
2824 contained user code/data. For example, consider this fragment:
2826 const char * stubborn_problems[] = { "np" };
2828 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2829 section called:
2831 .data.rel.local.stubborn_problems
2833 This then causes problems in arm32_arm_build_stubs() as it triggers:
2835 // Ignore non-stub sections.
2836 if (!strstr (stub_sec->name, STUB_SUFFIX))
2837 continue;
2839 And so the section would be ignored instead of being processed. Hence
2840 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2841 C identifier. */
2844 /* One entry per long/short branch stub defined above. */
2845 #define DEF_STUBS \
2846 DEF_STUB (long_branch_any_any) \
2847 DEF_STUB (long_branch_v4t_arm_thumb) \
2848 DEF_STUB (long_branch_thumb_only) \
2849 DEF_STUB (long_branch_v4t_thumb_thumb) \
2850 DEF_STUB (long_branch_v4t_thumb_arm) \
2851 DEF_STUB (short_branch_v4t_thumb_arm) \
2852 DEF_STUB (long_branch_any_arm_pic) \
2853 DEF_STUB (long_branch_any_thumb_pic) \
2854 DEF_STUB (long_branch_v4t_thumb_thumb_pic) \
2855 DEF_STUB (long_branch_v4t_arm_thumb_pic) \
2856 DEF_STUB (long_branch_v4t_thumb_arm_pic) \
2857 DEF_STUB (long_branch_thumb_only_pic) \
2858 DEF_STUB (long_branch_any_tls_pic) \
2859 DEF_STUB (long_branch_v4t_thumb_tls_pic) \
2860 DEF_STUB (long_branch_arm_nacl) \
2861 DEF_STUB (long_branch_arm_nacl_pic) \
2862 DEF_STUB (cmse_branch_thumb_only) \
2863 DEF_STUB (a8_veneer_b_cond) \
2864 DEF_STUB (a8_veneer_b) \
2865 DEF_STUB (a8_veneer_bl) \
2866 DEF_STUB (a8_veneer_blx) \
2867 DEF_STUB (long_branch_thumb2_only) \
2868 DEF_STUB (long_branch_thumb2_only_pure)
2870 #define DEF_STUB(x) arm_stub_##x,
2871 enum elf32_arm_stub_type
2872 {
2873 arm_stub_none,
2874 DEF_STUBS
2875 max_stub_type
2876 };
2877 #undef DEF_STUB
2879 /* Note the first a8_veneer type. */
2883 {
2888 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2890 {
2892 DEF_STUBS
2893 };
2895 struct elf32_arm_stub_hash_entry
2896 {
2897 /* Base hash table entry structure. */
2900 /* The stub section. */
2903 /* Offset within stub_sec of the beginning of this stub. */
2904 bfd_vma stub_offset;
2906 /* Given the symbol's value and its section we can determine its final
2907 value when building the stubs (so the stub knows where to jump). */
2908 bfd_vma target_value;
2911 /* Same as above but for the source of the branch to the stub. Used for
2912 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2913 such, source section does not need to be recorded since Cortex-A8 erratum
2914 workaround stubs are only generated when both source and target are in the
2915 same section. */
2916 bfd_vma source_value;
2918 /* The instruction which caused this stub to be generated (only valid for
2919 Cortex-A8 erratum workaround stubs at present). */
2922 /* The stub type. */
2924 /* Its encoding size in bytes. */
2926 /* Its template. */
2928 /* The size of the template (number of entries). */
2931 /* The symbol table entry, if any, that this was derived from. */
2934 /* Type of branch. */
2937 /* Where this stub is being called from, or, in the case of combined
2938 stub sections, the first input section in the group. */
2941 /* The name for the local symbol at the start of this stub. The
2942 stub name in the hash table has to be unique; this does not, so
2943 it can be friendlier. */
2945 };
2947 /* Used to build a map of a section. This is required for mixed-endian
2948 code/data. */
2951 {
2952 bfd_vma vma;
2954 }
2955 elf32_arm_section_map;
2957 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2960 {
2961 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2962 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2963 VFP11_ERRATUM_ARM_VENEER,
2964 VFP11_ERRATUM_THUMB_VENEER
2965 }
2966 elf32_vfp11_erratum_type;
2969 {
2971 bfd_vma vma;
2972 union
2973 {
2974 struct
2975 {
2979 struct
2980 {
2985 elf32_vfp11_erratum_type type;
2986 }
2987 elf32_vfp11_erratum_list;
2989 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2990 veneer. */
2992 {
2993 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2994 STM32L4XX_ERRATUM_VENEER
2995 }
2996 elf32_stm32l4xx_erratum_type;
2999 {
3001 bfd_vma vma;
3002 union
3003 {
3004 struct
3005 {
3009 struct
3010 {
3015 elf32_stm32l4xx_erratum_type type;
3016 }
3017 elf32_stm32l4xx_erratum_list;
3020 {
3021 DELETE_EXIDX_ENTRY,
3022 INSERT_EXIDX_CANTUNWIND_AT_END
3023 }
3024 arm_unwind_edit_type;
3026 /* A (sorted) list of edits to apply to an unwind table. */
3028 {
3029 arm_unwind_edit_type type;
3030 /* Note: we sometimes want to insert an unwind entry corresponding to a
3031 section different from the one we're currently writing out, so record the
3032 (text) section this edit relates to here. */
3036 }
3037 arm_unwind_table_edit;
3040 {
3041 /* Information about mapping symbols. */
3046 /* Information about CPU errata. */
3052 /* Information about unwind tables. */
3053 union
3054 {
3055 /* Unwind info attached to a text section. */
3056 struct
3057 {
3061 /* Unwind info attached to an .ARM.exidx section. */
3062 struct
3063 {
3068 }
3069 _arm_elf_section_data;
3071 #define elf32_arm_section_data(sec) \
3072 ((_arm_elf_section_data *) elf_section_data (sec))
3074 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3075 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3076 so may be created multiple times: we use an array of these entries whilst
3077 relaxing which we can refresh easily, then create stubs for each potentially
3078 erratum-triggering instruction once we've settled on a solution. */
3080 struct a8_erratum_fix
3081 {
3084 bfd_vma offset;
3085 bfd_vma target_offset;
3090 };
3092 /* A table of relocs applied to branches which might trigger Cortex-A8
3093 erratum. */
3095 struct a8_erratum_reloc
3096 {
3097 bfd_vma from;
3098 bfd_vma destination;
3104 };
3106 /* The size of the thread control block. */
3107 #define TCB_SIZE 8
3109 /* ARM-specific information about a PLT entry, over and above the usual
3110 gotplt_union. */
3111 struct arm_plt_info
3112 {
3113 /* We reference count Thumb references to a PLT entry separately,
3114 so that we can emit the Thumb trampoline only if needed. */
3115 bfd_signed_vma thumb_refcount;
3117 /* Some references from Thumb code may be eliminated by BL->BLX
3118 conversion, so record them separately. */
3119 bfd_signed_vma maybe_thumb_refcount;
3121 /* How many of the recorded PLT accesses were from non-call relocations.
3122 This information is useful when deciding whether anything takes the
3123 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3124 non-call references to the function should resolve directly to the
3125 real runtime target. */
3128 /* Since PLT entries have variable size if the Thumb prologue is
3129 used, we need to record the index into .got.plt instead of
3130 recomputing it from the PLT offset. */
3131 bfd_signed_vma got_offset;
3132 };
3134 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3135 struct arm_local_iplt_info
3136 {
3137 /* The information that is usually found in the generic ELF part of
3138 the hash table entry. */
3141 /* The information that is usually found in the ARM-specific part of
3142 the hash table entry. */
3145 /* A list of all potential dynamic relocations against this symbol. */
3147 };
3149 /* Structure to handle FDPIC support for local functions. */
3150 struct fdpic_local
3151 {
3155 };
3157 struct elf_arm_obj_tdata
3158 {
3161 /* Zero to warn when linking objects with incompatible enum sizes. */
3164 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3167 /* The number of entries in each of the arrays in this strcuture.
3168 Used to avoid buffer overruns. */
3169 bfd_size_type num_entries;
3171 /* tls_type for each local got entry. */
3174 /* GOTPLT entries for TLS descriptors. */
3177 /* Information for local symbols that need entries in .iplt. */
3180 /* Maintains FDPIC counters and funcdesc info. */
3182 };
3184 #define elf_arm_tdata(bfd) \
3185 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3187 #define elf32_arm_num_entries(bfd) \
3188 (elf_arm_tdata (bfd)->num_entries)
3190 #define elf32_arm_local_got_tls_type(bfd) \
3191 (elf_arm_tdata (bfd)->local_got_tls_type)
3193 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3194 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3196 #define elf32_arm_local_iplt(bfd) \
3197 (elf_arm_tdata (bfd)->local_iplt)
3199 #define elf32_arm_local_fdpic_cnts(bfd) \
3200 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3202 #define is_arm_elf(bfd) \
3203 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3204 && elf_tdata (bfd) != NULL \
3205 && elf_object_id (bfd) == ARM_ELF_DATA)
3207 static bool
3209 {
3211 ARM_ELF_DATA);
3212 }
3214 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3216 /* Structure to handle FDPIC support for extern functions. */
3223 };
3225 /* Arm ELF linker hash entry. */
3226 struct elf32_arm_link_hash_entry
3227 {
3230 /* ARM-specific PLT information. */
3233 #define GOT_UNKNOWN 0
3234 #define GOT_NORMAL 1
3235 #define GOT_TLS_GD 2
3236 #define GOT_TLS_IE 4
3237 #define GOT_TLS_GDESC 8
3238 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3241 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3246 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3247 starting at the end of the jump table. */
3248 bfd_vma tlsdesc_got;
3250 /* The symbol marking the real symbol location for exported thumb
3251 symbols with Arm stubs. */
3254 /* A pointer to the most recently used stub hash entry against this
3255 symbol. */
3258 /* Counter for FDPIC relocations against this symbol. */
3260 };
3262 /* Traverse an arm ELF linker hash table. */
3263 #define elf32_arm_link_hash_traverse(table, func, info) \
3264 (elf_link_hash_traverse \
3265 (&(table)->root, \
3266 (bool (*) (struct elf_link_hash_entry *, void *)) (func), \
3267 (info)))
3269 /* Get the ARM elf linker hash table from a link_info structure. */
3270 #define elf32_arm_hash_table(p) \
3271 ((is_elf_hash_table ((p)->hash) \
3272 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3273 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
3275 #define arm_stub_hash_lookup(table, string, create, copy) \
3276 ((struct elf32_arm_stub_hash_entry *) \
3277 bfd_hash_lookup ((table), (string), (create), (copy)))
3279 /* Array to keep track of which stub sections have been created, and
3280 information on stub grouping. */
3281 struct map_stub
3282 {
3283 /* This is the section to which stubs in the group will be
3284 attached. */
3286 /* The stub section. */
3288 };
3290 #define elf32_arm_compute_jump_table_size(htab) \
3291 ((htab)->next_tls_desc_index * 4)
3293 /* ARM ELF linker hash table. */
3294 struct elf32_arm_link_hash_table
3295 {
3296 /* The main hash table. */
3299 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3300 bfd_size_type thumb_glue_size;
3302 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3303 bfd_size_type arm_glue_size;
3305 /* The size in bytes of section containing the ARMv4 BX veneers. */
3306 bfd_size_type bx_glue_size;
3308 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3309 veneer has been populated. */
3312 /* The size in bytes of the section containing glue for VFP11 erratum
3313 veneers. */
3314 bfd_size_type vfp11_erratum_glue_size;
3316 /* The size in bytes of the section containing glue for STM32L4XX erratum
3317 veneers. */
3318 bfd_size_type stm32l4xx_erratum_glue_size;
3320 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3321 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3322 elf32_arm_write_section(). */
3326 /* An arbitrary input BFD chosen to hold the glue sections. */
3329 /* Nonzero to output a BE8 image. */
3332 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3333 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3336 /* The relocation to use for R_ARM_TARGET2 relocations. */
3339 /* 0 = Ignore R_ARM_V4BX.
3340 1 = Convert BX to MOV PC.
3341 2 = Generate v4 interworing stubs. */
3344 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3347 /* Whether we should fix the ARM1176 BLX immediate issue. */
3350 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3353 /* What sort of code sequences we should look for which may trigger the
3354 VFP11 denorm erratum. */
3355 bfd_arm_vfp11_fix vfp11_fix;
3357 /* Global counter for the number of fixes we have emitted. */
3360 /* What sort of code sequences we should look for which may trigger the
3361 STM32L4XX erratum. */
3362 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3364 /* Global counter for the number of fixes we have emitted. */
3367 /* Nonzero to force PIC branch veneers. */
3370 /* The number of bytes in the initial entry in the PLT. */
3371 bfd_size_type plt_header_size;
3373 /* The number of bytes in the subsequent PLT etries. */
3374 bfd_size_type plt_entry_size;
3376 /* True if the target uses REL relocations. */
3379 /* Nonzero if import library must be a secure gateway import library
3380 as per ARMv8-M Security Extensions. */
3383 /* The import library whose symbols' address must remain stable in
3384 the import library generated. */
3387 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3388 bfd_vma next_tls_desc_index;
3390 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3391 bfd_vma num_tls_desc;
3393 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3396 /* Offset in .plt section of tls_arm_trampoline. */
3397 bfd_vma tls_trampoline;
3399 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3400 union
3401 {
3402 bfd_signed_vma refcount;
3403 bfd_vma offset;
3406 /* For convenience in allocate_dynrelocs. */
3409 /* The amount of space used by the reserved portion of the sgotplt
3410 section, plus whatever space is used by the jump slots. */
3411 bfd_vma sgotplt_jump_table_size;
3413 /* The stub hash table. */
3416 /* Linker stub bfd. */
3419 /* Linker call-backs. */
3424 /* Array to keep track of which stub sections have been created, and
3425 information on stub grouping. */
3428 /* Input stub section holding secure gateway veneers. */
3431 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3432 start to be allocated. */
3433 bfd_vma new_cmse_stub_offset;
3435 /* Number of elements in stub_group. */
3438 /* Assorted information used by elf32_arm_size_stubs. */
3443 /* True if the target system uses FDPIC. */
3446 /* Fixup section. Used for FDPIC. */
3448 };
3450 /* Add an FDPIC read-only fixup. */
3451 static void
3453 {
3454 bfd_vma fixup_offset;
3459 }
3463 {
3464 #if GCC_VERSION >= 3004
3466 #else
3470 {
3474 }
3476 #endif
3477 }
3481 {
3482 #if GCC_VERSION >= 3004
3484 #else
3489 {
3491 sum++;
3493 }
3495 #endif
3496 }
3501 static void
3507 bfd_vma addr,
3508 bfd_vma dynreloc_value,
3509 bfd_vma seg)
3510 {
3512 {
3517 {
3519 Elf_Internal_Rela outrel;
3528 }
3529 else
3530 {
3544 }
3546 }
3547 }
3549 /* Create an entry in an ARM ELF linker hash table. */
3555 {
3559 /* Allocate the structure if it has not already been allocated by a
3560 subclass. */
3567 /* Call the allocation method of the superclass. */
3572 {
3589 }
3592 }
3594 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3595 symbols. */
3597 static bool
3599 {
3601 {
3602 bfd_size_type num_syms;
3606 /* Whilst it might be tempting to allocate a single block of memory and
3607 then divide it up amoungst the arrays in the elf_arm_obj_tdata
3608 structure, this interferes with the work of memory checkers looking
3609 for buffer overruns. So allocate each array individually. */
3645 #if GCC_VERSION >= 3000
3654 #endif
3655 }
3657 }
3659 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3660 to input bfd ABFD. Create the information if it doesn't already exist.
3661 Return null if an allocation fails. */
3665 {
3677 }
3679 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3680 in ABFD's symbol table. If the symbol is global, H points to its
3681 hash table entry, otherwise H is null.
3683 Return true if the symbol does have PLT information. When returning
3684 true, point *ROOT_PLT at the target-independent reference count/offset
3685 union and *ARM_PLT at the ARM-specific information. */
3687 static bool
3692 {
3699 {
3703 }
3718 }
3722 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3723 before it. */
3725 static bool
3728 {
3735 }
3737 /* Return a pointer to the head of the dynamic reloc list that should
3738 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3739 ABFD's symbol table. Return null if an error occurs. */
3744 {
3746 {
3753 }
3754 else
3755 {
3756 /* Track dynamic relocs needed for local syms too.
3757 We really need local syms available to do this
3758 easily. Oh well. */
3768 }
3769 }
3771 /* Initialize an entry in the stub hash table. */
3777 {
3778 /* Allocate the structure if it has not already been allocated by a
3779 subclass. */
3781 {
3786 }
3788 /* Call the allocation method of the superclass. */
3791 {
3794 /* Initialize the local fields. */
3809 }
3812 }
3814 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3815 shortcuts to them in our hash table. */
3817 static bool
3819 {
3829 /* Also create .rofixup. */
3831 {
3838 }
3841 }
3843 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3845 static bool
3847 {
3852 flagword flags;
3860 {
3867 }
3870 {
3878 }
3881 {
3887 }
3889 }
3891 /* Determine if we're dealing with a Thumb only architecture. */
3893 static bool
3895 {
3898 Tag_CPU_arch_profile);
3905 /* Force return logic to be reviewed for each new architecture. */
3917 }
3919 /* Determine if we're dealing with a Thumb-2 object. */
3921 static bool
3923 {
3926 Tag_THUMB_ISA_use);
3928 /* No use of thumb permitted, or a legacy thumb-1/2 definition. */
3932 /* Variant of thumb is described by the architecture tag. */
3935 /* Force return logic to be reviewed for each new architecture. */
3945 }
3947 /* Determine whether Thumb-2 BL instruction is available. */
3949 static bool
3951 {
3955 /* Force return logic to be reviewed for each new architecture. */
3958 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3961 }
3963 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3964 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3965 hash table. */
3967 static bool
3969 {
3983 {
3988 {
3990 htab->plt_entry_size
3992 }
3993 else
3994 {
3995 htab->plt_header_size
3997 htab->plt_entry_size
3999 }
4003 }
4004 else
4005 {
4006 /* PR ld/16017
4007 Test for thumb only architectures. Note - we cannot just call
4008 using_thumb_only() as the attributes in the output bfd have not been
4009 initialised at this point, so instead we use the input bfd. */
4014 {
4017 }
4019 }
4025 else
4027 }
4036 }
4038 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4040 static void
4044 {
4051 {
4052 /* Copy over PLT info. */
4060 /* Copy FDPIC counters. */
4065 /* We should only allocate a function to .iplt once the final
4066 symbol information is known. */
4070 {
4073 }
4074 }
4077 }
4079 /* Destroy an ARM elf linker hash table. */
4081 static void
4083 {
4089 }
4091 /* Create an ARM elf linker hash table. */
4095 {
4104 elf32_arm_link_hash_newfunc,
4106 ARM_ELF_DATA))
4107 {
4110 }
4114 #ifdef FOUR_WORD_PLT
4117 #else
4120 #endif
4127 {
4130 }
4134 }
4136 /* Determine what kind of NOPs are available. */
4138 static bool
4140 {
4142 Tag_CPU_arch);
4144 /* Force return logic to be reviewed for each new architecture. */
4153 }
4155 static bool
4157 {
4159 {
4176 }
4177 }
4179 /* Determine the type of stub needed, if any, for a call. */
4181 static enum elf32_arm_stub_type
4188 bfd_vma destination,
4192 {
4193 bfd_vma location;
4194 bfd_signed_vma branch_offset;
4219 /* True for architectures that implement the thumb2 movw instruction. */
4222 /* Determine where the call point is. */
4229 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4230 are considering a function call relocation. */
4236 /* For TLS call relocs, it is the caller's responsibility to provide
4237 the address of the appropriate trampoline. */
4244 {
4249 else
4252 {
4255 /* Note when dealing with PLT entries: the main PLT stub is in
4256 ARM mode, so if the branch is in Thumb mode, another
4257 Thumb->ARM stub will be inserted later just before the ARM
4258 PLT stub. If a long branch stub is needed, we'll add a
4259 Thumb->Arm one and branch directly to the ARM PLT entry.
4260 Here, we have to check if a pre-PLT Thumb->ARM stub
4261 is needed and if it will be close enough. */
4268 /* Thumb branch/call to PLT: it can become a branch to ARM
4269 or to Thumb. We must perform the same checks and
4270 corrections as in elf32_arm_final_link_relocate. */
4273 {
4277 {
4278 /* If the Thumb BLX instruction is available, convert
4279 the BL to a BLX instruction to call the ARM-mode
4280 PLT entry. */
4282 }
4283 else
4284 {
4286 /* Target the Thumb stub before the ARM PLT entry. */
4289 }
4290 }
4291 else
4292 {
4294 }
4295 }
4296 }
4297 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4304 {
4305 /* Handle cases where:
4306 - this call goes too far (different Thumb/Thumb2 max
4307 distance)
4308 - it's a Thumb->Arm call and blx is not available, or it's a
4309 Thumb->Arm branch (not bl). A stub is needed in this case,
4310 but only if this call is not through a PLT entry. Indeed,
4311 PLT stubs handle mode switching already. */
4315 || (thumb2_bl
4318 || (thumb2
4328 {
4329 /* If we need to insert a Thumb-Thumb long branch stub to a
4330 PLT, use one that branches directly to the ARM PLT
4331 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4332 stub, undo this now. */
4334 {
4337 }
4340 {
4341 /* Thumb to thumb. */
4343 {
4345 _bfd_error_handler
4347 " section with SHF_ARM_PURECODE section"
4348 " attribute is only supported for M-profile"
4353 /* PIC stubs. */
4356 /* V5T and above. Stub starts with ARM code, so
4357 we must be able to switch mode before
4358 reaching it, which is only possible for 'bl'
4359 (ie R_ARM_THM_CALL relocation). */
4360 ? arm_stub_long_branch_any_thumb_pic
4361 /* On V4T, use Thumb code only. */
4364 /* non-PIC stubs. */
4367 /* V5T and above. */
4368 ? arm_stub_long_branch_any_any
4369 /* V4T. */
4371 }
4372 else
4373 {
4376 else
4377 {
4379 _bfd_error_handler
4381 " section with SHF_ARM_PURECODE section"
4382 " attribute is only supported for M-profile"
4387 /* PIC stub. */
4388 ? arm_stub_long_branch_thumb_only_pic
4389 /* non-PIC stub. */
4392 }
4393 }
4394 }
4395 else
4396 {
4398 _bfd_error_handler
4400 " section with SHF_ARM_PURECODE section"
4405 /* Thumb to arm. */
4409 {
4410 _bfd_error_handler
4414 }
4416 stub_type =
4418 /* PIC stubs. */
4420 /* TLS PIC stubs. */
4424 /* V5T PIC and above. */
4425 ? arm_stub_long_branch_any_arm_pic
4426 /* V4T PIC stub. */
4429 /* non-PIC stubs. */
4431 /* V5T and above. */
4432 ? arm_stub_long_branch_any_any
4433 /* V4T. */
4436 /* Handle v4t short branches. */
4441 }
4442 }
4443 }
4448 {
4450 _bfd_error_handler
4452 " section with SHF_ARM_PURECODE section"
4453 " attribute is only supported for M-profile"
4457 {
4458 /* Arm to thumb. */
4463 {
4464 _bfd_error_handler
4468 }
4470 /* We have an extra 2-bytes reach because of
4471 the mode change (bit 24 (H) of BLX encoding). */
4477 {
4479 /* PIC stubs. */
4481 /* V5T and above. */
4482 ? arm_stub_long_branch_any_thumb_pic
4483 /* V4T stub. */
4486 /* non-PIC stubs. */
4488 /* V5T and above. */
4489 ? arm_stub_long_branch_any_any
4490 /* V4T. */
4492 }
4493 }
4494 else
4495 {
4496 /* Arm to arm. */
4499 {
4500 stub_type =
4502 /* PIC stubs. */
4504 /* TLS PIC Stub. */
4505 ? arm_stub_long_branch_any_tls_pic
4507 ? arm_stub_long_branch_arm_nacl_pic
4509 /* non-PIC stubs. */
4511 ? arm_stub_long_branch_arm_nacl
4513 }
4514 }
4515 }
4517 /* If a stub is needed, record the actual destination type. */
4522 }
4524 /* Build a name for an entry in the stub hash table. */
4532 {
4534 bfd_size_type len;
4537 {
4546 }
4547 else
4548 {
4560 }
4563 }
4565 /* Look up an entry in the stub hash. Stub entries are cached because
4566 creating the stub name takes a bit of time. */
4575 {
4583 /* If the input section is the CMSE stubs one and it needs a long
4584 branch stub to reach it's final destination, give up with an
4585 error message: this is not supported. See PR ld/24709. */
4587 {
4593 CMSE_STUB_NAME,
4599 /* Exit, rather than leave incompletely processed
4600 relocations. */
4602 }
4604 /* If this input section is part of a group of sections sharing one
4605 stub section, then use the id of the first section in the group.
4606 Stub names need to include a section id, as there may well be
4607 more than one stub used to reach say, printf, and we need to
4608 distinguish between them. */
4616 {
4618 }
4619 else
4620 {
4633 }
4636 }
4638 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4639 section. */
4641 static bool
4643 {
4648 {
4654 }
4657 }
4659 /* Required alignment (as a power of 2) for the dedicated section holding
4660 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4661 with input sections. */
4663 static int
4664 arm_dedicated_stub_output_section_required_alignment
4666 {
4671 {
4672 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4673 boundary. */
4680 }
4683 }
4685 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4686 NULL if veneers of this type are interspersed with input sections. */
4690 {
4695 {
4702 }
4705 }
4707 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4708 returns the address of the hash table field in HTAB holding a pointer to the
4709 corresponding input section. Otherwise, returns NULL. */
4714 {
4719 {
4726 }
4729 }
4731 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4732 is the section that branch into veneer and can be NULL if stub should go in
4733 a dedicated output section. Returns a pointer to the stub section, and the
4734 section to which the stub section will be attached (in *LINK_SEC_P).
4735 LINK_SEC_P may be NULL. */
4741 {
4749 {
4759 {
4763 }
4764 }
4765 else
4766 {
4776 }
4779 {
4781 bfd_size_type len;
4793 align);
4800 }
4809 }
4811 /* Add a new stub entry to the stub hash. Not all fields of the new
4812 stub entry are initialised. */
4818 {
4824 stub_type);
4828 /* Enter this entry into the linker stub hash table. */
4832 {
4838 }
4845 }
4847 /* Store an Arm insn into an output section not processed by
4848 elf32_arm_write_section. */
4850 static void
4853 {
4856 else
4858 }
4860 /* Store a 16-bit Thumb insn into an output section not processed by
4861 elf32_arm_write_section. */
4863 static void
4866 {
4869 else
4871 }
4873 /* Store a Thumb2 insn into an output section not processed by
4874 elf32_arm_write_section. */
4876 static void
4879 {
4880 /* T2 instructions are 16-bit streamed. */
4882 {
4885 }
4886 else
4887 {
4890 }
4891 }
4893 /* If it's possible to change R_TYPE to a more efficient access
4894 model, return the new reloc type. */
4896 static unsigned
4899 {
4906 /* We do not support relaxations for Old TLS models. */
4908 {
4915 }
4918 }
4920 static bfd_reloc_status_type elf32_arm_final_link_relocate
4926 static unsigned int
4928 {
4930 {
4962 }
4963 }
4965 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4966 veneering (TRUE) or have their own symbol (FALSE). */
4968 static bool
4970 {
4975 {
4981 }
4984 }
4986 /* Returns the padding needed for the dedicated section used stubs of type
4987 STUB_TYPE. */
4989 static int
4991 {
4996 {
5002 }
5005 }
5007 /* If veneers of type STUB_TYPE should go in a dedicated output section,
5008 returns the address of the hash table field in HTAB holding the offset at
5009 which new veneers should be layed out in the stub section. */
5014 {
5016 {
5023 }
5024 }
5026 static bool
5029 {
5030 #define MAXRELOCS 3
5038 bfd_vma sym_value;
5048 /* Massage our args to the form they really have. */
5052 /* Fail if the target section could not be assigned to an output
5053 section. The user should fix his linker script. */
5068 /* We have to do less-strictly-aligned fixes last. */
5071 /* Assign a slot at the end of section if none assigned yet. */
5073 {
5076 }
5081 /* This is the address of the stub destination. */
5091 {
5093 {
5095 {
5098 {
5099 /* We've borrowed the reloc_addend field to mean we should
5100 insert a condition code into this (Thumb-1 branch)
5101 instruction. See THUMB16_BCOND_INSN. */
5104 }
5107 }
5117 {
5120 }
5127 /* Handle cases where the target is encoded within the
5128 instruction. */
5130 {
5133 }
5147 }
5148 }
5153 /* Stub size has already been computed in arm_size_one_stub. Check
5154 consistency. */
5157 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5161 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5162 to relocate in each stub. */
5163 removed_sg_veneer =
5168 {
5169 Elf_Internal_Rela rel;
5172 bfd_vma points_to =
5181 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5182 template should refer back to the instruction after the original
5183 branch. We use target_section as Cortex-A8 erratum workaround stubs
5184 are only generated when both source and target are in the same
5185 section. */
5197 }
5200 #undef MAXRELOCS
5201 }
5203 /* Calculate the template, template size and instruction size for a stub.
5204 Return value is the instruction size. */
5206 static unsigned int
5210 {
5225 {
5227 {
5241 }
5242 }
5245 }
5247 /* As above, but don't actually build the stub. Just bump offset so
5248 we know stub section sizes. */
5250 static bool
5253 {
5258 /* Massage our args to the form they really have. */
5267 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5269 {
5273 }
5275 /* Already accounted for. */
5283 }
5285 /* External entry points for sizing and building linker stubs. */
5287 /* Set up various things so that we can make a list of input sections
5288 for each output section included in the link. Returns -1 on error,
5289 0 when no stubs will be needed, and 1 on success. */
5291 int
5294 {
5306 /* Count the number of input BFDs and find the top input section id. */
5310 {
5315 {
5318 }
5319 }
5328 /* We can't use output_bfd->section_count here to find the top output
5329 section index as some sections may have been removed, and
5330 _bfd_strip_section_from_output doesn't renumber the indices. */
5334 {
5337 }
5346 /* For sections we aren't interested in, mark their entries with a
5347 value we can check later. */
5349 do
5356 {
5359 }
5362 }
5364 /* The linker repeatedly calls this function for each input section,
5365 in the order that input sections are linked into output sections.
5366 Build lists of input sections to determine groupings between which
5367 we may insert linker stubs. */
5369 void
5372 {
5379 {
5383 {
5384 /* Steal the link_sec pointer for our list. */
5385 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5386 /* This happens to make the list in reverse order,
5387 which we reverse later. */
5390 }
5391 }
5392 }
5394 /* See whether we can group stub sections together. Grouping stub
5395 sections may result in fewer stubs. More importantly, we need to
5396 put all .init* and .fini* stubs at the end of the .init or
5397 .fini output sections respectively, because glibc splits the
5398 _init and _fini functions into multiple parts. Putting a stub in
5399 the middle of a function is not a good idea. */
5401 static void
5403 bfd_size_type stub_group_size,
5405 {
5408 do
5409 {
5416 /* Reverse the list: we must avoid placing stubs at the
5417 beginning of the section because the beginning of the text
5418 section may be required for an interrupt vector in bare metal
5419 code. */
5420 #define NEXT_SEC PREV_SEC
5423 {
5424 /* Pop from tail. */
5428 /* Push on head. */
5431 }
5434 {
5438 bfd_vma end_of_next;
5442 {
5446 /* End of NEXT is too far from start, so stop. */
5448 /* Add NEXT to the group. */
5450 }
5452 /* OK, the size from the start to the start of CURR is less
5453 than stub_group_size and thus can be handled by one stub
5454 section. (Or the head section is itself larger than
5455 stub_group_size, in which case we may be toast.)
5456 We should really be keeping track of the total size of
5457 stubs added here, as stubs contribute to the final output
5458 section size. */
5459 do
5460 {
5462 /* Set up this stub group. */
5464 }
5467 /* But wait, there's more! Input sections up to stub_group_size
5468 bytes after the stub section can be handled by it too. */
5470 {
5474 {
5477 /* End of NEXT is too far from stubs, so stop. */
5479 /* Add NEXT to the stub group. */
5483 }
5484 }
5486 }
5487 }
5491 #undef PREV_SEC
5492 #undef NEXT_SEC
5493 }
5495 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5496 erratum fix. */
5498 static int
5500 {
5508 else
5510 }
5515 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5516 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5517 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5518 otherwise. */
5520 static bool
5530 {
5543 {
5547 bfd_vma base_vma;
5566 {
5577 /* Span is entirely within a single 4KB region: skip scanning. */
5582 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5584 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5585 * The branch target is in the same 4KB region as the
5586 first half of the branch.
5587 * The instruction before the branch is a 32-bit
5588 length non-branch instruction. */
5590 {
5599 {
5600 /* Load the rest of the insn (in manual-friendly order). */
5603 /* Encoding T4: B<c>.W. */
5605 /* Encoding T1: BL<c>.W. */
5607 /* Encoding T2: BLX<c>.W. */
5609 /* Encoding T3: B<c>.W (not permitted in IT block). */
5612 }
5617 && insn_32bit
5618 && is_32bit_branch
5619 && last_was_32bit
5621 {
5625 bfd_vma target;
5637 {
5641 /* We don't care about the error returned from this
5642 function, only if there is glue or not. */
5649 /* Keep a simpler condition, for the sake of clarity. */
5655 {
5659 else
5661 }
5662 }
5664 /* Check if we have an offending branch instruction. */
5667 /* We've already made a stub for this instruction, e.g.
5668 it's a long branch or a Thumb->ARM stub. Assume that
5669 stub will suffice to work around the A8 erratum (see
5670 setting of always_after_branch above). */
5671 ;
5673 {
5682 }
5684 {
5704 }
5707 {
5710 /* The original instruction is a BL, but the target is
5711 an ARM instruction. If we were not making a stub,
5712 the BL would have been converted to a BLX. Use the
5713 BLX stub instead in that case. */
5716 {
5720 }
5721 /* Conversely, if the original instruction was
5722 BLX but the target is Thumb mode, use the BL
5723 stub. */
5726 {
5730 }
5735 /* If we found a relocation, use the proper destination,
5736 not the offset in the (unrelocated) instruction.
5737 Note this is always done if we switched the stub type
5738 above. */
5740 offset =
5743 /* If the stub will use a Thumb-mode branch to a
5744 PLT target, redirect it to the preceding Thumb
5745 entry point. */
5751 /* The BLX stub is ARM-mode code. Adjust the offset to
5752 take the different PC value (+8 instead of +4) into
5753 account. */
5758 {
5762 {
5768 }
5771 {
5772 /* If we're doing a subsequent scan,
5773 check if we've found the same fix as
5774 before, and try and reuse the stub
5775 name. */
5779 {
5783 }
5784 }
5787 {
5791 }
5804 num_a8_fixes++;
5805 }
5806 }
5807 }
5812 }
5813 }
5817 }
5824 }
5826 /* Create or update a stub entry depending on whether the stub can already be
5827 found in HTAB. The stub is identified by:
5828 - its type STUB_TYPE
5829 - its source branch (note that several can share the same stub) whose
5830 section and relocation (if any) are given by SECTION and IRELA
5831 respectively
5832 - its target symbol whose input section, hash, name, value and branch type
5833 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5834 respectively
5836 If found, the value of the stub's target symbol is updated from SYM_VALUE
5837 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5838 TRUE and the stub entry is initialized.
5840 Returns the stub that was created or updated, or NULL if an error
5841 occurred. */
5850 {
5862 else
5863 {
5868 /* Support for grouping stub sections. */
5871 /* Get the name of this stub. */
5873 stub_type);
5876 }
5880 /* The proper stub has already been created, just update its value. */
5882 {
5887 }
5891 {
5895 }
5905 else
5906 {
5913 {
5916 }
5918 /* For historical reasons, use the existing names for ARM-to-Thumb and
5919 Thumb-to-ARM stubs. */
5930 else
5932 }
5936 }
5938 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5939 gateway veneer to transition from non secure to secure state and create them
5940 accordingly.
5942 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5943 defines the conditions that govern Secure Gateway veneer creation for a
5944 given symbol <SYM> as follows:
5945 - it has function type
5946 - it has non local binding
5947 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5948 same type, binding and value as <SYM> (called normal symbol).
5949 An entry function can handle secure state transition itself in which case
5950 its special symbol would have a different value from the normal symbol.
5952 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5953 entry mapping while HTAB gives the name to hash entry mapping.
5954 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5955 created.
5957 The return value gives whether a stub failed to be allocated. */
5959 static bool
5963 {
5971 bfd_vma sym_value;
5987 NULL);
5991 /* Scan symbols. */
5993 {
5997 {
6005 /* Special symbol with local binding. */
6007 }
6008 else
6009 {
6018 /* Special symbol has incorrect binding or type. */
6023 }
6026 {
6032 }
6035 {
6042 }
6048 /* No associated normal symbol or it is neither global nor weak. */
6053 {
6054 /* Initialize here to avoid warning about use of possibly
6055 uninitialized variable. */
6059 {
6060 /* Searching for a normal symbol with local binding. */
6062 {
6063 lsym_name =
6069 }
6070 }
6073 {
6074 _bfd_error_handler
6078 }
6079 else
6080 _bfd_error_handler
6085 }
6091 {
6092 _bfd_error_handler
6096 }
6100 /* If this section is a link-once section that will be discarded, then
6101 don't create any stubs. */
6103 {
6104 _bfd_error_handler
6107 }
6110 {
6111 _bfd_error_handler
6114 }
6119 stub_entry
6126 else
6127 {
6130 }
6131 }
6136 }
6138 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6139 code entry function, ie can be called from non secure code without using a
6140 veneer. */
6142 static bool
6144 {
6148 file_ptr offset;
6151 /* Defined symbol of function type. */
6158 /* Read first instruction. */
6168 /* Starts by SG instruction. */
6170 }
6172 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6173 secure gateway veneers (ie. the veneers was not in the input import library)
6174 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6176 static bool
6178 {
6182 /* Massage our args to the form they really have. */
6196 }
6198 /* Set offset of each secure gateway veneers so that its address remain
6199 identical to the one in the input import library referred by
6200 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6201 (present in input import library but absent from the executable being
6202 linked) or if new veneers appeared and there is no output import library
6203 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6204 number of secure gateway veneers found in the input import library.
6206 The function returns whether an error occurred. If no error occurred,
6207 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6208 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6209 veneer observed set for new veneers to be layed out after. */
6211 static bool
6215 {
6218 flagword flags;
6225 bfd_size_type cmse_stub_size;
6234 /* No input secure gateway import library. */
6240 {
6244 }
6246 /* Get symbol table size. */
6251 /* Read in the input secure gateway import library's symbol table. */
6258 {
6261 }
6264 cmse_stub_size =
6268 out_sec_name =
6270 stub_out_sec =
6275 /* Set addresses of veneers mentionned in input secure gateway import
6276 library's symbol table. */
6278 {
6289 {
6291 "symbol should be absolute, global and "
6296 }
6305 /* Stub entry should have been created by cmse_scan or the symbol be of
6306 a secure function callable from non secure code. */
6308 {
6311 _bfd_error_handler
6315 stub_entry
6322 else
6323 {
6325 new_cmse_stubs_created++;
6327 }
6330 }
6331 /* Symbol found is not callable from non secure code. */
6333 {
6335 {
6337 sym_name);
6339 }
6341 }
6342 else
6343 {
6344 /* Only stubs for SG veneers should have been created. */
6347 /* Check visibility hasn't changed. */
6350 _bfd_error_handler
6352 sym_name);
6355 }
6357 /* Size should match that of a SG veneer. */
6359 {
6363 }
6365 /* Previous veneer address is before current SG veneer section. */
6367 {
6368 /* Avoid offset underflow. */
6373 }
6375 /* Complain if stub offset not a multiple of stub size. */
6377 {
6378 _bfd_error_handler
6382 }
6387 new_cmse_stubs_created--;
6393 }
6396 {
6398 _bfd_error_handler
6402 }
6405 {
6406 _bfd_error_handler
6408 out_sec_name);
6410 }
6412 free_sym_buf:
6415 }
6417 /* Determine and set the size of the stub section for a final link.
6419 The basic idea here is to examine all the relocations looking for
6420 PC-relative calls to a target that is unreachable with a "bl"
6421 instruction. */
6423 bool
6427 bfd_signed_vma group_size,
6429 asection *,
6432 {
6436 bfd_size_type stub_group_size;
6448 {
6453 }
6455 /* Propagate mach to stub bfd, because it may not have been
6456 finalized when we created stub_bfd. */
6460 /* Stash our params away. */
6469 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6470 as the first half of a 32-bit branch straddling two 4K pages. This is a
6471 crude way of enforcing that. */
6477 else
6481 {
6482 /* Default values. */
6483 /* Thumb branch range is +-4MB has to be used as the default
6484 maximum size (a given section can contain both ARM and Thumb
6485 code, so the worst case has to be taken into account).
6487 This value is 24K less than that, which allows for 2025
6488 12-byte stubs. If we exceed that, then we will fail to link.
6489 The user will have to relink with an explicit group size
6490 option. */
6492 }
6496 /* If we're applying the cortex A8 fix, we need to determine the
6497 program header size now, because we cannot change it later --
6498 that could alter section placements. Notice the A8 erratum fix
6499 ends up requiring the section addresses to remain unchanged
6500 modulo the page size. That's something we cannot represent
6501 inside BFD, and we don't want to force the section alignment to
6502 be the page size. */
6507 {
6519 {
6533 /* We'll need the symbol table in a second. */
6538 /* Limit scan of symbols to object file whose profile is
6539 Microcontroller to not hinder performance in the general case. */
6541 {
6551 }
6553 /* Walk over each section attached to the input bfd. */
6557 {
6560 /* If there aren't any relocs, then there's nothing more
6561 to do. */
6567 /* If this section is a link-once section that will be
6568 discarded, then don't create any stubs. */
6573 /* Get the relocs. */
6574 internal_relocs
6580 /* Now examine each relocation. */
6584 {
6587 bfd_vma sym_value;
6588 bfd_vma destination;
6599 {
6601 error_ret_free_internal:
6604 /* Fall through. */
6605 error_ret_free_local:
6609 }
6613 hash = elf32_arm_hash_entry
6617 /* Only look for stubs on branch instructions, or
6618 non-relaxed TLSCALL */
6632 : (elf32_arm_local_got_tls_type
6637 /* Now determine the call target, its name, value,
6638 section. */
6646 {
6647 /* A non-relaxed TLS call. The target is the
6648 plt-resident trampoline and nothing to do
6649 with the symbol. */
6656 }
6658 {
6659 /* It's a local symbol. */
6663 {
6664 local_syms
6667 local_syms
6673 }
6682 else
6683 sym_sec =
6687 /* This is an undefined symbol. It can never
6688 be resolved. */
6697 branch_type =
6699 sym_name
6703 }
6704 else
6705 {
6706 /* It's an external symbol. */
6714 {
6721 /* For a destination in a shared library,
6722 use the PLT stub as target address to
6723 decide whether a branch stub is
6724 needed. */
6729 {
6733 destination = (sym_value
6736 }
6741 }
6744 {
6745 /* For a shared library, use the PLT stub as
6746 target address to decide whether a long
6747 branch stub is needed.
6748 For absolute code, they cannot be handled. */
6756 {
6760 destination = (sym_value
6763 }
6764 else
6766 }
6767 else
6768 {
6771 }
6773 branch_type =
6776 }
6778 do
6779 {
6783 /* Determine what (if any) linker stub is needed. */
6791 /* We've either created a stub for this reloc already,
6792 or we are about to. */
6793 stub_entry =
6804 else
6806 }
6809 /* Look for relocations which might trigger Cortex-A8
6810 erratum. */
6816 {
6822 {
6823 /* Found a candidate. Note we haven't checked the
6824 destination is within 4K here: if we do so (and
6825 don't create an entry in a8_relocs) we can't tell
6826 that a branch should have been relocated when
6827 scanning later. */
6829 {
6835 }
6845 num_a8_relocs++;
6846 }
6847 }
6848 }
6850 /* We're done with the internal relocs, free them. */
6853 }
6856 {
6857 /* Sort relocs which might apply to Cortex-A8 erratum. */
6862 /* Scan for branches which might trigger Cortex-A8 erratum. */
6869 }
6873 {
6876 else
6878 }
6879 }
6892 /* OK, we've added some stubs. Find out the new size of the
6893 stub sections. */
6897 {
6898 /* Ignore non-stub sections. */
6903 }
6905 /* Add new SG veneers after those already in the input import
6906 library. */
6908 stub_type++)
6909 {
6921 }
6923 /* Compute stub section size, considering padding. */
6926 stub_type++)
6927 {
6933 /* Skip if no stub input section or no stub section padding
6934 required. */
6937 /* Stub section padding required but no dedicated section. */
6943 }
6945 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6948 {
6955 stub_sec->size
6957 NULL);
6958 }
6961 /* Ask the linker to do its stuff. */
6964 }
6966 /* Add stubs for Cortex-A8 erratum fixes now. */
6968 {
6970 {
6983 {
6987 }
7006 }
7008 /* Stash the Cortex-A8 erratum fix array for use later in
7009 elf32_arm_write_section(). */
7012 }
7013 else
7014 {
7017 }
7019 }
7021 /* Build all the stubs associated with the current output file. The
7022 stubs are kept in a hash table attached to the main linker hash
7023 table. We also set up the .plt entries for statically linked PIC
7024 functions here. This function is called via arm_elf_finish in the
7025 linker. */
7027 bool
7029 {
7042 {
7043 bfd_size_type size;
7045 /* Ignore non-stub sections. */
7049 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7050 must at least be done for stub section requiring padding and for SG
7051 veneers to ensure that a non secure code branching to a removed SG
7052 veneer causes an error. */
7059 }
7061 /* Add new SG veneers after those already in the input import library. */
7063 {
7075 }
7077 /* Build the stubs as directed by the stub hash table. */
7081 {
7082 /* Place the cortex a8 stubs last. */
7085 }
7088 }
7090 /* Locate the Thumb encoded calling stub for NAME. */
7096 {
7101 /* We need a pointer to the armelf specific hash table. */
7113 hash = elf_link_hash_lookup
7117 {
7122 }
7127 }
7129 /* Locate the ARM encoded calling stub for NAME. */
7135 {
7140 /* We need a pointer to the elfarm specific hash table. */
7151 myh = elf_link_hash_lookup
7155 {
7160 }
7164 }
7166 /* ARM->Thumb glue (static images):
7168 .arm
7169 __func_from_arm:
7170 ldr r12, __func_addr
7171 bx r12
7172 __func_addr:
7173 .word func @ behave as if you saw a ARM_32 reloc.
7175 (v5t static images)
7176 .arm
7177 __func_from_arm:
7178 ldr pc, __func_addr
7179 __func_addr:
7180 .word func @ behave as if you saw a ARM_32 reloc.
7182 (relocatable images)
7183 .arm
7184 __func_from_arm:
7185 ldr r12, __func_offset
7186 add r12, r12, pc
7187 bx r12
7188 __func_offset:
7189 .word func - . */
7191 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7196 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7200 #define ARM2THUMB_PIC_GLUE_SIZE 16
7205 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7207 .thumb .thumb
7208 .align 2 .align 2
7209 __func_from_thumb: __func_from_thumb:
7210 bx pc push {r6, lr}
7211 nop ldr r6, __func_addr
7212 .arm mov lr, pc
7213 b func bx r6
7214 .arm
7215 ;; back_to_thumb
7216 ldmia r13! {r6, lr}
7217 bx lr
7218 __func_addr:
7219 .word func */
7221 #define THUMB2ARM_GLUE_SIZE 8
7226 #define VFP11_ERRATUM_VENEER_SIZE 8
7227 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7228 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7230 #define ARM_BX_VENEER_SIZE 12
7235 #ifndef ELFARM_NABI_C_INCLUDED
7236 static void
7238 {
7243 {
7244 /* Do not include empty glue sections in the output. */
7246 {
7250 }
7252 }
7263 }
7265 bool
7267 {
7275 ARM2THUMB_GLUE_SECTION_NAME);
7279 THUMB2ARM_GLUE_SECTION_NAME);
7283 VFP11_ERRATUM_VENEER_SECTION_NAME);
7287 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7291 ARM_BX_GLUE_SECTION_NAME);
7294 }
7296 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7297 returns the symbol identifying the stub. */
7302 {
7309 bfd_vma val;
7310 bfd_size_type size;
7316 s = bfd_get_linker_section
7327 myh = elf_link_hash_lookup
7331 {
7332 /* We've already seen this guy. */
7335 }
7337 /* The only trick here is using hash_table->arm_glue_size as the value.
7338 Even though the section isn't allocated yet, this is where we will be
7339 putting it. The +1 on the value marks that the stub has not been
7340 output yet - not that it is a Thumb function. */
7359 else
7366 }
7368 /* Allocate space for ARMv4 BX veneers. */
7370 static void
7372 {
7378 bfd_vma val;
7380 /* BX PC does not need a veneer. */
7388 /* Check if this veneer has already been allocated. */
7392 s = bfd_get_linker_section
7397 /* Add symbol for veneer. */
7404 myh = elf_link_hash_lookup
7422 }
7425 /* Add an entry to the code/data map for section SEC. */
7427 static void
7429 {
7434 {
7439 }
7444 {
7449 }
7452 {
7455 }
7456 }
7459 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7460 veneers are handled for now. */
7462 static bfd_vma
7468 {
7474 bfd_vma val;
7482 s = bfd_get_linker_section
7496 myh = elf_link_hash_lookup
7511 /* Link veneer back to calling location. */
7525 /* A symbol for the return from the veneer. */
7529 myh = elf_link_hash_lookup
7546 /* Generate a mapping symbol for the veneer section, and explicitly add an
7547 entry for that symbol to the code/data map for the section. */
7549 {
7551 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7552 ever requires this erratum fix. */
7562 /* The elf32_arm_init_maps function only cares about symbols from input
7563 BFDs. We must make a note of this generated mapping symbol
7564 ourselves so that code byteswapping works properly in
7565 elf32_arm_write_section. */
7567 }
7573 /* The offset of the veneer. */
7575 }
7577 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7578 veneers need to be handled because used only in Cortex-M. */
7580 static bfd_vma
7586 bfd_size_type veneer_size)
7587 {
7593 bfd_vma val;
7601 s = bfd_get_linker_section
7615 myh = elf_link_hash_lookup
7630 /* Link veneer back to calling location. */
7644 /* A symbol for the return from the veneer. */
7648 myh = elf_link_hash_lookup
7665 /* Generate a mapping symbol for the veneer section, and explicitly add an
7666 entry for that symbol to the code/data map for the section. */
7668 {
7670 /* Creates a THUMB symbol since there is no other choice. */
7680 /* The elf32_arm_init_maps function only cares about symbols from input
7681 BFDs. We must make a note of this generated mapping symbol
7682 ourselves so that code byteswapping works properly in
7683 elf32_arm_write_section. */
7685 }
7691 /* The offset of the veneer. */
7693 }
7695 #define ARM_GLUE_SECTION_FLAGS \
7696 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7697 | SEC_READONLY | SEC_LINKER_CREATED)
7699 /* Create a fake section for use by the ARM backend of the linker. */
7701 static bool
7703 {
7708 /* Already made. */
7717 /* Set the gc mark to prevent the section from being removed by garbage
7718 collection, despite the fact that no relocs refer to this section. */
7722 }
7724 /* Set size of .plt entries. This function is called from the
7725 linker scripts in ld/emultempl/{armelf}.em. */
7727 void
7729 {
7731 }
7733 /* Add the glue sections to ABFD. This function is called from the
7734 linker scripts in ld/emultempl/{armelf}.em. */
7736 bool
7739 {
7745 /* If we are only performing a partial
7746 link do not bother adding the glue. */
7758 return addglue
7760 }
7762 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7763 ensures they are not marked for deletion by
7764 strip_excluded_output_sections () when veneers are going to be created
7765 later. Not doing so would trigger assert on empty section size in
7766 lang_size_sections_1 (). */
7768 void
7770 {
7773 /* If we are only performing a partial
7774 link do not bother adding the glue. */
7779 {
7790 }
7791 }
7793 /* Select a BFD to be used to hold the sections used by the glue code.
7794 This function is called from the linker scripts in ld/emultempl/
7795 {armelf/pe}.em. */
7797 bool
7799 {
7802 /* If we are only performing a partial link
7803 do not bother getting a bfd to hold the glue. */
7807 /* Make sure we don't attach the glue sections to a dynamic object. */
7816 /* Save the bfd for later use. */
7820 }
7822 static void
7824 {
7828 Tag_CPU_arch);
7831 {
7834 }
7835 else
7836 {
7839 }
7840 }
7842 bool
7845 {
7854 /* If we are only performing a partial link do not bother
7855 to construct any glue. */
7859 /* Here we have a bfd that is to be included on the link. We have a
7860 hook to do reloc rummaging, before section sizes are nailed down. */
7867 {
7869 abfd);
7871 }
7873 /* PR 5398: If we have not decided to include any loadable sections in
7874 the output then we will not have a glue owner bfd. This is OK, it
7875 just means that there is nothing else for us to do here. */
7879 /* Rummage around all the relocs and map the glue vectors. */
7886 {
7896 /* Load the relocs. */
7897 internal_relocs
7905 {
7914 /* These are the only relocation types we care about. */
7919 /* Get the section contents if we haven't done so already. */
7921 {
7922 /* Get cached copy if it exists. */
7925 else
7926 {
7927 /* Go get them off disk. */
7930 }
7931 }
7934 {
7940 }
7942 /* If the relocation is not against a symbol it cannot concern us. */
7945 /* We don't care about local symbols. */
7949 /* This is an external symbol. */
7954 /* If the relocation is against a static symbol it must be within
7955 the current section and so cannot be a cross ARM/Thumb relocation. */
7959 /* If the call will go through a PLT entry then we do not need
7960 glue. */
7965 {
7967 /* This one is a call from arm code. We need to look up
7968 the target of the call. If it is a thumb target, we
7969 insert glue. */
7977 }
7978 }
7987 }
7991 error_return:
7998 }
7999 #endif
8002 /* Initialise maps of ARM/Thumb/data for input BFDs. */
8004 void
8006 {
8011 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8021 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8022 should contain the number of local symbols, which should come before any
8023 global symbols. Mapping symbols are always local. */
8025 NULL);
8027 /* No internal symbols read? Skip this BFD. */
8032 {
8039 {
8044 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8046 }
8047 }
8048 }
8051 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8052 say what they wanted. */
8054 void
8056 {
8064 {
8065 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8070 else
8072 }
8073 }
8076 void
8078 {
8084 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8086 {
8088 {
8095 /* Give a warning, but do as the user requests anyway. */
8098 }
8099 }
8101 /* For earlier architectures, we might need the workaround, but do not
8102 enable it by default. If users is running with broken hardware, they
8103 must enable the erratum fix explicitly. */
8105 }
8107 void
8109 {
8116 /* We assume only Cortex-M4 may require the fix. */
8119 {
8121 /* Give a warning, but do as the user requests anyway. */
8122 _bfd_error_handler
8125 }
8126 }
8128 enum bfd_arm_vfp11_pipe
8129 {
8130 VFP11_FMAC,
8131 VFP11_LS,
8132 VFP11_DS,
8133 VFP11_BAD
8134 };
8136 /* Return a VFP register number. This is encoded as RX:X for single-precision
8137 registers, or X:RX for double-precision registers, where RX is the group of
8138 four bits in the instruction encoding and X is the single extension bit.
8139 RX and X fields are specified using their lowest (starting) bit. The return
8140 value is:
8142 0...31: single-precision registers s0...s31
8143 32...63: double-precision registers d0...d31.
8145 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8146 encounter VFP3 instructions, so we allow the full range for DP registers. */
8148 static unsigned int
8151 {
8154 else
8156 }
8158 /* Set bits in *WMASK according to a register number REG as encoded by
8159 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8161 static void
8163 {
8168 }
8170 /* Return TRUE if WMASK overwrites anything in REGS. */
8172 static bool
8174 {
8178 {
8191 }
8194 }
8196 /* In this function, we're interested in two things: finding input registers
8197 for VFP data-processing instructions, and finding the set of registers which
8198 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8199 hold the written set, so FLDM etc. are easy to deal with (we're only
8200 interested in 32 SP registers or 16 dp registers, due to the VFP version
8201 implemented by the chip in question). DP registers are marked by setting
8202 both SP registers in the write mask). */
8204 static enum bfd_arm_vfp11_pipe
8207 {
8212 {
8222 {
8244 vfp_binop:
8252 {
8257 {
8271 /* These instructions will not bounce due to underflow. */
8277 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8278 registers to cause the erratum in previous instructions. */
8284 {
8289 /* Only FCVTSD can underflow. */
8296 }
8301 }
8302 }
8307 }
8308 }
8309 /* Two-register transfer. */
8311 {
8315 {
8318 else
8319 {
8322 }
8323 }
8326 }
8328 {
8333 {
8340 {
8348 }
8358 }
8361 }
8362 /* Single-register transfer. Note L==0. */
8364 {
8369 {
8372 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8373 destination register. I don't know if this is exactly right,
8374 but it is the conservative choice. */
8380 }
8383 }
8386 }
8392 /* Look for potentially-troublesome code sequences which might trigger the
8393 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8394 (available from ARM) for details of the erratum. A short version is
8395 described in ld.texinfo. */
8397 bool
8399 {
8410 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8411 The states transition as follows:
8413 0 -> 1 (vector) or 0 -> 2 (scalar)
8414 A VFP FMAC-pipeline instruction has been seen. Fill
8415 regs[0]..regs[numregs-1] with its input operands. Remember this
8416 instruction in 'first_fmac'.
8418 1 -> 2
8419 Any instruction, except for a VFP instruction which overwrites
8420 regs[*].
8422 1 -> 3 [ -> 0 ] or
8423 2 -> 3 [ -> 0 ]
8424 A VFP instruction has been seen which overwrites any of regs[*].
8425 We must make a veneer! Reset state to 0 before examining next
8426 instruction.
8428 2 -> 0
8429 If we fail to match anything in state 2, reset to state 0 and reset
8430 the instruction pointer to the instruction after 'first_fmac'.
8432 If the VFP11 vector mode is in use, there must be at least two unrelated
8433 instructions between anti-dependent VFP11 instructions to properly avoid
8434 triggering the erratum, hence the use of the extra state 1. */
8436 /* If we are only performing a partial link do not bother
8437 to construct any glue. */
8441 /* Skip if this bfd does not correspond to an ELF image. */
8445 /* We should have chosen a fix type by the time we get here. */
8451 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8456 {
8460 /* If we don't have executable progbits, we're not interested in this
8461 section. Also skip if section is to be excluded. */
8481 elf32_arm_compare_mapping);
8484 {
8490 /* FIXME: Only ARM mode is supported at present. We may need to
8491 support Thumb-2 mode also at some point. */
8496 {
8511 {
8515 /* I'm assuming the VFP11 erratum can trigger with denorm
8516 operands on either the FMAC or the DS pipeline. This might
8517 lead to slightly overenthusiastic veneer insertion. */
8519 {
8523 }
8527 {
8530 other_regs,
8534 numregs))
8536 else
8538 }
8542 {
8545 other_regs,
8549 numregs))
8551 else
8552 {
8555 }
8556 }
8561 }
8564 {
8573 {
8580 }
8583 first_fmac);
8591 }
8594 }
8595 }
8600 }
8604 error_return:
8609 }
8611 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8612 after sections have been laid out, using specially-named symbols. */
8614 void
8617 {
8625 /* Skip if this bfd does not correspond to an ELF image. */
8638 {
8643 {
8645 bfd_vma vma;
8648 {
8651 /* Find veneer symbol. */
8655 myh = elf_link_hash_lookup
8671 /* Find return location. */
8675 myh = elf_link_hash_lookup
8691 }
8692 }
8693 }
8696 }
8698 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8699 return locations after sections have been laid out, using
8700 specially-named symbols. */
8702 void
8705 {
8713 /* Skip if this bfd does not correspond to an ELF image. */
8726 {
8731 {
8733 bfd_vma vma;
8736 {
8738 /* Find veneer symbol. */
8742 myh = elf_link_hash_lookup
8757 /* Find return location. */
8761 myh = elf_link_hash_lookup
8777 }
8778 }
8779 }
8782 }
8786 {
8787 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8788 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8790 }
8794 {
8795 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8796 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8798 }
8802 {
8803 /* A6.5 Extension register load or store instruction
8804 A7.7.229
8805 We look for SP 32-bit and DP 64-bit registers.
8806 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8807 <list> is consecutive 64-bit registers
8808 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8809 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8810 <list> is consecutive 32-bit registers
8811 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8812 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8813 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8814 return
8819 /* (IA with !), includes VPOP (when reg number is SP). */
8821 /* (DB with !). */
8823 }
8825 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8826 VLDM opcode and:
8827 - computes the number and the mode of memory accesses
8828 - decides if the replacement should be done:
8829 . replaces only if > 8-word accesses
8830 . or (testing purposes only) replaces all accesses. */
8832 static bool
8834 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8835 {
8838 /* The field encoding the register list is the same for both LDMIA
8839 and LDMDB encodings. */
8845 /* DEFAULT mode accounts for the real bug condition situation,
8846 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8850 }
8852 /* Look for potentially-troublesome code sequences which might trigger
8853 the STM STM32L4XX erratum. */
8855 bool
8858 {
8866 /* If we are only performing a partial link do not bother
8867 to construct any glue. */
8871 /* Skip if this bfd does not correspond to an ELF image. */
8878 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8883 {
8887 /* If we don't have executable progbits, we're not interested in this
8888 section. Also skip if section is to be excluded. */
8908 elf32_arm_compare_mapping);
8911 {
8918 /* Only Thumb2 mode need be supported with this CM4 specific
8919 code, we should not encounter any arm mode eg span_type
8920 != 'a'. */
8925 {
8932 /* The first 16-bits of all 32-bit thumb2 instructions start
8933 with opcode[15..13]=0b111 and the encoded op1 can be anything
8934 except opcode[12..11]!=0b00.
8935 See 32-bit Thumb instruction encoding. */
8939 /* Compute the predicate that tells if the instruction
8940 is concerned by the IT block
8941 - Creates an error if there is a ldm that is not
8942 last in the IT block thus cannot be replaced
8943 - Otherwise we can create a branch at the end of the
8944 IT block, it will be controlled naturally by IT
8945 with the proper pseudo-predicate
8946 - So the only interesting predicate is the one that
8947 tells that we are not on the last item of an IT
8948 block. */
8953 {
8954 /* Load the rest of the insn (in manual-friendly order). */
8959 /* Veneers are created for (v)ldm depending on
8960 option flags and memory accesses conditions; but
8961 if the instruction is not the last instruction of
8962 an IT block, we cannot create a jump there, so we
8963 bail out. */
8965 && stm32l4xx_need_create_replacing_stub
8967 {
8969 {
8970 _bfd_error_handler
8971 /* xgettext:c-format */
8973 " in non-last IT block instruction:"
8974 " STM32L4XX veneer cannot be generated; "
8975 "use gcc option -mrestrict-it to generate"
8978 }
8979 else
8980 {
8983 bfd_zmalloc
8989 /* We create only thumb branches. */
8991 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8992 record_stm32l4xx_erratum_veneer
8994 i,
8995 is_ldm ?
8996 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8997 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9001 }
9002 }
9003 }
9004 else
9005 {
9006 /* A7.7.37 IT p208
9007 IT blocks are only encoded in T1
9008 Encoding T1: IT{x{y{z}}} <firstcond>
9009 1 0 1 1 - 1 1 1 1 - firstcond - mask
9010 if mask = '0000' then see 'related encodings'
9011 We don't deal with UNPREDICTABLE, just ignore these.
9012 There can be no nested IT blocks so an IT block
9013 is naturally a new one for which it is worth
9014 computing its size. */
9017 /* If we have a new IT block we compute its size. */
9019 {
9020 /* Compute the number of instructions controlled
9021 by the IT block, it will be used to decide
9022 whether we are inside an IT block or not. */
9025 }
9026 }
9029 }
9030 }
9035 }
9039 error_return:
9044 }
9046 /* Set target relocation values needed during linking. */
9048 void
9052 {
9068 else
9069 {
9072 }
9079 else
9091 }
9093 /* Replace the target offset of a Thumb bl or b.w instruction. */
9095 static void
9097 {
9098 bfd_vma upper;
9099 bfd_vma lower;
9116 }
9118 /* Thumb code calling an ARM function. */
9120 static int
9128 bfd_vma offset,
9129 bfd_signed_vma addend,
9130 bfd_vma val,
9132 {
9134 bfd_vma my_offset;
9150 THUMB2ARM_GLUE_SECTION_NAME);
9157 {
9161 {
9162 _bfd_error_handler
9168 }
9179 ret_offset =
9180 /* Address of destination of the stub. */
9183 /* Offset from the start of the current section
9184 to the start of the stubs. */
9186 /* Offset of the start of this stub from the start of the stubs. */
9187 + my_offset
9188 /* Address of the start of the current section. */
9190 /* The branch instruction is 4 bytes into the stub. */
9192 /* ARM branches work from the pc of the instruction + 8. */
9198 }
9202 /* Now go back and fix up the original BL insn to point to here. */
9203 ret_offset =
9204 /* Address of where the stub is located. */
9206 /* Address of where the BL is located. */
9209 /* Addend in the relocation. */
9210 - addend
9211 /* Biassing for PC-relative addressing. */
9217 }
9219 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9227 bfd_vma val,
9230 {
9231 bfd_vma my_offset;
9247 {
9251 {
9252 _bfd_error_handler
9256 }
9264 {
9265 /* For relocatable objects we can't use absolute addresses,
9266 so construct the address from a relative offset. */
9267 /* TODO: If the offset is small it's probably worth
9268 constructing the address with adds. */
9275 /* Adjust the offset by 4 for the position of the add,
9276 and 8 for the pipeline offset. */
9283 }
9285 {
9289 /* It's a thumb address. Add the low order bit. */
9292 }
9293 else
9294 {
9301 /* It's a thumb address. Add the low order bit. */
9306 }
9307 }
9312 }
9314 /* Arm code calling a Thumb function. */
9316 static int
9324 bfd_vma offset,
9325 bfd_signed_vma addend,
9326 bfd_vma val,
9328 {
9330 bfd_vma my_offset;
9341 ARM2THUMB_GLUE_SECTION_NAME);
9355 /* Somehow these are both 4 too far, so subtract 8. */
9357 + my_offset
9369 }
9371 /* Populate Arm stub for an exported Thumb function. */
9373 static bool
9375 {
9382 bfd_vma val;
9386 /* Allocate stubs for exported Thumb functions on v4t. */
9395 ARM2THUMB_GLUE_SECTION_NAME);
9413 }
9415 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9417 static bfd_vma
9419 {
9421 bfd_vma glue_addr;
9430 ARM_BX_GLUE_SECTION_NAME);
9440 {
9446 }
9449 }
9451 /* Generate Arm stubs for exported Thumb symbols. */
9452 static void
9455 {
9459 /* Ignore this if we are not called by the ELF backend linker. */
9466 /* If blx is available then exported Thumb symbols are OK and there is
9467 nothing to do. */
9472 link_info);
9473 }
9475 /* Reserve space for COUNT dynamic relocations in relocation selection
9476 SRELOC. */
9478 static void
9480 bfd_size_type count)
9481 {
9489 }
9491 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9492 dynamic, the relocations should go in SRELOC, otherwise they should
9493 go in the special .rel.iplt section. */
9495 static void
9497 bfd_size_type count)
9498 {
9504 else
9505 {
9508 }
9509 }
9511 /* Add relocation REL to the end of relocation section SRELOC. */
9513 static void
9516 {
9531 }
9533 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9534 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9535 to .plt. */
9537 static void
9542 {
9550 {
9554 /* NaCl uses a special first entry in .iplt too. */
9558 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9560 }
9561 else
9562 {
9567 {
9568 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9569 /* For lazy binding, relocations will be put into .rel.plt, in
9570 .rel.got otherwise. */
9571 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9574 else
9576 }
9577 else
9578 {
9579 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9581 }
9583 /* If this is the first .plt entry, make room for the special
9584 first entry. */
9589 }
9591 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9597 /* We also need to make an entry in the .got.plt section, which
9598 will be placed in the .got section by the linker script. */
9601 else
9604 /* Function descriptor takes 64 bits in GOT. */
9606 else
9608 }
9610 static bfd_vma
9612 {
9614 }
9616 static bfd_vma
9618 {
9620 }
9622 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9623 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9624 Otherwise, DYNINDX is the index of the symbol in the dynamic
9625 symbol table and SYM_VALUE is undefined.
9627 ROOT_PLT points to the offset of the PLT entry from the start of its
9628 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9629 bookkeeping information.
9631 Returns FALSE if there was a problem. */
9633 static bool
9638 {
9644 bfd_vma plt_index;
9645 Elf_Internal_Rela rel;
9646 bfd_vma got_header_size;
9650 /* Pick the appropriate sections and sizes. */
9652 {
9657 /* There are no reserved entries in .igot.plt, and no special
9658 first entry in .iplt. */
9660 }
9661 else
9662 {
9668 }
9677 /* Get the offset into the .(i)got.plt table of the entry that
9678 corresponds to this function. */
9681 /* Get the index in the procedure linkage table which
9682 corresponds to this symbol. This is the index of this symbol
9683 in all the symbols for which we are making plt entries.
9684 After the reserved .got.plt entries, all symbols appear in
9685 the same order as in .plt. */
9687 /* Function descriptor takes 8 bytes. */
9689 else
9692 /* Calculate the address of the GOT entry. */
9697 /* ...and the address of the PLT entry. */
9704 {
9706 bfd_vma val;
9709 {
9717 else
9719 }
9720 }
9722 {
9724 bfd_vma val;
9727 {
9737 else
9739 }
9744 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9745 referencing the GOT for this PLT entry. */
9752 /* Create the R_ARM_ABS32 relocation referencing the
9753 beginning of the PLT for this GOT entry. */
9758 }
9760 {
9761 /* Calculate the displacement between the PLT slot and the
9762 common tail that's part of the special initial PLT slot. */
9763 int32_t tail_displacement
9773 /* Calculate the displacement between the PLT slot and the entry
9774 in the GOT. The offset accounts for the value produced by
9775 adding to pc in the penultimate instruction of the PLT stub. */
9776 got_displacement = (got_address
9779 /* NaCl does not support interworking at all. */
9797 }
9799 {
9801 ? elf32_arm_fdpic_thumb_plt_entry
9804 /* Fill-up Thumb stub if needed. */
9806 {
9811 }
9812 /* As we are using 32 bit instructions even for the Thumb
9813 version, we have to use 'put_arm_insn' instead of
9814 'put_thumb_insn'. */
9822 {
9823 /* funcdesc_value_reloc_offset. */
9831 }
9832 }
9834 {
9835 /* PR ld/16017: Generate thumb only PLT entries. */
9837 {
9838 /* FIXME: We ought to be able to generate thumb-1 PLT
9839 instructions... */
9841 output_bfd);
9843 }
9845 /* Calculate the displacement between the PLT slot and the entry in
9846 the GOT. The 12-byte offset accounts for the value produced by
9847 adding to pc in the 3rd instruction of the PLT stub. */
9850 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9851 instead of 'put_thumb_insn'. */
9872 }
9873 else
9874 {
9875 /* Calculate the displacement between the PLT slot and the
9876 entry in the GOT. The eight-byte offset accounts for the
9877 value produced by adding to pc in the first instruction
9878 of the PLT stub. */
9882 {
9887 }
9890 {
9905 #ifdef FOUR_WORD_PLT
9907 #endif
9908 }
9909 else
9910 {
9927 }
9928 }
9930 /* Fill in the entry in the .rel(a).(i)plt section. */
9934 {
9935 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9936 The dynamic linker or static executable then calls SYM_VALUE
9937 to determine the correct run-time value of the .igot.plt entry. */
9940 }
9941 else
9942 {
9943 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9944 used by PLT entry. */
9946 {
9949 }
9950 else
9951 {
9956 /* PR ld/16017
9957 When thumb only we need to set the LSB for any address that
9958 will be used with an interworking branch instruction. */
9961 }
9962 }
9964 /* Fill in the entry in the global offset table. */
9969 {
9970 /* Setup initial funcdesc value. */
9971 /* FIXME: we don't support lazy binding because there is a
9972 race condition between both words getting written and
9973 some other thread attempting to read them. The ARM
9974 architecture does not have an atomic 64 bit load/store
9975 instruction that could be used to prevent it; it is
9976 recommended that threaded FDPIC applications run with the
9977 LD_BIND_NOW environment variable set. */
9982 }
9986 else
9987 {
9989 {
9990 /* For FDPIC we put PLT relocationss into .rel.got when not
9991 lazy binding otherwise we put them in .rel.plt. For now,
9992 we don't support lazy binding so put it in .rel.got. */
9995 else
9997 }
9998 else
9999 {
10002 }
10003 }
10006 }
10008 /* Some relocations map to different relocations depending on the
10009 target. Return the real relocation. */
10011 static int
10014 {
10016 {
10020 else
10028 }
10029 }
10031 /* Return the base VMA address which should be subtracted from real addresses
10032 when resolving @dtpoff relocation.
10033 This is PT_TLS segment p_vaddr. */
10035 static bfd_vma
10037 {
10038 /* If tls_sec is NULL, we should have signalled an error already. */
10042 }
10044 /* Return the relocation value for @tpoff relocation
10045 if STT_TLS virtual address is ADDRESS. */
10047 static bfd_vma
10049 {
10051 bfd_vma base;
10053 /* If tls_sec is NULL, we should have signalled an error already. */
10058 }
10060 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10061 VALUE is the relocation value. */
10063 static bfd_reloc_status_type
10065 {
10072 }
10074 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10075 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10076 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10078 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10079 is to then call final_link_relocate. Return other values in the
10080 case of error.
10082 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10083 the pre-relaxed code. It would be nice if the relocs were updated
10084 to match the optimization. */
10086 static bfd_reloc_status_type
10090 {
10094 {
10101 else
10102 {
10106 else
10108 }
10113 /* Thumb insn. */
10116 {
10118 /* nop */
10120 }
10122 {
10124 /* nop */
10126 else
10127 /* ldr rx,[ry] */
10129 }
10131 {
10133 /* nop */
10135 else
10136 /* mov r0, rx */
10139 }
10140 else
10141 {
10143 /* It's a 32 bit instruction, fetch the rest of it for
10144 error generation. */
10147 _bfd_error_handler
10148 /* xgettext:c-format */
10154 }
10158 /* arm insn. */
10161 {
10163 /* mov rx, ry */
10166 }
10168 {
10170 /* nop */
10172 else
10173 /* ldr rx,[ry] */
10176 }
10178 {
10180 /* nop */
10182 else
10183 /* mov r0, rx */
10186 }
10187 else
10188 {
10189 _bfd_error_handler
10190 /* xgettext:c-format */
10196 }
10200 /* GD->IE relaxation, turn the instruction into 'nop' or
10201 'ldr r0, [pc,r0]' */
10207 /* GD->IE relaxation. */
10209 /* add r0,pc; ldr r0, [r0] */
10212 /* nop.w */
10214 else
10215 /* nop; nop */
10221 }
10223 }
10225 /* For a given value of n, calculate the value of G_n as required to
10226 deal with group relocations. We return it in the form of an
10227 encoded constant-and-rotation, together with the final residual. If n is
10228 specified as less than zero, then final_residual is filled with the
10229 input value and no further action is performed. */
10231 static bfd_vma
10233 {
10235 bfd_vma g_n;
10240 {
10243 /* Calculate which part of the value to mask. */
10246 else
10247 {
10250 /* Determine the most significant bit in the residual and
10251 align the resulting value to a 2-bit boundary. */
10256 /* The desired shift is now (msb - 6), or zero, whichever
10257 is the greater. */
10261 }
10263 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10268 /* Calculate the residual for the next time around. */
10270 }
10275 }
10277 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10278 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10280 static int
10282 {
10292 }
10294 /* Perform a relocation as part of a final link. */
10296 static bfd_reloc_status_type
10303 bfd_vma value,
10312 {
10322 bfd_vma addend;
10323 bfd_signed_vma signed_addend;
10325 bfd_vma dynreloc_value;
10330 bfd_vma plt_offset;
10331 bfd_vma gotplt_offset;
10342 /* Some relocation types map to different relocations depending on the
10343 target. We pick the right one here. */
10346 /* It is possible to have linker relaxations on some TLS access
10347 models. Update our information here. */
10360 else
10366 {
10367 bfd_vma sign;
10370 {
10375 }
10376 /* Note: the addend and signed_addend calculated here are
10377 incorrect for any split field. */
10383 }
10384 else
10387 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10388 are resolving a function call relocation. */
10395 /* Record the symbol information that should be used in dynamic
10396 relocations. */
10402 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10403 VALUE appropriately for relocations that we resolve at link time. */
10408 {
10413 {
10417 /* Populate .iplt entries here, because not all of them will
10418 be seen by finish_dynamic_symbol. The lower bit is set if
10419 we have already populated the entry. */
10421 plt_offset--;
10422 else
10423 {
10427 else
10429 }
10431 /* Static relocations always resolve to the .iplt entry. */
10438 /* If there are non-call relocations that resolve to the .iplt
10439 entry, then all dynamic ones must too. */
10441 {
10444 }
10445 }
10446 else
10447 /* We populate the .plt entry in finish_dynamic_symbol. */
10449 }
10450 else
10451 {
10455 }
10461 {
10463 /* We don't need to find a value for this symbol. It's just a
10464 marker. */
10471 /* Fall through. */
10483 /* Handle relocations which should use the PLT entry. ABS32/REL32
10484 will use the symbol's value, which may point to a PLT entry, but we
10485 don't need to handle that here. If we created a PLT entry, all
10486 branches in this object should go to it, except if the PLT is too
10487 far away, in which case a long branch stub should be inserted. */
10494 {
10495 /* If we've created a .plt section, and assigned a PLT entry
10496 to this function, it must either be a STT_GNU_IFUNC reference
10497 or not be known to bind locally. In other cases, we should
10498 have cleared the PLT entry by now. */
10508 }
10510 /* When generating a shared object or relocatable executable, these
10511 relocations are copied into the output file to be resolved at
10512 run time. */
10533 {
10534 Elf_Internal_Rela outrel;
10540 {
10546 _bfd_error_handler
10551 }
10556 {
10562 }
10587 else
10588 {
10591 /* This symbol is local, or marked to become local. */
10594 /* On SVR4-ish systems, the dynamic loader cannot
10595 relocate the text and data segments independently,
10596 so the symbol does not matter. */
10599 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10600 to the .iplt entry. Instead, every non-call reference
10601 must use an R_ARM_IRELATIVE relocation to obtain the
10602 correct run-time address. */
10606 else
10610 else
10612 }
10616 else
10619 /* If this reloc is against an external symbol, we do not want to
10620 fiddle with the addend. Otherwise, we need to include the symbol
10621 value so that it becomes an addend for the dynamic reloc. */
10628 }
10630 {
10639 {
10643 {
10644 /* Check for Arm calling Arm function. */
10645 /* FIXME: Should we translate the instruction into a BL
10646 instruction instead ? */
10648 _bfd_error_handler
10653 }
10655 {
10656 /* Check for Arm calling Thumb function. */
10658 {
10663 error_message))
10665 else
10667 }
10668 }
10670 /* Check if a stub has to be inserted because the
10671 destination is too far or we are changing mode. */
10675 {
10686 {
10687 /* The target is out of reach, so redirect the
10688 branch to the local stub for this function. */
10692 stub_type);
10693 {
10701 }
10702 }
10703 else
10704 {
10705 /* If the call goes through a PLT entry, make sure to
10706 check distance to the right destination address. */
10708 {
10713 /* The PLT entry is in ARM mode, regardless of the
10714 target function. */
10716 }
10717 }
10718 }
10720 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10721 where:
10722 S is the address of the symbol in the relocation.
10723 P is address of the instruction being relocated.
10724 A is the addend (extracted from the instruction) in bytes.
10726 S is held in 'value'.
10727 P is the base address of the section containing the
10728 instruction plus the offset of the reloc into that
10729 section, ie:
10730 (input_section->output_section->vma +
10731 input_section->output_offset +
10732 rel->r_offset).
10733 A is the addend, converted into bytes, ie:
10734 (signed_addend * 4)
10736 Note: None of these operations have knowledge of the pipeline
10737 size of the processor, thus it is up to the assembler to
10738 encode this information into the addend. */
10747 /* A branch to an undefined weak symbol is turned into a jump to
10748 the next instruction unless a PLT entry will be created.
10749 Do the same for local undefined symbols (but not for STN_UNDEF).
10750 The jump to the next instruction is optimized as a NOP depending
10751 on the architecture. */
10755 {
10760 else
10762 }
10763 else
10764 {
10765 /* Perform a signed range check. */
10776 {
10777 /* Set the H bit in the BLX instruction. */
10779 {
10782 else
10784 }
10786 /* Select the correct instruction (BL or BLX). */
10787 /* Only if we are not handling a BL to a stub. In this
10788 case, mode switching is performed by the stub. */
10792 {
10795 }
10796 }
10797 }
10798 }
10830 {
10831 /* Check for overflow. */
10834 }
10840 }
10848 /* There is no way to tell whether the user intended to use a signed or
10849 unsigned addend. When checking for overflow we accept either,
10850 as specified by the AAELF. */
10860 /* See comment for R_ARM_ABS8. */
10868 /* Support ldr and str instructions for the thumb. */
10870 {
10871 /* Need to refetch addend. */
10873 /* ??? Need to determine shift amount from operand size. */
10875 }
10878 /* ??? Isn't value unsigned? */
10882 /* ??? Value needs to be properly shifted into place first. */
10888 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10889 {
10890 bfd_vma insn;
10891 bfd_signed_vma relocation;
10897 {
10902 }
10909 /* PR 21523: Use an absolute value. The user of this reloc will
10910 have already selected an ADD or SUB insn appropriately. */
10916 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10930 }
10933 /* PR 10073: This reloc is not generated by the GNU toolchain,
10934 but it is supported for compatibility with third party libraries
10935 generated by other compilers, specifically the ARM/IAR. */
10936 {
10937 bfd_vma insn;
10938 bfd_signed_vma relocation;
10952 /* We do not check for overflow of this reloc. Although strictly
10953 speaking this is incorrect, it appears to be necessary in order
10954 to work with IAR generated relocs. Since GCC and GAS do not
10955 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10956 a problem for them. */
10964 }
10967 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10968 {
10969 bfd_vma insn;
10970 bfd_signed_vma relocation;
10976 {
10980 }
11000 }
11005 /* Thumb BL (branch long instruction). */
11006 {
11007 bfd_vma relocation;
11008 bfd_vma reloc_sign;
11012 bfd_signed_vma reloc_signed_max;
11013 bfd_signed_vma reloc_signed_min;
11014 bfd_vma check;
11015 bfd_signed_vma signed_check;
11020 /* A branch to an undefined weak symbol is turned into a jump to
11021 the next instruction unless a PLT entry will be created.
11022 The jump to the next instruction is optimized as a NOP.W for
11023 Thumb-2 enabled architectures. */
11026 {
11028 {
11031 }
11032 else
11033 {
11036 }
11038 }
11040 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11041 with Thumb-1) involving the J1 and J2 bits. */
11043 {
11053 /* Sign extend. */
11057 }
11060 {
11061 /* Check for Thumb to Thumb call. */
11062 /* FIXME: Should we translate the instruction into a BL
11063 instruction instead ? */
11065 _bfd_error_handler
11070 }
11071 else
11072 {
11073 /* If it is not a call to Thumb, assume call to Arm.
11074 If it is a call relative to a section name, then it is not a
11075 function call at all, but rather a long jump. Calls through
11076 the PLT do not require stubs. */
11078 {
11080 {
11081 /* Convert BL to BLX. */
11083 }
11086 {
11090 error_message))
11092 else
11094 }
11095 }
11099 {
11100 /* Make sure this is a BL. */
11102 }
11103 }
11107 {
11108 /* Check if a stub has to be inserted because the destination
11109 is too far. */
11121 {
11122 /* The target is out of reach or we are changing modes, so
11123 redirect the branch to the local stub for this
11124 function. */
11128 stub_type);
11130 {
11137 }
11139 /* If this call becomes a call to Arm, force BLX. */
11141 {
11146 }
11147 }
11148 }
11150 /* Handle calls via the PLT. */
11152 {
11160 {
11161 /* If the Thumb BLX instruction is available, convert
11162 the BL to a BLX instruction to call the ARM-mode
11163 PLT entry. */
11166 }
11167 else
11168 {
11170 /* Target the Thumb stub before the ARM PLT entry. */
11173 }
11175 }
11185 /* If this is a signed value, the rightshift just dropped
11186 leading 1 bits (assuming twos complement). */
11189 else
11192 /* Calculate the permissable maximum and minimum values for
11193 this relocation according to whether we're relocating for
11194 Thumb-2 or not. */
11201 /* Assumes two's complement. */
11206 /* For a BLX instruction, make sure that the relocation is rounded up
11207 to a word boundary. This follows the semantics of the instruction
11208 which specifies that bit 1 of the target address will come from bit
11209 1 of the base address. */
11212 /* Put RELOCATION back into the insn. Assumes two's complement.
11213 We use the Thumb-2 encoding, which is safe even if dealing with
11214 a Thumb-1 instruction by virtue of our overflow check above. */
11224 /* Put the relocated value back in the object file: */
11229 }
11233 /* Thumb32 conditional branch instruction. */
11234 {
11235 bfd_vma relocation;
11241 bfd_signed_vma signed_check;
11246 /* Need to refetch the addend, reconstruct the top three bits,
11247 and squish the two 11 bit pieces together. */
11249 {
11263 }
11265 /* Handle calls via the PLT. */
11267 {
11271 /* Target the Thumb stub before the ARM PLT entry. */
11274 }
11283 {
11287 stub_type);
11289 {
11293 }
11294 }
11305 /* Put RELOCATION back into the insn. */
11306 {
11315 }
11317 /* Put the relocated value back in the object file: */
11322 }
11327 /* Thumb B (branch) instruction). */
11328 {
11329 bfd_signed_vma relocation;
11332 bfd_signed_vma signed_check;
11334 /* CZB cannot jump backward. */
11336 {
11340 }
11353 else
11359 /* Assumes two's complement. */
11364 }
11369 {
11370 bfd_vma insn;
11371 bfd_vma relocation;
11375 {
11376 /* Extract the addend. */
11379 }
11389 }
11397 /* Relocation is relative to the start of the
11398 global offset table. */
11404 /* If we are addressing a Thumb function, we need to adjust the
11405 address by one, so that attempts to call the function pointer will
11406 correctly interpret it as Thumb code. */
11410 /* Note that sgot->output_offset is not involved in this
11411 calculation. We always want the start of .got. If we
11412 define _GLOBAL_OFFSET_TABLE in a different way, as is
11413 permitted by the ABI, we might have to change this
11414 calculation. */
11421 /* Use global offset table as symbol value. */
11435 /* Relocation is to the entry for this symbol in the
11436 global offset table. */
11443 {
11444 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11445 symbol, and the relocation resolves directly to the runtime
11446 target rather than to the .iplt entry. This means that any
11447 .got entry would be the same value as the .igot.plt entry,
11448 so there's no point creating both. */
11451 }
11453 {
11454 bfd_vma off;
11459 {
11460 /* We have already processsed one GOT relocation against
11461 this symbol. */
11466 }
11467 else
11468 {
11469 Elf_Internal_Rela outrel;
11474 {
11475 /* If the symbol doesn't resolve locally in a static
11476 object, we have an undefined reference. If the
11477 symbol doesn't resolve locally in a dynamic object,
11478 it should be resolved by the dynamic linker. */
11480 {
11483 }
11484 else
11487 }
11488 else
11489 {
11495 else
11496 {
11500 }
11502 }
11504 /* The GOT entry is initialized to zero by default.
11505 See if we should install a different value. */
11508 {
11512 }
11521 {
11526 }
11529 }
11531 }
11532 else
11533 {
11534 bfd_vma off;
11541 /* The offset must always be a multiple of 4. We use the
11542 least significant bit to record whether we have already
11543 generated the necessary reloc. */
11546 else
11547 {
11548 Elf_Internal_Rela outrel;
11555 else
11556 {
11560 }
11562 /* The GOT entry is initialized to zero by default.
11563 See if we should install a different value. */
11574 {
11580 }
11583 }
11586 }
11603 {
11604 bfd_vma off;
11613 else
11614 {
11615 /* If we don't know the module number, create a relocation
11616 for it. */
11618 {
11619 Elf_Internal_Rela outrel;
11634 }
11635 else
11639 }
11642 {
11648 }
11649 else
11650 {
11658 }
11659 }
11670 {
11678 {
11683 h)
11686 {
11689 }
11693 }
11694 else
11695 {
11699 {
11702 input_bfd,
11704 r_symndx);
11706 }
11710 }
11712 /* Linker relaxations happens from one of the
11713 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11721 else
11722 {
11724 Elf_Internal_Rela outrel;
11727 /* The GOT entries have not been initialized yet. Do it
11728 now, and emit any relocations. If both an IE GOT and a
11729 GD GOT are necessary, we emit the GD first. */
11736 {
11739 }
11742 {
11745 /* We should have relaxed, unless this is an undefined
11746 weak symbol. */
11755 + offplt
11767 /* For globals, the first word in the relocation gets
11768 the relocation index and the top bit set, or zero,
11769 if we're binding now. For locals, it gets the
11770 symbol's offset in the tls section. */
11778 /* Second word in the relocation is always zero. */
11782 }
11784 {
11786 {
11802 else
11803 {
11806 R_ARM_TLS_DTPOFF32);
11815 }
11816 }
11817 else
11818 {
11819 /* If we are not emitting relocations for a
11820 general dynamic reference, then we must be in a
11821 static link or an executable link with the
11822 symbol binding locally. Mark it as belonging
11823 to module 1, the executable. */
11828 }
11831 }
11834 {
11836 {
11839 else
11851 }
11852 else
11856 }
11860 else
11862 }
11871 {
11872 bfd_signed_vma offset;
11873 /* TLS stubs are arm mode. The original symbol is a
11874 data object, so branch_type is bogus. */
11876 enum elf32_arm_stub_type stub_type
11884 {
11886 = elf32_arm_get_stub_entry
11892 }
11893 else
11899 {
11909 }
11910 else
11911 {
11912 /* Thumb blx encodes the offset in a complicated
11913 fashion. */
11923 {
11925 }
11926 else
11927 {
11929 /* Round up the offset to a word boundary. */
11931 }
11943 }
11944 }
11945 /* These relocations needs special care, as besides the fact
11946 they point somewhere in .gotplt, the addend must be
11947 adjusted accordingly depending on the type of instruction
11948 we refer to. */
11950 {
11959 {
11966 /* bl/blx */
11969 /* add */
11971 else
11972 {
11973 _bfd_error_handler
11974 /* xgettext:c-format */
11976 "unexpected %s instruction '%#lx' "
11981 }
11982 }
11983 else
11984 {
11988 {
11999 _bfd_error_handler
12000 /* xgettext:c-format */
12002 "unexpected %s instruction '%#lx' "
12007 }
12008 }
12016 }
12017 else
12025 {
12026 /* For FDPIC relocations, resolve to the offset of the GOT
12027 entry from the start of GOT. */
12033 }
12034 else
12035 {
12039 }
12040 }
12044 {
12045 _bfd_error_handler
12046 /* xgettext:c-format */
12051 }
12052 else
12061 {
12064 /* Ensure that we have a BX instruction. */
12068 {
12069 /* Branch to veneer. */
12070 bfd_vma glue_addr;
12077 }
12078 else
12079 {
12080 /* Preserve Rm (lowest four bits) and the condition code
12081 (highest four bits). Other bits encode MOV PC,Rm. */
12083 }
12086 }
12093 /* Until we properly support segment-base-relative addressing then
12094 we assume the segment base to be zero, as for the group relocations.
12095 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12096 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12100 {
12104 {
12107 }
12129 }
12136 /* Until we properly support segment-base-relative addressing then
12137 we assume the segment base to be zero, as for the above relocations.
12138 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12139 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12140 as R_ARM_THM_MOVT_ABS. */
12144 {
12145 bfd_vma insn;
12151 {
12157 }
12183 }
12196 {
12200 /* sb is the origin of the *segment* containing the symbol. */
12202 bfd_vma residual;
12203 bfd_vma g_n;
12204 bfd_signed_vma signed_value;
12207 /* Determine which group of bits to select. */
12209 {
12231 }
12233 /* If REL, extract the addend from the insn. If RELA, it will
12234 have already been fetched for us. */
12236 {
12243 else
12244 {
12245 /* Compensate for the fact that in the instruction, the
12246 rotation is stored in multiples of 2 bits. */
12249 /* Rotate "constant" right by "rotation" bits. */
12252 }
12254 /* Determine if the instruction is an ADD or a SUB.
12255 (For REL, this determines the sign of the addend.) */
12258 {
12259 _bfd_error_handler
12260 /* xgettext:c-format */
12265 }
12268 }
12270 /* Compute the value (X) to go in the place. */
12276 /* PC relative. */
12278 else
12279 /* Section base relative. */
12282 /* If the target symbol is a Thumb function, then set the
12283 Thumb bit in the address. */
12287 /* Calculate the value of the relevant G_n, in encoded
12288 constant-with-rotation format. */
12292 /* Check for overflow if required. */
12299 {
12300 _bfd_error_handler
12301 /* xgettext:c-format */
12308 }
12310 /* Mask out the value and the ADD/SUB part of the opcode; take care
12311 not to destroy the S bit. */
12314 /* Set the opcode according to whether the value to go in the
12315 place is negative. */
12318 else
12321 /* Encode the offset. */
12325 }
12334 {
12338 /* sb is the origin of the *segment* containing the symbol. */
12340 bfd_vma residual;
12341 bfd_signed_vma signed_value;
12344 /* Determine which groups of bits to calculate. */
12346 {
12364 }
12366 /* If REL, extract the addend from the insn. If RELA, it will
12367 have already been fetched for us. */
12369 {
12372 }
12374 /* Compute the value (X) to go in the place. */
12378 /* PC relative. */
12380 else
12381 /* Section base relative. */
12384 /* Calculate the value of the relevant G_{n-1} to obtain
12385 the residual at that stage. */
12389 /* Check for overflow. */
12391 {
12392 _bfd_error_handler
12393 /* xgettext:c-format */
12400 }
12402 /* Mask out the value and U bit. */
12405 /* Set the U bit if the value to go in the place is non-negative. */
12409 /* Encode the offset. */
12413 }
12422 {
12426 /* sb is the origin of the *segment* containing the symbol. */
12428 bfd_vma residual;
12429 bfd_signed_vma signed_value;
12432 /* Determine which groups of bits to calculate. */
12434 {
12452 }
12454 /* If REL, extract the addend from the insn. If RELA, it will
12455 have already been fetched for us. */
12457 {
12460 }
12462 /* Compute the value (X) to go in the place. */
12466 /* PC relative. */
12468 else
12469 /* Section base relative. */
12472 /* Calculate the value of the relevant G_{n-1} to obtain
12473 the residual at that stage. */
12477 /* Check for overflow. */
12479 {
12480 _bfd_error_handler
12481 /* xgettext:c-format */
12488 }
12490 /* Mask out the value and U bit. */
12493 /* Set the U bit if the value to go in the place is non-negative. */
12497 /* Encode the offset. */
12501 }
12510 {
12514 /* sb is the origin of the *segment* containing the symbol. */
12516 bfd_vma residual;
12517 bfd_signed_vma signed_value;
12520 /* Determine which groups of bits to calculate. */
12522 {
12540 }
12542 /* If REL, extract the addend from the insn. If RELA, it will
12543 have already been fetched for us. */
12545 {
12548 }
12550 /* Compute the value (X) to go in the place. */
12554 /* PC relative. */
12556 else
12557 /* Section base relative. */
12560 /* Calculate the value of the relevant G_{n-1} to obtain
12561 the residual at that stage. */
12565 /* Check for overflow. (The absolute value to go in the place must be
12566 divisible by four and, after having been divided by four, must
12567 fit in eight bits.) */
12569 {
12570 _bfd_error_handler
12571 /* xgettext:c-format */
12578 }
12580 /* Mask out the value and U bit. */
12583 /* Set the U bit if the value to go in the place is non-negative. */
12587 /* Encode the offset. */
12591 }
12598 {
12604 /* Compute address. */
12610 /* Clean imm8 insn. */
12612 /* And update with correct part of address. */
12614 /* Update insn. */
12616 }
12622 {
12624 {
12629 {
12632 }
12639 {
12642 }
12644 /* Resolve relocation. */
12647 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12648 not done yet. */
12652 }
12653 else
12654 {
12657 bfd_vma addr;
12660 /* For static binaries, sym_sec can be null. */
12662 {
12665 }
12666 else
12667 {
12670 }
12673 {
12676 }
12678 /* This case cannot occur since funcdesc is allocated by
12679 the dynamic loader so we cannot resolve the relocation. */
12681 {
12684 }
12686 /* Resolve relocation. */
12689 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12693 }
12694 }
12699 {
12701 {
12702 Elf_Internal_Rela outrel;
12704 /* Resolve relocation. */
12708 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12710 {
12713 bfd_vma addr;
12716 /* For static binaries sym_sec can be null. */
12718 {
12721 }
12722 else
12723 {
12726 }
12728 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12732 }
12734 /* Add a dynamic relocation on GOT entry if not already done. */
12736 {
12738 {
12743 else
12747 sgot->contents
12749 }
12750 else
12751 {
12753 }
12761 else
12764 else
12767 }
12768 }
12769 else
12770 {
12771 /* Such relocation on static function should not have been
12772 emitted by the compiler. */
12774 }
12775 }
12780 {
12782 {
12784 Elf_Internal_Rela outrel;
12788 {
12791 }
12798 {
12801 }
12803 /* Replace static FUNCDESC relocation with a
12804 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12805 executable. */
12812 else
12818 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12822 }
12823 else
12824 {
12826 {
12829 bfd_vma addr;
12831 Elf_Internal_Rela outrel;
12833 /* For static binaries sym_sec can be null. */
12835 {
12838 }
12839 else
12840 {
12843 }
12848 /* Replace static FUNCDESC relocation with a
12849 R_ARM_RELATIVE dynamic relocation. */
12856 else
12862 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12866 }
12867 else
12868 {
12869 Elf_Internal_Rela outrel;
12871 /* Add a dynamic relocation. */
12877 }
12878 }
12879 }
12884 {
12885 bfd_vma relocation;
12890 {
12898 /* Sign extend. */
12900 }
12907 /* Put RELOCATION back into the insn. */
12908 {
12915 }
12917 /* Put the relocated value back in the object file: */
12922 }
12925 {
12926 bfd_vma relocation;
12931 {
12939 /* Sign extend. */
12942 }
12949 /* Put RELOCATION back into the insn. */
12950 {
12957 }
12959 /* Put the relocated value back in the object file: */
12964 }
12967 {
12968 bfd_vma relocation;
12973 {
12981 /* Sign extend. */
12984 }
12991 /* Put RELOCATION back into the insn. */
12992 {
12999 }
13001 /* Put the relocated value back in the object file: */
13006 }
13010 }
13011 }
13013 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13014 static void
13018 bfd_signed_vma increment)
13019 {
13020 bfd_signed_vma addend;
13024 {
13042 }
13043 else
13044 {
13045 bfd_vma contents;
13049 /* Get the (signed) value from the instruction. */
13052 {
13053 bfd_signed_vma mask;
13058 }
13060 /* Add in the increment, (which is a byte value). */
13062 {
13074 /* Should we check for overflow here ? */
13076 /* Drop any undesired bits. */
13079 }
13084 }
13085 }
13087 #define IS_ARM_TLS_RELOC(R_TYPE) \
13088 ((R_TYPE) == R_ARM_TLS_GD32 \
13089 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13090 || (R_TYPE) == R_ARM_TLS_LDO32 \
13091 || (R_TYPE) == R_ARM_TLS_LDM32 \
13092 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13093 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13094 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13095 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13096 || (R_TYPE) == R_ARM_TLS_LE32 \
13097 || (R_TYPE) == R_ARM_TLS_IE32 \
13098 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13099 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13101 /* Specific set of relocations for the gnu tls dialect. */
13102 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13103 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13104 || (R_TYPE) == R_ARM_TLS_CALL \
13105 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13106 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13107 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13109 /* Relocate an ARM ELF section. */
13111 static int
13120 {
13138 {
13145 bfd_vma relocation;
13146 bfd_reloc_status_type r;
13147 arelent bfd_reloc;
13170 {
13175 /* An object file might have a reference to a local
13176 undefined symbol. This is a daft object file, but we
13177 should at least do something about it. V4BX & NONE
13178 relocations do not use the symbol and are explicitly
13179 allowed to use the undefined symbol, so allow those.
13180 Likewise for relocations against STN_UNDEF. */
13193 {
13200 {
13205 {
13227 {
13228 _bfd_error_handler
13229 /* xgettext:c-format */
13235 }
13239 /* Get the (signed) value from the instruction. */
13242 {
13243 bfd_signed_vma mask;
13248 }
13250 }
13253 addend =
13258 /* Cases here must match those in the preceding
13259 switch statement. */
13261 {
13284 }
13285 }
13286 }
13287 else
13289 }
13290 else
13291 {
13300 }
13307 {
13308 /* This is a relocatable link. We don't have to change
13309 anything, unless the reloc is against a section symbol,
13310 in which case we have to adjust according to where the
13311 section symbol winds up in the output section. */
13313 {
13317 else
13319 }
13321 }
13325 else
13326 {
13327 name = (bfd_elf_string_from_elf_section
13331 }
13339 {
13340 _bfd_error_handler
13342 /* xgettext:c-format */
13344 /* xgettext:c-format */
13346 input_bfd,
13347 input_section,
13350 name);
13351 }
13353 /* We call elf32_arm_final_link_relocate unless we're completely
13354 done, i.e., the relaxation produced the final output we want,
13355 and we won't let anybody mess with it. Also, we have to do
13356 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13357 both in relaxed and non-relaxed cases. */
13363 {
13366 /* This may have been marked unresolved because it came from
13367 a shared library. But we've just dealt with that. */
13369 }
13370 else
13374 {
13385 }
13387 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13388 because such sections are not SEC_ALLOC and thus ld.so will
13389 not process them. */
13395 {
13396 _bfd_error_handler
13397 /* xgettext:c-format */
13400 input_bfd,
13401 input_section,
13406 }
13409 {
13411 {
13413 /* If the overflowing reloc was to an undefined symbol,
13414 we have already printed one error message and there
13415 is no point complaining again. */
13436 /* error_message should already be set. */
13441 /* Fall through. */
13443 common_error:
13448 }
13449 }
13450 }
13453 }
13455 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13456 adds the edit to the start of the list. (The list must be built in order of
13457 ascending TINDEX: the function's callers are primarily responsible for
13458 maintaining that condition). */
13460 static void
13463 arm_unwind_edit_type type,
13466 {
13475 {
13485 }
13486 else
13487 {
13494 }
13495 }
13499 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13501 static void
13503 {
13511 /* Adjust size of output section. */
13513 }
13515 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13517 static void
13519 {
13523 add_unwind_table_edit
13531 }
13533 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13534 made to those tables, such that:
13536 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13537 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13538 codes which have been inlined into the index).
13540 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13542 The edits are applied when the tables are written
13543 (in elf32_arm_write_section). */
13545 bool
13550 {
13557 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13558 text sections. */
13560 {
13564 {
13572 {
13573 Elf_Internal_Shdr *linked_hdr
13581 /* Link this .ARM.exidx section back from the text section it
13582 describes. */
13584 }
13585 }
13586 }
13588 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13589 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13590 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13593 {
13600 bfd_vma j;
13611 {
13612 /* Section has no unwind data. */
13616 /* Ignore zero sized sections. */
13623 }
13625 /* Skip /DISCARD/ sections. */
13642 /* An error? */
13646 {
13648 /* Add cantunwind if first unwind item does not match section
13649 start. */
13651 {
13654 }
13655 }
13658 {
13663 /* An EXIDX_CANTUNWIND entry. */
13665 {
13669 }
13670 /* Inlined unwinding data. Merge if equal to previous. */
13672 {
13678 }
13679 /* Normal table entry. In theory we could merge these too,
13680 but duplicate entries are likely to be much less common. */
13681 else
13685 {
13690 }
13693 }
13695 /* Free contents if we allocated it ourselves. */
13699 /* Record edits to be applied later (in elf32_arm_write_section). */
13708 }
13710 /* Add terminating CANTUNWIND entry. */
13716 }
13718 static bool
13721 {
13737 }
13739 static bool
13741 {
13748 /* Invoke the regular ELF backend linker to do all the work. */
13752 /* Process stub sections (eg BE8 encoding, ...). */
13756 {
13758 /* Only process it once, in its link_sec slot. */
13760 {
13766 }
13767 }
13769 /* Write out any glue sections now that we have created all the
13770 stubs. */
13772 {
13775 ARM2THUMB_GLUE_SECTION_NAME))
13780 THUMB2ARM_GLUE_SECTION_NAME))
13785 VFP11_ERRATUM_VENEER_SECTION_NAME))
13790 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13795 ARM_BX_GLUE_SECTION_NAME))
13797 }
13800 }
13802 /* Return a best guess for the machine number based on the attributes. */
13804 static unsigned int
13806 {
13810 {
13817 {
13824 {
13832 {
13838 {
13842 }
13843 }
13844 }
13847 }
13881 /* Force entry to be added for any new known Tag_CPU_arch value. */
13884 /* Unknown Tag_CPU_arch value. */
13886 }
13887 }
13889 /* Set the right machine number. */
13891 static bool
13893 {
13899 {
13902 else
13904 }
13908 }
13910 /* Function to keep ARM specific flags in the ELF header. */
13912 static bool
13914 {
13917 {
13919 {
13921 _bfd_error_handler
13922 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13923 abfd);
13924 else
13925 _bfd_error_handler
13927 abfd);
13928 }
13929 }
13930 else
13931 {
13934 }
13937 }
13939 /* Copy backend specific data from one object module to another. */
13941 static bool
13943 {
13944 flagword in_flags;
13945 flagword out_flags;
13956 {
13957 /* Cannot mix APCS26 and APCS32 code. */
13961 /* Cannot mix float APCS and non-float APCS code. */
13965 /* If the src and dest have different interworking flags
13966 then turn off the interworking bit. */
13968 {
13970 _bfd_error_handler
13971 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
13975 }
13977 /* Likewise for PIC, though don't warn for this case. */
13980 }
13986 }
13988 /* Values for Tag_ABI_PCS_R9_use. */
13989 enum
13990 {
13991 AEABI_R9_V6,
13992 AEABI_R9_SB,
13993 AEABI_R9_TLS,
13994 AEABI_R9_unused
13995 };
13997 /* Values for Tag_ABI_PCS_RW_data. */
13998 enum
13999 {
14000 AEABI_PCS_RW_data_absolute,
14001 AEABI_PCS_RW_data_PCrel,
14002 AEABI_PCS_RW_data_SBrel,
14003 AEABI_PCS_RW_data_unused
14004 };
14006 /* Values for Tag_ABI_enum_size. */
14007 enum
14008 {
14009 AEABI_enum_unused,
14010 AEABI_enum_short,
14011 AEABI_enum_wide,
14012 AEABI_enum_forced_wide
14013 };
14015 /* Determine whether an object attribute tag takes an integer, a
14016 string or both. */
14018 static int
14020 {
14029 else
14031 }
14033 /* The ABI defines that Tag_conformance should be emitted first, and that
14034 Tag_nodefaults should be second (if either is defined). This sets those
14035 two positions, and bumps up the position of all the remaining tags to
14036 compensate. */
14037 static int
14039 {
14049 }
14051 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14052 static bool
14054 {
14056 {
14057 _bfd_error_handler
14062 }
14063 else
14064 {
14065 _bfd_error_handler
14069 }
14070 }
14072 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14073 Returns -1 if no architecture could be read. */
14075 static int
14077 {
14081 /* Note: the tag and its argument below are uleb128 values, though
14082 currently-defined values fit in one byte for each. */
14089 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14091 }
14093 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14094 The tag is removed if ARCH is -1. */
14096 static void
14098 {
14103 {
14106 }
14108 /* Note: the tag and its argument below are uleb128 values, though
14109 currently-defined values fit in one byte for each. */
14115 }
14117 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14118 into account. */
14120 static int
14123 {
14124 #define T(X) TAG_CPU_ARCH_##X
14127 {
14137 };
14139 {
14150 };
14152 {
14164 };
14166 {
14179 };
14181 {
14195 };
14197 {
14212 };
14214 {
14237 };
14239 {
14256 };
14258 {
14276 };
14278 {
14297 };
14299 {
14322 };
14324 {
14348 };
14350 {
14375 };
14377 {
14378 v6t2,
14379 v6k,
14380 v7,
14381 v6_m,
14382 v6s_m,
14383 v7e_m,
14384 v8,
14385 v8r,
14386 v8m_baseline,
14387 v8m_mainline,
14388 NULL,
14389 NULL,
14390 NULL,
14391 v8_1m_mainline,
14392 v9,
14393 /* Pseudo-architecture. */
14394 v4t_plus_v6_m
14395 };
14397 /* Check we've not got a higher architecture than we know about. */
14400 {
14403 }
14405 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14411 /* And override the new tag if we have a Tag_also_compatible_with on the
14412 input. */
14421 /* Architectures before V6KZ add features monotonically. */
14427 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14428 as the canonical version. */
14430 {
14433 }
14434 else
14438 {
14442 }
14445 #undef T
14446 }
14448 /* Query attributes object to see if integer divide instructions may be
14449 present in an object. */
14450 static bool
14452 {
14457 {
14459 /* Integer divide allowed if instruction contained in archetecture. */
14464 else
14468 /* Integer divide explicitly prohibited. */
14472 /* Unrecognised case - treat as allowing divide everywhere. */
14474 /* Integer divide allowed in ARM state. */
14476 }
14477 }
14479 /* Query attributes object to see if integer divide instructions are
14480 forbidden to be in the object. This is not the inverse of
14481 elf32_arm_attributes_accept_div. */
14482 static bool
14484 {
14486 }
14488 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14489 are conflicting attributes. */
14491 static bool
14493 {
14497 /* Some tags have 0 = don't care, 1 = strong requirement,
14498 2 = weak requirement. */
14504 /* Skip the linker stubs file. This preserves previous behavior
14505 of accepting unknown attributes in the first input file - but
14506 is that a bug? */
14510 /* Skip any input that hasn't attribute section.
14511 This enables to link object files without attribute section with
14512 any others. */
14517 {
14518 /* This is the first object. Copy the attributes. */
14523 /* Use the Tag_null value to indicate the attributes have been
14524 initialized. */
14527 /* We do not output objects with Tag_MPextension_use_legacy - we move
14528 the attribute's value to Tag_MPextension_use. */
14530 {
14534 {
14535 _bfd_error_handler
14539 }
14545 }
14547 /* PR 28859 and 28848: Handle the case where the first input file,
14548 eg crti.o, has a Tag_ABI_HardFP_use of 3 but no Tag_FP_arch set.
14549 Using Tag_ABI_HardFP_use in this way is deprecated, so reset the
14550 attribute to zero.
14551 FIXME: Should we handle other non-zero values of Tag_ABI_HardFO_use ? */
14556 }
14560 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14562 {
14563 /* Ignore mismatches if the object doesn't use floating point or is
14564 floating point ABI independent. */
14571 {
14572 _bfd_error_handler
14577 }
14578 }
14581 {
14582 /* Merge this attribute with existing attributes. */
14584 {
14587 /* These are merged after Tag_CPU_arch. */
14592 /* Use the first value seen. */
14596 {
14601 {
14602 /* These aren't real CPU names, but we can't guess
14603 that from the architecture version alone. */
14627 };
14629 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14635 secondary_compat,
14636 name_table);
14638 /* Return with error if failed to merge. */
14646 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14650 {
14651 /* The output architecture has been changed to match the
14652 input architecture. Use the input names. */
14659 }
14660 else
14661 {
14664 }
14666 /* If we still don't have a value for Tag_CPU_name,
14667 make one up now. Tag_CPU_raw_name remains blank. */
14672 }
14679 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14693 /* Use the largest value specified. */
14700 /* Use the smallest value specified. */
14709 {
14710 /* This error message should be enabled once all non-conformant
14711 binaries in the toolchain have had the attributes set
14712 properly.
14713 _bfd_error_handler
14714 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14715 obfd, ibfd);
14716 result = false; */
14717 }
14718 /* Fall through. */
14721 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14722 value if greater than 2 (for future-proofing). */
14730 /* The virtualization tag effectively stores two bits of
14731 information: the intended use of TrustZone (in bit 0), and the
14732 intended use of Virtualization (in bit 1). */
14737 {
14740 else
14741 {
14742 _bfd_error_handler
14747 }
14748 }
14753 {
14754 /* 0 will merge with anything.
14755 'A' and 'S' merge to 'A'.
14756 'R' and 'S' merge to 'R'.
14757 'M' and 'A|R|S' is an error. */
14766 else
14767 {
14768 _bfd_error_handler
14770 ibfd,
14774 }
14775 }
14779 /* No need to change output value if any of:
14780 - pre (<=) ARMv5T input architecture (do not have DSP)
14781 - M input profile not ARMv7E-M and do not have DSP. */
14787 /* Output value should be 0 if DSP part of architecture, ie.
14788 - post (>=) ARMv5te architecture output
14789 - A, R or S profile output or ARMv7E-M output architecture. */
14796 /* Otherwise, DSP instructions are added and not part of output
14797 architecture. */
14798 else
14803 {
14804 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14805 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14806 when it's 0. It might mean absence of FP hardware if
14807 Tag_FP_arch is zero. */
14809 #define VFP_VERSION_COUNT 9
14810 static const struct
14811 {
14815 {
14825 };
14830 /* If the output has no requirement about FP hardware,
14831 follow the requirement of the input. */
14833 {
14834 /* This assert is still reasonable, we shouldn't
14835 produce the suspicious build attribute
14836 combination (See below for in_attr). */
14842 }
14843 /* If the input has no requirement about FP hardware, do
14844 nothing. */
14846 {
14847 /* We used to assert that Tag_ABI_HardFP_use was
14848 zero here, but we should never assert when
14849 consuming an object file that has suspicious
14850 build attributes. The single precision variant
14851 of 'no FP architecture' is still 'no FP
14852 architecture', so we just ignore the tag in this
14853 case. */
14855 }
14857 /* Both the input and the output have nonzero Tag_FP_arch.
14858 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14860 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14861 do nothing. */
14864 ;
14865 /* If the input and the output have different Tag_ABI_HardFP_use,
14866 the combination of them is 0 (implied by Tag_FP_arch). */
14871 /* Now we can handle Tag_FP_arch. */
14873 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14874 pick the biggest. */
14877 {
14880 }
14881 /* The output uses the superset of input features
14882 (ISA version) and registers. */
14889 /* This assumes all possible supersets are also a valid
14890 options. */
14892 {
14896 }
14898 }
14904 {
14905 /* It's sometimes ok to mix different configs, so this is only
14906 a warning. */
14907 _bfd_error_handler
14909 }
14915 {
14916 _bfd_error_handler
14919 }
14927 {
14928 _bfd_error_handler
14930 ibfd);
14932 }
14933 /* Use the smallest value specified. */
14940 {
14941 _bfd_error_handler
14942 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
14944 }
14950 {
14953 {
14954 /* The existing object is compatible with anything.
14955 Use whatever requirements the new object has. */
14957 }
14961 {
14972 _bfd_error_handler
14973 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
14975 }
14976 }
14979 /* Aready done. */
14983 {
14984 _bfd_error_handler
14988 }
14991 /* Merged in target-independent code. */
14994 /* This is handled along with Tag_FP_arch. */
14998 {
15000 {
15001 _bfd_error_handler
15005 }
15006 }
15012 /* A value of zero on input means that the divide instruction may
15013 be used if available in the base architecture as specified via
15014 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15015 the user did not want divide instructions. A value of 2
15016 explicitly means that divide instructions were allowed in ARM
15017 and Thumb state. */
15031 /* We don't output objects with Tag_MPextension_use_legacy - we
15032 move the value to Tag_MPextension_use. */
15034 {
15036 {
15037 _bfd_error_handler
15040 ibfd);
15042 }
15043 }
15051 /* This tag is set if it exists, but the value is unused (and is
15052 typically zero). We don't actually need to do anything here -
15053 the merge happens automatically when the type flags are merged
15054 below. */
15057 /* Already done in Tag_CPU_arch. */
15060 /* Keep the attribute if it matches. Throw it away otherwise.
15061 No attribute means no claim to conform. */
15068 result
15070 }
15072 /* If out_attr was copied from in_attr then it won't have a type yet. */
15075 }
15077 /* Merge Tag_compatibility attributes and any common GNU ones. */
15081 /* Check for any attributes not known on ARM. */
15085 }
15088 /* Return TRUE if the two EABI versions are incompatible. */
15090 static bool
15092 {
15093 /* v4 and v5 are the same spec before and after it was released,
15094 so allow mixing them. */
15100 }
15102 /* Merge backend specific data from an object file to the output
15103 object file when linking. */
15105 static bool
15108 /* Display the flags field. */
15110 static bool
15112 {
15118 /* Print normal ELF private data. */
15122 /* Ignore init flag - it may not be set, despite the flags field
15123 containing valid data. */
15128 {
15130 /* The following flag bits are GNU extensions and not part of the
15131 official ARM ELF extended ABI. Hence they are only decoded if
15132 the EABI version is not set. */
15138 else
15145 else
15174 else
15185 else
15217 eabi:
15230 }
15251 }
15253 static int
15255 {
15257 {
15262 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15263 This allows us to distinguish between data used by Thumb instructions
15264 and non-data (which is probably code) inside Thumb regions of an
15265 executable. */
15272 }
15275 }
15283 {
15286 {
15290 }
15293 }
15295 /* Look through the relocs for a section during the first phase. */
15297 static bool
15300 {
15324 /* Create dynamic sections for relocatable executables so that we can
15325 copy relocations. */
15328 {
15331 }
15346 {
15358 /* PR 9934: It is possible to have relocations that do not
15359 refer to symbols, thus it is also possible to have an
15360 object file containing relocations but no symbol table. */
15362 {
15364 r_symndx);
15366 }
15371 {
15373 {
15374 /* A local symbol. */
15379 }
15380 else
15381 {
15386 }
15387 }
15395 /* Could be done earlier, if h were already available. */
15398 {
15400 {
15402 {
15409 }
15410 else
15411 {
15413 }
15414 }
15418 {
15420 {
15421 /* Such a relocation is not supposed to be generated
15422 by gcc on a static function. */
15423 /* Anyway if needed it could be handled. */
15425 }
15426 else
15427 {
15429 }
15430 }
15434 {
15436 {
15443 }
15444 else
15445 {
15447 }
15448 }
15462 /* This symbol requires a global offset table entry. */
15463 {
15467 {
15480 }
15486 {
15489 }
15490 else
15491 {
15492 /* This is a global offset table entry for a local symbol. */
15496 {
15498 r_symndx);
15500 }
15504 }
15506 /* If a variable is accessed with both tls methods, two
15507 slots may be created. */
15512 /* We will already have issued an error message if there
15513 is a TLS/non-TLS mismatch, based on the symbol
15514 type. So just combine any TLS types needed. */
15519 /* If the symbol is accessed in both IE and GDESC
15520 method, we're able to relax. Turn off the GDESC flag,
15521 without messing up with any other kind of tls types
15522 that may be involved. */
15527 {
15530 else
15532 }
15533 }
15534 /* Fall through. */
15540 /* Fall through. */
15562 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15563 ldr __GOTT_INDEX__ offsets. */
15565 {
15568 }
15571 /* Fall through. */
15578 {
15579 _bfd_error_handler
15580 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15585 }
15587 /* Fall through. */
15590 jump_over:
15592 {
15594 }
15595 /* Fall through. */
15603 /* Should the interworking branches be listed here? */
15607 {
15610 {
15611 /* In shared libraries and relocatable executables,
15612 we treat local relative references as calls;
15613 see the related SYMBOL_CALLS_LOCAL code in
15614 allocate_dynrelocs. */
15617 }
15618 else
15619 /* We are creating a shared library or relocatable
15620 executable, and this is a reloc against a global symbol,
15621 or a non-PC-relative reloc against a local symbol.
15622 We may need to copy the reloc into the output. */
15624 }
15625 else
15629 /* This relocation describes the C++ object vtable hierarchy.
15630 Reconstruct it for later use during GC. */
15636 /* This relocation describes which C++ vtable entries are actually
15637 used. Record for later use during GC. */
15642 }
15645 {
15647 /* We may need a .plt entry if the function this reloc
15648 refers to is in a different object, regardless of the
15649 symbol's type. We can't tell for sure yet, because
15650 something later might force the symbol local. */
15653 /* If this reloc is in a read-only section, we might
15654 need a copy reloc. We can't check reliably at this
15655 stage whether the section is read-only, as input
15656 sections have not yet been mapped to output sections.
15657 Tentatively set the flag for now, and correct in
15658 adjust_dynamic_symbol. */
15660 }
15664 {
15670 {
15673 }
15674 else
15675 {
15681 }
15683 /* If the symbol is a function that doesn't bind locally,
15684 this relocation will need a PLT entry. */
15691 /* It's too early to use htab->use_blx here, so we have to
15692 record possible blx references separately from
15693 relocs that definitely need a thumb stub. */
15701 }
15704 {
15707 /* Create a reloc section in dynobj. */
15709 {
15710 sreloc = _bfd_elf_make_dynamic_reloc_section
15715 }
15717 /* If this is a global symbol, count the number of
15718 relocations we need for this symbol. */
15721 else
15722 {
15726 }
15730 {
15741 }
15748 {
15749 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15750 that will become rofixup. */
15751 /* This is due to the fact that we suppose all will become rofixup. */
15752 _bfd_error_handler
15757 }
15758 }
15759 }
15762 }
15764 static void
15767 {
15789 {
15792 }
15794 {
15797 }
15798 else
15810 {
15813 {
15816 irela++;
15817 count++;
15818 }
15820 {
15824 bfd_size_type j;
15825 bfd_vma offset;
15841 else
15845 {
15847 {
15849 bfd_vma bias;
15850 bfd_vma reloc_index;
15860 {
15861 bias++;
15863 }
15867 {
15869 irela++;
15870 count++;
15871 }
15874 }
15877 {
15878 /* New relocation entity. */
15887 irela++;
15888 count++;
15889 }
15890 }
15891 else
15892 {
15894 {
15897 irela++;
15898 }
15901 }
15902 }
15903 }
15911 {
15914 irela++;
15915 count--;
15916 }
15920 /* Hashes are no longer valid. */
15923 }
15925 /* Unwinding tables are not referenced directly. This pass marks them as
15926 required if the corresponding code section is marked. Similarly, ARMv8-M
15927 secure entry functions can only be referenced by SG veneers which are
15928 created after the GC process. They need to be marked in case they reside in
15929 their own section (as would be the case if code was compiled with
15930 -ffunction-sections). */
15932 static bool
15934 elf_gc_mark_hook_fn gc_mark_hook)
15935 {
15955 /* Marking EH data may cause additional code sections to be marked,
15956 requiring multiple passes. */
15959 {
15962 {
15970 {
15979 {
15983 }
15984 }
15986 /* Mark section holding ARMv8-M secure entry functions. We mark all
15987 of them so no need for a second browsing. */
15989 {
15998 /* Scan symbols. */
16000 {
16005 /* Assume it is a special symbol. If not, cmse_scan will
16006 warn about it and user can do something about it. */
16008 CMSE_PREFIX))
16009 {
16014 /* The debug sections related to these secure entry
16015 functions are marked on enabling below flag. */
16017 }
16018 }
16021 {
16022 /* Looping over all the sections of the object file containing
16023 Armv8-M secure entry functions and marking all the debug
16024 sections. */
16026 {
16027 /* If not a debug sections, skip it. */
16029 {
16032 }
16033 }
16035 }
16036 }
16037 }
16040 }
16042 /* PR 30354: If we have added extra marks then make sure that any
16043 dependencies of the newly marked sections are also marked. */
16048 }
16050 /* Treat mapping symbols as special target symbols. */
16052 static bool
16054 {
16056 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
16057 }
16059 /* If the ELF symbol SYM might be a function in SEC, return the
16060 function size and set *CODE_OFF to the function's entry point,
16061 otherwise return zero. */
16063 static bfd_size_type
16066 {
16067 bfd_size_type size;
16079 {
16081 /* Ignore symbols created by the annobin plugin for gcc and clang.
16082 These symbols are hidden, local, notype and have a size of 0. */
16087 /* Fall through. */
16090 /* FIXME: Allow STT_GNU_IFUNC as well ? */
16094 }
16098 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16103 /* Do not return 0 for the function's size. */
16106 }
16108 static bool
16113 {
16119 }
16121 /* Adjust a symbol defined by a dynamic object and referenced by a
16122 regular object. The current definition is in some section of the
16123 dynamic object, but we're not including those sections. We have to
16124 change the definition to something the rest of the link can
16125 understand. */
16127 static bool
16130 {
16142 /* Make sure we know what is going on here. */
16153 /* If this is a function, put it in the procedure linkage table. We
16154 will fill in the contents of the procedure linkage table later,
16155 when we know the address of the .got section. */
16157 {
16158 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16159 symbol binds locally. */
16165 {
16166 /* This case can occur if we saw a PLT32 reloc in an input
16167 file, but the symbol was never referred to by a dynamic
16168 object, or if all references were garbage collected. In
16169 such a case, we don't actually need to build a procedure
16170 linkage table, and we can just do a PC24 reloc instead. */
16176 }
16179 }
16180 else
16181 {
16182 /* It's possible that we incorrectly decided a .plt reloc was
16183 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16184 in check_relocs. We can't decide accurately between function
16185 and non-function syms in check-relocs; Objects loaded later in
16186 the link may change h->type. So fix it now. */
16191 }
16193 /* If this is a weak symbol, and there is a real definition, the
16194 processor independent code will have arranged for us to see the
16195 real definition first, and we can just use the same value. */
16197 {
16203 }
16205 /* If there are no non-GOT references, we do not need a copy
16206 relocation. */
16210 /* This is a reference to a symbol defined by a dynamic object which
16211 is not a function. */
16213 /* If we are creating a shared library, we must presume that the
16214 only references to the symbol are via the global offset table.
16215 For such cases we need not do anything here; the relocations will
16216 be handled correctly by relocate_section. Relocatable executables
16217 can reference data in shared objects directly, so we don't need to
16218 do anything here. */
16222 /* We must allocate the symbol in our .dynbss section, which will
16223 become part of the .bss section of the executable. There will be
16224 an entry for this symbol in the .dynsym section. The dynamic
16225 object will contain position independent code, so all references
16226 from the dynamic object to this symbol will go through the global
16227 offset table. The dynamic linker will use the .dynsym entry to
16228 determine the address it must put in the global offset table, so
16229 both the dynamic object and the regular object will refer to the
16230 same memory location for the variable. */
16231 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16232 linker to copy the initial value out of the dynamic object and into
16233 the runtime process image. We need to remember the offset into the
16234 .rel(a).bss section we are going to use. */
16236 {
16239 }
16240 else
16241 {
16244 }
16248 {
16251 }
16254 }
16256 /* Allocate space in .plt, .got and associated reloc sections for
16257 dynamic relocs. */
16259 static bool
16261 {
16279 {
16280 /* Make sure this symbol is output as a dynamic symbol.
16281 Undefined weak syms won't yet be marked as dynamic. */
16284 {
16287 }
16289 /* If the call in the PLT entry binds locally, the associated
16290 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16291 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16292 than the .plt section. */
16294 {
16298 /* All non-call references can be resolved directly.
16299 This means that they can (and in some cases, must)
16300 resolve directly to the run-time target, rather than
16301 to the PLT. That in turns means that any .got entry
16302 would be equal to the .igot.plt entry, so there's
16303 no point having both. */
16305 }
16310 {
16313 /* If this symbol is not defined in a regular file, and we are
16314 not generating a shared library, then set the symbol to this
16315 location in the .plt. This is required to make function
16316 pointers compare as equal between the normal executable and
16317 the shared library. */
16320 {
16324 /* Make sure the function is not marked as Thumb, in case
16325 it is the target of an ABS32 relocation, which will
16326 point to the PLT entry. */
16328 }
16330 /* VxWorks executables have a second set of relocations for
16331 each PLT entry. They go in a separate relocation section,
16332 which is processed by the kernel loader. */
16334 {
16335 /* There is a relocation for the initial PLT entry:
16336 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16340 /* There are two extra relocations for each subsequent
16341 PLT entry: an R_ARM_32 relocation for the GOT entry,
16342 and an R_ARM_32 relocation for the PLT entry. */
16344 }
16345 }
16346 else
16347 {
16350 }
16351 }
16352 else
16353 {
16356 }
16362 {
16368 /* Make sure this symbol is output as a dynamic symbol.
16369 Undefined weak syms won't yet be marked as dynamic. */
16374 {
16377 }
16386 /* Non-TLS symbols need one GOT slot. */
16388 else
16389 {
16391 {
16392 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16393 eh->tlsdesc_got
16398 /* plt.got_offset needs to know there's a TLS_DESC
16399 reloc in the middle of .got.plt. */
16401 }
16404 {
16405 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16406 consecutive GOT slots. If the symbol is both GD
16407 and GDESC, got.offset may have been
16408 overwritten. */
16411 }
16414 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16415 slot. */
16417 }
16431 {
16439 {
16441 /* GDESC needs a trampoline to jump to. */
16443 }
16445 /* Only GD needs it. GDESC just emits one relocation per
16446 2 entries. */
16449 }
16452 {
16454 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16456 }
16459 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16460 they all resolve dynamically instead. Reserve room for the
16461 GOT entry's R_ARM_IRELATIVE relocation. */
16465 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16468 /* Reserve room for rofixup for FDPIC executable. */
16469 /* TLS relocs do not need space since they are completely
16470 resolved. */
16472 }
16473 else
16476 /* FDPIC support. */
16478 {
16479 /* Symbol musn't be exported. */
16483 /* We only allocate one function descriptor with its associated
16484 relocation. */
16486 {
16491 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16494 else
16496 }
16497 }
16500 {
16509 {
16510 /* We only allocate one function descriptor with its
16511 associated relocation. */
16513 {
16517 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16518 rofixups. */
16521 else
16523 }
16524 }
16526 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16527 R_ARM_RELATIVE/rofixup relocation on it. */
16532 else
16534 }
16537 {
16544 {
16545 /* We only allocate one function descriptor with its
16546 associated relocation. */
16548 {
16553 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16554 rofixups. */
16557 else
16559 }
16560 }
16562 {
16563 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16565 }
16566 else
16567 {
16568 /* Will need one dynamic reloc per reference. will be either
16569 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16572 }
16573 }
16575 /* Allocate stubs for exported Thumb functions on v4t. */
16580 {
16587 /* Create a new symbol to regist the real location of the function. */
16601 /* Point the symbol at the stub. */
16606 }
16611 /* In the shared -Bsymbolic case, discard space allocated for
16612 dynamic pc-relative relocs against symbols which turn out to be
16613 defined in regular objects. For the normal shared case, discard
16614 space for pc-relative relocs that have become local due to symbol
16615 visibility changes. */
16620 {
16621 /* Relocs that use pc_count are PC-relative forms, which will appear
16622 on something like ".long foo - ." or "movw REG, foo - .". We want
16623 calls to protected symbols to resolve directly to the function
16624 rather than going via the plt. If people want function pointer
16625 comparisons to work as expected then they should avoid writing
16626 assembly like ".long foo - .". */
16628 {
16632 {
16637 else
16639 }
16640 }
16643 {
16647 {
16650 else
16652 }
16653 }
16655 /* Also discard relocs on undefined weak syms with non-default
16656 visibility. */
16659 {
16664 /* Make sure undefined weak symbols are output as a dynamic
16665 symbol in PIEs. */
16668 {
16671 }
16672 }
16676 {
16677 /* Output absolute symbols so that we can create relocations
16678 against them. For normal symbols we output a relocation
16679 against the section that contains them. */
16682 }
16684 }
16685 else
16686 {
16687 /* For the non-shared case, discard space for relocs against
16688 symbols which turn out to need copy relocs or are not
16689 dynamic. */
16697 {
16698 /* Make sure this symbol is output as a dynamic symbol.
16699 Undefined weak syms won't yet be marked as dynamic. */
16702 {
16705 }
16707 /* If that succeeded, we know we'll be keeping all the
16708 relocs. */
16711 }
16715 keep: ;
16716 }
16718 /* Finally, allocate space. */
16720 {
16732 else
16734 }
16737 }
16739 void
16742 {
16750 }
16752 /* Set the sizes of the dynamic sections. */
16754 static bool
16757 {
16773 {
16774 /* Set the contents of the .interp section to the interpreter. */
16776 {
16781 }
16782 }
16784 /* Set up .got offsets for local syms, and space for local dynamic
16785 relocs. */
16787 {
16793 bfd_size_type locsymcount;
16803 {
16808 {
16811 {
16812 /* Input section has been discarded, either because
16813 it is a copy of a linkonce section or due to
16814 linker script /DISCARD/, so we'll be discarding
16815 the relocs too. */
16816 }
16820 {
16821 /* Relocations in vxworks .tls_vars sections are
16822 handled specially by the loader. */
16823 }
16825 {
16829 else
16833 }
16834 }
16835 }
16854 {
16861 /* FDPIC support. */
16863 {
16865 {
16869 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16872 else
16874 }
16875 }
16878 {
16880 {
16884 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16887 else
16889 }
16891 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16894 else
16896 }
16899 {
16903 {
16908 /* All references to the PLT are calls, so all
16909 non-call references can resolve directly to the
16910 run-time target. This means that the .got entry
16911 would be the same as the .igot.plt entry, so there's
16912 no point creating both. */
16914 }
16915 else
16916 {
16919 }
16922 {
16928 else
16930 }
16931 }
16933 {
16938 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16941 {
16946 /* plt.got_offset needs to know there's a TLS_DESC
16947 reloc in the middle of .got.plt. */
16949 }
16954 {
16955 /* If the symbol is both GD and GDESC, *local_got
16956 may have been overwritten. */
16959 }
16962 symndx);
16966 /* If all references to an STT_GNU_IFUNC PLT are calls,
16967 then all non-call references, including this GOT entry,
16968 resolve directly to the run-time target. */
16974 {
16982 {
16986 }
16987 }
16988 }
16989 else
16991 }
16992 }
16995 {
16996 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16997 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
17002 }
17003 else
17006 /* At the very end of the .rofixup section is a pointer to the GOT,
17007 reserve space for it. */
17011 /* Allocate global sym .plt and .got entries, and space for global
17012 sym dynamic relocs. */
17015 /* Here we rummage through the found bfds to collect glue information. */
17017 {
17021 /* Initialise mapping tables for code/data. */
17028 }
17030 /* Allocate space for the glue sections now that we've sized them. */
17033 /* For every jump slot reserved in the sgotplt, reloc_count is
17034 incremented. However, when we reserve space for TLS descriptors,
17035 it's not incremented, so in order to compute the space reserved
17036 for them, it suffices to multiply the reloc count by the jump
17037 slot size. */
17042 {
17049 /* If we're not using lazy TLS relocations, don't generate the
17050 PLT and GOT entries they require. */
17053 else
17054 {
17060 }
17061 }
17063 /* The check_relocs and adjust_dynamic_symbol entry points have
17064 determined the sizes of the various dynamic sections. Allocate
17065 memory for them. */
17068 {
17074 /* It's OK to base decisions on the section name, because none
17075 of the dynobj section names depend upon the input files. */
17079 {
17080 /* Remember whether there is a PLT. */
17081 ;
17082 }
17084 {
17086 {
17087 /* Remember whether there are any reloc sections other
17088 than .rel(a).plt and .rela.plt.unloaded. */
17092 /* We use the reloc_count field as a counter if we need
17093 to copy relocs into the output file. */
17095 }
17096 }
17104 {
17105 /* It's not one of our sections, so don't allocate space. */
17107 }
17110 {
17111 /* If we don't need this section, strip it from the
17112 output file. This is mostly to handle .rel(a).bss and
17113 .rel(a).plt. We must create both sections in
17114 create_dynamic_sections, because they must be created
17115 before the linker maps input sections to output
17116 sections. The linker does that before
17117 adjust_dynamic_symbol is called, and it is that
17118 function which decides whether anything needs to go
17119 into these sections. */
17122 }
17127 /* Allocate memory for the section contents. */
17131 }
17134 relocs);
17135 }
17137 /* Size sections even though they're not dynamic. We use it to setup
17138 _TLS_MODULE_BASE_, if needed. */
17140 static bool
17143 {
17155 {
17158 tlsbase = elf_link_hash_lookup
17162 {
17178 }
17179 }
17187 }
17189 /* Finish up dynamic symbol handling. We set the contents of various
17190 dynamic sections here. */
17192 static bool
17197 {
17208 {
17210 {
17215 }
17218 {
17219 /* Mark the symbol as undefined, rather than as defined in
17220 the .plt section. */
17222 /* If the symbol is weak we need to clear the value.
17223 Otherwise, the PLT entry would provide a definition for
17224 the symbol even if the symbol wasn't defined anywhere,
17225 and so the symbol would never be NULL. Leave the value if
17226 there were any relocations where pointer equality matters
17227 (this is a clue for the dynamic linker, to make function
17228 pointer comparisons work between an application and shared
17229 library). */
17232 }
17234 {
17235 /* At least one non-call relocation references this .iplt entry,
17236 so the .iplt entry is the function's canonical address. */
17244 }
17245 }
17248 {
17250 Elf_Internal_Rela rel;
17252 /* This symbol needs a copy reloc. Set it up. */
17264 else
17267 }
17269 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17270 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17271 it is relative to the ".got" section. */
17279 }
17281 static void
17285 {
17289 {
17292 /* Emit mov pc,rx if bx is not permitted. */
17296 }
17297 }
17299 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17300 other variants, NaCl needs this entry in a static executable's
17301 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17302 zero. For .iplt really only the last bundle is useful, and .iplt
17303 could have a shorter first entry, with each individual PLT entry's
17304 relative branch calculated differently so it targets the last
17305 bundle instead of the instruction before it (labelled .Lplt_tail
17306 above). But it's simpler to keep the size and layout of PLT0
17307 consistent with the dynamic case, at the cost of some dead code at
17308 the start of .iplt and the one dead store to the stack at the start
17309 of .Lplt_tail. */
17310 static void
17313 {
17329 }
17331 /* Finish up the dynamic sections. */
17333 static bool
17335 {
17348 /* A broken linker script might have discarded the dynamic sections.
17349 Catch this here so that we do not seg-fault later on. */
17355 {
17367 {
17368 Elf_Internal_Dyn dyn;
17375 {
17395 get_vma:
17398 {
17399 _bfd_error_handler
17403 }
17435 /* Set the bottom bit of DT_INIT/FINI if the
17436 corresponding function is Thumb. */
17442 get_sym:
17443 /* If it wasn't set by elf_bfd_final_link
17444 then there is nothing to adjust. */
17446 {
17454 {
17457 }
17458 }
17460 }
17461 }
17463 /* Fill in the first entry in the procedure linkage table. */
17465 {
17469 /* Calculate the addresses of the GOT and PLT. */
17474 {
17475 /* The VxWorks GOT is relocated by the dynamic linker.
17476 Therefore, we must emit relocations rather than simply
17477 computing the values now. */
17478 Elf_Internal_Rela rel;
17489 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17495 }
17500 {
17512 }
17513 else
17514 {
17527 #ifdef FOUR_WORD_PLT
17528 /* The displacement value goes in the otherwise-unused
17529 last word of the second entry. */
17531 #else
17533 #endif
17534 }
17535 }
17537 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17538 really seem like the right value. */
17543 {
17544 bfd_vma got_address
17548 bfd_vma plt_address
17564 }
17567 {
17571 #ifdef FOUR_WORD_PLT
17574 #endif
17575 }
17580 {
17581 /* Correct the .rel(a).plt.unloaded relocations. They will have
17582 incorrect symbol indexes. */
17591 {
17592 Elf_Internal_Rela rel;
17603 }
17604 }
17605 }
17610 /* NaCl uses a special first entry in .iplt too. */
17613 /* Fill in the first three entries in the global offset table. */
17615 {
17617 {
17620 else
17626 }
17629 }
17631 /* At the very end of the .rofixup section is a pointer to the GOT. */
17633 {
17642 /* Make sure we allocated and generated the same number of fixups. */
17644 }
17647 }
17649 static bool
17651 {
17666 {
17673 }
17677 {
17681 else
17683 }
17685 /* Scan segment to set p_flags attribute if it contains only sections with
17686 SHF_ARM_PURECODE flag. */
17688 {
17694 {
17697 }
17699 {
17702 }
17703 }
17705 }
17707 static enum elf_reloc_type_class
17711 {
17716 {
17717 /* Check relocation against STT_GNU_IFUNC symbol if there are
17718 dynamic symbols. */
17723 {
17724 Elf_Internal_Sym sym;
17729 {
17730 /* xgettext:c-format */
17734 /* Ideally an error class should be returned here. */
17735 }
17738 }
17739 }
17742 {
17753 }
17754 }
17756 static void
17758 {
17760 }
17762 static bool
17764 {
17767 }
17769 /* Return TRUE if this is an unwinding table entry. */
17771 static bool
17773 {
17776 }
17779 /* Set the type and flags for an ARM section. We do this by
17780 the section name, which is a hack, but ought to work. */
17782 static bool
17784 {
17790 {
17793 }
17799 }
17801 /* Handle an ARM specific section when reading an object file. This is
17802 called when bfd_section_from_shdr finds a section with an unknown
17803 type. */
17805 static bool
17810 {
17811 /* There ought to be a place to keep ELF backend specific flags, but
17812 at the moment there isn't one. We just keep track of the
17813 sections by their name, instead. Fortunately, the ABI gives
17814 names for all the ARM specific sections, so we will probably get
17815 away with this. */
17817 {
17825 }
17831 }
17835 {
17838 else
17840 }
17843 {
17852 enum map_symbol_type
17853 {
17854 ARM_MAP_ARM,
17855 ARM_MAP_THUMB,
17856 ARM_MAP_DATA
17857 };
17860 /* Output a single mapping symbol. */
17862 static bool
17865 bfd_vma offset)
17866 {
17868 Elf_Internal_Sym sym;
17880 }
17882 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17883 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17885 static bool
17890 {
17902 {
17905 }
17906 else
17907 {
17910 }
17916 {
17925 }
17927 {
17930 }
17932 {
17934 ? ARM_MAP_THUMB
17947 }
17949 {
17952 }
17953 else
17954 {
17959 {
17962 }
17963 #ifdef FOUR_WORD_PLT
17968 #else
17969 /* A three-word PLT with no Thumb thunk contains only Arm code,
17970 so only need to output a mapping symbol for the first PLT entry and
17971 entries with thumb thunks. */
17973 {
17976 }
17977 #endif
17978 }
17981 }
17983 /* Output mapping symbols for PLT entries associated with H. */
17985 static bool
17987 {
17995 /* When warning symbols are created, they **replace** the "real"
17996 entry in the hash table, thus we never get to see the real
17997 symbol in a hash traversal. So look at it now. */
18003 }
18005 /* Bind a veneered symbol to its veneer identified by its hash entry
18006 STUB_ENTRY. The veneered location thus loose its symbol. */
18008 static void
18010 {
18017 }
18019 /* Output a single local symbol for a generated stub. */
18021 static bool
18024 {
18025 Elf_Internal_Sym sym;
18036 }
18038 static bool
18041 {
18044 bfd_vma addr;
18053 /* Massage our args to the form they really have. */
18059 /* Ensure this stub is attached to the current section being
18060 processed. */
18069 else
18070 {
18073 {
18088 }
18089 }
18094 {
18096 {
18113 }
18116 {
18120 }
18123 {
18140 }
18141 }
18144 }
18146 /* Output mapping symbols for linker generated sections,
18147 and for those data-only sections that do not have a
18148 $d. */
18150 static bool
18155 Elf_Internal_Sym *,
18156 asection *,
18158 {
18159 output_arch_syminfo osi;
18161 bfd_vma offset;
18162 bfd_size_type size;
18180 /* Add a $d mapping symbol to data-only sections that
18181 don't have any mapping symbol. This may result in (harmless) redundant
18182 mapping symbols. */
18186 {
18191 {
18196 == SEC_HAS_CONTENTS
18201 {
18206 }
18207 }
18208 }
18210 /* ARM->Thumb glue. */
18212 {
18214 ARM2THUMB_GLUE_SECTION_NAME);
18223 else
18227 {
18230 }
18231 }
18233 /* Thumb->ARM glue. */
18235 {
18237 THUMB2ARM_GLUE_SECTION_NAME);
18244 {
18247 }
18248 }
18250 /* ARMv4 BX veneers. */
18252 {
18254 ARM_BX_GLUE_SECTION_NAME);
18260 }
18262 /* Long calls stubs. */
18264 {
18270 {
18271 /* Ignore non-stub sections. */
18281 }
18282 }
18284 /* Finally, output mapping symbols for the PLT. */
18286 {
18291 /* Output mapping symbols for the plt header. */
18293 {
18294 /* VxWorks shared libraries have no PLT header. */
18296 {
18301 }
18302 }
18304 {
18307 }
18309 {
18316 }
18318 {
18321 #ifndef FOUR_WORD_PLT
18324 #endif
18325 }
18326 }
18330 {
18331 /* NaCl uses a special first entry in .iplt too. */
18337 }
18340 {
18345 {
18351 {
18354 {
18357 input_bfd,
18359 num_syms);
18361 }
18368 }
18369 }
18370 }
18372 {
18373 /* Mapping symbols for the lazy tls trampoline. */
18381 }
18383 {
18384 /* Mapping symbols for the tls trampoline. */
18387 #ifdef FOUR_WORD_PLT
18391 #endif
18392 }
18395 }
18397 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18398 the import library. All SYMCOUNT symbols of ABFD can be examined
18399 from their pointers in SYMS. Pointers of symbols to keep should be
18400 stored continuously at the beginning of that array.
18402 Returns the number of symbols to keep. */
18404 static unsigned int
18408 {
18423 {
18426 flagword flags;
18441 {
18445 }
18457 }
18463 }
18465 /* Filter symbols of ABFD to include in the import library. All
18466 SYMCOUNT symbols of ABFD can be examined from their pointers in
18467 SYMS. Pointers of symbols to keep should be stored continuously at
18468 the beginning of that array.
18470 Returns the number of symbols to keep. */
18472 static unsigned int
18476 {
18479 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18480 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18481 library to be a relocatable object file. */
18485 else
18487 }
18489 /* Allocate target specific section data. */
18491 static bool
18493 {
18495 {
18503 }
18506 }
18509 /* Used to order a list of mapping symbols by address. */
18511 static int
18513 {
18522 /* Ensure results do not depend on the host qsort for objects with
18523 multiple mapping symbols at the same address by sorting on type
18524 after vma. */
18528 else
18530 }
18532 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18534 static unsigned long
18536 {
18538 }
18540 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18541 relocations. */
18543 static void
18545 {
18549 /* High bit of first word is supposed to be zero. */
18553 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18554 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18560 }
18562 /* Data for make_branch_to_a8_stub(). */
18564 struct a8_branch_to_stub_data
18565 {
18568 };
18571 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18572 places for a particular section. */
18574 static bool
18577 {
18583 bfd_signed_vma branch_offset;
18596 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18597 generated when both source and target are in the same section. */
18614 /* We attempt to avoid this condition by setting stubs_always_after_branch
18615 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18616 This check is just to be on the safe side... */
18618 {
18622 }
18625 {
18636 {
18641 jump24:
18643 {
18644 /* There's not much we can do apart from complain if this
18645 happens. */
18649 }
18651 /* i1 = not(j1 eor s), so:
18652 not i1 = j1 eor s
18653 j1 = (not i1) eor s. */
18665 }
18671 }
18677 }
18679 /* Beginning of stm32l4xx work-around. */
18681 /* Functions encoding instructions necessary for the emission of the
18682 fix-stm32l4xx-629360.
18683 Encoding is extracted from the
18684 ARM (C) Architecture Reference Manual
18685 ARMv7-A and ARMv7-R edition
18686 ARM DDI 0406C.b (ID072512). */
18690 {
18691 /* A8.8.18 B (A8-334)
18692 B target_address (Encoding T4). */
18693 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18694 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18695 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18712 }
18716 {
18717 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18718 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18725 }
18729 {
18730 /* A8.8.60 LDMDB/LDMEA (A8-402)
18731 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18738 }
18742 {
18743 /* A8.8.103 MOV (register) (A8-486)
18744 MOV Rd, Rm (Encoding T1). */
18751 }
18755 {
18756 /* A8.8.221 SUB (immediate) (A8-708)
18757 SUB Rd, Rn, #value (Encoding T3). */
18767 }
18772 {
18773 /* A8.8.332 VLDM (A8-922)
18774 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18783 }
18788 {
18789 /* A8.8.332 VLDM (A8-922)
18790 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18798 }
18802 {
18803 /* A8.8.247 UDF (A8-758)
18804 Undefined (Encoding T2). */
18810 }
18814 {
18815 /* A8.8.247 UDF (A8-758)
18816 Undefined (Encoding T1). */
18821 }
18823 /* Functions writing an instruction in memory, returning the next
18824 memory position to write to. */
18829 {
18832 }
18837 {
18840 }
18842 /* Function filling up a region in memory with T1 and T2 UDFs taking
18843 care of alignment. */
18851 {
18854 /* Fill the remaining of the stub with deterministic contents : UDF
18855 instructions.
18856 Check if realignment is needed on modulo 4 frontier using T1, to
18857 further use T2. */
18861 current_stub_contents =
18866 current_stub_contents =
18871 }
18873 /* Functions writing the stream of instructions equivalent to the
18874 derived sequence for ldmia, ldmdb, vldm respectively. */
18876 static void
18882 {
18895 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18896 smaller than 8 registers load sequences that do not cause the
18897 hardware issue. */
18899 {
18900 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18901 current_stub_contents =
18903 initial_insn);
18905 /* B initial_insn_addr+4. */
18907 current_stub_contents =
18909 create_instruction_branch_absolute
18912 /* Fill the remaining of the stub with deterministic contents. */
18913 current_stub_contents =
18916 base_stub_contents +
18917 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18920 }
18922 /* - reg_list[13] == 0. */
18925 /* - reg_list[14] & reg_list[15] != 1. */
18928 /* - if (wback==1) reg_list[rn] == 0. */
18931 /* - nb_registers > 8. */
18934 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18936 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18937 - One with the 7 lowest registers (register mask 0x007F)
18938 This LDM will finally contain between 2 and 7 registers
18939 - One with the 7 highest registers (register mask 0xDF80)
18940 This ldm will finally contain between 2 and 7 registers. */
18944 /* A spare register may be needed during this veneer to temporarily
18945 handle the base register. This register will be restored with the
18946 last LDM operation.
18947 The usable register may be any general purpose register (that
18948 excludes PC, SP, LR : register mask is 0x1FFF). */
18951 /* Generate the stub function. */
18953 {
18954 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18955 current_stub_contents =
18957 create_instruction_ldmia
18960 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18961 current_stub_contents =
18963 create_instruction_ldmia
18966 {
18967 /* B initial_insn_addr+4. */
18968 current_stub_contents =
18970 create_instruction_branch_absolute
18972 }
18973 }
18975 {
18978 /* If Rn is not part of the high-register-list, move it there. */
18980 {
18981 /* Choose a Ri in the high-register-list that will be restored. */
18984 /* MOV Ri, Rn. */
18985 current_stub_contents =
18988 }
18990 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18991 current_stub_contents =
18993 create_instruction_ldmia
18996 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18997 current_stub_contents =
18999 create_instruction_ldmia
19003 {
19004 /* B initial_insn_addr+4. */
19005 current_stub_contents =
19007 create_instruction_branch_absolute
19009 }
19010 }
19012 /* Fill the remaining of the stub with deterministic contents. */
19013 current_stub_contents =
19016 base_stub_contents +
19017 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19018 }
19020 static void
19026 {
19039 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19040 smaller than 8 registers load sequences that do not cause the
19041 hardware issue. */
19043 {
19044 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19045 current_stub_contents =
19047 initial_insn);
19049 /* B initial_insn_addr+4. */
19050 current_stub_contents =
19052 create_instruction_branch_absolute
19055 /* Fill the remaining of the stub with deterministic contents. */
19056 current_stub_contents =
19059 base_stub_contents +
19060 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19063 }
19065 /* - reg_list[13] == 0. */
19068 /* - reg_list[14] & reg_list[15] != 1. */
19071 /* - if (wback==1) reg_list[rn] == 0. */
19074 /* - nb_registers > 8. */
19077 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19079 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19080 - One with the 7 lowest registers (register mask 0x007F)
19081 This LDM will finally contain between 2 and 7 registers
19082 - One with the 7 highest registers (register mask 0xDF80)
19083 This ldm will finally contain between 2 and 7 registers. */
19087 /* A spare register may be needed during this veneer to temporarily
19088 handle the base register. This register will be restored with
19089 the last LDM operation.
19090 The usable register may be any general purpose register (that excludes
19091 PC, SP, LR : register mask is 0x1FFF). */
19094 /* Generate the stub function. */
19096 {
19097 /* Choose a Ri in the low-register-list that will be restored. */
19100 /* MOV Ri, Rn. */
19101 current_stub_contents =
19105 /* LDMDB Ri!, {R-high-register-list}. */
19106 current_stub_contents =
19108 create_instruction_ldmdb
19111 /* LDMDB Ri, {R-low-register-list}. */
19112 current_stub_contents =
19114 create_instruction_ldmdb
19117 /* B initial_insn_addr+4. */
19118 current_stub_contents =
19120 create_instruction_branch_absolute
19122 }
19124 {
19125 /* LDMDB Rn!, {R-high-register-list}. */
19126 current_stub_contents =
19128 create_instruction_ldmdb
19131 /* LDMDB Rn!, {R-low-register-list}. */
19132 current_stub_contents =
19134 create_instruction_ldmdb
19137 /* B initial_insn_addr+4. */
19138 current_stub_contents =
19140 create_instruction_branch_absolute
19142 }
19144 {
19145 /* Choose a Ri in the high-register-list that will be restored. */
19148 /* SUB Ri, Rn, #(4*nb_registers). */
19149 current_stub_contents =
19153 /* LDMIA Ri!, {R-low-register-list}. */
19154 current_stub_contents =
19156 create_instruction_ldmia
19159 /* LDMIA Ri, {R-high-register-list}. */
19160 current_stub_contents =
19162 create_instruction_ldmia
19164 }
19166 {
19167 /* Choose a Ri in the high-register-list that will be restored. */
19170 /* SUB Rn, Rn, #(4*nb_registers) */
19171 current_stub_contents =
19175 /* MOV Ri, Rn. */
19176 current_stub_contents =
19180 /* LDMIA Ri!, {R-low-register-list}. */
19181 current_stub_contents =
19183 create_instruction_ldmia
19186 /* LDMIA Ri, {R-high-register-list}. */
19187 current_stub_contents =
19189 create_instruction_ldmia
19191 }
19193 {
19196 {
19197 /* Choose a Ri in the low-register-list that will be restored. */
19200 /* MOV Ri, Rn. */
19201 current_stub_contents =
19204 }
19206 /* LDMDB Ri!, {R-high-register-list}. */
19207 current_stub_contents =
19209 create_instruction_ldmdb
19212 /* LDMDB Ri, {R-low-register-list}. */
19213 current_stub_contents =
19215 create_instruction_ldmdb
19218 /* B initial_insn_addr+4. */
19219 current_stub_contents =
19221 create_instruction_branch_absolute
19223 }
19225 {
19228 {
19229 /* Choose a Ri in the high-register-list that will be restored. */
19231 }
19233 /* SUB Ri, Rn, #(4*nb_registers). */
19234 current_stub_contents =
19238 /* LDMIA Ri!, {R-low-register-list}. */
19239 current_stub_contents =
19241 create_instruction_ldmia
19244 /* LDMIA Ri, {R-high-register-list}. */
19245 current_stub_contents =
19247 create_instruction_ldmia
19249 }
19251 {
19252 /* The assembler should not have accepted to encode this. */
19255 }
19257 /* Fill the remaining of the stub with deterministic contents. */
19258 current_stub_contents =
19261 base_stub_contents +
19262 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19264 }
19266 static void
19272 {
19278 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19279 smaller than 8 words load sequences that do not cause the
19280 hardware issue. */
19282 {
19283 /* Untouched instruction. */
19284 current_stub_contents =
19286 initial_insn);
19288 /* B initial_insn_addr+4. */
19289 current_stub_contents =
19291 create_instruction_branch_absolute
19293 }
19294 else
19295 {
19305 /* d = UInt (Vd:D);. */
19309 /* Compute the number of 8-words chunks needed to split. */
19313 /* The test coverage has been done assuming the following
19314 hypothesis that exactly one of the previous is_ predicates is
19315 true. */
19319 /* We treat the cutting of the words in one pass for all
19320 cases, then we emit the adjustments:
19322 vldm rx, {...}
19323 -> vldm rx!, {8_words_or_less} for each needed 8_word
19324 -> sub rx, rx, #size (list)
19326 vldm rx!, {...}
19327 -> vldm rx!, {8_words_or_less} for each needed 8_word
19328 This also handles vpop instruction (when rx is sp)
19330 vldmd rx!, {...}
19331 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19333 {
19337 {
19338 new_insn = create_instruction_vldmia
19340 is_dp,
19345 }
19347 {
19348 new_insn = create_instruction_vldmdb
19350 is_dp,
19354 }
19357 current_stub_contents =
19359 new_insn);
19360 }
19362 /* Only this case requires the base register compensation
19363 subtract. */
19365 {
19366 current_stub_contents =
19368 create_instruction_sub
19370 }
19372 /* B initial_insn_addr+4. */
19373 current_stub_contents =
19375 create_instruction_branch_absolute
19377 }
19379 /* Fill the remaining of the stub with deterministic contents. */
19380 current_stub_contents =
19383 base_stub_contents +
19384 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19385 }
19387 static void
19393 {
19397 stub_contents);
19401 stub_contents);
19405 stub_contents);
19406 }
19408 /* End of stm32l4xx work-around. */
19411 /* Do code byteswapping. Return FALSE afterwards so that the section is
19412 written out as normal. */
19414 static bool
19419 {
19426 bfd_vma ptr;
19427 bfd_vma end;
19429 bfd_byte tmp;
19435 /* If this section has not been allocated an _arm_elf_section_data
19436 structure then we cannot record anything. */
19446 {
19451 {
19455 {
19457 {
19458 bfd_vma branch_to_veneer;
19459 /* Original condition code of instruction, plus bit mask for
19460 ARM B instruction. */
19464 /* The instruction is before the label. */
19467 /* Above offset included in -4 below. */
19481 }
19485 {
19486 bfd_vma branch_from_veneer;
19489 /* Take size of veneer into account. */
19498 /* Original instruction. */
19505 /* Branch back to insn after original insn. */
19511 }
19516 }
19517 }
19518 }
19521 {
19525 {
19529 {
19531 {
19533 bfd_vma branch_to_veneer =
19538 {
19539 bfd_vma out_of_range =
19545 _bfd_error_handler
19547 "cannot create STM32L4XX veneer; "
19550 output_bfd,
19554 }
19556 insn = create_instruction_branch_absolute
19559 /* The instruction is before the label. */
19564 }
19568 {
19574 veneer_r = veneer
19579 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19580 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19581 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19584 {
19588 }
19590 /* Original instruction. */
19593 stm32l4xx_create_replacing_stub
19595 }
19600 }
19601 }
19602 }
19605 {
19606 arm_unwind_table_edit *edit_node
19608 /* Now, sec->size is the size of the section we will write. The original
19609 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19610 markers) was sec->rawsize. (This isn't the case if we perform no
19611 edits, then rawsize will be zero and we should use size). */
19620 {
19622 {
19626 {
19629 out_index++;
19630 in_index++;
19631 }
19635 {
19637 {
19639 in_index++;
19644 {
19652 /* Note: this is meant to be equivalent to an
19653 R_ARM_PREL31 relocation. These synthetic
19654 EXIDX_CANTUNWIND markers are not relocated by the
19655 usual BFD method. */
19659 {
19660 /* Here relocation for new EXIDX_CANTUNWIND is
19661 created, so there is no need to
19662 adjust offset by hand. */
19665 }
19667 /* First address we can't unwind. */
19671 /* Code for EXIDX_CANTUNWIND. */
19675 out_index++;
19677 }
19679 }
19682 }
19683 }
19684 else
19685 {
19686 /* No more edits, copy remaining entries verbatim. */
19689 out_index++;
19690 in_index++;
19691 }
19692 }
19696 edited_contents,
19700 }
19702 /* Fix code to point to Cortex-A8 erratum stubs. */
19704 {
19712 }
19718 {
19723 {
19726 else
19730 {
19732 /* Byte swap code words. */
19734 {
19742 }
19746 /* Byte swap code halfwords. */
19748 {
19753 }
19757 /* Leave data alone. */
19759 }
19761 }
19762 }
19770 }
19772 /* Mangle thumb function symbols as we read them in. */
19774 static bool
19779 {
19784 /* New EABI objects mark thumb function symbols by setting the low bit of
19785 the address. */
19788 {
19790 {
19793 ST_BRANCH_TO_THUMB);
19794 }
19795 else
19797 }
19799 {
19802 }
19805 else
19809 }
19812 /* Mangle thumb function symbols as we write them out. */
19814 static void
19819 {
19820 Elf_Internal_Sym newsym;
19822 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19823 of the address set, as per the new EABI. We do this unconditionally
19824 because objcopy does not set the elf header flags until after
19825 it writes out the symbol table. */
19827 {
19832 {
19833 /* Do this only for defined symbols. At link type, the static
19834 linker will simulate the work of dynamic linker of resolving
19835 symbols and will carry over the thumbness of found symbols to
19836 the output symbol table. It's not clear how it happens, but
19837 the thumbness of undefined symbols can well be different at
19838 runtime, and writing '1' for them will be confusing for users
19839 and possibly for dynamic linker itself.
19840 */
19842 }
19845 }
19847 }
19849 /* Add the PT_ARM_EXIDX program header. */
19851 static bool
19854 {
19860 {
19861 /* If there is already a PT_ARM_EXIDX header, then we do not
19862 want to add another one. This situation arises when running
19863 "strip"; the input binary already has the header. */
19868 {
19879 }
19880 }
19883 }
19885 /* We may add a PT_ARM_EXIDX program header. */
19887 static int
19890 {
19896 else
19898 }
19900 /* Hook called by the linker routine which adds symbols from an object
19901 file. */
19903 static bool
19907 {
19917 }
19919 /* We use this to override swap_symbol_in and swap_symbol_out. */
19921 {
19934 bfd_elf32_write_out_phdrs,
19935 bfd_elf32_write_shdrs_and_ehdr,
19936 bfd_elf32_checksum_contents,
19937 bfd_elf32_write_relocs,
19938 elf32_arm_swap_symbol_in,
19939 elf32_arm_swap_symbol_out,
19940 bfd_elf32_slurp_reloc_table,
19941 bfd_elf32_slurp_symbol_table,
19942 bfd_elf32_swap_dyn_in,
19943 bfd_elf32_swap_dyn_out,
19944 bfd_elf32_swap_reloc_in,
19945 bfd_elf32_swap_reloc_out,
19946 bfd_elf32_swap_reloca_in,
19947 bfd_elf32_swap_reloca_out
19948 };
19950 static bfd_vma
19952 {
19953 /* V7 BE8 code is always little endian. */
19958 }
19960 static bfd_vma
19962 {
19963 /* V7 BE8 code is always little endian. */
19968 }
19970 /* Return size of plt0 entry starting at ADDR
19971 or (bfd_vma) -1 if size can not be determined. */
19973 static bfd_vma
19975 bfd_size_type data_size)
19976 {
19977 bfd_vma first_word;
19978 bfd_vma plt0_size;
19989 else
19990 /* We don't yet handle this PLT format. */
19994 }
19996 /* Return size of plt entry starting at offset OFFSET
19997 of plt section located at address START
19998 or (bfd_vma) -1 if size can not be determined. */
20000 static bfd_vma
20002 bfd_size_type data_size)
20003 {
20004 bfd_vma first_insn;
20007 /* PLT entry size if fixed on Thumb-only platforms. */
20011 /* Respect Thumb stub if necessary. */
20015 {
20017 }
20019 /* Strip immediate from first add. */
20024 #ifdef FOUR_WORD_PLT
20027 #else
20032 #endif
20033 else
20034 /* We don't yet handle this PLT format. */
20038 }
20040 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20042 static long
20049 {
20058 bfd_vma offset;
20093 {
20097 }
20102 {
20105 }
20111 {
20119 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20120 we are defining a symbol, ensure one of them is set. */
20132 {
20139 ;
20143 }
20148 }
20152 }
20154 static bool
20156 {
20160 }
20162 static flagword
20164 {
20169 }
20171 static unsigned int
20173 {
20178 }
20180 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20181 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20182 FALSE otherwise. ISECTION is the best guess matching section from the
20183 input bfd IBFD, but it might be NULL. */
20185 static bool
20190 {
20192 {
20194 {
20202 /* The sh_link field must be set to the text section associated with
20203 this index section. Unfortunately the ARM EHABI does not specify
20204 exactly how to determine this association. Our caller does try
20205 to match up OSECTION with its corresponding input section however
20206 so that is a good first guess. */
20217 )
20218 {
20223 }
20226 {
20227 /* Failing that we have to find a matching section ourselves. If
20228 we had the output section name available we could compare that
20229 with input section names. Unfortunately we don't. So instead
20230 we use a simple heuristic and look for the nearest executable
20231 section before this one. */
20243 }
20246 {
20248 /* If the text section was part of a group
20249 then the index section should be too. */
20253 }
20254 }
20266 }
20269 }
20271 /* Returns TRUE if NAME is an ARM mapping symbol.
20272 Traditionally the symbols $a, $d and $t have been used.
20273 The ARM ELF standard also defines $x (for A64 code). It also allows a
20274 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20275 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20276 not support them here. $t.x indicates the start of ThumbEE instructions. */
20278 static bool
20280 {
20283 the mapping symbols could have acquired a prefix.
20284 We do not support this here, since such symbols no
20285 longer conform to the ARM ELF ABI. */
20288 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20289 any characters that follow the period are legal characters for the body
20290 of a symbol's name. For now we just assume that this is the case. */
20291 }
20293 /* Make sure that mapping symbols in object files are not removed via the
20294 "strip --strip-unneeded" tool. These symbols are needed in order to
20295 correctly generate interworking veneers, and for byte swapping code
20296 regions. Once an object file has been linked, it is safe to remove the
20297 symbols as they will no longer be needed. */
20299 static void
20301 {
20306 }
20308 #undef elf_backend_copy_special_section_fields
20309 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20311 #define ELF_ARCH bfd_arch_arm
20312 #define ELF_TARGET_ID ARM_ELF_DATA
20313 #define ELF_MACHINE_CODE EM_ARM
20314 #define ELF_MAXPAGESIZE 0x1000
20315 #define ELF_COMMONPAGESIZE 0x1000
20317 #define bfd_elf32_mkobject elf32_arm_mkobject
20319 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20320 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20321 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20322 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20323 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20324 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20325 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20326 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20327 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20328 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20329 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20330 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20332 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20333 #define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
20334 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20335 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20336 #define elf_backend_check_relocs elf32_arm_check_relocs
20337 #define elf_backend_update_relocs elf32_arm_update_relocs
20338 #define elf_backend_relocate_section elf32_arm_relocate_section
20339 #define elf_backend_write_section elf32_arm_write_section
20340 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20341 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20342 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20343 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20344 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
20345 #define elf_backend_always_size_sections elf32_arm_always_size_sections
20346 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20347 #define elf_backend_init_file_header elf32_arm_init_file_header
20348 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20349 #define elf_backend_object_p elf32_arm_object_p
20350 #define elf_backend_fake_sections elf32_arm_fake_sections
20351 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20352 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20353 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20354 #define elf_backend_size_info elf32_arm_size_info
20355 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20356 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20357 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20358 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20359 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20360 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20361 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20362 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20364 #define elf_backend_can_refcount 1
20365 #define elf_backend_can_gc_sections 1
20366 #define elf_backend_plt_readonly 1
20367 #define elf_backend_want_got_plt 1
20368 #define elf_backend_want_plt_sym 0
20369 #define elf_backend_want_dynrelro 1
20370 #define elf_backend_may_use_rel_p 1
20371 #define elf_backend_may_use_rela_p 0
20372 #define elf_backend_default_use_rela_p 0
20373 #define elf_backend_dtrel_excludes_plt 1
20375 #define elf_backend_got_header_size 12
20376 #define elf_backend_extern_protected_data 0
20378 #undef elf_backend_obj_attrs_vendor
20380 #undef elf_backend_obj_attrs_section
20382 #undef elf_backend_obj_attrs_arg_type
20383 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20384 #undef elf_backend_obj_attrs_section_type
20385 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20386 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20387 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20389 #undef elf_backend_section_flags
20390 #define elf_backend_section_flags elf32_arm_section_flags
20391 #undef elf_backend_lookup_section_flags_hook
20392 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20394 #define elf_backend_linux_prpsinfo32_ugid16 true
20398 /* Native Client targets. */
20400 #undef TARGET_LITTLE_SYM
20401 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20402 #undef TARGET_LITTLE_NAME
20404 #undef TARGET_BIG_SYM
20405 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20406 #undef TARGET_BIG_NAME
20409 /* Like elf32_arm_link_hash_table_create -- but overrides
20410 appropriately for NaCl. */
20414 {
20419 {
20425 }
20427 }
20429 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20430 really need to use elf32_arm_modify_segment_map. But we do it
20431 anyway just to reduce gratuitous differences with the stock ARM backend. */
20433 static bool
20435 {
20438 }
20440 static bool
20442 {
20445 }
20447 static bfd_vma
20450 {
20454 }
20456 #undef elf32_bed
20457 #define elf32_bed elf32_arm_nacl_bed
20458 #undef bfd_elf32_bfd_link_hash_table_create
20459 #define bfd_elf32_bfd_link_hash_table_create \
20460 elf32_arm_nacl_link_hash_table_create
20461 #undef elf_backend_plt_alignment
20462 #define elf_backend_plt_alignment 4
20463 #undef elf_backend_modify_segment_map
20464 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20465 #undef elf_backend_modify_headers
20466 #define elf_backend_modify_headers nacl_modify_headers
20467 #undef elf_backend_final_write_processing
20468 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20469 #undef bfd_elf32_get_synthetic_symtab
20470 #undef elf_backend_plt_sym_val
20471 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20472 #undef elf_backend_copy_special_section_fields
20474 #undef ELF_MINPAGESIZE
20475 #undef ELF_COMMONPAGESIZE
20477 #undef ELF_TARGET_OS
20478 #define ELF_TARGET_OS is_nacl
20482 /* Reset to defaults. */
20483 #undef elf_backend_plt_alignment
20484 #undef elf_backend_modify_segment_map
20485 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20486 #undef elf_backend_modify_headers
20487 #undef elf_backend_final_write_processing
20488 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20489 #undef ELF_MINPAGESIZE
20490 #undef ELF_COMMONPAGESIZE
20491 #define ELF_COMMONPAGESIZE 0x1000
20494 /* FDPIC Targets. */
20496 #undef TARGET_LITTLE_SYM
20497 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20498 #undef TARGET_LITTLE_NAME
20500 #undef TARGET_BIG_SYM
20501 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20502 #undef TARGET_BIG_NAME
20504 #undef elf_match_priority
20505 #define elf_match_priority 128
20506 #undef ELF_OSABI
20507 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20509 /* Like elf32_arm_link_hash_table_create -- but overrides
20510 appropriately for FDPIC. */
20514 {
20519 {
20523 }
20525 }
20527 /* We need dynamic symbols for every section, since segments can
20528 relocate independently. */
20529 static bool
20532 ATTRIBUTE_UNUSED,
20534 {
20536 {
20539 /* If sh_type is yet undecided, assume it could be
20540 SHT_PROGBITS/SHT_NOBITS. */
20544 /* There shouldn't be section relative relocations
20545 against any other section. */
20548 }
20549 }
20551 #undef elf32_bed
20552 #define elf32_bed elf32_arm_fdpic_bed
20554 #undef bfd_elf32_bfd_link_hash_table_create
20555 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20557 #undef elf_backend_omit_section_dynsym
20558 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20560 #undef ELF_TARGET_OS
20564 #undef elf_match_priority
20565 #undef ELF_OSABI
20566 #undef elf_backend_omit_section_dynsym
20568 /* VxWorks Targets. */
20570 #undef TARGET_LITTLE_SYM
20571 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20572 #undef TARGET_LITTLE_NAME
20574 #undef TARGET_BIG_SYM
20575 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20576 #undef TARGET_BIG_NAME
20579 /* Like elf32_arm_link_hash_table_create -- but overrides
20580 appropriately for VxWorks. */
20584 {
20589 {
20593 }
20595 }
20597 static bool
20599 {
20602 }
20604 #undef elf32_bed
20605 #define elf32_bed elf32_arm_vxworks_bed
20607 #undef bfd_elf32_bfd_link_hash_table_create
20608 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20609 #undef elf_backend_final_write_processing
20610 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20611 #undef elf_backend_emit_relocs
20612 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20614 #undef elf_backend_may_use_rel_p
20615 #define elf_backend_may_use_rel_p 0
20616 #undef elf_backend_may_use_rela_p
20617 #define elf_backend_may_use_rela_p 1
20618 #undef elf_backend_default_use_rela_p
20619 #define elf_backend_default_use_rela_p 1
20620 #undef elf_backend_want_plt_sym
20621 #define elf_backend_want_plt_sym 1
20622 #undef ELF_MAXPAGESIZE
20623 #define ELF_MAXPAGESIZE 0x1000
20624 #undef ELF_TARGET_OS
20625 #define ELF_TARGET_OS is_vxworks
20630 /* Merge backend specific data from an object file to the output
20631 object file when linking. */
20633 static bool
20635 {
20637 flagword out_flags;
20638 flagword in_flags;
20642 /* Check if we have the same endianness. */
20652 /* The input BFD must have had its flags initialised. */
20653 /* The following seems bogus to me -- The flags are initialized in
20654 the assembler but I don't think an elf_flags_init field is
20655 written into the object. */
20656 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20661 /* In theory there is no reason why we couldn't handle this. However
20662 in practice it isn't even close to working and there is no real
20663 reason to want it. */
20667 {
20669 ibfd);
20671 }
20674 {
20675 /* If the input has no flags set, then do not set the output flags.
20676 This will allow future bfds to determine the desired output flags.
20677 If no input bfds have any flags set, then neither will the output bfd.
20679 Note - we used to restrict this test to when the input architecture
20680 variant was the default variant, but this does not allow for
20681 linker scripts which override the default. See PR 28910 for an
20682 example. */
20694 }
20696 /* Determine what should happen if the input ARM architecture
20697 does not match the output ARM architecture. */
20701 /* Identical flags must be compatible. */
20705 /* Check to see if the input BFD actually contains any sections. If
20706 not, its flags may not have been initialised either, but it
20707 cannot actually cause any incompatiblity. Do not short-circuit
20708 dynamic objects; their section list may be emptied by
20709 elf_link_add_object_symbols.
20711 Also check to see if there are no code sections in the input.
20712 In this case there is no need to check for code specific flags.
20713 XXX - do we need to worry about floating-point format compatability
20714 in data sections ? */
20716 {
20721 {
20722 /* Ignore synthetic glue sections. */
20725 {
20733 }
20734 }
20738 }
20740 /* Complain about various flag mismatches. */
20743 {
20744 _bfd_error_handler
20749 }
20751 /* Not sure what needs to be checked for EABI versions >= 1. */
20752 /* VxWorks libraries do not use these flags. */
20756 {
20758 {
20759 _bfd_error_handler
20764 }
20767 {
20769 _bfd_error_handler
20770 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20772 else
20773 _bfd_error_handler
20774 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20778 }
20781 {
20783 _bfd_error_handler
20786 else
20787 _bfd_error_handler
20792 }
20795 {
20797 _bfd_error_handler
20800 else
20801 _bfd_error_handler
20806 }
20808 #ifdef EF_ARM_SOFT_FLOAT
20810 {
20811 /* We can allow interworking between code that is VFP format
20812 layout, and uses either soft float or integer regs for
20813 passing floating point arguments and results. We already
20814 know that the APCS_FLOAT flags match; similarly for VFP
20815 flags. */
20818 {
20820 _bfd_error_handler
20823 else
20824 _bfd_error_handler
20829 }
20830 }
20831 #endif
20833 /* Interworking mismatch is only a warning. */
20835 {
20837 {
20838 _bfd_error_handler
20841 }
20842 else
20843 {
20844 _bfd_error_handler
20847 }
20848 }
20849 }
20852 }