Improve readelf's display of RELR relocs.

[binutils-gdb.git] / ld / testsuite / ld-x86-64 / apx-load1c.d

#source: apx-load1.s
#as: --64
#ld: -shared -melf_x86_64 --hash-style=sysv -z max-page-size=0x200000 -z noseparate-code $NO_DT_RELR_LDFLAGS
#objdump: -dw

.*: +file format .*

Disassembly of section .text:

0+188 <_start>:
 +[a-f0-9]+:    d5 40 13 05 f8 01 20 00         adc    0x2001f8\(%rip\),%r16d        # 200388 <.*>
 +[a-f0-9]+:    d5 40 03 0d f0 01 20 00         add    0x2001f0\(%rip\),%r17d        # 200388 <.*>
 +[a-f0-9]+:    d5 40 23 15 e8 01 20 00         and    0x2001e8\(%rip\),%r18d        # 200388 <.*>
 +[a-f0-9]+:    d5 40 3b 1d e0 01 20 00         cmp    0x2001e0\(%rip\),%r19d        # 200388 <.*>
 +[a-f0-9]+:    d5 40 0b 25 d8 01 20 00         or     0x2001d8\(%rip\),%r20d        # 200388 <.*>
 +[a-f0-9]+:    d5 40 1b 2d d0 01 20 00         sbb    0x2001d0\(%rip\),%r21d        # 200388 <.*>
 +[a-f0-9]+:    d5 40 2b 35 c8 01 20 00         sub    0x2001c8\(%rip\),%r22d        # 200388 <.*>
 +[a-f0-9]+:    d5 40 33 3d c0 01 20 00         xor    0x2001c0\(%rip\),%r23d        # 200388 <.*>
 +[a-f0-9]+:    d5 44 85 05 b8 01 20 00         test   %r24d,0x2001b8\(%rip\)        # 200388 <.*>
 +[a-f0-9]+:    d5 48 13 05 b0 01 20 00         adc    0x2001b0\(%rip\),%r16        # 200388 <.*>
 +[a-f0-9]+:    d5 48 03 0d a8 01 20 00         add    0x2001a8\(%rip\),%r17        # 200388 <.*>
 +[a-f0-9]+:    d5 48 23 15 a0 01 20 00         and    0x2001a0\(%rip\),%r18        # 200388 <.*>
 +[a-f0-9]+:    d5 48 3b 1d 98 01 20 00         cmp    0x200198\(%rip\),%r19        # 200388 <.*>
 +[a-f0-9]+:    d5 48 0b 25 90 01 20 00         or     0x200190\(%rip\),%r20        # 200388 <.*>
 +[a-f0-9]+:    d5 48 1b 2d 88 01 20 00         sbb    0x200188\(%rip\),%r21        # 200388 <.*>
 +[a-f0-9]+:    d5 48 2b 35 80 01 20 00         sub    0x200180\(%rip\),%r22        # 200388 <.*>
 +[a-f0-9]+:    d5 48 33 3d 78 01 20 00         xor    0x200178\(%rip\),%r23        # 200388 <.*>
 +[a-f0-9]+:    d5 4c 85 05 70 01 20 00         test   %r24,0x200170\(%rip\)        # 200388 <.*>
 +[a-f0-9]+:    d5 40 13 05 70 01 20 00         adc    0x200170\(%rip\),%r16d        # 200390 <.*>
 +[a-f0-9]+:    d5 40 03 0d 68 01 20 00         add    0x200168\(%rip\),%r17d        # 200390 <.*>
 +[a-f0-9]+:    d5 40 23 15 60 01 20 00         and    0x200160\(%rip\),%r18d        # 200390 <.*>
 +[a-f0-9]+:    d5 40 3b 1d 58 01 20 00         cmp    0x200158\(%rip\),%r19d        # 200390 <.*>
 +[a-f0-9]+:    d5 40 0b 25 50 01 20 00         or     0x200150\(%rip\),%r20d        # 200390 <.*>
 +[a-f0-9]+:    d5 40 1b 2d 48 01 20 00         sbb    0x200148\(%rip\),%r21d        # 200390 <.*>
 +[a-f0-9]+:    d5 40 2b 35 40 01 20 00         sub    0x200140\(%rip\),%r22d        # 200390 <.*>
 +[a-f0-9]+:    d5 40 33 3d 38 01 20 00         xor    0x200138\(%rip\),%r23d        # 200390 <.*>
 +[a-f0-9]+:    d5 44 85 05 30 01 20 00         test   %r24d,0x200130\(%rip\)        # 200390 <.*>
 +[a-f0-9]+:    d5 48 13 05 28 01 20 00         adc    0x200128\(%rip\),%r16        # 200390 <.*>
 +[a-f0-9]+:    d5 48 03 0d 20 01 20 00         add    0x200120\(%rip\),%r17        # 200390 <.*>
 +[a-f0-9]+:    d5 48 23 15 18 01 20 00         and    0x200118\(%rip\),%r18        # 200390 <.*>
 +[a-f0-9]+:    d5 48 3b 1d 10 01 20 00         cmp    0x200110\(%rip\),%r19        # 200390 <.*>
 +[a-f0-9]+:    d5 48 0b 25 08 01 20 00         or     0x200108\(%rip\),%r20        # 200390 <.*>
 +[a-f0-9]+:    d5 48 1b 2d 00 01 20 00         sbb    0x200100\(%rip\),%r21        # 200390 <.*>
 +[a-f0-9]+:    d5 48 2b 35 f8 00 20 00         sub    0x2000f8\(%rip\),%r22        # 200390 <.*>
 +[a-f0-9]+:    d5 48 33 3d f0 00 20 00         xor    0x2000f0\(%rip\),%r23        # 200390 <.*>
 +[a-f0-9]+:    d5 4c 85 05 e8 00 20 00         test   %r24,0x2000e8\(%rip\)        # 200390 <.*>
#pass