1 2023-10-05 Neal frager <neal.frager@amd.com>
3 * microblaze-opcm.h (struct op_code_struct): Tidy and remove
5 * microblaze-opc.h (MAX_OPCODES): Increase to 300.
6 (op_code_struct): Add address extension instructions.
8 2023-10-04 Neal frager <neal.frager@amd.com>
10 * microblaze-opc.h (struct op_code_struct): Add hiberante
12 * microblaze-opcm.h (enum microblaze_instr): Add microblaze_sleep,
13 hibernate, suspend entries.
15 2023-08-24 Tom Tromey <tom@tromey.com>
17 * cgen.sh: Don't pass "-s" to cgen.
18 * Makefile.in: Rebuild.
19 * Makefile.am (GUILE): Simplify.
21 2023-07-31 Jose E. Marchesi <jose.marchesi@oracle.com>
24 * bpf-dis.c (print_insn_bpf): Check that info->section->owner is
25 actually available before using it.
27 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
29 * bpf-dis.c: Initialize asm_bpf_version to -1.
30 (print_insn_bpf): Set BPF ISA version from the cpu version ELF
31 header flags if no explicit version set in the command line.
32 * disassemble.c (disassemble_init_for_target): Remove unused code.
34 2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
36 * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
39 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
41 * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
44 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
46 * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
49 2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
51 * bpf-opc.c (bpf_opcodes): Add entry for jal.
53 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
55 * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
58 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
60 * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
61 MOVS32{8,16,32}R instructions. and MOVS32I instructions.
63 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
65 * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
66 * Makefile.in: Regenerate.
68 2023-07-03 Nick Clifton <nickc@redhat.com>
70 * configure: Regenerate.
71 * po/opcodes.pot: Regenerate.
73 2023-07-03 Nick Clifton <nickc@redhat.com>
77 2023-05-23 Nick Clifton <nickc@redhat.com>
79 * po/sv.po: Updated translation.
81 2023-04-21 Tom Tromey <tromey@adacore.com>
83 * i386-dis.c (OP_J): Check result of get16.
85 2023-04-12 Claudiu Zissulescu <claziss@synopsys.com>
87 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
88 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
89 vsubs2h, and vsubs4h instructions.
91 2023-04-11 Nick Clifton <nickc@redhat.com>
94 * nfp-dis.c (init_nfp6000_priv): Check that the output section
97 2023-03-15 Nick Clifton <nickc@redhat.com>
100 * mep-dis.c: Regenerate.
102 2023-03-15 Nick Clifton <nickc@redhat.com>
105 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
107 2023-02-28 Richard Ball <richard.ball@arm.com>
109 * aarch64-opc.c: Add MEC system registers.
111 2023-01-03 Nick Clifton <nickc@redhat.com>
113 * po/de.po: Updated German translation.
114 * po/ro.po: Updated Romainian translation.
115 * po/uk.po: Updated Ukrainian translation.
117 2022-12-31 Nick Clifton <nickc@redhat.com>
119 * 2.40 branch created.
121 2022-11-22 Shahab Vahedi <shahab@synopsys.com>
123 * arc-regs.h: Change isa_config address to 0xc1.
124 isa_config exists for ARC700 and ARCV2 and not ARCALL.
126 2022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
128 * rx-decode.opc: Switch arguments of the MVTACGU insn.
129 * rx-decode.c: Regenerate.
131 2022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
133 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
134 Rm_BANK,Rn is always 1.
136 2022-07-21 Peter Bergner <bergner@linux.ibm.com>
138 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
139 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
140 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
141 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
142 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
143 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
144 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
146 2022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
148 * disassemble.c (disassemble_init_for_target): Set
149 created_styled_output for ARC based targets.
150 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
151 instead of fprintf_ftype throughout.
152 (find_format): Likewise.
153 (print_flags): Likewise.
154 (print_insn_arc): Likewise.
156 2022-07-08 Nick Clifton <nickc@redhat.com>
158 * 2.39 branch created.
160 2022-07-04 Marcus Nilsson <brainbomb@gmail.com>
162 * disassemble.c: (disassemble_init_for_target): Set
163 created_styled_output for AVR based targets.
164 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
165 instead of fprintf_ftype throughout.
166 (avr_operand): Pass in and fill disassembler_style when
169 2022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
171 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
174 2022-03-16 Simon Marchi <simon.marchi@efficios.com>
176 * configure.ac: Handle bfd_amdgcn_arch.
177 * configure: Re-generate.
179 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
180 Maciej W. Rozycki <macro@orcam.me.uk>
182 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
183 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
184 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
187 2022-02-17 Nick Clifton <nickc@redhat.com>
189 * po/sr.po: Updated Serbian translation.
191 2022-02-14 Sergei Trofimovich <siarheit@google.com>
193 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
194 * microblaze-opc.h: Follow 'fsqrt' rename.
196 2022-01-24 Nick Clifton <nickc@redhat.com>
198 * po/ro.po: Updated Romanian translation.
199 * po/uk.po: Updated Ukranian translation.
201 2022-01-22 Nick Clifton <nickc@redhat.com>
203 * configure: Regenerate.
204 * po/opcodes.pot: Regenerate.
206 2022-01-22 Nick Clifton <nickc@redhat.com>
208 * 2.38 release branch created.
210 2022-01-17 Nick Clifton <nickc@redhat.com>
212 * Makefile.in: Regenerate.
213 * po/opcodes.pot: Regenerate.
215 2021-12-02 Marcus Nilsson <brainbomb@gmail.com>
217 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
218 in insn_type on branching instructions.
220 2021-11-25 Andrew Burgess <aburgess@redhat.com>
221 Simon Cook <simon.cook@embecosm.com>
223 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
224 (riscv_options): New static global.
225 (disassembler_options_riscv): New function.
226 (print_riscv_disassembler_options): Rewrite to use
227 disassembler_options_riscv.
229 2021-11-25 Nick Clifton <nickc@redhat.com>
232 * aarch64-asm.c: Replace assert(0) with real code.
233 * aarch64-dis.c: Likewise.
234 * aarch64-opc.c: Likewise.
236 2021-11-25 Nick Clifton <nickc@redhat.com>
238 * po/fr.po; Updated French translation.
240 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
242 * Makefile.am: Remove obsolete comment.
243 * configure.ac: Refer `libbfd.la' to link shared BFD library
245 * Makefile.in: Regenerate.
246 * configure: Regenerate.
248 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
250 * configure: Regenerate.
252 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
254 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
257 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
259 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
260 before an unknown instruction, '%d' is replaced with the
263 2021-09-02 Nick Clifton <nickc@redhat.com>
266 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
269 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
271 * arc-regs.h (DEF): Fix the register numbers.
273 2021-08-10 Nick Clifton <nickc@redhat.com>
275 * po/sr.po: Updated Serbian translation.
277 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
279 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
281 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
283 * s390-opc.txt: Add qpaci.
285 2021-07-03 Nick Clifton <nickc@redhat.com>
287 * configure: Regenerate.
288 * po/opcodes.pot: Regenerate.
290 2021-07-03 Nick Clifton <nickc@redhat.com>
292 * 2.37 release branch created.
294 2021-07-02 Alan Modra <amodra@gmail.com>
296 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
297 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
298 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
299 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
300 (nds32_keyword_gpr): Move declarations to..
301 * nds32-asm.h: ..here, constifying to match definitions.
303 2021-07-01 Mike Frysinger <vapier@gentoo.org>
305 * Makefile.am (GUILE): New variable.
306 (CGEN): Use $(GUILE).
307 * Makefile.in: Regenerate.
309 2021-07-01 Mike Frysinger <vapier@gentoo.org>
311 * mep-asm.c (macros): Mark static & const.
312 (lookup_macro): Change return & m to const.
313 (expand_macro): Change mac to const.
314 (expand_string): Change pmacro to const.
316 2021-07-01 Mike Frysinger <vapier@gentoo.org>
318 * nds32-asm.c (operand_fields): Rename to ...
319 (nds32_operand_fields): ... this.
320 (keyword_gpr): Rename to ...
321 (nds32_keyword_gpr): ... this.
322 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
323 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
324 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
325 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
326 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
328 (keywords): Rename to ...
329 (nds32_keywords): ... this.
330 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
331 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
333 2021-07-01 Mike Frysinger <vapier@gentoo.org>
335 * z80-dis.c (opc_ed): Make const.
336 (pref_ed): Make p const.
338 2021-07-01 Mike Frysinger <vapier@gentoo.org>
340 * microblaze-dis.c (get_field_special): Make op const.
341 (read_insn_microblaze): Make opr & op const. Rename opcodes to
343 (print_insn_microblaze): Make op & pop const.
344 (get_insn_microblaze): Make op const. Rename opcodes to
346 (microblaze_get_target_address): Likewise.
347 * microblaze-opc.h (struct op_code_struct): Make const.
348 Rename opcodes to microblaze_opcodes.
350 2021-07-01 Mike Frysinger <vapier@gentoo.org>
352 * aarch64-gen.c (aarch64_opcode_table): Add const.
353 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
355 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
357 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
360 2021-06-22 Alan Modra <amodra@gmail.com>
362 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
363 print separator for pcrel insns.
365 2021-06-19 Alan Modra <amodra@gmail.com>
367 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
369 2021-06-19 Alan Modra <amodra@gmail.com>
371 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
374 2021-06-17 Alan Modra <amodra@gmail.com>
376 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
379 2021-06-03 Alan Modra <amodra@gmail.com>
382 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
383 Use unsigned int for inst.
385 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
387 * arc-dis.c (arc_option_arg_t): New enumeration.
388 (arc_options): New variable.
389 (disassembler_options_arc): New function.
390 (print_arc_disassembler_options): Reimplement in terms of
391 "disassembler_options_arc".
393 2021-05-29 Alan Modra <amodra@gmail.com>
395 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
396 Don't special case PPC_OPCODE_RAW.
397 (lookup_prefix): Likewise.
398 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
399 (print_insn_powerpc): ..update caller.
400 * ppc-opc.c (EXT): Define.
401 (powerpc_opcodes): Mark extended mnemonics with EXT.
402 (prefix_opcodes, vle_opcodes): Likewise.
403 (XISEL, XISEL_MASK): Add cr field and simplify.
404 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
405 all isel variants to where the base mnemonic belongs. Sort dstt,
408 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
410 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
411 COP3 opcode instructions.
413 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
415 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
416 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
417 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
418 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
419 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
420 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
421 "cop2", and "cop3" entries.
423 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
425 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
426 entries and associated comments.
428 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
430 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
433 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
435 * mips-dis.c (mips_cp1_names_mips): New variable.
436 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
437 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
438 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
439 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
440 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
443 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
445 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
446 handling code over to...
447 <OP_REG_CONTROL>: ... this new case.
448 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
449 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
450 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
451 replacing the `G' operand code with `g'. Update "cftc1" and
452 "cftc2" entries replacing the `E' operand code with `y'.
453 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
454 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
455 entries replacing the `G' operand code with `g'.
457 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
459 * mips-dis.c (mips_cp0_names_r3900): New variable.
460 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
463 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
465 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
466 and "mtthc2" to using the `G' rather than `g' operand code for
467 the coprocessor control register referred.
469 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
471 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
472 entries with each other.
474 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
476 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
478 2021-05-25 Alan Modra <amodra@gmail.com>
480 * cris-desc.c: Regenerate.
481 * cris-desc.h: Regenerate.
482 * cris-opc.h: Regenerate.
483 * po/POTFILES.in: Regenerate.
485 2021-05-24 Mike Frysinger <vapier@gentoo.org>
487 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
488 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
489 (CGEN_CPUS): Add cris.
491 (stamp-cris): New rule.
492 * cgen.sh: Handle desc action.
493 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
494 * Makefile.in, configure: Regenerate.
496 2021-05-18 Job Noorman <mtvec@pm.me>
499 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
502 2021-05-17 Alex Coplan <alex.coplan@arm.com>
504 * arm-dis.c (mve_opcodes): Fix disassembly of
505 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
506 (is_mve_encoding_conflict): MVE vector loads should not match
508 (is_mve_unpredictable): It's not unpredictable to use the same
509 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
511 2021-05-11 Nick Clifton <nickc@redhat.com>
514 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
515 the end of the code buffer.
517 2021-05-06 Stafford Horne <shorne@gmail.com>
520 * or1k-asm.c: Regenerate.
522 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
524 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
525 info->insn_info_valid.
527 2021-04-26 Jan Beulich <jbeulich@suse.com>
529 * i386-opc.tbl (lea): Add Optimize.
530 * opcodes/i386-tbl.h: Re-generate.
532 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
534 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
535 of l32r fetch and display referenced literal value.
537 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
539 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
540 to 4 for literal disassembly.
542 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
544 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
545 for TLBI instruction.
547 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
549 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
552 2021-04-19 Jan Beulich <jbeulich@suse.com>
554 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
556 (convert_mov_to_movewide): Add initializer for "value".
558 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
560 * aarch64-opc.c: Add RME system registers.
562 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
564 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
565 "addi d,CV,z" to "c.mv d,CV".
567 2021-04-12 Alan Modra <amodra@gmail.com>
569 * configure.ac (--enable-checking): Add support.
570 * config.in: Regenerate.
571 * configure: Regenerate.
573 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
575 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
576 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
578 2021-04-09 Alan Modra <amodra@gmail.com>
580 * ppc-dis.c (struct dis_private): Add "special".
581 (POWERPC_DIALECT): Delete. Replace uses with..
582 (private_data): ..this. New inline function.
583 (disassemble_init_powerpc): Init "special" names.
584 (skip_optional_operands): Add is_pcrel arg, set when detecting R
585 field of prefix instructions.
586 (bsearch_reloc, print_got_plt): New functions.
587 (print_insn_powerpc): For pcrel instructions, print target address
588 and symbol if known, and decode plt and got loads too.
590 2021-04-08 Alan Modra <amodra@gmail.com>
593 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
595 2021-04-08 Alan Modra <amodra@gmail.com>
598 * ppc-opc.c (DCBT_EO): Move earlier.
599 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
600 (powerpc_operands): Add THCT and THDS entries.
601 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
603 2021-04-06 Alan Modra <amodra@gmail.com>
605 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
606 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
607 symbol_at_address_func.
609 2021-04-05 Alan Modra <amodra@gmail.com>
611 * configure.ac: Don't check for limits.h, string.h, strings.h or
613 (AC_ISC_POSIX): Don't invoke.
614 * sysdep.h: Include stdlib.h and string.h unconditionally.
615 * i386-opc.h: Include limits.h unconditionally.
616 * wasm32-dis.c: Likewise.
617 * cgen-opc.c: Don't include alloca-conf.h.
618 * config.in: Regenerate.
619 * configure: Regenerate.
621 2021-04-01 Martin Liska <mliska@suse.cz>
623 * arm-dis.c (strneq): Remove strneq and use startswith.
624 * cr16-dis.c (print_insn_cr16): Likewise.
625 * score-dis.c (streq): Likewise.
627 * score7-dis.c (strneq): Likewise.
629 2021-04-01 Alan Modra <amodra@gmail.com>
632 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
634 2021-03-31 Alan Modra <amodra@gmail.com>
636 * sysdep.h (POISON_BFD_BOOLEAN): Define.
637 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
638 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
639 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
640 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
641 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
642 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
643 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
644 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
645 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
646 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
647 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
648 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
649 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
650 and TRUE with true throughout.
652 2021-03-31 Alan Modra <amodra@gmail.com>
654 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
655 * aarch64-dis.h: Likewise.
656 * aarch64-opc.c: Likewise.
657 * avr-dis.c: Likewise.
658 * csky-dis.c: Likewise.
659 * nds32-asm.c: Likewise.
660 * nds32-dis.c: Likewise.
661 * nfp-dis.c: Likewise.
662 * riscv-dis.c: Likewise.
663 * s12z-dis.c: Likewise.
664 * wasm32-dis.c: Likewise.
666 2021-03-30 Jan Beulich <jbeulich@suse.com>
668 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
669 (i386_seg_prefixes): New.
670 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
671 (i386_seg_prefixes): Declare.
673 2021-03-30 Jan Beulich <jbeulich@suse.com>
675 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
677 2021-03-30 Jan Beulich <jbeulich@suse.com>
679 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
680 * i386-reg.tbl (st): Move down.
681 (st(0)): Delete. Extend comment.
682 * i386-tbl.h: Re-generate.
684 2021-03-29 Jan Beulich <jbeulich@suse.com>
686 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
687 (cmpsd): Move next to cmps.
688 (movsd): Move next to movs.
689 (cmpxchg16b): Move to separate section.
690 (fisttp, fisttpll): Likewise.
691 (monitor, mwait): Likewise.
692 * i386-tbl.h: Re-generate.
694 2021-03-29 Jan Beulich <jbeulich@suse.com>
696 * i386-opc.tbl (psadbw): Add <sse2:comm>.
698 * i386-tbl.h: Re-generate.
700 2021-03-29 Jan Beulich <jbeulich@suse.com>
702 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
703 pclmul, gfni): New templates. Use them wherever possible. Move
704 SSE4.1 pextrw into respective section.
705 * i386-tbl.h: Re-generate.
707 2021-03-29 Jan Beulich <jbeulich@suse.com>
709 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
710 strtoull(). Bump upper loop bound. Widen masks. Sanity check
712 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
713 Convert all of their uses to representation in opcode.
715 2021-03-29 Jan Beulich <jbeulich@suse.com>
717 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
718 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
719 value of None. Shrink operands to 3 bits.
721 2021-03-29 Jan Beulich <jbeulich@suse.com>
723 * i386-gen.c (process_i386_opcode_modifier): New parameter
725 (output_i386_opcode): New local variable "space". Adjust
726 process_i386_opcode_modifier() invocation.
727 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
729 * i386-tbl.h: Re-generate.
731 2021-03-29 Alan Modra <amodra@gmail.com>
733 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
734 (fp_qualifier_p, get_data_pattern): Likewise.
735 (aarch64_get_operand_modifier_from_value): Likewise.
736 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
737 (operand_variant_qualifier_p): Likewise.
738 (qualifier_value_in_range_constraint_p): Likewise.
739 (aarch64_get_qualifier_esize): Likewise.
740 (aarch64_get_qualifier_nelem): Likewise.
741 (aarch64_get_qualifier_standard_value): Likewise.
742 (get_lower_bound, get_upper_bound): Likewise.
743 (aarch64_find_best_match, match_operands_qualifier): Likewise.
744 (aarch64_print_operand): Likewise.
745 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
746 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
747 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
748 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
749 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
750 (print_insn_tic6x): Likewise.
752 2021-03-29 Alan Modra <amodra@gmail.com>
754 * arc-dis.c (extract_operand_value): Correct NULL cast.
755 * frv-opc.h: Regenerate.
757 2021-03-26 Jan Beulich <jbeulich@suse.com>
759 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
761 * i386-tbl.h: Re-generate.
763 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
765 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
766 immediate in br.n instruction.
768 2021-03-25 Jan Beulich <jbeulich@suse.com>
770 * i386-dis.c (XMGatherD, VexGatherD): New.
771 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
772 (print_insn): Check masking for S/G insns.
773 (OP_E_memory): New local variable check_gather. Extend mandatory
774 SIB check. Check register conflicts for (EVEX-encoded) gathers.
775 Extend check for disallowed 16-bit addressing.
776 (OP_VEX): New local variables modrm_reg and sib_index. Convert
777 if()s to switch(). Check register conflicts for (VEX-encoded)
778 gathers. Drop no longer reachable cases.
779 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
782 2021-03-25 Jan Beulich <jbeulich@suse.com>
784 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
785 zeroing-masking without masking.
787 2021-03-25 Jan Beulich <jbeulich@suse.com>
789 * i386-opc.tbl (invlpgb): Fix multi-operand form.
790 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
791 single-operand forms as deprecated.
792 * i386-tbl.h: Re-generate.
794 2021-03-25 Alan Modra <amodra@gmail.com>
797 * ppc-opc.c (XLOCB_MASK): Delete.
798 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
800 (powerpc_opcodes): Accept a BH field on all extended forms of
801 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
803 2021-03-24 Jan Beulich <jbeulich@suse.com>
805 * i386-gen.c (output_i386_opcode): Drop processing of
806 opcode_length. Calculate length from base_opcode. Adjust prefix
807 encoding determination.
808 (process_i386_opcodes): Drop output of fake opcode_length.
809 * i386-opc.h (struct insn_template): Drop opcode_length field.
810 * i386-opc.tbl: Drop opcode length field from all templates.
811 * i386-tbl.h: Re-generate.
813 2021-03-24 Jan Beulich <jbeulich@suse.com>
815 * i386-gen.c (process_i386_opcode_modifier): Return void. New
816 parameter "prefix". Drop local variable "regular_encoding".
817 Record prefix setting / check for consistency.
818 (output_i386_opcode): Parse opcode_length and base_opcode
819 earlier. Derive prefix encoding. Drop no longer applicable
820 consistency checking. Adjust process_i386_opcode_modifier()
822 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
824 * i386-tbl.h: Re-generate.
826 2021-03-24 Jan Beulich <jbeulich@suse.com>
828 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
830 * i386-opc.h (Prefix_*): Move #define-s.
831 * i386-opc.tbl: Move pseudo prefix enumerator values to
832 extension opcode field. Introduce pseudopfx template.
833 * i386-tbl.h: Re-generate.
835 2021-03-23 Jan Beulich <jbeulich@suse.com>
837 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
839 * i386-tbl.h: Re-generate.
841 2021-03-23 Jan Beulich <jbeulich@suse.com>
843 * i386-opc.h (struct insn_template): Move cpu_flags field past
845 * i386-tbl.h: Re-generate.
847 2021-03-23 Jan Beulich <jbeulich@suse.com>
849 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
850 * i386-opc.h (OpcodeSpace): New enumerator.
851 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
852 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
853 SPACE_XOP09, SPACE_XOP0A): ... respectively.
854 (struct i386_opcode_modifier): New field opcodespace. Shrink
856 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
857 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
859 * i386-tbl.h: Re-generate.
861 2021-03-22 Martin Liska <mliska@suse.cz>
863 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
864 * arc-dis.c (parse_option): Likewise.
865 * arm-dis.c (parse_arm_disassembler_options): Likewise.
866 * cris-dis.c (print_with_operands): Likewise.
867 * h8300-dis.c (bfd_h8_disassemble): Likewise.
868 * i386-dis.c (print_insn): Likewise.
869 * ia64-gen.c (fetch_insn_class): Likewise.
870 (parse_resource_users): Likewise.
871 (in_iclass): Likewise.
872 (lookup_specifier): Likewise.
873 (insert_opcode_dependencies): Likewise.
874 * mips-dis.c (parse_mips_ase_option): Likewise.
875 (parse_mips_dis_option): Likewise.
876 * s390-dis.c (disassemble_init_s390): Likewise.
877 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
879 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
881 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
883 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
885 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
886 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
888 2021-03-12 Alan Modra <amodra@gmail.com>
890 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
892 2021-03-11 Jan Beulich <jbeulich@suse.com>
894 * i386-dis.c (OP_XMM): Re-order checks.
896 2021-03-11 Jan Beulich <jbeulich@suse.com>
898 * i386-dis.c (putop): Drop need_vex check when also checking
900 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
903 2021-03-11 Jan Beulich <jbeulich@suse.com>
905 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
906 checks. Move case label past broadcast check.
908 2021-03-10 Jan Beulich <jbeulich@suse.com>
910 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
911 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
912 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
913 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
914 EVEX_W_0F38C7_M_0_L_2): Delete.
915 (REG_EVEX_0F38C7_M_0_L_2): New.
916 (intel_operand_size): Handle VEX and EVEX the same for
917 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
918 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
919 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
920 vex_vsib_q_w_d_mode uses.
921 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
922 0F38A1, and 0F38A3 entries.
923 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
925 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
926 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
929 2021-03-10 Jan Beulich <jbeulich@suse.com>
931 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
932 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
933 MOD_VEX_0FXOP_09_12): Rename to ...
934 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
935 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
936 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
937 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
938 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
939 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
940 (reg_table): Adjust comments.
941 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
942 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
943 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
944 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
945 (vex_len_table): Adjust opcode 0A_12 entry.
946 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
947 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
948 (rm_table): Move hreset entry.
950 2021-03-10 Jan Beulich <jbeulich@suse.com>
952 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
953 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
954 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
955 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
956 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
957 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
958 (get_valid_dis386): Also handle 512-bit vector length when
959 vectoring into vex_len_table[].
960 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
961 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
963 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
964 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
965 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
966 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
969 2021-03-10 Jan Beulich <jbeulich@suse.com>
971 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
972 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
973 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
974 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
976 * i386-dis-evex-len.h (evex_len_table): Likewise.
977 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
979 2021-03-10 Jan Beulich <jbeulich@suse.com>
981 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
982 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
983 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
984 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
985 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
986 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
987 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
988 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
989 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
990 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
991 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
992 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
993 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
994 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
995 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
996 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
997 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
998 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
999 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
1000 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1001 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
1002 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
1003 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1004 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
1005 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1006 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
1007 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
1008 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
1009 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
1010 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
1011 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
1012 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
1013 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
1014 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
1015 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
1016 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
1017 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
1018 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
1019 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
1020 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
1021 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
1022 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
1023 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
1024 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
1025 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
1026 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
1027 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
1028 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
1029 EVEX_W_0F3A43_L_n): New.
1030 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
1031 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
1032 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
1033 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
1034 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
1035 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
1036 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
1037 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
1038 0F385B, 0F38C6, and 0F38C7 entries.
1039 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
1041 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
1042 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
1043 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
1044 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
1046 2021-03-10 Jan Beulich <jbeulich@suse.com>
1048 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
1049 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
1050 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
1051 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
1052 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
1053 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
1054 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
1055 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
1056 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1057 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1058 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1059 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1060 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1061 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1062 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1063 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1064 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1065 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1066 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1067 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1068 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1069 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1070 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1071 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1072 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1073 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1074 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1075 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1076 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1077 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1078 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1079 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1080 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1081 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1082 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1083 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1084 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1085 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1086 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1087 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1088 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1089 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1090 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1091 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1092 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1093 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1094 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1095 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1096 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1097 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1098 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1099 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1100 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1101 VEX_W_0F99_P_2_LEN_0): Delete.
1102 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1103 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1104 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1105 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1106 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1107 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1108 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1109 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1110 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1111 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1112 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1113 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1114 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1115 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1116 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1117 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1118 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1119 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1120 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1121 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1122 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1123 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1124 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1125 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1126 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1127 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1128 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1129 (prefix_table): No longer link to vex_len_table[] for opcodes
1130 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1131 0F92, 0F93, 0F98, and 0F99.
1132 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1133 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1135 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1136 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1138 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1139 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1141 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1142 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1145 2021-03-10 Jan Beulich <jbeulich@suse.com>
1147 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1148 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1149 REG_VEX_0F73_M_0 respectively.
1150 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1151 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1152 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1153 MOD_VEX_0F73_REG_7): Delete.
1154 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1155 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1156 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1157 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1158 PREFIX_VEX_0F3AF0_L_0 respectively.
1159 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1160 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1161 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1162 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1163 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1164 VEX_LEN_0F38F7): New.
1165 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1166 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1167 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1169 (prefix_table): No longer link to vex_len_table[] for opcodes
1170 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1171 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1172 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1173 0F38F6, 0F38F7, and 0F3AF0.
1174 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1175 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1176 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1179 2021-03-10 Jan Beulich <jbeulich@suse.com>
1181 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1182 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1183 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1184 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1185 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1186 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1187 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1189 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1191 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1194 2021-03-10 Jan Beulich <jbeulich@suse.com>
1196 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1197 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1198 (reg_table): Don't link to mod_table[] where not needed. Add
1199 PREFIX_IGNORED to nop entries.
1200 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1201 (mod_table): Add nop entries next to prefetch ones. Drop
1202 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1203 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1204 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1205 PREFIX_OPCODE from endbr* entries.
1206 (get_valid_dis386): Also consider entry's name when zapping
1208 (print_insn): Handle PREFIX_IGNORED.
1210 2021-03-09 Jan Beulich <jbeulich@suse.com>
1212 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1213 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1215 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1216 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1217 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1218 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1219 (struct i386_opcode_modifier): Delete notrackprefixok,
1220 islockable, hleprefixok, and repprefixok fields. Add prefixok
1222 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1223 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1224 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1225 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1226 Replace HLEPrefixOk.
1227 * opcodes/i386-tbl.h: Re-generate.
1229 2021-03-09 Jan Beulich <jbeulich@suse.com>
1231 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1232 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1234 * opcodes/i386-tbl.h: Re-generate.
1236 2021-03-03 Jan Beulich <jbeulich@suse.com>
1238 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1239 for {} instead of {0}. Don't look for '0'.
1240 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1243 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1246 * riscv-dis.c (print_insn_args): Updated encoding macros.
1247 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1248 (match_c_addi16sp): Updated encoding macros.
1249 (match_c_lui): Likewise.
1250 (match_c_lui_with_hint): Likewise.
1251 (match_c_addi4spn): Likewise.
1252 (match_c_slli): Likewise.
1253 (match_slli_as_c_slli): Likewise.
1254 (match_c_slli64): Likewise.
1255 (match_srxi_as_c_srxi): Likewise.
1256 (riscv_insn_types): Added .insn css/cl/cs.
1258 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1260 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1261 (default_priv_spec): Updated type to riscv_spec_class.
1262 (parse_riscv_dis_option): Updated.
1263 * riscv-opc.c: Moved stuff and make the file tidy.
1265 2021-02-17 Alan Modra <amodra@gmail.com>
1267 * wasm32-dis.c: Include limits.h.
1268 (CHAR_BIT): Provide backup define.
1269 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1270 Correct signed overflow checking.
1272 2021-02-16 Jan Beulich <jbeulich@suse.com>
1274 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1275 * i386-tbl.h: Re-generate.
1277 2021-02-16 Jan Beulich <jbeulich@suse.com>
1279 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1281 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1283 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1285 * s390-mkopc.c (main): Accept arch14 as cpu string.
1286 * s390-opc.txt: Add new arch14 instructions.
1288 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1290 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1292 * configure: Regenerated.
1294 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1296 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1297 * tic54x-opc.c (regs): Rename to ...
1298 (tic54x_regs): ... this.
1299 (mmregs): Rename to ...
1300 (tic54x_mmregs): ... this.
1301 (condition_codes): Rename to ...
1302 (tic54x_condition_codes): ... this.
1303 (cc2_codes): Rename to ...
1304 (tic54x_cc2_codes): ... this.
1305 (cc3_codes): Rename to ...
1306 (tic54x_cc3_codes): ... this.
1307 (status_bits): Rename to ...
1308 (tic54x_status_bits): ... this.
1309 (misc_symbols): Rename to ...
1310 (tic54x_misc_symbols): ... this.
1312 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1314 * riscv-opc.c (MASK_RVB_IMM): Removed.
1315 (riscv_opcodes): Removed zb* instructions.
1316 (riscv_ext_version_table): Removed versions for zb*.
1318 2021-01-26 Alan Modra <amodra@gmail.com>
1320 * i386-gen.c (parse_template): Ensure entire template_instance
1323 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1325 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1326 (riscv_fpr_names_abi): Likewise.
1327 (riscv_opcodes): Likewise.
1328 (riscv_insn_types): Likewise.
1330 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1332 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1334 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1336 * riscv-dis.c: Comments tidy and improvement.
1337 * riscv-opc.c: Likewise.
1339 2021-01-13 Alan Modra <amodra@gmail.com>
1341 * Makefile.in: Regenerate.
1343 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1346 * configure.ac: Use GNU_MAKE_JOBSERVER.
1347 * aclocal.m4: Regenerated.
1348 * configure: Likewise.
1350 2021-01-12 Nick Clifton <nickc@redhat.com>
1352 * po/sr.po: Updated Serbian translation.
1354 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1357 * configure: Regenerated.
1359 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1361 * aarch64-asm-2.c: Regenerate.
1362 * aarch64-dis-2.c: Likewise.
1363 * aarch64-opc-2.c: Likewise.
1364 * aarch64-opc.c (aarch64_print_operand):
1365 Delete handling of AARCH64_OPND_CSRE_CSR.
1366 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1368 (_CSRE_INSN): Likewise.
1369 (aarch64_opcode_table): Delete csr.
1371 2021-01-11 Nick Clifton <nickc@redhat.com>
1373 * po/de.po: Updated German translation.
1374 * po/fr.po: Updated French translation.
1375 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1376 * po/sv.po: Updated Swedish translation.
1377 * po/uk.po: Updated Ukranian translation.
1379 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1381 * configure: Regenerated.
1383 2021-01-09 Nick Clifton <nickc@redhat.com>
1385 * configure: Regenerate.
1386 * po/opcodes.pot: Regenerate.
1388 2021-01-09 Nick Clifton <nickc@redhat.com>
1390 * 2.36 release branch crated.
1392 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1394 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1395 (DW, (XRC_MASK): Define.
1396 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1398 2021-01-09 Alan Modra <amodra@gmail.com>
1400 * configure: Regenerate.
1402 2021-01-08 Nick Clifton <nickc@redhat.com>
1404 * po/sv.po: Updated Swedish translation.
1406 2021-01-08 Nick Clifton <nickc@redhat.com>
1409 * aarch64-dis.c (determine_disassembling_preference): Move call to
1410 aarch64_match_operands_constraint outside of the assertion.
1411 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1412 Replace with a return of FALSE.
1415 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1416 core system register.
1418 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1420 * configure: Regenerate.
1422 2021-01-07 Nick Clifton <nickc@redhat.com>
1424 * po/fr.po: Updated French translation.
1426 2021-01-07 Fredrik Noring <noring@nocrew.org>
1428 * m68k-opc.c (chkl): Change minimum architecture requirement to
1431 2021-01-07 Philipp Tomsich <prt@gnu.org>
1433 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1435 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1436 Jim Wilson <jimw@sifive.com>
1437 Andrew Waterman <andrew@sifive.com>
1438 Maxim Blinov <maxim.blinov@embecosm.com>
1439 Kito Cheng <kito.cheng@sifive.com>
1440 Nelson Chu <nelson.chu@sifive.com>
1442 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1443 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1445 2021-01-01 Alan Modra <amodra@gmail.com>
1447 Update year range in copyright notice of all files.
1449 For older changes see ChangeLog-2020
1451 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1453 Copying and distribution of this file, with or without modification,
1454 are permitted in any medium without royalty provided the copyright
1455 notice and this notice are preserved.
1461 version-control: never