opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2022 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43 typedef struct instr_info instr_info;
  44
  45 static void dofloat (instr_info *, int);
  46 static void OP_ST (instr_info *, int, int);
  47 static void OP_STi (instr_info *, int, int);
  48 static int putop (instr_info *, const char *, int);
  49 static void oappend_with_style (instr_info *, const char *,
  50                                 enum disassembler_style);
  51 static void oappend (instr_info *, const char *);
  52 static void append_seg (instr_info *);
  53 static void OP_indirE (instr_info *, int, int);
  54 static void OP_E_memory (instr_info *, int, int);
  55 static void OP_E (instr_info *, int, int);
  56 static void OP_G (instr_info *, int, int);
  57 static bfd_vma get64 (instr_info *);
  58 static bfd_signed_vma get32 (instr_info *);
  59 static bfd_signed_vma get32s (instr_info *);
  60 static int get16 (instr_info *);
  61 static void set_op (instr_info *, bfd_vma, bool);
  62 static void OP_Skip_MODRM (instr_info *, int, int);
  63 static void OP_REG (instr_info *, int, int);
  64 static void OP_IMREG (instr_info *, int, int);
  65 static void OP_I (instr_info *, int, int);
  66 static void OP_I64 (instr_info *, int, int);
  67 static void OP_sI (instr_info *, int, int);
  68 static void OP_J (instr_info *, int, int);
  69 static void OP_SEG (instr_info *, int, int);
  70 static void OP_DIR (instr_info *, int, int);
  71 static void OP_OFF (instr_info *, int, int);
  72 static void OP_OFF64 (instr_info *, int, int);
  73 static void ptr_reg (instr_info *, int, int);
  74 static void OP_ESreg (instr_info *, int, int);
  75 static void OP_DSreg (instr_info *, int, int);
  76 static void OP_C (instr_info *, int, int);
  77 static void OP_D (instr_info *, int, int);
  78 static void OP_T (instr_info *, int, int);
  79 static void OP_MMX (instr_info *, int, int);
  80 static void OP_XMM (instr_info *, int, int);
  81 static void OP_EM (instr_info *, int, int);
  82 static void OP_EX (instr_info *, int, int);
  83 static void OP_EMC (instr_info *, int,int);
  84 static void OP_MXC (instr_info *, int,int);
  85 static void OP_MS (instr_info *, int, int);
  86 static void OP_XS (instr_info *, int, int);
  87 static void OP_M (instr_info *, int, int);
  88 static void OP_VEX (instr_info *, int, int);
  89 static void OP_VexR (instr_info *, int, int);
  90 static void OP_VexW (instr_info *, int, int);
  91 static void OP_Rounding (instr_info *, int, int);
  92 static void OP_REG_VexI4 (instr_info *, int, int);
  93 static void OP_VexI4 (instr_info *, int, int);
  94 static void PCLMUL_Fixup (instr_info *, int, int);
  95 static void VPCMP_Fixup (instr_info *, int, int);
  96 static void VPCOM_Fixup (instr_info *, int, int);
  97 static void OP_0f07 (instr_info *, int, int);
  98 static void OP_Monitor (instr_info *, int, int);
  99 static void OP_Mwait (instr_info *, int, int);
 100 static void NOP_Fixup (instr_info *, int, int);
 101 static void OP_3DNowSuffix (instr_info *, int, int);
 102 static void CMP_Fixup (instr_info *, int, int);
 103 static void BadOp (instr_info *);
 104 static void REP_Fixup (instr_info *, int, int);
 105 static void SEP_Fixup (instr_info *, int, int);
 106 static void BND_Fixup (instr_info *, int, int);
 107 static void NOTRACK_Fixup (instr_info *, int, int);
 108 static void HLE_Fixup1 (instr_info *, int, int);
 109 static void HLE_Fixup2 (instr_info *, int, int);
 110 static void HLE_Fixup3 (instr_info *, int, int);
 111 static void CMPXCHG8B_Fixup (instr_info *, int, int);
 112 static void XMM_Fixup (instr_info *, int, int);
 113 static void FXSAVE_Fixup (instr_info *, int, int);
 114
 115 static void MOVSXD_Fixup (instr_info *, int, int);
 116 static void DistinctDest_Fixup (instr_info *, int, int);
 117
 118 /* This character is used to encode style information within the output
 119    buffers.  See oappend_insert_style for more details.  */
 120 #define STYLE_MARKER_CHAR '\002'
 121
 122 /* The maximum operand buffer size.  */
 123 #define MAX_OPERAND_BUFFER_SIZE 128
 124
 125 struct dis_private {
 126   /* Points to first byte not fetched.  */
 127   bfd_byte *max_fetched;
 128   bfd_byte the_buffer[MAX_MNEM_SIZE];
 129   bfd_vma insn_start;
 130   int orig_sizeflag;
 131   OPCODES_SIGJMP_BUF bailout;
 132 };
 133
 134 enum address_mode
 135 {
 136   mode_16bit,
 137   mode_32bit,
 138   mode_64bit
 139 };
 140
 141 enum x86_64_isa
 142 {
 143   amd64 = 1,
 144   intel64
 145 };
 146
 147 struct instr_info
 148 {
 149   enum address_mode address_mode;
 150
 151   /* Flags for the prefixes for the current instruction.  See below.  */
 152   int prefixes;
 153
 154   /* REX prefix the current instruction.  See below.  */
 155   unsigned char rex;
 156   /* Bits of REX we've already used.  */
 157   unsigned char rex_used;
 158
 159   bool need_modrm;
 160   bool need_vex;
 161   bool has_sib;
 162
 163   /* Flags for ins->prefixes which we somehow handled when printing the
 164      current instruction.  */
 165   int used_prefixes;
 166
 167   /* Flags for EVEX bits which we somehow handled when printing the
 168      current instruction.  */
 169   int evex_used;
 170
 171   char obuf[MAX_OPERAND_BUFFER_SIZE];
 172   char *obufp;
 173   char *mnemonicendp;
 174   unsigned char *start_codep;
 175   unsigned char *insn_codep;
 176   unsigned char *codep;
 177   unsigned char *end_codep;
 178   signed char last_lock_prefix;
 179   signed char last_repz_prefix;
 180   signed char last_repnz_prefix;
 181   signed char last_data_prefix;
 182   signed char last_addr_prefix;
 183   signed char last_rex_prefix;
 184   signed char last_seg_prefix;
 185   signed char fwait_prefix;
 186   /* The active segment register prefix.  */
 187   unsigned char active_seg_prefix;
 188
 189 #define MAX_CODE_LENGTH 15
 190   /* We can up to 14 ins->prefixes since the maximum instruction length is
 191      15bytes.  */
 192   unsigned char all_prefixes[MAX_CODE_LENGTH - 1];
 193   disassemble_info *info;
 194
 195   struct
 196   {
 197     int mod;
 198     int reg;
 199     int rm;
 200   }
 201   modrm;
 202
 203   struct
 204   {
 205     int scale;
 206     int index;
 207     int base;
 208   }
 209   sib;
 210
 211   struct
 212   {
 213     int register_specifier;
 214     int length;
 215     int prefix;
 216     int mask_register_specifier;
 217     int ll;
 218     bool w;
 219     bool evex;
 220     bool r;
 221     bool v;
 222     bool zeroing;
 223     bool b;
 224     bool no_broadcast;
 225   }
 226   vex;
 227
 228   /* Remember if the current op is a jump instruction.  */
 229   bool op_is_jump;
 230
 231   bool two_source_ops;
 232
 233   unsigned char op_ad;
 234   signed char op_index[MAX_OPERANDS];
 235   bool op_riprel[MAX_OPERANDS];
 236   char *op_out[MAX_OPERANDS];
 237   bfd_vma op_address[MAX_OPERANDS];
 238   bfd_vma start_pc;
 239
 240   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 241    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 242    *   section of the "Virtual 8086 Mode" chapter.)
 243    * 'pc' should be the address of this instruction, it will
 244    *   be used to print the target address if this is a relative jump or call
 245    * The function returns the length of this instruction in bytes.
 246    */
 247   char intel_syntax;
 248   bool intel_mnemonic;
 249   char open_char;
 250   char close_char;
 251   char separator_char;
 252   char scale_char;
 253
 254   enum x86_64_isa isa64;
 255 };
 256
 257 /* Mark parts used in the REX prefix.  When we are testing for
 258    empty prefix (for 8bit register REX extension), just mask it
 259    out.  Otherwise test for REX bit is excuse for existence of REX
 260    only in case value is nonzero.  */
 261 #define USED_REX(value)                                 \
 262   {                                                     \
 263     if (value)                                          \
 264       {                                                 \
 265         if ((ins->rex & value))                         \
 266           ins->rex_used |= (value) | REX_OPCODE;        \
 267       }                                                 \
 268     else                                                \
 269       ins->rex_used |= REX_OPCODE;                      \
 270   }
 271
 272
 273 #define EVEX_b_used 1
 274 #define EVEX_len_used 2
 275
 276 /* Flags stored in PREFIXES.  */
 277 #define PREFIX_REPZ 1
 278 #define PREFIX_REPNZ 2
 279 #define PREFIX_CS 4
 280 #define PREFIX_SS 8
 281 #define PREFIX_DS 0x10
 282 #define PREFIX_ES 0x20
 283 #define PREFIX_FS 0x40
 284 #define PREFIX_GS 0x80
 285 #define PREFIX_LOCK 0x100
 286 #define PREFIX_DATA 0x200
 287 #define PREFIX_ADDR 0x400
 288 #define PREFIX_FWAIT 0x800
 289
 290 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 291    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 292    on error.  */
 293 #define FETCH_DATA(info, addr) \
 294   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 295    ? 1 : fetch_data ((info), (addr)))
 296
 297 static int
 298 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 299 {
 300   int status;
 301   struct dis_private *priv = (struct dis_private *) info->private_data;
 302   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 303
 304   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 305     status = (*info->read_memory_func) (start,
 306                                         priv->max_fetched,
 307                                         addr - priv->max_fetched,
 308                                         info);
 309   else
 310     status = -1;
 311   if (status != 0)
 312     {
 313       /* If we did manage to read at least one byte, then
 314          print_insn_i386 will do something sensible.  Otherwise, print
 315          an error.  We do that here because this is where we know
 316          STATUS.  */
 317       if (priv->max_fetched == priv->the_buffer)
 318         (*info->memory_error_func) (status, start, info);
 319       OPCODES_SIGLONGJMP (priv->bailout, 1);
 320     }
 321   else
 322     priv->max_fetched = addr;
 323   return 1;
 324 }
 325
 326 /* Possible values for prefix requirement.  */
 327 #define PREFIX_IGNORED_SHIFT    16
 328 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 329 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 330 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 331 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 332 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 333
 334 /* Opcode prefixes.  */
 335 #define PREFIX_OPCODE           (PREFIX_REPZ \
 336                                  | PREFIX_REPNZ \
 337                                  | PREFIX_DATA)
 338
 339 /* Prefixes ignored.  */
 340 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 341                                  | PREFIX_IGNORED_REPNZ \
 342                                  | PREFIX_IGNORED_DATA)
 343
 344 #define XX { NULL, 0 }
 345 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 346
 347 #define Eb { OP_E, b_mode }
 348 #define Ebnd { OP_E, bnd_mode }
 349 #define EbS { OP_E, b_swap_mode }
 350 #define EbndS { OP_E, bnd_swap_mode }
 351 #define Ev { OP_E, v_mode }
 352 #define Eva { OP_E, va_mode }
 353 #define Ev_bnd { OP_E, v_bnd_mode }
 354 #define EvS { OP_E, v_swap_mode }
 355 #define Ed { OP_E, d_mode }
 356 #define Edq { OP_E, dq_mode }
 357 #define Edb { OP_E, db_mode }
 358 #define Edw { OP_E, dw_mode }
 359 #define Eq { OP_E, q_mode }
 360 #define indirEv { OP_indirE, indir_v_mode }
 361 #define indirEp { OP_indirE, f_mode }
 362 #define stackEv { OP_E, stack_v_mode }
 363 #define Em { OP_E, m_mode }
 364 #define Ew { OP_E, w_mode }
 365 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 366 #define Ma { OP_M, a_mode }
 367 #define Mb { OP_M, b_mode }
 368 #define Md { OP_M, d_mode }
 369 #define Mo { OP_M, o_mode }
 370 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 371 #define Mq { OP_M, q_mode }
 372 #define Mv { OP_M, v_mode }
 373 #define Mv_bnd { OP_M, v_bndmk_mode }
 374 #define Mx { OP_M, x_mode }
 375 #define Mxmm { OP_M, xmm_mode }
 376 #define Gb { OP_G, b_mode }
 377 #define Gbnd { OP_G, bnd_mode }
 378 #define Gv { OP_G, v_mode }
 379 #define Gd { OP_G, d_mode }
 380 #define Gdq { OP_G, dq_mode }
 381 #define Gm { OP_G, m_mode }
 382 #define Gva { OP_G, va_mode }
 383 #define Gw { OP_G, w_mode }
 384 #define Ib { OP_I, b_mode }
 385 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 386 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 387 #define Iv { OP_I, v_mode }
 388 #define sIv { OP_sI, v_mode }
 389 #define Iv64 { OP_I64, v_mode }
 390 #define Id { OP_I, d_mode }
 391 #define Iw { OP_I, w_mode }
 392 #define I1 { OP_I, const_1_mode }
 393 #define Jb { OP_J, b_mode }
 394 #define Jv { OP_J, v_mode }
 395 #define Jdqw { OP_J, dqw_mode }
 396 #define Cm { OP_C, m_mode }
 397 #define Dm { OP_D, m_mode }
 398 #define Td { OP_T, d_mode }
 399 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 400
 401 #define RMeAX { OP_REG, eAX_reg }
 402 #define RMeBX { OP_REG, eBX_reg }
 403 #define RMeCX { OP_REG, eCX_reg }
 404 #define RMeDX { OP_REG, eDX_reg }
 405 #define RMeSP { OP_REG, eSP_reg }
 406 #define RMeBP { OP_REG, eBP_reg }
 407 #define RMeSI { OP_REG, eSI_reg }
 408 #define RMeDI { OP_REG, eDI_reg }
 409 #define RMrAX { OP_REG, rAX_reg }
 410 #define RMrBX { OP_REG, rBX_reg }
 411 #define RMrCX { OP_REG, rCX_reg }
 412 #define RMrDX { OP_REG, rDX_reg }
 413 #define RMrSP { OP_REG, rSP_reg }
 414 #define RMrBP { OP_REG, rBP_reg }
 415 #define RMrSI { OP_REG, rSI_reg }
 416 #define RMrDI { OP_REG, rDI_reg }
 417 #define RMAL { OP_REG, al_reg }
 418 #define RMCL { OP_REG, cl_reg }
 419 #define RMDL { OP_REG, dl_reg }
 420 #define RMBL { OP_REG, bl_reg }
 421 #define RMAH { OP_REG, ah_reg }
 422 #define RMCH { OP_REG, ch_reg }
 423 #define RMDH { OP_REG, dh_reg }
 424 #define RMBH { OP_REG, bh_reg }
 425 #define RMAX { OP_REG, ax_reg }
 426 #define RMDX { OP_REG, dx_reg }
 427
 428 #define eAX { OP_IMREG, eAX_reg }
 429 #define AL { OP_IMREG, al_reg }
 430 #define CL { OP_IMREG, cl_reg }
 431 #define zAX { OP_IMREG, z_mode_ax_reg }
 432 #define indirDX { OP_IMREG, indir_dx_reg }
 433
 434 #define Sw { OP_SEG, w_mode }
 435 #define Sv { OP_SEG, v_mode }
 436 #define Ap { OP_DIR, 0 }
 437 #define Ob { OP_OFF64, b_mode }
 438 #define Ov { OP_OFF64, v_mode }
 439 #define Xb { OP_DSreg, eSI_reg }
 440 #define Xv { OP_DSreg, eSI_reg }
 441 #define Xz { OP_DSreg, eSI_reg }
 442 #define Yb { OP_ESreg, eDI_reg }
 443 #define Yv { OP_ESreg, eDI_reg }
 444 #define DSBX { OP_DSreg, eBX_reg }
 445
 446 #define es { OP_REG, es_reg }
 447 #define ss { OP_REG, ss_reg }
 448 #define cs { OP_REG, cs_reg }
 449 #define ds { OP_REG, ds_reg }
 450 #define fs { OP_REG, fs_reg }
 451 #define gs { OP_REG, gs_reg }
 452
 453 #define MX { OP_MMX, 0 }
 454 #define XM { OP_XMM, 0 }
 455 #define XMScalar { OP_XMM, scalar_mode }
 456 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 457 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 458 #define XMM { OP_XMM, xmm_mode }
 459 #define TMM { OP_XMM, tmm_mode }
 460 #define XMxmmq { OP_XMM, xmmq_mode }
 461 #define EM { OP_EM, v_mode }
 462 #define EMS { OP_EM, v_swap_mode }
 463 #define EMd { OP_EM, d_mode }
 464 #define EMx { OP_EM, x_mode }
 465 #define EXbwUnit { OP_EX, bw_unit_mode }
 466 #define EXb { OP_EX, b_mode }
 467 #define EXw { OP_EX, w_mode }
 468 #define EXd { OP_EX, d_mode }
 469 #define EXdS { OP_EX, d_swap_mode }
 470 #define EXwS { OP_EX, w_swap_mode }
 471 #define EXq { OP_EX, q_mode }
 472 #define EXqS { OP_EX, q_swap_mode }
 473 #define EXdq { OP_EX, dq_mode }
 474 #define EXx { OP_EX, x_mode }
 475 #define EXxh { OP_EX, xh_mode }
 476 #define EXxS { OP_EX, x_swap_mode }
 477 #define EXxmm { OP_EX, xmm_mode }
 478 #define EXymm { OP_EX, ymm_mode }
 479 #define EXtmm { OP_EX, tmm_mode }
 480 #define EXxmmq { OP_EX, xmmq_mode }
 481 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 482 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 483 #define EXxmmdw { OP_EX, xmmdw_mode }
 484 #define EXxmmqd { OP_EX, xmmqd_mode }
 485 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 486 #define EXymmq { OP_EX, ymmq_mode }
 487 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 488 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 489 #define MS { OP_MS, v_mode }
 490 #define XS { OP_XS, v_mode }
 491 #define EMCq { OP_EMC, q_mode }
 492 #define MXC { OP_MXC, 0 }
 493 #define OPSUF { OP_3DNowSuffix, 0 }
 494 #define SEP { SEP_Fixup, 0 }
 495 #define CMP { CMP_Fixup, 0 }
 496 #define XMM0 { XMM_Fixup, 0 }
 497 #define FXSAVE { FXSAVE_Fixup, 0 }
 498
 499 #define Vex { OP_VEX, x_mode }
 500 #define VexW { OP_VexW, x_mode }
 501 #define VexScalar { OP_VEX, scalar_mode }
 502 #define VexScalarR { OP_VexR, scalar_mode }
 503 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 504 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 505 #define VexGdq { OP_VEX, dq_mode }
 506 #define VexTmm { OP_VEX, tmm_mode }
 507 #define XMVexI4 { OP_REG_VexI4, x_mode }
 508 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 509 #define VexI4 { OP_VexI4, 0 }
 510 #define PCLMUL { PCLMUL_Fixup, 0 }
 511 #define VPCMP { VPCMP_Fixup, 0 }
 512 #define VPCOM { VPCOM_Fixup, 0 }
 513
 514 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 515 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 516 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 517
 518 #define MaskG { OP_G, mask_mode }
 519 #define MaskE { OP_E, mask_mode }
 520 #define MaskBDE { OP_E, mask_bd_mode }
 521 #define MaskVex { OP_VEX, mask_mode }
 522
 523 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 524 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 525
 526 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 527
 528 /* Used handle "rep" prefix for string instructions.  */
 529 #define Xbr { REP_Fixup, eSI_reg }
 530 #define Xvr { REP_Fixup, eSI_reg }
 531 #define Ybr { REP_Fixup, eDI_reg }
 532 #define Yvr { REP_Fixup, eDI_reg }
 533 #define Yzr { REP_Fixup, eDI_reg }
 534 #define indirDXr { REP_Fixup, indir_dx_reg }
 535 #define ALr { REP_Fixup, al_reg }
 536 #define eAXr { REP_Fixup, eAX_reg }
 537
 538 /* Used handle HLE prefix for lockable instructions.  */
 539 #define Ebh1 { HLE_Fixup1, b_mode }
 540 #define Evh1 { HLE_Fixup1, v_mode }
 541 #define Ebh2 { HLE_Fixup2, b_mode }
 542 #define Evh2 { HLE_Fixup2, v_mode }
 543 #define Ebh3 { HLE_Fixup3, b_mode }
 544 #define Evh3 { HLE_Fixup3, v_mode }
 545
 546 #define BND { BND_Fixup, 0 }
 547 #define NOTRACK { NOTRACK_Fixup, 0 }
 548
 549 #define cond_jump_flag { NULL, cond_jump_mode }
 550 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 551
 552 /* bits in sizeflag */
 553 #define SUFFIX_ALWAYS 4
 554 #define AFLAG 2
 555 #define DFLAG 1
 556
 557 enum
 558 {
 559   /* byte operand */
 560   b_mode = 1,
 561   /* byte operand with operand swapped */
 562   b_swap_mode,
 563   /* byte operand, sign extend like 'T' suffix */
 564   b_T_mode,
 565   /* operand size depends on prefixes */
 566   v_mode,
 567   /* operand size depends on prefixes with operand swapped */
 568   v_swap_mode,
 569   /* operand size depends on address prefix */
 570   va_mode,
 571   /* word operand */
 572   w_mode,
 573   /* double word operand  */
 574   d_mode,
 575   /* word operand with operand swapped  */
 576   w_swap_mode,
 577   /* double word operand with operand swapped */
 578   d_swap_mode,
 579   /* quad word operand */
 580   q_mode,
 581   /* quad word operand with operand swapped */
 582   q_swap_mode,
 583   /* ten-byte operand */
 584   t_mode,
 585   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 586      broadcast enabled.  */
 587   x_mode,
 588   /* Similar to x_mode, but with different EVEX mem shifts.  */
 589   evex_x_gscat_mode,
 590   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 591   bw_unit_mode,
 592   /* Similar to x_mode, but with disabled broadcast.  */
 593   evex_x_nobcst_mode,
 594   /* Similar to x_mode, but with operands swapped and disabled broadcast
 595      in EVEX.  */
 596   x_swap_mode,
 597   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 598      broadcast of 16bit enabled.  */
 599   xh_mode,
 600   /* 16-byte XMM operand */
 601   xmm_mode,
 602   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 603      memory operand (depending on vector length).  Broadcast isn't
 604      allowed.  */
 605   xmmq_mode,
 606   /* Same as xmmq_mode, but broadcast is allowed.  */
 607   evex_half_bcst_xmmq_mode,
 608   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 609      memory operand (depending on vector length).  16bit broadcast.  */
 610   evex_half_bcst_xmmqh_mode,
 611   /* 16-byte XMM, word, double word or quad word operand.  */
 612   xmmdw_mode,
 613   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 614   xmmqd_mode,
 615   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 616      16bit broadcast.  */
 617   evex_half_bcst_xmmqdh_mode,
 618   /* 32-byte YMM operand */
 619   ymm_mode,
 620   /* quad word, ymmword or zmmword memory operand.  */
 621   ymmq_mode,
 622   /* TMM operand */
 623   tmm_mode,
 624   /* d_mode in 32bit, q_mode in 64bit mode.  */
 625   m_mode,
 626   /* pair of v_mode operands */
 627   a_mode,
 628   cond_jump_mode,
 629   loop_jcxz_mode,
 630   movsxd_mode,
 631   v_bnd_mode,
 632   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 633   v_bndmk_mode,
 634   /* operand size depends on REX.W / VEX.W.  */
 635   dq_mode,
 636   /* Displacements like v_mode without considering Intel64 ISA.  */
 637   dqw_mode,
 638   /* bounds operand */
 639   bnd_mode,
 640   /* bounds operand with operand swapped */
 641   bnd_swap_mode,
 642   /* 4- or 6-byte pointer operand */
 643   f_mode,
 644   const_1_mode,
 645   /* v_mode for indirect branch opcodes.  */
 646   indir_v_mode,
 647   /* v_mode for stack-related opcodes.  */
 648   stack_v_mode,
 649   /* non-quad operand size depends on prefixes */
 650   z_mode,
 651   /* 16-byte operand */
 652   o_mode,
 653   /* registers like d_mode, memory like b_mode.  */
 654   db_mode,
 655   /* registers like d_mode, memory like w_mode.  */
 656   dw_mode,
 657
 658   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 659   vex_vsib_d_w_dq_mode,
 660   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 661   vex_vsib_q_w_dq_mode,
 662   /* mandatory non-vector SIB.  */
 663   vex_sibmem_mode,
 664
 665   /* scalar, ignore vector length.  */
 666   scalar_mode,
 667
 668   /* Static rounding.  */
 669   evex_rounding_mode,
 670   /* Static rounding, 64-bit mode only.  */
 671   evex_rounding_64_mode,
 672   /* Supress all exceptions.  */
 673   evex_sae_mode,
 674
 675   /* Mask register operand.  */
 676   mask_mode,
 677   /* Mask register operand.  */
 678   mask_bd_mode,
 679
 680   es_reg,
 681   cs_reg,
 682   ss_reg,
 683   ds_reg,
 684   fs_reg,
 685   gs_reg,
 686
 687   eAX_reg,
 688   eCX_reg,
 689   eDX_reg,
 690   eBX_reg,
 691   eSP_reg,
 692   eBP_reg,
 693   eSI_reg,
 694   eDI_reg,
 695
 696   al_reg,
 697   cl_reg,
 698   dl_reg,
 699   bl_reg,
 700   ah_reg,
 701   ch_reg,
 702   dh_reg,
 703   bh_reg,
 704
 705   ax_reg,
 706   cx_reg,
 707   dx_reg,
 708   bx_reg,
 709   sp_reg,
 710   bp_reg,
 711   si_reg,
 712   di_reg,
 713
 714   rAX_reg,
 715   rCX_reg,
 716   rDX_reg,
 717   rBX_reg,
 718   rSP_reg,
 719   rBP_reg,
 720   rSI_reg,
 721   rDI_reg,
 722
 723   z_mode_ax_reg,
 724   indir_dx_reg
 725 };
 726
 727 enum
 728 {
 729   FLOATCODE = 1,
 730   USE_REG_TABLE,
 731   USE_MOD_TABLE,
 732   USE_RM_TABLE,
 733   USE_PREFIX_TABLE,
 734   USE_X86_64_TABLE,
 735   USE_3BYTE_TABLE,
 736   USE_XOP_8F_TABLE,
 737   USE_VEX_C4_TABLE,
 738   USE_VEX_C5_TABLE,
 739   USE_VEX_LEN_TABLE,
 740   USE_VEX_W_TABLE,
 741   USE_EVEX_TABLE,
 742   USE_EVEX_LEN_TABLE
 743 };
 744
 745 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 746
 747 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 748 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 749 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 750 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 751 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 752 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 753 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 754 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 755 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 756 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 757 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 758 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 759 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 760 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 761 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 762 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 763
 764 enum
 765 {
 766   REG_80 = 0,
 767   REG_81,
 768   REG_83,
 769   REG_8F,
 770   REG_C0,
 771   REG_C1,
 772   REG_C6,
 773   REG_C7,
 774   REG_D0,
 775   REG_D1,
 776   REG_D2,
 777   REG_D3,
 778   REG_F6,
 779   REG_F7,
 780   REG_FE,
 781   REG_FF,
 782   REG_0F00,
 783   REG_0F01,
 784   REG_0F0D,
 785   REG_0F18,
 786   REG_0F1C_P_0_MOD_0,
 787   REG_0F1E_P_1_MOD_3,
 788   REG_0F38D8_PREFIX_1,
 789   REG_0F3A0F_PREFIX_1_MOD_3,
 790   REG_0F71_MOD_0,
 791   REG_0F72_MOD_0,
 792   REG_0F73_MOD_0,
 793   REG_0FA6,
 794   REG_0FA7,
 795   REG_0FAE,
 796   REG_0FBA,
 797   REG_0FC7,
 798   REG_VEX_0F71_M_0,
 799   REG_VEX_0F72_M_0,
 800   REG_VEX_0F73_M_0,
 801   REG_VEX_0FAE,
 802   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 803   REG_VEX_0F38F3_L_0,
 804
 805   REG_XOP_09_01_L_0,
 806   REG_XOP_09_02_L_0,
 807   REG_XOP_09_12_M_1_L_0,
 808   REG_XOP_0A_12_L_0,
 809
 810   REG_EVEX_0F71,
 811   REG_EVEX_0F72,
 812   REG_EVEX_0F73,
 813   REG_EVEX_0F38C6_M_0_L_2,
 814   REG_EVEX_0F38C7_M_0_L_2
 815 };
 816
 817 enum
 818 {
 819   MOD_62_32BIT = 0,
 820   MOD_8D,
 821   MOD_C4_32BIT,
 822   MOD_C5_32BIT,
 823   MOD_C6_REG_7,
 824   MOD_C7_REG_7,
 825   MOD_FF_REG_3,
 826   MOD_FF_REG_5,
 827   MOD_0F01_REG_0,
 828   MOD_0F01_REG_1,
 829   MOD_0F01_REG_2,
 830   MOD_0F01_REG_3,
 831   MOD_0F01_REG_5,
 832   MOD_0F01_REG_7,
 833   MOD_0F12_PREFIX_0,
 834   MOD_0F12_PREFIX_2,
 835   MOD_0F13,
 836   MOD_0F16_PREFIX_0,
 837   MOD_0F16_PREFIX_2,
 838   MOD_0F17,
 839   MOD_0F18_REG_0,
 840   MOD_0F18_REG_1,
 841   MOD_0F18_REG_2,
 842   MOD_0F18_REG_3,
 843   MOD_0F1A_PREFIX_0,
 844   MOD_0F1B_PREFIX_0,
 845   MOD_0F1B_PREFIX_1,
 846   MOD_0F1C_PREFIX_0,
 847   MOD_0F1E_PREFIX_1,
 848   MOD_0F2B_PREFIX_0,
 849   MOD_0F2B_PREFIX_1,
 850   MOD_0F2B_PREFIX_2,
 851   MOD_0F2B_PREFIX_3,
 852   MOD_0F50,
 853   MOD_0F71,
 854   MOD_0F72,
 855   MOD_0F73,
 856   MOD_0FAE_REG_0,
 857   MOD_0FAE_REG_1,
 858   MOD_0FAE_REG_2,
 859   MOD_0FAE_REG_3,
 860   MOD_0FAE_REG_4,
 861   MOD_0FAE_REG_5,
 862   MOD_0FAE_REG_6,
 863   MOD_0FAE_REG_7,
 864   MOD_0FB2,
 865   MOD_0FB4,
 866   MOD_0FB5,
 867   MOD_0FC3,
 868   MOD_0FC7_REG_3,
 869   MOD_0FC7_REG_4,
 870   MOD_0FC7_REG_5,
 871   MOD_0FC7_REG_6,
 872   MOD_0FC7_REG_7,
 873   MOD_0FD7,
 874   MOD_0FE7_PREFIX_2,
 875   MOD_0FF0_PREFIX_3,
 876   MOD_0F382A,
 877   MOD_0F38DC_PREFIX_1,
 878   MOD_0F38DD_PREFIX_1,
 879   MOD_0F38DE_PREFIX_1,
 880   MOD_0F38DF_PREFIX_1,
 881   MOD_0F38F5,
 882   MOD_0F38F6_PREFIX_0,
 883   MOD_0F38F8_PREFIX_1,
 884   MOD_0F38F8_PREFIX_2,
 885   MOD_0F38F8_PREFIX_3,
 886   MOD_0F38F9,
 887   MOD_0F38FA_PREFIX_1,
 888   MOD_0F38FB_PREFIX_1,
 889   MOD_0F3A0F_PREFIX_1,
 890
 891   MOD_VEX_0F12_PREFIX_0,
 892   MOD_VEX_0F12_PREFIX_2,
 893   MOD_VEX_0F13,
 894   MOD_VEX_0F16_PREFIX_0,
 895   MOD_VEX_0F16_PREFIX_2,
 896   MOD_VEX_0F17,
 897   MOD_VEX_0F2B,
 898   MOD_VEX_0F41_L_1,
 899   MOD_VEX_0F42_L_1,
 900   MOD_VEX_0F44_L_0,
 901   MOD_VEX_0F45_L_1,
 902   MOD_VEX_0F46_L_1,
 903   MOD_VEX_0F47_L_1,
 904   MOD_VEX_0F4A_L_1,
 905   MOD_VEX_0F4B_L_1,
 906   MOD_VEX_0F50,
 907   MOD_VEX_0F71,
 908   MOD_VEX_0F72,
 909   MOD_VEX_0F73,
 910   MOD_VEX_0F91_L_0,
 911   MOD_VEX_0F92_L_0,
 912   MOD_VEX_0F93_L_0,
 913   MOD_VEX_0F98_L_0,
 914   MOD_VEX_0F99_L_0,
 915   MOD_VEX_0FAE_REG_2,
 916   MOD_VEX_0FAE_REG_3,
 917   MOD_VEX_0FD7,
 918   MOD_VEX_0FE7,
 919   MOD_VEX_0FF0_PREFIX_3,
 920   MOD_VEX_0F381A,
 921   MOD_VEX_0F382A,
 922   MOD_VEX_0F382C,
 923   MOD_VEX_0F382D,
 924   MOD_VEX_0F382E,
 925   MOD_VEX_0F382F,
 926   MOD_VEX_0F3849_X86_64_P_0_W_0,
 927   MOD_VEX_0F3849_X86_64_P_2_W_0,
 928   MOD_VEX_0F3849_X86_64_P_3_W_0,
 929   MOD_VEX_0F384B_X86_64_P_1_W_0,
 930   MOD_VEX_0F384B_X86_64_P_2_W_0,
 931   MOD_VEX_0F384B_X86_64_P_3_W_0,
 932   MOD_VEX_0F385A,
 933   MOD_VEX_0F385C_X86_64_P_1_W_0,
 934   MOD_VEX_0F385C_X86_64_P_3_W_0,
 935   MOD_VEX_0F385E_X86_64_P_0_W_0,
 936   MOD_VEX_0F385E_X86_64_P_1_W_0,
 937   MOD_VEX_0F385E_X86_64_P_2_W_0,
 938   MOD_VEX_0F385E_X86_64_P_3_W_0,
 939   MOD_VEX_0F388C,
 940   MOD_VEX_0F388E,
 941   MOD_VEX_0F3A30_L_0,
 942   MOD_VEX_0F3A31_L_0,
 943   MOD_VEX_0F3A32_L_0,
 944   MOD_VEX_0F3A33_L_0,
 945
 946   MOD_XOP_09_12,
 947
 948   MOD_EVEX_0F381A,
 949   MOD_EVEX_0F381B,
 950   MOD_EVEX_0F3828_P_1,
 951   MOD_EVEX_0F382A_P_1_W_1,
 952   MOD_EVEX_0F3838_P_1,
 953   MOD_EVEX_0F383A_P_1_W_0,
 954   MOD_EVEX_0F385A,
 955   MOD_EVEX_0F385B,
 956   MOD_EVEX_0F387A_W_0,
 957   MOD_EVEX_0F387B_W_0,
 958   MOD_EVEX_0F387C,
 959   MOD_EVEX_0F38C6,
 960   MOD_EVEX_0F38C7,
 961 };
 962
 963 enum
 964 {
 965   RM_C6_REG_7 = 0,
 966   RM_C7_REG_7,
 967   RM_0F01_REG_0,
 968   RM_0F01_REG_1,
 969   RM_0F01_REG_2,
 970   RM_0F01_REG_3,
 971   RM_0F01_REG_5_MOD_3,
 972   RM_0F01_REG_7_MOD_3,
 973   RM_0F1E_P_1_MOD_3_REG_7,
 974   RM_0FAE_REG_6_MOD_3_P_0,
 975   RM_0FAE_REG_7_MOD_3,
 976   RM_0F3A0F_P_1_MOD_3_REG_0,
 977
 978   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 979 };
 980
 981 enum
 982 {
 983   PREFIX_90 = 0,
 984   PREFIX_0F01_REG_1_RM_4,
 985   PREFIX_0F01_REG_1_RM_5,
 986   PREFIX_0F01_REG_1_RM_6,
 987   PREFIX_0F01_REG_1_RM_7,
 988   PREFIX_0F01_REG_3_RM_1,
 989   PREFIX_0F01_REG_5_MOD_0,
 990   PREFIX_0F01_REG_5_MOD_3_RM_0,
 991   PREFIX_0F01_REG_5_MOD_3_RM_1,
 992   PREFIX_0F01_REG_5_MOD_3_RM_2,
 993   PREFIX_0F01_REG_5_MOD_3_RM_4,
 994   PREFIX_0F01_REG_5_MOD_3_RM_5,
 995   PREFIX_0F01_REG_5_MOD_3_RM_6,
 996   PREFIX_0F01_REG_5_MOD_3_RM_7,
 997   PREFIX_0F01_REG_7_MOD_3_RM_2,
 998   PREFIX_0F01_REG_7_MOD_3_RM_6,
 999   PREFIX_0F01_REG_7_MOD_3_RM_7,
1000   PREFIX_0F09,
1001   PREFIX_0F10,
1002   PREFIX_0F11,
1003   PREFIX_0F12,
1004   PREFIX_0F16,
1005   PREFIX_0F1A,
1006   PREFIX_0F1B,
1007   PREFIX_0F1C,
1008   PREFIX_0F1E,
1009   PREFIX_0F2A,
1010   PREFIX_0F2B,
1011   PREFIX_0F2C,
1012   PREFIX_0F2D,
1013   PREFIX_0F2E,
1014   PREFIX_0F2F,
1015   PREFIX_0F51,
1016   PREFIX_0F52,
1017   PREFIX_0F53,
1018   PREFIX_0F58,
1019   PREFIX_0F59,
1020   PREFIX_0F5A,
1021   PREFIX_0F5B,
1022   PREFIX_0F5C,
1023   PREFIX_0F5D,
1024   PREFIX_0F5E,
1025   PREFIX_0F5F,
1026   PREFIX_0F60,
1027   PREFIX_0F61,
1028   PREFIX_0F62,
1029   PREFIX_0F6F,
1030   PREFIX_0F70,
1031   PREFIX_0F78,
1032   PREFIX_0F79,
1033   PREFIX_0F7C,
1034   PREFIX_0F7D,
1035   PREFIX_0F7E,
1036   PREFIX_0F7F,
1037   PREFIX_0FAE_REG_0_MOD_3,
1038   PREFIX_0FAE_REG_1_MOD_3,
1039   PREFIX_0FAE_REG_2_MOD_3,
1040   PREFIX_0FAE_REG_3_MOD_3,
1041   PREFIX_0FAE_REG_4_MOD_0,
1042   PREFIX_0FAE_REG_4_MOD_3,
1043   PREFIX_0FAE_REG_5_MOD_3,
1044   PREFIX_0FAE_REG_6_MOD_0,
1045   PREFIX_0FAE_REG_6_MOD_3,
1046   PREFIX_0FAE_REG_7_MOD_0,
1047   PREFIX_0FB8,
1048   PREFIX_0FBC,
1049   PREFIX_0FBD,
1050   PREFIX_0FC2,
1051   PREFIX_0FC7_REG_6_MOD_0,
1052   PREFIX_0FC7_REG_6_MOD_3,
1053   PREFIX_0FC7_REG_7_MOD_3,
1054   PREFIX_0FD0,
1055   PREFIX_0FD6,
1056   PREFIX_0FE6,
1057   PREFIX_0FE7,
1058   PREFIX_0FF0,
1059   PREFIX_0FF7,
1060   PREFIX_0F38D8,
1061   PREFIX_0F38DC,
1062   PREFIX_0F38DD,
1063   PREFIX_0F38DE,
1064   PREFIX_0F38DF,
1065   PREFIX_0F38F0,
1066   PREFIX_0F38F1,
1067   PREFIX_0F38F6,
1068   PREFIX_0F38F8,
1069   PREFIX_0F38FA,
1070   PREFIX_0F38FB,
1071   PREFIX_0F3A0F,
1072   PREFIX_VEX_0F10,
1073   PREFIX_VEX_0F11,
1074   PREFIX_VEX_0F12,
1075   PREFIX_VEX_0F16,
1076   PREFIX_VEX_0F2A,
1077   PREFIX_VEX_0F2C,
1078   PREFIX_VEX_0F2D,
1079   PREFIX_VEX_0F2E,
1080   PREFIX_VEX_0F2F,
1081   PREFIX_VEX_0F41_L_1_M_1_W_0,
1082   PREFIX_VEX_0F41_L_1_M_1_W_1,
1083   PREFIX_VEX_0F42_L_1_M_1_W_0,
1084   PREFIX_VEX_0F42_L_1_M_1_W_1,
1085   PREFIX_VEX_0F44_L_0_M_1_W_0,
1086   PREFIX_VEX_0F44_L_0_M_1_W_1,
1087   PREFIX_VEX_0F45_L_1_M_1_W_0,
1088   PREFIX_VEX_0F45_L_1_M_1_W_1,
1089   PREFIX_VEX_0F46_L_1_M_1_W_0,
1090   PREFIX_VEX_0F46_L_1_M_1_W_1,
1091   PREFIX_VEX_0F47_L_1_M_1_W_0,
1092   PREFIX_VEX_0F47_L_1_M_1_W_1,
1093   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1094   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1095   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1096   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1097   PREFIX_VEX_0F51,
1098   PREFIX_VEX_0F52,
1099   PREFIX_VEX_0F53,
1100   PREFIX_VEX_0F58,
1101   PREFIX_VEX_0F59,
1102   PREFIX_VEX_0F5A,
1103   PREFIX_VEX_0F5B,
1104   PREFIX_VEX_0F5C,
1105   PREFIX_VEX_0F5D,
1106   PREFIX_VEX_0F5E,
1107   PREFIX_VEX_0F5F,
1108   PREFIX_VEX_0F6F,
1109   PREFIX_VEX_0F70,
1110   PREFIX_VEX_0F7C,
1111   PREFIX_VEX_0F7D,
1112   PREFIX_VEX_0F7E,
1113   PREFIX_VEX_0F7F,
1114   PREFIX_VEX_0F90_L_0_W_0,
1115   PREFIX_VEX_0F90_L_0_W_1,
1116   PREFIX_VEX_0F91_L_0_M_0_W_0,
1117   PREFIX_VEX_0F91_L_0_M_0_W_1,
1118   PREFIX_VEX_0F92_L_0_M_1_W_0,
1119   PREFIX_VEX_0F92_L_0_M_1_W_1,
1120   PREFIX_VEX_0F93_L_0_M_1_W_0,
1121   PREFIX_VEX_0F93_L_0_M_1_W_1,
1122   PREFIX_VEX_0F98_L_0_M_1_W_0,
1123   PREFIX_VEX_0F98_L_0_M_1_W_1,
1124   PREFIX_VEX_0F99_L_0_M_1_W_0,
1125   PREFIX_VEX_0F99_L_0_M_1_W_1,
1126   PREFIX_VEX_0FC2,
1127   PREFIX_VEX_0FD0,
1128   PREFIX_VEX_0FE6,
1129   PREFIX_VEX_0FF0,
1130   PREFIX_VEX_0F3849_X86_64,
1131   PREFIX_VEX_0F384B_X86_64,
1132   PREFIX_VEX_0F385C_X86_64,
1133   PREFIX_VEX_0F385E_X86_64,
1134   PREFIX_VEX_0F38F5_L_0,
1135   PREFIX_VEX_0F38F6_L_0,
1136   PREFIX_VEX_0F38F7_L_0,
1137   PREFIX_VEX_0F3AF0_L_0,
1138
1139   PREFIX_EVEX_0F5B,
1140   PREFIX_EVEX_0F6F,
1141   PREFIX_EVEX_0F70,
1142   PREFIX_EVEX_0F78,
1143   PREFIX_EVEX_0F79,
1144   PREFIX_EVEX_0F7A,
1145   PREFIX_EVEX_0F7B,
1146   PREFIX_EVEX_0F7E,
1147   PREFIX_EVEX_0F7F,
1148   PREFIX_EVEX_0FC2,
1149   PREFIX_EVEX_0FE6,
1150   PREFIX_EVEX_0F3810,
1151   PREFIX_EVEX_0F3811,
1152   PREFIX_EVEX_0F3812,
1153   PREFIX_EVEX_0F3813,
1154   PREFIX_EVEX_0F3814,
1155   PREFIX_EVEX_0F3815,
1156   PREFIX_EVEX_0F3820,
1157   PREFIX_EVEX_0F3821,
1158   PREFIX_EVEX_0F3822,
1159   PREFIX_EVEX_0F3823,
1160   PREFIX_EVEX_0F3824,
1161   PREFIX_EVEX_0F3825,
1162   PREFIX_EVEX_0F3826,
1163   PREFIX_EVEX_0F3827,
1164   PREFIX_EVEX_0F3828,
1165   PREFIX_EVEX_0F3829,
1166   PREFIX_EVEX_0F382A,
1167   PREFIX_EVEX_0F3830,
1168   PREFIX_EVEX_0F3831,
1169   PREFIX_EVEX_0F3832,
1170   PREFIX_EVEX_0F3833,
1171   PREFIX_EVEX_0F3834,
1172   PREFIX_EVEX_0F3835,
1173   PREFIX_EVEX_0F3838,
1174   PREFIX_EVEX_0F3839,
1175   PREFIX_EVEX_0F383A,
1176   PREFIX_EVEX_0F3852,
1177   PREFIX_EVEX_0F3853,
1178   PREFIX_EVEX_0F3868,
1179   PREFIX_EVEX_0F3872,
1180   PREFIX_EVEX_0F389A,
1181   PREFIX_EVEX_0F389B,
1182   PREFIX_EVEX_0F38AA,
1183   PREFIX_EVEX_0F38AB,
1184
1185   PREFIX_EVEX_0F3A08,
1186   PREFIX_EVEX_0F3A0A,
1187   PREFIX_EVEX_0F3A26,
1188   PREFIX_EVEX_0F3A27,
1189   PREFIX_EVEX_0F3A56,
1190   PREFIX_EVEX_0F3A57,
1191   PREFIX_EVEX_0F3A66,
1192   PREFIX_EVEX_0F3A67,
1193   PREFIX_EVEX_0F3AC2,
1194
1195   PREFIX_EVEX_MAP5_10,
1196   PREFIX_EVEX_MAP5_11,
1197   PREFIX_EVEX_MAP5_1D,
1198   PREFIX_EVEX_MAP5_2A,
1199   PREFIX_EVEX_MAP5_2C,
1200   PREFIX_EVEX_MAP5_2D,
1201   PREFIX_EVEX_MAP5_2E,
1202   PREFIX_EVEX_MAP5_2F,
1203   PREFIX_EVEX_MAP5_51,
1204   PREFIX_EVEX_MAP5_58,
1205   PREFIX_EVEX_MAP5_59,
1206   PREFIX_EVEX_MAP5_5A,
1207   PREFIX_EVEX_MAP5_5B,
1208   PREFIX_EVEX_MAP5_5C,
1209   PREFIX_EVEX_MAP5_5D,
1210   PREFIX_EVEX_MAP5_5E,
1211   PREFIX_EVEX_MAP5_5F,
1212   PREFIX_EVEX_MAP5_78,
1213   PREFIX_EVEX_MAP5_79,
1214   PREFIX_EVEX_MAP5_7A,
1215   PREFIX_EVEX_MAP5_7B,
1216   PREFIX_EVEX_MAP5_7C,
1217   PREFIX_EVEX_MAP5_7D,
1218
1219   PREFIX_EVEX_MAP6_13,
1220   PREFIX_EVEX_MAP6_56,
1221   PREFIX_EVEX_MAP6_57,
1222   PREFIX_EVEX_MAP6_D6,
1223   PREFIX_EVEX_MAP6_D7,
1224 };
1225
1226 enum
1227 {
1228   X86_64_06 = 0,
1229   X86_64_07,
1230   X86_64_0E,
1231   X86_64_16,
1232   X86_64_17,
1233   X86_64_1E,
1234   X86_64_1F,
1235   X86_64_27,
1236   X86_64_2F,
1237   X86_64_37,
1238   X86_64_3F,
1239   X86_64_60,
1240   X86_64_61,
1241   X86_64_62,
1242   X86_64_63,
1243   X86_64_6D,
1244   X86_64_6F,
1245   X86_64_82,
1246   X86_64_9A,
1247   X86_64_C2,
1248   X86_64_C3,
1249   X86_64_C4,
1250   X86_64_C5,
1251   X86_64_CE,
1252   X86_64_D4,
1253   X86_64_D5,
1254   X86_64_E8,
1255   X86_64_E9,
1256   X86_64_EA,
1257   X86_64_0F01_REG_0,
1258   X86_64_0F01_REG_1,
1259   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1260   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1261   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1262   X86_64_0F01_REG_2,
1263   X86_64_0F01_REG_3,
1264   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1265   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1266   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1267   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1268   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1269   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1270   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1271   X86_64_0F24,
1272   X86_64_0F26,
1273   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1274
1275   X86_64_VEX_0F3849,
1276   X86_64_VEX_0F384B,
1277   X86_64_VEX_0F385C,
1278   X86_64_VEX_0F385E
1279 };
1280
1281 enum
1282 {
1283   THREE_BYTE_0F38 = 0,
1284   THREE_BYTE_0F3A
1285 };
1286
1287 enum
1288 {
1289   XOP_08 = 0,
1290   XOP_09,
1291   XOP_0A
1292 };
1293
1294 enum
1295 {
1296   VEX_0F = 0,
1297   VEX_0F38,
1298   VEX_0F3A
1299 };
1300
1301 enum
1302 {
1303   EVEX_0F = 0,
1304   EVEX_0F38,
1305   EVEX_0F3A,
1306   EVEX_MAP5,
1307   EVEX_MAP6,
1308 };
1309
1310 enum
1311 {
1312   VEX_LEN_0F12_P_0_M_0 = 0,
1313   VEX_LEN_0F12_P_0_M_1,
1314 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1315   VEX_LEN_0F13_M_0,
1316   VEX_LEN_0F16_P_0_M_0,
1317   VEX_LEN_0F16_P_0_M_1,
1318 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1319   VEX_LEN_0F17_M_0,
1320   VEX_LEN_0F41,
1321   VEX_LEN_0F42,
1322   VEX_LEN_0F44,
1323   VEX_LEN_0F45,
1324   VEX_LEN_0F46,
1325   VEX_LEN_0F47,
1326   VEX_LEN_0F4A,
1327   VEX_LEN_0F4B,
1328   VEX_LEN_0F6E,
1329   VEX_LEN_0F77,
1330   VEX_LEN_0F7E_P_1,
1331   VEX_LEN_0F7E_P_2,
1332   VEX_LEN_0F90,
1333   VEX_LEN_0F91,
1334   VEX_LEN_0F92,
1335   VEX_LEN_0F93,
1336   VEX_LEN_0F98,
1337   VEX_LEN_0F99,
1338   VEX_LEN_0FAE_R_2_M_0,
1339   VEX_LEN_0FAE_R_3_M_0,
1340   VEX_LEN_0FC4,
1341   VEX_LEN_0FC5,
1342   VEX_LEN_0FD6,
1343   VEX_LEN_0FF7,
1344   VEX_LEN_0F3816,
1345   VEX_LEN_0F3819,
1346   VEX_LEN_0F381A_M_0,
1347   VEX_LEN_0F3836,
1348   VEX_LEN_0F3841,
1349   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1350   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1351   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1352   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1353   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1354   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1355   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1356   VEX_LEN_0F385A_M_0,
1357   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1358   VEX_LEN_0F385C_X86_64_P_3_W_0_M_0,
1359   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1360   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1361   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1362   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1363   VEX_LEN_0F38DB,
1364   VEX_LEN_0F38F2,
1365   VEX_LEN_0F38F3,
1366   VEX_LEN_0F38F5,
1367   VEX_LEN_0F38F6,
1368   VEX_LEN_0F38F7,
1369   VEX_LEN_0F3A00,
1370   VEX_LEN_0F3A01,
1371   VEX_LEN_0F3A06,
1372   VEX_LEN_0F3A14,
1373   VEX_LEN_0F3A15,
1374   VEX_LEN_0F3A16,
1375   VEX_LEN_0F3A17,
1376   VEX_LEN_0F3A18,
1377   VEX_LEN_0F3A19,
1378   VEX_LEN_0F3A20,
1379   VEX_LEN_0F3A21,
1380   VEX_LEN_0F3A22,
1381   VEX_LEN_0F3A30,
1382   VEX_LEN_0F3A31,
1383   VEX_LEN_0F3A32,
1384   VEX_LEN_0F3A33,
1385   VEX_LEN_0F3A38,
1386   VEX_LEN_0F3A39,
1387   VEX_LEN_0F3A41,
1388   VEX_LEN_0F3A46,
1389   VEX_LEN_0F3A60,
1390   VEX_LEN_0F3A61,
1391   VEX_LEN_0F3A62,
1392   VEX_LEN_0F3A63,
1393   VEX_LEN_0F3ADF,
1394   VEX_LEN_0F3AF0,
1395   VEX_LEN_0FXOP_08_85,
1396   VEX_LEN_0FXOP_08_86,
1397   VEX_LEN_0FXOP_08_87,
1398   VEX_LEN_0FXOP_08_8E,
1399   VEX_LEN_0FXOP_08_8F,
1400   VEX_LEN_0FXOP_08_95,
1401   VEX_LEN_0FXOP_08_96,
1402   VEX_LEN_0FXOP_08_97,
1403   VEX_LEN_0FXOP_08_9E,
1404   VEX_LEN_0FXOP_08_9F,
1405   VEX_LEN_0FXOP_08_A3,
1406   VEX_LEN_0FXOP_08_A6,
1407   VEX_LEN_0FXOP_08_B6,
1408   VEX_LEN_0FXOP_08_C0,
1409   VEX_LEN_0FXOP_08_C1,
1410   VEX_LEN_0FXOP_08_C2,
1411   VEX_LEN_0FXOP_08_C3,
1412   VEX_LEN_0FXOP_08_CC,
1413   VEX_LEN_0FXOP_08_CD,
1414   VEX_LEN_0FXOP_08_CE,
1415   VEX_LEN_0FXOP_08_CF,
1416   VEX_LEN_0FXOP_08_EC,
1417   VEX_LEN_0FXOP_08_ED,
1418   VEX_LEN_0FXOP_08_EE,
1419   VEX_LEN_0FXOP_08_EF,
1420   VEX_LEN_0FXOP_09_01,
1421   VEX_LEN_0FXOP_09_02,
1422   VEX_LEN_0FXOP_09_12_M_1,
1423   VEX_LEN_0FXOP_09_82_W_0,
1424   VEX_LEN_0FXOP_09_83_W_0,
1425   VEX_LEN_0FXOP_09_90,
1426   VEX_LEN_0FXOP_09_91,
1427   VEX_LEN_0FXOP_09_92,
1428   VEX_LEN_0FXOP_09_93,
1429   VEX_LEN_0FXOP_09_94,
1430   VEX_LEN_0FXOP_09_95,
1431   VEX_LEN_0FXOP_09_96,
1432   VEX_LEN_0FXOP_09_97,
1433   VEX_LEN_0FXOP_09_98,
1434   VEX_LEN_0FXOP_09_99,
1435   VEX_LEN_0FXOP_09_9A,
1436   VEX_LEN_0FXOP_09_9B,
1437   VEX_LEN_0FXOP_09_C1,
1438   VEX_LEN_0FXOP_09_C2,
1439   VEX_LEN_0FXOP_09_C3,
1440   VEX_LEN_0FXOP_09_C6,
1441   VEX_LEN_0FXOP_09_C7,
1442   VEX_LEN_0FXOP_09_CB,
1443   VEX_LEN_0FXOP_09_D1,
1444   VEX_LEN_0FXOP_09_D2,
1445   VEX_LEN_0FXOP_09_D3,
1446   VEX_LEN_0FXOP_09_D6,
1447   VEX_LEN_0FXOP_09_D7,
1448   VEX_LEN_0FXOP_09_DB,
1449   VEX_LEN_0FXOP_09_E1,
1450   VEX_LEN_0FXOP_09_E2,
1451   VEX_LEN_0FXOP_09_E3,
1452   VEX_LEN_0FXOP_0A_12,
1453 };
1454
1455 enum
1456 {
1457   EVEX_LEN_0F3816 = 0,
1458   EVEX_LEN_0F3819,
1459   EVEX_LEN_0F381A_M_0,
1460   EVEX_LEN_0F381B_M_0,
1461   EVEX_LEN_0F3836,
1462   EVEX_LEN_0F385A_M_0,
1463   EVEX_LEN_0F385B_M_0,
1464   EVEX_LEN_0F38C6_M_0,
1465   EVEX_LEN_0F38C7_M_0,
1466   EVEX_LEN_0F3A00,
1467   EVEX_LEN_0F3A01,
1468   EVEX_LEN_0F3A18,
1469   EVEX_LEN_0F3A19,
1470   EVEX_LEN_0F3A1A,
1471   EVEX_LEN_0F3A1B,
1472   EVEX_LEN_0F3A23,
1473   EVEX_LEN_0F3A38,
1474   EVEX_LEN_0F3A39,
1475   EVEX_LEN_0F3A3A,
1476   EVEX_LEN_0F3A3B,
1477   EVEX_LEN_0F3A43
1478 };
1479
1480 enum
1481 {
1482   VEX_W_0F41_L_1_M_1 = 0,
1483   VEX_W_0F42_L_1_M_1,
1484   VEX_W_0F44_L_0_M_1,
1485   VEX_W_0F45_L_1_M_1,
1486   VEX_W_0F46_L_1_M_1,
1487   VEX_W_0F47_L_1_M_1,
1488   VEX_W_0F4A_L_1_M_1,
1489   VEX_W_0F4B_L_1_M_1,
1490   VEX_W_0F90_L_0,
1491   VEX_W_0F91_L_0_M_0,
1492   VEX_W_0F92_L_0_M_1,
1493   VEX_W_0F93_L_0_M_1,
1494   VEX_W_0F98_L_0_M_1,
1495   VEX_W_0F99_L_0_M_1,
1496   VEX_W_0F380C,
1497   VEX_W_0F380D,
1498   VEX_W_0F380E,
1499   VEX_W_0F380F,
1500   VEX_W_0F3813,
1501   VEX_W_0F3816_L_1,
1502   VEX_W_0F3818,
1503   VEX_W_0F3819_L_1,
1504   VEX_W_0F381A_M_0_L_1,
1505   VEX_W_0F382C_M_0,
1506   VEX_W_0F382D_M_0,
1507   VEX_W_0F382E_M_0,
1508   VEX_W_0F382F_M_0,
1509   VEX_W_0F3836,
1510   VEX_W_0F3846,
1511   VEX_W_0F3849_X86_64_P_0,
1512   VEX_W_0F3849_X86_64_P_2,
1513   VEX_W_0F3849_X86_64_P_3,
1514   VEX_W_0F384B_X86_64_P_1,
1515   VEX_W_0F384B_X86_64_P_2,
1516   VEX_W_0F384B_X86_64_P_3,
1517   VEX_W_0F3850,
1518   VEX_W_0F3851,
1519   VEX_W_0F3852,
1520   VEX_W_0F3853,
1521   VEX_W_0F3858,
1522   VEX_W_0F3859,
1523   VEX_W_0F385A_M_0_L_0,
1524   VEX_W_0F385C_X86_64_P_1,
1525   VEX_W_0F385C_X86_64_P_3,
1526   VEX_W_0F385E_X86_64_P_0,
1527   VEX_W_0F385E_X86_64_P_1,
1528   VEX_W_0F385E_X86_64_P_2,
1529   VEX_W_0F385E_X86_64_P_3,
1530   VEX_W_0F3878,
1531   VEX_W_0F3879,
1532   VEX_W_0F38CF,
1533   VEX_W_0F3A00_L_1,
1534   VEX_W_0F3A01_L_1,
1535   VEX_W_0F3A02,
1536   VEX_W_0F3A04,
1537   VEX_W_0F3A05,
1538   VEX_W_0F3A06_L_1,
1539   VEX_W_0F3A18_L_1,
1540   VEX_W_0F3A19_L_1,
1541   VEX_W_0F3A1D,
1542   VEX_W_0F3A38_L_1,
1543   VEX_W_0F3A39_L_1,
1544   VEX_W_0F3A46_L_1,
1545   VEX_W_0F3A4A,
1546   VEX_W_0F3A4B,
1547   VEX_W_0F3A4C,
1548   VEX_W_0F3ACE,
1549   VEX_W_0F3ACF,
1550
1551   VEX_W_0FXOP_08_85_L_0,
1552   VEX_W_0FXOP_08_86_L_0,
1553   VEX_W_0FXOP_08_87_L_0,
1554   VEX_W_0FXOP_08_8E_L_0,
1555   VEX_W_0FXOP_08_8F_L_0,
1556   VEX_W_0FXOP_08_95_L_0,
1557   VEX_W_0FXOP_08_96_L_0,
1558   VEX_W_0FXOP_08_97_L_0,
1559   VEX_W_0FXOP_08_9E_L_0,
1560   VEX_W_0FXOP_08_9F_L_0,
1561   VEX_W_0FXOP_08_A6_L_0,
1562   VEX_W_0FXOP_08_B6_L_0,
1563   VEX_W_0FXOP_08_C0_L_0,
1564   VEX_W_0FXOP_08_C1_L_0,
1565   VEX_W_0FXOP_08_C2_L_0,
1566   VEX_W_0FXOP_08_C3_L_0,
1567   VEX_W_0FXOP_08_CC_L_0,
1568   VEX_W_0FXOP_08_CD_L_0,
1569   VEX_W_0FXOP_08_CE_L_0,
1570   VEX_W_0FXOP_08_CF_L_0,
1571   VEX_W_0FXOP_08_EC_L_0,
1572   VEX_W_0FXOP_08_ED_L_0,
1573   VEX_W_0FXOP_08_EE_L_0,
1574   VEX_W_0FXOP_08_EF_L_0,
1575
1576   VEX_W_0FXOP_09_80,
1577   VEX_W_0FXOP_09_81,
1578   VEX_W_0FXOP_09_82,
1579   VEX_W_0FXOP_09_83,
1580   VEX_W_0FXOP_09_C1_L_0,
1581   VEX_W_0FXOP_09_C2_L_0,
1582   VEX_W_0FXOP_09_C3_L_0,
1583   VEX_W_0FXOP_09_C6_L_0,
1584   VEX_W_0FXOP_09_C7_L_0,
1585   VEX_W_0FXOP_09_CB_L_0,
1586   VEX_W_0FXOP_09_D1_L_0,
1587   VEX_W_0FXOP_09_D2_L_0,
1588   VEX_W_0FXOP_09_D3_L_0,
1589   VEX_W_0FXOP_09_D6_L_0,
1590   VEX_W_0FXOP_09_D7_L_0,
1591   VEX_W_0FXOP_09_DB_L_0,
1592   VEX_W_0FXOP_09_E1_L_0,
1593   VEX_W_0FXOP_09_E2_L_0,
1594   VEX_W_0FXOP_09_E3_L_0,
1595
1596   EVEX_W_0F5B_P_0,
1597   EVEX_W_0F62,
1598   EVEX_W_0F66,
1599   EVEX_W_0F6A,
1600   EVEX_W_0F6B,
1601   EVEX_W_0F6C,
1602   EVEX_W_0F6D,
1603   EVEX_W_0F6F_P_1,
1604   EVEX_W_0F6F_P_2,
1605   EVEX_W_0F6F_P_3,
1606   EVEX_W_0F70_P_2,
1607   EVEX_W_0F72_R_2,
1608   EVEX_W_0F72_R_6,
1609   EVEX_W_0F73_R_2,
1610   EVEX_W_0F73_R_6,
1611   EVEX_W_0F76,
1612   EVEX_W_0F78_P_0,
1613   EVEX_W_0F78_P_2,
1614   EVEX_W_0F79_P_0,
1615   EVEX_W_0F79_P_2,
1616   EVEX_W_0F7A_P_1,
1617   EVEX_W_0F7A_P_2,
1618   EVEX_W_0F7A_P_3,
1619   EVEX_W_0F7B_P_2,
1620   EVEX_W_0F7E_P_1,
1621   EVEX_W_0F7F_P_1,
1622   EVEX_W_0F7F_P_2,
1623   EVEX_W_0F7F_P_3,
1624   EVEX_W_0FD2,
1625   EVEX_W_0FD3,
1626   EVEX_W_0FD4,
1627   EVEX_W_0FD6,
1628   EVEX_W_0FE6_P_1,
1629   EVEX_W_0FE7,
1630   EVEX_W_0FF2,
1631   EVEX_W_0FF3,
1632   EVEX_W_0FF4,
1633   EVEX_W_0FFA,
1634   EVEX_W_0FFB,
1635   EVEX_W_0FFE,
1636
1637   EVEX_W_0F3810_P_1,
1638   EVEX_W_0F3810_P_2,
1639   EVEX_W_0F3811_P_1,
1640   EVEX_W_0F3811_P_2,
1641   EVEX_W_0F3812_P_1,
1642   EVEX_W_0F3812_P_2,
1643   EVEX_W_0F3813_P_1,
1644   EVEX_W_0F3814_P_1,
1645   EVEX_W_0F3815_P_1,
1646   EVEX_W_0F3819_L_n,
1647   EVEX_W_0F381A_M_0_L_n,
1648   EVEX_W_0F381B_M_0_L_2,
1649   EVEX_W_0F381E,
1650   EVEX_W_0F381F,
1651   EVEX_W_0F3820_P_1,
1652   EVEX_W_0F3821_P_1,
1653   EVEX_W_0F3822_P_1,
1654   EVEX_W_0F3823_P_1,
1655   EVEX_W_0F3824_P_1,
1656   EVEX_W_0F3825_P_1,
1657   EVEX_W_0F3825_P_2,
1658   EVEX_W_0F3828_P_2,
1659   EVEX_W_0F3829_P_2,
1660   EVEX_W_0F382A_P_1,
1661   EVEX_W_0F382A_P_2,
1662   EVEX_W_0F382B,
1663   EVEX_W_0F3830_P_1,
1664   EVEX_W_0F3831_P_1,
1665   EVEX_W_0F3832_P_1,
1666   EVEX_W_0F3833_P_1,
1667   EVEX_W_0F3834_P_1,
1668   EVEX_W_0F3835_P_1,
1669   EVEX_W_0F3835_P_2,
1670   EVEX_W_0F3837,
1671   EVEX_W_0F383A_P_1,
1672   EVEX_W_0F3859,
1673   EVEX_W_0F385A_M_0_L_n,
1674   EVEX_W_0F385B_M_0_L_2,
1675   EVEX_W_0F3870,
1676   EVEX_W_0F3872_P_2,
1677   EVEX_W_0F387A,
1678   EVEX_W_0F387B,
1679   EVEX_W_0F3883,
1680
1681   EVEX_W_0F3A18_L_n,
1682   EVEX_W_0F3A19_L_n,
1683   EVEX_W_0F3A1A_L_2,
1684   EVEX_W_0F3A1B_L_2,
1685   EVEX_W_0F3A21,
1686   EVEX_W_0F3A23_L_n,
1687   EVEX_W_0F3A38_L_n,
1688   EVEX_W_0F3A39_L_n,
1689   EVEX_W_0F3A3A_L_2,
1690   EVEX_W_0F3A3B_L_2,
1691   EVEX_W_0F3A42,
1692   EVEX_W_0F3A43_L_n,
1693   EVEX_W_0F3A70,
1694   EVEX_W_0F3A72,
1695
1696   EVEX_W_MAP5_5B_P_0,
1697   EVEX_W_MAP5_7A_P_3,
1698 };
1699
1700 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1701
1702 struct dis386 {
1703   const char *name;
1704   struct
1705     {
1706       op_rtn rtn;
1707       int bytemode;
1708     } op[MAX_OPERANDS];
1709   unsigned int prefix_requirement;
1710 };
1711
1712 /* Upper case letters in the instruction names here are macros.
1713    'A' => print 'b' if no register operands or suffix_always is true
1714    'B' => print 'b' if suffix_always is true
1715    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1716           size prefix
1717    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1718           suffix_always is true
1719    'E' => print 'e' if 32-bit form of jcxz
1720    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1721    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1722    'H' => print ",pt" or ",pn" branch hint
1723    'I' unused.
1724    'J' unused.
1725    'K' => print 'd' or 'q' if rex prefix is present.
1726    'L' unused.
1727    'M' => print 'r' if intel_mnemonic is false.
1728    'N' => print 'n' if instruction has no wait "prefix"
1729    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1730    'P' => behave as 'T' except with register operand outside of suffix_always
1731           mode
1732    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1733           is true
1734    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1735    'S' => print 'w', 'l' or 'q' if suffix_always is true
1736    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1737           prefix or if suffix_always is true.
1738    'U' unused.
1739    'V' unused.
1740    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1741    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1742    'Y' unused.
1743    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1744    '!' => change condition from true to false or from false to true.
1745    '%' => add 1 upper case letter to the macro.
1746    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1747           prefix or suffix_always is true (lcall/ljmp).
1748    '@' => in 64bit mode for Intel64 ISA or if instruction
1749           has no operand sizing prefix, print 'q' if suffix_always is true or
1750           nothing otherwise; behave as 'P' in all other cases
1751
1752    2 upper case letter macros:
1753    "XY" => print 'x' or 'y' if suffix_always is true or no register
1754            operands and no broadcast.
1755    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1756            register operands and no broadcast.
1757    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1758    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1759    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1760    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1761    "XV" => print "{vex} " pseudo prefix
1762    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1763            is used by an EVEX-encoded (AVX512VL) instruction.
1764    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1765            being false, or no operand at all in 64bit mode, or if suffix_always
1766            is true.
1767    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1768    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1769    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1770    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1771    "BW" => print 'b' or 'w' depending on the VEX.W bit
1772    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1773            an operand size prefix, or suffix_always is true.  print
1774            'q' if rex prefix is present.
1775
1776    Many of the above letters print nothing in Intel mode.  See "putop"
1777    for the details.
1778
1779    Braces '{' and '}', and vertical bars '|', indicate alternative
1780    mnemonic strings for AT&T and Intel.  */
1781
1782 static const struct dis386 dis386[] = {
1783   /* 00 */
1784   { "addB",             { Ebh1, Gb }, 0 },
1785   { "addS",             { Evh1, Gv }, 0 },
1786   { "addB",             { Gb, EbS }, 0 },
1787   { "addS",             { Gv, EvS }, 0 },
1788   { "addB",             { AL, Ib }, 0 },
1789   { "addS",             { eAX, Iv }, 0 },
1790   { X86_64_TABLE (X86_64_06) },
1791   { X86_64_TABLE (X86_64_07) },
1792   /* 08 */
1793   { "orB",              { Ebh1, Gb }, 0 },
1794   { "orS",              { Evh1, Gv }, 0 },
1795   { "orB",              { Gb, EbS }, 0 },
1796   { "orS",              { Gv, EvS }, 0 },
1797   { "orB",              { AL, Ib }, 0 },
1798   { "orS",              { eAX, Iv }, 0 },
1799   { X86_64_TABLE (X86_64_0E) },
1800   { Bad_Opcode },       /* 0x0f extended opcode escape */
1801   /* 10 */
1802   { "adcB",             { Ebh1, Gb }, 0 },
1803   { "adcS",             { Evh1, Gv }, 0 },
1804   { "adcB",             { Gb, EbS }, 0 },
1805   { "adcS",             { Gv, EvS }, 0 },
1806   { "adcB",             { AL, Ib }, 0 },
1807   { "adcS",             { eAX, Iv }, 0 },
1808   { X86_64_TABLE (X86_64_16) },
1809   { X86_64_TABLE (X86_64_17) },
1810   /* 18 */
1811   { "sbbB",             { Ebh1, Gb }, 0 },
1812   { "sbbS",             { Evh1, Gv }, 0 },
1813   { "sbbB",             { Gb, EbS }, 0 },
1814   { "sbbS",             { Gv, EvS }, 0 },
1815   { "sbbB",             { AL, Ib }, 0 },
1816   { "sbbS",             { eAX, Iv }, 0 },
1817   { X86_64_TABLE (X86_64_1E) },
1818   { X86_64_TABLE (X86_64_1F) },
1819   /* 20 */
1820   { "andB",             { Ebh1, Gb }, 0 },
1821   { "andS",             { Evh1, Gv }, 0 },
1822   { "andB",             { Gb, EbS }, 0 },
1823   { "andS",             { Gv, EvS }, 0 },
1824   { "andB",             { AL, Ib }, 0 },
1825   { "andS",             { eAX, Iv }, 0 },
1826   { Bad_Opcode },       /* SEG ES prefix */
1827   { X86_64_TABLE (X86_64_27) },
1828   /* 28 */
1829   { "subB",             { Ebh1, Gb }, 0 },
1830   { "subS",             { Evh1, Gv }, 0 },
1831   { "subB",             { Gb, EbS }, 0 },
1832   { "subS",             { Gv, EvS }, 0 },
1833   { "subB",             { AL, Ib }, 0 },
1834   { "subS",             { eAX, Iv }, 0 },
1835   { Bad_Opcode },       /* SEG CS prefix */
1836   { X86_64_TABLE (X86_64_2F) },
1837   /* 30 */
1838   { "xorB",             { Ebh1, Gb }, 0 },
1839   { "xorS",             { Evh1, Gv }, 0 },
1840   { "xorB",             { Gb, EbS }, 0 },
1841   { "xorS",             { Gv, EvS }, 0 },
1842   { "xorB",             { AL, Ib }, 0 },
1843   { "xorS",             { eAX, Iv }, 0 },
1844   { Bad_Opcode },       /* SEG SS prefix */
1845   { X86_64_TABLE (X86_64_37) },
1846   /* 38 */
1847   { "cmpB",             { Eb, Gb }, 0 },
1848   { "cmpS",             { Ev, Gv }, 0 },
1849   { "cmpB",             { Gb, EbS }, 0 },
1850   { "cmpS",             { Gv, EvS }, 0 },
1851   { "cmpB",             { AL, Ib }, 0 },
1852   { "cmpS",             { eAX, Iv }, 0 },
1853   { Bad_Opcode },       /* SEG DS prefix */
1854   { X86_64_TABLE (X86_64_3F) },
1855   /* 40 */
1856   { "inc{S|}",          { RMeAX }, 0 },
1857   { "inc{S|}",          { RMeCX }, 0 },
1858   { "inc{S|}",          { RMeDX }, 0 },
1859   { "inc{S|}",          { RMeBX }, 0 },
1860   { "inc{S|}",          { RMeSP }, 0 },
1861   { "inc{S|}",          { RMeBP }, 0 },
1862   { "inc{S|}",          { RMeSI }, 0 },
1863   { "inc{S|}",          { RMeDI }, 0 },
1864   /* 48 */
1865   { "dec{S|}",          { RMeAX }, 0 },
1866   { "dec{S|}",          { RMeCX }, 0 },
1867   { "dec{S|}",          { RMeDX }, 0 },
1868   { "dec{S|}",          { RMeBX }, 0 },
1869   { "dec{S|}",          { RMeSP }, 0 },
1870   { "dec{S|}",          { RMeBP }, 0 },
1871   { "dec{S|}",          { RMeSI }, 0 },
1872   { "dec{S|}",          { RMeDI }, 0 },
1873   /* 50 */
1874   { "push{!P|}",                { RMrAX }, 0 },
1875   { "push{!P|}",                { RMrCX }, 0 },
1876   { "push{!P|}",                { RMrDX }, 0 },
1877   { "push{!P|}",                { RMrBX }, 0 },
1878   { "push{!P|}",                { RMrSP }, 0 },
1879   { "push{!P|}",                { RMrBP }, 0 },
1880   { "push{!P|}",                { RMrSI }, 0 },
1881   { "push{!P|}",                { RMrDI }, 0 },
1882   /* 58 */
1883   { "pop{!P|}",         { RMrAX }, 0 },
1884   { "pop{!P|}",         { RMrCX }, 0 },
1885   { "pop{!P|}",         { RMrDX }, 0 },
1886   { "pop{!P|}",         { RMrBX }, 0 },
1887   { "pop{!P|}",         { RMrSP }, 0 },
1888   { "pop{!P|}",         { RMrBP }, 0 },
1889   { "pop{!P|}",         { RMrSI }, 0 },
1890   { "pop{!P|}",         { RMrDI }, 0 },
1891   /* 60 */
1892   { X86_64_TABLE (X86_64_60) },
1893   { X86_64_TABLE (X86_64_61) },
1894   { X86_64_TABLE (X86_64_62) },
1895   { X86_64_TABLE (X86_64_63) },
1896   { Bad_Opcode },       /* seg fs */
1897   { Bad_Opcode },       /* seg gs */
1898   { Bad_Opcode },       /* op size prefix */
1899   { Bad_Opcode },       /* adr size prefix */
1900   /* 68 */
1901   { "pushP",            { sIv }, 0 },
1902   { "imulS",            { Gv, Ev, Iv }, 0 },
1903   { "pushP",            { sIbT }, 0 },
1904   { "imulS",            { Gv, Ev, sIb }, 0 },
1905   { "ins{b|}",          { Ybr, indirDX }, 0 },
1906   { X86_64_TABLE (X86_64_6D) },
1907   { "outs{b|}",         { indirDXr, Xb }, 0 },
1908   { X86_64_TABLE (X86_64_6F) },
1909   /* 70 */
1910   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1911   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1912   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1913   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1914   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1915   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1916   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1917   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1918   /* 78 */
1919   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1920   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1921   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1922   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1923   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1924   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1925   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1926   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1927   /* 80 */
1928   { REG_TABLE (REG_80) },
1929   { REG_TABLE (REG_81) },
1930   { X86_64_TABLE (X86_64_82) },
1931   { REG_TABLE (REG_83) },
1932   { "testB",            { Eb, Gb }, 0 },
1933   { "testS",            { Ev, Gv }, 0 },
1934   { "xchgB",            { Ebh2, Gb }, 0 },
1935   { "xchgS",            { Evh2, Gv }, 0 },
1936   /* 88 */
1937   { "movB",             { Ebh3, Gb }, 0 },
1938   { "movS",             { Evh3, Gv }, 0 },
1939   { "movB",             { Gb, EbS }, 0 },
1940   { "movS",             { Gv, EvS }, 0 },
1941   { "movD",             { Sv, Sw }, 0 },
1942   { MOD_TABLE (MOD_8D) },
1943   { "movD",             { Sw, Sv }, 0 },
1944   { REG_TABLE (REG_8F) },
1945   /* 90 */
1946   { PREFIX_TABLE (PREFIX_90) },
1947   { "xchgS",            { RMeCX, eAX }, 0 },
1948   { "xchgS",            { RMeDX, eAX }, 0 },
1949   { "xchgS",            { RMeBX, eAX }, 0 },
1950   { "xchgS",            { RMeSP, eAX }, 0 },
1951   { "xchgS",            { RMeBP, eAX }, 0 },
1952   { "xchgS",            { RMeSI, eAX }, 0 },
1953   { "xchgS",            { RMeDI, eAX }, 0 },
1954   /* 98 */
1955   { "cW{t|}R",          { XX }, 0 },
1956   { "cR{t|}O",          { XX }, 0 },
1957   { X86_64_TABLE (X86_64_9A) },
1958   { Bad_Opcode },       /* fwait */
1959   { "pushfP",           { XX }, 0 },
1960   { "popfP",            { XX }, 0 },
1961   { "sahf",             { XX }, 0 },
1962   { "lahf",             { XX }, 0 },
1963   /* a0 */
1964   { "mov%LB",           { AL, Ob }, 0 },
1965   { "mov%LS",           { eAX, Ov }, 0 },
1966   { "mov%LB",           { Ob, AL }, 0 },
1967   { "mov%LS",           { Ov, eAX }, 0 },
1968   { "movs{b|}",         { Ybr, Xb }, 0 },
1969   { "movs{R|}",         { Yvr, Xv }, 0 },
1970   { "cmps{b|}",         { Xb, Yb }, 0 },
1971   { "cmps{R|}",         { Xv, Yv }, 0 },
1972   /* a8 */
1973   { "testB",            { AL, Ib }, 0 },
1974   { "testS",            { eAX, Iv }, 0 },
1975   { "stosB",            { Ybr, AL }, 0 },
1976   { "stosS",            { Yvr, eAX }, 0 },
1977   { "lodsB",            { ALr, Xb }, 0 },
1978   { "lodsS",            { eAXr, Xv }, 0 },
1979   { "scasB",            { AL, Yb }, 0 },
1980   { "scasS",            { eAX, Yv }, 0 },
1981   /* b0 */
1982   { "movB",             { RMAL, Ib }, 0 },
1983   { "movB",             { RMCL, Ib }, 0 },
1984   { "movB",             { RMDL, Ib }, 0 },
1985   { "movB",             { RMBL, Ib }, 0 },
1986   { "movB",             { RMAH, Ib }, 0 },
1987   { "movB",             { RMCH, Ib }, 0 },
1988   { "movB",             { RMDH, Ib }, 0 },
1989   { "movB",             { RMBH, Ib }, 0 },
1990   /* b8 */
1991   { "mov%LV",           { RMeAX, Iv64 }, 0 },
1992   { "mov%LV",           { RMeCX, Iv64 }, 0 },
1993   { "mov%LV",           { RMeDX, Iv64 }, 0 },
1994   { "mov%LV",           { RMeBX, Iv64 }, 0 },
1995   { "mov%LV",           { RMeSP, Iv64 }, 0 },
1996   { "mov%LV",           { RMeBP, Iv64 }, 0 },
1997   { "mov%LV",           { RMeSI, Iv64 }, 0 },
1998   { "mov%LV",           { RMeDI, Iv64 }, 0 },
1999   /* c0 */
2000   { REG_TABLE (REG_C0) },
2001   { REG_TABLE (REG_C1) },
2002   { X86_64_TABLE (X86_64_C2) },
2003   { X86_64_TABLE (X86_64_C3) },
2004   { X86_64_TABLE (X86_64_C4) },
2005   { X86_64_TABLE (X86_64_C5) },
2006   { REG_TABLE (REG_C6) },
2007   { REG_TABLE (REG_C7) },
2008   /* c8 */
2009   { "enterP",           { Iw, Ib }, 0 },
2010   { "leaveP",           { XX }, 0 },
2011   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2012   { "{l|}ret{|f}%LP",   { XX }, 0 },
2013   { "int3",             { XX }, 0 },
2014   { "int",              { Ib }, 0 },
2015   { X86_64_TABLE (X86_64_CE) },
2016   { "iret%LP",          { XX }, 0 },
2017   /* d0 */
2018   { REG_TABLE (REG_D0) },
2019   { REG_TABLE (REG_D1) },
2020   { REG_TABLE (REG_D2) },
2021   { REG_TABLE (REG_D3) },
2022   { X86_64_TABLE (X86_64_D4) },
2023   { X86_64_TABLE (X86_64_D5) },
2024   { Bad_Opcode },
2025   { "xlat",             { DSBX }, 0 },
2026   /* d8 */
2027   { FLOAT },
2028   { FLOAT },
2029   { FLOAT },
2030   { FLOAT },
2031   { FLOAT },
2032   { FLOAT },
2033   { FLOAT },
2034   { FLOAT },
2035   /* e0 */
2036   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2037   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2038   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2039   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2040   { "inB",              { AL, Ib }, 0 },
2041   { "inG",              { zAX, Ib }, 0 },
2042   { "outB",             { Ib, AL }, 0 },
2043   { "outG",             { Ib, zAX }, 0 },
2044   /* e8 */
2045   { X86_64_TABLE (X86_64_E8) },
2046   { X86_64_TABLE (X86_64_E9) },
2047   { X86_64_TABLE (X86_64_EA) },
2048   { "jmp",              { Jb, BND }, 0 },
2049   { "inB",              { AL, indirDX }, 0 },
2050   { "inG",              { zAX, indirDX }, 0 },
2051   { "outB",             { indirDX, AL }, 0 },
2052   { "outG",             { indirDX, zAX }, 0 },
2053   /* f0 */
2054   { Bad_Opcode },       /* lock prefix */
2055   { "int1",             { XX }, 0 },
2056   { Bad_Opcode },       /* repne */
2057   { Bad_Opcode },       /* repz */
2058   { "hlt",              { XX }, 0 },
2059   { "cmc",              { XX }, 0 },
2060   { REG_TABLE (REG_F6) },
2061   { REG_TABLE (REG_F7) },
2062   /* f8 */
2063   { "clc",              { XX }, 0 },
2064   { "stc",              { XX }, 0 },
2065   { "cli",              { XX }, 0 },
2066   { "sti",              { XX }, 0 },
2067   { "cld",              { XX }, 0 },
2068   { "std",              { XX }, 0 },
2069   { REG_TABLE (REG_FE) },
2070   { REG_TABLE (REG_FF) },
2071 };
2072
2073 static const struct dis386 dis386_twobyte[] = {
2074   /* 00 */
2075   { REG_TABLE (REG_0F00 ) },
2076   { REG_TABLE (REG_0F01 ) },
2077   { "larS",             { Gv, Ew }, 0 },
2078   { "lslS",             { Gv, Ew }, 0 },
2079   { Bad_Opcode },
2080   { "syscall",          { XX }, 0 },
2081   { "clts",             { XX }, 0 },
2082   { "sysret%LQ",                { XX }, 0 },
2083   /* 08 */
2084   { "invd",             { XX }, 0 },
2085   { PREFIX_TABLE (PREFIX_0F09) },
2086   { Bad_Opcode },
2087   { "ud2",              { XX }, 0 },
2088   { Bad_Opcode },
2089   { REG_TABLE (REG_0F0D) },
2090   { "femms",            { XX }, 0 },
2091   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2092   /* 10 */
2093   { PREFIX_TABLE (PREFIX_0F10) },
2094   { PREFIX_TABLE (PREFIX_0F11) },
2095   { PREFIX_TABLE (PREFIX_0F12) },
2096   { MOD_TABLE (MOD_0F13) },
2097   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2098   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2099   { PREFIX_TABLE (PREFIX_0F16) },
2100   { MOD_TABLE (MOD_0F17) },
2101   /* 18 */
2102   { REG_TABLE (REG_0F18) },
2103   { "nopQ",             { Ev }, 0 },
2104   { PREFIX_TABLE (PREFIX_0F1A) },
2105   { PREFIX_TABLE (PREFIX_0F1B) },
2106   { PREFIX_TABLE (PREFIX_0F1C) },
2107   { "nopQ",             { Ev }, 0 },
2108   { PREFIX_TABLE (PREFIX_0F1E) },
2109   { "nopQ",             { Ev }, 0 },
2110   /* 20 */
2111   { "movZ",             { Em, Cm }, 0 },
2112   { "movZ",             { Em, Dm }, 0 },
2113   { "movZ",             { Cm, Em }, 0 },
2114   { "movZ",             { Dm, Em }, 0 },
2115   { X86_64_TABLE (X86_64_0F24) },
2116   { Bad_Opcode },
2117   { X86_64_TABLE (X86_64_0F26) },
2118   { Bad_Opcode },
2119   /* 28 */
2120   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2121   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2122   { PREFIX_TABLE (PREFIX_0F2A) },
2123   { PREFIX_TABLE (PREFIX_0F2B) },
2124   { PREFIX_TABLE (PREFIX_0F2C) },
2125   { PREFIX_TABLE (PREFIX_0F2D) },
2126   { PREFIX_TABLE (PREFIX_0F2E) },
2127   { PREFIX_TABLE (PREFIX_0F2F) },
2128   /* 30 */
2129   { "wrmsr",            { XX }, 0 },
2130   { "rdtsc",            { XX }, 0 },
2131   { "rdmsr",            { XX }, 0 },
2132   { "rdpmc",            { XX }, 0 },
2133   { "sysenter",         { SEP }, 0 },
2134   { "sysexit%LQ",       { SEP }, 0 },
2135   { Bad_Opcode },
2136   { "getsec",           { XX }, 0 },
2137   /* 38 */
2138   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2139   { Bad_Opcode },
2140   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2141   { Bad_Opcode },
2142   { Bad_Opcode },
2143   { Bad_Opcode },
2144   { Bad_Opcode },
2145   { Bad_Opcode },
2146   /* 40 */
2147   { "cmovoS",           { Gv, Ev }, 0 },
2148   { "cmovnoS",          { Gv, Ev }, 0 },
2149   { "cmovbS",           { Gv, Ev }, 0 },
2150   { "cmovaeS",          { Gv, Ev }, 0 },
2151   { "cmoveS",           { Gv, Ev }, 0 },
2152   { "cmovneS",          { Gv, Ev }, 0 },
2153   { "cmovbeS",          { Gv, Ev }, 0 },
2154   { "cmovaS",           { Gv, Ev }, 0 },
2155   /* 48 */
2156   { "cmovsS",           { Gv, Ev }, 0 },
2157   { "cmovnsS",          { Gv, Ev }, 0 },
2158   { "cmovpS",           { Gv, Ev }, 0 },
2159   { "cmovnpS",          { Gv, Ev }, 0 },
2160   { "cmovlS",           { Gv, Ev }, 0 },
2161   { "cmovgeS",          { Gv, Ev }, 0 },
2162   { "cmovleS",          { Gv, Ev }, 0 },
2163   { "cmovgS",           { Gv, Ev }, 0 },
2164   /* 50 */
2165   { MOD_TABLE (MOD_0F50) },
2166   { PREFIX_TABLE (PREFIX_0F51) },
2167   { PREFIX_TABLE (PREFIX_0F52) },
2168   { PREFIX_TABLE (PREFIX_0F53) },
2169   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2170   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2171   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2172   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2173   /* 58 */
2174   { PREFIX_TABLE (PREFIX_0F58) },
2175   { PREFIX_TABLE (PREFIX_0F59) },
2176   { PREFIX_TABLE (PREFIX_0F5A) },
2177   { PREFIX_TABLE (PREFIX_0F5B) },
2178   { PREFIX_TABLE (PREFIX_0F5C) },
2179   { PREFIX_TABLE (PREFIX_0F5D) },
2180   { PREFIX_TABLE (PREFIX_0F5E) },
2181   { PREFIX_TABLE (PREFIX_0F5F) },
2182   /* 60 */
2183   { PREFIX_TABLE (PREFIX_0F60) },
2184   { PREFIX_TABLE (PREFIX_0F61) },
2185   { PREFIX_TABLE (PREFIX_0F62) },
2186   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2187   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2188   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2189   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2190   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2191   /* 68 */
2192   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2193   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2194   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2195   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2196   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2197   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2198   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2199   { PREFIX_TABLE (PREFIX_0F6F) },
2200   /* 70 */
2201   { PREFIX_TABLE (PREFIX_0F70) },
2202   { MOD_TABLE (MOD_0F71) },
2203   { MOD_TABLE (MOD_0F72) },
2204   { MOD_TABLE (MOD_0F73) },
2205   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2206   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2207   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2208   { "emms",             { XX }, PREFIX_OPCODE },
2209   /* 78 */
2210   { PREFIX_TABLE (PREFIX_0F78) },
2211   { PREFIX_TABLE (PREFIX_0F79) },
2212   { Bad_Opcode },
2213   { Bad_Opcode },
2214   { PREFIX_TABLE (PREFIX_0F7C) },
2215   { PREFIX_TABLE (PREFIX_0F7D) },
2216   { PREFIX_TABLE (PREFIX_0F7E) },
2217   { PREFIX_TABLE (PREFIX_0F7F) },
2218   /* 80 */
2219   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2220   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2221   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2222   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2223   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2224   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2225   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2226   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2227   /* 88 */
2228   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2229   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2230   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2231   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2232   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2233   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2234   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2235   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2236   /* 90 */
2237   { "seto",             { Eb }, 0 },
2238   { "setno",            { Eb }, 0 },
2239   { "setb",             { Eb }, 0 },
2240   { "setae",            { Eb }, 0 },
2241   { "sete",             { Eb }, 0 },
2242   { "setne",            { Eb }, 0 },
2243   { "setbe",            { Eb }, 0 },
2244   { "seta",             { Eb }, 0 },
2245   /* 98 */
2246   { "sets",             { Eb }, 0 },
2247   { "setns",            { Eb }, 0 },
2248   { "setp",             { Eb }, 0 },
2249   { "setnp",            { Eb }, 0 },
2250   { "setl",             { Eb }, 0 },
2251   { "setge",            { Eb }, 0 },
2252   { "setle",            { Eb }, 0 },
2253   { "setg",             { Eb }, 0 },
2254   /* a0 */
2255   { "pushP",            { fs }, 0 },
2256   { "popP",             { fs }, 0 },
2257   { "cpuid",            { XX }, 0 },
2258   { "btS",              { Ev, Gv }, 0 },
2259   { "shldS",            { Ev, Gv, Ib }, 0 },
2260   { "shldS",            { Ev, Gv, CL }, 0 },
2261   { REG_TABLE (REG_0FA6) },
2262   { REG_TABLE (REG_0FA7) },
2263   /* a8 */
2264   { "pushP",            { gs }, 0 },
2265   { "popP",             { gs }, 0 },
2266   { "rsm",              { XX }, 0 },
2267   { "btsS",             { Evh1, Gv }, 0 },
2268   { "shrdS",            { Ev, Gv, Ib }, 0 },
2269   { "shrdS",            { Ev, Gv, CL }, 0 },
2270   { REG_TABLE (REG_0FAE) },
2271   { "imulS",            { Gv, Ev }, 0 },
2272   /* b0 */
2273   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2274   { "cmpxchgS",         { Evh1, Gv }, 0 },
2275   { MOD_TABLE (MOD_0FB2) },
2276   { "btrS",             { Evh1, Gv }, 0 },
2277   { MOD_TABLE (MOD_0FB4) },
2278   { MOD_TABLE (MOD_0FB5) },
2279   { "movz{bR|x}",       { Gv, Eb }, 0 },
2280   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2281   /* b8 */
2282   { PREFIX_TABLE (PREFIX_0FB8) },
2283   { "ud1S",             { Gv, Ev }, 0 },
2284   { REG_TABLE (REG_0FBA) },
2285   { "btcS",             { Evh1, Gv }, 0 },
2286   { PREFIX_TABLE (PREFIX_0FBC) },
2287   { PREFIX_TABLE (PREFIX_0FBD) },
2288   { "movs{bR|x}",       { Gv, Eb }, 0 },
2289   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2290   /* c0 */
2291   { "xaddB",            { Ebh1, Gb }, 0 },
2292   { "xaddS",            { Evh1, Gv }, 0 },
2293   { PREFIX_TABLE (PREFIX_0FC2) },
2294   { MOD_TABLE (MOD_0FC3) },
2295   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2296   { "pextrw",           { Gd, MS, Ib }, PREFIX_OPCODE },
2297   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2298   { REG_TABLE (REG_0FC7) },
2299   /* c8 */
2300   { "bswap",            { RMeAX }, 0 },
2301   { "bswap",            { RMeCX }, 0 },
2302   { "bswap",            { RMeDX }, 0 },
2303   { "bswap",            { RMeBX }, 0 },
2304   { "bswap",            { RMeSP }, 0 },
2305   { "bswap",            { RMeBP }, 0 },
2306   { "bswap",            { RMeSI }, 0 },
2307   { "bswap",            { RMeDI }, 0 },
2308   /* d0 */
2309   { PREFIX_TABLE (PREFIX_0FD0) },
2310   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2311   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2312   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2313   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2314   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2315   { PREFIX_TABLE (PREFIX_0FD6) },
2316   { MOD_TABLE (MOD_0FD7) },
2317   /* d8 */
2318   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2319   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2320   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2321   { "pand",             { MX, EM }, PREFIX_OPCODE },
2322   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2323   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2324   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2325   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2326   /* e0 */
2327   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2328   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2329   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2330   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2331   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2332   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2333   { PREFIX_TABLE (PREFIX_0FE6) },
2334   { PREFIX_TABLE (PREFIX_0FE7) },
2335   /* e8 */
2336   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2337   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2338   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2339   { "por",              { MX, EM }, PREFIX_OPCODE },
2340   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2341   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2342   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2343   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2344   /* f0 */
2345   { PREFIX_TABLE (PREFIX_0FF0) },
2346   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2347   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2348   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2349   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2350   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2351   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2352   { PREFIX_TABLE (PREFIX_0FF7) },
2353   /* f8 */
2354   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2355   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2356   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2357   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2358   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2359   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2360   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2361   { "ud0S",             { Gv, Ev }, 0 },
2362 };
2363
2364 static const bool onebyte_has_modrm[256] = {
2365   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2366   /*       -------------------------------        */
2367   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2368   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2369   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2370   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2371   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2372   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2373   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2374   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2375   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2376   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2377   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2378   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2379   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2380   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2381   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2382   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2383   /*       -------------------------------        */
2384   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2385 };
2386
2387 static const bool twobyte_has_modrm[256] = {
2388   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2389   /*       -------------------------------        */
2390   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2391   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2392   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2393   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2394   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2395   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2396   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2397   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2398   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2399   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2400   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2401   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2402   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2403   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2404   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2405   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2406   /*       -------------------------------        */
2407   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2408 };
2409
2410
2411 struct op
2412   {
2413     const char *name;
2414     unsigned int len;
2415   };
2416
2417 /* If we are accessing mod/rm/reg without need_modrm set, then the
2418    values are stale.  Hitting this abort likely indicates that you
2419    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2420 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2421
2422 static const char *const intel_index16[] = {
2423   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2424 };
2425
2426 static const char *const att_names64[] = {
2427   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2428   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2429 };
2430 static const char *const att_names32[] = {
2431   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2432   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2433 };
2434 static const char *const att_names16[] = {
2435   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2436   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2437 };
2438 static const char *const att_names8[] = {
2439   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2440 };
2441 static const char *const att_names8rex[] = {
2442   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2443   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2444 };
2445 static const char *const att_names_seg[] = {
2446   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2447 };
2448 static const char att_index64[] = "%riz";
2449 static const char att_index32[] = "%eiz";
2450 static const char *const att_index16[] = {
2451   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2452 };
2453
2454 static const char *const att_names_mm[] = {
2455   "%mm0", "%mm1", "%mm2", "%mm3",
2456   "%mm4", "%mm5", "%mm6", "%mm7"
2457 };
2458
2459 static const char *const att_names_bnd[] = {
2460   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2461 };
2462
2463 static const char *const att_names_xmm[] = {
2464   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2465   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2466   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2467   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2468   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2469   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2470   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2471   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2472 };
2473
2474 static const char *const att_names_ymm[] = {
2475   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2476   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2477   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2478   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2479   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2480   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2481   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2482   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2483 };
2484
2485 static const char *const att_names_zmm[] = {
2486   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2487   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2488   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2489   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2490   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2491   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2492   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2493   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2494 };
2495
2496 static const char *const att_names_tmm[] = {
2497   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2498   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2499 };
2500
2501 static const char *const att_names_mask[] = {
2502   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2503 };
2504
2505 static const char *const names_rounding[] =
2506 {
2507   "{rn-",
2508   "{rd-",
2509   "{ru-",
2510   "{rz-"
2511 };
2512
2513 static const struct dis386 reg_table[][8] = {
2514   /* REG_80 */
2515   {
2516     { "addA",   { Ebh1, Ib }, 0 },
2517     { "orA",    { Ebh1, Ib }, 0 },
2518     { "adcA",   { Ebh1, Ib }, 0 },
2519     { "sbbA",   { Ebh1, Ib }, 0 },
2520     { "andA",   { Ebh1, Ib }, 0 },
2521     { "subA",   { Ebh1, Ib }, 0 },
2522     { "xorA",   { Ebh1, Ib }, 0 },
2523     { "cmpA",   { Eb, Ib }, 0 },
2524   },
2525   /* REG_81 */
2526   {
2527     { "addQ",   { Evh1, Iv }, 0 },
2528     { "orQ",    { Evh1, Iv }, 0 },
2529     { "adcQ",   { Evh1, Iv }, 0 },
2530     { "sbbQ",   { Evh1, Iv }, 0 },
2531     { "andQ",   { Evh1, Iv }, 0 },
2532     { "subQ",   { Evh1, Iv }, 0 },
2533     { "xorQ",   { Evh1, Iv }, 0 },
2534     { "cmpQ",   { Ev, Iv }, 0 },
2535   },
2536   /* REG_83 */
2537   {
2538     { "addQ",   { Evh1, sIb }, 0 },
2539     { "orQ",    { Evh1, sIb }, 0 },
2540     { "adcQ",   { Evh1, sIb }, 0 },
2541     { "sbbQ",   { Evh1, sIb }, 0 },
2542     { "andQ",   { Evh1, sIb }, 0 },
2543     { "subQ",   { Evh1, sIb }, 0 },
2544     { "xorQ",   { Evh1, sIb }, 0 },
2545     { "cmpQ",   { Ev, sIb }, 0 },
2546   },
2547   /* REG_8F */
2548   {
2549     { "pop{P|}", { stackEv }, 0 },
2550     { XOP_8F_TABLE (XOP_09) },
2551     { Bad_Opcode },
2552     { Bad_Opcode },
2553     { Bad_Opcode },
2554     { XOP_8F_TABLE (XOP_09) },
2555   },
2556   /* REG_C0 */
2557   {
2558     { "rolA",   { Eb, Ib }, 0 },
2559     { "rorA",   { Eb, Ib }, 0 },
2560     { "rclA",   { Eb, Ib }, 0 },
2561     { "rcrA",   { Eb, Ib }, 0 },
2562     { "shlA",   { Eb, Ib }, 0 },
2563     { "shrA",   { Eb, Ib }, 0 },
2564     { "shlA",   { Eb, Ib }, 0 },
2565     { "sarA",   { Eb, Ib }, 0 },
2566   },
2567   /* REG_C1 */
2568   {
2569     { "rolQ",   { Ev, Ib }, 0 },
2570     { "rorQ",   { Ev, Ib }, 0 },
2571     { "rclQ",   { Ev, Ib }, 0 },
2572     { "rcrQ",   { Ev, Ib }, 0 },
2573     { "shlQ",   { Ev, Ib }, 0 },
2574     { "shrQ",   { Ev, Ib }, 0 },
2575     { "shlQ",   { Ev, Ib }, 0 },
2576     { "sarQ",   { Ev, Ib }, 0 },
2577   },
2578   /* REG_C6 */
2579   {
2580     { "movA",   { Ebh3, Ib }, 0 },
2581     { Bad_Opcode },
2582     { Bad_Opcode },
2583     { Bad_Opcode },
2584     { Bad_Opcode },
2585     { Bad_Opcode },
2586     { Bad_Opcode },
2587     { MOD_TABLE (MOD_C6_REG_7) },
2588   },
2589   /* REG_C7 */
2590   {
2591     { "movQ",   { Evh3, Iv }, 0 },
2592     { Bad_Opcode },
2593     { Bad_Opcode },
2594     { Bad_Opcode },
2595     { Bad_Opcode },
2596     { Bad_Opcode },
2597     { Bad_Opcode },
2598     { MOD_TABLE (MOD_C7_REG_7) },
2599   },
2600   /* REG_D0 */
2601   {
2602     { "rolA",   { Eb, I1 }, 0 },
2603     { "rorA",   { Eb, I1 }, 0 },
2604     { "rclA",   { Eb, I1 }, 0 },
2605     { "rcrA",   { Eb, I1 }, 0 },
2606     { "shlA",   { Eb, I1 }, 0 },
2607     { "shrA",   { Eb, I1 }, 0 },
2608     { "shlA",   { Eb, I1 }, 0 },
2609     { "sarA",   { Eb, I1 }, 0 },
2610   },
2611   /* REG_D1 */
2612   {
2613     { "rolQ",   { Ev, I1 }, 0 },
2614     { "rorQ",   { Ev, I1 }, 0 },
2615     { "rclQ",   { Ev, I1 }, 0 },
2616     { "rcrQ",   { Ev, I1 }, 0 },
2617     { "shlQ",   { Ev, I1 }, 0 },
2618     { "shrQ",   { Ev, I1 }, 0 },
2619     { "shlQ",   { Ev, I1 }, 0 },
2620     { "sarQ",   { Ev, I1 }, 0 },
2621   },
2622   /* REG_D2 */
2623   {
2624     { "rolA",   { Eb, CL }, 0 },
2625     { "rorA",   { Eb, CL }, 0 },
2626     { "rclA",   { Eb, CL }, 0 },
2627     { "rcrA",   { Eb, CL }, 0 },
2628     { "shlA",   { Eb, CL }, 0 },
2629     { "shrA",   { Eb, CL }, 0 },
2630     { "shlA",   { Eb, CL }, 0 },
2631     { "sarA",   { Eb, CL }, 0 },
2632   },
2633   /* REG_D3 */
2634   {
2635     { "rolQ",   { Ev, CL }, 0 },
2636     { "rorQ",   { Ev, CL }, 0 },
2637     { "rclQ",   { Ev, CL }, 0 },
2638     { "rcrQ",   { Ev, CL }, 0 },
2639     { "shlQ",   { Ev, CL }, 0 },
2640     { "shrQ",   { Ev, CL }, 0 },
2641     { "shlQ",   { Ev, CL }, 0 },
2642     { "sarQ",   { Ev, CL }, 0 },
2643   },
2644   /* REG_F6 */
2645   {
2646     { "testA",  { Eb, Ib }, 0 },
2647     { "testA",  { Eb, Ib }, 0 },
2648     { "notA",   { Ebh1 }, 0 },
2649     { "negA",   { Ebh1 }, 0 },
2650     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2651     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2652     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2653     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2654   },
2655   /* REG_F7 */
2656   {
2657     { "testQ",  { Ev, Iv }, 0 },
2658     { "testQ",  { Ev, Iv }, 0 },
2659     { "notQ",   { Evh1 }, 0 },
2660     { "negQ",   { Evh1 }, 0 },
2661     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2662     { "imulQ",  { Ev }, 0 },
2663     { "divQ",   { Ev }, 0 },
2664     { "idivQ",  { Ev }, 0 },
2665   },
2666   /* REG_FE */
2667   {
2668     { "incA",   { Ebh1 }, 0 },
2669     { "decA",   { Ebh1 }, 0 },
2670   },
2671   /* REG_FF */
2672   {
2673     { "incQ",   { Evh1 }, 0 },
2674     { "decQ",   { Evh1 }, 0 },
2675     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2676     { MOD_TABLE (MOD_FF_REG_3) },
2677     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2678     { MOD_TABLE (MOD_FF_REG_5) },
2679     { "push{P|}", { stackEv }, 0 },
2680     { Bad_Opcode },
2681   },
2682   /* REG_0F00 */
2683   {
2684     { "sldtD",  { Sv }, 0 },
2685     { "strD",   { Sv }, 0 },
2686     { "lldt",   { Ew }, 0 },
2687     { "ltr",    { Ew }, 0 },
2688     { "verr",   { Ew }, 0 },
2689     { "verw",   { Ew }, 0 },
2690     { Bad_Opcode },
2691     { Bad_Opcode },
2692   },
2693   /* REG_0F01 */
2694   {
2695     { MOD_TABLE (MOD_0F01_REG_0) },
2696     { MOD_TABLE (MOD_0F01_REG_1) },
2697     { MOD_TABLE (MOD_0F01_REG_2) },
2698     { MOD_TABLE (MOD_0F01_REG_3) },
2699     { "smswD",  { Sv }, 0 },
2700     { MOD_TABLE (MOD_0F01_REG_5) },
2701     { "lmsw",   { Ew }, 0 },
2702     { MOD_TABLE (MOD_0F01_REG_7) },
2703   },
2704   /* REG_0F0D */
2705   {
2706     { "prefetch",       { Mb }, 0 },
2707     { "prefetchw",      { Mb }, 0 },
2708     { "prefetchwt1",    { Mb }, 0 },
2709     { "prefetch",       { Mb }, 0 },
2710     { "prefetch",       { Mb }, 0 },
2711     { "prefetch",       { Mb }, 0 },
2712     { "prefetch",       { Mb }, 0 },
2713     { "prefetch",       { Mb }, 0 },
2714   },
2715   /* REG_0F18 */
2716   {
2717     { MOD_TABLE (MOD_0F18_REG_0) },
2718     { MOD_TABLE (MOD_0F18_REG_1) },
2719     { MOD_TABLE (MOD_0F18_REG_2) },
2720     { MOD_TABLE (MOD_0F18_REG_3) },
2721     { "nopQ",           { Ev }, 0 },
2722     { "nopQ",           { Ev }, 0 },
2723     { "nopQ",           { Ev }, 0 },
2724     { "nopQ",           { Ev }, 0 },
2725   },
2726   /* REG_0F1C_P_0_MOD_0 */
2727   {
2728     { "cldemote",       { Mb }, 0 },
2729     { "nopQ",           { Ev }, 0 },
2730     { "nopQ",           { Ev }, 0 },
2731     { "nopQ",           { Ev }, 0 },
2732     { "nopQ",           { Ev }, 0 },
2733     { "nopQ",           { Ev }, 0 },
2734     { "nopQ",           { Ev }, 0 },
2735     { "nopQ",           { Ev }, 0 },
2736   },
2737   /* REG_0F1E_P_1_MOD_3 */
2738   {
2739     { "nopQ",           { Ev }, PREFIX_IGNORED },
2740     { "rdsspK",         { Edq }, 0 },
2741     { "nopQ",           { Ev }, PREFIX_IGNORED },
2742     { "nopQ",           { Ev }, PREFIX_IGNORED },
2743     { "nopQ",           { Ev }, PREFIX_IGNORED },
2744     { "nopQ",           { Ev }, PREFIX_IGNORED },
2745     { "nopQ",           { Ev }, PREFIX_IGNORED },
2746     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2747   },
2748   /* REG_0F38D8_PREFIX_1 */
2749   {
2750     { "aesencwide128kl",        { M }, 0 },
2751     { "aesdecwide128kl",        { M }, 0 },
2752     { "aesencwide256kl",        { M }, 0 },
2753     { "aesdecwide256kl",        { M }, 0 },
2754   },
2755   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2756   {
2757     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2758   },
2759   /* REG_0F71_MOD_0 */
2760   {
2761     { Bad_Opcode },
2762     { Bad_Opcode },
2763     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2764     { Bad_Opcode },
2765     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2766     { Bad_Opcode },
2767     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2768   },
2769   /* REG_0F72_MOD_0 */
2770   {
2771     { Bad_Opcode },
2772     { Bad_Opcode },
2773     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2774     { Bad_Opcode },
2775     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2776     { Bad_Opcode },
2777     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2778   },
2779   /* REG_0F73_MOD_0 */
2780   {
2781     { Bad_Opcode },
2782     { Bad_Opcode },
2783     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2784     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2785     { Bad_Opcode },
2786     { Bad_Opcode },
2787     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2788     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2789   },
2790   /* REG_0FA6 */
2791   {
2792     { "montmul",        { { OP_0f07, 0 } }, 0 },
2793     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2794     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2795   },
2796   /* REG_0FA7 */
2797   {
2798     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2799     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2800     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2801     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2802     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2803     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2804   },
2805   /* REG_0FAE */
2806   {
2807     { MOD_TABLE (MOD_0FAE_REG_0) },
2808     { MOD_TABLE (MOD_0FAE_REG_1) },
2809     { MOD_TABLE (MOD_0FAE_REG_2) },
2810     { MOD_TABLE (MOD_0FAE_REG_3) },
2811     { MOD_TABLE (MOD_0FAE_REG_4) },
2812     { MOD_TABLE (MOD_0FAE_REG_5) },
2813     { MOD_TABLE (MOD_0FAE_REG_6) },
2814     { MOD_TABLE (MOD_0FAE_REG_7) },
2815   },
2816   /* REG_0FBA */
2817   {
2818     { Bad_Opcode },
2819     { Bad_Opcode },
2820     { Bad_Opcode },
2821     { Bad_Opcode },
2822     { "btQ",    { Ev, Ib }, 0 },
2823     { "btsQ",   { Evh1, Ib }, 0 },
2824     { "btrQ",   { Evh1, Ib }, 0 },
2825     { "btcQ",   { Evh1, Ib }, 0 },
2826   },
2827   /* REG_0FC7 */
2828   {
2829     { Bad_Opcode },
2830     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2831     { Bad_Opcode },
2832     { MOD_TABLE (MOD_0FC7_REG_3) },
2833     { MOD_TABLE (MOD_0FC7_REG_4) },
2834     { MOD_TABLE (MOD_0FC7_REG_5) },
2835     { MOD_TABLE (MOD_0FC7_REG_6) },
2836     { MOD_TABLE (MOD_0FC7_REG_7) },
2837   },
2838   /* REG_VEX_0F71_M_0 */
2839   {
2840     { Bad_Opcode },
2841     { Bad_Opcode },
2842     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2843     { Bad_Opcode },
2844     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2845     { Bad_Opcode },
2846     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2847   },
2848   /* REG_VEX_0F72_M_0 */
2849   {
2850     { Bad_Opcode },
2851     { Bad_Opcode },
2852     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2853     { Bad_Opcode },
2854     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2855     { Bad_Opcode },
2856     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2857   },
2858   /* REG_VEX_0F73_M_0 */
2859   {
2860     { Bad_Opcode },
2861     { Bad_Opcode },
2862     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2863     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2864     { Bad_Opcode },
2865     { Bad_Opcode },
2866     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2867     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2868   },
2869   /* REG_VEX_0FAE */
2870   {
2871     { Bad_Opcode },
2872     { Bad_Opcode },
2873     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2874     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2875   },
2876   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2877   {
2878     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2879   },
2880   /* REG_VEX_0F38F3_L_0 */
2881   {
2882     { Bad_Opcode },
2883     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2884     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2885     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2886   },
2887   /* REG_XOP_09_01_L_0 */
2888   {
2889     { Bad_Opcode },
2890     { "blcfill",        { VexGdq, Edq }, 0 },
2891     { "blsfill",        { VexGdq, Edq }, 0 },
2892     { "blcs",   { VexGdq, Edq }, 0 },
2893     { "tzmsk",  { VexGdq, Edq }, 0 },
2894     { "blcic",  { VexGdq, Edq }, 0 },
2895     { "blsic",  { VexGdq, Edq }, 0 },
2896     { "t1mskc", { VexGdq, Edq }, 0 },
2897   },
2898   /* REG_XOP_09_02_L_0 */
2899   {
2900     { Bad_Opcode },
2901     { "blcmsk", { VexGdq, Edq }, 0 },
2902     { Bad_Opcode },
2903     { Bad_Opcode },
2904     { Bad_Opcode },
2905     { Bad_Opcode },
2906     { "blci",   { VexGdq, Edq }, 0 },
2907   },
2908   /* REG_XOP_09_12_M_1_L_0 */
2909   {
2910     { "llwpcb", { Edq }, 0 },
2911     { "slwpcb", { Edq }, 0 },
2912   },
2913   /* REG_XOP_0A_12_L_0 */
2914   {
2915     { "lwpins", { VexGdq, Ed, Id }, 0 },
2916     { "lwpval", { VexGdq, Ed, Id }, 0 },
2917   },
2918
2919 #include "i386-dis-evex-reg.h"
2920 };
2921
2922 static const struct dis386 prefix_table[][4] = {
2923   /* PREFIX_90 */
2924   {
2925     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2926     { "pause", { XX }, 0 },
2927     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2928     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2929   },
2930
2931   /* PREFIX_0F01_REG_1_RM_4 */
2932   {
2933     { Bad_Opcode },
2934     { Bad_Opcode },
2935     { "tdcall",         { Skip_MODRM }, 0 },
2936     { Bad_Opcode },
2937   },
2938
2939   /* PREFIX_0F01_REG_1_RM_5 */
2940   {
2941     { Bad_Opcode },
2942     { Bad_Opcode },
2943     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2944     { Bad_Opcode },
2945   },
2946
2947   /* PREFIX_0F01_REG_1_RM_6 */
2948   {
2949     { Bad_Opcode },
2950     { Bad_Opcode },
2951     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
2952     { Bad_Opcode },
2953   },
2954
2955   /* PREFIX_0F01_REG_1_RM_7 */
2956   {
2957     { "encls",          { Skip_MODRM }, 0 },
2958     { Bad_Opcode },
2959     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
2960     { Bad_Opcode },
2961   },
2962
2963   /* PREFIX_0F01_REG_3_RM_1 */
2964   {
2965     { "vmmcall",        { Skip_MODRM }, 0 },
2966     { "vmgexit",        { Skip_MODRM }, 0 },
2967     { Bad_Opcode },
2968     { "vmgexit",        { Skip_MODRM }, 0 },
2969   },
2970
2971   /* PREFIX_0F01_REG_5_MOD_0 */
2972   {
2973     { Bad_Opcode },
2974     { "rstorssp",       { Mq }, PREFIX_OPCODE },
2975   },
2976
2977   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
2978   {
2979     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
2980     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
2981     { Bad_Opcode },
2982     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
2983   },
2984
2985   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
2986   {
2987     { Bad_Opcode },
2988     { Bad_Opcode },
2989     { Bad_Opcode },
2990     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
2991   },
2992
2993   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
2994   {
2995     { Bad_Opcode },
2996     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
2997   },
2998
2999   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3000   {
3001     { Bad_Opcode },
3002     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3003   },
3004
3005   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3006   {
3007     { Bad_Opcode },
3008     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3009   },
3010
3011   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3012   {
3013     { "rdpkru", { Skip_MODRM }, 0 },
3014     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3015   },
3016
3017   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3018   {
3019     { "wrpkru", { Skip_MODRM }, 0 },
3020     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3021   },
3022
3023   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3024   {
3025     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3026     { "mcommit",        { Skip_MODRM }, 0 },
3027   },
3028
3029   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3030   {
3031     { "invlpgb",        { Skip_MODRM }, 0 },
3032     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3033     { Bad_Opcode },
3034     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3035   },
3036
3037   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3038   {
3039     { "tlbsync",        { Skip_MODRM }, 0 },
3040     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3041     { Bad_Opcode },
3042     { "pvalidate",      { Skip_MODRM }, 0 },
3043   },
3044
3045   /* PREFIX_0F09 */
3046   {
3047     { "wbinvd",   { XX }, 0 },
3048     { "wbnoinvd", { XX }, 0 },
3049   },
3050
3051   /* PREFIX_0F10 */
3052   {
3053     { "movups", { XM, EXx }, PREFIX_OPCODE },
3054     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3055     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3056     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3057   },
3058
3059   /* PREFIX_0F11 */
3060   {
3061     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3062     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3063     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3064     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3065   },
3066
3067   /* PREFIX_0F12 */
3068   {
3069     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3070     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3071     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3072     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3073   },
3074
3075   /* PREFIX_0F16 */
3076   {
3077     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3078     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3079     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3080   },
3081
3082   /* PREFIX_0F1A */
3083   {
3084     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3085     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3086     { "bndmov", { Gbnd, Ebnd }, 0 },
3087     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3088   },
3089
3090   /* PREFIX_0F1B */
3091   {
3092     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3093     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3094     { "bndmov", { EbndS, Gbnd }, 0 },
3095     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3096   },
3097
3098   /* PREFIX_0F1C */
3099   {
3100     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3101     { "nopQ",   { Ev }, PREFIX_IGNORED },
3102     { "nopQ",   { Ev }, 0 },
3103     { "nopQ",   { Ev }, PREFIX_IGNORED },
3104   },
3105
3106   /* PREFIX_0F1E */
3107   {
3108     { "nopQ",   { Ev }, 0 },
3109     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3110     { "nopQ",   { Ev }, 0 },
3111     { NULL,     { XX }, PREFIX_IGNORED },
3112   },
3113
3114   /* PREFIX_0F2A */
3115   {
3116     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3117     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3118     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3119     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3120   },
3121
3122   /* PREFIX_0F2B */
3123   {
3124     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3125     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3126     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3127     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3128   },
3129
3130   /* PREFIX_0F2C */
3131   {
3132     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3133     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3134     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3135     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3136   },
3137
3138   /* PREFIX_0F2D */
3139   {
3140     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3141     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3142     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3143     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3144   },
3145
3146   /* PREFIX_0F2E */
3147   {
3148     { "ucomiss",{ XM, EXd }, 0 },
3149     { Bad_Opcode },
3150     { "ucomisd",{ XM, EXq }, 0 },
3151   },
3152
3153   /* PREFIX_0F2F */
3154   {
3155     { "comiss", { XM, EXd }, 0 },
3156     { Bad_Opcode },
3157     { "comisd", { XM, EXq }, 0 },
3158   },
3159
3160   /* PREFIX_0F51 */
3161   {
3162     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3163     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3164     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3165     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3166   },
3167
3168   /* PREFIX_0F52 */
3169   {
3170     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3171     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3172   },
3173
3174   /* PREFIX_0F53 */
3175   {
3176     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3177     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3178   },
3179
3180   /* PREFIX_0F58 */
3181   {
3182     { "addps", { XM, EXx }, PREFIX_OPCODE },
3183     { "addss", { XM, EXd }, PREFIX_OPCODE },
3184     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3185     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3186   },
3187
3188   /* PREFIX_0F59 */
3189   {
3190     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3191     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3192     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3193     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3194   },
3195
3196   /* PREFIX_0F5A */
3197   {
3198     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3199     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3200     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3201     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3202   },
3203
3204   /* PREFIX_0F5B */
3205   {
3206     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3207     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3208     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3209   },
3210
3211   /* PREFIX_0F5C */
3212   {
3213     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3214     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3215     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3216     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3217   },
3218
3219   /* PREFIX_0F5D */
3220   {
3221     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3222     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3223     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3224     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3225   },
3226
3227   /* PREFIX_0F5E */
3228   {
3229     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3230     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3231     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3232     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3233   },
3234
3235   /* PREFIX_0F5F */
3236   {
3237     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3238     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3239     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3240     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3241   },
3242
3243   /* PREFIX_0F60 */
3244   {
3245     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3246     { Bad_Opcode },
3247     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3248   },
3249
3250   /* PREFIX_0F61 */
3251   {
3252     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3253     { Bad_Opcode },
3254     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3255   },
3256
3257   /* PREFIX_0F62 */
3258   {
3259     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3260     { Bad_Opcode },
3261     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3262   },
3263
3264   /* PREFIX_0F6F */
3265   {
3266     { "movq",   { MX, EM }, PREFIX_OPCODE },
3267     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3268     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3269   },
3270
3271   /* PREFIX_0F70 */
3272   {
3273     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3274     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3275     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3276     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3277   },
3278
3279   /* PREFIX_0F78 */
3280   {
3281     {"vmread",  { Em, Gm }, 0 },
3282     { Bad_Opcode },
3283     {"extrq",   { XS, Ib, Ib }, 0 },
3284     {"insertq", { XM, XS, Ib, Ib }, 0 },
3285   },
3286
3287   /* PREFIX_0F79 */
3288   {
3289     {"vmwrite", { Gm, Em }, 0 },
3290     { Bad_Opcode },
3291     {"extrq",   { XM, XS }, 0 },
3292     {"insertq", { XM, XS }, 0 },
3293   },
3294
3295   /* PREFIX_0F7C */
3296   {
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3300     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3301   },
3302
3303   /* PREFIX_0F7D */
3304   {
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3308     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3309   },
3310
3311   /* PREFIX_0F7E */
3312   {
3313     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3314     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3315     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3316   },
3317
3318   /* PREFIX_0F7F */
3319   {
3320     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3321     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3322     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3323   },
3324
3325   /* PREFIX_0FAE_REG_0_MOD_3 */
3326   {
3327     { Bad_Opcode },
3328     { "rdfsbase", { Ev }, 0 },
3329   },
3330
3331   /* PREFIX_0FAE_REG_1_MOD_3 */
3332   {
3333     { Bad_Opcode },
3334     { "rdgsbase", { Ev }, 0 },
3335   },
3336
3337   /* PREFIX_0FAE_REG_2_MOD_3 */
3338   {
3339     { Bad_Opcode },
3340     { "wrfsbase", { Ev }, 0 },
3341   },
3342
3343   /* PREFIX_0FAE_REG_3_MOD_3 */
3344   {
3345     { Bad_Opcode },
3346     { "wrgsbase", { Ev }, 0 },
3347   },
3348
3349   /* PREFIX_0FAE_REG_4_MOD_0 */
3350   {
3351     { "xsave",  { FXSAVE }, 0 },
3352     { "ptwrite{%LQ|}", { Edq }, 0 },
3353   },
3354
3355   /* PREFIX_0FAE_REG_4_MOD_3 */
3356   {
3357     { Bad_Opcode },
3358     { "ptwrite{%LQ|}", { Edq }, 0 },
3359   },
3360
3361   /* PREFIX_0FAE_REG_5_MOD_3 */
3362   {
3363     { "lfence",         { Skip_MODRM }, 0 },
3364     { "incsspK",        { Edq }, PREFIX_OPCODE },
3365   },
3366
3367   /* PREFIX_0FAE_REG_6_MOD_0 */
3368   {
3369     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3370     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3371     { "clwb",   { Mb }, PREFIX_OPCODE },
3372   },
3373
3374   /* PREFIX_0FAE_REG_6_MOD_3 */
3375   {
3376     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3377     { "umonitor",       { Eva }, PREFIX_OPCODE },
3378     { "tpause", { Edq }, PREFIX_OPCODE },
3379     { "umwait", { Edq }, PREFIX_OPCODE },
3380   },
3381
3382   /* PREFIX_0FAE_REG_7_MOD_0 */
3383   {
3384     { "clflush",        { Mb }, 0 },
3385     { Bad_Opcode },
3386     { "clflushopt",     { Mb }, 0 },
3387   },
3388
3389   /* PREFIX_0FB8 */
3390   {
3391     { Bad_Opcode },
3392     { "popcntS", { Gv, Ev }, 0 },
3393   },
3394
3395   /* PREFIX_0FBC */
3396   {
3397     { "bsfS",   { Gv, Ev }, 0 },
3398     { "tzcntS", { Gv, Ev }, 0 },
3399     { "bsfS",   { Gv, Ev }, 0 },
3400   },
3401
3402   /* PREFIX_0FBD */
3403   {
3404     { "bsrS",   { Gv, Ev }, 0 },
3405     { "lzcntS", { Gv, Ev }, 0 },
3406     { "bsrS",   { Gv, Ev }, 0 },
3407   },
3408
3409   /* PREFIX_0FC2 */
3410   {
3411     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3412     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3413     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3414     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3415   },
3416
3417   /* PREFIX_0FC7_REG_6_MOD_0 */
3418   {
3419     { "vmptrld",{ Mq }, 0 },
3420     { "vmxon",  { Mq }, 0 },
3421     { "vmclear",{ Mq }, 0 },
3422   },
3423
3424   /* PREFIX_0FC7_REG_6_MOD_3 */
3425   {
3426     { "rdrand", { Ev }, 0 },
3427     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3428     { "rdrand", { Ev }, 0 }
3429   },
3430
3431   /* PREFIX_0FC7_REG_7_MOD_3 */
3432   {
3433     { "rdseed", { Ev }, 0 },
3434     { "rdpid",  { Em }, 0 },
3435     { "rdseed", { Ev }, 0 },
3436   },
3437
3438   /* PREFIX_0FD0 */
3439   {
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { "addsubpd", { XM, EXx }, 0 },
3443     { "addsubps", { XM, EXx }, 0 },
3444   },
3445
3446   /* PREFIX_0FD6 */
3447   {
3448     { Bad_Opcode },
3449     { "movq2dq",{ XM, MS }, 0 },
3450     { "movq",   { EXqS, XM }, 0 },
3451     { "movdq2q",{ MX, XS }, 0 },
3452   },
3453
3454   /* PREFIX_0FE6 */
3455   {
3456     { Bad_Opcode },
3457     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3458     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3459     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3460   },
3461
3462   /* PREFIX_0FE7 */
3463   {
3464     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3467   },
3468
3469   /* PREFIX_0FF0 */
3470   {
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3475   },
3476
3477   /* PREFIX_0FF7 */
3478   {
3479     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3480     { Bad_Opcode },
3481     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3482   },
3483
3484   /* PREFIX_0F38D8 */
3485   {
3486     { Bad_Opcode },
3487     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3488   },
3489
3490   /* PREFIX_0F38DC */
3491   {
3492     { Bad_Opcode },
3493     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3494     { "aesenc", { XM, EXx }, 0 },
3495   },
3496
3497   /* PREFIX_0F38DD */
3498   {
3499     { Bad_Opcode },
3500     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3501     { "aesenclast", { XM, EXx }, 0 },
3502   },
3503
3504   /* PREFIX_0F38DE */
3505   {
3506     { Bad_Opcode },
3507     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3508     { "aesdec", { XM, EXx }, 0 },
3509   },
3510
3511   /* PREFIX_0F38DF */
3512   {
3513     { Bad_Opcode },
3514     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3515     { "aesdeclast", { XM, EXx }, 0 },
3516   },
3517
3518   /* PREFIX_0F38F0 */
3519   {
3520     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3521     { Bad_Opcode },
3522     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3523     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3524   },
3525
3526   /* PREFIX_0F38F1 */
3527   {
3528     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3529     { Bad_Opcode },
3530     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3531     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3532   },
3533
3534   /* PREFIX_0F38F6 */
3535   {
3536     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3537     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3538     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3539     { Bad_Opcode },
3540   },
3541
3542   /* PREFIX_0F38F8 */
3543   {
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3546     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3547     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3548   },
3549   /* PREFIX_0F38FA */
3550   {
3551     { Bad_Opcode },
3552     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3553   },
3554
3555   /* PREFIX_0F38FB */
3556   {
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3559   },
3560
3561   /* PREFIX_0F3A0F */
3562   {
3563     { Bad_Opcode },
3564     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3565   },
3566
3567   /* PREFIX_VEX_0F10 */
3568   {
3569     { "%XEvmovupX",     { XM, EXEvexXNoBcst }, 0 },
3570     { "%XEvmovs%XS",    { XMScalar, VexScalarR, EXd }, 0 },
3571     { "%XEvmovupX",     { XM, EXEvexXNoBcst }, 0 },
3572     { "%XEvmovs%XD",    { XMScalar, VexScalarR, EXq }, 0 },
3573   },
3574
3575   /* PREFIX_VEX_0F11 */
3576   {
3577     { "%XEvmovupX",     { EXxS, XM }, 0 },
3578     { "%XEvmovs%XS",    { EXdS, VexScalarR, XMScalar }, 0 },
3579     { "%XEvmovupX",     { EXxS, XM }, 0 },
3580     { "%XEvmovs%XD",    { EXqS, VexScalarR, XMScalar }, 0 },
3581   },
3582
3583   /* PREFIX_VEX_0F12 */
3584   {
3585     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3586     { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3587     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3588     { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3589   },
3590
3591   /* PREFIX_VEX_0F16 */
3592   {
3593     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3594     { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3595     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3596   },
3597
3598   /* PREFIX_VEX_0F2A */
3599   {
3600     { Bad_Opcode },
3601     { "%XEvcvtsi2ss{%LQ|}",     { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3602     { Bad_Opcode },
3603     { "%XEvcvtsi2sd{%LQ|}",     { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3604   },
3605
3606   /* PREFIX_VEX_0F2C */
3607   {
3608     { Bad_Opcode },
3609     { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3610     { Bad_Opcode },
3611     { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3612   },
3613
3614   /* PREFIX_VEX_0F2D */
3615   {
3616     { Bad_Opcode },
3617     { "%XEvcvtss2si",   { Gdq, EXd, EXxEVexR }, 0 },
3618     { Bad_Opcode },
3619     { "%XEvcvtsd2si",   { Gdq, EXq, EXxEVexR }, 0 },
3620   },
3621
3622   /* PREFIX_VEX_0F2E */
3623   {
3624     { "%XEvucomisX",    { XMScalar, EXd, EXxEVexS }, 0 },
3625     { Bad_Opcode },
3626     { "%XEvucomisX",    { XMScalar, EXq, EXxEVexS }, 0 },
3627   },
3628
3629   /* PREFIX_VEX_0F2F */
3630   {
3631     { "%XEvcomisX",     { XMScalar, EXd, EXxEVexS }, 0 },
3632     { Bad_Opcode },
3633     { "%XEvcomisX",     { XMScalar, EXq, EXxEVexS }, 0 },
3634   },
3635
3636   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3637   {
3638     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3639     { Bad_Opcode },
3640     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3641   },
3642
3643   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3644   {
3645     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3646     { Bad_Opcode },
3647     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3648   },
3649
3650   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3651   {
3652     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3653     { Bad_Opcode },
3654     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3655   },
3656
3657   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3658   {
3659     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3660     { Bad_Opcode },
3661     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3662   },
3663
3664   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3665   {
3666     { "knotw",          { MaskG, MaskE }, 0 },
3667     { Bad_Opcode },
3668     { "knotb",          { MaskG, MaskE }, 0 },
3669   },
3670
3671   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3672   {
3673     { "knotq",          { MaskG, MaskE }, 0 },
3674     { Bad_Opcode },
3675     { "knotd",          { MaskG, MaskE }, 0 },
3676   },
3677
3678   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3679   {
3680     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3681     { Bad_Opcode },
3682     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3683   },
3684
3685   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3686   {
3687     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3688     { Bad_Opcode },
3689     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3690   },
3691
3692   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3693   {
3694     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3695     { Bad_Opcode },
3696     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3697   },
3698
3699   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3700   {
3701     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3702     { Bad_Opcode },
3703     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3704   },
3705
3706   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3707   {
3708     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3709     { Bad_Opcode },
3710     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3711   },
3712
3713   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3714   {
3715     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3716     { Bad_Opcode },
3717     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3718   },
3719
3720   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3721   {
3722     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3723     { Bad_Opcode },
3724     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3725   },
3726
3727   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3728   {
3729     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3730     { Bad_Opcode },
3731     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3732   },
3733
3734   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3735   {
3736     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3737     { Bad_Opcode },
3738     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3739   },
3740
3741   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3742   {
3743     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3744   },
3745
3746   /* PREFIX_VEX_0F51 */
3747   {
3748     { "%XEvsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3749     { "%XEvsqrts%XS",   { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3750     { "%XEvsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3751     { "%XEvsqrts%XD",   { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3752   },
3753
3754   /* PREFIX_VEX_0F52 */
3755   {
3756     { "vrsqrtps",       { XM, EXx }, 0 },
3757     { "vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3758   },
3759
3760   /* PREFIX_VEX_0F53 */
3761   {
3762     { "vrcpps",         { XM, EXx }, 0 },
3763     { "vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3764   },
3765
3766   /* PREFIX_VEX_0F58 */
3767   {
3768     { "%XEvaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3769     { "%XEvadds%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3770     { "%XEvaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3771     { "%XEvadds%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3772   },
3773
3774   /* PREFIX_VEX_0F59 */
3775   {
3776     { "%XEvmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3777     { "%XEvmuls%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3778     { "%XEvmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3779     { "%XEvmuls%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3780   },
3781
3782   /* PREFIX_VEX_0F5A */
3783   {
3784     { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3785     { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3786     { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3787     { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3788   },
3789
3790   /* PREFIX_VEX_0F5B */
3791   {
3792     { "vcvtdq2ps",      { XM, EXx }, 0 },
3793     { "vcvttps2dq",     { XM, EXx }, 0 },
3794     { "vcvtps2dq",      { XM, EXx }, 0 },
3795   },
3796
3797   /* PREFIX_VEX_0F5C */
3798   {
3799     { "%XEvsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3800     { "%XEvsubs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3801     { "%XEvsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3802     { "%XEvsubs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3803   },
3804
3805   /* PREFIX_VEX_0F5D */
3806   {
3807     { "%XEvminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3808     { "%XEvmins%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3809     { "%XEvminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3810     { "%XEvmins%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3811   },
3812
3813   /* PREFIX_VEX_0F5E */
3814   {
3815     { "%XEvdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3816     { "%XEvdivs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3817     { "%XEvdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3818     { "%XEvdivs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3819   },
3820
3821   /* PREFIX_VEX_0F5F */
3822   {
3823     { "%XEvmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3824     { "%XEvmaxs%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3825     { "%XEvmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3826     { "%XEvmaxs%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3827   },
3828
3829   /* PREFIX_VEX_0F6F */
3830   {
3831     { Bad_Opcode },
3832     { "vmovdqu",        { XM, EXx }, 0 },
3833     { "vmovdqa",        { XM, EXx }, 0 },
3834   },
3835
3836   /* PREFIX_VEX_0F70 */
3837   {
3838     { Bad_Opcode },
3839     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3840     { "vpshufd",        { XM, EXx, Ib }, 0 },
3841     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3842   },
3843
3844   /* PREFIX_VEX_0F7C */
3845   {
3846     { Bad_Opcode },
3847     { Bad_Opcode },
3848     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3849     { "vhaddps",        { XM, Vex, EXx }, 0 },
3850   },
3851
3852   /* PREFIX_VEX_0F7D */
3853   {
3854     { Bad_Opcode },
3855     { Bad_Opcode },
3856     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3857     { "vhsubps",        { XM, Vex, EXx }, 0 },
3858   },
3859
3860   /* PREFIX_VEX_0F7E */
3861   {
3862     { Bad_Opcode },
3863     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3864     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3865   },
3866
3867   /* PREFIX_VEX_0F7F */
3868   {
3869     { Bad_Opcode },
3870     { "vmovdqu",        { EXxS, XM }, 0 },
3871     { "vmovdqa",        { EXxS, XM }, 0 },
3872   },
3873
3874   /* PREFIX_VEX_0F90_L_0_W_0 */
3875   {
3876     { "kmovw",          { MaskG, MaskE }, 0 },
3877     { Bad_Opcode },
3878     { "kmovb",          { MaskG, MaskBDE }, 0 },
3879   },
3880
3881   /* PREFIX_VEX_0F90_L_0_W_1 */
3882   {
3883     { "kmovq",          { MaskG, MaskE }, 0 },
3884     { Bad_Opcode },
3885     { "kmovd",          { MaskG, MaskBDE }, 0 },
3886   },
3887
3888   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3889   {
3890     { "kmovw",          { Ew, MaskG }, 0 },
3891     { Bad_Opcode },
3892     { "kmovb",          { Eb, MaskG }, 0 },
3893   },
3894
3895   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3896   {
3897     { "kmovq",          { Eq, MaskG }, 0 },
3898     { Bad_Opcode },
3899     { "kmovd",          { Ed, MaskG }, 0 },
3900   },
3901
3902   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3903   {
3904     { "kmovw",          { MaskG, Edq }, 0 },
3905     { Bad_Opcode },
3906     { "kmovb",          { MaskG, Edq }, 0 },
3907     { "kmovd",          { MaskG, Edq }, 0 },
3908   },
3909
3910   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3911   {
3912     { Bad_Opcode },
3913     { Bad_Opcode },
3914     { Bad_Opcode },
3915     { "kmovK",          { MaskG, Edq }, 0 },
3916   },
3917
3918   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3919   {
3920     { "kmovw",          { Gdq, MaskE }, 0 },
3921     { Bad_Opcode },
3922     { "kmovb",          { Gdq, MaskE }, 0 },
3923     { "kmovd",          { Gdq, MaskE }, 0 },
3924   },
3925
3926   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3927   {
3928     { Bad_Opcode },
3929     { Bad_Opcode },
3930     { Bad_Opcode },
3931     { "kmovK",          { Gdq, MaskE }, 0 },
3932   },
3933
3934   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3935   {
3936     { "kortestw", { MaskG, MaskE }, 0 },
3937     { Bad_Opcode },
3938     { "kortestb", { MaskG, MaskE }, 0 },
3939   },
3940
3941   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3942   {
3943     { "kortestq", { MaskG, MaskE }, 0 },
3944     { Bad_Opcode },
3945     { "kortestd", { MaskG, MaskE }, 0 },
3946   },
3947
3948   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
3949   {
3950     { "ktestw", { MaskG, MaskE }, 0 },
3951     { Bad_Opcode },
3952     { "ktestb", { MaskG, MaskE }, 0 },
3953   },
3954
3955   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
3956   {
3957     { "ktestq", { MaskG, MaskE }, 0 },
3958     { Bad_Opcode },
3959     { "ktestd", { MaskG, MaskE }, 0 },
3960   },
3961
3962   /* PREFIX_VEX_0FC2 */
3963   {
3964     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
3965     { "vcmpss",         { XMScalar, VexScalar, EXd, CMP }, 0 },
3966     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
3967     { "vcmpsd",         { XMScalar, VexScalar, EXq, CMP }, 0 },
3968   },
3969
3970   /* PREFIX_VEX_0FD0 */
3971   {
3972     { Bad_Opcode },
3973     { Bad_Opcode },
3974     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
3975     { "vaddsubps",      { XM, Vex, EXx }, 0 },
3976   },
3977
3978   /* PREFIX_VEX_0FE6 */
3979   {
3980     { Bad_Opcode },
3981     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
3982     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3983     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3984   },
3985
3986   /* PREFIX_VEX_0FF0 */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3992   },
3993
3994   /* PREFIX_VEX_0F3849_X86_64 */
3995   {
3996     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3997     { Bad_Opcode },
3998     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3999     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4000   },
4001
4002   /* PREFIX_VEX_0F384B_X86_64 */
4003   {
4004     { Bad_Opcode },
4005     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4006     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4007     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4008   },
4009
4010   /* PREFIX_VEX_0F385C_X86_64 */
4011   {
4012     { Bad_Opcode },
4013     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4014     { Bad_Opcode },
4015     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_3) },
4016   },
4017
4018   /* PREFIX_VEX_0F385E_X86_64 */
4019   {
4020     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4021     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4022     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4023     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4024   },
4025
4026   /* PREFIX_VEX_0F38F5_L_0 */
4027   {
4028     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4029     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4030     { Bad_Opcode },
4031     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4032   },
4033
4034   /* PREFIX_VEX_0F38F6_L_0 */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { Bad_Opcode },
4039     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4040   },
4041
4042   /* PREFIX_VEX_0F38F7_L_0 */
4043   {
4044     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4045     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4046     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4047     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4048   },
4049
4050   /* PREFIX_VEX_0F3AF0_L_0 */
4051   {
4052     { Bad_Opcode },
4053     { Bad_Opcode },
4054     { Bad_Opcode },
4055     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4056   },
4057
4058 #include "i386-dis-evex-prefix.h"
4059 };
4060
4061 static const struct dis386 x86_64_table[][2] = {
4062   /* X86_64_06 */
4063   {
4064     { "pushP", { es }, 0 },
4065   },
4066
4067   /* X86_64_07 */
4068   {
4069     { "popP", { es }, 0 },
4070   },
4071
4072   /* X86_64_0E */
4073   {
4074     { "pushP", { cs }, 0 },
4075   },
4076
4077   /* X86_64_16 */
4078   {
4079     { "pushP", { ss }, 0 },
4080   },
4081
4082   /* X86_64_17 */
4083   {
4084     { "popP", { ss }, 0 },
4085   },
4086
4087   /* X86_64_1E */
4088   {
4089     { "pushP", { ds }, 0 },
4090   },
4091
4092   /* X86_64_1F */
4093   {
4094     { "popP", { ds }, 0 },
4095   },
4096
4097   /* X86_64_27 */
4098   {
4099     { "daa", { XX }, 0 },
4100   },
4101
4102   /* X86_64_2F */
4103   {
4104     { "das", { XX }, 0 },
4105   },
4106
4107   /* X86_64_37 */
4108   {
4109     { "aaa", { XX }, 0 },
4110   },
4111
4112   /* X86_64_3F */
4113   {
4114     { "aas", { XX }, 0 },
4115   },
4116
4117   /* X86_64_60 */
4118   {
4119     { "pushaP", { XX }, 0 },
4120   },
4121
4122   /* X86_64_61 */
4123   {
4124     { "popaP", { XX }, 0 },
4125   },
4126
4127   /* X86_64_62 */
4128   {
4129     { MOD_TABLE (MOD_62_32BIT) },
4130     { EVEX_TABLE (EVEX_0F) },
4131   },
4132
4133   /* X86_64_63 */
4134   {
4135     { "arpl", { Ew, Gw }, 0 },
4136     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4137   },
4138
4139   /* X86_64_6D */
4140   {
4141     { "ins{R|}", { Yzr, indirDX }, 0 },
4142     { "ins{G|}", { Yzr, indirDX }, 0 },
4143   },
4144
4145   /* X86_64_6F */
4146   {
4147     { "outs{R|}", { indirDXr, Xz }, 0 },
4148     { "outs{G|}", { indirDXr, Xz }, 0 },
4149   },
4150
4151   /* X86_64_82 */
4152   {
4153     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4154     { REG_TABLE (REG_80) },
4155   },
4156
4157   /* X86_64_9A */
4158   {
4159     { "{l|}call{P|}", { Ap }, 0 },
4160   },
4161
4162   /* X86_64_C2 */
4163   {
4164     { "retP",           { Iw, BND }, 0 },
4165     { "ret@",           { Iw, BND }, 0 },
4166   },
4167
4168   /* X86_64_C3 */
4169   {
4170     { "retP",           { BND }, 0 },
4171     { "ret@",           { BND }, 0 },
4172   },
4173
4174   /* X86_64_C4 */
4175   {
4176     { MOD_TABLE (MOD_C4_32BIT) },
4177     { VEX_C4_TABLE (VEX_0F) },
4178   },
4179
4180   /* X86_64_C5 */
4181   {
4182     { MOD_TABLE (MOD_C5_32BIT) },
4183     { VEX_C5_TABLE (VEX_0F) },
4184   },
4185
4186   /* X86_64_CE */
4187   {
4188     { "into", { XX }, 0 },
4189   },
4190
4191   /* X86_64_D4 */
4192   {
4193     { "aam", { Ib }, 0 },
4194   },
4195
4196   /* X86_64_D5 */
4197   {
4198     { "aad", { Ib }, 0 },
4199   },
4200
4201   /* X86_64_E8 */
4202   {
4203     { "callP",          { Jv, BND }, 0 },
4204     { "call@",          { Jv, BND }, 0 }
4205   },
4206
4207   /* X86_64_E9 */
4208   {
4209     { "jmpP",           { Jv, BND }, 0 },
4210     { "jmp@",           { Jv, BND }, 0 }
4211   },
4212
4213   /* X86_64_EA */
4214   {
4215     { "{l|}jmp{P|}", { Ap }, 0 },
4216   },
4217
4218   /* X86_64_0F01_REG_0 */
4219   {
4220     { "sgdt{Q|Q}", { M }, 0 },
4221     { "sgdt", { M }, 0 },
4222   },
4223
4224   /* X86_64_0F01_REG_1 */
4225   {
4226     { "sidt{Q|Q}", { M }, 0 },
4227     { "sidt", { M }, 0 },
4228   },
4229
4230   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4231   {
4232     { Bad_Opcode },
4233     { "seamret",        { Skip_MODRM }, 0 },
4234   },
4235
4236   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4237   {
4238     { Bad_Opcode },
4239     { "seamops",        { Skip_MODRM }, 0 },
4240   },
4241
4242   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4243   {
4244     { Bad_Opcode },
4245     { "seamcall",       { Skip_MODRM }, 0 },
4246   },
4247
4248   /* X86_64_0F01_REG_2 */
4249   {
4250     { "lgdt{Q|Q}", { M }, 0 },
4251     { "lgdt", { M }, 0 },
4252   },
4253
4254   /* X86_64_0F01_REG_3 */
4255   {
4256     { "lidt{Q|Q}", { M }, 0 },
4257     { "lidt", { M }, 0 },
4258   },
4259
4260   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4261   {
4262     { Bad_Opcode },
4263     { "uiret",  { Skip_MODRM }, 0 },
4264   },
4265
4266   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4267   {
4268     { Bad_Opcode },
4269     { "testui", { Skip_MODRM }, 0 },
4270   },
4271
4272   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4273   {
4274     { Bad_Opcode },
4275     { "clui",   { Skip_MODRM }, 0 },
4276   },
4277
4278   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4279   {
4280     { Bad_Opcode },
4281     { "stui",   { Skip_MODRM }, 0 },
4282   },
4283
4284   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4285   {
4286     { Bad_Opcode },
4287     { "rmpadjust",      { Skip_MODRM }, 0 },
4288   },
4289
4290   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4291   {
4292     { Bad_Opcode },
4293     { "rmpupdate",      { Skip_MODRM }, 0 },
4294   },
4295
4296   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4297   {
4298     { Bad_Opcode },
4299     { "psmash", { Skip_MODRM }, 0 },
4300   },
4301
4302   {
4303     /* X86_64_0F24 */
4304     { "movZ",           { Em, Td }, 0 },
4305   },
4306
4307   {
4308     /* X86_64_0F26 */
4309     { "movZ",           { Td, Em }, 0 },
4310   },
4311
4312   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4313   {
4314     { Bad_Opcode },
4315     { "senduipi",       { Eq }, 0 },
4316   },
4317
4318   /* X86_64_VEX_0F3849 */
4319   {
4320     { Bad_Opcode },
4321     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4322   },
4323
4324   /* X86_64_VEX_0F384B */
4325   {
4326     { Bad_Opcode },
4327     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4328   },
4329
4330   /* X86_64_VEX_0F385C */
4331   {
4332     { Bad_Opcode },
4333     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4334   },
4335
4336   /* X86_64_VEX_0F385E */
4337   {
4338     { Bad_Opcode },
4339     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4340   },
4341 };
4342
4343 static const struct dis386 three_byte_table[][256] = {
4344
4345   /* THREE_BYTE_0F38 */
4346   {
4347     /* 00 */
4348     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4349     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4350     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4351     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4352     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4353     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4354     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4355     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4356     /* 08 */
4357     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4358     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4359     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4360     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     /* 10 */
4366     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4371     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4372     { Bad_Opcode },
4373     { "ptest",  { XM, EXx }, PREFIX_DATA },
4374     /* 18 */
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4380     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4381     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4382     { Bad_Opcode },
4383     /* 20 */
4384     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4385     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4386     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4387     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4388     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4389     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     /* 28 */
4393     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4394     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4395     { MOD_TABLE (MOD_0F382A) },
4396     { "packusdw", { XM, EXx }, PREFIX_DATA },
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     /* 30 */
4402     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4403     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4404     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4405     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4406     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4407     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4408     { Bad_Opcode },
4409     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4410     /* 38 */
4411     { "pminsb", { XM, EXx }, PREFIX_DATA },
4412     { "pminsd", { XM, EXx }, PREFIX_DATA },
4413     { "pminuw", { XM, EXx }, PREFIX_DATA },
4414     { "pminud", { XM, EXx }, PREFIX_DATA },
4415     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4416     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4417     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4418     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4419     /* 40 */
4420     { "pmulld", { XM, EXx }, PREFIX_DATA },
4421     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     /* 48 */
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     /* 50 */
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     /* 58 */
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     /* 60 */
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     /* 68 */
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     /* 70 */
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     /* 78 */
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     /* 80 */
4492     { "invept", { Gm, Mo }, PREFIX_DATA },
4493     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4494     { "invpcid", { Gm, M }, PREFIX_DATA },
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     /* 88 */
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     /* 90 */
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     /* 98 */
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     /* a0 */
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     /* a8 */
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     /* b0 */
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     /* b8 */
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     /* c0 */
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     /* c8 */
4573     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4574     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4575     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4576     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4577     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4578     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4579     { Bad_Opcode },
4580     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4581     /* d0 */
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     /* d8 */
4591     { PREFIX_TABLE (PREFIX_0F38D8) },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { "aesimc", { XM, EXx }, PREFIX_DATA },
4595     { PREFIX_TABLE (PREFIX_0F38DC) },
4596     { PREFIX_TABLE (PREFIX_0F38DD) },
4597     { PREFIX_TABLE (PREFIX_0F38DE) },
4598     { PREFIX_TABLE (PREFIX_0F38DF) },
4599     /* e0 */
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     /* e8 */
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     /* f0 */
4618     { PREFIX_TABLE (PREFIX_0F38F0) },
4619     { PREFIX_TABLE (PREFIX_0F38F1) },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { MOD_TABLE (MOD_0F38F5) },
4624     { PREFIX_TABLE (PREFIX_0F38F6) },
4625     { Bad_Opcode },
4626     /* f8 */
4627     { PREFIX_TABLE (PREFIX_0F38F8) },
4628     { MOD_TABLE (MOD_0F38F9) },
4629     { PREFIX_TABLE (PREFIX_0F38FA) },
4630     { PREFIX_TABLE (PREFIX_0F38FB) },
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635   },
4636   /* THREE_BYTE_0F3A */
4637   {
4638     /* 00 */
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     /* 08 */
4648     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4649     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4650     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4651     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4652     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4653     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4654     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4655     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4656     /* 10 */
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4662     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4663     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4664     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4665     /* 18 */
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     /* 20 */
4675     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4676     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4677     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     /* 28 */
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     /* 30 */
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     /* 38 */
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     /* 40 */
4711     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4712     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4713     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4714     { Bad_Opcode },
4715     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     /* 48 */
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     /* 50 */
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     /* 58 */
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     /* 60 */
4747     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4748     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4749     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4750     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     /* 68 */
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     /* 70 */
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     /* 78 */
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     /* 80 */
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     /* 88 */
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     /* 90 */
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     /* 98 */
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     /* a0 */
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     /* a8 */
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     /* b0 */
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     /* b8 */
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     /* c0 */
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     /* c8 */
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4869     { Bad_Opcode },
4870     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4871     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4872     /* d0 */
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     /* d8 */
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4890     /* e0 */
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     /* e8 */
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     /* f0 */
4909     { PREFIX_TABLE (PREFIX_0F3A0F) },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     /* f8 */
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926   },
4927 };
4928
4929 static const struct dis386 xop_table[][256] = {
4930   /* XOP_08 */
4931   {
4932     /* 00 */
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     /* 08 */
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     /* 10 */
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     /* 18 */
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     /* 20 */
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     /* 28 */
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     /* 30 */
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     /* 38 */
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     /* 40 */
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     /* 48 */
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     /* 50 */
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     /* 58 */
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     /* 60 */
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     /* 68 */
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     /* 70 */
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     /* 78 */
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     /* 80 */
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5083     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5084     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5085     /* 88 */
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5093     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5094     /* 90 */
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5101     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5102     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5103     /* 98 */
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5111     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5112     /* a0 */
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5116     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5120     { Bad_Opcode },
5121     /* a8 */
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     /* b0 */
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5138     { Bad_Opcode },
5139     /* b8 */
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     /* c0 */
5149     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5150     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5151     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5152     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     /* c8 */
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5163     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5164     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5165     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5166     /* d0 */
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     /* d8 */
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     /* e0 */
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     /* e8 */
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5199     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5200     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5201     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5202     /* f0 */
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     /* f8 */
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220   },
5221   /* XOP_09 */
5222   {
5223     /* 00 */
5224     { Bad_Opcode },
5225     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5226     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     /* 08 */
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     /* 10 */
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { MOD_TABLE (MOD_XOP_09_12) },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     /* 18 */
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     /* 20 */
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     /* 28 */
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     /* 30 */
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     /* 38 */
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     /* 40 */
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     /* 48 */
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     /* 50 */
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     /* 58 */
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     /* 60 */
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     /* 68 */
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     /* 70 */
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     /* 78 */
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     /* 80 */
5368     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5369     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5370     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5371     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     /* 88 */
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     /* 90 */
5386     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5387     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5388     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5389     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5390     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5391     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5392     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5393     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5394     /* 98 */
5395     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5396     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5397     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5398     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     /* a0 */
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     /* a8 */
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     /* b0 */
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     /* b8 */
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     /* c0 */
5440     { Bad_Opcode },
5441     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5442     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5443     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5447     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5448     /* c8 */
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     /* d0 */
5458     { Bad_Opcode },
5459     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5460     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5461     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5465     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5466     /* d8 */
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     /* e0 */
5476     { Bad_Opcode },
5477     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5478     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5479     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     /* e8 */
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     /* f0 */
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     /* f8 */
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511   },
5512   /* XOP_0A */
5513   {
5514     /* 00 */
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     /* 08 */
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     /* 10 */
5533     { "bextrS", { Gdq, Edq, Id }, 0 },
5534     { Bad_Opcode },
5535     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     /* 18 */
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     /* 20 */
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     /* 28 */
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     /* 30 */
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     /* 38 */
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     /* 40 */
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     /* 48 */
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     /* 50 */
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     /* 58 */
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     /* 60 */
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     /* 68 */
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     /* 70 */
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     /* 78 */
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     /* 80 */
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     /* 88 */
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     /* 90 */
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     /* 98 */
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     /* a0 */
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     /* a8 */
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     /* b0 */
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     /* b8 */
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     /* c0 */
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     /* c8 */
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     /* d0 */
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     /* d8 */
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     /* e0 */
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     /* e8 */
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     /* f0 */
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     /* f8 */
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802   },
5803 };
5804
5805 static const struct dis386 vex_table[][256] = {
5806   /* VEX_0F */
5807   {
5808     /* 00 */
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     /* 08 */
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     /* 10 */
5827     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5828     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5829     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5830     { MOD_TABLE (MOD_VEX_0F13) },
5831     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5832     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5833     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5834     { MOD_TABLE (MOD_VEX_0F17) },
5835     /* 18 */
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     /* 20 */
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     /* 28 */
5854     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5855     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5856     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5857     { MOD_TABLE (MOD_VEX_0F2B) },
5858     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5859     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5860     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5861     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5862     /* 30 */
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     /* 38 */
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     /* 40 */
5881     { Bad_Opcode },
5882     { VEX_LEN_TABLE (VEX_LEN_0F41) },
5883     { VEX_LEN_TABLE (VEX_LEN_0F42) },
5884     { Bad_Opcode },
5885     { VEX_LEN_TABLE (VEX_LEN_0F44) },
5886     { VEX_LEN_TABLE (VEX_LEN_0F45) },
5887     { VEX_LEN_TABLE (VEX_LEN_0F46) },
5888     { VEX_LEN_TABLE (VEX_LEN_0F47) },
5889     /* 48 */
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5893     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     /* 50 */
5899     { MOD_TABLE (MOD_VEX_0F50) },
5900     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5901     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5902     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5903     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5904     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5905     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5906     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5907     /* 58 */
5908     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5909     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5910     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5911     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5912     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5913     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5914     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5915     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5916     /* 60 */
5917     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5918     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5919     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5920     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5921     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5922     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5923     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5924     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5925     /* 68 */
5926     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5927     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5928     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5929     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5930     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5931     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5932     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5933     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5934     /* 70 */
5935     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5936     { MOD_TABLE (MOD_VEX_0F71) },
5937     { MOD_TABLE (MOD_VEX_0F72) },
5938     { MOD_TABLE (MOD_VEX_0F73) },
5939     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5940     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5941     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5942     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5943     /* 78 */
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5949     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5950     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5951     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5952     /* 80 */
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     /* 88 */
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     /* 90 */
5971     { VEX_LEN_TABLE (VEX_LEN_0F90) },
5972     { VEX_LEN_TABLE (VEX_LEN_0F91) },
5973     { VEX_LEN_TABLE (VEX_LEN_0F92) },
5974     { VEX_LEN_TABLE (VEX_LEN_0F93) },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     /* 98 */
5980     { VEX_LEN_TABLE (VEX_LEN_0F98) },
5981     { VEX_LEN_TABLE (VEX_LEN_0F99) },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     /* a0 */
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     /* a8 */
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { REG_TABLE (REG_VEX_0FAE) },
6005     { Bad_Opcode },
6006     /* b0 */
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     /* b8 */
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     /* c0 */
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6028     { Bad_Opcode },
6029     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6030     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6031     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6032     { Bad_Opcode },
6033     /* c8 */
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     /* d0 */
6043     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6044     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6045     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6046     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6047     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6048     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6049     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6050     { MOD_TABLE (MOD_VEX_0FD7) },
6051     /* d8 */
6052     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6053     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6054     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6055     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6056     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6057     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6058     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6059     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6060     /* e0 */
6061     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6062     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6063     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6064     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6065     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6066     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6067     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6068     { MOD_TABLE (MOD_VEX_0FE7) },
6069     /* e8 */
6070     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6071     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6072     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6073     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6074     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6075     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6076     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6077     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6078     /* f0 */
6079     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6080     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6081     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6082     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6083     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6084     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6085     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6086     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6087     /* f8 */
6088     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6089     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6090     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6091     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6092     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6093     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6094     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6095     { Bad_Opcode },
6096   },
6097   /* VEX_0F38 */
6098   {
6099     /* 00 */
6100     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6101     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6102     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6103     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6104     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6105     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6106     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6107     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6108     /* 08 */
6109     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6110     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6111     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6112     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6113     { VEX_W_TABLE (VEX_W_0F380C) },
6114     { VEX_W_TABLE (VEX_W_0F380D) },
6115     { VEX_W_TABLE (VEX_W_0F380E) },
6116     { VEX_W_TABLE (VEX_W_0F380F) },
6117     /* 10 */
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { VEX_W_TABLE (VEX_W_0F3813) },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6125     { "vptest",         { XM, EXx }, PREFIX_DATA },
6126     /* 18 */
6127     { VEX_W_TABLE (VEX_W_0F3818) },
6128     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6129     { MOD_TABLE (MOD_VEX_0F381A) },
6130     { Bad_Opcode },
6131     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6132     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6133     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6134     { Bad_Opcode },
6135     /* 20 */
6136     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6137     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6138     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6139     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6140     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6141     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     /* 28 */
6145     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6146     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6147     { MOD_TABLE (MOD_VEX_0F382A) },
6148     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6149     { MOD_TABLE (MOD_VEX_0F382C) },
6150     { MOD_TABLE (MOD_VEX_0F382D) },
6151     { MOD_TABLE (MOD_VEX_0F382E) },
6152     { MOD_TABLE (MOD_VEX_0F382F) },
6153     /* 30 */
6154     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6155     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6156     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6157     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6158     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6159     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6160     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6161     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6162     /* 38 */
6163     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6164     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6165     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6166     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6167     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6168     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6169     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6170     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6171     /* 40 */
6172     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6173     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6178     { VEX_W_TABLE (VEX_W_0F3846) },
6179     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6180     /* 48 */
6181     { Bad_Opcode },
6182     { X86_64_TABLE (X86_64_VEX_0F3849) },
6183     { Bad_Opcode },
6184     { X86_64_TABLE (X86_64_VEX_0F384B) },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     /* 50 */
6190     { VEX_W_TABLE (VEX_W_0F3850) },
6191     { VEX_W_TABLE (VEX_W_0F3851) },
6192     { VEX_W_TABLE (VEX_W_0F3852) },
6193     { VEX_W_TABLE (VEX_W_0F3853) },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     /* 58 */
6199     { VEX_W_TABLE (VEX_W_0F3858) },
6200     { VEX_W_TABLE (VEX_W_0F3859) },
6201     { MOD_TABLE (MOD_VEX_0F385A) },
6202     { Bad_Opcode },
6203     { X86_64_TABLE (X86_64_VEX_0F385C) },
6204     { Bad_Opcode },
6205     { X86_64_TABLE (X86_64_VEX_0F385E) },
6206     { Bad_Opcode },
6207     /* 60 */
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     /* 68 */
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     /* 70 */
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     /* 78 */
6235     { VEX_W_TABLE (VEX_W_0F3878) },
6236     { VEX_W_TABLE (VEX_W_0F3879) },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     /* 80 */
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     /* 88 */
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { MOD_TABLE (MOD_VEX_0F388C) },
6258     { Bad_Opcode },
6259     { MOD_TABLE (MOD_VEX_0F388E) },
6260     { Bad_Opcode },
6261     /* 90 */
6262     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6263     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6264     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6265     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6269     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6270     /* 98 */
6271     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6272     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6273     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6274     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6275     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6276     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6277     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6278     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6279     /* a0 */
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6287     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6288     /* a8 */
6289     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6290     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6291     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6292     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6293     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6294     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6295     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6296     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6297     /* b0 */
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6305     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6306     /* b8 */
6307     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6308     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6309     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6310     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6311     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6312     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6313     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6314     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6315     /* c0 */
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     /* c8 */
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_W_TABLE (VEX_W_0F38CF) },
6333     /* d0 */
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     /* d8 */
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6347     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6348     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6349     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6350     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6351     /* e0 */
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     /* e8 */
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     /* f0 */
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6373     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6376     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6377     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6378     /* f8 */
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387   },
6388   /* VEX_0F3A */
6389   {
6390     /* 00 */
6391     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6392     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6393     { VEX_W_TABLE (VEX_W_0F3A02) },
6394     { Bad_Opcode },
6395     { VEX_W_TABLE (VEX_W_0F3A04) },
6396     { VEX_W_TABLE (VEX_W_0F3A05) },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6398     { Bad_Opcode },
6399     /* 08 */
6400     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6401     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6402     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6403     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6404     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6405     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6406     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6407     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6408     /* 10 */
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6415     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6416     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6417     /* 18 */
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_W_TABLE (VEX_W_0F3A1D) },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     /* 20 */
6427     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6429     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     /* 28 */
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     /* 30 */
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6448     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     /* 38 */
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6455     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     /* 40 */
6463     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6465     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6466     { Bad_Opcode },
6467     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6468     { Bad_Opcode },
6469     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6470     { Bad_Opcode },
6471     /* 48 */
6472     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6473     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6474     { VEX_W_TABLE (VEX_W_0F3A4A) },
6475     { VEX_W_TABLE (VEX_W_0F3A4B) },
6476     { VEX_W_TABLE (VEX_W_0F3A4C) },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     /* 50 */
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     /* 58 */
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6495     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6496     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6497     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6498     /* 60 */
6499     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     /* 68 */
6508     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6509     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6510     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6511     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6512     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6513     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6514     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6515     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6516     /* 70 */
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     /* 78 */
6526     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6527     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6528     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6529     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6530     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6531     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6532     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6533     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6534     /* 80 */
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     /* 88 */
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     /* 90 */
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     /* 98 */
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     /* a0 */
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     /* a8 */
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     /* b0 */
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     /* b8 */
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     /* c0 */
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     /* c8 */
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { VEX_W_TABLE (VEX_W_0F3ACE) },
6623     { VEX_W_TABLE (VEX_W_0F3ACF) },
6624     /* d0 */
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     /* d8 */
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6642     /* e0 */
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     /* e8 */
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     /* f0 */
6661     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     /* f8 */
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678   },
6679 };
6680
6681 #include "i386-dis-evex.h"
6682
6683 static const struct dis386 vex_len_table[][2] = {
6684   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6685   {
6686     { "%XEvmovlpX",     { XM, Vex, EXq }, 0 },
6687   },
6688
6689   /* VEX_LEN_0F12_P_0_M_1 */
6690   {
6691     { "%XEvmovhlp%XS",  { XM, Vex, EXq }, 0 },
6692   },
6693
6694   /* VEX_LEN_0F13_M_0 */
6695   {
6696     { "%XEvmovlpX",     { EXq, XM }, PREFIX_OPCODE },
6697   },
6698
6699   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6700   {
6701     { "%XEvmovhpX",     { XM, Vex, EXq }, 0 },
6702   },
6703
6704   /* VEX_LEN_0F16_P_0_M_1 */
6705   {
6706     { "%XEvmovlhp%XS",  { XM, Vex, EXq }, 0 },
6707   },
6708
6709   /* VEX_LEN_0F17_M_0 */
6710   {
6711     { "%XEvmovhpX",     { EXq, XM }, PREFIX_OPCODE },
6712   },
6713
6714   /* VEX_LEN_0F41 */
6715   {
6716     { Bad_Opcode },
6717     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6718   },
6719
6720   /* VEX_LEN_0F42 */
6721   {
6722     { Bad_Opcode },
6723     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6724   },
6725
6726   /* VEX_LEN_0F44 */
6727   {
6728     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6729   },
6730
6731   /* VEX_LEN_0F45 */
6732   {
6733     { Bad_Opcode },
6734     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6735   },
6736
6737   /* VEX_LEN_0F46 */
6738   {
6739     { Bad_Opcode },
6740     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6741   },
6742
6743   /* VEX_LEN_0F47 */
6744   {
6745     { Bad_Opcode },
6746     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6747   },
6748
6749   /* VEX_LEN_0F4A */
6750   {
6751     { Bad_Opcode },
6752     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6753   },
6754
6755   /* VEX_LEN_0F4B */
6756   {
6757     { Bad_Opcode },
6758     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6759   },
6760
6761   /* VEX_LEN_0F6E */
6762   {
6763     { "%XEvmovK",       { XMScalar, Edq }, PREFIX_DATA },
6764   },
6765
6766   /* VEX_LEN_0F77 */
6767   {
6768     { "vzeroupper",     { XX }, 0 },
6769     { "vzeroall",       { XX }, 0 },
6770   },
6771
6772   /* VEX_LEN_0F7E_P_1 */
6773   {
6774     { "%XEvmovq",       { XMScalar, EXq }, 0 },
6775   },
6776
6777   /* VEX_LEN_0F7E_P_2 */
6778   {
6779     { "%XEvmovK",       { Edq, XMScalar }, 0 },
6780   },
6781
6782   /* VEX_LEN_0F90 */
6783   {
6784     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6785   },
6786
6787   /* VEX_LEN_0F91 */
6788   {
6789     { MOD_TABLE (MOD_VEX_0F91_L_0) },
6790   },
6791
6792   /* VEX_LEN_0F92 */
6793   {
6794     { MOD_TABLE (MOD_VEX_0F92_L_0) },
6795   },
6796
6797   /* VEX_LEN_0F93 */
6798   {
6799     { MOD_TABLE (MOD_VEX_0F93_L_0) },
6800   },
6801
6802   /* VEX_LEN_0F98 */
6803   {
6804     { MOD_TABLE (MOD_VEX_0F98_L_0) },
6805   },
6806
6807   /* VEX_LEN_0F99 */
6808   {
6809     { MOD_TABLE (MOD_VEX_0F99_L_0) },
6810   },
6811
6812   /* VEX_LEN_0FAE_R_2_M_0 */
6813   {
6814     { "vldmxcsr",       { Md }, 0 },
6815   },
6816
6817   /* VEX_LEN_0FAE_R_3_M_0 */
6818   {
6819     { "vstmxcsr",       { Md }, 0 },
6820   },
6821
6822   /* VEX_LEN_0FC4 */
6823   {
6824     { "%XEvpinsrw",     { XM, Vex, Edw, Ib }, PREFIX_DATA },
6825   },
6826
6827   /* VEX_LEN_0FC5 */
6828   {
6829     { "%XEvpextrw",     { Gd, XS, Ib }, PREFIX_DATA },
6830   },
6831
6832   /* VEX_LEN_0FD6 */
6833   {
6834     { "%XEvmovq",       { EXqS, XMScalar }, PREFIX_DATA },
6835   },
6836
6837   /* VEX_LEN_0FF7 */
6838   {
6839     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6840   },
6841
6842   /* VEX_LEN_0F3816 */
6843   {
6844     { Bad_Opcode },
6845     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6846   },
6847
6848   /* VEX_LEN_0F3819 */
6849   {
6850     { Bad_Opcode },
6851     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6852   },
6853
6854   /* VEX_LEN_0F381A_M_0 */
6855   {
6856     { Bad_Opcode },
6857     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6858   },
6859
6860   /* VEX_LEN_0F3836 */
6861   {
6862     { Bad_Opcode },
6863     { VEX_W_TABLE (VEX_W_0F3836) },
6864   },
6865
6866   /* VEX_LEN_0F3841 */
6867   {
6868     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6869   },
6870
6871    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6872   {
6873     { "ldtilecfg", { M }, 0 },
6874   },
6875
6876   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6877   {
6878     { "tilerelease", { Skip_MODRM }, 0 },
6879   },
6880
6881   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6882   {
6883     { "sttilecfg", { M }, 0 },
6884   },
6885
6886   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6887   {
6888     { "tilezero", { TMM, Skip_MODRM }, 0 },
6889   },
6890
6891   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6892   {
6893     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6894   },
6895   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6896   {
6897     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6898   },
6899
6900   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6901   {
6902     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6903   },
6904
6905   /* VEX_LEN_0F385A_M_0 */
6906   {
6907     { Bad_Opcode },
6908     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6909   },
6910
6911   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6912   {
6913     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6914   },
6915
6916   /* VEX_LEN_0F385C_X86_64_P_3_W_0_M_0 */
6917   {
6918     { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
6919   },
6920
6921   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6922   {
6923     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6924   },
6925
6926   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6927   {
6928     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6929   },
6930
6931   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6932   {
6933     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6934   },
6935
6936   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6937   {
6938     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6939   },
6940
6941   /* VEX_LEN_0F38DB */
6942   {
6943     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
6944   },
6945
6946   /* VEX_LEN_0F38F2 */
6947   {
6948     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6949   },
6950
6951   /* VEX_LEN_0F38F3 */
6952   {
6953     { REG_TABLE(REG_VEX_0F38F3_L_0) },
6954   },
6955
6956   /* VEX_LEN_0F38F5 */
6957   {
6958     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
6959   },
6960
6961   /* VEX_LEN_0F38F6 */
6962   {
6963     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
6964   },
6965
6966   /* VEX_LEN_0F38F7 */
6967   {
6968     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
6969   },
6970
6971   /* VEX_LEN_0F3A00 */
6972   {
6973     { Bad_Opcode },
6974     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6975   },
6976
6977   /* VEX_LEN_0F3A01 */
6978   {
6979     { Bad_Opcode },
6980     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6981   },
6982
6983   /* VEX_LEN_0F3A06 */
6984   {
6985     { Bad_Opcode },
6986     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6987   },
6988
6989   /* VEX_LEN_0F3A14 */
6990   {
6991     { "%XEvpextrb",     { Edb, XM, Ib }, PREFIX_DATA },
6992   },
6993
6994   /* VEX_LEN_0F3A15 */
6995   {
6996     { "%XEvpextrw",     { Edw, XM, Ib }, PREFIX_DATA },
6997   },
6998
6999   /* VEX_LEN_0F3A16  */
7000   {
7001     { "%XEvpextrK",     { Edq, XM, Ib }, PREFIX_DATA },
7002   },
7003
7004   /* VEX_LEN_0F3A17 */
7005   {
7006     { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7007   },
7008
7009   /* VEX_LEN_0F3A18 */
7010   {
7011     { Bad_Opcode },
7012     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7013   },
7014
7015   /* VEX_LEN_0F3A19 */
7016   {
7017     { Bad_Opcode },
7018     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7019   },
7020
7021   /* VEX_LEN_0F3A20 */
7022   {
7023     { "%XEvpinsrb",     { XM, Vex, Edb, Ib }, PREFIX_DATA },
7024   },
7025
7026   /* VEX_LEN_0F3A21 */
7027   {
7028     { "%XEvinsertps",   { XM, Vex, EXd, Ib }, PREFIX_DATA },
7029   },
7030
7031   /* VEX_LEN_0F3A22 */
7032   {
7033     { "%XEvpinsrK",     { XM, Vex, Edq, Ib }, PREFIX_DATA },
7034   },
7035
7036   /* VEX_LEN_0F3A30 */
7037   {
7038     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7039   },
7040
7041   /* VEX_LEN_0F3A31 */
7042   {
7043     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7044   },
7045
7046   /* VEX_LEN_0F3A32 */
7047   {
7048     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7049   },
7050
7051   /* VEX_LEN_0F3A33 */
7052   {
7053     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7054   },
7055
7056   /* VEX_LEN_0F3A38 */
7057   {
7058     { Bad_Opcode },
7059     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7060   },
7061
7062   /* VEX_LEN_0F3A39 */
7063   {
7064     { Bad_Opcode },
7065     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7066   },
7067
7068   /* VEX_LEN_0F3A41 */
7069   {
7070     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7071   },
7072
7073   /* VEX_LEN_0F3A46 */
7074   {
7075     { Bad_Opcode },
7076     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7077   },
7078
7079   /* VEX_LEN_0F3A60 */
7080   {
7081     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7082   },
7083
7084   /* VEX_LEN_0F3A61 */
7085   {
7086     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7087   },
7088
7089   /* VEX_LEN_0F3A62 */
7090   {
7091     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7092   },
7093
7094   /* VEX_LEN_0F3A63 */
7095   {
7096     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7097   },
7098
7099   /* VEX_LEN_0F3ADF */
7100   {
7101     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7102   },
7103
7104   /* VEX_LEN_0F3AF0 */
7105   {
7106     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7107   },
7108
7109   /* VEX_LEN_0FXOP_08_85 */
7110   {
7111     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7112   },
7113
7114   /* VEX_LEN_0FXOP_08_86 */
7115   {
7116     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7117   },
7118
7119   /* VEX_LEN_0FXOP_08_87 */
7120   {
7121     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7122   },
7123
7124   /* VEX_LEN_0FXOP_08_8E */
7125   {
7126     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7127   },
7128
7129   /* VEX_LEN_0FXOP_08_8F */
7130   {
7131     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7132   },
7133
7134   /* VEX_LEN_0FXOP_08_95 */
7135   {
7136     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7137   },
7138
7139   /* VEX_LEN_0FXOP_08_96 */
7140   {
7141     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7142   },
7143
7144   /* VEX_LEN_0FXOP_08_97 */
7145   {
7146     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7147   },
7148
7149   /* VEX_LEN_0FXOP_08_9E */
7150   {
7151     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7152   },
7153
7154   /* VEX_LEN_0FXOP_08_9F */
7155   {
7156     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7157   },
7158
7159   /* VEX_LEN_0FXOP_08_A3 */
7160   {
7161     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7162   },
7163
7164   /* VEX_LEN_0FXOP_08_A6 */
7165   {
7166     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7167   },
7168
7169   /* VEX_LEN_0FXOP_08_B6 */
7170   {
7171     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7172   },
7173
7174   /* VEX_LEN_0FXOP_08_C0 */
7175   {
7176     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7177   },
7178
7179   /* VEX_LEN_0FXOP_08_C1 */
7180   {
7181     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7182   },
7183
7184   /* VEX_LEN_0FXOP_08_C2 */
7185   {
7186     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7187   },
7188
7189   /* VEX_LEN_0FXOP_08_C3 */
7190   {
7191     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7192   },
7193
7194   /* VEX_LEN_0FXOP_08_CC */
7195   {
7196     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7197   },
7198
7199   /* VEX_LEN_0FXOP_08_CD */
7200   {
7201     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7202   },
7203
7204   /* VEX_LEN_0FXOP_08_CE */
7205   {
7206     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7207   },
7208
7209   /* VEX_LEN_0FXOP_08_CF */
7210   {
7211     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7212   },
7213
7214   /* VEX_LEN_0FXOP_08_EC */
7215   {
7216     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7217   },
7218
7219   /* VEX_LEN_0FXOP_08_ED */
7220   {
7221     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7222   },
7223
7224   /* VEX_LEN_0FXOP_08_EE */
7225   {
7226     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7227   },
7228
7229   /* VEX_LEN_0FXOP_08_EF */
7230   {
7231     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7232   },
7233
7234   /* VEX_LEN_0FXOP_09_01 */
7235   {
7236     { REG_TABLE (REG_XOP_09_01_L_0) },
7237   },
7238
7239   /* VEX_LEN_0FXOP_09_02 */
7240   {
7241     { REG_TABLE (REG_XOP_09_02_L_0) },
7242   },
7243
7244   /* VEX_LEN_0FXOP_09_12_M_1 */
7245   {
7246     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7247   },
7248
7249   /* VEX_LEN_0FXOP_09_82_W_0 */
7250   {
7251     { "vfrczss",        { XM, EXd }, 0 },
7252   },
7253
7254   /* VEX_LEN_0FXOP_09_83_W_0 */
7255   {
7256     { "vfrczsd",        { XM, EXq }, 0 },
7257   },
7258
7259   /* VEX_LEN_0FXOP_09_90 */
7260   {
7261     { "vprotb",         { XM, EXx, VexW }, 0 },
7262   },
7263
7264   /* VEX_LEN_0FXOP_09_91 */
7265   {
7266     { "vprotw",         { XM, EXx, VexW }, 0 },
7267   },
7268
7269   /* VEX_LEN_0FXOP_09_92 */
7270   {
7271     { "vprotd",         { XM, EXx, VexW }, 0 },
7272   },
7273
7274   /* VEX_LEN_0FXOP_09_93 */
7275   {
7276     { "vprotq",         { XM, EXx, VexW }, 0 },
7277   },
7278
7279   /* VEX_LEN_0FXOP_09_94 */
7280   {
7281     { "vpshlb",         { XM, EXx, VexW }, 0 },
7282   },
7283
7284   /* VEX_LEN_0FXOP_09_95 */
7285   {
7286     { "vpshlw",         { XM, EXx, VexW }, 0 },
7287   },
7288
7289   /* VEX_LEN_0FXOP_09_96 */
7290   {
7291     { "vpshld",         { XM, EXx, VexW }, 0 },
7292   },
7293
7294   /* VEX_LEN_0FXOP_09_97 */
7295   {
7296     { "vpshlq",         { XM, EXx, VexW }, 0 },
7297   },
7298
7299   /* VEX_LEN_0FXOP_09_98 */
7300   {
7301     { "vpshab",         { XM, EXx, VexW }, 0 },
7302   },
7303
7304   /* VEX_LEN_0FXOP_09_99 */
7305   {
7306     { "vpshaw",         { XM, EXx, VexW }, 0 },
7307   },
7308
7309   /* VEX_LEN_0FXOP_09_9A */
7310   {
7311     { "vpshad",         { XM, EXx, VexW }, 0 },
7312   },
7313
7314   /* VEX_LEN_0FXOP_09_9B */
7315   {
7316     { "vpshaq",         { XM, EXx, VexW }, 0 },
7317   },
7318
7319   /* VEX_LEN_0FXOP_09_C1 */
7320   {
7321     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7322   },
7323
7324   /* VEX_LEN_0FXOP_09_C2 */
7325   {
7326     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7327   },
7328
7329   /* VEX_LEN_0FXOP_09_C3 */
7330   {
7331     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7332   },
7333
7334   /* VEX_LEN_0FXOP_09_C6 */
7335   {
7336     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7337   },
7338
7339   /* VEX_LEN_0FXOP_09_C7 */
7340   {
7341     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7342   },
7343
7344   /* VEX_LEN_0FXOP_09_CB */
7345   {
7346     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7347   },
7348
7349   /* VEX_LEN_0FXOP_09_D1 */
7350   {
7351     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7352   },
7353
7354   /* VEX_LEN_0FXOP_09_D2 */
7355   {
7356     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7357   },
7358
7359   /* VEX_LEN_0FXOP_09_D3 */
7360   {
7361     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7362   },
7363
7364   /* VEX_LEN_0FXOP_09_D6 */
7365   {
7366     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7367   },
7368
7369   /* VEX_LEN_0FXOP_09_D7 */
7370   {
7371     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7372   },
7373
7374   /* VEX_LEN_0FXOP_09_DB */
7375   {
7376     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7377   },
7378
7379   /* VEX_LEN_0FXOP_09_E1 */
7380   {
7381     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7382   },
7383
7384   /* VEX_LEN_0FXOP_09_E2 */
7385   {
7386     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7387   },
7388
7389   /* VEX_LEN_0FXOP_09_E3 */
7390   {
7391     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7392   },
7393
7394   /* VEX_LEN_0FXOP_0A_12 */
7395   {
7396     { REG_TABLE (REG_XOP_0A_12_L_0) },
7397   },
7398 };
7399
7400 #include "i386-dis-evex-len.h"
7401
7402 static const struct dis386 vex_w_table[][2] = {
7403   {
7404     /* VEX_W_0F41_L_1_M_1 */
7405     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7406     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7407   },
7408   {
7409     /* VEX_W_0F42_L_1_M_1 */
7410     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7411     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7412   },
7413   {
7414     /* VEX_W_0F44_L_0_M_1 */
7415     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7416     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7417   },
7418   {
7419     /* VEX_W_0F45_L_1_M_1 */
7420     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7421     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7422   },
7423   {
7424     /* VEX_W_0F46_L_1_M_1 */
7425     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7426     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7427   },
7428   {
7429     /* VEX_W_0F47_L_1_M_1 */
7430     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7431     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7432   },
7433   {
7434     /* VEX_W_0F4A_L_1_M_1 */
7435     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7436     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7437   },
7438   {
7439     /* VEX_W_0F4B_L_1_M_1 */
7440     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7441     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7442   },
7443   {
7444     /* VEX_W_0F90_L_0 */
7445     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7446     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7447   },
7448   {
7449     /* VEX_W_0F91_L_0_M_0 */
7450     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7451     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7452   },
7453   {
7454     /* VEX_W_0F92_L_0_M_1 */
7455     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7456     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7457   },
7458   {
7459     /* VEX_W_0F93_L_0_M_1 */
7460     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7461     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7462   },
7463   {
7464     /* VEX_W_0F98_L_0_M_1 */
7465     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7466     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7467   },
7468   {
7469     /* VEX_W_0F99_L_0_M_1 */
7470     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7471     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7472   },
7473   {
7474     /* VEX_W_0F380C  */
7475     { "%XEvpermilps",   { XM, Vex, EXx }, PREFIX_DATA },
7476   },
7477   {
7478     /* VEX_W_0F380D  */
7479     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7480   },
7481   {
7482     /* VEX_W_0F380E  */
7483     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7484   },
7485   {
7486     /* VEX_W_0F380F  */
7487     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7488   },
7489   {
7490     /* VEX_W_0F3813 */
7491     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7492   },
7493   {
7494     /* VEX_W_0F3816_L_1  */
7495     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7496   },
7497   {
7498     /* VEX_W_0F3818 */
7499     { "%XEvbroadcastss",        { XM, EXd }, PREFIX_DATA },
7500   },
7501   {
7502     /* VEX_W_0F3819_L_1 */
7503     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7504   },
7505   {
7506     /* VEX_W_0F381A_M_0_L_1 */
7507     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7508   },
7509   {
7510     /* VEX_W_0F382C_M_0 */
7511     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7512   },
7513   {
7514     /* VEX_W_0F382D_M_0 */
7515     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7516   },
7517   {
7518     /* VEX_W_0F382E_M_0 */
7519     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7520   },
7521   {
7522     /* VEX_W_0F382F_M_0 */
7523     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7524   },
7525   {
7526     /* VEX_W_0F3836  */
7527     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7528   },
7529   {
7530     /* VEX_W_0F3846 */
7531     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7532   },
7533   {
7534     /* VEX_W_0F3849_X86_64_P_0 */
7535     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7536   },
7537   {
7538     /* VEX_W_0F3849_X86_64_P_2 */
7539     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7540   },
7541   {
7542     /* VEX_W_0F3849_X86_64_P_3 */
7543     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7544   },
7545   {
7546     /* VEX_W_0F384B_X86_64_P_1 */
7547     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7548   },
7549   {
7550     /* VEX_W_0F384B_X86_64_P_2 */
7551     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7552   },
7553   {
7554     /* VEX_W_0F384B_X86_64_P_3 */
7555     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7556   },
7557   {
7558     /* VEX_W_0F3850 */
7559     { "%XVvpdpbusd",    { XM, Vex, EXx }, PREFIX_DATA },
7560   },
7561   {
7562     /* VEX_W_0F3851 */
7563     { "%XVvpdpbusds",   { XM, Vex, EXx }, PREFIX_DATA },
7564   },
7565   {
7566     /* VEX_W_0F3852 */
7567     { "%XVvpdpwssd",    { XM, Vex, EXx }, PREFIX_DATA },
7568   },
7569   {
7570     /* VEX_W_0F3853 */
7571     { "%XVvpdpwssds",   { XM, Vex, EXx }, PREFIX_DATA },
7572   },
7573   {
7574     /* VEX_W_0F3858 */
7575     { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7576   },
7577   {
7578     /* VEX_W_0F3859 */
7579     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7580   },
7581   {
7582     /* VEX_W_0F385A_M_0_L_0 */
7583     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7584   },
7585   {
7586     /* VEX_W_0F385C_X86_64_P_1 */
7587     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7588   },
7589   {
7590     /* VEX_W_0F385C_X86_64_P_3 */
7591     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_3_W_0) },
7592   },
7593   {
7594     /* VEX_W_0F385E_X86_64_P_0 */
7595     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7596   },
7597   {
7598     /* VEX_W_0F385E_X86_64_P_1 */
7599     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7600   },
7601   {
7602     /* VEX_W_0F385E_X86_64_P_2 */
7603     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7604   },
7605   {
7606     /* VEX_W_0F385E_X86_64_P_3 */
7607     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7608   },
7609   {
7610     /* VEX_W_0F3878 */
7611     { "%XEvpbroadcastb",        { XM, EXb }, PREFIX_DATA },
7612   },
7613   {
7614     /* VEX_W_0F3879 */
7615     { "%XEvpbroadcastw",        { XM, EXw }, PREFIX_DATA },
7616   },
7617   {
7618     /* VEX_W_0F38CF */
7619     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7620   },
7621   {
7622     /* VEX_W_0F3A00_L_1 */
7623     { Bad_Opcode },
7624     { "%XEvpermq",              { XM, EXx, Ib }, PREFIX_DATA },
7625   },
7626   {
7627     /* VEX_W_0F3A01_L_1 */
7628     { Bad_Opcode },
7629     { "%XEvpermpd",     { XM, EXx, Ib }, PREFIX_DATA },
7630   },
7631   {
7632     /* VEX_W_0F3A02 */
7633     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7634   },
7635   {
7636     /* VEX_W_0F3A04 */
7637     { "%XEvpermilps",   { XM, EXx, Ib }, PREFIX_DATA },
7638   },
7639   {
7640     /* VEX_W_0F3A05 */
7641     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7642   },
7643   {
7644     /* VEX_W_0F3A06_L_1 */
7645     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7646   },
7647   {
7648     /* VEX_W_0F3A18_L_1 */
7649     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7650   },
7651   {
7652     /* VEX_W_0F3A19_L_1 */
7653     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7654   },
7655   {
7656     /* VEX_W_0F3A1D */
7657     { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7658   },
7659   {
7660     /* VEX_W_0F3A38_L_1 */
7661     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7662   },
7663   {
7664     /* VEX_W_0F3A39_L_1 */
7665     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7666   },
7667   {
7668     /* VEX_W_0F3A46_L_1 */
7669     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7670   },
7671   {
7672     /* VEX_W_0F3A4A */
7673     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7674   },
7675   {
7676     /* VEX_W_0F3A4B */
7677     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7678   },
7679   {
7680     /* VEX_W_0F3A4C */
7681     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7682   },
7683   {
7684     /* VEX_W_0F3ACE */
7685     { Bad_Opcode },
7686     { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7687   },
7688   {
7689     /* VEX_W_0F3ACF */
7690     { Bad_Opcode },
7691     { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7692   },
7693   /* VEX_W_0FXOP_08_85_L_0 */
7694   {
7695     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7696   },
7697   /* VEX_W_0FXOP_08_86_L_0 */
7698   {
7699     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7700   },
7701   /* VEX_W_0FXOP_08_87_L_0 */
7702   {
7703     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7704   },
7705   /* VEX_W_0FXOP_08_8E_L_0 */
7706   {
7707     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7708   },
7709   /* VEX_W_0FXOP_08_8F_L_0 */
7710   {
7711     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7712   },
7713   /* VEX_W_0FXOP_08_95_L_0 */
7714   {
7715     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7716   },
7717   /* VEX_W_0FXOP_08_96_L_0 */
7718   {
7719     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7720   },
7721   /* VEX_W_0FXOP_08_97_L_0 */
7722   {
7723     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7724   },
7725   /* VEX_W_0FXOP_08_9E_L_0 */
7726   {
7727     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7728   },
7729   /* VEX_W_0FXOP_08_9F_L_0 */
7730   {
7731     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7732   },
7733   /* VEX_W_0FXOP_08_A6_L_0 */
7734   {
7735     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7736   },
7737   /* VEX_W_0FXOP_08_B6_L_0 */
7738   {
7739     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7740   },
7741   /* VEX_W_0FXOP_08_C0_L_0 */
7742   {
7743     { "vprotb",         { XM, EXx, Ib }, 0 },
7744   },
7745   /* VEX_W_0FXOP_08_C1_L_0 */
7746   {
7747     { "vprotw",         { XM, EXx, Ib }, 0 },
7748   },
7749   /* VEX_W_0FXOP_08_C2_L_0 */
7750   {
7751     { "vprotd",         { XM, EXx, Ib }, 0 },
7752   },
7753   /* VEX_W_0FXOP_08_C3_L_0 */
7754   {
7755     { "vprotq",         { XM, EXx, Ib }, 0 },
7756   },
7757   /* VEX_W_0FXOP_08_CC_L_0 */
7758   {
7759      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7760   },
7761   /* VEX_W_0FXOP_08_CD_L_0 */
7762   {
7763      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7764   },
7765   /* VEX_W_0FXOP_08_CE_L_0 */
7766   {
7767      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7768   },
7769   /* VEX_W_0FXOP_08_CF_L_0 */
7770   {
7771      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7772   },
7773   /* VEX_W_0FXOP_08_EC_L_0 */
7774   {
7775      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7776   },
7777   /* VEX_W_0FXOP_08_ED_L_0 */
7778   {
7779      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7780   },
7781   /* VEX_W_0FXOP_08_EE_L_0 */
7782   {
7783      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7784   },
7785   /* VEX_W_0FXOP_08_EF_L_0 */
7786   {
7787      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7788   },
7789   /* VEX_W_0FXOP_09_80 */
7790   {
7791     { "vfrczps",        { XM, EXx }, 0 },
7792   },
7793   /* VEX_W_0FXOP_09_81 */
7794   {
7795     { "vfrczpd",        { XM, EXx }, 0 },
7796   },
7797   /* VEX_W_0FXOP_09_82 */
7798   {
7799     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7800   },
7801   /* VEX_W_0FXOP_09_83 */
7802   {
7803     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7804   },
7805   /* VEX_W_0FXOP_09_C1_L_0 */
7806   {
7807     { "vphaddbw",       { XM, EXxmm }, 0 },
7808   },
7809   /* VEX_W_0FXOP_09_C2_L_0 */
7810   {
7811     { "vphaddbd",       { XM, EXxmm }, 0 },
7812   },
7813   /* VEX_W_0FXOP_09_C3_L_0 */
7814   {
7815     { "vphaddbq",       { XM, EXxmm }, 0 },
7816   },
7817   /* VEX_W_0FXOP_09_C6_L_0 */
7818   {
7819     { "vphaddwd",       { XM, EXxmm }, 0 },
7820   },
7821   /* VEX_W_0FXOP_09_C7_L_0 */
7822   {
7823     { "vphaddwq",       { XM, EXxmm }, 0 },
7824   },
7825   /* VEX_W_0FXOP_09_CB_L_0 */
7826   {
7827     { "vphadddq",       { XM, EXxmm }, 0 },
7828   },
7829   /* VEX_W_0FXOP_09_D1_L_0 */
7830   {
7831     { "vphaddubw",      { XM, EXxmm }, 0 },
7832   },
7833   /* VEX_W_0FXOP_09_D2_L_0 */
7834   {
7835     { "vphaddubd",      { XM, EXxmm }, 0 },
7836   },
7837   /* VEX_W_0FXOP_09_D3_L_0 */
7838   {
7839     { "vphaddubq",      { XM, EXxmm }, 0 },
7840   },
7841   /* VEX_W_0FXOP_09_D6_L_0 */
7842   {
7843     { "vphadduwd",      { XM, EXxmm }, 0 },
7844   },
7845   /* VEX_W_0FXOP_09_D7_L_0 */
7846   {
7847     { "vphadduwq",      { XM, EXxmm }, 0 },
7848   },
7849   /* VEX_W_0FXOP_09_DB_L_0 */
7850   {
7851     { "vphaddudq",      { XM, EXxmm }, 0 },
7852   },
7853   /* VEX_W_0FXOP_09_E1_L_0 */
7854   {
7855     { "vphsubbw",       { XM, EXxmm }, 0 },
7856   },
7857   /* VEX_W_0FXOP_09_E2_L_0 */
7858   {
7859     { "vphsubwd",       { XM, EXxmm }, 0 },
7860   },
7861   /* VEX_W_0FXOP_09_E3_L_0 */
7862   {
7863     { "vphsubdq",       { XM, EXxmm }, 0 },
7864   },
7865
7866 #include "i386-dis-evex-w.h"
7867 };
7868
7869 static const struct dis386 mod_table[][2] = {
7870   {
7871     /* MOD_62_32BIT */
7872     { "bound{S|}",      { Gv, Ma }, 0 },
7873     { EVEX_TABLE (EVEX_0F) },
7874   },
7875   {
7876     /* MOD_8D */
7877     { "leaS",           { Gv, M }, 0 },
7878   },
7879   {
7880     /* MOD_C4_32BIT */
7881     { "lesS",           { Gv, Mp }, 0 },
7882     { VEX_C4_TABLE (VEX_0F) },
7883   },
7884   {
7885     /* MOD_C5_32BIT */
7886     { "ldsS",           { Gv, Mp }, 0 },
7887     { VEX_C5_TABLE (VEX_0F) },
7888   },
7889   {
7890     /* MOD_C6_REG_7 */
7891     { Bad_Opcode },
7892     { RM_TABLE (RM_C6_REG_7) },
7893   },
7894   {
7895     /* MOD_C7_REG_7 */
7896     { Bad_Opcode },
7897     { RM_TABLE (RM_C7_REG_7) },
7898   },
7899   {
7900     /* MOD_FF_REG_3 */
7901     { "{l|}call^", { indirEp }, 0 },
7902   },
7903   {
7904     /* MOD_FF_REG_5 */
7905     { "{l|}jmp^", { indirEp }, 0 },
7906   },
7907   {
7908     /* MOD_0F01_REG_0 */
7909     { X86_64_TABLE (X86_64_0F01_REG_0) },
7910     { RM_TABLE (RM_0F01_REG_0) },
7911   },
7912   {
7913     /* MOD_0F01_REG_1 */
7914     { X86_64_TABLE (X86_64_0F01_REG_1) },
7915     { RM_TABLE (RM_0F01_REG_1) },
7916   },
7917   {
7918     /* MOD_0F01_REG_2 */
7919     { X86_64_TABLE (X86_64_0F01_REG_2) },
7920     { RM_TABLE (RM_0F01_REG_2) },
7921   },
7922   {
7923     /* MOD_0F01_REG_3 */
7924     { X86_64_TABLE (X86_64_0F01_REG_3) },
7925     { RM_TABLE (RM_0F01_REG_3) },
7926   },
7927   {
7928     /* MOD_0F01_REG_5 */
7929     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7930     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7931   },
7932   {
7933     /* MOD_0F01_REG_7 */
7934     { "invlpg",         { Mb }, 0 },
7935     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7936   },
7937   {
7938     /* MOD_0F12_PREFIX_0 */
7939     { "movlpX",         { XM, EXq }, 0 },
7940     { "movhlps",        { XM, EXq }, 0 },
7941   },
7942   {
7943     /* MOD_0F12_PREFIX_2 */
7944     { "movlpX", { XM, EXq }, 0 },
7945   },
7946   {
7947     /* MOD_0F13 */
7948     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
7949   },
7950   {
7951     /* MOD_0F16_PREFIX_0 */
7952     { "movhpX",         { XM, EXq }, 0 },
7953     { "movlhps",        { XM, EXq }, 0 },
7954   },
7955   {
7956     /* MOD_0F16_PREFIX_2 */
7957     { "movhpX", { XM, EXq }, 0 },
7958   },
7959   {
7960     /* MOD_0F17 */
7961     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
7962   },
7963   {
7964     /* MOD_0F18_REG_0 */
7965     { "prefetchnta",    { Mb }, 0 },
7966     { "nopQ",           { Ev }, 0 },
7967   },
7968   {
7969     /* MOD_0F18_REG_1 */
7970     { "prefetcht0",     { Mb }, 0 },
7971     { "nopQ",           { Ev }, 0 },
7972   },
7973   {
7974     /* MOD_0F18_REG_2 */
7975     { "prefetcht1",     { Mb }, 0 },
7976     { "nopQ",           { Ev }, 0 },
7977   },
7978   {
7979     /* MOD_0F18_REG_3 */
7980     { "prefetcht2",     { Mb }, 0 },
7981     { "nopQ",           { Ev }, 0 },
7982   },
7983   {
7984     /* MOD_0F1A_PREFIX_0 */
7985     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
7986     { "nopQ",           { Ev }, 0 },
7987   },
7988   {
7989     /* MOD_0F1B_PREFIX_0 */
7990     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
7991     { "nopQ",           { Ev }, 0 },
7992   },
7993   {
7994     /* MOD_0F1B_PREFIX_1 */
7995     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
7996     { "nopQ",           { Ev }, PREFIX_IGNORED },
7997   },
7998   {
7999     /* MOD_0F1C_PREFIX_0 */
8000     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8001     { "nopQ",           { Ev }, 0 },
8002   },
8003   {
8004     /* MOD_0F1E_PREFIX_1 */
8005     { "nopQ",           { Ev }, PREFIX_IGNORED },
8006     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8007   },
8008   {
8009     /* MOD_0F2B_PREFIX_0 */
8010     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8011   },
8012   {
8013     /* MOD_0F2B_PREFIX_1 */
8014     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8015   },
8016   {
8017     /* MOD_0F2B_PREFIX_2 */
8018     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8019   },
8020   {
8021     /* MOD_0F2B_PREFIX_3 */
8022     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8023   },
8024   {
8025     /* MOD_0F50 */
8026     { Bad_Opcode },
8027     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8028   },
8029   {
8030     /* MOD_0F71 */
8031     { Bad_Opcode },
8032     { REG_TABLE (REG_0F71_MOD_0) },
8033   },
8034   {
8035     /* MOD_0F72 */
8036     { Bad_Opcode },
8037     { REG_TABLE (REG_0F72_MOD_0) },
8038   },
8039   {
8040     /* MOD_0F73 */
8041     { Bad_Opcode },
8042     { REG_TABLE (REG_0F73_MOD_0) },
8043   },
8044   {
8045     /* MOD_0FAE_REG_0 */
8046     { "fxsave",         { FXSAVE }, 0 },
8047     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8048   },
8049   {
8050     /* MOD_0FAE_REG_1 */
8051     { "fxrstor",        { FXSAVE }, 0 },
8052     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8053   },
8054   {
8055     /* MOD_0FAE_REG_2 */
8056     { "ldmxcsr",        { Md }, 0 },
8057     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8058   },
8059   {
8060     /* MOD_0FAE_REG_3 */
8061     { "stmxcsr",        { Md }, 0 },
8062     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8063   },
8064   {
8065     /* MOD_0FAE_REG_4 */
8066     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8067     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8068   },
8069   {
8070     /* MOD_0FAE_REG_5 */
8071     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8072     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8073   },
8074   {
8075     /* MOD_0FAE_REG_6 */
8076     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8077     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8078   },
8079   {
8080     /* MOD_0FAE_REG_7 */
8081     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8082     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8083   },
8084   {
8085     /* MOD_0FB2 */
8086     { "lssS",           { Gv, Mp }, 0 },
8087   },
8088   {
8089     /* MOD_0FB4 */
8090     { "lfsS",           { Gv, Mp }, 0 },
8091   },
8092   {
8093     /* MOD_0FB5 */
8094     { "lgsS",           { Gv, Mp }, 0 },
8095   },
8096   {
8097     /* MOD_0FC3 */
8098     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8099   },
8100   {
8101     /* MOD_0FC7_REG_3 */
8102     { "xrstors",        { FXSAVE }, 0 },
8103   },
8104   {
8105     /* MOD_0FC7_REG_4 */
8106     { "xsavec",         { FXSAVE }, 0 },
8107   },
8108   {
8109     /* MOD_0FC7_REG_5 */
8110     { "xsaves",         { FXSAVE }, 0 },
8111   },
8112   {
8113     /* MOD_0FC7_REG_6 */
8114     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8115     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8116   },
8117   {
8118     /* MOD_0FC7_REG_7 */
8119     { "vmptrst",        { Mq }, 0 },
8120     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8121   },
8122   {
8123     /* MOD_0FD7 */
8124     { Bad_Opcode },
8125     { "pmovmskb",       { Gdq, MS }, 0 },
8126   },
8127   {
8128     /* MOD_0FE7_PREFIX_2 */
8129     { "movntdq",        { Mx, XM }, 0 },
8130   },
8131   {
8132     /* MOD_0FF0_PREFIX_3 */
8133     { "lddqu",          { XM, M }, 0 },
8134   },
8135   {
8136     /* MOD_0F382A */
8137     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8138   },
8139   {
8140     /* MOD_0F38DC_PREFIX_1 */
8141     { "aesenc128kl",    { XM, M }, 0 },
8142     { "loadiwkey",      { XM, EXx }, 0 },
8143   },
8144   {
8145     /* MOD_0F38DD_PREFIX_1 */
8146     { "aesdec128kl",    { XM, M }, 0 },
8147   },
8148   {
8149     /* MOD_0F38DE_PREFIX_1 */
8150     { "aesenc256kl",    { XM, M }, 0 },
8151   },
8152   {
8153     /* MOD_0F38DF_PREFIX_1 */
8154     { "aesdec256kl",    { XM, M }, 0 },
8155   },
8156   {
8157     /* MOD_0F38F5 */
8158     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8159   },
8160   {
8161     /* MOD_0F38F6_PREFIX_0 */
8162     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8163   },
8164   {
8165     /* MOD_0F38F8_PREFIX_1 */
8166     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8167   },
8168   {
8169     /* MOD_0F38F8_PREFIX_2 */
8170     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8171   },
8172   {
8173     /* MOD_0F38F8_PREFIX_3 */
8174     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8175   },
8176   {
8177     /* MOD_0F38F9 */
8178     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8179   },
8180   {
8181     /* MOD_0F38FA_PREFIX_1 */
8182     { Bad_Opcode },
8183     { "encodekey128", { Gd, Ed }, 0 },
8184   },
8185   {
8186     /* MOD_0F38FB_PREFIX_1 */
8187     { Bad_Opcode },
8188     { "encodekey256", { Gd, Ed }, 0 },
8189   },
8190   {
8191     /* MOD_0F3A0F_PREFIX_1 */
8192     { Bad_Opcode },
8193     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8194   },
8195   {
8196     /* MOD_VEX_0F12_PREFIX_0 */
8197     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8198     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8199   },
8200   {
8201     /* MOD_VEX_0F12_PREFIX_2 */
8202     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8203   },
8204   {
8205     /* MOD_VEX_0F13 */
8206     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8207   },
8208   {
8209     /* MOD_VEX_0F16_PREFIX_0 */
8210     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8211     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8212   },
8213   {
8214     /* MOD_VEX_0F16_PREFIX_2 */
8215     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8216   },
8217   {
8218     /* MOD_VEX_0F17 */
8219     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8220   },
8221   {
8222     /* MOD_VEX_0F2B */
8223     { "%XEvmovntpX",    { Mx, XM }, PREFIX_OPCODE },
8224   },
8225   {
8226     /* MOD_VEX_0F41_L_1 */
8227     { Bad_Opcode },
8228     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8229   },
8230   {
8231     /* MOD_VEX_0F42_L_1 */
8232     { Bad_Opcode },
8233     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8234   },
8235   {
8236     /* MOD_VEX_0F44_L_0 */
8237     { Bad_Opcode },
8238     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8239   },
8240   {
8241     /* MOD_VEX_0F45_L_1 */
8242     { Bad_Opcode },
8243     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8244   },
8245   {
8246     /* MOD_VEX_0F46_L_1 */
8247     { Bad_Opcode },
8248     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8249   },
8250   {
8251     /* MOD_VEX_0F47_L_1 */
8252     { Bad_Opcode },
8253     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8254   },
8255   {
8256     /* MOD_VEX_0F4A_L_1 */
8257     { Bad_Opcode },
8258     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8259   },
8260   {
8261     /* MOD_VEX_0F4B_L_1 */
8262     { Bad_Opcode },
8263     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8264   },
8265   {
8266     /* MOD_VEX_0F50 */
8267     { Bad_Opcode },
8268     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8269   },
8270   {
8271     /* MOD_VEX_0F71 */
8272     { Bad_Opcode },
8273     { REG_TABLE (REG_VEX_0F71_M_0) },
8274   },
8275   {
8276     /* MOD_VEX_0F72 */
8277     { Bad_Opcode },
8278     { REG_TABLE (REG_VEX_0F72_M_0) },
8279   },
8280   {
8281     /* MOD_VEX_0F73 */
8282     { Bad_Opcode },
8283     { REG_TABLE (REG_VEX_0F73_M_0) },
8284   },
8285   {
8286     /* MOD_VEX_0F91_L_0 */
8287     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8288   },
8289   {
8290     /* MOD_VEX_0F92_L_0 */
8291     { Bad_Opcode },
8292     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8293   },
8294   {
8295     /* MOD_VEX_0F93_L_0 */
8296     { Bad_Opcode },
8297     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8298   },
8299   {
8300     /* MOD_VEX_0F98_L_0 */
8301     { Bad_Opcode },
8302     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8303   },
8304   {
8305     /* MOD_VEX_0F99_L_0 */
8306     { Bad_Opcode },
8307     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8308   },
8309   {
8310     /* MOD_VEX_0FAE_REG_2 */
8311     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8312   },
8313   {
8314     /* MOD_VEX_0FAE_REG_3 */
8315     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8316   },
8317   {
8318     /* MOD_VEX_0FD7 */
8319     { Bad_Opcode },
8320     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8321   },
8322   {
8323     /* MOD_VEX_0FE7 */
8324     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8325   },
8326   {
8327     /* MOD_VEX_0FF0_PREFIX_3 */
8328     { "vlddqu",         { XM, M }, 0 },
8329   },
8330   {
8331     /* MOD_VEX_0F381A */
8332     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8333   },
8334   {
8335     /* MOD_VEX_0F382A */
8336     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8337   },
8338   {
8339     /* MOD_VEX_0F382C */
8340     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8341   },
8342   {
8343     /* MOD_VEX_0F382D */
8344     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8345   },
8346   {
8347     /* MOD_VEX_0F382E */
8348     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8349   },
8350   {
8351     /* MOD_VEX_0F382F */
8352     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8353   },
8354   {
8355     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8356     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8357     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8358   },
8359   {
8360     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8361     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8362   },
8363   {
8364     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8365     { Bad_Opcode },
8366     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8367   },
8368   {
8369     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8370     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8371   },
8372   {
8373     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8374     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8375   },
8376   {
8377     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8378     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8379   },
8380   {
8381     /* MOD_VEX_0F385A */
8382     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8383   },
8384   {
8385     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8386     { Bad_Opcode },
8387     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8388   },
8389   {
8390     /* MOD_VEX_0F385C_X86_64_P_3_W_0 */
8391     { Bad_Opcode },
8392     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0) },
8393   },
8394   {
8395     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8396     { Bad_Opcode },
8397     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8398   },
8399   {
8400     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8401     { Bad_Opcode },
8402     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8403   },
8404   {
8405     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8406     { Bad_Opcode },
8407     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8408   },
8409   {
8410     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8411     { Bad_Opcode },
8412     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8413   },
8414   {
8415     /* MOD_VEX_0F388C */
8416     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8417   },
8418   {
8419     /* MOD_VEX_0F388E */
8420     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8421   },
8422   {
8423     /* MOD_VEX_0F3A30_L_0 */
8424     { Bad_Opcode },
8425     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8426   },
8427   {
8428     /* MOD_VEX_0F3A31_L_0 */
8429     { Bad_Opcode },
8430     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8431   },
8432   {
8433     /* MOD_VEX_0F3A32_L_0 */
8434     { Bad_Opcode },
8435     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8436   },
8437   {
8438     /* MOD_VEX_0F3A33_L_0 */
8439     { Bad_Opcode },
8440     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8441   },
8442   {
8443     /* MOD_XOP_09_12 */
8444     { Bad_Opcode },
8445     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8446   },
8447
8448 #include "i386-dis-evex-mod.h"
8449 };
8450
8451 static const struct dis386 rm_table[][8] = {
8452   {
8453     /* RM_C6_REG_7 */
8454     { "xabort",         { Skip_MODRM, Ib }, 0 },
8455   },
8456   {
8457     /* RM_C7_REG_7 */
8458     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8459   },
8460   {
8461     /* RM_0F01_REG_0 */
8462     { "enclv",          { Skip_MODRM }, 0 },
8463     { "vmcall",         { Skip_MODRM }, 0 },
8464     { "vmlaunch",       { Skip_MODRM }, 0 },
8465     { "vmresume",       { Skip_MODRM }, 0 },
8466     { "vmxoff",         { Skip_MODRM }, 0 },
8467     { "pconfig",        { Skip_MODRM }, 0 },
8468   },
8469   {
8470     /* RM_0F01_REG_1 */
8471     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8472     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8473     { "clac",           { Skip_MODRM }, 0 },
8474     { "stac",           { Skip_MODRM }, 0 },
8475     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8476     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8477     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8478     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8479   },
8480   {
8481     /* RM_0F01_REG_2 */
8482     { "xgetbv",         { Skip_MODRM }, 0 },
8483     { "xsetbv",         { Skip_MODRM }, 0 },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { "vmfunc",         { Skip_MODRM }, 0 },
8487     { "xend",           { Skip_MODRM }, 0 },
8488     { "xtest",          { Skip_MODRM }, 0 },
8489     { "enclu",          { Skip_MODRM }, 0 },
8490   },
8491   {
8492     /* RM_0F01_REG_3 */
8493     { "vmrun",          { Skip_MODRM }, 0 },
8494     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8495     { "vmload",         { Skip_MODRM }, 0 },
8496     { "vmsave",         { Skip_MODRM }, 0 },
8497     { "stgi",           { Skip_MODRM }, 0 },
8498     { "clgi",           { Skip_MODRM }, 0 },
8499     { "skinit",         { Skip_MODRM }, 0 },
8500     { "invlpga",        { Skip_MODRM }, 0 },
8501   },
8502   {
8503     /* RM_0F01_REG_5_MOD_3 */
8504     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8505     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8506     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8507     { Bad_Opcode },
8508     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8509     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8510     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8511     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8512   },
8513   {
8514     /* RM_0F01_REG_7_MOD_3 */
8515     { "swapgs",         { Skip_MODRM }, 0  },
8516     { "rdtscp",         { Skip_MODRM }, 0  },
8517     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8518     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8519     { "clzero",         { Skip_MODRM }, 0  },
8520     { "rdpru",          { Skip_MODRM }, 0  },
8521     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8522     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8523   },
8524   {
8525     /* RM_0F1E_P_1_MOD_3_REG_7 */
8526     { "nopQ",           { Ev }, PREFIX_IGNORED },
8527     { "nopQ",           { Ev }, PREFIX_IGNORED },
8528     { "endbr64",        { Skip_MODRM }, 0 },
8529     { "endbr32",        { Skip_MODRM }, 0 },
8530     { "nopQ",           { Ev }, PREFIX_IGNORED },
8531     { "nopQ",           { Ev }, PREFIX_IGNORED },
8532     { "nopQ",           { Ev }, PREFIX_IGNORED },
8533     { "nopQ",           { Ev }, PREFIX_IGNORED },
8534   },
8535   {
8536     /* RM_0FAE_REG_6_MOD_3 */
8537     { "mfence",         { Skip_MODRM }, 0 },
8538   },
8539   {
8540     /* RM_0FAE_REG_7_MOD_3 */
8541     { "sfence",         { Skip_MODRM }, 0 },
8542   },
8543   {
8544     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8545     { "hreset",         { Skip_MODRM, Ib }, 0 },
8546   },
8547   {
8548     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8549     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8550   },
8551 };
8552
8553 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8554
8555 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8556    in conflict with actual prefix opcodes.  */
8557 #define REP_PREFIX      0x01
8558 #define XACQUIRE_PREFIX 0x02
8559 #define XRELEASE_PREFIX 0x03
8560 #define BND_PREFIX      0x04
8561 #define NOTRACK_PREFIX  0x05
8562
8563 static int
8564 ckprefix (instr_info *ins)
8565 {
8566   int newrex, i, length;
8567
8568   i = 0;
8569   length = 0;
8570   /* The maximum instruction length is 15bytes.  */
8571   while (length < MAX_CODE_LENGTH - 1)
8572     {
8573       FETCH_DATA (ins->info, ins->codep + 1);
8574       newrex = 0;
8575       switch (*ins->codep)
8576         {
8577         /* REX prefixes family.  */
8578         case 0x40:
8579         case 0x41:
8580         case 0x42:
8581         case 0x43:
8582         case 0x44:
8583         case 0x45:
8584         case 0x46:
8585         case 0x47:
8586         case 0x48:
8587         case 0x49:
8588         case 0x4a:
8589         case 0x4b:
8590         case 0x4c:
8591         case 0x4d:
8592         case 0x4e:
8593         case 0x4f:
8594           if (ins->address_mode == mode_64bit)
8595             newrex = *ins->codep;
8596           else
8597             return 1;
8598           ins->last_rex_prefix = i;
8599           break;
8600         case 0xf3:
8601           ins->prefixes |= PREFIX_REPZ;
8602           ins->last_repz_prefix = i;
8603           break;
8604         case 0xf2:
8605           ins->prefixes |= PREFIX_REPNZ;
8606           ins->last_repnz_prefix = i;
8607           break;
8608         case 0xf0:
8609           ins->prefixes |= PREFIX_LOCK;
8610           ins->last_lock_prefix = i;
8611           break;
8612         case 0x2e:
8613           ins->prefixes |= PREFIX_CS;
8614           ins->last_seg_prefix = i;
8615           if (ins->address_mode != mode_64bit)
8616             ins->active_seg_prefix = PREFIX_CS;
8617           break;
8618         case 0x36:
8619           ins->prefixes |= PREFIX_SS;
8620           ins->last_seg_prefix = i;
8621           if (ins->address_mode != mode_64bit)
8622             ins->active_seg_prefix = PREFIX_SS;
8623           break;
8624         case 0x3e:
8625           ins->prefixes |= PREFIX_DS;
8626           ins->last_seg_prefix = i;
8627           if (ins->address_mode != mode_64bit)
8628             ins->active_seg_prefix = PREFIX_DS;
8629           break;
8630         case 0x26:
8631           ins->prefixes |= PREFIX_ES;
8632           ins->last_seg_prefix = i;
8633           if (ins->address_mode != mode_64bit)
8634             ins->active_seg_prefix = PREFIX_ES;
8635           break;
8636         case 0x64:
8637           ins->prefixes |= PREFIX_FS;
8638           ins->last_seg_prefix = i;
8639           ins->active_seg_prefix = PREFIX_FS;
8640           break;
8641         case 0x65:
8642           ins->prefixes |= PREFIX_GS;
8643           ins->last_seg_prefix = i;
8644           ins->active_seg_prefix = PREFIX_GS;
8645           break;
8646         case 0x66:
8647           ins->prefixes |= PREFIX_DATA;
8648           ins->last_data_prefix = i;
8649           break;
8650         case 0x67:
8651           ins->prefixes |= PREFIX_ADDR;
8652           ins->last_addr_prefix = i;
8653           break;
8654         case FWAIT_OPCODE:
8655           /* fwait is really an instruction.  If there are prefixes
8656              before the fwait, they belong to the fwait, *not* to the
8657              following instruction.  */
8658           ins->fwait_prefix = i;
8659           if (ins->prefixes || ins->rex)
8660             {
8661               ins->prefixes |= PREFIX_FWAIT;
8662               ins->codep++;
8663               /* This ensures that the previous REX prefixes are noticed
8664                  as unused prefixes, as in the return case below.  */
8665               ins->rex_used = ins->rex;
8666               return 1;
8667             }
8668           ins->prefixes = PREFIX_FWAIT;
8669           break;
8670         default:
8671           return 1;
8672         }
8673       /* Rex is ignored when followed by another prefix.  */
8674       if (ins->rex)
8675         {
8676           ins->rex_used = ins->rex;
8677           return 1;
8678         }
8679       if (*ins->codep != FWAIT_OPCODE)
8680         ins->all_prefixes[i++] = *ins->codep;
8681       ins->rex = newrex;
8682       ins->codep++;
8683       length++;
8684     }
8685   return 0;
8686 }
8687
8688 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8689    prefix byte.  */
8690
8691 static const char *
8692 prefix_name (instr_info *ins, int pref, int sizeflag)
8693 {
8694   static const char *rexes [16] =
8695     {
8696       "rex",            /* 0x40 */
8697       "rex.B",          /* 0x41 */
8698       "rex.X",          /* 0x42 */
8699       "rex.XB",         /* 0x43 */
8700       "rex.R",          /* 0x44 */
8701       "rex.RB",         /* 0x45 */
8702       "rex.RX",         /* 0x46 */
8703       "rex.RXB",        /* 0x47 */
8704       "rex.W",          /* 0x48 */
8705       "rex.WB",         /* 0x49 */
8706       "rex.WX",         /* 0x4a */
8707       "rex.WXB",        /* 0x4b */
8708       "rex.WR",         /* 0x4c */
8709       "rex.WRB",        /* 0x4d */
8710       "rex.WRX",        /* 0x4e */
8711       "rex.WRXB",       /* 0x4f */
8712     };
8713
8714   switch (pref)
8715     {
8716     /* REX prefixes family.  */
8717     case 0x40:
8718     case 0x41:
8719     case 0x42:
8720     case 0x43:
8721     case 0x44:
8722     case 0x45:
8723     case 0x46:
8724     case 0x47:
8725     case 0x48:
8726     case 0x49:
8727     case 0x4a:
8728     case 0x4b:
8729     case 0x4c:
8730     case 0x4d:
8731     case 0x4e:
8732     case 0x4f:
8733       return rexes [pref - 0x40];
8734     case 0xf3:
8735       return "repz";
8736     case 0xf2:
8737       return "repnz";
8738     case 0xf0:
8739       return "lock";
8740     case 0x2e:
8741       return "cs";
8742     case 0x36:
8743       return "ss";
8744     case 0x3e:
8745       return "ds";
8746     case 0x26:
8747       return "es";
8748     case 0x64:
8749       return "fs";
8750     case 0x65:
8751       return "gs";
8752     case 0x66:
8753       return (sizeflag & DFLAG) ? "data16" : "data32";
8754     case 0x67:
8755       if (ins->address_mode == mode_64bit)
8756         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8757       else
8758         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8759     case FWAIT_OPCODE:
8760       return "fwait";
8761     case REP_PREFIX:
8762       return "rep";
8763     case XACQUIRE_PREFIX:
8764       return "xacquire";
8765     case XRELEASE_PREFIX:
8766       return "xrelease";
8767     case BND_PREFIX:
8768       return "bnd";
8769     case NOTRACK_PREFIX:
8770       return "notrack";
8771     default:
8772       return NULL;
8773     }
8774 }
8775
8776 void
8777 print_i386_disassembler_options (FILE *stream)
8778 {
8779   fprintf (stream, _("\n\
8780 The following i386/x86-64 specific disassembler options are supported for use\n\
8781 with the -M switch (multiple options should be separated by commas):\n"));
8782
8783   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8784   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8785   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8786   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8787   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8788   fprintf (stream, _("  att-mnemonic\n"
8789                      "              Display instruction in AT&T mnemonic\n"));
8790   fprintf (stream, _("  intel-mnemonic\n"
8791                      "              Display instruction in Intel mnemonic\n"));
8792   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8793   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8794   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8795   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8796   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8797   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8798   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8799   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8800 }
8801
8802 /* Bad opcode.  */
8803 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8804
8805 /* Get a pointer to struct dis386 with a valid name.  */
8806
8807 static const struct dis386 *
8808 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8809 {
8810   int vindex, vex_table_index;
8811
8812   if (dp->name != NULL)
8813     return dp;
8814
8815   switch (dp->op[0].bytemode)
8816     {
8817     case USE_REG_TABLE:
8818       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8819       break;
8820
8821     case USE_MOD_TABLE:
8822       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8823       dp = &mod_table[dp->op[1].bytemode][vindex];
8824       break;
8825
8826     case USE_RM_TABLE:
8827       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8828       break;
8829
8830     case USE_PREFIX_TABLE:
8831       if (ins->need_vex)
8832         {
8833           /* The prefix in VEX is implicit.  */
8834           switch (ins->vex.prefix)
8835             {
8836             case 0:
8837               vindex = 0;
8838               break;
8839             case REPE_PREFIX_OPCODE:
8840               vindex = 1;
8841               break;
8842             case DATA_PREFIX_OPCODE:
8843               vindex = 2;
8844               break;
8845             case REPNE_PREFIX_OPCODE:
8846               vindex = 3;
8847               break;
8848             default:
8849               abort ();
8850               break;
8851             }
8852         }
8853       else
8854         {
8855           int last_prefix = -1;
8856           int prefix = 0;
8857           vindex = 0;
8858           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8859              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8860              last one wins.  */
8861           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8862             {
8863               if (ins->last_repz_prefix > ins->last_repnz_prefix)
8864                 {
8865                   vindex = 1;
8866                   prefix = PREFIX_REPZ;
8867                   last_prefix = ins->last_repz_prefix;
8868                 }
8869               else
8870                 {
8871                   vindex = 3;
8872                   prefix = PREFIX_REPNZ;
8873                   last_prefix = ins->last_repnz_prefix;
8874                 }
8875
8876               /* Check if prefix should be ignored.  */
8877               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8878                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8879                    & prefix) != 0
8880                   && !prefix_table[dp->op[1].bytemode][vindex].name)
8881                 vindex = 0;
8882             }
8883
8884           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8885             {
8886               vindex = 2;
8887               prefix = PREFIX_DATA;
8888               last_prefix = ins->last_data_prefix;
8889             }
8890
8891           if (vindex != 0)
8892             {
8893               ins->used_prefixes |= prefix;
8894               ins->all_prefixes[last_prefix] = 0;
8895             }
8896         }
8897       dp = &prefix_table[dp->op[1].bytemode][vindex];
8898       break;
8899
8900     case USE_X86_64_TABLE:
8901       vindex = ins->address_mode == mode_64bit ? 1 : 0;
8902       dp = &x86_64_table[dp->op[1].bytemode][vindex];
8903       break;
8904
8905     case USE_3BYTE_TABLE:
8906       FETCH_DATA (ins->info, ins->codep + 2);
8907       vindex = *ins->codep++;
8908       dp = &three_byte_table[dp->op[1].bytemode][vindex];
8909       ins->end_codep = ins->codep;
8910       ins->modrm.mod = (*ins->codep >> 6) & 3;
8911       ins->modrm.reg = (*ins->codep >> 3) & 7;
8912       ins->modrm.rm = *ins->codep & 7;
8913       break;
8914
8915     case USE_VEX_LEN_TABLE:
8916       if (!ins->need_vex)
8917         abort ();
8918
8919       switch (ins->vex.length)
8920         {
8921         case 128:
8922           vindex = 0;
8923           break;
8924         case 512:
8925           /* This allows re-using in particular table entries where only
8926              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
8927           if (ins->vex.evex)
8928             {
8929         case 256:
8930               vindex = 1;
8931               break;
8932             }
8933         /* Fall through.  */
8934         default:
8935           abort ();
8936           break;
8937         }
8938
8939       dp = &vex_len_table[dp->op[1].bytemode][vindex];
8940       break;
8941
8942     case USE_EVEX_LEN_TABLE:
8943       if (!ins->vex.evex)
8944         abort ();
8945
8946       switch (ins->vex.length)
8947         {
8948         case 128:
8949           vindex = 0;
8950           break;
8951         case 256:
8952           vindex = 1;
8953           break;
8954         case 512:
8955           vindex = 2;
8956           break;
8957         default:
8958           abort ();
8959           break;
8960         }
8961
8962       dp = &evex_len_table[dp->op[1].bytemode][vindex];
8963       break;
8964
8965     case USE_XOP_8F_TABLE:
8966       FETCH_DATA (ins->info, ins->codep + 3);
8967       ins->rex = ~(*ins->codep >> 5) & 0x7;
8968
8969       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
8970       switch ((*ins->codep & 0x1f))
8971         {
8972         default:
8973           dp = &bad_opcode;
8974           return dp;
8975         case 0x8:
8976           vex_table_index = XOP_08;
8977           break;
8978         case 0x9:
8979           vex_table_index = XOP_09;
8980           break;
8981         case 0xa:
8982           vex_table_index = XOP_0A;
8983           break;
8984         }
8985       ins->codep++;
8986       ins->vex.w = *ins->codep & 0x80;
8987       if (ins->vex.w && ins->address_mode == mode_64bit)
8988         ins->rex |= REX_W;
8989
8990       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8991       if (ins->address_mode != mode_64bit)
8992         {
8993           /* In 16/32-bit mode REX_B is silently ignored.  */
8994           ins->rex &= ~REX_B;
8995         }
8996
8997       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8998       switch ((*ins->codep & 0x3))
8999         {
9000         case 0:
9001           break;
9002         case 1:
9003           ins->vex.prefix = DATA_PREFIX_OPCODE;
9004           break;
9005         case 2:
9006           ins->vex.prefix = REPE_PREFIX_OPCODE;
9007           break;
9008         case 3:
9009           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9010           break;
9011         }
9012       ins->need_vex = true;
9013       ins->codep++;
9014       vindex = *ins->codep++;
9015       dp = &xop_table[vex_table_index][vindex];
9016
9017       ins->end_codep = ins->codep;
9018       FETCH_DATA (ins->info, ins->codep + 1);
9019       ins->modrm.mod = (*ins->codep >> 6) & 3;
9020       ins->modrm.reg = (*ins->codep >> 3) & 7;
9021       ins->modrm.rm = *ins->codep & 7;
9022
9023       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9024          having to decode the bits for every otherwise valid encoding.  */
9025       if (ins->vex.prefix)
9026         return &bad_opcode;
9027       break;
9028
9029     case USE_VEX_C4_TABLE:
9030       /* VEX prefix.  */
9031       FETCH_DATA (ins->info, ins->codep + 3);
9032       ins->rex = ~(*ins->codep >> 5) & 0x7;
9033       switch ((*ins->codep & 0x1f))
9034         {
9035         default:
9036           dp = &bad_opcode;
9037           return dp;
9038         case 0x1:
9039           vex_table_index = VEX_0F;
9040           break;
9041         case 0x2:
9042           vex_table_index = VEX_0F38;
9043           break;
9044         case 0x3:
9045           vex_table_index = VEX_0F3A;
9046           break;
9047         }
9048       ins->codep++;
9049       ins->vex.w = *ins->codep & 0x80;
9050       if (ins->address_mode == mode_64bit)
9051         {
9052           if (ins->vex.w)
9053             ins->rex |= REX_W;
9054         }
9055       else
9056         {
9057           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9058              is ignored, other REX bits are 0 and the highest bit in
9059              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9060           ins->rex = 0;
9061         }
9062       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9063       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9064       switch ((*ins->codep & 0x3))
9065         {
9066         case 0:
9067           break;
9068         case 1:
9069           ins->vex.prefix = DATA_PREFIX_OPCODE;
9070           break;
9071         case 2:
9072           ins->vex.prefix = REPE_PREFIX_OPCODE;
9073           break;
9074         case 3:
9075           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9076           break;
9077         }
9078       ins->need_vex = true;
9079       ins->codep++;
9080       vindex = *ins->codep++;
9081       dp = &vex_table[vex_table_index][vindex];
9082       ins->end_codep = ins->codep;
9083       /* There is no MODRM byte for VEX0F 77.  */
9084       if (vex_table_index != VEX_0F || vindex != 0x77)
9085         {
9086           FETCH_DATA (ins->info, ins->codep + 1);
9087           ins->modrm.mod = (*ins->codep >> 6) & 3;
9088           ins->modrm.reg = (*ins->codep >> 3) & 7;
9089           ins->modrm.rm = *ins->codep & 7;
9090         }
9091       break;
9092
9093     case USE_VEX_C5_TABLE:
9094       /* VEX prefix.  */
9095       FETCH_DATA (ins->info, ins->codep + 2);
9096       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9097
9098       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9099          VEX.vvvv is 1.  */
9100       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9101       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9102       switch ((*ins->codep & 0x3))
9103         {
9104         case 0:
9105           break;
9106         case 1:
9107           ins->vex.prefix = DATA_PREFIX_OPCODE;
9108           break;
9109         case 2:
9110           ins->vex.prefix = REPE_PREFIX_OPCODE;
9111           break;
9112         case 3:
9113           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9114           break;
9115         }
9116       ins->need_vex = true;
9117       ins->codep++;
9118       vindex = *ins->codep++;
9119       dp = &vex_table[dp->op[1].bytemode][vindex];
9120       ins->end_codep = ins->codep;
9121       /* There is no MODRM byte for VEX 77.  */
9122       if (vindex != 0x77)
9123         {
9124           FETCH_DATA (ins->info, ins->codep + 1);
9125           ins->modrm.mod = (*ins->codep >> 6) & 3;
9126           ins->modrm.reg = (*ins->codep >> 3) & 7;
9127           ins->modrm.rm = *ins->codep & 7;
9128         }
9129       break;
9130
9131     case USE_VEX_W_TABLE:
9132       if (!ins->need_vex)
9133         abort ();
9134
9135       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9136       break;
9137
9138     case USE_EVEX_TABLE:
9139       ins->two_source_ops = false;
9140       /* EVEX prefix.  */
9141       ins->vex.evex = true;
9142       FETCH_DATA (ins->info, ins->codep + 4);
9143       /* The first byte after 0x62.  */
9144       ins->rex = ~(*ins->codep >> 5) & 0x7;
9145       ins->vex.r = *ins->codep & 0x10;
9146       switch ((*ins->codep & 0xf))
9147         {
9148         default:
9149           return &bad_opcode;
9150         case 0x1:
9151           vex_table_index = EVEX_0F;
9152           break;
9153         case 0x2:
9154           vex_table_index = EVEX_0F38;
9155           break;
9156         case 0x3:
9157           vex_table_index = EVEX_0F3A;
9158           break;
9159         case 0x5:
9160           vex_table_index = EVEX_MAP5;
9161           break;
9162         case 0x6:
9163           vex_table_index = EVEX_MAP6;
9164           break;
9165         }
9166
9167       /* The second byte after 0x62.  */
9168       ins->codep++;
9169       ins->vex.w = *ins->codep & 0x80;
9170       if (ins->vex.w && ins->address_mode == mode_64bit)
9171         ins->rex |= REX_W;
9172
9173       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9174
9175       /* The U bit.  */
9176       if (!(*ins->codep & 0x4))
9177         return &bad_opcode;
9178
9179       switch ((*ins->codep & 0x3))
9180         {
9181         case 0:
9182           break;
9183         case 1:
9184           ins->vex.prefix = DATA_PREFIX_OPCODE;
9185           break;
9186         case 2:
9187           ins->vex.prefix = REPE_PREFIX_OPCODE;
9188           break;
9189         case 3:
9190           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9191           break;
9192         }
9193
9194       /* The third byte after 0x62.  */
9195       ins->codep++;
9196
9197       /* Remember the static rounding bits.  */
9198       ins->vex.ll = (*ins->codep >> 5) & 3;
9199       ins->vex.b = *ins->codep & 0x10;
9200
9201       ins->vex.v = *ins->codep & 0x8;
9202       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9203       ins->vex.zeroing = *ins->codep & 0x80;
9204
9205       if (ins->address_mode != mode_64bit)
9206         {
9207           /* In 16/32-bit mode silently ignore following bits.  */
9208           ins->rex &= ~REX_B;
9209           ins->vex.r = true;
9210         }
9211
9212       ins->need_vex = true;
9213       ins->codep++;
9214       vindex = *ins->codep++;
9215       dp = &evex_table[vex_table_index][vindex];
9216       ins->end_codep = ins->codep;
9217       FETCH_DATA (ins->info, ins->codep + 1);
9218       ins->modrm.mod = (*ins->codep >> 6) & 3;
9219       ins->modrm.reg = (*ins->codep >> 3) & 7;
9220       ins->modrm.rm = *ins->codep & 7;
9221
9222       /* Set vector length.  */
9223       if (ins->modrm.mod == 3 && ins->vex.b)
9224         ins->vex.length = 512;
9225       else
9226         {
9227           switch (ins->vex.ll)
9228             {
9229             case 0x0:
9230               ins->vex.length = 128;
9231               break;
9232             case 0x1:
9233               ins->vex.length = 256;
9234               break;
9235             case 0x2:
9236               ins->vex.length = 512;
9237               break;
9238             default:
9239               return &bad_opcode;
9240             }
9241         }
9242       break;
9243
9244     case 0:
9245       dp = &bad_opcode;
9246       break;
9247
9248     default:
9249       abort ();
9250     }
9251
9252   if (dp->name != NULL)
9253     return dp;
9254   else
9255     return get_valid_dis386 (dp, ins);
9256 }
9257
9258 static void
9259 get_sib (instr_info *ins, int sizeflag)
9260 {
9261   /* If modrm.mod == 3, operand must be register.  */
9262   if (ins->need_modrm
9263       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9264       && ins->modrm.mod != 3
9265       && ins->modrm.rm == 4)
9266     {
9267       FETCH_DATA (ins->info, ins->codep + 2);
9268       ins->sib.index = (ins->codep[1] >> 3) & 7;
9269       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9270       ins->sib.base = ins->codep[1] & 7;
9271       ins->has_sib = true;
9272     }
9273   else
9274     ins->has_sib = false;
9275 }
9276
9277 /* Like oappend (below), but S is a string starting with '%'.  In
9278    Intel syntax, the '%' is elided.  */
9279
9280 static void
9281 oappend_register (instr_info *ins, const char *s)
9282 {
9283   oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9284 }
9285
9286 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9287    STYLE is the default style to use in the fprintf_styled_func calls,
9288    however, FMT might include embedded style markers (see oappend_style),
9289    these embedded markers are not printed, but instead change the style
9290    used in the next fprintf_styled_func call.  */
9291
9292 static void ATTRIBUTE_PRINTF_3
9293 i386_dis_printf (instr_info *ins, enum disassembler_style style,
9294                  const char *fmt, ...)
9295 {
9296   va_list ap;
9297   enum disassembler_style curr_style = style;
9298   const char *start, *curr;
9299   char staging_area[40];
9300
9301   va_start (ap, fmt);
9302   /* In particular print_insn()'s processing of op_txt[] can hand rather long
9303      strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9304      with the staging area.  */
9305   if (strcmp (fmt, "%s"))
9306     {
9307       int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9308
9309       va_end (ap);
9310
9311       if (res < 0)
9312         return;
9313
9314       if ((size_t) res >= sizeof (staging_area))
9315         abort ();
9316
9317       start = curr = staging_area;
9318     }
9319   else
9320     {
9321       start = curr = va_arg (ap, const char *);
9322       va_end (ap);
9323     }
9324
9325   do
9326     {
9327       if (*curr == '\0'
9328           || (*curr == STYLE_MARKER_CHAR
9329               && ISXDIGIT (*(curr + 1))
9330               && *(curr + 2) == STYLE_MARKER_CHAR))
9331         {
9332           /* Output content between our START position and CURR.  */
9333           int len = curr - start;
9334           int n = (*ins->info->fprintf_styled_func) (ins->info->stream,
9335                                                      curr_style,
9336                                                      "%.*s", len, start);
9337           if (n < 0)
9338             break;
9339
9340           if (*curr == '\0')
9341             break;
9342
9343           /* Skip over the initial STYLE_MARKER_CHAR.  */
9344           ++curr;
9345
9346           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9347              is possible, that if the input is corrupted in some way, that
9348              we might set CURR_STYLE to an invalid value.  Don't worry
9349              though, we check for this situation.  */
9350           if (*curr >= '0' && *curr <= '9')
9351             curr_style = (enum disassembler_style) (*curr - '0');
9352           else if (*curr >= 'a' && *curr <= 'f')
9353             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9354           else
9355             curr_style = dis_style_text;
9356
9357           /* Check for an invalid style having been selected.  This should
9358              never happen, but it doesn't hurt to be a little paranoid.  */
9359           if (curr_style > dis_style_comment_start)
9360             curr_style = dis_style_text;
9361
9362           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9363           curr += 2;
9364
9365           /* Reset the START to after the style marker.  */
9366           start = curr;
9367         }
9368       else
9369         ++curr;
9370     }
9371   while (true);
9372 }
9373
9374 static int
9375 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9376 {
9377   const struct dis386 *dp;
9378   int i;
9379   char *op_txt[MAX_OPERANDS];
9380   int needcomma;
9381   bool intel_swap_2_3;
9382   int sizeflag, orig_sizeflag;
9383   const char *p;
9384   struct dis_private priv;
9385   int prefix_length;
9386   int op_count;
9387   instr_info ins = {
9388     .info = info,
9389     .intel_syntax = intel_syntax >= 0
9390                     ? intel_syntax
9391                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9392     .intel_mnemonic = !SYSV386_COMPAT,
9393     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9394     .start_pc = pc,
9395     .start_codep = priv.the_buffer,
9396     .codep = priv.the_buffer,
9397     .obufp = ins.obuf,
9398     .last_lock_prefix = -1,
9399     .last_repz_prefix = -1,
9400     .last_repnz_prefix = -1,
9401     .last_data_prefix = -1,
9402     .last_addr_prefix = -1,
9403     .last_rex_prefix = -1,
9404     .last_seg_prefix = -1,
9405     .fwait_prefix = -1,
9406   };
9407   char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9408
9409   priv.orig_sizeflag = AFLAG | DFLAG;
9410   if ((info->mach & bfd_mach_i386_i386) != 0)
9411     ins.address_mode = mode_32bit;
9412   else if (info->mach == bfd_mach_i386_i8086)
9413     {
9414       ins.address_mode = mode_16bit;
9415       priv.orig_sizeflag = 0;
9416     }
9417   else
9418     ins.address_mode = mode_64bit;
9419
9420   for (p = info->disassembler_options; p != NULL;)
9421     {
9422       if (startswith (p, "amd64"))
9423         ins.isa64 = amd64;
9424       else if (startswith (p, "intel64"))
9425         ins.isa64 = intel64;
9426       else if (startswith (p, "x86-64"))
9427         {
9428           ins.address_mode = mode_64bit;
9429           priv.orig_sizeflag |= AFLAG | DFLAG;
9430         }
9431       else if (startswith (p, "i386"))
9432         {
9433           ins.address_mode = mode_32bit;
9434           priv.orig_sizeflag |= AFLAG | DFLAG;
9435         }
9436       else if (startswith (p, "i8086"))
9437         {
9438           ins.address_mode = mode_16bit;
9439           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9440         }
9441       else if (startswith (p, "intel"))
9442         {
9443           ins.intel_syntax = 1;
9444           if (startswith (p + 5, "-mnemonic"))
9445             ins.intel_mnemonic = true;
9446         }
9447       else if (startswith (p, "att"))
9448         {
9449           ins.intel_syntax = 0;
9450           if (startswith (p + 3, "-mnemonic"))
9451             ins.intel_mnemonic = false;
9452         }
9453       else if (startswith (p, "addr"))
9454         {
9455           if (ins.address_mode == mode_64bit)
9456             {
9457               if (p[4] == '3' && p[5] == '2')
9458                 priv.orig_sizeflag &= ~AFLAG;
9459               else if (p[4] == '6' && p[5] == '4')
9460                 priv.orig_sizeflag |= AFLAG;
9461             }
9462           else
9463             {
9464               if (p[4] == '1' && p[5] == '6')
9465                 priv.orig_sizeflag &= ~AFLAG;
9466               else if (p[4] == '3' && p[5] == '2')
9467                 priv.orig_sizeflag |= AFLAG;
9468             }
9469         }
9470       else if (startswith (p, "data"))
9471         {
9472           if (p[4] == '1' && p[5] == '6')
9473             priv.orig_sizeflag &= ~DFLAG;
9474           else if (p[4] == '3' && p[5] == '2')
9475             priv.orig_sizeflag |= DFLAG;
9476         }
9477       else if (startswith (p, "suffix"))
9478         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9479
9480       p = strchr (p, ',');
9481       if (p != NULL)
9482         p++;
9483     }
9484
9485   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9486     {
9487       i386_dis_printf (&ins, dis_style_text, _("64-bit address is disabled"));
9488       return -1;
9489     }
9490
9491   if (ins.intel_syntax)
9492     {
9493       ins.open_char = '[';
9494       ins.close_char = ']';
9495       ins.separator_char = '+';
9496       ins.scale_char = '*';
9497     }
9498   else
9499     {
9500       ins.open_char = '(';
9501       ins.close_char =  ')';
9502       ins.separator_char = ',';
9503       ins.scale_char = ',';
9504     }
9505
9506   /* The output looks better if we put 7 bytes on a line, since that
9507      puts most long word instructions on a single line.  */
9508   info->bytes_per_line = 7;
9509
9510   info->private_data = &priv;
9511   priv.max_fetched = priv.the_buffer;
9512   priv.insn_start = pc;
9513
9514   for (i = 0; i < MAX_OPERANDS; ++i)
9515     {
9516       op_out[i][0] = 0;
9517       ins.op_out[i] = op_out[i];
9518     }
9519
9520   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9521     {
9522       /* Getting here means we tried for data but didn't get it.  That
9523          means we have an incomplete instruction of some sort.  Just
9524          print the first byte as a prefix or a .byte pseudo-op.  */
9525       if (ins.codep > priv.the_buffer)
9526         {
9527           const char *name = NULL;
9528
9529           if (ins.prefixes || ins.fwait_prefix >= 0 || (ins.rex & REX_OPCODE))
9530             name = prefix_name (&ins, priv.the_buffer[0], priv.orig_sizeflag);
9531           if (name != NULL)
9532             i386_dis_printf (&ins, dis_style_mnemonic, "%s", name);
9533           else
9534             {
9535               /* Just print the first byte as a .byte instruction.  */
9536               i386_dis_printf (&ins, dis_style_assembler_directive,
9537                                ".byte ");
9538               i386_dis_printf (&ins, dis_style_immediate, "0x%x",
9539                                (unsigned int) priv.the_buffer[0]);
9540             }
9541
9542           return 1;
9543         }
9544
9545       return -1;
9546     }
9547
9548   sizeflag = priv.orig_sizeflag;
9549
9550   if (!ckprefix (&ins) || ins.rex_used)
9551     {
9552       /* Too many prefixes or unused REX prefixes.  */
9553       for (i = 0;
9554            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9555            i++)
9556         i386_dis_printf (&ins, dis_style_mnemonic, "%s%s",
9557                          (i == 0 ? "" : " "),
9558                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9559       return i;
9560     }
9561
9562   ins.insn_codep = ins.codep;
9563
9564   FETCH_DATA (info, ins.codep + 1);
9565   ins.two_source_ops = (*ins.codep == 0x62) || (*ins.codep == 0xc8);
9566
9567   if (((ins.prefixes & PREFIX_FWAIT)
9568        && ((*ins.codep < 0xd8) || (*ins.codep > 0xdf))))
9569     {
9570       /* Handle ins.prefixes before fwait.  */
9571       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9572            i++)
9573         i386_dis_printf (&ins, dis_style_mnemonic, "%s ",
9574                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9575       i386_dis_printf (&ins, dis_style_mnemonic, "fwait");
9576       return i + 1;
9577     }
9578
9579   if (*ins.codep == 0x0f)
9580     {
9581       unsigned char threebyte;
9582
9583       ins.codep++;
9584       FETCH_DATA (info, ins.codep + 1);
9585       threebyte = *ins.codep;
9586       dp = &dis386_twobyte[threebyte];
9587       ins.need_modrm = twobyte_has_modrm[threebyte];
9588       ins.codep++;
9589     }
9590   else
9591     {
9592       dp = &dis386[*ins.codep];
9593       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9594       ins.codep++;
9595     }
9596
9597   /* Save sizeflag for printing the extra ins.prefixes later before updating
9598      it for mnemonic and operand processing.  The prefix names depend
9599      only on the address mode.  */
9600   orig_sizeflag = sizeflag;
9601   if (ins.prefixes & PREFIX_ADDR)
9602     sizeflag ^= AFLAG;
9603   if ((ins.prefixes & PREFIX_DATA))
9604     sizeflag ^= DFLAG;
9605
9606   ins.end_codep = ins.codep;
9607   if (ins.need_modrm)
9608     {
9609       FETCH_DATA (info, ins.codep + 1);
9610       ins.modrm.mod = (*ins.codep >> 6) & 3;
9611       ins.modrm.reg = (*ins.codep >> 3) & 7;
9612       ins.modrm.rm = *ins.codep & 7;
9613     }
9614
9615   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9616     {
9617       get_sib (&ins, sizeflag);
9618       dofloat (&ins, sizeflag);
9619     }
9620   else
9621     {
9622       dp = get_valid_dis386 (dp, &ins);
9623       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9624         {
9625           get_sib (&ins, sizeflag);
9626           for (i = 0; i < MAX_OPERANDS; ++i)
9627             {
9628               ins.obufp = ins.op_out[i];
9629               ins.op_ad = MAX_OPERANDS - 1 - i;
9630               if (dp->op[i].rtn)
9631                 (*dp->op[i].rtn) (&ins, dp->op[i].bytemode, sizeflag);
9632               /* For EVEX instruction after the last operand masking
9633                  should be printed.  */
9634               if (i == 0 && ins.vex.evex)
9635                 {
9636                   /* Don't print {%k0}.  */
9637                   if (ins.vex.mask_register_specifier)
9638                     {
9639                       const char *reg_name
9640                         = att_names_mask[ins.vex.mask_register_specifier];
9641
9642                       oappend (&ins, "{");
9643                       oappend_register (&ins, reg_name);
9644                       oappend (&ins, "}");
9645                     }
9646                   if (ins.vex.zeroing)
9647                     oappend (&ins, "{z}");
9648
9649                   /* S/G insns require a mask and don't allow
9650                      zeroing-masking.  */
9651                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9652                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9653                       && (ins.vex.mask_register_specifier == 0
9654                           || ins.vex.zeroing))
9655                     oappend (&ins, "/(bad)");
9656                 }
9657             }
9658
9659           /* Check whether rounding control was enabled for an insn not
9660              supporting it.  */
9661           if (ins.modrm.mod == 3 && ins.vex.b
9662               && !(ins.evex_used & EVEX_b_used))
9663             {
9664               for (i = 0; i < MAX_OPERANDS; ++i)
9665                 {
9666                   ins.obufp = ins.op_out[i];
9667                   if (*ins.obufp)
9668                     continue;
9669                   oappend (&ins, names_rounding[ins.vex.ll]);
9670                   oappend (&ins, "bad}");
9671                   break;
9672                 }
9673             }
9674         }
9675     }
9676
9677   /* Clear instruction information.  */
9678   info->insn_info_valid = 0;
9679   info->branch_delay_insns = 0;
9680   info->data_size = 0;
9681   info->insn_type = dis_noninsn;
9682   info->target = 0;
9683   info->target2 = 0;
9684
9685   /* Reset jump operation indicator.  */
9686   ins.op_is_jump = false;
9687   {
9688     int jump_detection = 0;
9689
9690     /* Extract flags.  */
9691     for (i = 0; i < MAX_OPERANDS; ++i)
9692       {
9693         if ((dp->op[i].rtn == OP_J)
9694             || (dp->op[i].rtn == OP_indirE))
9695           jump_detection |= 1;
9696         else if ((dp->op[i].rtn == BND_Fixup)
9697                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9698           jump_detection |= 2;
9699         else if ((dp->op[i].bytemode == cond_jump_mode)
9700                  || (dp->op[i].bytemode == loop_jcxz_mode))
9701           jump_detection |= 4;
9702       }
9703
9704     /* Determine if this is a jump or branch.  */
9705     if ((jump_detection & 0x3) == 0x3)
9706       {
9707         ins.op_is_jump = true;
9708         if (jump_detection & 0x4)
9709           info->insn_type = dis_condbranch;
9710         else
9711           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9712             ? dis_jsr : dis_branch;
9713       }
9714   }
9715
9716   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9717      are all 0s in inverted form.  */
9718   if (ins.need_vex && ins.vex.register_specifier != 0)
9719     {
9720       i386_dis_printf (&ins, dis_style_text, "(bad)");
9721       return ins.end_codep - priv.the_buffer;
9722     }
9723
9724   /* If EVEX.z is set, there must be an actual mask register in use.  */
9725   if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
9726     {
9727       i386_dis_printf (&ins, dis_style_text, "(bad)");
9728       return ins.end_codep - priv.the_buffer;
9729     }
9730
9731   switch (dp->prefix_requirement)
9732     {
9733     case PREFIX_DATA:
9734       /* If only the data prefix is marked as mandatory, its absence renders
9735          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9736       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9737         {
9738           i386_dis_printf (&ins, dis_style_text, "(bad)");
9739           return ins.end_codep - priv.the_buffer;
9740         }
9741       ins.used_prefixes |= PREFIX_DATA;
9742       /* Fall through.  */
9743     case PREFIX_OPCODE:
9744       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9745          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9746          used by putop and MMX/SSE operand and may be overridden by the
9747          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9748          separately.  */
9749       if (((ins.need_vex
9750             ? ins.vex.prefix == REPE_PREFIX_OPCODE
9751               || ins.vex.prefix == REPNE_PREFIX_OPCODE
9752             : (ins.prefixes
9753                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9754            && (ins.used_prefixes
9755                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9756           || (((ins.need_vex
9757                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9758                 : ((ins.prefixes
9759                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9760                    == PREFIX_DATA))
9761                && (ins.used_prefixes & PREFIX_DATA) == 0))
9762           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9763               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9764         {
9765           i386_dis_printf (&ins, dis_style_text, "(bad)");
9766           return ins.end_codep - priv.the_buffer;
9767         }
9768       break;
9769
9770     case PREFIX_IGNORED:
9771       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9772          origins in all_prefixes.  */
9773       ins.used_prefixes &= ~PREFIX_OPCODE;
9774       if (ins.last_data_prefix >= 0)
9775         ins.all_prefixes[ins.last_data_prefix] = 0x66;
9776       if (ins.last_repz_prefix >= 0)
9777         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9778       if (ins.last_repnz_prefix >= 0)
9779         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9780       break;
9781     }
9782
9783   /* Check if the REX prefix is used.  */
9784   if ((ins.rex ^ ins.rex_used) == 0
9785       && !ins.need_vex && ins.last_rex_prefix >= 0)
9786     ins.all_prefixes[ins.last_rex_prefix] = 0;
9787
9788   /* Check if the SEG prefix is used.  */
9789   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9790                        | PREFIX_FS | PREFIX_GS)) != 0
9791       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9792     ins.all_prefixes[ins.last_seg_prefix] = 0;
9793
9794   /* Check if the ADDR prefix is used.  */
9795   if ((ins.prefixes & PREFIX_ADDR) != 0
9796       && (ins.used_prefixes & PREFIX_ADDR) != 0)
9797     ins.all_prefixes[ins.last_addr_prefix] = 0;
9798
9799   /* Check if the DATA prefix is used.  */
9800   if ((ins.prefixes & PREFIX_DATA) != 0
9801       && (ins.used_prefixes & PREFIX_DATA) != 0
9802       && !ins.need_vex)
9803     ins.all_prefixes[ins.last_data_prefix] = 0;
9804
9805   /* Print the extra ins.prefixes.  */
9806   prefix_length = 0;
9807   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9808     if (ins.all_prefixes[i])
9809       {
9810         const char *name;
9811         name = prefix_name (&ins, ins.all_prefixes[i], orig_sizeflag);
9812         if (name == NULL)
9813           abort ();
9814         prefix_length += strlen (name) + 1;
9815         i386_dis_printf (&ins, dis_style_mnemonic, "%s ", name);
9816       }
9817
9818   /* Check maximum code length.  */
9819   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9820     {
9821       i386_dis_printf (&ins, dis_style_text, "(bad)");
9822       return MAX_CODE_LENGTH;
9823     }
9824
9825   /* Calculate the number of operands this instruction has.  */
9826   op_count = 0;
9827   for (i = 0; i < MAX_OPERANDS; ++i)
9828     if (*ins.op_out[i] != '\0')
9829       ++op_count;
9830
9831   /* Calculate the number of spaces to print after the mnemonic.  */
9832   ins.obufp = ins.mnemonicendp;
9833   if (op_count > 0)
9834     {
9835       i = strlen (ins.obuf) + prefix_length;
9836       if (i < 7)
9837         i = 7 - i;
9838       else
9839         i = 1;
9840     }
9841   else
9842     i = 0;
9843
9844   /* Print the instruction mnemonic along with any trailing whitespace.  */
9845   i386_dis_printf (&ins, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9846
9847   /* The enter and bound instructions are printed with operands in the same
9848      order as the intel book; everything else is printed in reverse order.  */
9849   intel_swap_2_3 = false;
9850   if (ins.intel_syntax || ins.two_source_ops)
9851     {
9852       for (i = 0; i < MAX_OPERANDS; ++i)
9853         op_txt[i] = ins.op_out[i];
9854
9855       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9856           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9857         {
9858           op_txt[2] = ins.op_out[3];
9859           op_txt[3] = ins.op_out[2];
9860           intel_swap_2_3 = true;
9861         }
9862
9863       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9864         {
9865           bool riprel;
9866
9867           ins.op_ad = ins.op_index[i];
9868           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9869           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9870           riprel = ins.op_riprel[i];
9871           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9872           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9873         }
9874     }
9875   else
9876     {
9877       for (i = 0; i < MAX_OPERANDS; ++i)
9878         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9879     }
9880
9881   needcomma = 0;
9882   for (i = 0; i < MAX_OPERANDS; ++i)
9883     if (*op_txt[i])
9884       {
9885         /* In Intel syntax embedded rounding / SAE are not separate operands.
9886            Instead they're attached to the prior register operand.  Simply
9887            suppress emission of the comma to achieve that effect.  */
9888         switch (i & -(ins.intel_syntax && dp))
9889           {
9890           case 2:
9891             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9892               needcomma = 0;
9893             break;
9894           case 3:
9895             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9896               needcomma = 0;
9897             break;
9898           }
9899         if (needcomma)
9900           i386_dis_printf (&ins, dis_style_text, ",");
9901         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9902           {
9903             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9904
9905             if (ins.op_is_jump)
9906               {
9907                 info->insn_info_valid = 1;
9908                 info->branch_delay_insns = 0;
9909                 info->data_size = 0;
9910                 info->target = target;
9911                 info->target2 = 0;
9912               }
9913             (*info->print_address_func) (target, info);
9914           }
9915         else
9916           i386_dis_printf (&ins, dis_style_text, "%s", op_txt[i]);
9917         needcomma = 1;
9918       }
9919
9920   for (i = 0; i < MAX_OPERANDS; i++)
9921     if (ins.op_index[i] != -1 && ins.op_riprel[i])
9922       {
9923         i386_dis_printf (&ins, dis_style_comment_start, "        # ");
9924         (*info->print_address_func)
9925           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9926                      + ins.op_address[ins.op_index[i]]),
9927           info);
9928         break;
9929       }
9930   return ins.codep - priv.the_buffer;
9931 }
9932
9933 /* Here for backwards compatibility.  When gdb stops using
9934    print_insn_i386_att and print_insn_i386_intel these functions can
9935    disappear, and print_insn_i386 be merged into print_insn.  */
9936 int
9937 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9938 {
9939   return print_insn (pc, info, 0);
9940 }
9941
9942 int
9943 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9944 {
9945   return print_insn (pc, info, 1);
9946 }
9947
9948 int
9949 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9950 {
9951   return print_insn (pc, info, -1);
9952 }
9953
9954 static const char *float_mem[] = {
9955   /* d8 */
9956   "fadd{s|}",
9957   "fmul{s|}",
9958   "fcom{s|}",
9959   "fcomp{s|}",
9960   "fsub{s|}",
9961   "fsubr{s|}",
9962   "fdiv{s|}",
9963   "fdivr{s|}",
9964   /* d9 */
9965   "fld{s|}",
9966   "(bad)",
9967   "fst{s|}",
9968   "fstp{s|}",
9969   "fldenv{C|C}",
9970   "fldcw",
9971   "fNstenv{C|C}",
9972   "fNstcw",
9973   /* da */
9974   "fiadd{l|}",
9975   "fimul{l|}",
9976   "ficom{l|}",
9977   "ficomp{l|}",
9978   "fisub{l|}",
9979   "fisubr{l|}",
9980   "fidiv{l|}",
9981   "fidivr{l|}",
9982   /* db */
9983   "fild{l|}",
9984   "fisttp{l|}",
9985   "fist{l|}",
9986   "fistp{l|}",
9987   "(bad)",
9988   "fld{t|}",
9989   "(bad)",
9990   "fstp{t|}",
9991   /* dc */
9992   "fadd{l|}",
9993   "fmul{l|}",
9994   "fcom{l|}",
9995   "fcomp{l|}",
9996   "fsub{l|}",
9997   "fsubr{l|}",
9998   "fdiv{l|}",
9999   "fdivr{l|}",
10000   /* dd */
10001   "fld{l|}",
10002   "fisttp{ll|}",
10003   "fst{l||}",
10004   "fstp{l|}",
10005   "frstor{C|C}",
10006   "(bad)",
10007   "fNsave{C|C}",
10008   "fNstsw",
10009   /* de */
10010   "fiadd{s|}",
10011   "fimul{s|}",
10012   "ficom{s|}",
10013   "ficomp{s|}",
10014   "fisub{s|}",
10015   "fisubr{s|}",
10016   "fidiv{s|}",
10017   "fidivr{s|}",
10018   /* df */
10019   "fild{s|}",
10020   "fisttp{s|}",
10021   "fist{s|}",
10022   "fistp{s|}",
10023   "fbld",
10024   "fild{ll|}",
10025   "fbstp",
10026   "fistp{ll|}",
10027 };
10028
10029 static const unsigned char float_mem_mode[] = {
10030   /* d8 */
10031   d_mode,
10032   d_mode,
10033   d_mode,
10034   d_mode,
10035   d_mode,
10036   d_mode,
10037   d_mode,
10038   d_mode,
10039   /* d9 */
10040   d_mode,
10041   0,
10042   d_mode,
10043   d_mode,
10044   0,
10045   w_mode,
10046   0,
10047   w_mode,
10048   /* da */
10049   d_mode,
10050   d_mode,
10051   d_mode,
10052   d_mode,
10053   d_mode,
10054   d_mode,
10055   d_mode,
10056   d_mode,
10057   /* db */
10058   d_mode,
10059   d_mode,
10060   d_mode,
10061   d_mode,
10062   0,
10063   t_mode,
10064   0,
10065   t_mode,
10066   /* dc */
10067   q_mode,
10068   q_mode,
10069   q_mode,
10070   q_mode,
10071   q_mode,
10072   q_mode,
10073   q_mode,
10074   q_mode,
10075   /* dd */
10076   q_mode,
10077   q_mode,
10078   q_mode,
10079   q_mode,
10080   0,
10081   0,
10082   0,
10083   w_mode,
10084   /* de */
10085   w_mode,
10086   w_mode,
10087   w_mode,
10088   w_mode,
10089   w_mode,
10090   w_mode,
10091   w_mode,
10092   w_mode,
10093   /* df */
10094   w_mode,
10095   w_mode,
10096   w_mode,
10097   w_mode,
10098   t_mode,
10099   q_mode,
10100   t_mode,
10101   q_mode
10102 };
10103
10104 #define ST { OP_ST, 0 }
10105 #define STi { OP_STi, 0 }
10106
10107 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10108 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10109 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10110 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10111 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10112 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10113 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10114 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10115 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10116
10117 static const struct dis386 float_reg[][8] = {
10118   /* d8 */
10119   {
10120     { "fadd",   { ST, STi }, 0 },
10121     { "fmul",   { ST, STi }, 0 },
10122     { "fcom",   { STi }, 0 },
10123     { "fcomp",  { STi }, 0 },
10124     { "fsub",   { ST, STi }, 0 },
10125     { "fsubr",  { ST, STi }, 0 },
10126     { "fdiv",   { ST, STi }, 0 },
10127     { "fdivr",  { ST, STi }, 0 },
10128   },
10129   /* d9 */
10130   {
10131     { "fld",    { STi }, 0 },
10132     { "fxch",   { STi }, 0 },
10133     { FGRPd9_2 },
10134     { Bad_Opcode },
10135     { FGRPd9_4 },
10136     { FGRPd9_5 },
10137     { FGRPd9_6 },
10138     { FGRPd9_7 },
10139   },
10140   /* da */
10141   {
10142     { "fcmovb", { ST, STi }, 0 },
10143     { "fcmove", { ST, STi }, 0 },
10144     { "fcmovbe",{ ST, STi }, 0 },
10145     { "fcmovu", { ST, STi }, 0 },
10146     { Bad_Opcode },
10147     { FGRPda_5 },
10148     { Bad_Opcode },
10149     { Bad_Opcode },
10150   },
10151   /* db */
10152   {
10153     { "fcmovnb",{ ST, STi }, 0 },
10154     { "fcmovne",{ ST, STi }, 0 },
10155     { "fcmovnbe",{ ST, STi }, 0 },
10156     { "fcmovnu",{ ST, STi }, 0 },
10157     { FGRPdb_4 },
10158     { "fucomi", { ST, STi }, 0 },
10159     { "fcomi",  { ST, STi }, 0 },
10160     { Bad_Opcode },
10161   },
10162   /* dc */
10163   {
10164     { "fadd",   { STi, ST }, 0 },
10165     { "fmul",   { STi, ST }, 0 },
10166     { Bad_Opcode },
10167     { Bad_Opcode },
10168     { "fsub{!M|r}",     { STi, ST }, 0 },
10169     { "fsub{M|}",       { STi, ST }, 0 },
10170     { "fdiv{!M|r}",     { STi, ST }, 0 },
10171     { "fdiv{M|}",       { STi, ST }, 0 },
10172   },
10173   /* dd */
10174   {
10175     { "ffree",  { STi }, 0 },
10176     { Bad_Opcode },
10177     { "fst",    { STi }, 0 },
10178     { "fstp",   { STi }, 0 },
10179     { "fucom",  { STi }, 0 },
10180     { "fucomp", { STi }, 0 },
10181     { Bad_Opcode },
10182     { Bad_Opcode },
10183   },
10184   /* de */
10185   {
10186     { "faddp",  { STi, ST }, 0 },
10187     { "fmulp",  { STi, ST }, 0 },
10188     { Bad_Opcode },
10189     { FGRPde_3 },
10190     { "fsub{!M|r}p",    { STi, ST }, 0 },
10191     { "fsub{M|}p",      { STi, ST }, 0 },
10192     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10193     { "fdiv{M|}p",      { STi, ST }, 0 },
10194   },
10195   /* df */
10196   {
10197     { "ffreep", { STi }, 0 },
10198     { Bad_Opcode },
10199     { Bad_Opcode },
10200     { Bad_Opcode },
10201     { FGRPdf_4 },
10202     { "fucomip", { ST, STi }, 0 },
10203     { "fcomip", { ST, STi }, 0 },
10204     { Bad_Opcode },
10205   },
10206 };
10207
10208 static const char *const fgrps[][8] = {
10209   /* Bad opcode 0 */
10210   {
10211     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10212   },
10213
10214   /* d9_2  1 */
10215   {
10216     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10217   },
10218
10219   /* d9_4  2 */
10220   {
10221     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10222   },
10223
10224   /* d9_5  3 */
10225   {
10226     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10227   },
10228
10229   /* d9_6  4 */
10230   {
10231     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10232   },
10233
10234   /* d9_7  5 */
10235   {
10236     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10237   },
10238
10239   /* da_5  6 */
10240   {
10241     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10242   },
10243
10244   /* db_4  7 */
10245   {
10246     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10247     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10248   },
10249
10250   /* de_3  8 */
10251   {
10252     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10253   },
10254
10255   /* df_4  9 */
10256   {
10257     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10258   },
10259 };
10260
10261 static void
10262 swap_operand (instr_info *ins)
10263 {
10264   ins->mnemonicendp[0] = '.';
10265   ins->mnemonicendp[1] = 's';
10266   ins->mnemonicendp[2] = '\0';
10267   ins->mnemonicendp += 2;
10268 }
10269
10270 static void
10271 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10272                int sizeflag ATTRIBUTE_UNUSED)
10273 {
10274   /* Skip mod/rm byte.  */
10275   MODRM_CHECK;
10276   ins->codep++;
10277 }
10278
10279 static void
10280 dofloat (instr_info *ins, int sizeflag)
10281 {
10282   const struct dis386 *dp;
10283   unsigned char floatop;
10284
10285   floatop = ins->codep[-1];
10286
10287   if (ins->modrm.mod != 3)
10288     {
10289       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10290
10291       putop (ins, float_mem[fp_indx], sizeflag);
10292       ins->obufp = ins->op_out[0];
10293       ins->op_ad = 2;
10294       OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10295       return;
10296     }
10297   /* Skip mod/rm byte.  */
10298   MODRM_CHECK;
10299   ins->codep++;
10300
10301   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10302   if (dp->name == NULL)
10303     {
10304       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10305
10306       /* Instruction fnstsw is only one with strange arg.  */
10307       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10308         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10309     }
10310   else
10311     {
10312       putop (ins, dp->name, sizeflag);
10313
10314       ins->obufp = ins->op_out[0];
10315       ins->op_ad = 2;
10316       if (dp->op[0].rtn)
10317         (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10318
10319       ins->obufp = ins->op_out[1];
10320       ins->op_ad = 1;
10321       if (dp->op[1].rtn)
10322         (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10323     }
10324 }
10325
10326 static void
10327 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10328        int sizeflag ATTRIBUTE_UNUSED)
10329 {
10330   oappend_register (ins, "%st");
10331 }
10332
10333 static void
10334 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10335         int sizeflag ATTRIBUTE_UNUSED)
10336 {
10337   char scratch[8];
10338   int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10339
10340   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10341     abort ();
10342   oappend_register (ins, scratch);
10343 }
10344
10345 /* Capital letters in template are macros.  */
10346 static int
10347 putop (instr_info *ins, const char *in_template, int sizeflag)
10348 {
10349   const char *p;
10350   int alt = 0;
10351   int cond = 1;
10352   unsigned int l = 0, len = 0;
10353   char last[4];
10354
10355   for (p = in_template; *p; p++)
10356     {
10357       if (len > l)
10358         {
10359           if (l >= sizeof (last) || !ISUPPER (*p))
10360             abort ();
10361           last[l++] = *p;
10362           continue;
10363         }
10364       switch (*p)
10365         {
10366         default:
10367           *ins->obufp++ = *p;
10368           break;
10369         case '%':
10370           len++;
10371           break;
10372         case '!':
10373           cond = 0;
10374           break;
10375         case '{':
10376           if (ins->intel_syntax)
10377             {
10378               while (*++p != '|')
10379                 if (*p == '}' || *p == '\0')
10380                   abort ();
10381               alt = 1;
10382             }
10383           break;
10384         case '|':
10385           while (*++p != '}')
10386             {
10387               if (*p == '\0')
10388                 abort ();
10389             }
10390           break;
10391         case '}':
10392           alt = 0;
10393           break;
10394         case 'A':
10395           if (ins->intel_syntax)
10396             break;
10397           if ((ins->need_modrm && ins->modrm.mod != 3)
10398               || (sizeflag & SUFFIX_ALWAYS))
10399             *ins->obufp++ = 'b';
10400           break;
10401         case 'B':
10402           if (l == 0)
10403             {
10404             case_B:
10405               if (ins->intel_syntax)
10406                 break;
10407               if (sizeflag & SUFFIX_ALWAYS)
10408                 *ins->obufp++ = 'b';
10409             }
10410           else if (l == 1 && last[0] == 'L')
10411             {
10412               if (ins->address_mode == mode_64bit
10413                   && !(ins->prefixes & PREFIX_ADDR))
10414                 {
10415                   *ins->obufp++ = 'a';
10416                   *ins->obufp++ = 'b';
10417                   *ins->obufp++ = 's';
10418                 }
10419
10420               goto case_B;
10421             }
10422           else
10423             abort ();
10424           break;
10425         case 'C':
10426           if (ins->intel_syntax && !alt)
10427             break;
10428           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10429             {
10430               if (sizeflag & DFLAG)
10431                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10432               else
10433                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10434               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10435             }
10436           break;
10437         case 'D':
10438           if (l == 1)
10439             {
10440               switch (last[0])
10441               {
10442               case 'X':
10443                 if (!ins->vex.evex || ins->vex.w)
10444                   *ins->obufp++ = 'd';
10445                 else
10446                   oappend (ins, "{bad}");
10447                 break;
10448               default:
10449                 abort ();
10450               }
10451               break;
10452             }
10453           if (l)
10454             abort ();
10455           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10456             break;
10457           USED_REX (REX_W);
10458           if (ins->modrm.mod == 3)
10459             {
10460               if (ins->rex & REX_W)
10461                 *ins->obufp++ = 'q';
10462               else
10463                 {
10464                   if (sizeflag & DFLAG)
10465                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10466                   else
10467                     *ins->obufp++ = 'w';
10468                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10469                 }
10470             }
10471           else
10472             *ins->obufp++ = 'w';
10473           break;
10474         case 'E':
10475           if (l == 1)
10476             {
10477               switch (last[0])
10478                 {
10479                 case 'X':
10480                   if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10481                       || !ins->vex.r
10482                       || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10483                       || !ins->vex.v || ins->vex.mask_register_specifier)
10484                     break;
10485                   /* AVX512 extends a number of V*D insns to also have V*Q variants,
10486                      merely distinguished by EVEX.W.  Look for a use of the
10487                      respective macro.  */
10488                   if (ins->vex.w)
10489                     {
10490                       const char *pct = strchr (p + 1, '%');
10491
10492                       if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10493                         break;
10494                     }
10495                   *ins->obufp++ = '{';
10496                   *ins->obufp++ = 'e';
10497                   *ins->obufp++ = 'v';
10498                   *ins->obufp++ = 'e';
10499                   *ins->obufp++ = 'x';
10500                   *ins->obufp++ = '}';
10501                   *ins->obufp++ = ' ';
10502                   break;
10503                 default:
10504                   abort ();
10505                 }
10506                 break;
10507             }
10508           /* For jcxz/jecxz */
10509           if (ins->address_mode == mode_64bit)
10510             {
10511               if (sizeflag & AFLAG)
10512                 *ins->obufp++ = 'r';
10513               else
10514                 *ins->obufp++ = 'e';
10515             }
10516           else
10517             if (sizeflag & AFLAG)
10518               *ins->obufp++ = 'e';
10519           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10520           break;
10521         case 'F':
10522           if (ins->intel_syntax)
10523             break;
10524           if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10525             {
10526               if (sizeflag & AFLAG)
10527                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10528               else
10529                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10530               ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10531             }
10532           break;
10533         case 'G':
10534           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10535                                     && !(sizeflag & SUFFIX_ALWAYS)))
10536             break;
10537           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10538             *ins->obufp++ = 'l';
10539           else
10540             *ins->obufp++ = 'w';
10541           if (!(ins->rex & REX_W))
10542             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10543           break;
10544         case 'H':
10545           if (l == 0)
10546             {
10547               if (ins->intel_syntax)
10548                 break;
10549               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10550                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10551                 {
10552                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10553                   *ins->obufp++ = ',';
10554                   *ins->obufp++ = 'p';
10555
10556                   /* Set active_seg_prefix even if not set in 64-bit mode
10557                      because here it is a valid branch hint. */
10558                   if (ins->prefixes & PREFIX_DS)
10559                     {
10560                       ins->active_seg_prefix = PREFIX_DS;
10561                       *ins->obufp++ = 't';
10562                     }
10563                   else
10564                     {
10565                       ins->active_seg_prefix = PREFIX_CS;
10566                       *ins->obufp++ = 'n';
10567                     }
10568                 }
10569             }
10570           else if (l == 1 && last[0] == 'X')
10571             {
10572               if (!ins->vex.w)
10573                 *ins->obufp++ = 'h';
10574               else
10575                 oappend (ins, "{bad}");
10576             }
10577           else
10578             abort ();
10579           break;
10580         case 'K':
10581           USED_REX (REX_W);
10582           if (ins->rex & REX_W)
10583             *ins->obufp++ = 'q';
10584           else
10585             *ins->obufp++ = 'd';
10586           break;
10587         case 'L':
10588           abort ();
10589         case 'M':
10590           if (ins->intel_mnemonic != cond)
10591             *ins->obufp++ = 'r';
10592           break;
10593         case 'N':
10594           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10595             *ins->obufp++ = 'n';
10596           else
10597             ins->used_prefixes |= PREFIX_FWAIT;
10598           break;
10599         case 'O':
10600           USED_REX (REX_W);
10601           if (ins->rex & REX_W)
10602             *ins->obufp++ = 'o';
10603           else if (ins->intel_syntax && (sizeflag & DFLAG))
10604             *ins->obufp++ = 'q';
10605           else
10606             *ins->obufp++ = 'd';
10607           if (!(ins->rex & REX_W))
10608             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10609           break;
10610         case '@':
10611           if (ins->address_mode == mode_64bit
10612               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10613                   || !(ins->prefixes & PREFIX_DATA)))
10614             {
10615               if (sizeflag & SUFFIX_ALWAYS)
10616                 *ins->obufp++ = 'q';
10617               break;
10618             }
10619           /* Fall through.  */
10620         case 'P':
10621           if (l == 0)
10622             {
10623               if ((ins->modrm.mod == 3 || !cond)
10624                   && !(sizeflag & SUFFIX_ALWAYS))
10625                 break;
10626           /* Fall through.  */
10627         case 'T':
10628               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10629                   || ((sizeflag & SUFFIX_ALWAYS)
10630                       && ins->address_mode != mode_64bit))
10631                 {
10632                   *ins->obufp++ = (sizeflag & DFLAG)
10633                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10634                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10635                 }
10636               else if (sizeflag & SUFFIX_ALWAYS)
10637                 *ins->obufp++ = 'q';
10638             }
10639           else if (l == 1 && last[0] == 'L')
10640             {
10641               if ((ins->prefixes & PREFIX_DATA)
10642                   || (ins->rex & REX_W)
10643                   || (sizeflag & SUFFIX_ALWAYS))
10644                 {
10645                   USED_REX (REX_W);
10646                   if (ins->rex & REX_W)
10647                     *ins->obufp++ = 'q';
10648                   else
10649                     {
10650                       if (sizeflag & DFLAG)
10651                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10652                       else
10653                         *ins->obufp++ = 'w';
10654                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10655                     }
10656                 }
10657             }
10658           else
10659             abort ();
10660           break;
10661         case 'Q':
10662           if (l == 0)
10663             {
10664               if (ins->intel_syntax && !alt)
10665                 break;
10666               USED_REX (REX_W);
10667               if ((ins->need_modrm && ins->modrm.mod != 3)
10668                   || (sizeflag & SUFFIX_ALWAYS))
10669                 {
10670                   if (ins->rex & REX_W)
10671                     *ins->obufp++ = 'q';
10672                   else
10673                     {
10674                       if (sizeflag & DFLAG)
10675                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10676                       else
10677                         *ins->obufp++ = 'w';
10678                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10679                     }
10680                 }
10681             }
10682           else if (l == 1 && last[0] == 'D')
10683             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10684           else if (l == 1 && last[0] == 'L')
10685             {
10686               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10687                        : ins->address_mode != mode_64bit)
10688                 break;
10689               if ((ins->rex & REX_W))
10690                 {
10691                   USED_REX (REX_W);
10692                   *ins->obufp++ = 'q';
10693                 }
10694               else if ((ins->address_mode == mode_64bit && cond)
10695                       || (sizeflag & SUFFIX_ALWAYS))
10696                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10697             }
10698           else
10699             abort ();
10700           break;
10701         case 'R':
10702           USED_REX (REX_W);
10703           if (ins->rex & REX_W)
10704             *ins->obufp++ = 'q';
10705           else if (sizeflag & DFLAG)
10706             {
10707               if (ins->intel_syntax)
10708                   *ins->obufp++ = 'd';
10709               else
10710                   *ins->obufp++ = 'l';
10711             }
10712           else
10713             *ins->obufp++ = 'w';
10714           if (ins->intel_syntax && !p[1]
10715               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10716             *ins->obufp++ = 'e';
10717           if (!(ins->rex & REX_W))
10718             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10719           break;
10720         case 'S':
10721           if (l == 0)
10722             {
10723             case_S:
10724               if (ins->intel_syntax)
10725                 break;
10726               if (sizeflag & SUFFIX_ALWAYS)
10727                 {
10728                   if (ins->rex & REX_W)
10729                     *ins->obufp++ = 'q';
10730                   else
10731                     {
10732                       if (sizeflag & DFLAG)
10733                         *ins->obufp++ = 'l';
10734                       else
10735                         *ins->obufp++ = 'w';
10736                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10737                     }
10738                 }
10739               break;
10740             }
10741           if (l != 1)
10742             abort ();
10743           switch (last[0])
10744             {
10745             case 'L':
10746               if (ins->address_mode == mode_64bit
10747                   && !(ins->prefixes & PREFIX_ADDR))
10748                 {
10749                   *ins->obufp++ = 'a';
10750                   *ins->obufp++ = 'b';
10751                   *ins->obufp++ = 's';
10752                 }
10753
10754               goto case_S;
10755             case 'X':
10756               if (!ins->vex.evex || !ins->vex.w)
10757                 *ins->obufp++ = 's';
10758               else
10759                 oappend (ins, "{bad}");
10760               break;
10761             default:
10762               abort ();
10763             }
10764           break;
10765         case 'V':
10766           if (l == 0)
10767             abort ();
10768           else if (l == 1)
10769             {
10770               switch (last[0])
10771                 {
10772                 case 'X':
10773                   if (ins->vex.evex)
10774                     break;
10775                   *ins->obufp++ = '{';
10776                   *ins->obufp++ = 'v';
10777                   *ins->obufp++ = 'e';
10778                   *ins->obufp++ = 'x';
10779                   *ins->obufp++ = '}';
10780                   *ins->obufp++ = ' ';
10781                   break;
10782                 case 'L':
10783                   if (!(ins->rex & REX_W))
10784                     break;
10785                   *ins->obufp++ = 'a';
10786                   *ins->obufp++ = 'b';
10787                   *ins->obufp++ = 's';
10788                   break;
10789                 default:
10790                   abort ();
10791                 }
10792             }
10793           else
10794             abort ();
10795           goto case_S;
10796         case 'W':
10797           if (l == 0)
10798             {
10799               /* operand size flag for cwtl, cbtw */
10800               USED_REX (REX_W);
10801               if (ins->rex & REX_W)
10802                 {
10803                   if (ins->intel_syntax)
10804                     *ins->obufp++ = 'd';
10805                   else
10806                     *ins->obufp++ = 'l';
10807                 }
10808               else if (sizeflag & DFLAG)
10809                 *ins->obufp++ = 'w';
10810               else
10811                 *ins->obufp++ = 'b';
10812               if (!(ins->rex & REX_W))
10813                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10814             }
10815           else if (l == 1)
10816             {
10817               if (!ins->need_vex)
10818                 abort ();
10819               if (last[0] == 'X')
10820                 *ins->obufp++ = ins->vex.w ? 'd': 's';
10821               else if (last[0] == 'B')
10822                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10823               else
10824                 abort ();
10825             }
10826           else
10827             abort ();
10828           break;
10829         case 'X':
10830           if (l != 0)
10831             abort ();
10832           if (ins->need_vex
10833               ? ins->vex.prefix == DATA_PREFIX_OPCODE
10834               : ins->prefixes & PREFIX_DATA)
10835             {
10836               *ins->obufp++ = 'd';
10837               ins->used_prefixes |= PREFIX_DATA;
10838             }
10839           else
10840             *ins->obufp++ = 's';
10841           break;
10842         case 'Y':
10843           if (l == 1 && last[0] == 'X')
10844             {
10845               if (!ins->need_vex)
10846                 abort ();
10847               if (ins->intel_syntax
10848                   || ((ins->modrm.mod == 3 || ins->vex.b)
10849                       && !(sizeflag & SUFFIX_ALWAYS)))
10850                 break;
10851               switch (ins->vex.length)
10852                 {
10853                 case 128:
10854                   *ins->obufp++ = 'x';
10855                   break;
10856                 case 256:
10857                   *ins->obufp++ = 'y';
10858                   break;
10859                 case 512:
10860                   if (!ins->vex.evex)
10861                 default:
10862                     abort ();
10863                 }
10864             }
10865           else
10866             abort ();
10867           break;
10868         case 'Z':
10869           if (l == 0)
10870             {
10871               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10872               ins->modrm.mod = 3;
10873               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10874                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10875             }
10876           else if (l == 1 && last[0] == 'X')
10877             {
10878               if (!ins->vex.evex)
10879                 abort ();
10880               if (ins->intel_syntax
10881                   || ((ins->modrm.mod == 3 || ins->vex.b)
10882                       && !(sizeflag & SUFFIX_ALWAYS)))
10883                 break;
10884               switch (ins->vex.length)
10885                 {
10886                 case 128:
10887                   *ins->obufp++ = 'x';
10888                   break;
10889                 case 256:
10890                   *ins->obufp++ = 'y';
10891                   break;
10892                 case 512:
10893                   *ins->obufp++ = 'z';
10894                   break;
10895                 default:
10896                   abort ();
10897                 }
10898             }
10899           else
10900             abort ();
10901           break;
10902         case '^':
10903           if (ins->intel_syntax)
10904             break;
10905           if (ins->isa64 == intel64 && (ins->rex & REX_W))
10906             {
10907               USED_REX (REX_W);
10908               *ins->obufp++ = 'q';
10909               break;
10910             }
10911           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10912             {
10913               if (sizeflag & DFLAG)
10914                 *ins->obufp++ = 'l';
10915               else
10916                 *ins->obufp++ = 'w';
10917               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10918             }
10919           break;
10920         }
10921
10922       if (len == l)
10923         len = l = 0;
10924     }
10925   *ins->obufp = 0;
10926   ins->mnemonicendp = ins->obufp;
10927   return 0;
10928 }
10929
10930 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
10931    the buffer pointed to by INS->obufp has space.  A style marker is made
10932    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
10933    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
10934    that the number of styles is not greater than 16.  */
10935
10936 static void
10937 oappend_insert_style (instr_info *ins, enum disassembler_style style)
10938 {
10939   unsigned num = (unsigned) style;
10940
10941   /* We currently assume that STYLE can be encoded as a single hex
10942      character.  If more styles are added then this might start to fail,
10943      and we'll need to expand this code.  */
10944   if (num > 0xf)
10945     abort ();
10946
10947   *ins->obufp++ = STYLE_MARKER_CHAR;
10948   *ins->obufp++ = (num < 10 ? ('0' + num)
10949                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
10950   *ins->obufp++ = STYLE_MARKER_CHAR;
10951
10952   /* This final null character is not strictly necessary, after inserting a
10953      style marker we should always be inserting some additional content.
10954      However, having the buffer null terminated doesn't cost much, and make
10955      it easier to debug what's going on.  Also, if we do ever forget to add
10956      any additional content after this style marker, then the buffer will
10957      still be well formed.  */
10958   *ins->obufp = '\0';
10959 }
10960
10961 static void
10962 oappend_with_style (instr_info *ins, const char *s,
10963                     enum disassembler_style style)
10964 {
10965   oappend_insert_style (ins, style);
10966   ins->obufp = stpcpy (ins->obufp, s);
10967 }
10968
10969 /* Like oappend_with_style but always with text style.  */
10970
10971 static void
10972 oappend (instr_info *ins, const char *s)
10973 {
10974   oappend_with_style (ins, s, dis_style_text);
10975 }
10976
10977 /* Add a single character C to the buffer pointer to by INS->obufp, marking
10978    the style for the character as STYLE.  */
10979
10980 static void
10981 oappend_char_with_style (instr_info *ins, const char c,
10982                          enum disassembler_style style)
10983 {
10984   oappend_insert_style (ins, style);
10985   *ins->obufp++ = c;
10986   *ins->obufp = '\0';
10987 }
10988
10989 /* Like oappend_char_with_style, but always uses dis_style_text.  */
10990
10991 static void
10992 oappend_char (instr_info *ins, const char c)
10993 {
10994   oappend_char_with_style (ins, c, dis_style_text);
10995 }
10996
10997 static void
10998 append_seg (instr_info *ins)
10999 {
11000   /* Only print the active segment register.  */
11001   if (!ins->active_seg_prefix)
11002     return;
11003
11004   ins->used_prefixes |= ins->active_seg_prefix;
11005   switch (ins->active_seg_prefix)
11006     {
11007     case PREFIX_CS:
11008       oappend_register (ins, "%cs");
11009       break;
11010     case PREFIX_DS:
11011       oappend_register (ins, "%ds");
11012       break;
11013     case PREFIX_SS:
11014       oappend_register (ins, "%ss");
11015       break;
11016     case PREFIX_ES:
11017       oappend_register (ins, "%es");
11018       break;
11019     case PREFIX_FS:
11020       oappend_register (ins, "%fs");
11021       break;
11022     case PREFIX_GS:
11023       oappend_register (ins, "%gs");
11024       break;
11025     default:
11026       break;
11027     }
11028   oappend_char (ins, ':');
11029 }
11030
11031 static void
11032 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
11033 {
11034   if (!ins->intel_syntax)
11035     oappend (ins, "*");
11036   OP_E (ins, bytemode, sizeflag);
11037 }
11038
11039 static void
11040 print_operand_value (instr_info *ins, bfd_vma disp,
11041                      enum disassembler_style style)
11042 {
11043   char tmp[30];
11044
11045   if (ins->address_mode == mode_64bit)
11046     sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11047   else
11048     sprintf (tmp, "0x%x", (unsigned int) disp);
11049   oappend_with_style (ins, tmp, style);
11050 }
11051
11052 /* Like oappend, but called for immediate operands.  */
11053
11054 static void
11055 oappend_immediate (instr_info *ins, bfd_vma imm)
11056 {
11057   if (!ins->intel_syntax)
11058     oappend_char_with_style (ins, '$', dis_style_immediate);
11059   print_operand_value (ins, imm, dis_style_immediate);
11060 }
11061
11062 /* Put DISP in BUF as signed hex number.  */
11063
11064 static void
11065 print_displacement (instr_info *ins, bfd_vma disp)
11066 {
11067   bfd_signed_vma val = disp;
11068   char tmp[30];
11069
11070   if (val < 0)
11071     {
11072       oappend_char_with_style (ins, '-', dis_style_address_offset);
11073       val = -disp;
11074
11075       /* Check for possible overflow.  */
11076       if (val < 0)
11077         {
11078           switch (ins->address_mode)
11079             {
11080             case mode_64bit:
11081               oappend_with_style (ins, "0x8000000000000000",
11082                                   dis_style_address_offset);
11083               break;
11084             case mode_32bit:
11085               oappend_with_style (ins, "0x80000000",
11086                                   dis_style_address_offset);
11087               break;
11088             case mode_16bit:
11089               oappend_with_style (ins, "0x8000",
11090                                   dis_style_address_offset);
11091               break;
11092             }
11093           return;
11094         }
11095     }
11096
11097   sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11098   oappend_with_style (ins, tmp, dis_style_address_offset);
11099 }
11100
11101 static void
11102 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11103 {
11104   if (ins->vex.b)
11105     {
11106       if (!ins->vex.no_broadcast)
11107         switch (bytemode)
11108           {
11109           case x_mode:
11110           case evex_half_bcst_xmmq_mode:
11111             if (ins->vex.w)
11112               oappend (ins, "QWORD BCST ");
11113             else
11114               oappend (ins, "DWORD BCST ");
11115             break;
11116           case xh_mode:
11117           case evex_half_bcst_xmmqh_mode:
11118           case evex_half_bcst_xmmqdh_mode:
11119             oappend (ins, "WORD BCST ");
11120             break;
11121           default:
11122             ins->vex.no_broadcast = true;
11123             break;
11124           }
11125       return;
11126     }
11127   switch (bytemode)
11128     {
11129     case b_mode:
11130     case b_swap_mode:
11131     case db_mode:
11132       oappend (ins, "BYTE PTR ");
11133       break;
11134     case w_mode:
11135     case w_swap_mode:
11136     case dw_mode:
11137       oappend (ins, "WORD PTR ");
11138       break;
11139     case indir_v_mode:
11140       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11141         {
11142           oappend (ins, "QWORD PTR ");
11143           break;
11144         }
11145       /* Fall through.  */
11146     case stack_v_mode:
11147       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11148                                               || (ins->rex & REX_W)))
11149         {
11150           oappend (ins, "QWORD PTR ");
11151           break;
11152         }
11153       /* Fall through.  */
11154     case v_mode:
11155     case v_swap_mode:
11156     case dq_mode:
11157       USED_REX (REX_W);
11158       if (ins->rex & REX_W)
11159         oappend (ins, "QWORD PTR ");
11160       else if (bytemode == dq_mode)
11161         oappend (ins, "DWORD PTR ");
11162       else
11163         {
11164           if (sizeflag & DFLAG)
11165             oappend (ins, "DWORD PTR ");
11166           else
11167             oappend (ins, "WORD PTR ");
11168           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11169         }
11170       break;
11171     case z_mode:
11172       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11173         *ins->obufp++ = 'D';
11174       oappend (ins, "WORD PTR ");
11175       if (!(ins->rex & REX_W))
11176         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11177       break;
11178     case a_mode:
11179       if (sizeflag & DFLAG)
11180         oappend (ins, "QWORD PTR ");
11181       else
11182         oappend (ins, "DWORD PTR ");
11183       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11184       break;
11185     case movsxd_mode:
11186       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11187         oappend (ins, "WORD PTR ");
11188       else
11189         oappend (ins, "DWORD PTR ");
11190       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11191       break;
11192     case d_mode:
11193     case d_swap_mode:
11194       oappend (ins, "DWORD PTR ");
11195       break;
11196     case q_mode:
11197     case q_swap_mode:
11198       oappend (ins, "QWORD PTR ");
11199       break;
11200     case m_mode:
11201       if (ins->address_mode == mode_64bit)
11202         oappend (ins, "QWORD PTR ");
11203       else
11204         oappend (ins, "DWORD PTR ");
11205       break;
11206     case f_mode:
11207       if (sizeflag & DFLAG)
11208         oappend (ins, "FWORD PTR ");
11209       else
11210         oappend (ins, "DWORD PTR ");
11211       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11212       break;
11213     case t_mode:
11214       oappend (ins, "TBYTE PTR ");
11215       break;
11216     case x_mode:
11217     case xh_mode:
11218     case x_swap_mode:
11219     case evex_x_gscat_mode:
11220     case evex_x_nobcst_mode:
11221     case bw_unit_mode:
11222       if (ins->need_vex)
11223         {
11224           switch (ins->vex.length)
11225             {
11226             case 128:
11227               oappend (ins, "XMMWORD PTR ");
11228               break;
11229             case 256:
11230               oappend (ins, "YMMWORD PTR ");
11231               break;
11232             case 512:
11233               oappend (ins, "ZMMWORD PTR ");
11234               break;
11235             default:
11236               abort ();
11237             }
11238         }
11239       else
11240         oappend (ins, "XMMWORD PTR ");
11241       break;
11242     case xmm_mode:
11243       oappend (ins, "XMMWORD PTR ");
11244       break;
11245     case ymm_mode:
11246       oappend (ins, "YMMWORD PTR ");
11247       break;
11248     case xmmq_mode:
11249     case evex_half_bcst_xmmqh_mode:
11250     case evex_half_bcst_xmmq_mode:
11251       if (!ins->need_vex)
11252         abort ();
11253
11254       switch (ins->vex.length)
11255         {
11256         case 128:
11257           oappend (ins, "QWORD PTR ");
11258           break;
11259         case 256:
11260           oappend (ins, "XMMWORD PTR ");
11261           break;
11262         case 512:
11263           oappend (ins, "YMMWORD PTR ");
11264           break;
11265         default:
11266           abort ();
11267         }
11268       break;
11269     case xmmdw_mode:
11270       if (!ins->need_vex)
11271         abort ();
11272
11273       switch (ins->vex.length)
11274         {
11275         case 128:
11276           oappend (ins, "WORD PTR ");
11277           break;
11278         case 256:
11279           oappend (ins, "DWORD PTR ");
11280           break;
11281         case 512:
11282           oappend (ins, "QWORD PTR ");
11283           break;
11284         default:
11285           abort ();
11286         }
11287       break;
11288     case xmmqd_mode:
11289     case evex_half_bcst_xmmqdh_mode:
11290       if (!ins->need_vex)
11291         abort ();
11292
11293       switch (ins->vex.length)
11294         {
11295         case 128:
11296           oappend (ins, "DWORD PTR ");
11297           break;
11298         case 256:
11299           oappend (ins, "QWORD PTR ");
11300           break;
11301         case 512:
11302           oappend (ins, "XMMWORD PTR ");
11303           break;
11304         default:
11305           abort ();
11306         }
11307       break;
11308     case ymmq_mode:
11309       if (!ins->need_vex)
11310         abort ();
11311
11312       switch (ins->vex.length)
11313         {
11314         case 128:
11315           oappend (ins, "QWORD PTR ");
11316           break;
11317         case 256:
11318           oappend (ins, "YMMWORD PTR ");
11319           break;
11320         case 512:
11321           oappend (ins, "ZMMWORD PTR ");
11322           break;
11323         default:
11324           abort ();
11325         }
11326       break;
11327     case o_mode:
11328       oappend (ins, "OWORD PTR ");
11329       break;
11330     case vex_vsib_d_w_dq_mode:
11331     case vex_vsib_q_w_dq_mode:
11332       if (!ins->need_vex)
11333         abort ();
11334       if (ins->vex.w)
11335         oappend (ins, "QWORD PTR ");
11336       else
11337         oappend (ins, "DWORD PTR ");
11338       break;
11339     case mask_bd_mode:
11340       if (!ins->need_vex || ins->vex.length != 128)
11341         abort ();
11342       if (ins->vex.w)
11343         oappend (ins, "DWORD PTR ");
11344       else
11345         oappend (ins, "BYTE PTR ");
11346       break;
11347     case mask_mode:
11348       if (!ins->need_vex)
11349         abort ();
11350       if (ins->vex.w)
11351         oappend (ins, "QWORD PTR ");
11352       else
11353         oappend (ins, "WORD PTR ");
11354       break;
11355     case v_bnd_mode:
11356     case v_bndmk_mode:
11357     default:
11358       break;
11359     }
11360 }
11361
11362 static void
11363 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11364                 int bytemode, int sizeflag)
11365 {
11366   const char *const *names;
11367
11368   USED_REX (rexmask);
11369   if (ins->rex & rexmask)
11370     reg += 8;
11371
11372   switch (bytemode)
11373     {
11374     case b_mode:
11375     case b_swap_mode:
11376       if (reg & 4)
11377         USED_REX (0);
11378       if (ins->rex)
11379         names = att_names8rex;
11380       else
11381         names = att_names8;
11382       break;
11383     case w_mode:
11384       names = att_names16;
11385       break;
11386     case d_mode:
11387     case dw_mode:
11388     case db_mode:
11389       names = att_names32;
11390       break;
11391     case q_mode:
11392       names = att_names64;
11393       break;
11394     case m_mode:
11395     case v_bnd_mode:
11396       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11397       break;
11398     case bnd_mode:
11399     case bnd_swap_mode:
11400       if (reg > 0x3)
11401         {
11402           oappend (ins, "(bad)");
11403           return;
11404         }
11405       names = att_names_bnd;
11406       break;
11407     case indir_v_mode:
11408       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11409         {
11410           names = att_names64;
11411           break;
11412         }
11413       /* Fall through.  */
11414     case stack_v_mode:
11415       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11416                                               || (ins->rex & REX_W)))
11417         {
11418           names = att_names64;
11419           break;
11420         }
11421       bytemode = v_mode;
11422       /* Fall through.  */
11423     case v_mode:
11424     case v_swap_mode:
11425     case dq_mode:
11426       USED_REX (REX_W);
11427       if (ins->rex & REX_W)
11428         names = att_names64;
11429       else if (bytemode != v_mode && bytemode != v_swap_mode)
11430         names = att_names32;
11431       else
11432         {
11433           if (sizeflag & DFLAG)
11434             names = att_names32;
11435           else
11436             names = att_names16;
11437           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11438         }
11439       break;
11440     case movsxd_mode:
11441       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11442         names = att_names16;
11443       else
11444         names = att_names32;
11445       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11446       break;
11447     case va_mode:
11448       names = (ins->address_mode == mode_64bit
11449                ? att_names64 : att_names32);
11450       if (!(ins->prefixes & PREFIX_ADDR))
11451         names = (ins->address_mode == mode_16bit
11452                      ? att_names16 : names);
11453       else
11454         {
11455           /* Remove "addr16/addr32".  */
11456           ins->all_prefixes[ins->last_addr_prefix] = 0;
11457           names = (ins->address_mode != mode_32bit
11458                        ? att_names32 : att_names16);
11459           ins->used_prefixes |= PREFIX_ADDR;
11460         }
11461       break;
11462     case mask_bd_mode:
11463     case mask_mode:
11464       if (reg > 0x7)
11465         {
11466           oappend (ins, "(bad)");
11467           return;
11468         }
11469       names = att_names_mask;
11470       break;
11471     case 0:
11472       return;
11473     default:
11474       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11475       return;
11476     }
11477   oappend_register (ins, names[reg]);
11478 }
11479
11480 static void
11481 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11482 {
11483   bfd_vma disp = 0;
11484   int add = (ins->rex & REX_B) ? 8 : 0;
11485   int riprel = 0;
11486   int shift;
11487
11488   if (ins->vex.evex)
11489     {
11490       switch (bytemode)
11491         {
11492         case dw_mode:
11493         case w_mode:
11494         case w_swap_mode:
11495           shift = 1;
11496           break;
11497         case db_mode:
11498         case b_mode:
11499           shift = 0;
11500           break;
11501         case dq_mode:
11502           if (ins->address_mode != mode_64bit)
11503             {
11504         case d_mode:
11505         case d_swap_mode:
11506               shift = 2;
11507               break;
11508             }
11509             /* fall through */
11510         case vex_vsib_d_w_dq_mode:
11511         case vex_vsib_q_w_dq_mode:
11512         case evex_x_gscat_mode:
11513           shift = ins->vex.w ? 3 : 2;
11514           break;
11515         case xh_mode:
11516         case evex_half_bcst_xmmqh_mode:
11517         case evex_half_bcst_xmmqdh_mode:
11518           if (ins->vex.b)
11519             {
11520               shift = ins->vex.w ? 2 : 1;
11521               break;
11522             }
11523           /* Fall through.  */
11524         case x_mode:
11525         case evex_half_bcst_xmmq_mode:
11526           if (ins->vex.b)
11527             {
11528               shift = ins->vex.w ? 3 : 2;
11529               break;
11530             }
11531           /* Fall through.  */
11532         case xmmqd_mode:
11533         case xmmdw_mode:
11534         case xmmq_mode:
11535         case ymmq_mode:
11536         case evex_x_nobcst_mode:
11537         case x_swap_mode:
11538           switch (ins->vex.length)
11539             {
11540             case 128:
11541               shift = 4;
11542               break;
11543             case 256:
11544               shift = 5;
11545               break;
11546             case 512:
11547               shift = 6;
11548               break;
11549             default:
11550               abort ();
11551             }
11552           /* Make necessary corrections to shift for modes that need it.  */
11553           if (bytemode == xmmq_mode
11554               || bytemode == evex_half_bcst_xmmqh_mode
11555               || bytemode == evex_half_bcst_xmmq_mode
11556               || (bytemode == ymmq_mode && ins->vex.length == 128))
11557             shift -= 1;
11558           else if (bytemode == xmmqd_mode
11559                    || bytemode == evex_half_bcst_xmmqdh_mode)
11560             shift -= 2;
11561           else if (bytemode == xmmdw_mode)
11562             shift -= 3;
11563           break;
11564         case ymm_mode:
11565           shift = 5;
11566           break;
11567         case xmm_mode:
11568           shift = 4;
11569           break;
11570         case q_mode:
11571         case q_swap_mode:
11572           shift = 3;
11573           break;
11574         case bw_unit_mode:
11575           shift = ins->vex.w ? 1 : 0;
11576           break;
11577         default:
11578           abort ();
11579         }
11580     }
11581   else
11582     shift = 0;
11583
11584   USED_REX (REX_B);
11585   if (ins->intel_syntax)
11586     intel_operand_size (ins, bytemode, sizeflag);
11587   append_seg (ins);
11588
11589   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11590     {
11591       /* 32/64 bit address mode */
11592       int havedisp;
11593       int havebase;
11594       int needindex;
11595       int needaddr32;
11596       int base, rbase;
11597       int vindex = 0;
11598       int scale = 0;
11599       int addr32flag = !((sizeflag & AFLAG)
11600                          || bytemode == v_bnd_mode
11601                          || bytemode == v_bndmk_mode
11602                          || bytemode == bnd_mode
11603                          || bytemode == bnd_swap_mode);
11604       bool check_gather = false;
11605       const char *const *indexes = NULL;
11606
11607       havebase = 1;
11608       base = ins->modrm.rm;
11609
11610       if (base == 4)
11611         {
11612           vindex = ins->sib.index;
11613           USED_REX (REX_X);
11614           if (ins->rex & REX_X)
11615             vindex += 8;
11616           switch (bytemode)
11617             {
11618             case vex_vsib_d_w_dq_mode:
11619             case vex_vsib_q_w_dq_mode:
11620               if (!ins->need_vex)
11621                 abort ();
11622               if (ins->vex.evex)
11623                 {
11624                   if (!ins->vex.v)
11625                     vindex += 16;
11626                   check_gather = ins->obufp == ins->op_out[1];
11627                 }
11628
11629               switch (ins->vex.length)
11630                 {
11631                 case 128:
11632                   indexes = att_names_xmm;
11633                   break;
11634                 case 256:
11635                   if (!ins->vex.w
11636                       || bytemode == vex_vsib_q_w_dq_mode)
11637                     indexes = att_names_ymm;
11638                   else
11639                     indexes = att_names_xmm;
11640                   break;
11641                 case 512:
11642                   if (!ins->vex.w
11643                       || bytemode == vex_vsib_q_w_dq_mode)
11644                     indexes = att_names_zmm;
11645                   else
11646                     indexes = att_names_ymm;
11647                   break;
11648                 default:
11649                   abort ();
11650                 }
11651               break;
11652             default:
11653               if (vindex != 4)
11654                 indexes = ins->address_mode == mode_64bit && !addr32flag
11655                           ? att_names64 : att_names32;
11656               break;
11657             }
11658           scale = ins->sib.scale;
11659           base = ins->sib.base;
11660           ins->codep++;
11661         }
11662       else
11663         {
11664           /* Check for mandatory SIB.  */
11665           if (bytemode == vex_vsib_d_w_dq_mode
11666               || bytemode == vex_vsib_q_w_dq_mode
11667               || bytemode == vex_sibmem_mode)
11668             {
11669               oappend (ins, "(bad)");
11670               return;
11671             }
11672         }
11673       rbase = base + add;
11674
11675       switch (ins->modrm.mod)
11676         {
11677         case 0:
11678           if (base == 5)
11679             {
11680               havebase = 0;
11681               if (ins->address_mode == mode_64bit && !ins->has_sib)
11682                 riprel = 1;
11683               disp = get32s (ins);
11684               if (riprel && bytemode == v_bndmk_mode)
11685                 {
11686                   oappend (ins, "(bad)");
11687                   return;
11688                 }
11689             }
11690           break;
11691         case 1:
11692           FETCH_DATA (ins->info, ins->codep + 1);
11693           disp = *ins->codep++;
11694           if ((disp & 0x80) != 0)
11695             disp -= 0x100;
11696           if (ins->vex.evex && shift > 0)
11697             disp <<= shift;
11698           break;
11699         case 2:
11700           disp = get32s (ins);
11701           break;
11702         }
11703
11704       needindex = 0;
11705       needaddr32 = 0;
11706       if (ins->has_sib
11707           && !havebase
11708           && !indexes
11709           && ins->address_mode != mode_16bit)
11710         {
11711           if (ins->address_mode == mode_64bit)
11712             {
11713               if (addr32flag)
11714                 {
11715                   /* Without base nor index registers, zero-extend the
11716                      lower 32-bit displacement to 64 bits.  */
11717                   disp = (unsigned int) disp;
11718                   needindex = 1;
11719                 }
11720               needaddr32 = 1;
11721             }
11722           else
11723             {
11724               /* In 32-bit mode, we need index register to tell [offset]
11725                  from [eiz*1 + offset].  */
11726               needindex = 1;
11727             }
11728         }
11729
11730       havedisp = (havebase
11731                   || needindex
11732                   || (ins->has_sib && (indexes || scale != 0)));
11733
11734       if (!ins->intel_syntax)
11735         if (ins->modrm.mod != 0 || base == 5)
11736           {
11737             if (havedisp || riprel)
11738               print_displacement (ins, disp);
11739             else
11740               print_operand_value (ins, disp, dis_style_address_offset);
11741             if (riprel)
11742               {
11743                 set_op (ins, disp, true);
11744                 oappend_char (ins, '(');
11745                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11746                                     dis_style_register);
11747                 oappend_char (ins, ')');
11748               }
11749           }
11750
11751       if ((havebase || indexes || needindex || needaddr32 || riprel)
11752           && (ins->address_mode != mode_64bit
11753               || ((bytemode != v_bnd_mode)
11754                   && (bytemode != v_bndmk_mode)
11755                   && (bytemode != bnd_mode)
11756                   && (bytemode != bnd_swap_mode))))
11757         ins->used_prefixes |= PREFIX_ADDR;
11758
11759       if (havedisp || (ins->intel_syntax && riprel))
11760         {
11761           oappend_char (ins, ins->open_char);
11762           if (ins->intel_syntax && riprel)
11763             {
11764               set_op (ins, disp, true);
11765               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
11766                                   dis_style_register);
11767             }
11768           if (havebase)
11769             oappend_register
11770               (ins,
11771                (ins->address_mode == mode_64bit && !addr32flag
11772                 ? att_names64 : att_names32)[rbase]);
11773           if (ins->has_sib)
11774             {
11775               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11776                  print index to tell base + index from base.  */
11777               if (scale != 0
11778                   || needindex
11779                   || indexes
11780                   || (havebase && base != ESP_REG_NUM))
11781                 {
11782                   if (!ins->intel_syntax || havebase)
11783                     oappend_char (ins, ins->separator_char);
11784                   if (indexes)
11785                     {
11786                       if (ins->address_mode == mode_64bit || vindex < 16)
11787                         oappend_register (ins, indexes[vindex]);
11788                       else
11789                         oappend (ins, "(bad)");
11790                     }
11791                   else
11792                     oappend_register (ins,
11793                                       ins->address_mode == mode_64bit
11794                                       && !addr32flag
11795                                       ? att_index64
11796                                       : att_index32);
11797
11798                   oappend_char (ins, ins->scale_char);
11799                   oappend_char_with_style (ins, '0' + (1 << scale),
11800                                            dis_style_immediate);
11801                 }
11802             }
11803           if (ins->intel_syntax
11804               && (disp || ins->modrm.mod != 0 || base == 5))
11805             {
11806               if (!havedisp || (bfd_signed_vma) disp >= 0)
11807                   oappend_char (ins, '+');
11808               else if (ins->modrm.mod != 1 && disp != -disp)
11809                 {
11810                   oappend_char (ins, '-');
11811                   disp = -disp;
11812                 }
11813
11814               if (havedisp)
11815                 print_displacement (ins, disp);
11816               else
11817                 print_operand_value (ins, disp, dis_style_address_offset);
11818             }
11819
11820           oappend_char (ins, ins->close_char);
11821
11822           if (check_gather)
11823             {
11824               /* Both XMM/YMM/ZMM registers must be distinct.  */
11825               int modrm_reg = ins->modrm.reg;
11826
11827               if (ins->rex & REX_R)
11828                 modrm_reg += 8;
11829               if (!ins->vex.r)
11830                 modrm_reg += 16;
11831               if (vindex == modrm_reg)
11832                 oappend (ins, "/(bad)");
11833             }
11834         }
11835       else if (ins->intel_syntax)
11836         {
11837           if (ins->modrm.mod != 0 || base == 5)
11838             {
11839               if (!ins->active_seg_prefix)
11840                 {
11841                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
11842                   oappend (ins, ":");
11843                 }
11844               print_operand_value (ins, disp, dis_style_text);
11845             }
11846         }
11847     }
11848   else if (bytemode == v_bnd_mode
11849            || bytemode == v_bndmk_mode
11850            || bytemode == bnd_mode
11851            || bytemode == bnd_swap_mode
11852            || bytemode == vex_vsib_d_w_dq_mode
11853            || bytemode == vex_vsib_q_w_dq_mode)
11854     {
11855       oappend (ins, "(bad)");
11856       return;
11857     }
11858   else
11859     {
11860       /* 16 bit address mode */
11861       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
11862       switch (ins->modrm.mod)
11863         {
11864         case 0:
11865           if (ins->modrm.rm == 6)
11866             {
11867               disp = get16 (ins);
11868               if ((disp & 0x8000) != 0)
11869                 disp -= 0x10000;
11870             }
11871           break;
11872         case 1:
11873           FETCH_DATA (ins->info, ins->codep + 1);
11874           disp = *ins->codep++;
11875           if ((disp & 0x80) != 0)
11876             disp -= 0x100;
11877           if (ins->vex.evex && shift > 0)
11878             disp <<= shift;
11879           break;
11880         case 2:
11881           disp = get16 (ins);
11882           if ((disp & 0x8000) != 0)
11883             disp -= 0x10000;
11884           break;
11885         }
11886
11887       if (!ins->intel_syntax)
11888         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
11889           print_displacement (ins, disp);
11890
11891       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
11892         {
11893           oappend_char (ins, ins->open_char);
11894           oappend (ins, (ins->intel_syntax ? intel_index16
11895                          : att_index16)[ins->modrm.rm]);
11896           if (ins->intel_syntax
11897               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
11898             {
11899               if ((bfd_signed_vma) disp >= 0)
11900                 oappend_char (ins, '+');
11901               else if (ins->modrm.mod != 1)
11902                 {
11903                   oappend_char (ins, '-');
11904                   disp = -disp;
11905                 }
11906
11907               print_displacement (ins, disp);
11908             }
11909
11910           oappend_char (ins, ins->close_char);
11911         }
11912       else if (ins->intel_syntax)
11913         {
11914           if (!ins->active_seg_prefix)
11915             {
11916               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
11917               oappend (ins, ":");
11918             }
11919           print_operand_value (ins, disp & 0xffff, dis_style_text);
11920         }
11921     }
11922   if (ins->vex.b)
11923     {
11924       ins->evex_used |= EVEX_b_used;
11925
11926       /* Broadcast can only ever be valid for memory sources.  */
11927       if (ins->obufp == ins->op_out[0])
11928         ins->vex.no_broadcast = true;
11929
11930       if (!ins->vex.no_broadcast
11931           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
11932         {
11933           if (bytemode == xh_mode)
11934             {
11935               if (ins->vex.w)
11936                 oappend (ins, "{bad}");
11937               else
11938                 {
11939                   switch (ins->vex.length)
11940                     {
11941                     case 128:
11942                       oappend (ins, "{1to8}");
11943                       break;
11944                     case 256:
11945                       oappend (ins, "{1to16}");
11946                       break;
11947                     case 512:
11948                       oappend (ins, "{1to32}");
11949                       break;
11950                     default:
11951                       abort ();
11952                     }
11953                 }
11954             }
11955           else if (bytemode == q_mode
11956                    || bytemode == ymmq_mode)
11957             ins->vex.no_broadcast = true;
11958           else if (ins->vex.w
11959                    || bytemode == evex_half_bcst_xmmqdh_mode
11960                    || bytemode == evex_half_bcst_xmmq_mode)
11961             {
11962               switch (ins->vex.length)
11963                 {
11964                 case 128:
11965                   oappend (ins, "{1to2}");
11966                   break;
11967                 case 256:
11968                   oappend (ins, "{1to4}");
11969                   break;
11970                 case 512:
11971                   oappend (ins, "{1to8}");
11972                   break;
11973                 default:
11974                   abort ();
11975                 }
11976             }
11977           else if (bytemode == x_mode
11978                    || bytemode == evex_half_bcst_xmmqh_mode)
11979             {
11980               switch (ins->vex.length)
11981                 {
11982                 case 128:
11983                   oappend (ins, "{1to4}");
11984                   break;
11985                 case 256:
11986                   oappend (ins, "{1to8}");
11987                   break;
11988                 case 512:
11989                   oappend (ins, "{1to16}");
11990                   break;
11991                 default:
11992                   abort ();
11993                 }
11994             }
11995           else
11996             ins->vex.no_broadcast = true;
11997         }
11998       if (ins->vex.no_broadcast)
11999         oappend (ins, "{bad}");
12000     }
12001 }
12002
12003 static void
12004 OP_E (instr_info *ins, int bytemode, int sizeflag)
12005 {
12006   /* Skip mod/rm byte.  */
12007   MODRM_CHECK;
12008   ins->codep++;
12009
12010   if (ins->modrm.mod == 3)
12011     {
12012       if ((sizeflag & SUFFIX_ALWAYS)
12013           && (bytemode == b_swap_mode
12014               || bytemode == bnd_swap_mode
12015               || bytemode == v_swap_mode))
12016         swap_operand (ins);
12017
12018       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12019     }
12020   else
12021     OP_E_memory (ins, bytemode, sizeflag);
12022 }
12023
12024 static void
12025 OP_G (instr_info *ins, int bytemode, int sizeflag)
12026 {
12027   if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
12028     {
12029       oappend (ins, "(bad)");
12030       return;
12031     }
12032
12033   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12034 }
12035
12036 #ifdef BFD64
12037 static bfd_vma
12038 get64 (instr_info *ins)
12039 {
12040   bfd_vma x;
12041   unsigned int a;
12042   unsigned int b;
12043
12044   FETCH_DATA (ins->info, ins->codep + 8);
12045   a = *ins->codep++ & 0xff;
12046   a |= (*ins->codep++ & 0xff) << 8;
12047   a |= (*ins->codep++ & 0xff) << 16;
12048   a |= (*ins->codep++ & 0xffu) << 24;
12049   b = *ins->codep++ & 0xff;
12050   b |= (*ins->codep++ & 0xff) << 8;
12051   b |= (*ins->codep++ & 0xff) << 16;
12052   b |= (*ins->codep++ & 0xffu) << 24;
12053   x = a + ((bfd_vma) b << 32);
12054   return x;
12055 }
12056 #else
12057 static bfd_vma
12058 get64 (instr_info *ins ATTRIBUTE_UNUSED)
12059 {
12060   abort ();
12061   return 0;
12062 }
12063 #endif
12064
12065 static bfd_signed_vma
12066 get32 (instr_info *ins)
12067 {
12068   bfd_vma x = 0;
12069
12070   FETCH_DATA (ins->info, ins->codep + 4);
12071   x = *ins->codep++ & (bfd_vma) 0xff;
12072   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12073   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12074   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12075   return x;
12076 }
12077
12078 static bfd_signed_vma
12079 get32s (instr_info *ins)
12080 {
12081   bfd_vma x = 0;
12082
12083   FETCH_DATA (ins->info, ins->codep + 4);
12084   x = *ins->codep++ & (bfd_vma) 0xff;
12085   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12086   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12087   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12088
12089   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12090
12091   return x;
12092 }
12093
12094 static int
12095 get16 (instr_info *ins)
12096 {
12097   int x = 0;
12098
12099   FETCH_DATA (ins->info, ins->codep + 2);
12100   x = *ins->codep++ & 0xff;
12101   x |= (*ins->codep++ & 0xff) << 8;
12102   return x;
12103 }
12104
12105 static void
12106 set_op (instr_info *ins, bfd_vma op, bool riprel)
12107 {
12108   ins->op_index[ins->op_ad] = ins->op_ad;
12109   if (ins->address_mode == mode_64bit)
12110     ins->op_address[ins->op_ad] = op;
12111   else /* Mask to get a 32-bit address.  */
12112     ins->op_address[ins->op_ad] = op & 0xffffffff;
12113   ins->op_riprel[ins->op_ad] = riprel;
12114 }
12115
12116 static void
12117 OP_REG (instr_info *ins, int code, int sizeflag)
12118 {
12119   const char *s;
12120   int add;
12121
12122   switch (code)
12123     {
12124     case es_reg: case ss_reg: case cs_reg:
12125     case ds_reg: case fs_reg: case gs_reg:
12126       oappend_register (ins, att_names_seg[code - es_reg]);
12127       return;
12128     }
12129
12130   USED_REX (REX_B);
12131   if (ins->rex & REX_B)
12132     add = 8;
12133   else
12134     add = 0;
12135
12136   switch (code)
12137     {
12138     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12139     case sp_reg: case bp_reg: case si_reg: case di_reg:
12140       s = att_names16[code - ax_reg + add];
12141       break;
12142     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12143       USED_REX (0);
12144       /* Fall through.  */
12145     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12146       if (ins->rex)
12147         s = att_names8rex[code - al_reg + add];
12148       else
12149         s = att_names8[code - al_reg];
12150       break;
12151     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12152     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12153       if (ins->address_mode == mode_64bit
12154           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12155         {
12156           s = att_names64[code - rAX_reg + add];
12157           break;
12158         }
12159       code += eAX_reg - rAX_reg;
12160       /* Fall through.  */
12161     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12162     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12163       USED_REX (REX_W);
12164       if (ins->rex & REX_W)
12165         s = att_names64[code - eAX_reg + add];
12166       else
12167         {
12168           if (sizeflag & DFLAG)
12169             s = att_names32[code - eAX_reg + add];
12170           else
12171             s = att_names16[code - eAX_reg + add];
12172           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12173         }
12174       break;
12175     default:
12176       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12177       return;
12178     }
12179   oappend_register (ins, s);
12180 }
12181
12182 static void
12183 OP_IMREG (instr_info *ins, int code, int sizeflag)
12184 {
12185   const char *s;
12186
12187   switch (code)
12188     {
12189     case indir_dx_reg:
12190       if (!ins->intel_syntax)
12191         {
12192           oappend (ins, "(%dx)");
12193           return;
12194         }
12195       s = att_names16[dx_reg - ax_reg];
12196       break;
12197     case al_reg: case cl_reg:
12198       s = att_names8[code - al_reg];
12199       break;
12200     case eAX_reg:
12201       USED_REX (REX_W);
12202       if (ins->rex & REX_W)
12203         {
12204           s = *att_names64;
12205           break;
12206         }
12207       /* Fall through.  */
12208     case z_mode_ax_reg:
12209       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12210         s = *att_names32;
12211       else
12212         s = *att_names16;
12213       if (!(ins->rex & REX_W))
12214         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12215       break;
12216     default:
12217       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12218       return;
12219     }
12220   oappend_register (ins, s);
12221 }
12222
12223 static void
12224 OP_I (instr_info *ins, int bytemode, int sizeflag)
12225 {
12226   bfd_signed_vma op;
12227   bfd_signed_vma mask = -1;
12228
12229   switch (bytemode)
12230     {
12231     case b_mode:
12232       FETCH_DATA (ins->info, ins->codep + 1);
12233       op = *ins->codep++;
12234       mask = 0xff;
12235       break;
12236     case v_mode:
12237       USED_REX (REX_W);
12238       if (ins->rex & REX_W)
12239         op = get32s (ins);
12240       else
12241         {
12242           if (sizeflag & DFLAG)
12243             {
12244               op = get32 (ins);
12245               mask = 0xffffffff;
12246             }
12247           else
12248             {
12249               op = get16 (ins);
12250               mask = 0xfffff;
12251             }
12252           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12253         }
12254       break;
12255     case d_mode:
12256       mask = 0xffffffff;
12257       op = get32 (ins);
12258       break;
12259     case w_mode:
12260       mask = 0xfffff;
12261       op = get16 (ins);
12262       break;
12263     case const_1_mode:
12264       if (ins->intel_syntax)
12265         oappend (ins, "1");
12266       return;
12267     default:
12268       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12269       return;
12270     }
12271
12272   op &= mask;
12273   oappend_immediate (ins, op);
12274 }
12275
12276 static void
12277 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12278 {
12279   if (bytemode != v_mode || ins->address_mode != mode_64bit
12280       || !(ins->rex & REX_W))
12281     {
12282       OP_I (ins, bytemode, sizeflag);
12283       return;
12284     }
12285
12286   USED_REX (REX_W);
12287
12288   oappend_immediate (ins, get64 (ins));
12289 }
12290
12291 static void
12292 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12293 {
12294   bfd_signed_vma op;
12295
12296   switch (bytemode)
12297     {
12298     case b_mode:
12299     case b_T_mode:
12300       FETCH_DATA (ins->info, ins->codep + 1);
12301       op = *ins->codep++;
12302       if ((op & 0x80) != 0)
12303         op -= 0x100;
12304       if (bytemode == b_T_mode)
12305         {
12306           if (ins->address_mode != mode_64bit
12307               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12308             {
12309               /* The operand-size prefix is overridden by a REX prefix.  */
12310               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12311                 op &= 0xffffffff;
12312               else
12313                 op &= 0xffff;
12314           }
12315         }
12316       else
12317         {
12318           if (!(ins->rex & REX_W))
12319             {
12320               if (sizeflag & DFLAG)
12321                 op &= 0xffffffff;
12322               else
12323                 op &= 0xffff;
12324             }
12325         }
12326       break;
12327     case v_mode:
12328       /* The operand-size prefix is overridden by a REX prefix.  */
12329       if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12330         op = get32s (ins);
12331       else
12332         op = get16 (ins);
12333       break;
12334     default:
12335       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12336       return;
12337     }
12338
12339   oappend_immediate (ins, op);
12340 }
12341
12342 static void
12343 OP_J (instr_info *ins, int bytemode, int sizeflag)
12344 {
12345   bfd_vma disp;
12346   bfd_vma mask = -1;
12347   bfd_vma segment = 0;
12348
12349   switch (bytemode)
12350     {
12351     case b_mode:
12352       FETCH_DATA (ins->info, ins->codep + 1);
12353       disp = *ins->codep++;
12354       if ((disp & 0x80) != 0)
12355         disp -= 0x100;
12356       break;
12357     case v_mode:
12358     case dqw_mode:
12359       if ((sizeflag & DFLAG)
12360           || (ins->address_mode == mode_64bit
12361               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12362                   || (ins->rex & REX_W))))
12363         disp = get32s (ins);
12364       else
12365         {
12366           disp = get16 (ins);
12367           if ((disp & 0x8000) != 0)
12368             disp -= 0x10000;
12369           /* In 16bit mode, address is wrapped around at 64k within
12370              the same segment.  Otherwise, a data16 prefix on a jump
12371              instruction means that the pc is masked to 16 bits after
12372              the displacement is added!  */
12373           mask = 0xffff;
12374           if ((ins->prefixes & PREFIX_DATA) == 0)
12375             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12376                        & ~((bfd_vma) 0xffff));
12377         }
12378       if (ins->address_mode != mode_64bit
12379           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12380         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12381       break;
12382     default:
12383       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12384       return;
12385     }
12386   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12387          | segment;
12388   set_op (ins, disp, false);
12389   print_operand_value (ins, disp, dis_style_text);
12390 }
12391
12392 static void
12393 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12394 {
12395   if (bytemode == w_mode)
12396     oappend_register (ins, att_names_seg[ins->modrm.reg]);
12397   else
12398     OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12399 }
12400
12401 static void
12402 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12403 {
12404   int seg, offset, res;
12405   char scratch[24];
12406
12407   if (sizeflag & DFLAG)
12408     {
12409       offset = get32 (ins);
12410       seg = get16 (ins);
12411     }
12412   else
12413     {
12414       offset = get16 (ins);
12415       seg = get16 (ins);
12416     }
12417   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12418
12419   res = snprintf (scratch, ARRAY_SIZE (scratch),
12420                   ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12421                   seg, offset);
12422   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12423     abort ();
12424   oappend (ins, scratch);
12425 }
12426
12427 static void
12428 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12429 {
12430   bfd_vma off;
12431
12432   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12433     intel_operand_size (ins, bytemode, sizeflag);
12434   append_seg (ins);
12435
12436   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12437     off = get32 (ins);
12438   else
12439     off = get16 (ins);
12440
12441   if (ins->intel_syntax)
12442     {
12443       if (!ins->active_seg_prefix)
12444         {
12445           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12446           oappend (ins, ":");
12447         }
12448     }
12449   print_operand_value (ins, off, dis_style_address_offset);
12450 }
12451
12452 static void
12453 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12454 {
12455   bfd_vma off;
12456
12457   if (ins->address_mode != mode_64bit
12458       || (ins->prefixes & PREFIX_ADDR))
12459     {
12460       OP_OFF (ins, bytemode, sizeflag);
12461       return;
12462     }
12463
12464   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12465     intel_operand_size (ins, bytemode, sizeflag);
12466   append_seg (ins);
12467
12468   off = get64 (ins);
12469
12470   if (ins->intel_syntax)
12471     {
12472       if (!ins->active_seg_prefix)
12473         {
12474           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12475           oappend (ins, ":");
12476         }
12477     }
12478   print_operand_value (ins, off, dis_style_address_offset);
12479 }
12480
12481 static void
12482 ptr_reg (instr_info *ins, int code, int sizeflag)
12483 {
12484   const char *s;
12485
12486   *ins->obufp++ = ins->open_char;
12487   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12488   if (ins->address_mode == mode_64bit)
12489     {
12490       if (!(sizeflag & AFLAG))
12491         s = att_names32[code - eAX_reg];
12492       else
12493         s = att_names64[code - eAX_reg];
12494     }
12495   else if (sizeflag & AFLAG)
12496     s = att_names32[code - eAX_reg];
12497   else
12498     s = att_names16[code - eAX_reg];
12499   oappend_register (ins, s);
12500   oappend_char (ins, ins->close_char);
12501 }
12502
12503 static void
12504 OP_ESreg (instr_info *ins, int code, int sizeflag)
12505 {
12506   if (ins->intel_syntax)
12507     {
12508       switch (ins->codep[-1])
12509         {
12510         case 0x6d:      /* insw/insl */
12511           intel_operand_size (ins, z_mode, sizeflag);
12512           break;
12513         case 0xa5:      /* movsw/movsl/movsq */
12514         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12515         case 0xab:      /* stosw/stosl */
12516         case 0xaf:      /* scasw/scasl */
12517           intel_operand_size (ins, v_mode, sizeflag);
12518           break;
12519         default:
12520           intel_operand_size (ins, b_mode, sizeflag);
12521         }
12522     }
12523   oappend_register (ins, "%es");
12524   oappend_char (ins, ':');
12525   ptr_reg (ins, code, sizeflag);
12526 }
12527
12528 static void
12529 OP_DSreg (instr_info *ins, int code, int sizeflag)
12530 {
12531   if (ins->intel_syntax)
12532     {
12533       switch (ins->codep[-1])
12534         {
12535         case 0x6f:      /* outsw/outsl */
12536           intel_operand_size (ins, z_mode, sizeflag);
12537           break;
12538         case 0xa5:      /* movsw/movsl/movsq */
12539         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12540         case 0xad:      /* lodsw/lodsl/lodsq */
12541           intel_operand_size (ins, v_mode, sizeflag);
12542           break;
12543         default:
12544           intel_operand_size (ins, b_mode, sizeflag);
12545         }
12546     }
12547   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12548      default segment register DS is printed.  */
12549   if (!ins->active_seg_prefix)
12550     ins->active_seg_prefix = PREFIX_DS;
12551   append_seg (ins);
12552   ptr_reg (ins, code, sizeflag);
12553 }
12554
12555 static void
12556 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12557       int sizeflag ATTRIBUTE_UNUSED)
12558 {
12559   int add, res;
12560   char scratch[8];
12561
12562   if (ins->rex & REX_R)
12563     {
12564       USED_REX (REX_R);
12565       add = 8;
12566     }
12567   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12568     {
12569       ins->all_prefixes[ins->last_lock_prefix] = 0;
12570       ins->used_prefixes |= PREFIX_LOCK;
12571       add = 8;
12572     }
12573   else
12574     add = 0;
12575   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12576                   ins->modrm.reg + add);
12577   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12578     abort ();
12579   oappend_register (ins, scratch);
12580 }
12581
12582 static void
12583 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12584       int sizeflag ATTRIBUTE_UNUSED)
12585 {
12586   int add, res;
12587   char scratch[8];
12588
12589   USED_REX (REX_R);
12590   if (ins->rex & REX_R)
12591     add = 8;
12592   else
12593     add = 0;
12594   res = snprintf (scratch, ARRAY_SIZE (scratch),
12595                   ins->intel_syntax ? "dr%d" : "%%db%d",
12596                   ins->modrm.reg + add);
12597   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12598     abort ();
12599   oappend (ins, scratch);
12600 }
12601
12602 static void
12603 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12604       int sizeflag ATTRIBUTE_UNUSED)
12605 {
12606   int res;
12607   char scratch[8];
12608
12609   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12610   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12611     abort ();
12612   oappend_register (ins, scratch);
12613 }
12614
12615 static void
12616 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12617         int sizeflag ATTRIBUTE_UNUSED)
12618 {
12619   int reg = ins->modrm.reg;
12620   const char *const *names;
12621
12622   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12623   if (ins->prefixes & PREFIX_DATA)
12624     {
12625       names = att_names_xmm;
12626       USED_REX (REX_R);
12627       if (ins->rex & REX_R)
12628         reg += 8;
12629     }
12630   else
12631     names = att_names_mm;
12632   oappend_register (ins, names[reg]);
12633 }
12634
12635 static void
12636 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12637 {
12638   const char *const *names;
12639
12640   if (bytemode == xmmq_mode
12641       || bytemode == evex_half_bcst_xmmqh_mode
12642       || bytemode == evex_half_bcst_xmmq_mode)
12643     {
12644       switch (ins->vex.length)
12645         {
12646         case 128:
12647         case 256:
12648           names = att_names_xmm;
12649           break;
12650         case 512:
12651           names = att_names_ymm;
12652           ins->evex_used |= EVEX_len_used;
12653           break;
12654         default:
12655           abort ();
12656         }
12657     }
12658   else if (bytemode == ymm_mode)
12659     names = att_names_ymm;
12660   else if (bytemode == tmm_mode)
12661     {
12662       if (reg >= 8)
12663         {
12664           oappend (ins, "(bad)");
12665           return;
12666         }
12667       names = att_names_tmm;
12668     }
12669   else if (ins->need_vex
12670            && bytemode != xmm_mode
12671            && bytemode != scalar_mode
12672            && bytemode != xmmdw_mode
12673            && bytemode != xmmqd_mode
12674            && bytemode != evex_half_bcst_xmmqdh_mode
12675            && bytemode != w_swap_mode
12676            && bytemode != b_mode
12677            && bytemode != w_mode
12678            && bytemode != d_mode
12679            && bytemode != q_mode)
12680     {
12681       ins->evex_used |= EVEX_len_used;
12682       switch (ins->vex.length)
12683         {
12684         case 128:
12685           names = att_names_xmm;
12686           break;
12687         case 256:
12688           if (ins->vex.w
12689               || bytemode != vex_vsib_q_w_dq_mode)
12690             names = att_names_ymm;
12691           else
12692             names = att_names_xmm;
12693           break;
12694         case 512:
12695           if (ins->vex.w
12696               || bytemode != vex_vsib_q_w_dq_mode)
12697             names = att_names_zmm;
12698           else
12699             names = att_names_ymm;
12700           break;
12701         default:
12702           abort ();
12703         }
12704     }
12705   else
12706     names = att_names_xmm;
12707   oappend_register (ins, names[reg]);
12708 }
12709
12710 static void
12711 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12712 {
12713   unsigned int reg = ins->modrm.reg;
12714
12715   USED_REX (REX_R);
12716   if (ins->rex & REX_R)
12717     reg += 8;
12718   if (ins->vex.evex)
12719     {
12720       if (!ins->vex.r)
12721         reg += 16;
12722     }
12723
12724   if (bytemode == tmm_mode)
12725     ins->modrm.reg = reg;
12726   else if (bytemode == scalar_mode)
12727     ins->vex.no_broadcast = true;
12728
12729   print_vector_reg (ins, reg, bytemode);
12730 }
12731
12732 static void
12733 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12734 {
12735   int reg;
12736   const char *const *names;
12737
12738   if (ins->modrm.mod != 3)
12739     {
12740       if (ins->intel_syntax
12741           && (bytemode == v_mode || bytemode == v_swap_mode))
12742         {
12743           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12744           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12745         }
12746       OP_E (ins, bytemode, sizeflag);
12747       return;
12748     }
12749
12750   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12751     swap_operand (ins);
12752
12753   /* Skip mod/rm byte.  */
12754   MODRM_CHECK;
12755   ins->codep++;
12756   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12757   reg = ins->modrm.rm;
12758   if (ins->prefixes & PREFIX_DATA)
12759     {
12760       names = att_names_xmm;
12761       USED_REX (REX_B);
12762       if (ins->rex & REX_B)
12763         reg += 8;
12764     }
12765   else
12766     names = att_names_mm;
12767   oappend_register (ins, names[reg]);
12768 }
12769
12770 /* cvt* are the only instructions in sse2 which have
12771    both SSE and MMX operands and also have 0x66 prefix
12772    in their opcode. 0x66 was originally used to differentiate
12773    between SSE and MMX instruction(operands). So we have to handle the
12774    cvt* separately using OP_EMC and OP_MXC */
12775 static void
12776 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12777 {
12778   if (ins->modrm.mod != 3)
12779     {
12780       if (ins->intel_syntax && bytemode == v_mode)
12781         {
12782           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12783           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12784         }
12785       OP_E (ins, bytemode, sizeflag);
12786       return;
12787     }
12788
12789   /* Skip mod/rm byte.  */
12790   MODRM_CHECK;
12791   ins->codep++;
12792   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12793   oappend_register (ins, att_names_mm[ins->modrm.rm]);
12794 }
12795
12796 static void
12797 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12798         int sizeflag ATTRIBUTE_UNUSED)
12799 {
12800   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12801   oappend_register (ins, att_names_mm[ins->modrm.reg]);
12802 }
12803
12804 static void
12805 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12806 {
12807   int reg;
12808
12809   /* Skip mod/rm byte.  */
12810   MODRM_CHECK;
12811   ins->codep++;
12812
12813   if (bytemode == dq_mode)
12814     bytemode = ins->vex.w ? q_mode : d_mode;
12815
12816   if (ins->modrm.mod != 3)
12817     {
12818       OP_E_memory (ins, bytemode, sizeflag);
12819       return;
12820     }
12821
12822   reg = ins->modrm.rm;
12823   USED_REX (REX_B);
12824   if (ins->rex & REX_B)
12825     reg += 8;
12826   if (ins->vex.evex)
12827     {
12828       USED_REX (REX_X);
12829       if ((ins->rex & REX_X))
12830         reg += 16;
12831     }
12832
12833   if ((sizeflag & SUFFIX_ALWAYS)
12834       && (bytemode == x_swap_mode
12835           || bytemode == w_swap_mode
12836           || bytemode == d_swap_mode
12837           || bytemode == q_swap_mode))
12838     swap_operand (ins);
12839
12840   if (bytemode == tmm_mode)
12841     ins->modrm.rm = reg;
12842
12843   print_vector_reg (ins, reg, bytemode);
12844 }
12845
12846 static void
12847 OP_MS (instr_info *ins, int bytemode, int sizeflag)
12848 {
12849   if (ins->modrm.mod == 3)
12850     OP_EM (ins, bytemode, sizeflag);
12851   else
12852     BadOp (ins);
12853 }
12854
12855 static void
12856 OP_XS (instr_info *ins, int bytemode, int sizeflag)
12857 {
12858   if (ins->modrm.mod == 3)
12859     OP_EX (ins, bytemode, sizeflag);
12860   else
12861     BadOp (ins);
12862 }
12863
12864 static void
12865 OP_M (instr_info *ins, int bytemode, int sizeflag)
12866 {
12867   if (ins->modrm.mod == 3)
12868     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12869     BadOp (ins);
12870   else
12871     OP_E (ins, bytemode, sizeflag);
12872 }
12873
12874 static void
12875 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
12876 {
12877   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
12878     BadOp (ins);
12879   else
12880     OP_E (ins, bytemode, sizeflag);
12881 }
12882
12883 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12884    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12885
12886 static void
12887 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
12888 {
12889   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
12890     ins->mnemonicendp = stpcpy (ins->obuf, "nop");
12891   else if (opnd == 0)
12892     OP_REG (ins, eAX_reg, sizeflag);
12893   else
12894     OP_IMREG (ins, eAX_reg, sizeflag);
12895 }
12896
12897 static const char *const Suffix3DNow[] = {
12898 /* 00 */        NULL,           NULL,           NULL,           NULL,
12899 /* 04 */        NULL,           NULL,           NULL,           NULL,
12900 /* 08 */        NULL,           NULL,           NULL,           NULL,
12901 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12902 /* 10 */        NULL,           NULL,           NULL,           NULL,
12903 /* 14 */        NULL,           NULL,           NULL,           NULL,
12904 /* 18 */        NULL,           NULL,           NULL,           NULL,
12905 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12906 /* 20 */        NULL,           NULL,           NULL,           NULL,
12907 /* 24 */        NULL,           NULL,           NULL,           NULL,
12908 /* 28 */        NULL,           NULL,           NULL,           NULL,
12909 /* 2C */        NULL,           NULL,           NULL,           NULL,
12910 /* 30 */        NULL,           NULL,           NULL,           NULL,
12911 /* 34 */        NULL,           NULL,           NULL,           NULL,
12912 /* 38 */        NULL,           NULL,           NULL,           NULL,
12913 /* 3C */        NULL,           NULL,           NULL,           NULL,
12914 /* 40 */        NULL,           NULL,           NULL,           NULL,
12915 /* 44 */        NULL,           NULL,           NULL,           NULL,
12916 /* 48 */        NULL,           NULL,           NULL,           NULL,
12917 /* 4C */        NULL,           NULL,           NULL,           NULL,
12918 /* 50 */        NULL,           NULL,           NULL,           NULL,
12919 /* 54 */        NULL,           NULL,           NULL,           NULL,
12920 /* 58 */        NULL,           NULL,           NULL,           NULL,
12921 /* 5C */        NULL,           NULL,           NULL,           NULL,
12922 /* 60 */        NULL,           NULL,           NULL,           NULL,
12923 /* 64 */        NULL,           NULL,           NULL,           NULL,
12924 /* 68 */        NULL,           NULL,           NULL,           NULL,
12925 /* 6C */        NULL,           NULL,           NULL,           NULL,
12926 /* 70 */        NULL,           NULL,           NULL,           NULL,
12927 /* 74 */        NULL,           NULL,           NULL,           NULL,
12928 /* 78 */        NULL,           NULL,           NULL,           NULL,
12929 /* 7C */        NULL,           NULL,           NULL,           NULL,
12930 /* 80 */        NULL,           NULL,           NULL,           NULL,
12931 /* 84 */        NULL,           NULL,           NULL,           NULL,
12932 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12933 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12934 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12935 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12936 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12937 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12938 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12939 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12940 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12941 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12942 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12943 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12944 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12945 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12946 /* C0 */        NULL,           NULL,           NULL,           NULL,
12947 /* C4 */        NULL,           NULL,           NULL,           NULL,
12948 /* C8 */        NULL,           NULL,           NULL,           NULL,
12949 /* CC */        NULL,           NULL,           NULL,           NULL,
12950 /* D0 */        NULL,           NULL,           NULL,           NULL,
12951 /* D4 */        NULL,           NULL,           NULL,           NULL,
12952 /* D8 */        NULL,           NULL,           NULL,           NULL,
12953 /* DC */        NULL,           NULL,           NULL,           NULL,
12954 /* E0 */        NULL,           NULL,           NULL,           NULL,
12955 /* E4 */        NULL,           NULL,           NULL,           NULL,
12956 /* E8 */        NULL,           NULL,           NULL,           NULL,
12957 /* EC */        NULL,           NULL,           NULL,           NULL,
12958 /* F0 */        NULL,           NULL,           NULL,           NULL,
12959 /* F4 */        NULL,           NULL,           NULL,           NULL,
12960 /* F8 */        NULL,           NULL,           NULL,           NULL,
12961 /* FC */        NULL,           NULL,           NULL,           NULL,
12962 };
12963
12964 static void
12965 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12966                 int sizeflag ATTRIBUTE_UNUSED)
12967 {
12968   const char *mnemonic;
12969
12970   FETCH_DATA (ins->info, ins->codep + 1);
12971   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12972      place where an 8-bit immediate would normally go.  ie. the last
12973      byte of the instruction.  */
12974   ins->obufp = ins->mnemonicendp;
12975   mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
12976   if (mnemonic)
12977     ins->obufp = stpcpy (ins->obufp, mnemonic);
12978   else
12979     {
12980       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
12981          of the opcode (0x0f0f) and the opcode suffix, we need to do
12982          all the ins->modrm processing first, and don't know until now that
12983          we have a bad opcode.  This necessitates some cleaning up.  */
12984       ins->op_out[0][0] = '\0';
12985       ins->op_out[1][0] = '\0';
12986       BadOp (ins);
12987     }
12988   ins->mnemonicendp = ins->obufp;
12989 }
12990
12991 static const struct op simd_cmp_op[] =
12992 {
12993   { STRING_COMMA_LEN ("eq") },
12994   { STRING_COMMA_LEN ("lt") },
12995   { STRING_COMMA_LEN ("le") },
12996   { STRING_COMMA_LEN ("unord") },
12997   { STRING_COMMA_LEN ("neq") },
12998   { STRING_COMMA_LEN ("nlt") },
12999   { STRING_COMMA_LEN ("nle") },
13000   { STRING_COMMA_LEN ("ord") }
13001 };
13002
13003 static const struct op vex_cmp_op[] =
13004 {
13005   { STRING_COMMA_LEN ("eq_uq") },
13006   { STRING_COMMA_LEN ("nge") },
13007   { STRING_COMMA_LEN ("ngt") },
13008   { STRING_COMMA_LEN ("false") },
13009   { STRING_COMMA_LEN ("neq_oq") },
13010   { STRING_COMMA_LEN ("ge") },
13011   { STRING_COMMA_LEN ("gt") },
13012   { STRING_COMMA_LEN ("true") },
13013   { STRING_COMMA_LEN ("eq_os") },
13014   { STRING_COMMA_LEN ("lt_oq") },
13015   { STRING_COMMA_LEN ("le_oq") },
13016   { STRING_COMMA_LEN ("unord_s") },
13017   { STRING_COMMA_LEN ("neq_us") },
13018   { STRING_COMMA_LEN ("nlt_uq") },
13019   { STRING_COMMA_LEN ("nle_uq") },
13020   { STRING_COMMA_LEN ("ord_s") },
13021   { STRING_COMMA_LEN ("eq_us") },
13022   { STRING_COMMA_LEN ("nge_uq") },
13023   { STRING_COMMA_LEN ("ngt_uq") },
13024   { STRING_COMMA_LEN ("false_os") },
13025   { STRING_COMMA_LEN ("neq_os") },
13026   { STRING_COMMA_LEN ("ge_oq") },
13027   { STRING_COMMA_LEN ("gt_oq") },
13028   { STRING_COMMA_LEN ("true_us") },
13029 };
13030
13031 static void
13032 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13033            int sizeflag ATTRIBUTE_UNUSED)
13034 {
13035   unsigned int cmp_type;
13036
13037   FETCH_DATA (ins->info, ins->codep + 1);
13038   cmp_type = *ins->codep++ & 0xff;
13039   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13040     {
13041       char suffix[3];
13042       char *p = ins->mnemonicendp - 2;
13043       suffix[0] = p[0];
13044       suffix[1] = p[1];
13045       suffix[2] = '\0';
13046       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13047       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13048     }
13049   else if (ins->need_vex
13050            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13051     {
13052       char suffix[3];
13053       char *p = ins->mnemonicendp - 2;
13054       suffix[0] = p[0];
13055       suffix[1] = p[1];
13056       suffix[2] = '\0';
13057       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13058       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13059       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13060     }
13061   else
13062     {
13063       /* We have a reserved extension byte.  Output it directly.  */
13064       oappend_immediate (ins, cmp_type);
13065     }
13066 }
13067
13068 static void
13069 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13070 {
13071   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13072   if (!ins->intel_syntax)
13073     {
13074       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13075       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13076       if (bytemode == eBX_reg)
13077         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13078       ins->two_source_ops = true;
13079     }
13080   /* Skip mod/rm byte.  */
13081   MODRM_CHECK;
13082   ins->codep++;
13083 }
13084
13085 static void
13086 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13087             int sizeflag ATTRIBUTE_UNUSED)
13088 {
13089   /* monitor %{e,r,}ax,%ecx,%edx"  */
13090   if (!ins->intel_syntax)
13091     {
13092       const char *const *names = (ins->address_mode == mode_64bit
13093                                   ? att_names64 : att_names32);
13094
13095       if (ins->prefixes & PREFIX_ADDR)
13096         {
13097           /* Remove "addr16/addr32".  */
13098           ins->all_prefixes[ins->last_addr_prefix] = 0;
13099           names = (ins->address_mode != mode_32bit
13100                    ? att_names32 : att_names16);
13101           ins->used_prefixes |= PREFIX_ADDR;
13102         }
13103       else if (ins->address_mode == mode_16bit)
13104         names = att_names16;
13105       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13106       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13107       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13108       ins->two_source_ops = true;
13109     }
13110   /* Skip mod/rm byte.  */
13111   MODRM_CHECK;
13112   ins->codep++;
13113 }
13114
13115 static void
13116 BadOp (instr_info *ins)
13117 {
13118   /* Throw away prefixes and 1st. opcode byte.  */
13119   ins->codep = ins->insn_codep + 1;
13120   ins->obufp = stpcpy (ins->obufp, "(bad)");
13121 }
13122
13123 static void
13124 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13125 {
13126   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13127      lods and stos.  */
13128   if (ins->prefixes & PREFIX_REPZ)
13129     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13130
13131   switch (bytemode)
13132     {
13133     case al_reg:
13134     case eAX_reg:
13135     case indir_dx_reg:
13136       OP_IMREG (ins, bytemode, sizeflag);
13137       break;
13138     case eDI_reg:
13139       OP_ESreg (ins, bytemode, sizeflag);
13140       break;
13141     case eSI_reg:
13142       OP_DSreg (ins, bytemode, sizeflag);
13143       break;
13144     default:
13145       abort ();
13146       break;
13147     }
13148 }
13149
13150 static void
13151 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13152            int sizeflag ATTRIBUTE_UNUSED)
13153 {
13154   if (ins->isa64 != amd64)
13155     return;
13156
13157   ins->obufp = ins->obuf;
13158   BadOp (ins);
13159   ins->mnemonicendp = ins->obufp;
13160   ++ins->codep;
13161 }
13162
13163 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13164    "bnd".  */
13165
13166 static void
13167 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13168            int sizeflag ATTRIBUTE_UNUSED)
13169 {
13170   if (ins->prefixes & PREFIX_REPNZ)
13171     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13172 }
13173
13174 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13175    "notrack".  */
13176
13177 static void
13178 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13179                int sizeflag ATTRIBUTE_UNUSED)
13180 {
13181   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13182      we've seen a PREFIX_DS.  */
13183   if ((ins->prefixes & PREFIX_DS) != 0
13184       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13185     {
13186       /* NOTRACK prefix is only valid on indirect branch instructions.
13187          NB: DATA prefix is unsupported for Intel64.  */
13188       ins->active_seg_prefix = 0;
13189       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13190     }
13191 }
13192
13193 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13194    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13195  */
13196
13197 static void
13198 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13199 {
13200   if (ins->modrm.mod != 3
13201       && (ins->prefixes & PREFIX_LOCK) != 0)
13202     {
13203       if (ins->prefixes & PREFIX_REPZ)
13204         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13205       if (ins->prefixes & PREFIX_REPNZ)
13206         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13207     }
13208
13209   OP_E (ins, bytemode, sizeflag);
13210 }
13211
13212 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13213    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13214  */
13215
13216 static void
13217 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13218 {
13219   if (ins->modrm.mod != 3)
13220     {
13221       if (ins->prefixes & PREFIX_REPZ)
13222         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13223       if (ins->prefixes & PREFIX_REPNZ)
13224         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13225     }
13226
13227   OP_E (ins, bytemode, sizeflag);
13228 }
13229
13230 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13231    "xrelease" for memory operand.  No check for LOCK prefix.   */
13232
13233 static void
13234 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13235 {
13236   if (ins->modrm.mod != 3
13237       && ins->last_repz_prefix > ins->last_repnz_prefix
13238       && (ins->prefixes & PREFIX_REPZ) != 0)
13239     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13240
13241   OP_E (ins, bytemode, sizeflag);
13242 }
13243
13244 static void
13245 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13246 {
13247   USED_REX (REX_W);
13248   if (ins->rex & REX_W)
13249     {
13250       /* Change cmpxchg8b to cmpxchg16b.  */
13251       char *p = ins->mnemonicendp - 2;
13252       ins->mnemonicendp = stpcpy (p, "16b");
13253       bytemode = o_mode;
13254     }
13255   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13256     {
13257       if (ins->prefixes & PREFIX_REPZ)
13258         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13259       if (ins->prefixes & PREFIX_REPNZ)
13260         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13261     }
13262
13263   OP_M (ins, bytemode, sizeflag);
13264 }
13265
13266 static void
13267 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13268 {
13269   const char *const *names = att_names_xmm;
13270
13271   if (ins->need_vex)
13272     {
13273       switch (ins->vex.length)
13274         {
13275         case 128:
13276           break;
13277         case 256:
13278           names = att_names_ymm;
13279           break;
13280         default:
13281           abort ();
13282         }
13283     }
13284   oappend_register (ins, names[reg]);
13285 }
13286
13287 static void
13288 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13289 {
13290   /* Add proper suffix to "fxsave" and "fxrstor".  */
13291   USED_REX (REX_W);
13292   if (ins->rex & REX_W)
13293     {
13294       char *p = ins->mnemonicendp;
13295       *p++ = '6';
13296       *p++ = '4';
13297       *p = '\0';
13298       ins->mnemonicendp = p;
13299     }
13300   OP_M (ins, bytemode, sizeflag);
13301 }
13302
13303 /* Display the destination register operand for instructions with
13304    VEX. */
13305
13306 static void
13307 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13308 {
13309   int reg, modrm_reg, sib_index = -1;
13310   const char *const *names;
13311
13312   if (!ins->need_vex)
13313     abort ();
13314
13315   reg = ins->vex.register_specifier;
13316   ins->vex.register_specifier = 0;
13317   if (ins->address_mode != mode_64bit)
13318     {
13319       if (ins->vex.evex && !ins->vex.v)
13320         {
13321           oappend (ins, "(bad)");
13322           return;
13323         }
13324
13325       reg &= 7;
13326     }
13327   else if (ins->vex.evex && !ins->vex.v)
13328     reg += 16;
13329
13330   switch (bytemode)
13331     {
13332     case scalar_mode:
13333       oappend_register (ins, att_names_xmm[reg]);
13334       return;
13335
13336     case vex_vsib_d_w_dq_mode:
13337     case vex_vsib_q_w_dq_mode:
13338       /* This must be the 3rd operand.  */
13339       if (ins->obufp != ins->op_out[2])
13340         abort ();
13341       if (ins->vex.length == 128
13342           || (bytemode != vex_vsib_d_w_dq_mode
13343               && !ins->vex.w))
13344         oappend_register (ins, att_names_xmm[reg]);
13345       else
13346         oappend_register (ins, att_names_ymm[reg]);
13347
13348       /* All 3 XMM/YMM registers must be distinct.  */
13349       modrm_reg = ins->modrm.reg;
13350       if (ins->rex & REX_R)
13351         modrm_reg += 8;
13352
13353       if (ins->has_sib && ins->modrm.rm == 4)
13354         {
13355           sib_index = ins->sib.index;
13356           if (ins->rex & REX_X)
13357             sib_index += 8;
13358         }
13359
13360       if (reg == modrm_reg || reg == sib_index)
13361         strcpy (ins->obufp, "/(bad)");
13362       if (modrm_reg == sib_index || modrm_reg == reg)
13363         strcat (ins->op_out[0], "/(bad)");
13364       if (sib_index == modrm_reg || sib_index == reg)
13365         strcat (ins->op_out[1], "/(bad)");
13366
13367       return;
13368
13369     case tmm_mode:
13370       /* All 3 TMM registers must be distinct.  */
13371       if (reg >= 8)
13372         oappend (ins, "(bad)");
13373       else
13374         {
13375           /* This must be the 3rd operand.  */
13376           if (ins->obufp != ins->op_out[2])
13377             abort ();
13378           oappend_register (ins, att_names_tmm[reg]);
13379           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13380             strcpy (ins->obufp, "/(bad)");
13381         }
13382
13383       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13384           || ins->modrm.rm == reg)
13385         {
13386           if (ins->modrm.reg <= 8
13387               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13388             strcat (ins->op_out[0], "/(bad)");
13389           if (ins->modrm.rm <= 8
13390               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13391             strcat (ins->op_out[1], "/(bad)");
13392         }
13393
13394       return;
13395     }
13396
13397   switch (ins->vex.length)
13398     {
13399     case 128:
13400       switch (bytemode)
13401         {
13402         case x_mode:
13403           names = att_names_xmm;
13404           ins->evex_used |= EVEX_len_used;
13405           break;
13406         case dq_mode:
13407           if (ins->rex & REX_W)
13408             names = att_names64;
13409           else
13410             names = att_names32;
13411           break;
13412         case mask_bd_mode:
13413         case mask_mode:
13414           if (reg > 0x7)
13415             {
13416               oappend (ins, "(bad)");
13417               return;
13418             }
13419           names = att_names_mask;
13420           break;
13421         default:
13422           abort ();
13423           return;
13424         }
13425       break;
13426     case 256:
13427       switch (bytemode)
13428         {
13429         case x_mode:
13430           names = att_names_ymm;
13431           ins->evex_used |= EVEX_len_used;
13432           break;
13433         case mask_bd_mode:
13434         case mask_mode:
13435           if (reg > 0x7)
13436             {
13437               oappend (ins, "(bad)");
13438               return;
13439             }
13440           names = att_names_mask;
13441           break;
13442         default:
13443           /* See PR binutils/20893 for a reproducer.  */
13444           oappend (ins, "(bad)");
13445           return;
13446         }
13447       break;
13448     case 512:
13449       names = att_names_zmm;
13450       ins->evex_used |= EVEX_len_used;
13451       break;
13452     default:
13453       abort ();
13454       break;
13455     }
13456   oappend_register (ins, names[reg]);
13457 }
13458
13459 static void
13460 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13461 {
13462   if (ins->modrm.mod == 3)
13463     OP_VEX (ins, bytemode, sizeflag);
13464 }
13465
13466 static void
13467 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13468 {
13469   OP_VEX (ins, bytemode, sizeflag);
13470
13471   if (ins->vex.w)
13472     {
13473       /* Swap 2nd and 3rd operands.  */
13474       char *tmp = ins->op_out[2];
13475
13476       ins->op_out[2] = ins->op_out[1];
13477       ins->op_out[1] = tmp;
13478     }
13479 }
13480
13481 static void
13482 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13483 {
13484   int reg;
13485   const char *const *names = att_names_xmm;
13486
13487   FETCH_DATA (ins->info, ins->codep + 1);
13488   reg = *ins->codep++;
13489
13490   if (bytemode != x_mode && bytemode != scalar_mode)
13491     abort ();
13492
13493   reg >>= 4;
13494   if (ins->address_mode != mode_64bit)
13495     reg &= 7;
13496
13497   if (bytemode == x_mode && ins->vex.length == 256)
13498     names = att_names_ymm;
13499
13500   oappend_register (ins, names[reg]);
13501
13502   if (ins->vex.w)
13503     {
13504       /* Swap 3rd and 4th operands.  */
13505       char *tmp = ins->op_out[3];
13506
13507       ins->op_out[3] = ins->op_out[2];
13508       ins->op_out[2] = tmp;
13509     }
13510 }
13511
13512 static void
13513 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13514           int sizeflag ATTRIBUTE_UNUSED)
13515 {
13516   oappend_immediate (ins, ins->codep[-1] & 0xf);
13517 }
13518
13519 static void
13520 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13521              int sizeflag ATTRIBUTE_UNUSED)
13522 {
13523   unsigned int cmp_type;
13524
13525   if (!ins->vex.evex)
13526     abort ();
13527
13528   FETCH_DATA (ins->info, ins->codep + 1);
13529   cmp_type = *ins->codep++ & 0xff;
13530   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13531      If it's the case, print suffix, otherwise - print the immediate.  */
13532   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13533       && cmp_type != 3
13534       && cmp_type != 7)
13535     {
13536       char suffix[3];
13537       char *p = ins->mnemonicendp - 2;
13538
13539       /* vpcmp* can have both one- and two-lettered suffix.  */
13540       if (p[0] == 'p')
13541         {
13542           p++;
13543           suffix[0] = p[0];
13544           suffix[1] = '\0';
13545         }
13546       else
13547         {
13548           suffix[0] = p[0];
13549           suffix[1] = p[1];
13550           suffix[2] = '\0';
13551         }
13552
13553       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13554       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13555     }
13556   else
13557     {
13558       /* We have a reserved extension byte.  Output it directly.  */
13559       oappend_immediate (ins, cmp_type);
13560     }
13561 }
13562
13563 static const struct op xop_cmp_op[] =
13564 {
13565   { STRING_COMMA_LEN ("lt") },
13566   { STRING_COMMA_LEN ("le") },
13567   { STRING_COMMA_LEN ("gt") },
13568   { STRING_COMMA_LEN ("ge") },
13569   { STRING_COMMA_LEN ("eq") },
13570   { STRING_COMMA_LEN ("neq") },
13571   { STRING_COMMA_LEN ("false") },
13572   { STRING_COMMA_LEN ("true") }
13573 };
13574
13575 static void
13576 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13577              int sizeflag ATTRIBUTE_UNUSED)
13578 {
13579   unsigned int cmp_type;
13580
13581   FETCH_DATA (ins->info, ins->codep + 1);
13582   cmp_type = *ins->codep++ & 0xff;
13583   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13584     {
13585       char suffix[3];
13586       char *p = ins->mnemonicendp - 2;
13587
13588       /* vpcom* can have both one- and two-lettered suffix.  */
13589       if (p[0] == 'm')
13590         {
13591           p++;
13592           suffix[0] = p[0];
13593           suffix[1] = '\0';
13594         }
13595       else
13596         {
13597           suffix[0] = p[0];
13598           suffix[1] = p[1];
13599           suffix[2] = '\0';
13600         }
13601
13602       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13603       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13604     }
13605   else
13606     {
13607       /* We have a reserved extension byte.  Output it directly.  */
13608       oappend_immediate (ins, cmp_type);
13609     }
13610 }
13611
13612 static const struct op pclmul_op[] =
13613 {
13614   { STRING_COMMA_LEN ("lql") },
13615   { STRING_COMMA_LEN ("hql") },
13616   { STRING_COMMA_LEN ("lqh") },
13617   { STRING_COMMA_LEN ("hqh") }
13618 };
13619
13620 static void
13621 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13622               int sizeflag ATTRIBUTE_UNUSED)
13623 {
13624   unsigned int pclmul_type;
13625
13626   FETCH_DATA (ins->info, ins->codep + 1);
13627   pclmul_type = *ins->codep++ & 0xff;
13628   switch (pclmul_type)
13629     {
13630     case 0x10:
13631       pclmul_type = 2;
13632       break;
13633     case 0x11:
13634       pclmul_type = 3;
13635       break;
13636     default:
13637       break;
13638     }
13639   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13640     {
13641       char suffix[4];
13642       char *p = ins->mnemonicendp - 3;
13643       suffix[0] = p[0];
13644       suffix[1] = p[1];
13645       suffix[2] = p[2];
13646       suffix[3] = '\0';
13647       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13648       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13649     }
13650   else
13651     {
13652       /* We have a reserved extension byte.  Output it directly.  */
13653       oappend_immediate (ins, pclmul_type);
13654     }
13655 }
13656
13657 static void
13658 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13659 {
13660   /* Add proper suffix to "movsxd".  */
13661   char *p = ins->mnemonicendp;
13662
13663   switch (bytemode)
13664     {
13665     case movsxd_mode:
13666       if (!ins->intel_syntax)
13667         {
13668           USED_REX (REX_W);
13669           if (ins->rex & REX_W)
13670             {
13671               *p++ = 'l';
13672               *p++ = 'q';
13673               break;
13674             }
13675         }
13676
13677       *p++ = 'x';
13678       *p++ = 'd';
13679       break;
13680     default:
13681       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13682       break;
13683     }
13684
13685   ins->mnemonicendp = p;
13686   *p = '\0';
13687   OP_E (ins, bytemode, sizeflag);
13688 }
13689
13690 static void
13691 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13692 {
13693   unsigned int reg = ins->vex.register_specifier;
13694   unsigned int modrm_reg = ins->modrm.reg;
13695   unsigned int modrm_rm = ins->modrm.rm;
13696
13697   /* Calc destination register number.  */
13698   if (ins->rex & REX_R)
13699     modrm_reg += 8;
13700   if (!ins->vex.r)
13701     modrm_reg += 16;
13702
13703   /* Calc src1 register number.  */
13704   if (ins->address_mode != mode_64bit)
13705     reg &= 7;
13706   else if (ins->vex.evex && !ins->vex.v)
13707     reg += 16;
13708
13709   /* Calc src2 register number.  */
13710   if (ins->modrm.mod == 3)
13711     {
13712       if (ins->rex & REX_B)
13713         modrm_rm += 8;
13714       if (ins->rex & REX_X)
13715         modrm_rm += 16;
13716     }
13717
13718   /* Destination and source registers must be distinct, output bad if
13719      dest == src1 or dest == src2.  */
13720   if (modrm_reg == reg
13721       || (ins->modrm.mod == 3
13722           && modrm_reg == modrm_rm))
13723     {
13724       oappend (ins, "(bad)");
13725     }
13726   else
13727     OP_XMM (ins, bytemode, sizeflag);
13728 }
13729
13730 static void
13731 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13732 {
13733   if (ins->modrm.mod != 3 || !ins->vex.b)
13734     return;
13735
13736   switch (bytemode)
13737     {
13738     case evex_rounding_64_mode:
13739       if (ins->address_mode != mode_64bit || !ins->vex.w)
13740         return;
13741       /* Fall through.  */
13742     case evex_rounding_mode:
13743       ins->evex_used |= EVEX_b_used;
13744       oappend (ins, names_rounding[ins->vex.ll]);
13745       break;
13746     case evex_sae_mode:
13747       ins->evex_used |= EVEX_b_used;
13748       oappend (ins, "{");
13749       break;
13750     default:
13751       abort ();
13752     }
13753   oappend (ins, "sae}");
13754 }