sim/frv/frv-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1998-2022 Free Software Foundation, Inc.
   3    Contributed by Red Hat
   4
   5 This file is part of the GNU Simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef FRV_SIM_H
  21 #define FRV_SIM_H
  22
  23 #include "sim-options.h"
  24
  25 /* True if SPR is the number of accumulator or accumulator guard register.  */
  26 #define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
  27
  28 /* Initialization of the frv cpu.  */
  29 void frv_initialize (SIM_CPU *, SIM_DESC);
  30 void frv_term (SIM_DESC);
  31 void frv_power_on_reset (SIM_CPU *);
  32 void frv_hardware_reset (SIM_CPU *);
  33 void frv_software_reset (SIM_CPU *);
  34
  35 /* The reset register.  See FRV LSI section 10.3.1  */
  36 #define RSTR_ADDRESS        0xfeff0500
  37 #define RSTR_INITIAL_VALUE  0x00000400
  38 #define RSTR_HARDWARE_RESET 0x00000200
  39 #define RSTR_SOFTWARE_RESET 0x00000100
  40
  41 #define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1)
  42 #define GET_RSTR_SR(rstr) (((rstr)     ) & 1)
  43
  44 #define SET_RSTR_H(rstr) ((rstr) |= (1 << 9))
  45 #define SET_RSTR_S(rstr) ((rstr) |= (1 << 8))
  46
  47 #define CLEAR_RSTR_P(rstr)  ((rstr) &= ~(1 << 10))
  48 #define CLEAR_RSTR_H(rstr)  ((rstr) &= ~(1 <<  9))
  49 #define CLEAR_RSTR_S(rstr)  ((rstr) &= ~(1 <<  8))
  50 #define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 <<  1))
  51 #define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1)
  52
  53 /* Cutomized hardware get/set functions.  */
  54 extern USI  frvbf_h_spr_get_handler (SIM_CPU *, UINT);
  55 extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI);
  56 extern USI  frvbf_h_gr_get_handler (SIM_CPU *, UINT);
  57 extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI);
  58 extern UHI  frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT);
  59 extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI);
  60 extern UHI  frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT);
  61 extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI);
  62 extern DI   frvbf_h_gr_double_get_handler (SIM_CPU *, UINT);
  63 extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI);
  64 extern SF   frvbf_h_fr_get_handler (SIM_CPU *, UINT);
  65 extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF);
  66 extern DF   frvbf_h_fr_double_get_handler (SIM_CPU *, UINT);
  67 extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF);
  68 extern USI  frvbf_h_fr_int_get_handler (SIM_CPU *, UINT);
  69 extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI);
  70 extern DI   frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT);
  71 extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI);
  72 extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *);
  73 extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *);
  74 extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *);
  75 extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
  76
  77 extern USI  spr_psr_get_handler (SIM_CPU *);
  78 extern void spr_psr_set_handler (SIM_CPU *, USI);
  79 extern USI  spr_tbr_get_handler (SIM_CPU *);
  80 extern void spr_tbr_set_handler (SIM_CPU *, USI);
  81 extern USI  spr_bpsr_get_handler (SIM_CPU *);
  82 extern void spr_bpsr_set_handler (SIM_CPU *, USI);
  83 extern USI  spr_ccr_get_handler (SIM_CPU *);
  84 extern void spr_ccr_set_handler (SIM_CPU *, USI);
  85 extern void spr_cccr_set_handler (SIM_CPU *, USI);
  86 extern USI  spr_cccr_get_handler (SIM_CPU *);
  87 extern USI  spr_isr_get_handler (SIM_CPU *);
  88 extern void spr_isr_set_handler (SIM_CPU *, USI);
  89 extern USI  spr_sr_get_handler (SIM_CPU *, UINT);
  90 extern void spr_sr_set_handler (SIM_CPU *, UINT, USI);
  91
  92 extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
  93
  94 extern QI frvbf_set_icc_for_shift_left  (SIM_CPU *, SI, SI, QI);
  95 extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
  96
  97 /* Insn semantics.  */
  98 extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
  99 extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
 100 extern SI   frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
 101 extern SI   frvbf_iacc_cut (SIM_CPU *, DI, SI);
 102
 103 extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
 104
 105 extern SI   frvbf_scan_result (SIM_CPU *, SI);
 106 extern SI   frvbf_cut (SIM_CPU *, SI, SI, SI);
 107 extern SI   frvbf_media_cut (SIM_CPU *, DI, SI);
 108 extern SI   frvbf_media_cut_ss (SIM_CPU *, DI, SI);
 109 extern void frvbf_media_cop (SIM_CPU *, int);
 110 extern UQI  frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI);
 111
 112 extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int);
 113 extern int  frvbf_write_next_vliw_addr_to_LR;
 114
 115 extern void frvbf_set_ne_index (SIM_CPU *, int);
 116 extern void frvbf_force_update (SIM_CPU *);
 117 \f
 118 #define GETTWI GETTSI
 119 #define SETTWI SETTSI
 120 #define LEUINT LEUSI
 121 \f
 122 /* Hardware/device support.
 123    ??? Will eventually want to move device stuff to config files.  */
 124
 125 /* maintain the address of the start of the previous VLIW insn sequence.  */
 126 extern IADDR previous_vliw_pc;
 127 extern CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
 128
 129 /* Hardware status.  */
 130 #define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
 131 #define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0))
 132
 133 #define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1)
 134 #define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31))
 135 #define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31))
 136
 137 #define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1)
 138 #define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30))
 139 #define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30))
 140
 141 #define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1)
 142 #define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1)
 143 #define GET_HSR0_SA(hsr0)  (((hsr0) >> 12) & 1)
 144 #define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1)
 145 #define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1)
 146 #define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1)
 147 #define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1)
 148 #define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1)
 149 #define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1)
 150
 151 #define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
 152 #define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
 153 #define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >>  1) & 1)
 154 #define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >>  8) & 7)
 155 #define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
 156
 157 void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
 158 void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
 159 void frvbf_insn_cache_unlock (SIM_CPU *, SI);
 160 void frvbf_data_cache_unlock (SIM_CPU *, SI);
 161 void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int);
 162 void frvbf_data_cache_invalidate (SIM_CPU *, SI, int);
 163 void frvbf_data_cache_flush (SIM_CPU *, SI, int);
 164
 165 /* FR-V Interrupt classes.
 166    These are declared in order of increasing priority.  */
 167 enum frv_interrupt_class
 168 {
 169   FRV_EXTERNAL_INTERRUPT,
 170   FRV_SOFTWARE_INTERRUPT,
 171   FRV_PROGRAM_INTERRUPT,
 172   FRV_BREAK_INTERRUPT,
 173   FRV_RESET_INTERRUPT,
 174   NUM_FRV_INTERRUPT_CLASSES
 175 };
 176
 177 /* FR-V Interrupt kinds.
 178    These are declared in order of increasing priority.  */
 179 enum frv_interrupt_kind
 180 {
 181   /* External interrupts */
 182   FRV_INTERRUPT_LEVEL_1,
 183   FRV_INTERRUPT_LEVEL_2,
 184   FRV_INTERRUPT_LEVEL_3,
 185   FRV_INTERRUPT_LEVEL_4,
 186   FRV_INTERRUPT_LEVEL_5,
 187   FRV_INTERRUPT_LEVEL_6,
 188   FRV_INTERRUPT_LEVEL_7,
 189   FRV_INTERRUPT_LEVEL_8,
 190   FRV_INTERRUPT_LEVEL_9,
 191   FRV_INTERRUPT_LEVEL_10,
 192   FRV_INTERRUPT_LEVEL_11,
 193   FRV_INTERRUPT_LEVEL_12,
 194   FRV_INTERRUPT_LEVEL_13,
 195   FRV_INTERRUPT_LEVEL_14,
 196   FRV_INTERRUPT_LEVEL_15,
 197   /* Software interrupt */
 198   FRV_TRAP_INSTRUCTION,
 199   /* Program interrupts */
 200   FRV_COMMIT_EXCEPTION,
 201   FRV_DIVISION_EXCEPTION,
 202   FRV_DATA_STORE_ERROR,
 203   FRV_DATA_ACCESS_EXCEPTION,
 204   FRV_DATA_ACCESS_MMU_MISS,
 205   FRV_DATA_ACCESS_ERROR,
 206   FRV_MP_EXCEPTION,
 207   FRV_FP_EXCEPTION,
 208   FRV_MEM_ADDRESS_NOT_ALIGNED,
 209   FRV_REGISTER_EXCEPTION,
 210   FRV_MP_DISABLED,
 211   FRV_FP_DISABLED,
 212   FRV_PRIVILEGED_INSTRUCTION,
 213   FRV_ILLEGAL_INSTRUCTION,
 214   FRV_INSTRUCTION_ACCESS_EXCEPTION,
 215   FRV_INSTRUCTION_ACCESS_ERROR,
 216   FRV_INSTRUCTION_ACCESS_MMU_MISS,
 217   FRV_COMPOUND_EXCEPTION,
 218   /* Break interrupt */
 219   FRV_BREAK_EXCEPTION,
 220   /* Reset interrupt */
 221   FRV_RESET,
 222   NUM_FRV_INTERRUPT_KINDS
 223 };
 224
 225 /* FRV interrupt exception codes */
 226 enum frv_ec
 227 {
 228   FRV_EC_DATA_STORE_ERROR             = 0x00,
 229   FRV_EC_INSTRUCTION_ACCESS_MMU_MISS  = 0x01,
 230   FRV_EC_INSTRUCTION_ACCESS_ERROR     = 0x02,
 231   FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03,
 232   FRV_EC_PRIVILEGED_INSTRUCTION       = 0x04,
 233   FRV_EC_ILLEGAL_INSTRUCTION          = 0x05,
 234   FRV_EC_FP_DISABLED                  = 0x06,
 235   FRV_EC_MP_DISABLED                  = 0x07,
 236   FRV_EC_MEM_ADDRESS_NOT_ALIGNED      = 0x0b,
 237   FRV_EC_REGISTER_EXCEPTION           = 0x0c,
 238   FRV_EC_FP_EXCEPTION                 = 0x0d,
 239   FRV_EC_MP_EXCEPTION                 = 0x0e,
 240   FRV_EC_DATA_ACCESS_ERROR            = 0x10,
 241   FRV_EC_DATA_ACCESS_MMU_MISS         = 0x11,
 242   FRV_EC_DATA_ACCESS_EXCEPTION        = 0x12,
 243   FRV_EC_DIVISION_EXCEPTION           = 0x13,
 244   FRV_EC_COMMIT_EXCEPTION             = 0x14,
 245   FRV_EC_NOT_EXECUTED                 = 0x1f,
 246   FRV_EC_INTERRUPT_LEVEL_1            = FRV_EC_NOT_EXECUTED,
 247   FRV_EC_INTERRUPT_LEVEL_2            = FRV_EC_NOT_EXECUTED,
 248   FRV_EC_INTERRUPT_LEVEL_3            = FRV_EC_NOT_EXECUTED,
 249   FRV_EC_INTERRUPT_LEVEL_4            = FRV_EC_NOT_EXECUTED,
 250   FRV_EC_INTERRUPT_LEVEL_5            = FRV_EC_NOT_EXECUTED,
 251   FRV_EC_INTERRUPT_LEVEL_6            = FRV_EC_NOT_EXECUTED,
 252   FRV_EC_INTERRUPT_LEVEL_7            = FRV_EC_NOT_EXECUTED,
 253   FRV_EC_INTERRUPT_LEVEL_8            = FRV_EC_NOT_EXECUTED,
 254   FRV_EC_INTERRUPT_LEVEL_9            = FRV_EC_NOT_EXECUTED,
 255   FRV_EC_INTERRUPT_LEVEL_10           = FRV_EC_NOT_EXECUTED,
 256   FRV_EC_INTERRUPT_LEVEL_11           = FRV_EC_NOT_EXECUTED,
 257   FRV_EC_INTERRUPT_LEVEL_12           = FRV_EC_NOT_EXECUTED,
 258   FRV_EC_INTERRUPT_LEVEL_13           = FRV_EC_NOT_EXECUTED,
 259   FRV_EC_INTERRUPT_LEVEL_14           = FRV_EC_NOT_EXECUTED,
 260   FRV_EC_INTERRUPT_LEVEL_15           = FRV_EC_NOT_EXECUTED,
 261   FRV_EC_TRAP_INSTRUCTION             = FRV_EC_NOT_EXECUTED,
 262   FRV_EC_COMPOUND_EXCEPTION           = FRV_EC_NOT_EXECUTED,
 263   FRV_EC_BREAK_EXCEPTION              = FRV_EC_NOT_EXECUTED,
 264   FRV_EC_RESET                        = FRV_EC_NOT_EXECUTED
 265 };
 266
 267 /* FR-V Interrupt.
 268    This struct contains enough information to describe a particular interrupt
 269    occurance.  */
 270 struct frv_interrupt
 271 {
 272   enum frv_interrupt_kind  kind;
 273   enum frv_ec              ec;
 274   enum frv_interrupt_class iclass;
 275   unsigned char deferred;
 276   unsigned char precise;
 277   unsigned char handler_offset;
 278 };
 279
 280 /* FR-V Interrupt table.
 281    Describes the interrupts supported by the FR-V.  */
 282 extern struct frv_interrupt frv_interrupt_table[];
 283
 284 /* FR-V Interrupt State.
 285    Interrupts are queued during execution of parallel insns and the interupt(s)
 286    to be handled determined by analysing the queue after each VLIW insn.  */
 287 #define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now.  */
 288
 289 /* register_exception codes */
 290 enum frv_rec
 291 {
 292   FRV_REC_UNIMPLEMENTED = 0,
 293   FRV_REC_UNALIGNED     = 1
 294 };
 295
 296 /* instruction_access_exception codes */
 297 enum frv_iaec
 298 {
 299   FRV_IAEC_PROTECT_VIOLATION = 1
 300 };
 301
 302 /* data_access_exception codes */
 303 enum frv_daec
 304 {
 305   FRV_DAEC_PROTECT_VIOLATION = 1
 306 };
 307
 308 /* division_exception ISR codes */
 309 enum frv_dtt
 310 {
 311   FRV_DTT_NO_EXCEPTION     = 0,
 312   FRV_DTT_DIVISION_BY_ZERO = 1,
 313   FRV_DTT_OVERFLOW         = 2,
 314   FRV_DTT_BOTH             = 3
 315 };
 316
 317 /* data written during an insn causing an interrupt */
 318 struct frv_data_written
 319 {
 320   USI words[4]; /* Actual data in words */
 321   int length;   /* length of data written */
 322 };
 323
 324 /* fp_exception info */
 325 /* Trap codes for FSR0 and FQ registers.  */
 326 enum frv_fsr_traps
 327 {
 328   FSR_INVALID_OPERATION = 0x20,
 329   FSR_OVERFLOW          = 0x10,
 330   FSR_UNDERFLOW         = 0x08,
 331   FSR_DIVISION_BY_ZERO  = 0x04,
 332   FSR_INEXACT           = 0x02,
 333   FSR_DENORMAL_INPUT    = 0x01,
 334   FSR_NO_EXCEPTION      = 0
 335 };
 336
 337 /* Floating point trap types for FSR.  */
 338 enum frv_fsr_ftt
 339 {
 340   FTT_NONE               = 0,
 341   FTT_IEEE_754_EXCEPTION = 1,
 342   FTT_UNIMPLEMENTED_FPOP = 3,
 343   FTT_SEQUENCE_ERROR     = 4,
 344   FTT_INVALID_FR         = 6,
 345   FTT_DENORMAL_INPUT     = 7
 346 };
 347
 348 struct frv_fp_exception_info
 349 {
 350   enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
 351   enum frv_fsr_ftt   ftt;      /* floating point trap type */
 352 };
 353
 354 struct frv_interrupt_queue_element
 355 {
 356   enum frv_interrupt_kind kind;      /* kind of interrupt */
 357   IADDR                   vpc;       /* address of insn causing interrupt */
 358   int                     slot;      /* VLIW slot containing the insn.  */
 359   USI                     eaddress;  /* address of data access */
 360   union {
 361     enum frv_rec  rec;               /* register exception code */
 362     enum frv_iaec iaec;              /* insn access exception code */
 363     enum frv_daec daec;              /* data access exception code */
 364     enum frv_dtt  dtt;               /* division exception code */
 365     struct frv_fp_exception_info fp_info;
 366     struct frv_data_written data_written;
 367   } u;
 368 };
 369
 370 struct frv_interrupt_timer
 371 {
 372   int enabled;
 373   unsigned value;
 374   unsigned current;
 375   enum frv_interrupt_kind interrupt;
 376 };
 377
 378 struct frv_interrupt_state
 379 {
 380   /* The interrupt queue */
 381   struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE];
 382   int queue_index;
 383
 384   /* interrupt queue element causing imprecise interrupt.  */
 385   struct frv_interrupt_queue_element *imprecise_interrupt;
 386
 387   /* interrupt timer.  */
 388   struct frv_interrupt_timer timer;
 389
 390   /* The last data written stored as an array of words.  */
 391   struct frv_data_written data_written;
 392
 393   /* The vliw slot of the insn causing the interrupt.  */
 394   int slot;
 395
 396   /* target register index for non excepting insns.  */
 397 #define NE_NOFLAG (-1)
 398   int ne_index;
 399
 400   /* Accumulated NE flags for non excepting floating point insns.  */
 401   SI f_ne_flags[2];
 402 };
 403
 404 extern struct frv_interrupt_state frv_interrupt_state;
 405
 406 /* Macros to manipulate the PSR.  */
 407 #define GET_PSR() GET_H_SPR (H_SPR_PSR)
 408
 409 #define SET_PSR_ET(psr, et) (           \
 410   (psr) = ((psr) & ~0x1) | ((et) & 0x1) \
 411 )
 412
 413 #define GET_PSR_PS(psr) (((psr) >> 1) & 1)
 414
 415 #define SET_PSR_S(psr, s) (                          \
 416   (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \
 417 )
 418
 419 /* Macros to handle the ISR register.  */
 420 #define GET_ISR() GET_H_SPR (H_SPR_ISR)
 421 #define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr))
 422
 423 #define GET_ISR_EDE(isr) (((isr) >> 5) & 1)
 424
 425 #define GET_ISR_DTT(isr) (((isr) >> 3) & 3)
 426 #define SET_ISR_DTT(isr, dtt) (                        \
 427   (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \
 428 )
 429
 430 #define SET_ISR_AEXC(isr) ((isr) |= (1 << 2))
 431
 432 #define GET_ISR_EMAM(isr) ((isr) & 1)
 433
 434 /* Macros to handle exception status registers.
 435    Get and set the hardware directly, since we may be getting/setting fields
 436    which are not accessible to the user.  */
 437 #define GET_ESR(index) \
 438   (CPU (h_spr[H_SPR_ESR0 + (index)]))
 439 #define SET_ESR(index, esr) \
 440   (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr))
 441
 442 #define SET_ESR_VALID(esr) ((esr) |= 1)
 443 #define CLEAR_ESR_VALID(esr) ((esr) &= ~1)
 444
 445 #define SET_ESR_EC(esr, ec) (                           \
 446   (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
 447 )
 448
 449 #define SET_ESR_REC(esr, rec) (                        \
 450   (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
 451 )
 452
 453 #define SET_ESR_IAEC(esr, iaec) (                       \
 454   (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
 455 )
 456
 457 #define SET_ESR_DAEC(esr, daec) (                       \
 458   (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
 459 )
 460
 461 #define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
 462 #define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))
 463
 464 #define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
 465 #define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
 466 #define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))
 467
 468 #define GET_ESR_EDN(esr) ( \
 469   ((esr) >> 13) & 0xf      \
 470 )
 471 #define SET_ESR_EDN(esr, edn) (                       \
 472   (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
 473 )
 474
 475 #define SET_EPCR(index, address) \
 476   (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))
 477
 478 #define SET_EAR(index, address) \
 479   (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))
 480
 481 #define SET_EDR(index, edr) \
 482   (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))
 483
 484 #define GET_ESFR(index) \
 485   (CPU (h_spr[H_SPR_ESFR0 + (index)]))
 486 #define SET_ESFR(index, esfr) \
 487   (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))
 488
 489 #define GET_ESFR_FLAG(findex) ( \
 490   (findex) > 31 ? \
 491     ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
 492     : \
 493     ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
 494 )
 495 #define SET_ESFR_FLAG(findex) ( \
 496   (findex) > 31 ? \
 497     (CPU (h_spr[H_SPR_ESFR0]) = \
 498       (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
 499     ) : \
 500     (CPU (h_spr[H_SPR_ESFR1]) = \
 501       (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
 502     ) \
 503 )
 504
 505 /* The FSR registers.
 506    Get and set the hardware directly, since we may be getting/setting fields
 507    which are not accessible to the user.  */
 508 #define GET_FSR(index) \
 509   (CPU (h_spr[H_SPR_FSR0 + (index)]))
 510 #define SET_FSR(index, fsr) \
 511   (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
 512
 513 #define GET_FSR_TEM(fsr) ( \
 514   ((fsr) >> 24) & 0x3f     \
 515 )
 516
 517 #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
 518 #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)
 519
 520 #define SET_FSR_FTT(fsr, ftt) (                          \
 521   (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
 522 )
 523
 524 #define GET_FSR_AEXC(fsr) ( \
 525   ((fsr) >> 10) & 0x3f      \
 526 )
 527 #define SET_FSR_AEXC(fsr, aexc) (                          \
 528   (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
 529 )
 530
 531 /* SIMD instruction exception codes for FQ.  */
 532 enum frv_sie
 533 {
 534   SIE_NIL   = 0,
 535   SIE_FRi   = 1,
 536   SIE_FRi_1 = 2
 537 };
 538
 539 /* MIV field of FQ.  */
 540 enum frv_miv
 541 {
 542   MIV_FLOAT = 0,
 543   MIV_MEDIA = 1
 544 };
 545
 546 /* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
 547    index here refers to the low order 32 bit element.
 548    Get and set the hardware directly, since we may be getting/setting fields
 549    which are not accessible to the user.  */
 550 #define GET_FQ(index) \
 551   (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
 552 #define SET_FQ(index, fq) \
 553   (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
 554
 555 #define SET_FQ_MIV(fq, miv) (                          \
 556   (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
 557 )
 558
 559 #define SET_FQ_SIE(fq, sie) (                          \
 560   (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
 561 )
 562
 563 #define SET_FQ_FTT(fq, ftt) (                        \
 564   (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
 565 )
 566
 567 #define SET_FQ_CEXC(fq, cexc) (                         \
 568   (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
 569 )
 570
 571 #define GET_FQ_VALID(fq) ((fq) & 1)
 572 #define SET_FQ_VALID(fq) ((fq) |= 1)
 573
 574 #define SET_FQ_OPC(index, insn) \
 575   (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))
 576
 577 /* mp_exception support.  */
 578 /* Media trap types for MSR.  */
 579 enum frv_msr_mtt
 580 {
 581   MTT_NONE                = 0,
 582   MTT_OVERFLOW            = 1,
 583   MTT_ACC_NOT_ALIGNED     = 2,
 584   MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED.  */
 585   MTT_CR_NOT_ALIGNED      = 3,
 586   MTT_UNIMPLEMENTED_MPOP  = 5,
 587   MTT_INVALID_FR          = 6
 588 };
 589
 590 /* Media status registers.
 591    Get and set the hardware directly, since we may be getting/setting fields
 592    which are not accessible to the user.  */
 593 #define GET_MSR(index) \
 594   (CPU (h_spr[H_SPR_MSR0 + (index)]))
 595 #define SET_MSR(index, msr) \
 596   (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))
 597
 598 #define GET_MSR_AOVF(msr) ((msr) & 1)
 599 #define SET_MSR_AOVF(msr) ((msr) |=  1)
 600
 601 #define GET_MSR_OVF(msr) ( \
 602   ((msr) >> 1) & 0x1       \
 603 )
 604 #define SET_MSR_OVF(msr) ( \
 605   (msr) |= (1 << 1)        \
 606 )
 607 #define CLEAR_MSR_OVF(msr) ( \
 608   (msr) &= ~(1 << 1)         \
 609 )
 610
 611 #define OR_MSR_SIE(msr, sie) (  \
 612   (msr) |= (((sie) & 0xf) << 2) \
 613 )
 614 #define CLEAR_MSR_SIE(msr) ( \
 615   (msr) &= ~(0xf << 2)       \
 616 )
 617
 618 #define GET_MSR_MTT(msr) ( \
 619   ((msr) >> 12) & 0x7      \
 620 )
 621 #define SET_MSR_MTT(msr, mtt) (                          \
 622   (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
 623 )
 624 #define GET_MSR_EMCI(msr) ( \
 625   ((msr) >> 24) & 0x1       \
 626 )
 627 #define GET_MSR_MPEM(msr) ( \
 628   ((msr) >> 27) & 0x1        \
 629 )
 630 #define GET_MSR_SRDAV(msr) ( \
 631   ((msr) >> 28) & 0x1        \
 632 )
 633 #define GET_MSR_RDAV(msr) ( \
 634   ((msr) >> 29) & 0x1       \
 635 )
 636 #define GET_MSR_RD(msr) ( \
 637   ((msr) >> 30) & 0x3     \
 638 )
 639
 640 void frvbf_media_register_not_aligned (SIM_CPU *);
 641 void frvbf_media_acc_not_aligned (SIM_CPU *);
 642 void frvbf_media_cr_not_aligned (SIM_CPU *);
 643 void frvbf_media_overflow (SIM_CPU *, int);
 644 SI frvbf_media_average (SIM_CPU *, SI, SI);
 645
 646 /* Functions for queuing and processing interrupts.  */
 647 struct frv_interrupt_queue_element *
 648 frv_queue_break_interrupt (SIM_CPU *);
 649
 650 struct frv_interrupt_queue_element *
 651 frv_queue_software_interrupt (SIM_CPU *, SI);
 652
 653 struct frv_interrupt_queue_element *
 654 frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 655
 656 struct frv_interrupt_queue_element *
 657 frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 658
 659 struct frv_interrupt_queue_element *
 660 frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 661
 662 struct frv_interrupt_queue_element *
 663 frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 664
 665 struct frv_interrupt_queue_element *
 666 frv_queue_float_disabled_interrupt (SIM_CPU *);
 667
 668 struct frv_interrupt_queue_element *
 669 frv_queue_media_disabled_interrupt (SIM_CPU *);
 670
 671 struct frv_interrupt_queue_element *
 672 frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
 673
 674 struct frv_interrupt_queue_element *
 675 frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec);
 676
 677 struct frv_interrupt_queue_element *
 678 frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);
 679
 680 struct frv_interrupt_queue_element *
 681 frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
 682
 683 struct frv_interrupt_queue_element *
 684 frv_queue_data_access_exception_interrupt (SIM_CPU *);
 685
 686 struct frv_interrupt_queue_element *
 687 frv_queue_instruction_access_error_interrupt (SIM_CPU *);
 688
 689 struct frv_interrupt_queue_element *
 690 frv_queue_instruction_access_exception_interrupt (SIM_CPU *);
 691
 692 struct frv_interrupt_queue_element *
 693 frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);
 694
 695 enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
 696
 697 struct frv_interrupt_queue_element *
 698 frv_queue_division_exception_interrupt (SIM_CPU *, enum frv_dtt);
 699
 700 struct frv_interrupt_queue_element *
 701 frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
 702
 703 void
 704 frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *);
 705
 706 void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int);
 707 void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *);
 708
 709 void frv_process_interrupts (SIM_CPU *);
 710
 711 void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR);
 712 void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR);
 713 void frv_program_interrupt (
 714   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 715 );
 716 void frv_software_interrupt (
 717   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 718 );
 719 void frv_external_interrupt (
 720   SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
 721 );
 722 void frv_program_or_software_interrupt (
 723   SIM_CPU *, struct frv_interrupt *, IADDR
 724 );
 725 void frv_clear_interrupt_classes (
 726   enum frv_interrupt_class, enum frv_interrupt_class
 727 );
 728
 729 void
 730 frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *);
 731
 732 /* Special purpose traps.  */
 733 #define TRAP_SYSCALL    0x80
 734 #define TRAP_BREAKPOINT 0x81
 735 #define TRAP_REGDUMP1   0x82
 736 #define TRAP_REGDUMP2   0x83
 737
 738 /* Handle the trap insns  */
 739 void frv_itrap (SIM_CPU *, PCADDR, USI, int);
 740 void frv_mtrap (SIM_CPU *);
 741 /* Handle the break insn.  */
 742 void frv_break (SIM_CPU *);
 743 /* Handle the rett insn.  */
 744 USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
 745
 746 /* Parallel write queue flags.  */
 747 #define FRV_WRITE_QUEUE_FORCE_WRITE 1
 748
 749 #define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)
 750
 751 /* Functions and macros for handling non-excepting instruction side effects.
 752    Get and set the hardware directly, since we may be getting/setting fields
 753    which are not accessible to the user.  */
 754 #define GET_NECR()           (GET_H_SPR (H_SPR_NECR))
 755 #define GET_NECR_ELOS(necr)  (((necr) >> 6) & 1)
 756 #define GET_NECR_NEN(necr)   (((necr) >> 1) & 0x1f)
 757 #define GET_NECR_VALID(necr) (((necr)     ) & 1)
 758
 759 #define NO_NESR    (-1)
 760 /* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
 761    Architecture volume 1.  */
 762 #define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
 763 #define NESR_REGISTER_NOT_ALIGNED    0x1
 764 #define NESR_UQI_SIZE 0
 765 #define NESR_QI_SIZE  1
 766 #define NESR_UHI_SIZE 2
 767 #define NESR_HI_SIZE  3
 768 #define NESR_SI_SIZE  4
 769 #define NESR_DI_SIZE  5
 770 #define NESR_XI_SIZE  6
 771
 772 #define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
 773 #define SET_NESR(index, value) (                          \
 774   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,    \
 775                          H_SPR_NESR0 + (index), (value)), \
 776   frvbf_force_update (current_cpu)                        \
 777 )
 778 #define GET_NESR_VALID(nesr) ((nesr) & 1)
 779 #define SET_NESR_VALID(nesr) ((nesr) |= 1)
 780
 781 #define SET_NESR_EAV(nesr)   ((nesr) |= (1 << 31))
 782
 783 #define GET_NESR_FR(nesr)    (((nesr) >> 30) & 1)
 784 #define SET_NESR_FR(nesr)    ((nesr) |= (1 << 30))
 785 #define CLEAR_NESR_FR(nesr)  ((nesr) &= ~(1 << 30))
 786
 787 #define GET_NESR_DRN(nesr)   (((nesr) >> 24) & 0x3f)
 788 #define SET_NESR_DRN(nesr, drn) (                            \
 789   (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
 790 )
 791
 792 #define SET_NESR_SIZE(nesr, data_size) (                         \
 793   (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
 794 )
 795
 796 #define SET_NESR_NEAN(nesr, index) (                           \
 797   (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
 798 )
 799
 800 #define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
 801 #define SET_NESR_DAEC(nesr, daec) (                   \
 802   (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
 803 )
 804
 805 #define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
 806 #define SET_NESR_REC(nesr, rec) (                    \
 807   (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
 808 )
 809
 810 #define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
 811 #define SET_NESR_EC(nesr, ec) (                       \
 812   (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
 813 )
 814
 815 #define SET_NEEAR(index, address) ( \
 816   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set,       \
 817                          H_SPR_NEEAR0 + (index), (address)), \
 818   frvbf_force_update (current_cpu)                           \
 819 )
 820
 821 #define GET_NE_FLAGS(flags, NE_base) (   \
 822   (flags)[0] = GET_H_SPR ((NE_base)),    \
 823   (flags)[1] = GET_H_SPR ((NE_base) + 1) \
 824 )
 825 #define SET_NE_FLAGS(NE_base, flags) ( \
 826   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base),      \
 827                          (flags)[0]),                                  \
 828   frvbf_force_update (current_cpu),                                    \
 829   sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1,  \
 830                          (flags)[1]),                                  \
 831   frvbf_force_update (current_cpu)                                     \
 832 )
 833
 834 #define GET_NE_FLAG(flags, index) (    \
 835   (index) > 31 ?                       \
 836     ((flags[0] >> ((index) - 32)) & 1) \
 837   :                                    \
 838     ((flags[1] >> (index)) & 1)        \
 839 )
 840 #define SET_NE_FLAG(flags, index) (       \
 841   (index) > 31 ?                          \
 842     ((flags)[0] |= (1 << ((index) - 32))) \
 843   :                                       \
 844     ((flags)[1] |= (1 << (index)))        \
 845 )
 846 #define CLEAR_NE_FLAG(flags, index) (      \
 847   (index) > 31 ?                           \
 848     ((flags)[0] &= ~(1 << ((index) - 32))) \
 849   :                                        \
 850     ((flags)[1] &= ~(1 << (index)))        \
 851 )
 852
 853 BI   frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
 854 void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
 855 SI   frvbf_check_acc_range (SIM_CPU *, SI);
 856 void frvbf_check_swap_address (SIM_CPU *, SI);
 857
 858 void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
 859 void frvbf_commit (SIM_CPU *, SI, BI);
 860
 861 void frvbf_fpu_error (CGEN_FPU *, int);
 862
 863 void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *);
 864
 865 extern int insns_in_slot[];
 866
 867 #define COUNT_INSNS_IN_SLOT(slot) \
 868 {                                 \
 869   if (WITH_PROFILE_MODEL_P)       \
 870     ++insns_in_slot[slot];        \
 871 }
 872
 873 #define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
 874
 875 /* Multiple loads and stores.  */
 876 void frvbf_load_quad_GR (SIM_CPU *, PCADDR, SI, SI);
 877 void frvbf_load_quad_FRint (SIM_CPU *, PCADDR, SI, SI);
 878 void frvbf_load_quad_CPR (SIM_CPU *, PCADDR, SI, SI);
 879 void frvbf_store_quad_GR (SIM_CPU *, PCADDR, SI, SI);
 880 void frvbf_store_quad_FRint (SIM_CPU *, PCADDR, SI, SI);
 881 void frvbf_store_quad_CPR (SIM_CPU *, PCADDR, SI, SI);
 882
 883 /* Memory and cache support.  */
 884 QI  frvbf_read_mem_QI  (SIM_CPU *, IADDR, SI);
 885 UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI);
 886 HI  frvbf_read_mem_HI  (SIM_CPU *, IADDR, SI);
 887 UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI);
 888 SI  frvbf_read_mem_SI  (SIM_CPU *, IADDR, SI);
 889 SI  frvbf_read_mem_WI  (SIM_CPU *, IADDR, SI);
 890 DI  frvbf_read_mem_DI  (SIM_CPU *, IADDR, SI);
 891 DF  frvbf_read_mem_DF  (SIM_CPU *, IADDR, SI);
 892
 893 USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);
 894
 895 void frvbf_write_mem_QI  (SIM_CPU *, IADDR, SI, QI);
 896 void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI);
 897 void frvbf_write_mem_HI  (SIM_CPU *, IADDR, SI, HI);
 898 void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI);
 899 void frvbf_write_mem_SI  (SIM_CPU *, IADDR, SI, SI);
 900 void frvbf_write_mem_WI  (SIM_CPU *, IADDR, SI, SI);
 901 void frvbf_write_mem_DI  (SIM_CPU *, IADDR, SI, DI);
 902 void frvbf_write_mem_DF  (SIM_CPU *, IADDR, SI, DF);
 903
 904 void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI);
 905 void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI);
 906 void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI);
 907 void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI);
 908 void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF);
 909 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
 910
 911 void frv_set_write_queue_slot (SIM_CPU *current_cpu);
 912
 913 /* FRV specific options.  */
 914 extern const OPTION frv_options[];
 915
 916 #endif /* FRV_SIM_H */