opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2022 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43 typedef struct instr_info instr_info;
  44
  45 static void dofloat (instr_info *, int);
  46 static void OP_ST (instr_info *, int, int);
  47 static void OP_STi (instr_info *, int, int);
  48 static int putop (instr_info *, const char *, int);
  49 static void oappend_with_style (instr_info *, const char *,
  50                                 enum disassembler_style);
  51 static void oappend (instr_info *, const char *);
  52 static void append_seg (instr_info *);
  53 static void OP_indirE (instr_info *, int, int);
  54 static void OP_E_memory (instr_info *, int, int);
  55 static void OP_E (instr_info *, int, int);
  56 static void OP_G (instr_info *, int, int);
  57 static bfd_vma get64 (instr_info *);
  58 static bfd_signed_vma get32 (instr_info *);
  59 static bfd_signed_vma get32s (instr_info *);
  60 static int get16 (instr_info *);
  61 static void set_op (instr_info *, bfd_vma, bool);
  62 static void OP_Skip_MODRM (instr_info *, int, int);
  63 static void OP_REG (instr_info *, int, int);
  64 static void OP_IMREG (instr_info *, int, int);
  65 static void OP_I (instr_info *, int, int);
  66 static void OP_I64 (instr_info *, int, int);
  67 static void OP_sI (instr_info *, int, int);
  68 static void OP_J (instr_info *, int, int);
  69 static void OP_SEG (instr_info *, int, int);
  70 static void OP_DIR (instr_info *, int, int);
  71 static void OP_OFF (instr_info *, int, int);
  72 static void OP_OFF64 (instr_info *, int, int);
  73 static void ptr_reg (instr_info *, int, int);
  74 static void OP_ESreg (instr_info *, int, int);
  75 static void OP_DSreg (instr_info *, int, int);
  76 static void OP_C (instr_info *, int, int);
  77 static void OP_D (instr_info *, int, int);
  78 static void OP_T (instr_info *, int, int);
  79 static void OP_MMX (instr_info *, int, int);
  80 static void OP_XMM (instr_info *, int, int);
  81 static void OP_EM (instr_info *, int, int);
  82 static void OP_EX (instr_info *, int, int);
  83 static void OP_EMC (instr_info *, int,int);
  84 static void OP_MXC (instr_info *, int,int);
  85 static void OP_MS (instr_info *, int, int);
  86 static void OP_XS (instr_info *, int, int);
  87 static void OP_M (instr_info *, int, int);
  88 static void OP_VEX (instr_info *, int, int);
  89 static void OP_VexR (instr_info *, int, int);
  90 static void OP_VexW (instr_info *, int, int);
  91 static void OP_Rounding (instr_info *, int, int);
  92 static void OP_REG_VexI4 (instr_info *, int, int);
  93 static void OP_VexI4 (instr_info *, int, int);
  94 static void PCLMUL_Fixup (instr_info *, int, int);
  95 static void VPCMP_Fixup (instr_info *, int, int);
  96 static void VPCOM_Fixup (instr_info *, int, int);
  97 static void OP_0f07 (instr_info *, int, int);
  98 static void OP_Monitor (instr_info *, int, int);
  99 static void OP_Mwait (instr_info *, int, int);
 100 static void NOP_Fixup (instr_info *, int, int);
 101 static void OP_3DNowSuffix (instr_info *, int, int);
 102 static void CMP_Fixup (instr_info *, int, int);
 103 static void BadOp (instr_info *);
 104 static void REP_Fixup (instr_info *, int, int);
 105 static void SEP_Fixup (instr_info *, int, int);
 106 static void BND_Fixup (instr_info *, int, int);
 107 static void NOTRACK_Fixup (instr_info *, int, int);
 108 static void HLE_Fixup1 (instr_info *, int, int);
 109 static void HLE_Fixup2 (instr_info *, int, int);
 110 static void HLE_Fixup3 (instr_info *, int, int);
 111 static void CMPXCHG8B_Fixup (instr_info *, int, int);
 112 static void XMM_Fixup (instr_info *, int, int);
 113 static void FXSAVE_Fixup (instr_info *, int, int);
 114
 115 static void MOVSXD_Fixup (instr_info *, int, int);
 116 static void DistinctDest_Fixup (instr_info *, int, int);
 117 static void PREFETCHI_Fixup (instr_info *, int, int);
 118
 119 /* This character is used to encode style information within the output
 120    buffers.  See oappend_insert_style for more details.  */
 121 #define STYLE_MARKER_CHAR '\002'
 122
 123 /* The maximum operand buffer size.  */
 124 #define MAX_OPERAND_BUFFER_SIZE 128
 125
 126 struct dis_private {
 127   /* Points to first byte not fetched.  */
 128   bfd_byte *max_fetched;
 129   bfd_byte the_buffer[MAX_MNEM_SIZE];
 130   bfd_vma insn_start;
 131   int orig_sizeflag;
 132   OPCODES_SIGJMP_BUF bailout;
 133 };
 134
 135 enum address_mode
 136 {
 137   mode_16bit,
 138   mode_32bit,
 139   mode_64bit
 140 };
 141
 142 enum x86_64_isa
 143 {
 144   amd64 = 1,
 145   intel64
 146 };
 147
 148 struct instr_info
 149 {
 150   enum address_mode address_mode;
 151
 152   /* Flags for the prefixes for the current instruction.  See below.  */
 153   int prefixes;
 154
 155   /* REX prefix the current instruction.  See below.  */
 156   unsigned char rex;
 157   /* Bits of REX we've already used.  */
 158   unsigned char rex_used;
 159
 160   bool need_modrm;
 161   bool need_vex;
 162   bool has_sib;
 163
 164   /* Flags for ins->prefixes which we somehow handled when printing the
 165      current instruction.  */
 166   int used_prefixes;
 167
 168   /* Flags for EVEX bits which we somehow handled when printing the
 169      current instruction.  */
 170   int evex_used;
 171
 172   char obuf[MAX_OPERAND_BUFFER_SIZE];
 173   char *obufp;
 174   char *mnemonicendp;
 175   unsigned char *start_codep;
 176   unsigned char *insn_codep;
 177   unsigned char *codep;
 178   unsigned char *end_codep;
 179   signed char last_lock_prefix;
 180   signed char last_repz_prefix;
 181   signed char last_repnz_prefix;
 182   signed char last_data_prefix;
 183   signed char last_addr_prefix;
 184   signed char last_rex_prefix;
 185   signed char last_seg_prefix;
 186   signed char fwait_prefix;
 187   /* The active segment register prefix.  */
 188   unsigned char active_seg_prefix;
 189
 190 #define MAX_CODE_LENGTH 15
 191   /* We can up to 14 ins->prefixes since the maximum instruction length is
 192      15bytes.  */
 193   unsigned char all_prefixes[MAX_CODE_LENGTH - 1];
 194   disassemble_info *info;
 195
 196   struct
 197   {
 198     int mod;
 199     int reg;
 200     int rm;
 201   }
 202   modrm;
 203
 204   struct
 205   {
 206     int scale;
 207     int index;
 208     int base;
 209   }
 210   sib;
 211
 212   struct
 213   {
 214     int register_specifier;
 215     int length;
 216     int prefix;
 217     int mask_register_specifier;
 218     int ll;
 219     bool w;
 220     bool evex;
 221     bool r;
 222     bool v;
 223     bool zeroing;
 224     bool b;
 225     bool no_broadcast;
 226   }
 227   vex;
 228
 229   /* Remember if the current op is a jump instruction.  */
 230   bool op_is_jump;
 231
 232   bool two_source_ops;
 233
 234   unsigned char op_ad;
 235   signed char op_index[MAX_OPERANDS];
 236   bool op_riprel[MAX_OPERANDS];
 237   char *op_out[MAX_OPERANDS];
 238   bfd_vma op_address[MAX_OPERANDS];
 239   bfd_vma start_pc;
 240
 241   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 242    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 243    *   section of the "Virtual 8086 Mode" chapter.)
 244    * 'pc' should be the address of this instruction, it will
 245    *   be used to print the target address if this is a relative jump or call
 246    * The function returns the length of this instruction in bytes.
 247    */
 248   char intel_syntax;
 249   bool intel_mnemonic;
 250   char open_char;
 251   char close_char;
 252   char separator_char;
 253   char scale_char;
 254
 255   enum x86_64_isa isa64;
 256 };
 257
 258 /* Mark parts used in the REX prefix.  When we are testing for
 259    empty prefix (for 8bit register REX extension), just mask it
 260    out.  Otherwise test for REX bit is excuse for existence of REX
 261    only in case value is nonzero.  */
 262 #define USED_REX(value)                                 \
 263   {                                                     \
 264     if (value)                                          \
 265       {                                                 \
 266         if ((ins->rex & value))                         \
 267           ins->rex_used |= (value) | REX_OPCODE;        \
 268       }                                                 \
 269     else                                                \
 270       ins->rex_used |= REX_OPCODE;                      \
 271   }
 272
 273
 274 #define EVEX_b_used 1
 275 #define EVEX_len_used 2
 276
 277 /* Flags stored in PREFIXES.  */
 278 #define PREFIX_REPZ 1
 279 #define PREFIX_REPNZ 2
 280 #define PREFIX_CS 4
 281 #define PREFIX_SS 8
 282 #define PREFIX_DS 0x10
 283 #define PREFIX_ES 0x20
 284 #define PREFIX_FS 0x40
 285 #define PREFIX_GS 0x80
 286 #define PREFIX_LOCK 0x100
 287 #define PREFIX_DATA 0x200
 288 #define PREFIX_ADDR 0x400
 289 #define PREFIX_FWAIT 0x800
 290
 291 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 292    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 293    on error.  */
 294 #define FETCH_DATA(info, addr) \
 295   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 296    ? 1 : fetch_data ((info), (addr)))
 297
 298 static int
 299 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 300 {
 301   int status;
 302   struct dis_private *priv = (struct dis_private *) info->private_data;
 303   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 304
 305   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 306     status = (*info->read_memory_func) (start,
 307                                         priv->max_fetched,
 308                                         addr - priv->max_fetched,
 309                                         info);
 310   else
 311     status = -1;
 312   if (status != 0)
 313     {
 314       /* If we did manage to read at least one byte, then
 315          print_insn_i386 will do something sensible.  Otherwise, print
 316          an error.  We do that here because this is where we know
 317          STATUS.  */
 318       if (priv->max_fetched == priv->the_buffer)
 319         (*info->memory_error_func) (status, start, info);
 320       OPCODES_SIGLONGJMP (priv->bailout, 1);
 321     }
 322   else
 323     priv->max_fetched = addr;
 324   return 1;
 325 }
 326
 327 /* Possible values for prefix requirement.  */
 328 #define PREFIX_IGNORED_SHIFT    16
 329 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 330 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 331 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 332 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 333 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 334
 335 /* Opcode prefixes.  */
 336 #define PREFIX_OPCODE           (PREFIX_REPZ \
 337                                  | PREFIX_REPNZ \
 338                                  | PREFIX_DATA)
 339
 340 /* Prefixes ignored.  */
 341 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 342                                  | PREFIX_IGNORED_REPNZ \
 343                                  | PREFIX_IGNORED_DATA)
 344
 345 #define XX { NULL, 0 }
 346 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 347
 348 #define Eb { OP_E, b_mode }
 349 #define Ebnd { OP_E, bnd_mode }
 350 #define EbS { OP_E, b_swap_mode }
 351 #define EbndS { OP_E, bnd_swap_mode }
 352 #define Ev { OP_E, v_mode }
 353 #define Eva { OP_E, va_mode }
 354 #define Ev_bnd { OP_E, v_bnd_mode }
 355 #define EvS { OP_E, v_swap_mode }
 356 #define Ed { OP_E, d_mode }
 357 #define Edq { OP_E, dq_mode }
 358 #define Edb { OP_E, db_mode }
 359 #define Edw { OP_E, dw_mode }
 360 #define Eq { OP_E, q_mode }
 361 #define indirEv { OP_indirE, indir_v_mode }
 362 #define indirEp { OP_indirE, f_mode }
 363 #define stackEv { OP_E, stack_v_mode }
 364 #define Em { OP_E, m_mode }
 365 #define Ew { OP_E, w_mode }
 366 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 367 #define Ma { OP_M, a_mode }
 368 #define Mb { OP_M, b_mode }
 369 #define Md { OP_M, d_mode }
 370 #define Mdq { OP_M, dq_mode }
 371 #define Mo { OP_M, o_mode }
 372 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 373 #define Mq { OP_M, q_mode }
 374 #define Mv { OP_M, v_mode }
 375 #define Mv_bnd { OP_M, v_bndmk_mode }
 376 #define Mw { OP_M, w_mode }
 377 #define Mx { OP_M, x_mode }
 378 #define Mxmm { OP_M, xmm_mode }
 379 #define Gb { OP_G, b_mode }
 380 #define Gbnd { OP_G, bnd_mode }
 381 #define Gv { OP_G, v_mode }
 382 #define Gd { OP_G, d_mode }
 383 #define Gdq { OP_G, dq_mode }
 384 #define Gm { OP_G, m_mode }
 385 #define Gva { OP_G, va_mode }
 386 #define Gw { OP_G, w_mode }
 387 #define Ib { OP_I, b_mode }
 388 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 389 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 390 #define Iv { OP_I, v_mode }
 391 #define sIv { OP_sI, v_mode }
 392 #define Iv64 { OP_I64, v_mode }
 393 #define Id { OP_I, d_mode }
 394 #define Iw { OP_I, w_mode }
 395 #define I1 { OP_I, const_1_mode }
 396 #define Jb { OP_J, b_mode }
 397 #define Jv { OP_J, v_mode }
 398 #define Jdqw { OP_J, dqw_mode }
 399 #define Cm { OP_C, m_mode }
 400 #define Dm { OP_D, m_mode }
 401 #define Td { OP_T, d_mode }
 402 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 403
 404 #define RMeAX { OP_REG, eAX_reg }
 405 #define RMeBX { OP_REG, eBX_reg }
 406 #define RMeCX { OP_REG, eCX_reg }
 407 #define RMeDX { OP_REG, eDX_reg }
 408 #define RMeSP { OP_REG, eSP_reg }
 409 #define RMeBP { OP_REG, eBP_reg }
 410 #define RMeSI { OP_REG, eSI_reg }
 411 #define RMeDI { OP_REG, eDI_reg }
 412 #define RMrAX { OP_REG, rAX_reg }
 413 #define RMrBX { OP_REG, rBX_reg }
 414 #define RMrCX { OP_REG, rCX_reg }
 415 #define RMrDX { OP_REG, rDX_reg }
 416 #define RMrSP { OP_REG, rSP_reg }
 417 #define RMrBP { OP_REG, rBP_reg }
 418 #define RMrSI { OP_REG, rSI_reg }
 419 #define RMrDI { OP_REG, rDI_reg }
 420 #define RMAL { OP_REG, al_reg }
 421 #define RMCL { OP_REG, cl_reg }
 422 #define RMDL { OP_REG, dl_reg }
 423 #define RMBL { OP_REG, bl_reg }
 424 #define RMAH { OP_REG, ah_reg }
 425 #define RMCH { OP_REG, ch_reg }
 426 #define RMDH { OP_REG, dh_reg }
 427 #define RMBH { OP_REG, bh_reg }
 428 #define RMAX { OP_REG, ax_reg }
 429 #define RMDX { OP_REG, dx_reg }
 430
 431 #define eAX { OP_IMREG, eAX_reg }
 432 #define AL { OP_IMREG, al_reg }
 433 #define CL { OP_IMREG, cl_reg }
 434 #define zAX { OP_IMREG, z_mode_ax_reg }
 435 #define indirDX { OP_IMREG, indir_dx_reg }
 436
 437 #define Sw { OP_SEG, w_mode }
 438 #define Sv { OP_SEG, v_mode }
 439 #define Ap { OP_DIR, 0 }
 440 #define Ob { OP_OFF64, b_mode }
 441 #define Ov { OP_OFF64, v_mode }
 442 #define Xb { OP_DSreg, eSI_reg }
 443 #define Xv { OP_DSreg, eSI_reg }
 444 #define Xz { OP_DSreg, eSI_reg }
 445 #define Yb { OP_ESreg, eDI_reg }
 446 #define Yv { OP_ESreg, eDI_reg }
 447 #define DSBX { OP_DSreg, eBX_reg }
 448
 449 #define es { OP_REG, es_reg }
 450 #define ss { OP_REG, ss_reg }
 451 #define cs { OP_REG, cs_reg }
 452 #define ds { OP_REG, ds_reg }
 453 #define fs { OP_REG, fs_reg }
 454 #define gs { OP_REG, gs_reg }
 455
 456 #define MX { OP_MMX, 0 }
 457 #define XM { OP_XMM, 0 }
 458 #define XMScalar { OP_XMM, scalar_mode }
 459 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 460 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 461 #define XMM { OP_XMM, xmm_mode }
 462 #define TMM { OP_XMM, tmm_mode }
 463 #define XMxmmq { OP_XMM, xmmq_mode }
 464 #define EM { OP_EM, v_mode }
 465 #define EMS { OP_EM, v_swap_mode }
 466 #define EMd { OP_EM, d_mode }
 467 #define EMx { OP_EM, x_mode }
 468 #define EXbwUnit { OP_EX, bw_unit_mode }
 469 #define EXb { OP_EX, b_mode }
 470 #define EXw { OP_EX, w_mode }
 471 #define EXd { OP_EX, d_mode }
 472 #define EXdS { OP_EX, d_swap_mode }
 473 #define EXwS { OP_EX, w_swap_mode }
 474 #define EXq { OP_EX, q_mode }
 475 #define EXqS { OP_EX, q_swap_mode }
 476 #define EXdq { OP_EX, dq_mode }
 477 #define EXx { OP_EX, x_mode }
 478 #define EXxh { OP_EX, xh_mode }
 479 #define EXxS { OP_EX, x_swap_mode }
 480 #define EXxmm { OP_EX, xmm_mode }
 481 #define EXymm { OP_EX, ymm_mode }
 482 #define EXtmm { OP_EX, tmm_mode }
 483 #define EXxmmq { OP_EX, xmmq_mode }
 484 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 485 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 486 #define EXxmmdw { OP_EX, xmmdw_mode }
 487 #define EXxmmqd { OP_EX, xmmqd_mode }
 488 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 489 #define EXymmq { OP_EX, ymmq_mode }
 490 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 491 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 492 #define MS { OP_MS, v_mode }
 493 #define XS { OP_XS, v_mode }
 494 #define EMCq { OP_EMC, q_mode }
 495 #define MXC { OP_MXC, 0 }
 496 #define OPSUF { OP_3DNowSuffix, 0 }
 497 #define SEP { SEP_Fixup, 0 }
 498 #define CMP { CMP_Fixup, 0 }
 499 #define XMM0 { XMM_Fixup, 0 }
 500 #define FXSAVE { FXSAVE_Fixup, 0 }
 501
 502 #define Vex { OP_VEX, x_mode }
 503 #define VexW { OP_VexW, x_mode }
 504 #define VexScalar { OP_VEX, scalar_mode }
 505 #define VexScalarR { OP_VexR, scalar_mode }
 506 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 507 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 508 #define VexGdq { OP_VEX, dq_mode }
 509 #define VexTmm { OP_VEX, tmm_mode }
 510 #define XMVexI4 { OP_REG_VexI4, x_mode }
 511 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 512 #define VexI4 { OP_VexI4, 0 }
 513 #define PCLMUL { PCLMUL_Fixup, 0 }
 514 #define VPCMP { VPCMP_Fixup, 0 }
 515 #define VPCOM { VPCOM_Fixup, 0 }
 516
 517 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 518 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 519 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 520
 521 #define MaskG { OP_G, mask_mode }
 522 #define MaskE { OP_E, mask_mode }
 523 #define MaskBDE { OP_E, mask_bd_mode }
 524 #define MaskVex { OP_VEX, mask_mode }
 525
 526 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 527 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 528
 529 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 530
 531 /* Used handle "rep" prefix for string instructions.  */
 532 #define Xbr { REP_Fixup, eSI_reg }
 533 #define Xvr { REP_Fixup, eSI_reg }
 534 #define Ybr { REP_Fixup, eDI_reg }
 535 #define Yvr { REP_Fixup, eDI_reg }
 536 #define Yzr { REP_Fixup, eDI_reg }
 537 #define indirDXr { REP_Fixup, indir_dx_reg }
 538 #define ALr { REP_Fixup, al_reg }
 539 #define eAXr { REP_Fixup, eAX_reg }
 540
 541 /* Used handle HLE prefix for lockable instructions.  */
 542 #define Ebh1 { HLE_Fixup1, b_mode }
 543 #define Evh1 { HLE_Fixup1, v_mode }
 544 #define Ebh2 { HLE_Fixup2, b_mode }
 545 #define Evh2 { HLE_Fixup2, v_mode }
 546 #define Ebh3 { HLE_Fixup3, b_mode }
 547 #define Evh3 { HLE_Fixup3, v_mode }
 548
 549 #define BND { BND_Fixup, 0 }
 550 #define NOTRACK { NOTRACK_Fixup, 0 }
 551
 552 #define cond_jump_flag { NULL, cond_jump_mode }
 553 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 554
 555 /* bits in sizeflag */
 556 #define SUFFIX_ALWAYS 4
 557 #define AFLAG 2
 558 #define DFLAG 1
 559
 560 enum
 561 {
 562   /* byte operand */
 563   b_mode = 1,
 564   /* byte operand with operand swapped */
 565   b_swap_mode,
 566   /* byte operand, sign extend like 'T' suffix */
 567   b_T_mode,
 568   /* operand size depends on prefixes */
 569   v_mode,
 570   /* operand size depends on prefixes with operand swapped */
 571   v_swap_mode,
 572   /* operand size depends on address prefix */
 573   va_mode,
 574   /* word operand */
 575   w_mode,
 576   /* double word operand  */
 577   d_mode,
 578   /* word operand with operand swapped  */
 579   w_swap_mode,
 580   /* double word operand with operand swapped */
 581   d_swap_mode,
 582   /* quad word operand */
 583   q_mode,
 584   /* quad word operand with operand swapped */
 585   q_swap_mode,
 586   /* ten-byte operand */
 587   t_mode,
 588   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 589      broadcast enabled.  */
 590   x_mode,
 591   /* Similar to x_mode, but with different EVEX mem shifts.  */
 592   evex_x_gscat_mode,
 593   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 594   bw_unit_mode,
 595   /* Similar to x_mode, but with disabled broadcast.  */
 596   evex_x_nobcst_mode,
 597   /* Similar to x_mode, but with operands swapped and disabled broadcast
 598      in EVEX.  */
 599   x_swap_mode,
 600   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 601      broadcast of 16bit enabled.  */
 602   xh_mode,
 603   /* 16-byte XMM operand */
 604   xmm_mode,
 605   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 606      memory operand (depending on vector length).  Broadcast isn't
 607      allowed.  */
 608   xmmq_mode,
 609   /* Same as xmmq_mode, but broadcast is allowed.  */
 610   evex_half_bcst_xmmq_mode,
 611   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 612      memory operand (depending on vector length).  16bit broadcast.  */
 613   evex_half_bcst_xmmqh_mode,
 614   /* 16-byte XMM, word, double word or quad word operand.  */
 615   xmmdw_mode,
 616   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 617   xmmqd_mode,
 618   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 619      16bit broadcast.  */
 620   evex_half_bcst_xmmqdh_mode,
 621   /* 32-byte YMM operand */
 622   ymm_mode,
 623   /* quad word, ymmword or zmmword memory operand.  */
 624   ymmq_mode,
 625   /* TMM operand */
 626   tmm_mode,
 627   /* d_mode in 32bit, q_mode in 64bit mode.  */
 628   m_mode,
 629   /* pair of v_mode operands */
 630   a_mode,
 631   cond_jump_mode,
 632   loop_jcxz_mode,
 633   movsxd_mode,
 634   v_bnd_mode,
 635   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 636   v_bndmk_mode,
 637   /* operand size depends on REX.W / VEX.W.  */
 638   dq_mode,
 639   /* Displacements like v_mode without considering Intel64 ISA.  */
 640   dqw_mode,
 641   /* bounds operand */
 642   bnd_mode,
 643   /* bounds operand with operand swapped */
 644   bnd_swap_mode,
 645   /* 4- or 6-byte pointer operand */
 646   f_mode,
 647   const_1_mode,
 648   /* v_mode for indirect branch opcodes.  */
 649   indir_v_mode,
 650   /* v_mode for stack-related opcodes.  */
 651   stack_v_mode,
 652   /* non-quad operand size depends on prefixes */
 653   z_mode,
 654   /* 16-byte operand */
 655   o_mode,
 656   /* registers like d_mode, memory like b_mode.  */
 657   db_mode,
 658   /* registers like d_mode, memory like w_mode.  */
 659   dw_mode,
 660
 661   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 662   vex_vsib_d_w_dq_mode,
 663   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 664   vex_vsib_q_w_dq_mode,
 665   /* mandatory non-vector SIB.  */
 666   vex_sibmem_mode,
 667
 668   /* scalar, ignore vector length.  */
 669   scalar_mode,
 670
 671   /* Static rounding.  */
 672   evex_rounding_mode,
 673   /* Static rounding, 64-bit mode only.  */
 674   evex_rounding_64_mode,
 675   /* Supress all exceptions.  */
 676   evex_sae_mode,
 677
 678   /* Mask register operand.  */
 679   mask_mode,
 680   /* Mask register operand.  */
 681   mask_bd_mode,
 682
 683   es_reg,
 684   cs_reg,
 685   ss_reg,
 686   ds_reg,
 687   fs_reg,
 688   gs_reg,
 689
 690   eAX_reg,
 691   eCX_reg,
 692   eDX_reg,
 693   eBX_reg,
 694   eSP_reg,
 695   eBP_reg,
 696   eSI_reg,
 697   eDI_reg,
 698
 699   al_reg,
 700   cl_reg,
 701   dl_reg,
 702   bl_reg,
 703   ah_reg,
 704   ch_reg,
 705   dh_reg,
 706   bh_reg,
 707
 708   ax_reg,
 709   cx_reg,
 710   dx_reg,
 711   bx_reg,
 712   sp_reg,
 713   bp_reg,
 714   si_reg,
 715   di_reg,
 716
 717   rAX_reg,
 718   rCX_reg,
 719   rDX_reg,
 720   rBX_reg,
 721   rSP_reg,
 722   rBP_reg,
 723   rSI_reg,
 724   rDI_reg,
 725
 726   z_mode_ax_reg,
 727   indir_dx_reg
 728 };
 729
 730 enum
 731 {
 732   FLOATCODE = 1,
 733   USE_REG_TABLE,
 734   USE_MOD_TABLE,
 735   USE_RM_TABLE,
 736   USE_PREFIX_TABLE,
 737   USE_X86_64_TABLE,
 738   USE_3BYTE_TABLE,
 739   USE_XOP_8F_TABLE,
 740   USE_VEX_C4_TABLE,
 741   USE_VEX_C5_TABLE,
 742   USE_VEX_LEN_TABLE,
 743   USE_VEX_W_TABLE,
 744   USE_EVEX_TABLE,
 745   USE_EVEX_LEN_TABLE
 746 };
 747
 748 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 749
 750 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 751 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 752 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 753 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 754 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 755 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 756 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 757 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 758 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 759 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 760 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 761 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 762 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 763 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 764 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 765 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 766
 767 enum
 768 {
 769   REG_80 = 0,
 770   REG_81,
 771   REG_83,
 772   REG_8F,
 773   REG_C0,
 774   REG_C1,
 775   REG_C6,
 776   REG_C7,
 777   REG_D0,
 778   REG_D1,
 779   REG_D2,
 780   REG_D3,
 781   REG_F6,
 782   REG_F7,
 783   REG_FE,
 784   REG_FF,
 785   REG_0F00,
 786   REG_0F01,
 787   REG_0F0D,
 788   REG_0F18,
 789   REG_0F1C_P_0_MOD_0,
 790   REG_0F1E_P_1_MOD_3,
 791   REG_0F38D8_PREFIX_1,
 792   REG_0F3A0F_PREFIX_1_MOD_3,
 793   REG_0F71_MOD_0,
 794   REG_0F72_MOD_0,
 795   REG_0F73_MOD_0,
 796   REG_0FA6,
 797   REG_0FA7,
 798   REG_0FAE,
 799   REG_0FBA,
 800   REG_0FC7,
 801   REG_VEX_0F71_M_0,
 802   REG_VEX_0F72_M_0,
 803   REG_VEX_0F73_M_0,
 804   REG_VEX_0FAE,
 805   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 806   REG_VEX_0F38F3_L_0,
 807
 808   REG_XOP_09_01_L_0,
 809   REG_XOP_09_02_L_0,
 810   REG_XOP_09_12_M_1_L_0,
 811   REG_XOP_0A_12_L_0,
 812
 813   REG_EVEX_0F71,
 814   REG_EVEX_0F72,
 815   REG_EVEX_0F73,
 816   REG_EVEX_0F38C6_M_0_L_2,
 817   REG_EVEX_0F38C7_M_0_L_2
 818 };
 819
 820 enum
 821 {
 822   MOD_62_32BIT = 0,
 823   MOD_8D,
 824   MOD_C4_32BIT,
 825   MOD_C5_32BIT,
 826   MOD_C6_REG_7,
 827   MOD_C7_REG_7,
 828   MOD_FF_REG_3,
 829   MOD_FF_REG_5,
 830   MOD_0F01_REG_0,
 831   MOD_0F01_REG_1,
 832   MOD_0F01_REG_2,
 833   MOD_0F01_REG_3,
 834   MOD_0F01_REG_5,
 835   MOD_0F01_REG_7,
 836   MOD_0F12_PREFIX_0,
 837   MOD_0F12_PREFIX_2,
 838   MOD_0F13,
 839   MOD_0F16_PREFIX_0,
 840   MOD_0F16_PREFIX_2,
 841   MOD_0F17,
 842   MOD_0F18_REG_0,
 843   MOD_0F18_REG_1,
 844   MOD_0F18_REG_2,
 845   MOD_0F18_REG_3,
 846   MOD_0F18_REG_6,
 847   MOD_0F18_REG_7,
 848   MOD_0F1A_PREFIX_0,
 849   MOD_0F1B_PREFIX_0,
 850   MOD_0F1B_PREFIX_1,
 851   MOD_0F1C_PREFIX_0,
 852   MOD_0F1E_PREFIX_1,
 853   MOD_0F2B_PREFIX_0,
 854   MOD_0F2B_PREFIX_1,
 855   MOD_0F2B_PREFIX_2,
 856   MOD_0F2B_PREFIX_3,
 857   MOD_0F50,
 858   MOD_0F71,
 859   MOD_0F72,
 860   MOD_0F73,
 861   MOD_0FAE_REG_0,
 862   MOD_0FAE_REG_1,
 863   MOD_0FAE_REG_2,
 864   MOD_0FAE_REG_3,
 865   MOD_0FAE_REG_4,
 866   MOD_0FAE_REG_5,
 867   MOD_0FAE_REG_6,
 868   MOD_0FAE_REG_7,
 869   MOD_0FB2,
 870   MOD_0FB4,
 871   MOD_0FB5,
 872   MOD_0FC3,
 873   MOD_0FC7_REG_3,
 874   MOD_0FC7_REG_4,
 875   MOD_0FC7_REG_5,
 876   MOD_0FC7_REG_6,
 877   MOD_0FC7_REG_7,
 878   MOD_0FD7,
 879   MOD_0FE7_PREFIX_2,
 880   MOD_0FF0_PREFIX_3,
 881   MOD_0F382A,
 882   MOD_0F38DC_PREFIX_1,
 883   MOD_0F38DD_PREFIX_1,
 884   MOD_0F38DE_PREFIX_1,
 885   MOD_0F38DF_PREFIX_1,
 886   MOD_0F38F5,
 887   MOD_0F38F6_PREFIX_0,
 888   MOD_0F38F8_PREFIX_1,
 889   MOD_0F38F8_PREFIX_2,
 890   MOD_0F38F8_PREFIX_3,
 891   MOD_0F38F9,
 892   MOD_0F38FA_PREFIX_1,
 893   MOD_0F38FB_PREFIX_1,
 894   MOD_0F3A0F_PREFIX_1,
 895
 896   MOD_VEX_0F12_PREFIX_0,
 897   MOD_VEX_0F12_PREFIX_2,
 898   MOD_VEX_0F13,
 899   MOD_VEX_0F16_PREFIX_0,
 900   MOD_VEX_0F16_PREFIX_2,
 901   MOD_VEX_0F17,
 902   MOD_VEX_0F2B,
 903   MOD_VEX_0F41_L_1,
 904   MOD_VEX_0F42_L_1,
 905   MOD_VEX_0F44_L_0,
 906   MOD_VEX_0F45_L_1,
 907   MOD_VEX_0F46_L_1,
 908   MOD_VEX_0F47_L_1,
 909   MOD_VEX_0F4A_L_1,
 910   MOD_VEX_0F4B_L_1,
 911   MOD_VEX_0F50,
 912   MOD_VEX_0F71,
 913   MOD_VEX_0F72,
 914   MOD_VEX_0F73,
 915   MOD_VEX_0F91_L_0,
 916   MOD_VEX_0F92_L_0,
 917   MOD_VEX_0F93_L_0,
 918   MOD_VEX_0F98_L_0,
 919   MOD_VEX_0F99_L_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7,
 923   MOD_VEX_0FE7,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A,
 926   MOD_VEX_0F382A,
 927   MOD_VEX_0F382C,
 928   MOD_VEX_0F382D,
 929   MOD_VEX_0F382E,
 930   MOD_VEX_0F382F,
 931   MOD_VEX_0F3849_X86_64_P_0_W_0,
 932   MOD_VEX_0F3849_X86_64_P_2_W_0,
 933   MOD_VEX_0F3849_X86_64_P_3_W_0,
 934   MOD_VEX_0F384B_X86_64_P_1_W_0,
 935   MOD_VEX_0F384B_X86_64_P_2_W_0,
 936   MOD_VEX_0F384B_X86_64_P_3_W_0,
 937   MOD_VEX_0F385A,
 938   MOD_VEX_0F385C_X86_64_P_1_W_0,
 939   MOD_VEX_0F385C_X86_64_P_3_W_0,
 940   MOD_VEX_0F385E_X86_64_P_0_W_0,
 941   MOD_VEX_0F385E_X86_64_P_1_W_0,
 942   MOD_VEX_0F385E_X86_64_P_2_W_0,
 943   MOD_VEX_0F385E_X86_64_P_3_W_0,
 944   MOD_VEX_0F388C,
 945   MOD_VEX_0F388E,
 946   MOD_VEX_0F3A30_L_0,
 947   MOD_VEX_0F3A31_L_0,
 948   MOD_VEX_0F3A32_L_0,
 949   MOD_VEX_0F3A33_L_0,
 950
 951   MOD_XOP_09_12,
 952
 953   MOD_EVEX_0F381A,
 954   MOD_EVEX_0F381B,
 955   MOD_EVEX_0F3828_P_1,
 956   MOD_EVEX_0F382A_P_1_W_1,
 957   MOD_EVEX_0F3838_P_1,
 958   MOD_EVEX_0F383A_P_1_W_0,
 959   MOD_EVEX_0F385A,
 960   MOD_EVEX_0F385B,
 961   MOD_EVEX_0F387A_W_0,
 962   MOD_EVEX_0F387B_W_0,
 963   MOD_EVEX_0F387C,
 964   MOD_EVEX_0F38C6,
 965   MOD_EVEX_0F38C7,
 966 };
 967
 968 enum
 969 {
 970   RM_C6_REG_7 = 0,
 971   RM_C7_REG_7,
 972   RM_0F01_REG_0,
 973   RM_0F01_REG_1,
 974   RM_0F01_REG_2,
 975   RM_0F01_REG_3,
 976   RM_0F01_REG_5_MOD_3,
 977   RM_0F01_REG_7_MOD_3,
 978   RM_0F1E_P_1_MOD_3_REG_7,
 979   RM_0FAE_REG_6_MOD_3_P_0,
 980   RM_0FAE_REG_7_MOD_3,
 981   RM_0F3A0F_P_1_MOD_3_REG_0,
 982
 983   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 984 };
 985
 986 enum
 987 {
 988   PREFIX_90 = 0,
 989   PREFIX_0F01_REG_0_MOD_3_RM_6,
 990   PREFIX_0F01_REG_1_RM_4,
 991   PREFIX_0F01_REG_1_RM_5,
 992   PREFIX_0F01_REG_1_RM_6,
 993   PREFIX_0F01_REG_1_RM_7,
 994   PREFIX_0F01_REG_3_RM_1,
 995   PREFIX_0F01_REG_5_MOD_0,
 996   PREFIX_0F01_REG_5_MOD_3_RM_0,
 997   PREFIX_0F01_REG_5_MOD_3_RM_1,
 998   PREFIX_0F01_REG_5_MOD_3_RM_2,
 999   PREFIX_0F01_REG_5_MOD_3_RM_4,
1000   PREFIX_0F01_REG_5_MOD_3_RM_5,
1001   PREFIX_0F01_REG_5_MOD_3_RM_6,
1002   PREFIX_0F01_REG_5_MOD_3_RM_7,
1003   PREFIX_0F01_REG_7_MOD_3_RM_2,
1004   PREFIX_0F01_REG_7_MOD_3_RM_5,
1005   PREFIX_0F01_REG_7_MOD_3_RM_6,
1006   PREFIX_0F01_REG_7_MOD_3_RM_7,
1007   PREFIX_0F09,
1008   PREFIX_0F10,
1009   PREFIX_0F11,
1010   PREFIX_0F12,
1011   PREFIX_0F16,
1012   PREFIX_0F18_REG_6_MOD_0_X86_64,
1013   PREFIX_0F18_REG_7_MOD_0_X86_64,
1014   PREFIX_0F1A,
1015   PREFIX_0F1B,
1016   PREFIX_0F1C,
1017   PREFIX_0F1E,
1018   PREFIX_0F2A,
1019   PREFIX_0F2B,
1020   PREFIX_0F2C,
1021   PREFIX_0F2D,
1022   PREFIX_0F2E,
1023   PREFIX_0F2F,
1024   PREFIX_0F51,
1025   PREFIX_0F52,
1026   PREFIX_0F53,
1027   PREFIX_0F58,
1028   PREFIX_0F59,
1029   PREFIX_0F5A,
1030   PREFIX_0F5B,
1031   PREFIX_0F5C,
1032   PREFIX_0F5D,
1033   PREFIX_0F5E,
1034   PREFIX_0F5F,
1035   PREFIX_0F60,
1036   PREFIX_0F61,
1037   PREFIX_0F62,
1038   PREFIX_0F6F,
1039   PREFIX_0F70,
1040   PREFIX_0F78,
1041   PREFIX_0F79,
1042   PREFIX_0F7C,
1043   PREFIX_0F7D,
1044   PREFIX_0F7E,
1045   PREFIX_0F7F,
1046   PREFIX_0FAE_REG_0_MOD_3,
1047   PREFIX_0FAE_REG_1_MOD_3,
1048   PREFIX_0FAE_REG_2_MOD_3,
1049   PREFIX_0FAE_REG_3_MOD_3,
1050   PREFIX_0FAE_REG_4_MOD_0,
1051   PREFIX_0FAE_REG_4_MOD_3,
1052   PREFIX_0FAE_REG_5_MOD_3,
1053   PREFIX_0FAE_REG_6_MOD_0,
1054   PREFIX_0FAE_REG_6_MOD_3,
1055   PREFIX_0FAE_REG_7_MOD_0,
1056   PREFIX_0FB8,
1057   PREFIX_0FBC,
1058   PREFIX_0FBD,
1059   PREFIX_0FC2,
1060   PREFIX_0FC7_REG_6_MOD_0,
1061   PREFIX_0FC7_REG_6_MOD_3,
1062   PREFIX_0FC7_REG_7_MOD_3,
1063   PREFIX_0FD0,
1064   PREFIX_0FD6,
1065   PREFIX_0FE6,
1066   PREFIX_0FE7,
1067   PREFIX_0FF0,
1068   PREFIX_0FF7,
1069   PREFIX_0F38D8,
1070   PREFIX_0F38DC,
1071   PREFIX_0F38DD,
1072   PREFIX_0F38DE,
1073   PREFIX_0F38DF,
1074   PREFIX_0F38F0,
1075   PREFIX_0F38F1,
1076   PREFIX_0F38F6,
1077   PREFIX_0F38F8,
1078   PREFIX_0F38FA,
1079   PREFIX_0F38FB,
1080   PREFIX_0F38FC,
1081   PREFIX_0F3A0F,
1082   PREFIX_VEX_0F10,
1083   PREFIX_VEX_0F11,
1084   PREFIX_VEX_0F12,
1085   PREFIX_VEX_0F16,
1086   PREFIX_VEX_0F2A,
1087   PREFIX_VEX_0F2C,
1088   PREFIX_VEX_0F2D,
1089   PREFIX_VEX_0F2E,
1090   PREFIX_VEX_0F2F,
1091   PREFIX_VEX_0F41_L_1_M_1_W_0,
1092   PREFIX_VEX_0F41_L_1_M_1_W_1,
1093   PREFIX_VEX_0F42_L_1_M_1_W_0,
1094   PREFIX_VEX_0F42_L_1_M_1_W_1,
1095   PREFIX_VEX_0F44_L_0_M_1_W_0,
1096   PREFIX_VEX_0F44_L_0_M_1_W_1,
1097   PREFIX_VEX_0F45_L_1_M_1_W_0,
1098   PREFIX_VEX_0F45_L_1_M_1_W_1,
1099   PREFIX_VEX_0F46_L_1_M_1_W_0,
1100   PREFIX_VEX_0F46_L_1_M_1_W_1,
1101   PREFIX_VEX_0F47_L_1_M_1_W_0,
1102   PREFIX_VEX_0F47_L_1_M_1_W_1,
1103   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1104   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1105   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1106   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1107   PREFIX_VEX_0F51,
1108   PREFIX_VEX_0F52,
1109   PREFIX_VEX_0F53,
1110   PREFIX_VEX_0F58,
1111   PREFIX_VEX_0F59,
1112   PREFIX_VEX_0F5A,
1113   PREFIX_VEX_0F5B,
1114   PREFIX_VEX_0F5C,
1115   PREFIX_VEX_0F5D,
1116   PREFIX_VEX_0F5E,
1117   PREFIX_VEX_0F5F,
1118   PREFIX_VEX_0F6F,
1119   PREFIX_VEX_0F70,
1120   PREFIX_VEX_0F7C,
1121   PREFIX_VEX_0F7D,
1122   PREFIX_VEX_0F7E,
1123   PREFIX_VEX_0F7F,
1124   PREFIX_VEX_0F90_L_0_W_0,
1125   PREFIX_VEX_0F90_L_0_W_1,
1126   PREFIX_VEX_0F91_L_0_M_0_W_0,
1127   PREFIX_VEX_0F91_L_0_M_0_W_1,
1128   PREFIX_VEX_0F92_L_0_M_1_W_0,
1129   PREFIX_VEX_0F92_L_0_M_1_W_1,
1130   PREFIX_VEX_0F93_L_0_M_1_W_0,
1131   PREFIX_VEX_0F93_L_0_M_1_W_1,
1132   PREFIX_VEX_0F98_L_0_M_1_W_0,
1133   PREFIX_VEX_0F98_L_0_M_1_W_1,
1134   PREFIX_VEX_0F99_L_0_M_1_W_0,
1135   PREFIX_VEX_0F99_L_0_M_1_W_1,
1136   PREFIX_VEX_0FC2,
1137   PREFIX_VEX_0FD0,
1138   PREFIX_VEX_0FE6,
1139   PREFIX_VEX_0FF0,
1140   PREFIX_VEX_0F3849_X86_64,
1141   PREFIX_VEX_0F384B_X86_64,
1142   PREFIX_VEX_0F3850_W_0,
1143   PREFIX_VEX_0F3851_W_0,
1144   PREFIX_VEX_0F385C_X86_64,
1145   PREFIX_VEX_0F385E_X86_64,
1146   PREFIX_VEX_0F3872,
1147   PREFIX_VEX_0F38B0_W_0,
1148   PREFIX_VEX_0F38B1_W_0,
1149   PREFIX_VEX_0F38F5_L_0,
1150   PREFIX_VEX_0F38F6_L_0,
1151   PREFIX_VEX_0F38F7_L_0,
1152   PREFIX_VEX_0F3AF0_L_0,
1153
1154   PREFIX_EVEX_0F5B,
1155   PREFIX_EVEX_0F6F,
1156   PREFIX_EVEX_0F70,
1157   PREFIX_EVEX_0F78,
1158   PREFIX_EVEX_0F79,
1159   PREFIX_EVEX_0F7A,
1160   PREFIX_EVEX_0F7B,
1161   PREFIX_EVEX_0F7E,
1162   PREFIX_EVEX_0F7F,
1163   PREFIX_EVEX_0FC2,
1164   PREFIX_EVEX_0FE6,
1165   PREFIX_EVEX_0F3810,
1166   PREFIX_EVEX_0F3811,
1167   PREFIX_EVEX_0F3812,
1168   PREFIX_EVEX_0F3813,
1169   PREFIX_EVEX_0F3814,
1170   PREFIX_EVEX_0F3815,
1171   PREFIX_EVEX_0F3820,
1172   PREFIX_EVEX_0F3821,
1173   PREFIX_EVEX_0F3822,
1174   PREFIX_EVEX_0F3823,
1175   PREFIX_EVEX_0F3824,
1176   PREFIX_EVEX_0F3825,
1177   PREFIX_EVEX_0F3826,
1178   PREFIX_EVEX_0F3827,
1179   PREFIX_EVEX_0F3828,
1180   PREFIX_EVEX_0F3829,
1181   PREFIX_EVEX_0F382A,
1182   PREFIX_EVEX_0F3830,
1183   PREFIX_EVEX_0F3831,
1184   PREFIX_EVEX_0F3832,
1185   PREFIX_EVEX_0F3833,
1186   PREFIX_EVEX_0F3834,
1187   PREFIX_EVEX_0F3835,
1188   PREFIX_EVEX_0F3838,
1189   PREFIX_EVEX_0F3839,
1190   PREFIX_EVEX_0F383A,
1191   PREFIX_EVEX_0F3852,
1192   PREFIX_EVEX_0F3853,
1193   PREFIX_EVEX_0F3868,
1194   PREFIX_EVEX_0F3872,
1195   PREFIX_EVEX_0F389A,
1196   PREFIX_EVEX_0F389B,
1197   PREFIX_EVEX_0F38AA,
1198   PREFIX_EVEX_0F38AB,
1199
1200   PREFIX_EVEX_0F3A08,
1201   PREFIX_EVEX_0F3A0A,
1202   PREFIX_EVEX_0F3A26,
1203   PREFIX_EVEX_0F3A27,
1204   PREFIX_EVEX_0F3A56,
1205   PREFIX_EVEX_0F3A57,
1206   PREFIX_EVEX_0F3A66,
1207   PREFIX_EVEX_0F3A67,
1208   PREFIX_EVEX_0F3AC2,
1209
1210   PREFIX_EVEX_MAP5_10,
1211   PREFIX_EVEX_MAP5_11,
1212   PREFIX_EVEX_MAP5_1D,
1213   PREFIX_EVEX_MAP5_2A,
1214   PREFIX_EVEX_MAP5_2C,
1215   PREFIX_EVEX_MAP5_2D,
1216   PREFIX_EVEX_MAP5_2E,
1217   PREFIX_EVEX_MAP5_2F,
1218   PREFIX_EVEX_MAP5_51,
1219   PREFIX_EVEX_MAP5_58,
1220   PREFIX_EVEX_MAP5_59,
1221   PREFIX_EVEX_MAP5_5A,
1222   PREFIX_EVEX_MAP5_5B,
1223   PREFIX_EVEX_MAP5_5C,
1224   PREFIX_EVEX_MAP5_5D,
1225   PREFIX_EVEX_MAP5_5E,
1226   PREFIX_EVEX_MAP5_5F,
1227   PREFIX_EVEX_MAP5_78,
1228   PREFIX_EVEX_MAP5_79,
1229   PREFIX_EVEX_MAP5_7A,
1230   PREFIX_EVEX_MAP5_7B,
1231   PREFIX_EVEX_MAP5_7C,
1232   PREFIX_EVEX_MAP5_7D,
1233
1234   PREFIX_EVEX_MAP6_13,
1235   PREFIX_EVEX_MAP6_56,
1236   PREFIX_EVEX_MAP6_57,
1237   PREFIX_EVEX_MAP6_D6,
1238   PREFIX_EVEX_MAP6_D7,
1239 };
1240
1241 enum
1242 {
1243   X86_64_06 = 0,
1244   X86_64_07,
1245   X86_64_0E,
1246   X86_64_16,
1247   X86_64_17,
1248   X86_64_1E,
1249   X86_64_1F,
1250   X86_64_27,
1251   X86_64_2F,
1252   X86_64_37,
1253   X86_64_3F,
1254   X86_64_60,
1255   X86_64_61,
1256   X86_64_62,
1257   X86_64_63,
1258   X86_64_6D,
1259   X86_64_6F,
1260   X86_64_82,
1261   X86_64_9A,
1262   X86_64_C2,
1263   X86_64_C3,
1264   X86_64_C4,
1265   X86_64_C5,
1266   X86_64_CE,
1267   X86_64_D4,
1268   X86_64_D5,
1269   X86_64_E8,
1270   X86_64_E9,
1271   X86_64_EA,
1272   X86_64_0F01_REG_0,
1273   X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1274   X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1275   X86_64_0F01_REG_1,
1276   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1277   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1278   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1279   X86_64_0F01_REG_2,
1280   X86_64_0F01_REG_3,
1281   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1282   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1283   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1284   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1285   X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1286   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1287   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1288   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1289   X86_64_0F18_REG_6_MOD_0,
1290   X86_64_0F18_REG_7_MOD_0,
1291   X86_64_0F24,
1292   X86_64_0F26,
1293   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1294
1295   X86_64_VEX_0F3849,
1296   X86_64_VEX_0F384B,
1297   X86_64_VEX_0F385C,
1298   X86_64_VEX_0F385E,
1299   X86_64_VEX_0F38E0,
1300   X86_64_VEX_0F38E1,
1301   X86_64_VEX_0F38E2,
1302   X86_64_VEX_0F38E3,
1303   X86_64_VEX_0F38E4,
1304   X86_64_VEX_0F38E5,
1305   X86_64_VEX_0F38E6,
1306   X86_64_VEX_0F38E7,
1307   X86_64_VEX_0F38E8,
1308   X86_64_VEX_0F38E9,
1309   X86_64_VEX_0F38EA,
1310   X86_64_VEX_0F38EB,
1311   X86_64_VEX_0F38EC,
1312   X86_64_VEX_0F38ED,
1313   X86_64_VEX_0F38EE,
1314   X86_64_VEX_0F38EF,
1315 };
1316
1317 enum
1318 {
1319   THREE_BYTE_0F38 = 0,
1320   THREE_BYTE_0F3A
1321 };
1322
1323 enum
1324 {
1325   XOP_08 = 0,
1326   XOP_09,
1327   XOP_0A
1328 };
1329
1330 enum
1331 {
1332   VEX_0F = 0,
1333   VEX_0F38,
1334   VEX_0F3A
1335 };
1336
1337 enum
1338 {
1339   EVEX_0F = 0,
1340   EVEX_0F38,
1341   EVEX_0F3A,
1342   EVEX_MAP5,
1343   EVEX_MAP6,
1344 };
1345
1346 enum
1347 {
1348   VEX_LEN_0F12_P_0_M_0 = 0,
1349   VEX_LEN_0F12_P_0_M_1,
1350 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1351   VEX_LEN_0F13_M_0,
1352   VEX_LEN_0F16_P_0_M_0,
1353   VEX_LEN_0F16_P_0_M_1,
1354 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1355   VEX_LEN_0F17_M_0,
1356   VEX_LEN_0F41,
1357   VEX_LEN_0F42,
1358   VEX_LEN_0F44,
1359   VEX_LEN_0F45,
1360   VEX_LEN_0F46,
1361   VEX_LEN_0F47,
1362   VEX_LEN_0F4A,
1363   VEX_LEN_0F4B,
1364   VEX_LEN_0F6E,
1365   VEX_LEN_0F77,
1366   VEX_LEN_0F7E_P_1,
1367   VEX_LEN_0F7E_P_2,
1368   VEX_LEN_0F90,
1369   VEX_LEN_0F91,
1370   VEX_LEN_0F92,
1371   VEX_LEN_0F93,
1372   VEX_LEN_0F98,
1373   VEX_LEN_0F99,
1374   VEX_LEN_0FAE_R_2_M_0,
1375   VEX_LEN_0FAE_R_3_M_0,
1376   VEX_LEN_0FC4,
1377   VEX_LEN_0FC5,
1378   VEX_LEN_0FD6,
1379   VEX_LEN_0FF7,
1380   VEX_LEN_0F3816,
1381   VEX_LEN_0F3819,
1382   VEX_LEN_0F381A_M_0,
1383   VEX_LEN_0F3836,
1384   VEX_LEN_0F3841,
1385   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1386   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1387   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1388   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1389   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1390   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1391   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1392   VEX_LEN_0F385A_M_0,
1393   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1394   VEX_LEN_0F385C_X86_64_P_3_W_0_M_0,
1395   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1396   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1397   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1398   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1399   VEX_LEN_0F38DB,
1400   VEX_LEN_0F38F2,
1401   VEX_LEN_0F38F3,
1402   VEX_LEN_0F38F5,
1403   VEX_LEN_0F38F6,
1404   VEX_LEN_0F38F7,
1405   VEX_LEN_0F3A00,
1406   VEX_LEN_0F3A01,
1407   VEX_LEN_0F3A06,
1408   VEX_LEN_0F3A14,
1409   VEX_LEN_0F3A15,
1410   VEX_LEN_0F3A16,
1411   VEX_LEN_0F3A17,
1412   VEX_LEN_0F3A18,
1413   VEX_LEN_0F3A19,
1414   VEX_LEN_0F3A20,
1415   VEX_LEN_0F3A21,
1416   VEX_LEN_0F3A22,
1417   VEX_LEN_0F3A30,
1418   VEX_LEN_0F3A31,
1419   VEX_LEN_0F3A32,
1420   VEX_LEN_0F3A33,
1421   VEX_LEN_0F3A38,
1422   VEX_LEN_0F3A39,
1423   VEX_LEN_0F3A41,
1424   VEX_LEN_0F3A46,
1425   VEX_LEN_0F3A60,
1426   VEX_LEN_0F3A61,
1427   VEX_LEN_0F3A62,
1428   VEX_LEN_0F3A63,
1429   VEX_LEN_0F3ADF,
1430   VEX_LEN_0F3AF0,
1431   VEX_LEN_0FXOP_08_85,
1432   VEX_LEN_0FXOP_08_86,
1433   VEX_LEN_0FXOP_08_87,
1434   VEX_LEN_0FXOP_08_8E,
1435   VEX_LEN_0FXOP_08_8F,
1436   VEX_LEN_0FXOP_08_95,
1437   VEX_LEN_0FXOP_08_96,
1438   VEX_LEN_0FXOP_08_97,
1439   VEX_LEN_0FXOP_08_9E,
1440   VEX_LEN_0FXOP_08_9F,
1441   VEX_LEN_0FXOP_08_A3,
1442   VEX_LEN_0FXOP_08_A6,
1443   VEX_LEN_0FXOP_08_B6,
1444   VEX_LEN_0FXOP_08_C0,
1445   VEX_LEN_0FXOP_08_C1,
1446   VEX_LEN_0FXOP_08_C2,
1447   VEX_LEN_0FXOP_08_C3,
1448   VEX_LEN_0FXOP_08_CC,
1449   VEX_LEN_0FXOP_08_CD,
1450   VEX_LEN_0FXOP_08_CE,
1451   VEX_LEN_0FXOP_08_CF,
1452   VEX_LEN_0FXOP_08_EC,
1453   VEX_LEN_0FXOP_08_ED,
1454   VEX_LEN_0FXOP_08_EE,
1455   VEX_LEN_0FXOP_08_EF,
1456   VEX_LEN_0FXOP_09_01,
1457   VEX_LEN_0FXOP_09_02,
1458   VEX_LEN_0FXOP_09_12_M_1,
1459   VEX_LEN_0FXOP_09_82_W_0,
1460   VEX_LEN_0FXOP_09_83_W_0,
1461   VEX_LEN_0FXOP_09_90,
1462   VEX_LEN_0FXOP_09_91,
1463   VEX_LEN_0FXOP_09_92,
1464   VEX_LEN_0FXOP_09_93,
1465   VEX_LEN_0FXOP_09_94,
1466   VEX_LEN_0FXOP_09_95,
1467   VEX_LEN_0FXOP_09_96,
1468   VEX_LEN_0FXOP_09_97,
1469   VEX_LEN_0FXOP_09_98,
1470   VEX_LEN_0FXOP_09_99,
1471   VEX_LEN_0FXOP_09_9A,
1472   VEX_LEN_0FXOP_09_9B,
1473   VEX_LEN_0FXOP_09_C1,
1474   VEX_LEN_0FXOP_09_C2,
1475   VEX_LEN_0FXOP_09_C3,
1476   VEX_LEN_0FXOP_09_C6,
1477   VEX_LEN_0FXOP_09_C7,
1478   VEX_LEN_0FXOP_09_CB,
1479   VEX_LEN_0FXOP_09_D1,
1480   VEX_LEN_0FXOP_09_D2,
1481   VEX_LEN_0FXOP_09_D3,
1482   VEX_LEN_0FXOP_09_D6,
1483   VEX_LEN_0FXOP_09_D7,
1484   VEX_LEN_0FXOP_09_DB,
1485   VEX_LEN_0FXOP_09_E1,
1486   VEX_LEN_0FXOP_09_E2,
1487   VEX_LEN_0FXOP_09_E3,
1488   VEX_LEN_0FXOP_0A_12,
1489 };
1490
1491 enum
1492 {
1493   EVEX_LEN_0F3816 = 0,
1494   EVEX_LEN_0F3819,
1495   EVEX_LEN_0F381A_M_0,
1496   EVEX_LEN_0F381B_M_0,
1497   EVEX_LEN_0F3836,
1498   EVEX_LEN_0F385A_M_0,
1499   EVEX_LEN_0F385B_M_0,
1500   EVEX_LEN_0F38C6_M_0,
1501   EVEX_LEN_0F38C7_M_0,
1502   EVEX_LEN_0F3A00,
1503   EVEX_LEN_0F3A01,
1504   EVEX_LEN_0F3A18,
1505   EVEX_LEN_0F3A19,
1506   EVEX_LEN_0F3A1A,
1507   EVEX_LEN_0F3A1B,
1508   EVEX_LEN_0F3A23,
1509   EVEX_LEN_0F3A38,
1510   EVEX_LEN_0F3A39,
1511   EVEX_LEN_0F3A3A,
1512   EVEX_LEN_0F3A3B,
1513   EVEX_LEN_0F3A43
1514 };
1515
1516 enum
1517 {
1518   VEX_W_0F41_L_1_M_1 = 0,
1519   VEX_W_0F42_L_1_M_1,
1520   VEX_W_0F44_L_0_M_1,
1521   VEX_W_0F45_L_1_M_1,
1522   VEX_W_0F46_L_1_M_1,
1523   VEX_W_0F47_L_1_M_1,
1524   VEX_W_0F4A_L_1_M_1,
1525   VEX_W_0F4B_L_1_M_1,
1526   VEX_W_0F90_L_0,
1527   VEX_W_0F91_L_0_M_0,
1528   VEX_W_0F92_L_0_M_1,
1529   VEX_W_0F93_L_0_M_1,
1530   VEX_W_0F98_L_0_M_1,
1531   VEX_W_0F99_L_0_M_1,
1532   VEX_W_0F380C,
1533   VEX_W_0F380D,
1534   VEX_W_0F380E,
1535   VEX_W_0F380F,
1536   VEX_W_0F3813,
1537   VEX_W_0F3816_L_1,
1538   VEX_W_0F3818,
1539   VEX_W_0F3819_L_1,
1540   VEX_W_0F381A_M_0_L_1,
1541   VEX_W_0F382C_M_0,
1542   VEX_W_0F382D_M_0,
1543   VEX_W_0F382E_M_0,
1544   VEX_W_0F382F_M_0,
1545   VEX_W_0F3836,
1546   VEX_W_0F3846,
1547   VEX_W_0F3849_X86_64_P_0,
1548   VEX_W_0F3849_X86_64_P_2,
1549   VEX_W_0F3849_X86_64_P_3,
1550   VEX_W_0F384B_X86_64_P_1,
1551   VEX_W_0F384B_X86_64_P_2,
1552   VEX_W_0F384B_X86_64_P_3,
1553   VEX_W_0F3850,
1554   VEX_W_0F3851,
1555   VEX_W_0F3852,
1556   VEX_W_0F3853,
1557   VEX_W_0F3858,
1558   VEX_W_0F3859,
1559   VEX_W_0F385A_M_0_L_0,
1560   VEX_W_0F385C_X86_64_P_1,
1561   VEX_W_0F385C_X86_64_P_3,
1562   VEX_W_0F385E_X86_64_P_0,
1563   VEX_W_0F385E_X86_64_P_1,
1564   VEX_W_0F385E_X86_64_P_2,
1565   VEX_W_0F385E_X86_64_P_3,
1566   VEX_W_0F3872_P_1,
1567   VEX_W_0F3878,
1568   VEX_W_0F3879,
1569   VEX_W_0F38B0,
1570   VEX_W_0F38B1,
1571   VEX_W_0F38B4,
1572   VEX_W_0F38B5,
1573   VEX_W_0F38CF,
1574   VEX_W_0F3A00_L_1,
1575   VEX_W_0F3A01_L_1,
1576   VEX_W_0F3A02,
1577   VEX_W_0F3A04,
1578   VEX_W_0F3A05,
1579   VEX_W_0F3A06_L_1,
1580   VEX_W_0F3A18_L_1,
1581   VEX_W_0F3A19_L_1,
1582   VEX_W_0F3A1D,
1583   VEX_W_0F3A38_L_1,
1584   VEX_W_0F3A39_L_1,
1585   VEX_W_0F3A46_L_1,
1586   VEX_W_0F3A4A,
1587   VEX_W_0F3A4B,
1588   VEX_W_0F3A4C,
1589   VEX_W_0F3ACE,
1590   VEX_W_0F3ACF,
1591
1592   VEX_W_0FXOP_08_85_L_0,
1593   VEX_W_0FXOP_08_86_L_0,
1594   VEX_W_0FXOP_08_87_L_0,
1595   VEX_W_0FXOP_08_8E_L_0,
1596   VEX_W_0FXOP_08_8F_L_0,
1597   VEX_W_0FXOP_08_95_L_0,
1598   VEX_W_0FXOP_08_96_L_0,
1599   VEX_W_0FXOP_08_97_L_0,
1600   VEX_W_0FXOP_08_9E_L_0,
1601   VEX_W_0FXOP_08_9F_L_0,
1602   VEX_W_0FXOP_08_A6_L_0,
1603   VEX_W_0FXOP_08_B6_L_0,
1604   VEX_W_0FXOP_08_C0_L_0,
1605   VEX_W_0FXOP_08_C1_L_0,
1606   VEX_W_0FXOP_08_C2_L_0,
1607   VEX_W_0FXOP_08_C3_L_0,
1608   VEX_W_0FXOP_08_CC_L_0,
1609   VEX_W_0FXOP_08_CD_L_0,
1610   VEX_W_0FXOP_08_CE_L_0,
1611   VEX_W_0FXOP_08_CF_L_0,
1612   VEX_W_0FXOP_08_EC_L_0,
1613   VEX_W_0FXOP_08_ED_L_0,
1614   VEX_W_0FXOP_08_EE_L_0,
1615   VEX_W_0FXOP_08_EF_L_0,
1616
1617   VEX_W_0FXOP_09_80,
1618   VEX_W_0FXOP_09_81,
1619   VEX_W_0FXOP_09_82,
1620   VEX_W_0FXOP_09_83,
1621   VEX_W_0FXOP_09_C1_L_0,
1622   VEX_W_0FXOP_09_C2_L_0,
1623   VEX_W_0FXOP_09_C3_L_0,
1624   VEX_W_0FXOP_09_C6_L_0,
1625   VEX_W_0FXOP_09_C7_L_0,
1626   VEX_W_0FXOP_09_CB_L_0,
1627   VEX_W_0FXOP_09_D1_L_0,
1628   VEX_W_0FXOP_09_D2_L_0,
1629   VEX_W_0FXOP_09_D3_L_0,
1630   VEX_W_0FXOP_09_D6_L_0,
1631   VEX_W_0FXOP_09_D7_L_0,
1632   VEX_W_0FXOP_09_DB_L_0,
1633   VEX_W_0FXOP_09_E1_L_0,
1634   VEX_W_0FXOP_09_E2_L_0,
1635   VEX_W_0FXOP_09_E3_L_0,
1636
1637   EVEX_W_0F5B_P_0,
1638   EVEX_W_0F62,
1639   EVEX_W_0F66,
1640   EVEX_W_0F6A,
1641   EVEX_W_0F6B,
1642   EVEX_W_0F6C,
1643   EVEX_W_0F6D,
1644   EVEX_W_0F6F_P_1,
1645   EVEX_W_0F6F_P_2,
1646   EVEX_W_0F6F_P_3,
1647   EVEX_W_0F70_P_2,
1648   EVEX_W_0F72_R_2,
1649   EVEX_W_0F72_R_6,
1650   EVEX_W_0F73_R_2,
1651   EVEX_W_0F73_R_6,
1652   EVEX_W_0F76,
1653   EVEX_W_0F78_P_0,
1654   EVEX_W_0F78_P_2,
1655   EVEX_W_0F79_P_0,
1656   EVEX_W_0F79_P_2,
1657   EVEX_W_0F7A_P_1,
1658   EVEX_W_0F7A_P_2,
1659   EVEX_W_0F7A_P_3,
1660   EVEX_W_0F7B_P_2,
1661   EVEX_W_0F7E_P_1,
1662   EVEX_W_0F7F_P_1,
1663   EVEX_W_0F7F_P_2,
1664   EVEX_W_0F7F_P_3,
1665   EVEX_W_0FD2,
1666   EVEX_W_0FD3,
1667   EVEX_W_0FD4,
1668   EVEX_W_0FD6,
1669   EVEX_W_0FE6_P_1,
1670   EVEX_W_0FE7,
1671   EVEX_W_0FF2,
1672   EVEX_W_0FF3,
1673   EVEX_W_0FF4,
1674   EVEX_W_0FFA,
1675   EVEX_W_0FFB,
1676   EVEX_W_0FFE,
1677
1678   EVEX_W_0F3810_P_1,
1679   EVEX_W_0F3810_P_2,
1680   EVEX_W_0F3811_P_1,
1681   EVEX_W_0F3811_P_2,
1682   EVEX_W_0F3812_P_1,
1683   EVEX_W_0F3812_P_2,
1684   EVEX_W_0F3813_P_1,
1685   EVEX_W_0F3814_P_1,
1686   EVEX_W_0F3815_P_1,
1687   EVEX_W_0F3819_L_n,
1688   EVEX_W_0F381A_M_0_L_n,
1689   EVEX_W_0F381B_M_0_L_2,
1690   EVEX_W_0F381E,
1691   EVEX_W_0F381F,
1692   EVEX_W_0F3820_P_1,
1693   EVEX_W_0F3821_P_1,
1694   EVEX_W_0F3822_P_1,
1695   EVEX_W_0F3823_P_1,
1696   EVEX_W_0F3824_P_1,
1697   EVEX_W_0F3825_P_1,
1698   EVEX_W_0F3825_P_2,
1699   EVEX_W_0F3828_P_2,
1700   EVEX_W_0F3829_P_2,
1701   EVEX_W_0F382A_P_1,
1702   EVEX_W_0F382A_P_2,
1703   EVEX_W_0F382B,
1704   EVEX_W_0F3830_P_1,
1705   EVEX_W_0F3831_P_1,
1706   EVEX_W_0F3832_P_1,
1707   EVEX_W_0F3833_P_1,
1708   EVEX_W_0F3834_P_1,
1709   EVEX_W_0F3835_P_1,
1710   EVEX_W_0F3835_P_2,
1711   EVEX_W_0F3837,
1712   EVEX_W_0F383A_P_1,
1713   EVEX_W_0F3859,
1714   EVEX_W_0F385A_M_0_L_n,
1715   EVEX_W_0F385B_M_0_L_2,
1716   EVEX_W_0F3870,
1717   EVEX_W_0F3872_P_2,
1718   EVEX_W_0F387A,
1719   EVEX_W_0F387B,
1720   EVEX_W_0F3883,
1721
1722   EVEX_W_0F3A18_L_n,
1723   EVEX_W_0F3A19_L_n,
1724   EVEX_W_0F3A1A_L_2,
1725   EVEX_W_0F3A1B_L_2,
1726   EVEX_W_0F3A21,
1727   EVEX_W_0F3A23_L_n,
1728   EVEX_W_0F3A38_L_n,
1729   EVEX_W_0F3A39_L_n,
1730   EVEX_W_0F3A3A_L_2,
1731   EVEX_W_0F3A3B_L_2,
1732   EVEX_W_0F3A42,
1733   EVEX_W_0F3A43_L_n,
1734   EVEX_W_0F3A70,
1735   EVEX_W_0F3A72,
1736
1737   EVEX_W_MAP5_5B_P_0,
1738   EVEX_W_MAP5_7A_P_3,
1739 };
1740
1741 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1742
1743 struct dis386 {
1744   const char *name;
1745   struct
1746     {
1747       op_rtn rtn;
1748       int bytemode;
1749     } op[MAX_OPERANDS];
1750   unsigned int prefix_requirement;
1751 };
1752
1753 /* Upper case letters in the instruction names here are macros.
1754    'A' => print 'b' if no register operands or suffix_always is true
1755    'B' => print 'b' if suffix_always is true
1756    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1757           size prefix
1758    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1759           suffix_always is true
1760    'E' => print 'e' if 32-bit form of jcxz
1761    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1762    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1763    'H' => print ",pt" or ",pn" branch hint
1764    'I' unused.
1765    'J' unused.
1766    'K' => print 'd' or 'q' if rex prefix is present.
1767    'L' unused.
1768    'M' => print 'r' if intel_mnemonic is false.
1769    'N' => print 'n' if instruction has no wait "prefix"
1770    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1771    'P' => behave as 'T' except with register operand outside of suffix_always
1772           mode
1773    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1774           is true
1775    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1776    'S' => print 'w', 'l' or 'q' if suffix_always is true
1777    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1778           prefix or if suffix_always is true.
1779    'U' unused.
1780    'V' unused.
1781    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1782    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1783    'Y' unused.
1784    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1785    '!' => change condition from true to false or from false to true.
1786    '%' => add 1 upper case letter to the macro.
1787    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1788           prefix or suffix_always is true (lcall/ljmp).
1789    '@' => in 64bit mode for Intel64 ISA or if instruction
1790           has no operand sizing prefix, print 'q' if suffix_always is true or
1791           nothing otherwise; behave as 'P' in all other cases
1792
1793    2 upper case letter macros:
1794    "XY" => print 'x' or 'y' if suffix_always is true or no register
1795            operands and no broadcast.
1796    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1797            register operands and no broadcast.
1798    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1799    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1800    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1801    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1802    "XV" => print "{vex} " pseudo prefix
1803    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1804            is used by an EVEX-encoded (AVX512VL) instruction.
1805    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1806            being false, or no operand at all in 64bit mode, or if suffix_always
1807            is true.
1808    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1809    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1810    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1811    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1812    "BW" => print 'b' or 'w' depending on the VEX.W bit
1813    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1814            an operand size prefix, or suffix_always is true.  print
1815            'q' if rex prefix is present.
1816
1817    Many of the above letters print nothing in Intel mode.  See "putop"
1818    for the details.
1819
1820    Braces '{' and '}', and vertical bars '|', indicate alternative
1821    mnemonic strings for AT&T and Intel.  */
1822
1823 static const struct dis386 dis386[] = {
1824   /* 00 */
1825   { "addB",             { Ebh1, Gb }, 0 },
1826   { "addS",             { Evh1, Gv }, 0 },
1827   { "addB",             { Gb, EbS }, 0 },
1828   { "addS",             { Gv, EvS }, 0 },
1829   { "addB",             { AL, Ib }, 0 },
1830   { "addS",             { eAX, Iv }, 0 },
1831   { X86_64_TABLE (X86_64_06) },
1832   { X86_64_TABLE (X86_64_07) },
1833   /* 08 */
1834   { "orB",              { Ebh1, Gb }, 0 },
1835   { "orS",              { Evh1, Gv }, 0 },
1836   { "orB",              { Gb, EbS }, 0 },
1837   { "orS",              { Gv, EvS }, 0 },
1838   { "orB",              { AL, Ib }, 0 },
1839   { "orS",              { eAX, Iv }, 0 },
1840   { X86_64_TABLE (X86_64_0E) },
1841   { Bad_Opcode },       /* 0x0f extended opcode escape */
1842   /* 10 */
1843   { "adcB",             { Ebh1, Gb }, 0 },
1844   { "adcS",             { Evh1, Gv }, 0 },
1845   { "adcB",             { Gb, EbS }, 0 },
1846   { "adcS",             { Gv, EvS }, 0 },
1847   { "adcB",             { AL, Ib }, 0 },
1848   { "adcS",             { eAX, Iv }, 0 },
1849   { X86_64_TABLE (X86_64_16) },
1850   { X86_64_TABLE (X86_64_17) },
1851   /* 18 */
1852   { "sbbB",             { Ebh1, Gb }, 0 },
1853   { "sbbS",             { Evh1, Gv }, 0 },
1854   { "sbbB",             { Gb, EbS }, 0 },
1855   { "sbbS",             { Gv, EvS }, 0 },
1856   { "sbbB",             { AL, Ib }, 0 },
1857   { "sbbS",             { eAX, Iv }, 0 },
1858   { X86_64_TABLE (X86_64_1E) },
1859   { X86_64_TABLE (X86_64_1F) },
1860   /* 20 */
1861   { "andB",             { Ebh1, Gb }, 0 },
1862   { "andS",             { Evh1, Gv }, 0 },
1863   { "andB",             { Gb, EbS }, 0 },
1864   { "andS",             { Gv, EvS }, 0 },
1865   { "andB",             { AL, Ib }, 0 },
1866   { "andS",             { eAX, Iv }, 0 },
1867   { Bad_Opcode },       /* SEG ES prefix */
1868   { X86_64_TABLE (X86_64_27) },
1869   /* 28 */
1870   { "subB",             { Ebh1, Gb }, 0 },
1871   { "subS",             { Evh1, Gv }, 0 },
1872   { "subB",             { Gb, EbS }, 0 },
1873   { "subS",             { Gv, EvS }, 0 },
1874   { "subB",             { AL, Ib }, 0 },
1875   { "subS",             { eAX, Iv }, 0 },
1876   { Bad_Opcode },       /* SEG CS prefix */
1877   { X86_64_TABLE (X86_64_2F) },
1878   /* 30 */
1879   { "xorB",             { Ebh1, Gb }, 0 },
1880   { "xorS",             { Evh1, Gv }, 0 },
1881   { "xorB",             { Gb, EbS }, 0 },
1882   { "xorS",             { Gv, EvS }, 0 },
1883   { "xorB",             { AL, Ib }, 0 },
1884   { "xorS",             { eAX, Iv }, 0 },
1885   { Bad_Opcode },       /* SEG SS prefix */
1886   { X86_64_TABLE (X86_64_37) },
1887   /* 38 */
1888   { "cmpB",             { Eb, Gb }, 0 },
1889   { "cmpS",             { Ev, Gv }, 0 },
1890   { "cmpB",             { Gb, EbS }, 0 },
1891   { "cmpS",             { Gv, EvS }, 0 },
1892   { "cmpB",             { AL, Ib }, 0 },
1893   { "cmpS",             { eAX, Iv }, 0 },
1894   { Bad_Opcode },       /* SEG DS prefix */
1895   { X86_64_TABLE (X86_64_3F) },
1896   /* 40 */
1897   { "inc{S|}",          { RMeAX }, 0 },
1898   { "inc{S|}",          { RMeCX }, 0 },
1899   { "inc{S|}",          { RMeDX }, 0 },
1900   { "inc{S|}",          { RMeBX }, 0 },
1901   { "inc{S|}",          { RMeSP }, 0 },
1902   { "inc{S|}",          { RMeBP }, 0 },
1903   { "inc{S|}",          { RMeSI }, 0 },
1904   { "inc{S|}",          { RMeDI }, 0 },
1905   /* 48 */
1906   { "dec{S|}",          { RMeAX }, 0 },
1907   { "dec{S|}",          { RMeCX }, 0 },
1908   { "dec{S|}",          { RMeDX }, 0 },
1909   { "dec{S|}",          { RMeBX }, 0 },
1910   { "dec{S|}",          { RMeSP }, 0 },
1911   { "dec{S|}",          { RMeBP }, 0 },
1912   { "dec{S|}",          { RMeSI }, 0 },
1913   { "dec{S|}",          { RMeDI }, 0 },
1914   /* 50 */
1915   { "push{!P|}",                { RMrAX }, 0 },
1916   { "push{!P|}",                { RMrCX }, 0 },
1917   { "push{!P|}",                { RMrDX }, 0 },
1918   { "push{!P|}",                { RMrBX }, 0 },
1919   { "push{!P|}",                { RMrSP }, 0 },
1920   { "push{!P|}",                { RMrBP }, 0 },
1921   { "push{!P|}",                { RMrSI }, 0 },
1922   { "push{!P|}",                { RMrDI }, 0 },
1923   /* 58 */
1924   { "pop{!P|}",         { RMrAX }, 0 },
1925   { "pop{!P|}",         { RMrCX }, 0 },
1926   { "pop{!P|}",         { RMrDX }, 0 },
1927   { "pop{!P|}",         { RMrBX }, 0 },
1928   { "pop{!P|}",         { RMrSP }, 0 },
1929   { "pop{!P|}",         { RMrBP }, 0 },
1930   { "pop{!P|}",         { RMrSI }, 0 },
1931   { "pop{!P|}",         { RMrDI }, 0 },
1932   /* 60 */
1933   { X86_64_TABLE (X86_64_60) },
1934   { X86_64_TABLE (X86_64_61) },
1935   { X86_64_TABLE (X86_64_62) },
1936   { X86_64_TABLE (X86_64_63) },
1937   { Bad_Opcode },       /* seg fs */
1938   { Bad_Opcode },       /* seg gs */
1939   { Bad_Opcode },       /* op size prefix */
1940   { Bad_Opcode },       /* adr size prefix */
1941   /* 68 */
1942   { "pushP",            { sIv }, 0 },
1943   { "imulS",            { Gv, Ev, Iv }, 0 },
1944   { "pushP",            { sIbT }, 0 },
1945   { "imulS",            { Gv, Ev, sIb }, 0 },
1946   { "ins{b|}",          { Ybr, indirDX }, 0 },
1947   { X86_64_TABLE (X86_64_6D) },
1948   { "outs{b|}",         { indirDXr, Xb }, 0 },
1949   { X86_64_TABLE (X86_64_6F) },
1950   /* 70 */
1951   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1952   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1953   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1954   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1955   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1956   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1957   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1958   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1959   /* 78 */
1960   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1961   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1962   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1963   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1964   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1965   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1966   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1967   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1968   /* 80 */
1969   { REG_TABLE (REG_80) },
1970   { REG_TABLE (REG_81) },
1971   { X86_64_TABLE (X86_64_82) },
1972   { REG_TABLE (REG_83) },
1973   { "testB",            { Eb, Gb }, 0 },
1974   { "testS",            { Ev, Gv }, 0 },
1975   { "xchgB",            { Ebh2, Gb }, 0 },
1976   { "xchgS",            { Evh2, Gv }, 0 },
1977   /* 88 */
1978   { "movB",             { Ebh3, Gb }, 0 },
1979   { "movS",             { Evh3, Gv }, 0 },
1980   { "movB",             { Gb, EbS }, 0 },
1981   { "movS",             { Gv, EvS }, 0 },
1982   { "movD",             { Sv, Sw }, 0 },
1983   { MOD_TABLE (MOD_8D) },
1984   { "movD",             { Sw, Sv }, 0 },
1985   { REG_TABLE (REG_8F) },
1986   /* 90 */
1987   { PREFIX_TABLE (PREFIX_90) },
1988   { "xchgS",            { RMeCX, eAX }, 0 },
1989   { "xchgS",            { RMeDX, eAX }, 0 },
1990   { "xchgS",            { RMeBX, eAX }, 0 },
1991   { "xchgS",            { RMeSP, eAX }, 0 },
1992   { "xchgS",            { RMeBP, eAX }, 0 },
1993   { "xchgS",            { RMeSI, eAX }, 0 },
1994   { "xchgS",            { RMeDI, eAX }, 0 },
1995   /* 98 */
1996   { "cW{t|}R",          { XX }, 0 },
1997   { "cR{t|}O",          { XX }, 0 },
1998   { X86_64_TABLE (X86_64_9A) },
1999   { Bad_Opcode },       /* fwait */
2000   { "pushfP",           { XX }, 0 },
2001   { "popfP",            { XX }, 0 },
2002   { "sahf",             { XX }, 0 },
2003   { "lahf",             { XX }, 0 },
2004   /* a0 */
2005   { "mov%LB",           { AL, Ob }, 0 },
2006   { "mov%LS",           { eAX, Ov }, 0 },
2007   { "mov%LB",           { Ob, AL }, 0 },
2008   { "mov%LS",           { Ov, eAX }, 0 },
2009   { "movs{b|}",         { Ybr, Xb }, 0 },
2010   { "movs{R|}",         { Yvr, Xv }, 0 },
2011   { "cmps{b|}",         { Xb, Yb }, 0 },
2012   { "cmps{R|}",         { Xv, Yv }, 0 },
2013   /* a8 */
2014   { "testB",            { AL, Ib }, 0 },
2015   { "testS",            { eAX, Iv }, 0 },
2016   { "stosB",            { Ybr, AL }, 0 },
2017   { "stosS",            { Yvr, eAX }, 0 },
2018   { "lodsB",            { ALr, Xb }, 0 },
2019   { "lodsS",            { eAXr, Xv }, 0 },
2020   { "scasB",            { AL, Yb }, 0 },
2021   { "scasS",            { eAX, Yv }, 0 },
2022   /* b0 */
2023   { "movB",             { RMAL, Ib }, 0 },
2024   { "movB",             { RMCL, Ib }, 0 },
2025   { "movB",             { RMDL, Ib }, 0 },
2026   { "movB",             { RMBL, Ib }, 0 },
2027   { "movB",             { RMAH, Ib }, 0 },
2028   { "movB",             { RMCH, Ib }, 0 },
2029   { "movB",             { RMDH, Ib }, 0 },
2030   { "movB",             { RMBH, Ib }, 0 },
2031   /* b8 */
2032   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2033   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2034   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2035   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2036   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2037   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2038   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2039   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2040   /* c0 */
2041   { REG_TABLE (REG_C0) },
2042   { REG_TABLE (REG_C1) },
2043   { X86_64_TABLE (X86_64_C2) },
2044   { X86_64_TABLE (X86_64_C3) },
2045   { X86_64_TABLE (X86_64_C4) },
2046   { X86_64_TABLE (X86_64_C5) },
2047   { REG_TABLE (REG_C6) },
2048   { REG_TABLE (REG_C7) },
2049   /* c8 */
2050   { "enterP",           { Iw, Ib }, 0 },
2051   { "leaveP",           { XX }, 0 },
2052   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2053   { "{l|}ret{|f}%LP",   { XX }, 0 },
2054   { "int3",             { XX }, 0 },
2055   { "int",              { Ib }, 0 },
2056   { X86_64_TABLE (X86_64_CE) },
2057   { "iret%LP",          { XX }, 0 },
2058   /* d0 */
2059   { REG_TABLE (REG_D0) },
2060   { REG_TABLE (REG_D1) },
2061   { REG_TABLE (REG_D2) },
2062   { REG_TABLE (REG_D3) },
2063   { X86_64_TABLE (X86_64_D4) },
2064   { X86_64_TABLE (X86_64_D5) },
2065   { Bad_Opcode },
2066   { "xlat",             { DSBX }, 0 },
2067   /* d8 */
2068   { FLOAT },
2069   { FLOAT },
2070   { FLOAT },
2071   { FLOAT },
2072   { FLOAT },
2073   { FLOAT },
2074   { FLOAT },
2075   { FLOAT },
2076   /* e0 */
2077   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2078   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2079   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2080   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2081   { "inB",              { AL, Ib }, 0 },
2082   { "inG",              { zAX, Ib }, 0 },
2083   { "outB",             { Ib, AL }, 0 },
2084   { "outG",             { Ib, zAX }, 0 },
2085   /* e8 */
2086   { X86_64_TABLE (X86_64_E8) },
2087   { X86_64_TABLE (X86_64_E9) },
2088   { X86_64_TABLE (X86_64_EA) },
2089   { "jmp",              { Jb, BND }, 0 },
2090   { "inB",              { AL, indirDX }, 0 },
2091   { "inG",              { zAX, indirDX }, 0 },
2092   { "outB",             { indirDX, AL }, 0 },
2093   { "outG",             { indirDX, zAX }, 0 },
2094   /* f0 */
2095   { Bad_Opcode },       /* lock prefix */
2096   { "int1",             { XX }, 0 },
2097   { Bad_Opcode },       /* repne */
2098   { Bad_Opcode },       /* repz */
2099   { "hlt",              { XX }, 0 },
2100   { "cmc",              { XX }, 0 },
2101   { REG_TABLE (REG_F6) },
2102   { REG_TABLE (REG_F7) },
2103   /* f8 */
2104   { "clc",              { XX }, 0 },
2105   { "stc",              { XX }, 0 },
2106   { "cli",              { XX }, 0 },
2107   { "sti",              { XX }, 0 },
2108   { "cld",              { XX }, 0 },
2109   { "std",              { XX }, 0 },
2110   { REG_TABLE (REG_FE) },
2111   { REG_TABLE (REG_FF) },
2112 };
2113
2114 static const struct dis386 dis386_twobyte[] = {
2115   /* 00 */
2116   { REG_TABLE (REG_0F00 ) },
2117   { REG_TABLE (REG_0F01 ) },
2118   { "larS",             { Gv, Ew }, 0 },
2119   { "lslS",             { Gv, Ew }, 0 },
2120   { Bad_Opcode },
2121   { "syscall",          { XX }, 0 },
2122   { "clts",             { XX }, 0 },
2123   { "sysret%LQ",                { XX }, 0 },
2124   /* 08 */
2125   { "invd",             { XX }, 0 },
2126   { PREFIX_TABLE (PREFIX_0F09) },
2127   { Bad_Opcode },
2128   { "ud2",              { XX }, 0 },
2129   { Bad_Opcode },
2130   { REG_TABLE (REG_0F0D) },
2131   { "femms",            { XX }, 0 },
2132   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2133   /* 10 */
2134   { PREFIX_TABLE (PREFIX_0F10) },
2135   { PREFIX_TABLE (PREFIX_0F11) },
2136   { PREFIX_TABLE (PREFIX_0F12) },
2137   { MOD_TABLE (MOD_0F13) },
2138   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2139   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2140   { PREFIX_TABLE (PREFIX_0F16) },
2141   { MOD_TABLE (MOD_0F17) },
2142   /* 18 */
2143   { REG_TABLE (REG_0F18) },
2144   { "nopQ",             { Ev }, 0 },
2145   { PREFIX_TABLE (PREFIX_0F1A) },
2146   { PREFIX_TABLE (PREFIX_0F1B) },
2147   { PREFIX_TABLE (PREFIX_0F1C) },
2148   { "nopQ",             { Ev }, 0 },
2149   { PREFIX_TABLE (PREFIX_0F1E) },
2150   { "nopQ",             { Ev }, 0 },
2151   /* 20 */
2152   { "movZ",             { Em, Cm }, 0 },
2153   { "movZ",             { Em, Dm }, 0 },
2154   { "movZ",             { Cm, Em }, 0 },
2155   { "movZ",             { Dm, Em }, 0 },
2156   { X86_64_TABLE (X86_64_0F24) },
2157   { Bad_Opcode },
2158   { X86_64_TABLE (X86_64_0F26) },
2159   { Bad_Opcode },
2160   /* 28 */
2161   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2162   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2163   { PREFIX_TABLE (PREFIX_0F2A) },
2164   { PREFIX_TABLE (PREFIX_0F2B) },
2165   { PREFIX_TABLE (PREFIX_0F2C) },
2166   { PREFIX_TABLE (PREFIX_0F2D) },
2167   { PREFIX_TABLE (PREFIX_0F2E) },
2168   { PREFIX_TABLE (PREFIX_0F2F) },
2169   /* 30 */
2170   { "wrmsr",            { XX }, 0 },
2171   { "rdtsc",            { XX }, 0 },
2172   { "rdmsr",            { XX }, 0 },
2173   { "rdpmc",            { XX }, 0 },
2174   { "sysenter",         { SEP }, 0 },
2175   { "sysexit%LQ",       { SEP }, 0 },
2176   { Bad_Opcode },
2177   { "getsec",           { XX }, 0 },
2178   /* 38 */
2179   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2180   { Bad_Opcode },
2181   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2182   { Bad_Opcode },
2183   { Bad_Opcode },
2184   { Bad_Opcode },
2185   { Bad_Opcode },
2186   { Bad_Opcode },
2187   /* 40 */
2188   { "cmovoS",           { Gv, Ev }, 0 },
2189   { "cmovnoS",          { Gv, Ev }, 0 },
2190   { "cmovbS",           { Gv, Ev }, 0 },
2191   { "cmovaeS",          { Gv, Ev }, 0 },
2192   { "cmoveS",           { Gv, Ev }, 0 },
2193   { "cmovneS",          { Gv, Ev }, 0 },
2194   { "cmovbeS",          { Gv, Ev }, 0 },
2195   { "cmovaS",           { Gv, Ev }, 0 },
2196   /* 48 */
2197   { "cmovsS",           { Gv, Ev }, 0 },
2198   { "cmovnsS",          { Gv, Ev }, 0 },
2199   { "cmovpS",           { Gv, Ev }, 0 },
2200   { "cmovnpS",          { Gv, Ev }, 0 },
2201   { "cmovlS",           { Gv, Ev }, 0 },
2202   { "cmovgeS",          { Gv, Ev }, 0 },
2203   { "cmovleS",          { Gv, Ev }, 0 },
2204   { "cmovgS",           { Gv, Ev }, 0 },
2205   /* 50 */
2206   { MOD_TABLE (MOD_0F50) },
2207   { PREFIX_TABLE (PREFIX_0F51) },
2208   { PREFIX_TABLE (PREFIX_0F52) },
2209   { PREFIX_TABLE (PREFIX_0F53) },
2210   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2211   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2212   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2213   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2214   /* 58 */
2215   { PREFIX_TABLE (PREFIX_0F58) },
2216   { PREFIX_TABLE (PREFIX_0F59) },
2217   { PREFIX_TABLE (PREFIX_0F5A) },
2218   { PREFIX_TABLE (PREFIX_0F5B) },
2219   { PREFIX_TABLE (PREFIX_0F5C) },
2220   { PREFIX_TABLE (PREFIX_0F5D) },
2221   { PREFIX_TABLE (PREFIX_0F5E) },
2222   { PREFIX_TABLE (PREFIX_0F5F) },
2223   /* 60 */
2224   { PREFIX_TABLE (PREFIX_0F60) },
2225   { PREFIX_TABLE (PREFIX_0F61) },
2226   { PREFIX_TABLE (PREFIX_0F62) },
2227   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2228   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2229   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2230   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2231   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2232   /* 68 */
2233   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2234   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2235   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2236   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2237   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2238   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2239   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2240   { PREFIX_TABLE (PREFIX_0F6F) },
2241   /* 70 */
2242   { PREFIX_TABLE (PREFIX_0F70) },
2243   { MOD_TABLE (MOD_0F71) },
2244   { MOD_TABLE (MOD_0F72) },
2245   { MOD_TABLE (MOD_0F73) },
2246   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2247   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2248   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2249   { "emms",             { XX }, PREFIX_OPCODE },
2250   /* 78 */
2251   { PREFIX_TABLE (PREFIX_0F78) },
2252   { PREFIX_TABLE (PREFIX_0F79) },
2253   { Bad_Opcode },
2254   { Bad_Opcode },
2255   { PREFIX_TABLE (PREFIX_0F7C) },
2256   { PREFIX_TABLE (PREFIX_0F7D) },
2257   { PREFIX_TABLE (PREFIX_0F7E) },
2258   { PREFIX_TABLE (PREFIX_0F7F) },
2259   /* 80 */
2260   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2261   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2262   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2263   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2264   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2265   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2266   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2267   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2268   /* 88 */
2269   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2270   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2271   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2272   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2273   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2274   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2275   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2276   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2277   /* 90 */
2278   { "seto",             { Eb }, 0 },
2279   { "setno",            { Eb }, 0 },
2280   { "setb",             { Eb }, 0 },
2281   { "setae",            { Eb }, 0 },
2282   { "sete",             { Eb }, 0 },
2283   { "setne",            { Eb }, 0 },
2284   { "setbe",            { Eb }, 0 },
2285   { "seta",             { Eb }, 0 },
2286   /* 98 */
2287   { "sets",             { Eb }, 0 },
2288   { "setns",            { Eb }, 0 },
2289   { "setp",             { Eb }, 0 },
2290   { "setnp",            { Eb }, 0 },
2291   { "setl",             { Eb }, 0 },
2292   { "setge",            { Eb }, 0 },
2293   { "setle",            { Eb }, 0 },
2294   { "setg",             { Eb }, 0 },
2295   /* a0 */
2296   { "pushP",            { fs }, 0 },
2297   { "popP",             { fs }, 0 },
2298   { "cpuid",            { XX }, 0 },
2299   { "btS",              { Ev, Gv }, 0 },
2300   { "shldS",            { Ev, Gv, Ib }, 0 },
2301   { "shldS",            { Ev, Gv, CL }, 0 },
2302   { REG_TABLE (REG_0FA6) },
2303   { REG_TABLE (REG_0FA7) },
2304   /* a8 */
2305   { "pushP",            { gs }, 0 },
2306   { "popP",             { gs }, 0 },
2307   { "rsm",              { XX }, 0 },
2308   { "btsS",             { Evh1, Gv }, 0 },
2309   { "shrdS",            { Ev, Gv, Ib }, 0 },
2310   { "shrdS",            { Ev, Gv, CL }, 0 },
2311   { REG_TABLE (REG_0FAE) },
2312   { "imulS",            { Gv, Ev }, 0 },
2313   /* b0 */
2314   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2315   { "cmpxchgS",         { Evh1, Gv }, 0 },
2316   { MOD_TABLE (MOD_0FB2) },
2317   { "btrS",             { Evh1, Gv }, 0 },
2318   { MOD_TABLE (MOD_0FB4) },
2319   { MOD_TABLE (MOD_0FB5) },
2320   { "movz{bR|x}",       { Gv, Eb }, 0 },
2321   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2322   /* b8 */
2323   { PREFIX_TABLE (PREFIX_0FB8) },
2324   { "ud1S",             { Gv, Ev }, 0 },
2325   { REG_TABLE (REG_0FBA) },
2326   { "btcS",             { Evh1, Gv }, 0 },
2327   { PREFIX_TABLE (PREFIX_0FBC) },
2328   { PREFIX_TABLE (PREFIX_0FBD) },
2329   { "movs{bR|x}",       { Gv, Eb }, 0 },
2330   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2331   /* c0 */
2332   { "xaddB",            { Ebh1, Gb }, 0 },
2333   { "xaddS",            { Evh1, Gv }, 0 },
2334   { PREFIX_TABLE (PREFIX_0FC2) },
2335   { MOD_TABLE (MOD_0FC3) },
2336   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2337   { "pextrw",           { Gd, MS, Ib }, PREFIX_OPCODE },
2338   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2339   { REG_TABLE (REG_0FC7) },
2340   /* c8 */
2341   { "bswap",            { RMeAX }, 0 },
2342   { "bswap",            { RMeCX }, 0 },
2343   { "bswap",            { RMeDX }, 0 },
2344   { "bswap",            { RMeBX }, 0 },
2345   { "bswap",            { RMeSP }, 0 },
2346   { "bswap",            { RMeBP }, 0 },
2347   { "bswap",            { RMeSI }, 0 },
2348   { "bswap",            { RMeDI }, 0 },
2349   /* d0 */
2350   { PREFIX_TABLE (PREFIX_0FD0) },
2351   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2352   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2353   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2354   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2355   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2356   { PREFIX_TABLE (PREFIX_0FD6) },
2357   { MOD_TABLE (MOD_0FD7) },
2358   /* d8 */
2359   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2360   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2361   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2362   { "pand",             { MX, EM }, PREFIX_OPCODE },
2363   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2364   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2365   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2366   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2367   /* e0 */
2368   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2369   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2370   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2371   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2372   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2373   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2374   { PREFIX_TABLE (PREFIX_0FE6) },
2375   { PREFIX_TABLE (PREFIX_0FE7) },
2376   /* e8 */
2377   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2378   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2379   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2380   { "por",              { MX, EM }, PREFIX_OPCODE },
2381   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2382   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2383   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2384   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2385   /* f0 */
2386   { PREFIX_TABLE (PREFIX_0FF0) },
2387   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2388   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2389   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2390   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2391   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2392   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2393   { PREFIX_TABLE (PREFIX_0FF7) },
2394   /* f8 */
2395   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2396   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2397   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2398   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2399   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2400   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2401   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2402   { "ud0S",             { Gv, Ev }, 0 },
2403 };
2404
2405 static const bool onebyte_has_modrm[256] = {
2406   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2407   /*       -------------------------------        */
2408   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2409   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2410   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2411   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2412   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2413   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2414   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2415   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2416   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2417   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2418   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2419   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2420   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2421   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2422   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2423   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2424   /*       -------------------------------        */
2425   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2426 };
2427
2428 static const bool twobyte_has_modrm[256] = {
2429   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2430   /*       -------------------------------        */
2431   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2432   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2433   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2434   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2435   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2436   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2437   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2438   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2439   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2440   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2441   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2442   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2443   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2444   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2445   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2446   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2447   /*       -------------------------------        */
2448   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2449 };
2450
2451
2452 struct op
2453   {
2454     const char *name;
2455     unsigned int len;
2456   };
2457
2458 /* If we are accessing mod/rm/reg without need_modrm set, then the
2459    values are stale.  Hitting this abort likely indicates that you
2460    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2461 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2462
2463 static const char *const intel_index16[] = {
2464   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2465 };
2466
2467 static const char *const att_names64[] = {
2468   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2469   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2470 };
2471 static const char *const att_names32[] = {
2472   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2473   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2474 };
2475 static const char *const att_names16[] = {
2476   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2477   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2478 };
2479 static const char *const att_names8[] = {
2480   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2481 };
2482 static const char *const att_names8rex[] = {
2483   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2484   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2485 };
2486 static const char *const att_names_seg[] = {
2487   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2488 };
2489 static const char att_index64[] = "%riz";
2490 static const char att_index32[] = "%eiz";
2491 static const char *const att_index16[] = {
2492   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2493 };
2494
2495 static const char *const att_names_mm[] = {
2496   "%mm0", "%mm1", "%mm2", "%mm3",
2497   "%mm4", "%mm5", "%mm6", "%mm7"
2498 };
2499
2500 static const char *const att_names_bnd[] = {
2501   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2502 };
2503
2504 static const char *const att_names_xmm[] = {
2505   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2506   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2507   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2508   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2509   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2510   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2511   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2512   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2513 };
2514
2515 static const char *const att_names_ymm[] = {
2516   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2517   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2518   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2519   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2520   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2521   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2522   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2523   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2524 };
2525
2526 static const char *const att_names_zmm[] = {
2527   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2528   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2529   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2530   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2531   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2532   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2533   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2534   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2535 };
2536
2537 static const char *const att_names_tmm[] = {
2538   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2539   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2540 };
2541
2542 static const char *const att_names_mask[] = {
2543   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2544 };
2545
2546 static const char *const names_rounding[] =
2547 {
2548   "{rn-",
2549   "{rd-",
2550   "{ru-",
2551   "{rz-"
2552 };
2553
2554 static const struct dis386 reg_table[][8] = {
2555   /* REG_80 */
2556   {
2557     { "addA",   { Ebh1, Ib }, 0 },
2558     { "orA",    { Ebh1, Ib }, 0 },
2559     { "adcA",   { Ebh1, Ib }, 0 },
2560     { "sbbA",   { Ebh1, Ib }, 0 },
2561     { "andA",   { Ebh1, Ib }, 0 },
2562     { "subA",   { Ebh1, Ib }, 0 },
2563     { "xorA",   { Ebh1, Ib }, 0 },
2564     { "cmpA",   { Eb, Ib }, 0 },
2565   },
2566   /* REG_81 */
2567   {
2568     { "addQ",   { Evh1, Iv }, 0 },
2569     { "orQ",    { Evh1, Iv }, 0 },
2570     { "adcQ",   { Evh1, Iv }, 0 },
2571     { "sbbQ",   { Evh1, Iv }, 0 },
2572     { "andQ",   { Evh1, Iv }, 0 },
2573     { "subQ",   { Evh1, Iv }, 0 },
2574     { "xorQ",   { Evh1, Iv }, 0 },
2575     { "cmpQ",   { Ev, Iv }, 0 },
2576   },
2577   /* REG_83 */
2578   {
2579     { "addQ",   { Evh1, sIb }, 0 },
2580     { "orQ",    { Evh1, sIb }, 0 },
2581     { "adcQ",   { Evh1, sIb }, 0 },
2582     { "sbbQ",   { Evh1, sIb }, 0 },
2583     { "andQ",   { Evh1, sIb }, 0 },
2584     { "subQ",   { Evh1, sIb }, 0 },
2585     { "xorQ",   { Evh1, sIb }, 0 },
2586     { "cmpQ",   { Ev, sIb }, 0 },
2587   },
2588   /* REG_8F */
2589   {
2590     { "pop{P|}", { stackEv }, 0 },
2591     { XOP_8F_TABLE (XOP_09) },
2592     { Bad_Opcode },
2593     { Bad_Opcode },
2594     { Bad_Opcode },
2595     { XOP_8F_TABLE (XOP_09) },
2596   },
2597   /* REG_C0 */
2598   {
2599     { "rolA",   { Eb, Ib }, 0 },
2600     { "rorA",   { Eb, Ib }, 0 },
2601     { "rclA",   { Eb, Ib }, 0 },
2602     { "rcrA",   { Eb, Ib }, 0 },
2603     { "shlA",   { Eb, Ib }, 0 },
2604     { "shrA",   { Eb, Ib }, 0 },
2605     { "shlA",   { Eb, Ib }, 0 },
2606     { "sarA",   { Eb, Ib }, 0 },
2607   },
2608   /* REG_C1 */
2609   {
2610     { "rolQ",   { Ev, Ib }, 0 },
2611     { "rorQ",   { Ev, Ib }, 0 },
2612     { "rclQ",   { Ev, Ib }, 0 },
2613     { "rcrQ",   { Ev, Ib }, 0 },
2614     { "shlQ",   { Ev, Ib }, 0 },
2615     { "shrQ",   { Ev, Ib }, 0 },
2616     { "shlQ",   { Ev, Ib }, 0 },
2617     { "sarQ",   { Ev, Ib }, 0 },
2618   },
2619   /* REG_C6 */
2620   {
2621     { "movA",   { Ebh3, Ib }, 0 },
2622     { Bad_Opcode },
2623     { Bad_Opcode },
2624     { Bad_Opcode },
2625     { Bad_Opcode },
2626     { Bad_Opcode },
2627     { Bad_Opcode },
2628     { MOD_TABLE (MOD_C6_REG_7) },
2629   },
2630   /* REG_C7 */
2631   {
2632     { "movQ",   { Evh3, Iv }, 0 },
2633     { Bad_Opcode },
2634     { Bad_Opcode },
2635     { Bad_Opcode },
2636     { Bad_Opcode },
2637     { Bad_Opcode },
2638     { Bad_Opcode },
2639     { MOD_TABLE (MOD_C7_REG_7) },
2640   },
2641   /* REG_D0 */
2642   {
2643     { "rolA",   { Eb, I1 }, 0 },
2644     { "rorA",   { Eb, I1 }, 0 },
2645     { "rclA",   { Eb, I1 }, 0 },
2646     { "rcrA",   { Eb, I1 }, 0 },
2647     { "shlA",   { Eb, I1 }, 0 },
2648     { "shrA",   { Eb, I1 }, 0 },
2649     { "shlA",   { Eb, I1 }, 0 },
2650     { "sarA",   { Eb, I1 }, 0 },
2651   },
2652   /* REG_D1 */
2653   {
2654     { "rolQ",   { Ev, I1 }, 0 },
2655     { "rorQ",   { Ev, I1 }, 0 },
2656     { "rclQ",   { Ev, I1 }, 0 },
2657     { "rcrQ",   { Ev, I1 }, 0 },
2658     { "shlQ",   { Ev, I1 }, 0 },
2659     { "shrQ",   { Ev, I1 }, 0 },
2660     { "shlQ",   { Ev, I1 }, 0 },
2661     { "sarQ",   { Ev, I1 }, 0 },
2662   },
2663   /* REG_D2 */
2664   {
2665     { "rolA",   { Eb, CL }, 0 },
2666     { "rorA",   { Eb, CL }, 0 },
2667     { "rclA",   { Eb, CL }, 0 },
2668     { "rcrA",   { Eb, CL }, 0 },
2669     { "shlA",   { Eb, CL }, 0 },
2670     { "shrA",   { Eb, CL }, 0 },
2671     { "shlA",   { Eb, CL }, 0 },
2672     { "sarA",   { Eb, CL }, 0 },
2673   },
2674   /* REG_D3 */
2675   {
2676     { "rolQ",   { Ev, CL }, 0 },
2677     { "rorQ",   { Ev, CL }, 0 },
2678     { "rclQ",   { Ev, CL }, 0 },
2679     { "rcrQ",   { Ev, CL }, 0 },
2680     { "shlQ",   { Ev, CL }, 0 },
2681     { "shrQ",   { Ev, CL }, 0 },
2682     { "shlQ",   { Ev, CL }, 0 },
2683     { "sarQ",   { Ev, CL }, 0 },
2684   },
2685   /* REG_F6 */
2686   {
2687     { "testA",  { Eb, Ib }, 0 },
2688     { "testA",  { Eb, Ib }, 0 },
2689     { "notA",   { Ebh1 }, 0 },
2690     { "negA",   { Ebh1 }, 0 },
2691     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2692     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2693     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2694     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2695   },
2696   /* REG_F7 */
2697   {
2698     { "testQ",  { Ev, Iv }, 0 },
2699     { "testQ",  { Ev, Iv }, 0 },
2700     { "notQ",   { Evh1 }, 0 },
2701     { "negQ",   { Evh1 }, 0 },
2702     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2703     { "imulQ",  { Ev }, 0 },
2704     { "divQ",   { Ev }, 0 },
2705     { "idivQ",  { Ev }, 0 },
2706   },
2707   /* REG_FE */
2708   {
2709     { "incA",   { Ebh1 }, 0 },
2710     { "decA",   { Ebh1 }, 0 },
2711   },
2712   /* REG_FF */
2713   {
2714     { "incQ",   { Evh1 }, 0 },
2715     { "decQ",   { Evh1 }, 0 },
2716     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2717     { MOD_TABLE (MOD_FF_REG_3) },
2718     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2719     { MOD_TABLE (MOD_FF_REG_5) },
2720     { "push{P|}", { stackEv }, 0 },
2721     { Bad_Opcode },
2722   },
2723   /* REG_0F00 */
2724   {
2725     { "sldtD",  { Sv }, 0 },
2726     { "strD",   { Sv }, 0 },
2727     { "lldt",   { Ew }, 0 },
2728     { "ltr",    { Ew }, 0 },
2729     { "verr",   { Ew }, 0 },
2730     { "verw",   { Ew }, 0 },
2731     { Bad_Opcode },
2732     { Bad_Opcode },
2733   },
2734   /* REG_0F01 */
2735   {
2736     { MOD_TABLE (MOD_0F01_REG_0) },
2737     { MOD_TABLE (MOD_0F01_REG_1) },
2738     { MOD_TABLE (MOD_0F01_REG_2) },
2739     { MOD_TABLE (MOD_0F01_REG_3) },
2740     { "smswD",  { Sv }, 0 },
2741     { MOD_TABLE (MOD_0F01_REG_5) },
2742     { "lmsw",   { Ew }, 0 },
2743     { MOD_TABLE (MOD_0F01_REG_7) },
2744   },
2745   /* REG_0F0D */
2746   {
2747     { "prefetch",       { Mb }, 0 },
2748     { "prefetchw",      { Mb }, 0 },
2749     { "prefetchwt1",    { Mb }, 0 },
2750     { "prefetch",       { Mb }, 0 },
2751     { "prefetch",       { Mb }, 0 },
2752     { "prefetch",       { Mb }, 0 },
2753     { "prefetch",       { Mb }, 0 },
2754     { "prefetch",       { Mb }, 0 },
2755   },
2756   /* REG_0F18 */
2757   {
2758     { MOD_TABLE (MOD_0F18_REG_0) },
2759     { MOD_TABLE (MOD_0F18_REG_1) },
2760     { MOD_TABLE (MOD_0F18_REG_2) },
2761     { MOD_TABLE (MOD_0F18_REG_3) },
2762     { "nopQ",           { Ev }, 0 },
2763     { "nopQ",           { Ev }, 0 },
2764     { MOD_TABLE (MOD_0F18_REG_6) },
2765     { MOD_TABLE (MOD_0F18_REG_7) },
2766   },
2767   /* REG_0F1C_P_0_MOD_0 */
2768   {
2769     { "cldemote",       { Mb }, 0 },
2770     { "nopQ",           { Ev }, 0 },
2771     { "nopQ",           { Ev }, 0 },
2772     { "nopQ",           { Ev }, 0 },
2773     { "nopQ",           { Ev }, 0 },
2774     { "nopQ",           { Ev }, 0 },
2775     { "nopQ",           { Ev }, 0 },
2776     { "nopQ",           { Ev }, 0 },
2777   },
2778   /* REG_0F1E_P_1_MOD_3 */
2779   {
2780     { "nopQ",           { Ev }, PREFIX_IGNORED },
2781     { "rdsspK",         { Edq }, 0 },
2782     { "nopQ",           { Ev }, PREFIX_IGNORED },
2783     { "nopQ",           { Ev }, PREFIX_IGNORED },
2784     { "nopQ",           { Ev }, PREFIX_IGNORED },
2785     { "nopQ",           { Ev }, PREFIX_IGNORED },
2786     { "nopQ",           { Ev }, PREFIX_IGNORED },
2787     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2788   },
2789   /* REG_0F38D8_PREFIX_1 */
2790   {
2791     { "aesencwide128kl",        { M }, 0 },
2792     { "aesdecwide128kl",        { M }, 0 },
2793     { "aesencwide256kl",        { M }, 0 },
2794     { "aesdecwide256kl",        { M }, 0 },
2795   },
2796   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2797   {
2798     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2799   },
2800   /* REG_0F71_MOD_0 */
2801   {
2802     { Bad_Opcode },
2803     { Bad_Opcode },
2804     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2805     { Bad_Opcode },
2806     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2807     { Bad_Opcode },
2808     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2809   },
2810   /* REG_0F72_MOD_0 */
2811   {
2812     { Bad_Opcode },
2813     { Bad_Opcode },
2814     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2815     { Bad_Opcode },
2816     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2817     { Bad_Opcode },
2818     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2819   },
2820   /* REG_0F73_MOD_0 */
2821   {
2822     { Bad_Opcode },
2823     { Bad_Opcode },
2824     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2825     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2826     { Bad_Opcode },
2827     { Bad_Opcode },
2828     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2829     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2830   },
2831   /* REG_0FA6 */
2832   {
2833     { "montmul",        { { OP_0f07, 0 } }, 0 },
2834     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2835     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2836   },
2837   /* REG_0FA7 */
2838   {
2839     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2840     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2841     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2842     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2843     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2844     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2845   },
2846   /* REG_0FAE */
2847   {
2848     { MOD_TABLE (MOD_0FAE_REG_0) },
2849     { MOD_TABLE (MOD_0FAE_REG_1) },
2850     { MOD_TABLE (MOD_0FAE_REG_2) },
2851     { MOD_TABLE (MOD_0FAE_REG_3) },
2852     { MOD_TABLE (MOD_0FAE_REG_4) },
2853     { MOD_TABLE (MOD_0FAE_REG_5) },
2854     { MOD_TABLE (MOD_0FAE_REG_6) },
2855     { MOD_TABLE (MOD_0FAE_REG_7) },
2856   },
2857   /* REG_0FBA */
2858   {
2859     { Bad_Opcode },
2860     { Bad_Opcode },
2861     { Bad_Opcode },
2862     { Bad_Opcode },
2863     { "btQ",    { Ev, Ib }, 0 },
2864     { "btsQ",   { Evh1, Ib }, 0 },
2865     { "btrQ",   { Evh1, Ib }, 0 },
2866     { "btcQ",   { Evh1, Ib }, 0 },
2867   },
2868   /* REG_0FC7 */
2869   {
2870     { Bad_Opcode },
2871     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2872     { Bad_Opcode },
2873     { MOD_TABLE (MOD_0FC7_REG_3) },
2874     { MOD_TABLE (MOD_0FC7_REG_4) },
2875     { MOD_TABLE (MOD_0FC7_REG_5) },
2876     { MOD_TABLE (MOD_0FC7_REG_6) },
2877     { MOD_TABLE (MOD_0FC7_REG_7) },
2878   },
2879   /* REG_VEX_0F71_M_0 */
2880   {
2881     { Bad_Opcode },
2882     { Bad_Opcode },
2883     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2884     { Bad_Opcode },
2885     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2886     { Bad_Opcode },
2887     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2888   },
2889   /* REG_VEX_0F72_M_0 */
2890   {
2891     { Bad_Opcode },
2892     { Bad_Opcode },
2893     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2894     { Bad_Opcode },
2895     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2896     { Bad_Opcode },
2897     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2898   },
2899   /* REG_VEX_0F73_M_0 */
2900   {
2901     { Bad_Opcode },
2902     { Bad_Opcode },
2903     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2904     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2905     { Bad_Opcode },
2906     { Bad_Opcode },
2907     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2908     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2909   },
2910   /* REG_VEX_0FAE */
2911   {
2912     { Bad_Opcode },
2913     { Bad_Opcode },
2914     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2915     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2916   },
2917   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2918   {
2919     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2920   },
2921   /* REG_VEX_0F38F3_L_0 */
2922   {
2923     { Bad_Opcode },
2924     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2925     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2926     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2927   },
2928   /* REG_XOP_09_01_L_0 */
2929   {
2930     { Bad_Opcode },
2931     { "blcfill",        { VexGdq, Edq }, 0 },
2932     { "blsfill",        { VexGdq, Edq }, 0 },
2933     { "blcs",   { VexGdq, Edq }, 0 },
2934     { "tzmsk",  { VexGdq, Edq }, 0 },
2935     { "blcic",  { VexGdq, Edq }, 0 },
2936     { "blsic",  { VexGdq, Edq }, 0 },
2937     { "t1mskc", { VexGdq, Edq }, 0 },
2938   },
2939   /* REG_XOP_09_02_L_0 */
2940   {
2941     { Bad_Opcode },
2942     { "blcmsk", { VexGdq, Edq }, 0 },
2943     { Bad_Opcode },
2944     { Bad_Opcode },
2945     { Bad_Opcode },
2946     { Bad_Opcode },
2947     { "blci",   { VexGdq, Edq }, 0 },
2948   },
2949   /* REG_XOP_09_12_M_1_L_0 */
2950   {
2951     { "llwpcb", { Edq }, 0 },
2952     { "slwpcb", { Edq }, 0 },
2953   },
2954   /* REG_XOP_0A_12_L_0 */
2955   {
2956     { "lwpins", { VexGdq, Ed, Id }, 0 },
2957     { "lwpval", { VexGdq, Ed, Id }, 0 },
2958   },
2959
2960 #include "i386-dis-evex-reg.h"
2961 };
2962
2963 static const struct dis386 prefix_table[][4] = {
2964   /* PREFIX_90 */
2965   {
2966     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2967     { "pause", { XX }, 0 },
2968     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2969     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2970   },
2971
2972   /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
2973   {
2974     { "wrmsrns",        { Skip_MODRM }, 0 },
2975     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
2976     { Bad_Opcode },
2977     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
2978   },
2979
2980   /* PREFIX_0F01_REG_1_RM_4 */
2981   {
2982     { Bad_Opcode },
2983     { Bad_Opcode },
2984     { "tdcall",         { Skip_MODRM }, 0 },
2985     { Bad_Opcode },
2986   },
2987
2988   /* PREFIX_0F01_REG_1_RM_5 */
2989   {
2990     { Bad_Opcode },
2991     { Bad_Opcode },
2992     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2993     { Bad_Opcode },
2994   },
2995
2996   /* PREFIX_0F01_REG_1_RM_6 */
2997   {
2998     { Bad_Opcode },
2999     { Bad_Opcode },
3000     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3001     { Bad_Opcode },
3002   },
3003
3004   /* PREFIX_0F01_REG_1_RM_7 */
3005   {
3006     { "encls",          { Skip_MODRM }, 0 },
3007     { Bad_Opcode },
3008     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3009     { Bad_Opcode },
3010   },
3011
3012   /* PREFIX_0F01_REG_3_RM_1 */
3013   {
3014     { "vmmcall",        { Skip_MODRM }, 0 },
3015     { "vmgexit",        { Skip_MODRM }, 0 },
3016     { Bad_Opcode },
3017     { "vmgexit",        { Skip_MODRM }, 0 },
3018   },
3019
3020   /* PREFIX_0F01_REG_5_MOD_0 */
3021   {
3022     { Bad_Opcode },
3023     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3024   },
3025
3026   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3027   {
3028     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3029     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3030     { Bad_Opcode },
3031     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3032   },
3033
3034   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3035   {
3036     { Bad_Opcode },
3037     { Bad_Opcode },
3038     { Bad_Opcode },
3039     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3040   },
3041
3042   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3043   {
3044     { Bad_Opcode },
3045     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3046   },
3047
3048   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3049   {
3050     { Bad_Opcode },
3051     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3052   },
3053
3054   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3055   {
3056     { Bad_Opcode },
3057     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3058   },
3059
3060   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3061   {
3062     { "rdpkru", { Skip_MODRM }, 0 },
3063     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3064   },
3065
3066   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3067   {
3068     { "wrpkru", { Skip_MODRM }, 0 },
3069     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3070   },
3071
3072   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3073   {
3074     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3075     { "mcommit",        { Skip_MODRM }, 0 },
3076   },
3077
3078   /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3079   {
3080     { "rdpru", { Skip_MODRM }, 0 },
3081     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3082   },
3083
3084   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3085   {
3086     { "invlpgb",        { Skip_MODRM }, 0 },
3087     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3088     { Bad_Opcode },
3089     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3090   },
3091
3092   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3093   {
3094     { "tlbsync",        { Skip_MODRM }, 0 },
3095     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3096     { Bad_Opcode },
3097     { "pvalidate",      { Skip_MODRM }, 0 },
3098   },
3099
3100   /* PREFIX_0F09 */
3101   {
3102     { "wbinvd",   { XX }, 0 },
3103     { "wbnoinvd", { XX }, 0 },
3104   },
3105
3106   /* PREFIX_0F10 */
3107   {
3108     { "movups", { XM, EXx }, PREFIX_OPCODE },
3109     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3110     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3111     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3112   },
3113
3114   /* PREFIX_0F11 */
3115   {
3116     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3117     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3118     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3119     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3120   },
3121
3122   /* PREFIX_0F12 */
3123   {
3124     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3125     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3126     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3127     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3128   },
3129
3130   /* PREFIX_0F16 */
3131   {
3132     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3133     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3134     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3135   },
3136
3137   /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3138   {
3139     { "prefetchit1",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3140     { "nopQ",           { Ev }, 0 },
3141     { "nopQ",           { Ev }, 0 },
3142     { "nopQ",           { Ev }, 0 },
3143   },
3144
3145   /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3146   {
3147     { "prefetchit0",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3148     { "nopQ",           { Ev }, 0 },
3149     { "nopQ",           { Ev }, 0 },
3150     { "nopQ",           { Ev }, 0 },
3151   },
3152
3153   /* PREFIX_0F1A */
3154   {
3155     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3156     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3157     { "bndmov", { Gbnd, Ebnd }, 0 },
3158     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3159   },
3160
3161   /* PREFIX_0F1B */
3162   {
3163     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3164     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3165     { "bndmov", { EbndS, Gbnd }, 0 },
3166     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3167   },
3168
3169   /* PREFIX_0F1C */
3170   {
3171     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3172     { "nopQ",   { Ev }, PREFIX_IGNORED },
3173     { "nopQ",   { Ev }, 0 },
3174     { "nopQ",   { Ev }, PREFIX_IGNORED },
3175   },
3176
3177   /* PREFIX_0F1E */
3178   {
3179     { "nopQ",   { Ev }, 0 },
3180     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3181     { "nopQ",   { Ev }, 0 },
3182     { NULL,     { XX }, PREFIX_IGNORED },
3183   },
3184
3185   /* PREFIX_0F2A */
3186   {
3187     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3188     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3189     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3190     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3191   },
3192
3193   /* PREFIX_0F2B */
3194   {
3195     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3196     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3197     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3198     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3199   },
3200
3201   /* PREFIX_0F2C */
3202   {
3203     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3204     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3205     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3206     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3207   },
3208
3209   /* PREFIX_0F2D */
3210   {
3211     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3212     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3213     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3214     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3215   },
3216
3217   /* PREFIX_0F2E */
3218   {
3219     { "ucomiss",{ XM, EXd }, 0 },
3220     { Bad_Opcode },
3221     { "ucomisd",{ XM, EXq }, 0 },
3222   },
3223
3224   /* PREFIX_0F2F */
3225   {
3226     { "comiss", { XM, EXd }, 0 },
3227     { Bad_Opcode },
3228     { "comisd", { XM, EXq }, 0 },
3229   },
3230
3231   /* PREFIX_0F51 */
3232   {
3233     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3234     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3235     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3236     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3237   },
3238
3239   /* PREFIX_0F52 */
3240   {
3241     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3242     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3243   },
3244
3245   /* PREFIX_0F53 */
3246   {
3247     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3248     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3249   },
3250
3251   /* PREFIX_0F58 */
3252   {
3253     { "addps", { XM, EXx }, PREFIX_OPCODE },
3254     { "addss", { XM, EXd }, PREFIX_OPCODE },
3255     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3256     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3257   },
3258
3259   /* PREFIX_0F59 */
3260   {
3261     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3262     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3263     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3264     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3265   },
3266
3267   /* PREFIX_0F5A */
3268   {
3269     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3270     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3271     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3272     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3273   },
3274
3275   /* PREFIX_0F5B */
3276   {
3277     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3278     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3279     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3280   },
3281
3282   /* PREFIX_0F5C */
3283   {
3284     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3285     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3286     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3287     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3288   },
3289
3290   /* PREFIX_0F5D */
3291   {
3292     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3293     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3294     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3295     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3296   },
3297
3298   /* PREFIX_0F5E */
3299   {
3300     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3301     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3302     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3303     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3304   },
3305
3306   /* PREFIX_0F5F */
3307   {
3308     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3309     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3310     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3311     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3312   },
3313
3314   /* PREFIX_0F60 */
3315   {
3316     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3317     { Bad_Opcode },
3318     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3319   },
3320
3321   /* PREFIX_0F61 */
3322   {
3323     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3324     { Bad_Opcode },
3325     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3326   },
3327
3328   /* PREFIX_0F62 */
3329   {
3330     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3331     { Bad_Opcode },
3332     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3333   },
3334
3335   /* PREFIX_0F6F */
3336   {
3337     { "movq",   { MX, EM }, PREFIX_OPCODE },
3338     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3339     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3340   },
3341
3342   /* PREFIX_0F70 */
3343   {
3344     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3345     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3346     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3347     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3348   },
3349
3350   /* PREFIX_0F78 */
3351   {
3352     {"vmread",  { Em, Gm }, 0 },
3353     { Bad_Opcode },
3354     {"extrq",   { XS, Ib, Ib }, 0 },
3355     {"insertq", { XM, XS, Ib, Ib }, 0 },
3356   },
3357
3358   /* PREFIX_0F79 */
3359   {
3360     {"vmwrite", { Gm, Em }, 0 },
3361     { Bad_Opcode },
3362     {"extrq",   { XM, XS }, 0 },
3363     {"insertq", { XM, XS }, 0 },
3364   },
3365
3366   /* PREFIX_0F7C */
3367   {
3368     { Bad_Opcode },
3369     { Bad_Opcode },
3370     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3371     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3372   },
3373
3374   /* PREFIX_0F7D */
3375   {
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3379     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3380   },
3381
3382   /* PREFIX_0F7E */
3383   {
3384     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3385     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3386     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3387   },
3388
3389   /* PREFIX_0F7F */
3390   {
3391     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3392     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3393     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3394   },
3395
3396   /* PREFIX_0FAE_REG_0_MOD_3 */
3397   {
3398     { Bad_Opcode },
3399     { "rdfsbase", { Ev }, 0 },
3400   },
3401
3402   /* PREFIX_0FAE_REG_1_MOD_3 */
3403   {
3404     { Bad_Opcode },
3405     { "rdgsbase", { Ev }, 0 },
3406   },
3407
3408   /* PREFIX_0FAE_REG_2_MOD_3 */
3409   {
3410     { Bad_Opcode },
3411     { "wrfsbase", { Ev }, 0 },
3412   },
3413
3414   /* PREFIX_0FAE_REG_3_MOD_3 */
3415   {
3416     { Bad_Opcode },
3417     { "wrgsbase", { Ev }, 0 },
3418   },
3419
3420   /* PREFIX_0FAE_REG_4_MOD_0 */
3421   {
3422     { "xsave",  { FXSAVE }, 0 },
3423     { "ptwrite{%LQ|}", { Edq }, 0 },
3424   },
3425
3426   /* PREFIX_0FAE_REG_4_MOD_3 */
3427   {
3428     { Bad_Opcode },
3429     { "ptwrite{%LQ|}", { Edq }, 0 },
3430   },
3431
3432   /* PREFIX_0FAE_REG_5_MOD_3 */
3433   {
3434     { "lfence",         { Skip_MODRM }, 0 },
3435     { "incsspK",        { Edq }, PREFIX_OPCODE },
3436   },
3437
3438   /* PREFIX_0FAE_REG_6_MOD_0 */
3439   {
3440     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3441     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3442     { "clwb",   { Mb }, PREFIX_OPCODE },
3443   },
3444
3445   /* PREFIX_0FAE_REG_6_MOD_3 */
3446   {
3447     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3448     { "umonitor",       { Eva }, PREFIX_OPCODE },
3449     { "tpause", { Edq }, PREFIX_OPCODE },
3450     { "umwait", { Edq }, PREFIX_OPCODE },
3451   },
3452
3453   /* PREFIX_0FAE_REG_7_MOD_0 */
3454   {
3455     { "clflush",        { Mb }, 0 },
3456     { Bad_Opcode },
3457     { "clflushopt",     { Mb }, 0 },
3458   },
3459
3460   /* PREFIX_0FB8 */
3461   {
3462     { Bad_Opcode },
3463     { "popcntS", { Gv, Ev }, 0 },
3464   },
3465
3466   /* PREFIX_0FBC */
3467   {
3468     { "bsfS",   { Gv, Ev }, 0 },
3469     { "tzcntS", { Gv, Ev }, 0 },
3470     { "bsfS",   { Gv, Ev }, 0 },
3471   },
3472
3473   /* PREFIX_0FBD */
3474   {
3475     { "bsrS",   { Gv, Ev }, 0 },
3476     { "lzcntS", { Gv, Ev }, 0 },
3477     { "bsrS",   { Gv, Ev }, 0 },
3478   },
3479
3480   /* PREFIX_0FC2 */
3481   {
3482     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3483     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3484     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3485     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3486   },
3487
3488   /* PREFIX_0FC7_REG_6_MOD_0 */
3489   {
3490     { "vmptrld",{ Mq }, 0 },
3491     { "vmxon",  { Mq }, 0 },
3492     { "vmclear",{ Mq }, 0 },
3493   },
3494
3495   /* PREFIX_0FC7_REG_6_MOD_3 */
3496   {
3497     { "rdrand", { Ev }, 0 },
3498     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3499     { "rdrand", { Ev }, 0 }
3500   },
3501
3502   /* PREFIX_0FC7_REG_7_MOD_3 */
3503   {
3504     { "rdseed", { Ev }, 0 },
3505     { "rdpid",  { Em }, 0 },
3506     { "rdseed", { Ev }, 0 },
3507   },
3508
3509   /* PREFIX_0FD0 */
3510   {
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { "addsubpd", { XM, EXx }, 0 },
3514     { "addsubps", { XM, EXx }, 0 },
3515   },
3516
3517   /* PREFIX_0FD6 */
3518   {
3519     { Bad_Opcode },
3520     { "movq2dq",{ XM, MS }, 0 },
3521     { "movq",   { EXqS, XM }, 0 },
3522     { "movdq2q",{ MX, XS }, 0 },
3523   },
3524
3525   /* PREFIX_0FE6 */
3526   {
3527     { Bad_Opcode },
3528     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3529     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3530     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3531   },
3532
3533   /* PREFIX_0FE7 */
3534   {
3535     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3536     { Bad_Opcode },
3537     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3538   },
3539
3540   /* PREFIX_0FF0 */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3546   },
3547
3548   /* PREFIX_0FF7 */
3549   {
3550     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3551     { Bad_Opcode },
3552     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3553   },
3554
3555   /* PREFIX_0F38D8 */
3556   {
3557     { Bad_Opcode },
3558     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3559   },
3560
3561   /* PREFIX_0F38DC */
3562   {
3563     { Bad_Opcode },
3564     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3565     { "aesenc", { XM, EXx }, 0 },
3566   },
3567
3568   /* PREFIX_0F38DD */
3569   {
3570     { Bad_Opcode },
3571     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3572     { "aesenclast", { XM, EXx }, 0 },
3573   },
3574
3575   /* PREFIX_0F38DE */
3576   {
3577     { Bad_Opcode },
3578     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3579     { "aesdec", { XM, EXx }, 0 },
3580   },
3581
3582   /* PREFIX_0F38DF */
3583   {
3584     { Bad_Opcode },
3585     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3586     { "aesdeclast", { XM, EXx }, 0 },
3587   },
3588
3589   /* PREFIX_0F38F0 */
3590   {
3591     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3592     { Bad_Opcode },
3593     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3594     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3595   },
3596
3597   /* PREFIX_0F38F1 */
3598   {
3599     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3600     { Bad_Opcode },
3601     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3602     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3603   },
3604
3605   /* PREFIX_0F38F6 */
3606   {
3607     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3608     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3609     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3610     { Bad_Opcode },
3611   },
3612
3613   /* PREFIX_0F38F8 */
3614   {
3615     { Bad_Opcode },
3616     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3617     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3618     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3619   },
3620   /* PREFIX_0F38FA */
3621   {
3622     { Bad_Opcode },
3623     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3624   },
3625
3626   /* PREFIX_0F38FB */
3627   {
3628     { Bad_Opcode },
3629     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3630   },
3631
3632   /* PREFIX_0F38FC */
3633   {
3634     { "aadd",   { Mdq, Gdq }, 0 },
3635     { "axor",   { Mdq, Gdq }, 0 },
3636     { "aand",   { Mdq, Gdq }, 0 },
3637     { "aor",    { Mdq, Gdq }, 0 },
3638   },
3639
3640   /* PREFIX_0F3A0F */
3641   {
3642     { Bad_Opcode },
3643     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3644   },
3645
3646   /* PREFIX_VEX_0F10 */
3647   {
3648     { "%XEvmovupX",     { XM, EXEvexXNoBcst }, 0 },
3649     { "%XEvmovs%XS",    { XMScalar, VexScalarR, EXd }, 0 },
3650     { "%XEvmovupX",     { XM, EXEvexXNoBcst }, 0 },
3651     { "%XEvmovs%XD",    { XMScalar, VexScalarR, EXq }, 0 },
3652   },
3653
3654   /* PREFIX_VEX_0F11 */
3655   {
3656     { "%XEvmovupX",     { EXxS, XM }, 0 },
3657     { "%XEvmovs%XS",    { EXdS, VexScalarR, XMScalar }, 0 },
3658     { "%XEvmovupX",     { EXxS, XM }, 0 },
3659     { "%XEvmovs%XD",    { EXqS, VexScalarR, XMScalar }, 0 },
3660   },
3661
3662   /* PREFIX_VEX_0F12 */
3663   {
3664     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3665     { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3666     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3667     { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3668   },
3669
3670   /* PREFIX_VEX_0F16 */
3671   {
3672     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3673     { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3674     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3675   },
3676
3677   /* PREFIX_VEX_0F2A */
3678   {
3679     { Bad_Opcode },
3680     { "%XEvcvtsi2ss{%LQ|}",     { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3681     { Bad_Opcode },
3682     { "%XEvcvtsi2sd{%LQ|}",     { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3683   },
3684
3685   /* PREFIX_VEX_0F2C */
3686   {
3687     { Bad_Opcode },
3688     { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3689     { Bad_Opcode },
3690     { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3691   },
3692
3693   /* PREFIX_VEX_0F2D */
3694   {
3695     { Bad_Opcode },
3696     { "%XEvcvtss2si",   { Gdq, EXd, EXxEVexR }, 0 },
3697     { Bad_Opcode },
3698     { "%XEvcvtsd2si",   { Gdq, EXq, EXxEVexR }, 0 },
3699   },
3700
3701   /* PREFIX_VEX_0F2E */
3702   {
3703     { "%XEvucomisX",    { XMScalar, EXd, EXxEVexS }, 0 },
3704     { Bad_Opcode },
3705     { "%XEvucomisX",    { XMScalar, EXq, EXxEVexS }, 0 },
3706   },
3707
3708   /* PREFIX_VEX_0F2F */
3709   {
3710     { "%XEvcomisX",     { XMScalar, EXd, EXxEVexS }, 0 },
3711     { Bad_Opcode },
3712     { "%XEvcomisX",     { XMScalar, EXq, EXxEVexS }, 0 },
3713   },
3714
3715   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3716   {
3717     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3718     { Bad_Opcode },
3719     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3720   },
3721
3722   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3723   {
3724     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3725     { Bad_Opcode },
3726     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3727   },
3728
3729   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3730   {
3731     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3732     { Bad_Opcode },
3733     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3734   },
3735
3736   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3737   {
3738     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3739     { Bad_Opcode },
3740     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3741   },
3742
3743   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3744   {
3745     { "knotw",          { MaskG, MaskE }, 0 },
3746     { Bad_Opcode },
3747     { "knotb",          { MaskG, MaskE }, 0 },
3748   },
3749
3750   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3751   {
3752     { "knotq",          { MaskG, MaskE }, 0 },
3753     { Bad_Opcode },
3754     { "knotd",          { MaskG, MaskE }, 0 },
3755   },
3756
3757   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3758   {
3759     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3760     { Bad_Opcode },
3761     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3762   },
3763
3764   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3765   {
3766     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3767     { Bad_Opcode },
3768     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3769   },
3770
3771   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3772   {
3773     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3774     { Bad_Opcode },
3775     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3776   },
3777
3778   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3779   {
3780     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3781     { Bad_Opcode },
3782     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3783   },
3784
3785   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3786   {
3787     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3788     { Bad_Opcode },
3789     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3790   },
3791
3792   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3793   {
3794     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3795     { Bad_Opcode },
3796     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3797   },
3798
3799   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3800   {
3801     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3802     { Bad_Opcode },
3803     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3804   },
3805
3806   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3807   {
3808     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3809     { Bad_Opcode },
3810     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3811   },
3812
3813   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3814   {
3815     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3816     { Bad_Opcode },
3817     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3818   },
3819
3820   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3821   {
3822     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3823   },
3824
3825   /* PREFIX_VEX_0F51 */
3826   {
3827     { "%XEvsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3828     { "%XEvsqrts%XS",   { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3829     { "%XEvsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3830     { "%XEvsqrts%XD",   { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3831   },
3832
3833   /* PREFIX_VEX_0F52 */
3834   {
3835     { "vrsqrtps",       { XM, EXx }, 0 },
3836     { "vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3837   },
3838
3839   /* PREFIX_VEX_0F53 */
3840   {
3841     { "vrcpps",         { XM, EXx }, 0 },
3842     { "vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3843   },
3844
3845   /* PREFIX_VEX_0F58 */
3846   {
3847     { "%XEvaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3848     { "%XEvadds%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3849     { "%XEvaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3850     { "%XEvadds%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3851   },
3852
3853   /* PREFIX_VEX_0F59 */
3854   {
3855     { "%XEvmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3856     { "%XEvmuls%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3857     { "%XEvmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3858     { "%XEvmuls%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3859   },
3860
3861   /* PREFIX_VEX_0F5A */
3862   {
3863     { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3864     { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3865     { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3866     { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3867   },
3868
3869   /* PREFIX_VEX_0F5B */
3870   {
3871     { "vcvtdq2ps",      { XM, EXx }, 0 },
3872     { "vcvttps2dq",     { XM, EXx }, 0 },
3873     { "vcvtps2dq",      { XM, EXx }, 0 },
3874   },
3875
3876   /* PREFIX_VEX_0F5C */
3877   {
3878     { "%XEvsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3879     { "%XEvsubs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3880     { "%XEvsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3881     { "%XEvsubs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3882   },
3883
3884   /* PREFIX_VEX_0F5D */
3885   {
3886     { "%XEvminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3887     { "%XEvmins%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3888     { "%XEvminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3889     { "%XEvmins%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3890   },
3891
3892   /* PREFIX_VEX_0F5E */
3893   {
3894     { "%XEvdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3895     { "%XEvdivs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3896     { "%XEvdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3897     { "%XEvdivs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3898   },
3899
3900   /* PREFIX_VEX_0F5F */
3901   {
3902     { "%XEvmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3903     { "%XEvmaxs%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3904     { "%XEvmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3905     { "%XEvmaxs%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3906   },
3907
3908   /* PREFIX_VEX_0F6F */
3909   {
3910     { Bad_Opcode },
3911     { "vmovdqu",        { XM, EXx }, 0 },
3912     { "vmovdqa",        { XM, EXx }, 0 },
3913   },
3914
3915   /* PREFIX_VEX_0F70 */
3916   {
3917     { Bad_Opcode },
3918     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3919     { "vpshufd",        { XM, EXx, Ib }, 0 },
3920     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3921   },
3922
3923   /* PREFIX_VEX_0F7C */
3924   {
3925     { Bad_Opcode },
3926     { Bad_Opcode },
3927     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3928     { "vhaddps",        { XM, Vex, EXx }, 0 },
3929   },
3930
3931   /* PREFIX_VEX_0F7D */
3932   {
3933     { Bad_Opcode },
3934     { Bad_Opcode },
3935     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3936     { "vhsubps",        { XM, Vex, EXx }, 0 },
3937   },
3938
3939   /* PREFIX_VEX_0F7E */
3940   {
3941     { Bad_Opcode },
3942     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3943     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3944   },
3945
3946   /* PREFIX_VEX_0F7F */
3947   {
3948     { Bad_Opcode },
3949     { "vmovdqu",        { EXxS, XM }, 0 },
3950     { "vmovdqa",        { EXxS, XM }, 0 },
3951   },
3952
3953   /* PREFIX_VEX_0F90_L_0_W_0 */
3954   {
3955     { "kmovw",          { MaskG, MaskE }, 0 },
3956     { Bad_Opcode },
3957     { "kmovb",          { MaskG, MaskBDE }, 0 },
3958   },
3959
3960   /* PREFIX_VEX_0F90_L_0_W_1 */
3961   {
3962     { "kmovq",          { MaskG, MaskE }, 0 },
3963     { Bad_Opcode },
3964     { "kmovd",          { MaskG, MaskBDE }, 0 },
3965   },
3966
3967   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3968   {
3969     { "kmovw",          { Ew, MaskG }, 0 },
3970     { Bad_Opcode },
3971     { "kmovb",          { Eb, MaskG }, 0 },
3972   },
3973
3974   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3975   {
3976     { "kmovq",          { Eq, MaskG }, 0 },
3977     { Bad_Opcode },
3978     { "kmovd",          { Ed, MaskG }, 0 },
3979   },
3980
3981   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3982   {
3983     { "kmovw",          { MaskG, Edq }, 0 },
3984     { Bad_Opcode },
3985     { "kmovb",          { MaskG, Edq }, 0 },
3986     { "kmovd",          { MaskG, Edq }, 0 },
3987   },
3988
3989   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3990   {
3991     { Bad_Opcode },
3992     { Bad_Opcode },
3993     { Bad_Opcode },
3994     { "kmovK",          { MaskG, Edq }, 0 },
3995   },
3996
3997   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3998   {
3999     { "kmovw",          { Gdq, MaskE }, 0 },
4000     { Bad_Opcode },
4001     { "kmovb",          { Gdq, MaskE }, 0 },
4002     { "kmovd",          { Gdq, MaskE }, 0 },
4003   },
4004
4005   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4006   {
4007     { Bad_Opcode },
4008     { Bad_Opcode },
4009     { Bad_Opcode },
4010     { "kmovK",          { Gdq, MaskE }, 0 },
4011   },
4012
4013   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4014   {
4015     { "kortestw", { MaskG, MaskE }, 0 },
4016     { Bad_Opcode },
4017     { "kortestb", { MaskG, MaskE }, 0 },
4018   },
4019
4020   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4021   {
4022     { "kortestq", { MaskG, MaskE }, 0 },
4023     { Bad_Opcode },
4024     { "kortestd", { MaskG, MaskE }, 0 },
4025   },
4026
4027   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4028   {
4029     { "ktestw", { MaskG, MaskE }, 0 },
4030     { Bad_Opcode },
4031     { "ktestb", { MaskG, MaskE }, 0 },
4032   },
4033
4034   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4035   {
4036     { "ktestq", { MaskG, MaskE }, 0 },
4037     { Bad_Opcode },
4038     { "ktestd", { MaskG, MaskE }, 0 },
4039   },
4040
4041   /* PREFIX_VEX_0FC2 */
4042   {
4043     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4044     { "vcmpss",         { XMScalar, VexScalar, EXd, CMP }, 0 },
4045     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4046     { "vcmpsd",         { XMScalar, VexScalar, EXq, CMP }, 0 },
4047   },
4048
4049   /* PREFIX_VEX_0FD0 */
4050   {
4051     { Bad_Opcode },
4052     { Bad_Opcode },
4053     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4054     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4055   },
4056
4057   /* PREFIX_VEX_0FE6 */
4058   {
4059     { Bad_Opcode },
4060     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4061     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4062     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4063   },
4064
4065   /* PREFIX_VEX_0FF0 */
4066   {
4067     { Bad_Opcode },
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4071   },
4072
4073   /* PREFIX_VEX_0F3849_X86_64 */
4074   {
4075     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4076     { Bad_Opcode },
4077     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4078     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4079   },
4080
4081   /* PREFIX_VEX_0F384B_X86_64 */
4082   {
4083     { Bad_Opcode },
4084     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4085     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4086     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4087   },
4088
4089   /* PREFIX_VEX_0F3850_W_0 */
4090   {
4091     { "vpdpbuud",       { XM, Vex, EXx }, 0 },
4092     { "vpdpbsud",       { XM, Vex, EXx }, 0 },
4093     { "%XVvpdpbusd",    { XM, Vex, EXx }, 0 },
4094     { "vpdpbssd",       { XM, Vex, EXx }, 0 },
4095   },
4096
4097   /* PREFIX_VEX_0F3851_W_0 */
4098   {
4099     { "vpdpbuuds",      { XM, Vex, EXx }, 0 },
4100     { "vpdpbsuds",      { XM, Vex, EXx }, 0 },
4101     { "%XVvpdpbusds",   { XM, Vex, EXx }, 0 },
4102     { "vpdpbssds",      { XM, Vex, EXx }, 0 },
4103   },
4104   /* PREFIX_VEX_0F385C_X86_64 */
4105   {
4106     { Bad_Opcode },
4107     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4108     { Bad_Opcode },
4109     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_3) },
4110   },
4111
4112   /* PREFIX_VEX_0F385E_X86_64 */
4113   {
4114     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4115     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4116     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4117     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4118   },
4119
4120   /* PREFIX_VEX_0F3872 */
4121   {
4122     { Bad_Opcode },
4123     { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4124   },
4125
4126   /* PREFIX_VEX_0F38B0_W_0 */
4127   {
4128     { "vcvtneoph2ps", { XM, Mx }, 0 },
4129     { "vcvtneebf162ps", { XM, Mx }, 0 },
4130     { "vcvtneeph2ps", { XM, Mx }, 0 },
4131     { "vcvtneobf162ps", { XM, Mx }, 0 },
4132   },
4133
4134   /* PREFIX_VEX_0F38B1_W_0 */
4135   {
4136     { Bad_Opcode },
4137     { "vbcstnebf162ps", { XM, Mw }, 0 },
4138     { "vbcstnesh2ps", { XM, Mw }, 0 },
4139   },
4140
4141   /* PREFIX_VEX_0F38F5_L_0 */
4142   {
4143     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4144     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4145     { Bad_Opcode },
4146     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4147   },
4148
4149   /* PREFIX_VEX_0F38F6_L_0 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4155   },
4156
4157   /* PREFIX_VEX_0F38F7_L_0 */
4158   {
4159     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4160     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4161     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4162     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4163   },
4164
4165   /* PREFIX_VEX_0F3AF0_L_0 */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4171   },
4172
4173 #include "i386-dis-evex-prefix.h"
4174 };
4175
4176 static const struct dis386 x86_64_table[][2] = {
4177   /* X86_64_06 */
4178   {
4179     { "pushP", { es }, 0 },
4180   },
4181
4182   /* X86_64_07 */
4183   {
4184     { "popP", { es }, 0 },
4185   },
4186
4187   /* X86_64_0E */
4188   {
4189     { "pushP", { cs }, 0 },
4190   },
4191
4192   /* X86_64_16 */
4193   {
4194     { "pushP", { ss }, 0 },
4195   },
4196
4197   /* X86_64_17 */
4198   {
4199     { "popP", { ss }, 0 },
4200   },
4201
4202   /* X86_64_1E */
4203   {
4204     { "pushP", { ds }, 0 },
4205   },
4206
4207   /* X86_64_1F */
4208   {
4209     { "popP", { ds }, 0 },
4210   },
4211
4212   /* X86_64_27 */
4213   {
4214     { "daa", { XX }, 0 },
4215   },
4216
4217   /* X86_64_2F */
4218   {
4219     { "das", { XX }, 0 },
4220   },
4221
4222   /* X86_64_37 */
4223   {
4224     { "aaa", { XX }, 0 },
4225   },
4226
4227   /* X86_64_3F */
4228   {
4229     { "aas", { XX }, 0 },
4230   },
4231
4232   /* X86_64_60 */
4233   {
4234     { "pushaP", { XX }, 0 },
4235   },
4236
4237   /* X86_64_61 */
4238   {
4239     { "popaP", { XX }, 0 },
4240   },
4241
4242   /* X86_64_62 */
4243   {
4244     { MOD_TABLE (MOD_62_32BIT) },
4245     { EVEX_TABLE (EVEX_0F) },
4246   },
4247
4248   /* X86_64_63 */
4249   {
4250     { "arpl", { Ew, Gw }, 0 },
4251     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4252   },
4253
4254   /* X86_64_6D */
4255   {
4256     { "ins{R|}", { Yzr, indirDX }, 0 },
4257     { "ins{G|}", { Yzr, indirDX }, 0 },
4258   },
4259
4260   /* X86_64_6F */
4261   {
4262     { "outs{R|}", { indirDXr, Xz }, 0 },
4263     { "outs{G|}", { indirDXr, Xz }, 0 },
4264   },
4265
4266   /* X86_64_82 */
4267   {
4268     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4269     { REG_TABLE (REG_80) },
4270   },
4271
4272   /* X86_64_9A */
4273   {
4274     { "{l|}call{P|}", { Ap }, 0 },
4275   },
4276
4277   /* X86_64_C2 */
4278   {
4279     { "retP",           { Iw, BND }, 0 },
4280     { "ret@",           { Iw, BND }, 0 },
4281   },
4282
4283   /* X86_64_C3 */
4284   {
4285     { "retP",           { BND }, 0 },
4286     { "ret@",           { BND }, 0 },
4287   },
4288
4289   /* X86_64_C4 */
4290   {
4291     { MOD_TABLE (MOD_C4_32BIT) },
4292     { VEX_C4_TABLE (VEX_0F) },
4293   },
4294
4295   /* X86_64_C5 */
4296   {
4297     { MOD_TABLE (MOD_C5_32BIT) },
4298     { VEX_C5_TABLE (VEX_0F) },
4299   },
4300
4301   /* X86_64_CE */
4302   {
4303     { "into", { XX }, 0 },
4304   },
4305
4306   /* X86_64_D4 */
4307   {
4308     { "aam", { Ib }, 0 },
4309   },
4310
4311   /* X86_64_D5 */
4312   {
4313     { "aad", { Ib }, 0 },
4314   },
4315
4316   /* X86_64_E8 */
4317   {
4318     { "callP",          { Jv, BND }, 0 },
4319     { "call@",          { Jv, BND }, 0 }
4320   },
4321
4322   /* X86_64_E9 */
4323   {
4324     { "jmpP",           { Jv, BND }, 0 },
4325     { "jmp@",           { Jv, BND }, 0 }
4326   },
4327
4328   /* X86_64_EA */
4329   {
4330     { "{l|}jmp{P|}", { Ap }, 0 },
4331   },
4332
4333   /* X86_64_0F01_REG_0 */
4334   {
4335     { "sgdt{Q|Q}", { M }, 0 },
4336     { "sgdt", { M }, 0 },
4337   },
4338
4339   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4340   {
4341     { Bad_Opcode },
4342     { "wrmsrlist",      { Skip_MODRM }, 0 },
4343   },
4344
4345   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4346   {
4347     { Bad_Opcode },
4348     { "rdmsrlist",      { Skip_MODRM }, 0 },
4349   },
4350
4351   /* X86_64_0F01_REG_1 */
4352   {
4353     { "sidt{Q|Q}", { M }, 0 },
4354     { "sidt", { M }, 0 },
4355   },
4356
4357   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4358   {
4359     { Bad_Opcode },
4360     { "seamret",        { Skip_MODRM }, 0 },
4361   },
4362
4363   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4364   {
4365     { Bad_Opcode },
4366     { "seamops",        { Skip_MODRM }, 0 },
4367   },
4368
4369   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4370   {
4371     { Bad_Opcode },
4372     { "seamcall",       { Skip_MODRM }, 0 },
4373   },
4374
4375   /* X86_64_0F01_REG_2 */
4376   {
4377     { "lgdt{Q|Q}", { M }, 0 },
4378     { "lgdt", { M }, 0 },
4379   },
4380
4381   /* X86_64_0F01_REG_3 */
4382   {
4383     { "lidt{Q|Q}", { M }, 0 },
4384     { "lidt", { M }, 0 },
4385   },
4386
4387   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4388   {
4389     { Bad_Opcode },
4390     { "uiret",  { Skip_MODRM }, 0 },
4391   },
4392
4393   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4394   {
4395     { Bad_Opcode },
4396     { "testui", { Skip_MODRM }, 0 },
4397   },
4398
4399   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4400   {
4401     { Bad_Opcode },
4402     { "clui",   { Skip_MODRM }, 0 },
4403   },
4404
4405   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4406   {
4407     { Bad_Opcode },
4408     { "stui",   { Skip_MODRM }, 0 },
4409   },
4410
4411   /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4412   {
4413     { Bad_Opcode },
4414     { "rmpquery", { Skip_MODRM }, 0 },
4415   },
4416
4417   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4418   {
4419     { Bad_Opcode },
4420     { "rmpadjust",      { Skip_MODRM }, 0 },
4421   },
4422
4423   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4424   {
4425     { Bad_Opcode },
4426     { "rmpupdate",      { Skip_MODRM }, 0 },
4427   },
4428
4429   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4430   {
4431     { Bad_Opcode },
4432     { "psmash", { Skip_MODRM }, 0 },
4433   },
4434
4435   /* X86_64_0F18_REG_6_MOD_0 */
4436   {
4437     { "nopQ",           { Ev }, 0 },
4438     { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4439   },
4440
4441   /* X86_64_0F18_REG_7_MOD_0 */
4442   {
4443     { "nopQ",           { Ev }, 0 },
4444     { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4445   },
4446
4447   {
4448     /* X86_64_0F24 */
4449     { "movZ",           { Em, Td }, 0 },
4450   },
4451
4452   {
4453     /* X86_64_0F26 */
4454     { "movZ",           { Td, Em }, 0 },
4455   },
4456
4457   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4458   {
4459     { Bad_Opcode },
4460     { "senduipi",       { Eq }, 0 },
4461   },
4462
4463   /* X86_64_VEX_0F3849 */
4464   {
4465     { Bad_Opcode },
4466     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4467   },
4468
4469   /* X86_64_VEX_0F384B */
4470   {
4471     { Bad_Opcode },
4472     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4473   },
4474
4475   /* X86_64_VEX_0F385C */
4476   {
4477     { Bad_Opcode },
4478     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4479   },
4480
4481   /* X86_64_VEX_0F385E */
4482   {
4483     { Bad_Opcode },
4484     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4485   },
4486
4487   /* X86_64_VEX_0F38E0 */
4488   {
4489     { Bad_Opcode },
4490     { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4491   },
4492
4493   /* X86_64_VEX_0F38E1 */
4494   {
4495     { Bad_Opcode },
4496     { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4497   },
4498
4499   /* X86_64_VEX_0F38E2 */
4500   {
4501     { Bad_Opcode },
4502     { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4503   },
4504
4505   /* X86_64_VEX_0F38E3 */
4506   {
4507     { Bad_Opcode },
4508     { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4509   },
4510
4511   /* X86_64_VEX_0F38E4 */
4512   {
4513     { Bad_Opcode },
4514     { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4515   },
4516
4517   /* X86_64_VEX_0F38E5 */
4518   {
4519     { Bad_Opcode },
4520     { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4521   },
4522
4523   /* X86_64_VEX_0F38E6 */
4524   {
4525     { Bad_Opcode },
4526     { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4527   },
4528
4529   /* X86_64_VEX_0F38E7 */
4530   {
4531     { Bad_Opcode },
4532     { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4533   },
4534
4535   /* X86_64_VEX_0F38E8 */
4536   {
4537     { Bad_Opcode },
4538     { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4539   },
4540
4541   /* X86_64_VEX_0F38E9 */
4542   {
4543     { Bad_Opcode },
4544     { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4545   },
4546
4547   /* X86_64_VEX_0F38EA */
4548   {
4549     { Bad_Opcode },
4550     { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4551   },
4552
4553   /* X86_64_VEX_0F38EB */
4554   {
4555     { Bad_Opcode },
4556     { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4557   },
4558
4559   /* X86_64_VEX_0F38EC */
4560   {
4561     { Bad_Opcode },
4562     { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4563   },
4564
4565   /* X86_64_VEX_0F38ED */
4566   {
4567     { Bad_Opcode },
4568     { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4569   },
4570
4571   /* X86_64_VEX_0F38EE */
4572   {
4573     { Bad_Opcode },
4574     { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4575   },
4576
4577   /* X86_64_VEX_0F38EF */
4578   {
4579     { Bad_Opcode },
4580     { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4581   },
4582 };
4583
4584 static const struct dis386 three_byte_table[][256] = {
4585
4586   /* THREE_BYTE_0F38 */
4587   {
4588     /* 00 */
4589     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4590     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4591     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4592     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4593     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4594     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4595     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4596     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4597     /* 08 */
4598     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4599     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4600     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4601     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     /* 10 */
4607     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4612     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4613     { Bad_Opcode },
4614     { "ptest",  { XM, EXx }, PREFIX_DATA },
4615     /* 18 */
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4621     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4622     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4623     { Bad_Opcode },
4624     /* 20 */
4625     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4626     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4627     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4628     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4629     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4630     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     /* 28 */
4634     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4635     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4636     { MOD_TABLE (MOD_0F382A) },
4637     { "packusdw", { XM, EXx }, PREFIX_DATA },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     /* 30 */
4643     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4644     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4645     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4646     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4647     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4648     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4649     { Bad_Opcode },
4650     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4651     /* 38 */
4652     { "pminsb", { XM, EXx }, PREFIX_DATA },
4653     { "pminsd", { XM, EXx }, PREFIX_DATA },
4654     { "pminuw", { XM, EXx }, PREFIX_DATA },
4655     { "pminud", { XM, EXx }, PREFIX_DATA },
4656     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4657     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4658     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4659     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4660     /* 40 */
4661     { "pmulld", { XM, EXx }, PREFIX_DATA },
4662     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     /* 48 */
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     /* 50 */
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     /* 58 */
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     /* 60 */
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     /* 68 */
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     /* 70 */
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     /* 78 */
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     /* 80 */
4733     { "invept", { Gm, Mo }, PREFIX_DATA },
4734     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4735     { "invpcid", { Gm, M }, PREFIX_DATA },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     /* 88 */
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     /* 90 */
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     /* 98 */
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     /* a0 */
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     /* a8 */
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     /* b0 */
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     /* b8 */
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     /* c0 */
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     /* c8 */
4814     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4815     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4816     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4817     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4818     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4819     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4820     { Bad_Opcode },
4821     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4822     /* d0 */
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     /* d8 */
4832     { PREFIX_TABLE (PREFIX_0F38D8) },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { "aesimc", { XM, EXx }, PREFIX_DATA },
4836     { PREFIX_TABLE (PREFIX_0F38DC) },
4837     { PREFIX_TABLE (PREFIX_0F38DD) },
4838     { PREFIX_TABLE (PREFIX_0F38DE) },
4839     { PREFIX_TABLE (PREFIX_0F38DF) },
4840     /* e0 */
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     /* e8 */
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     /* f0 */
4859     { PREFIX_TABLE (PREFIX_0F38F0) },
4860     { PREFIX_TABLE (PREFIX_0F38F1) },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { MOD_TABLE (MOD_0F38F5) },
4865     { PREFIX_TABLE (PREFIX_0F38F6) },
4866     { Bad_Opcode },
4867     /* f8 */
4868     { PREFIX_TABLE (PREFIX_0F38F8) },
4869     { MOD_TABLE (MOD_0F38F9) },
4870     { PREFIX_TABLE (PREFIX_0F38FA) },
4871     { PREFIX_TABLE (PREFIX_0F38FB) },
4872     { PREFIX_TABLE (PREFIX_0F38FC) },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876   },
4877   /* THREE_BYTE_0F3A */
4878   {
4879     /* 00 */
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     /* 08 */
4889     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4890     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4891     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4892     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4893     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4894     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4895     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4896     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4897     /* 10 */
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4903     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4904     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4905     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4906     /* 18 */
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     /* 20 */
4916     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4917     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4918     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     /* 28 */
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     /* 30 */
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     /* 38 */
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     /* 40 */
4952     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4953     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4954     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4955     { Bad_Opcode },
4956     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     /* 48 */
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     /* 50 */
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     /* 58 */
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     /* 60 */
4988     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4989     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4990     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4991     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     /* 68 */
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     /* 70 */
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     /* 78 */
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     /* 80 */
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     /* 88 */
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     /* 90 */
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     /* 98 */
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     /* a0 */
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     /* a8 */
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     /* b0 */
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     /* b8 */
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     /* c0 */
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     /* c8 */
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5110     { Bad_Opcode },
5111     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5112     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5113     /* d0 */
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     /* d8 */
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5131     /* e0 */
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     /* e8 */
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     /* f0 */
5150     { PREFIX_TABLE (PREFIX_0F3A0F) },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     /* f8 */
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167   },
5168 };
5169
5170 static const struct dis386 xop_table[][256] = {
5171   /* XOP_08 */
5172   {
5173     /* 00 */
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     /* 08 */
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     /* 10 */
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     /* 18 */
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     /* 20 */
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     /* 28 */
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     /* 30 */
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     /* 38 */
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     /* 40 */
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     /* 48 */
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     /* 50 */
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     /* 58 */
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     /* 60 */
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     /* 68 */
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     /* 70 */
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     /* 78 */
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     /* 80 */
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5324     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5325     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5326     /* 88 */
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5334     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5335     /* 90 */
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5342     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5343     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5344     /* 98 */
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5352     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5353     /* a0 */
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5357     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5361     { Bad_Opcode },
5362     /* a8 */
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     /* b0 */
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5379     { Bad_Opcode },
5380     /* b8 */
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     /* c0 */
5390     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5391     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5392     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5393     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     /* c8 */
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5404     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5405     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5406     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5407     /* d0 */
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     /* d8 */
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     /* e0 */
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     /* e8 */
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5440     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5441     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5442     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5443     /* f0 */
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     /* f8 */
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461   },
5462   /* XOP_09 */
5463   {
5464     /* 00 */
5465     { Bad_Opcode },
5466     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5467     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     /* 08 */
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     /* 10 */
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { MOD_TABLE (MOD_XOP_09_12) },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     /* 18 */
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     /* 20 */
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     /* 28 */
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     /* 30 */
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     /* 38 */
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     /* 40 */
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     /* 48 */
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     /* 50 */
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     /* 58 */
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     /* 60 */
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     /* 68 */
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     /* 70 */
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     /* 78 */
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     /* 80 */
5609     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5610     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5611     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5612     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     /* 88 */
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     /* 90 */
5627     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5628     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5629     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5630     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5631     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5632     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5633     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5634     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5635     /* 98 */
5636     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5637     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5638     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5639     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     /* a0 */
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     /* a8 */
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     /* b0 */
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     /* b8 */
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     /* c0 */
5681     { Bad_Opcode },
5682     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5683     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5684     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5688     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5689     /* c8 */
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     /* d0 */
5699     { Bad_Opcode },
5700     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5701     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5702     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5706     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5707     /* d8 */
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     /* e0 */
5717     { Bad_Opcode },
5718     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5719     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5720     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     /* e8 */
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     /* f0 */
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     /* f8 */
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752   },
5753   /* XOP_0A */
5754   {
5755     /* 00 */
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     /* 08 */
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     /* 10 */
5774     { "bextrS", { Gdq, Edq, Id }, 0 },
5775     { Bad_Opcode },
5776     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     /* 18 */
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     /* 20 */
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     /* 28 */
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     /* 30 */
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     /* 38 */
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     /* 40 */
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     /* 48 */
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     /* 50 */
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     /* 58 */
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     /* 60 */
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     /* 68 */
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     /* 70 */
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     /* 78 */
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     /* 80 */
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     /* 88 */
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     /* 90 */
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     /* 98 */
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     /* a0 */
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     /* a8 */
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     /* b0 */
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     /* b8 */
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     /* c0 */
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     /* c8 */
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     /* d0 */
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     /* d8 */
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     /* e0 */
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     /* e8 */
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     /* f0 */
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     /* f8 */
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043   },
6044 };
6045
6046 static const struct dis386 vex_table[][256] = {
6047   /* VEX_0F */
6048   {
6049     /* 00 */
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     /* 08 */
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     /* 10 */
6068     { PREFIX_TABLE (PREFIX_VEX_0F10) },
6069     { PREFIX_TABLE (PREFIX_VEX_0F11) },
6070     { PREFIX_TABLE (PREFIX_VEX_0F12) },
6071     { MOD_TABLE (MOD_VEX_0F13) },
6072     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6073     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6074     { PREFIX_TABLE (PREFIX_VEX_0F16) },
6075     { MOD_TABLE (MOD_VEX_0F17) },
6076     /* 18 */
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     /* 20 */
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     /* 28 */
6095     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
6096     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
6097     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6098     { MOD_TABLE (MOD_VEX_0F2B) },
6099     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6100     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6101     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
6102     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
6103     /* 30 */
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     /* 38 */
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     /* 40 */
6122     { Bad_Opcode },
6123     { VEX_LEN_TABLE (VEX_LEN_0F41) },
6124     { VEX_LEN_TABLE (VEX_LEN_0F42) },
6125     { Bad_Opcode },
6126     { VEX_LEN_TABLE (VEX_LEN_0F44) },
6127     { VEX_LEN_TABLE (VEX_LEN_0F45) },
6128     { VEX_LEN_TABLE (VEX_LEN_0F46) },
6129     { VEX_LEN_TABLE (VEX_LEN_0F47) },
6130     /* 48 */
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6134     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     /* 50 */
6140     { MOD_TABLE (MOD_VEX_0F50) },
6141     { PREFIX_TABLE (PREFIX_VEX_0F51) },
6142     { PREFIX_TABLE (PREFIX_VEX_0F52) },
6143     { PREFIX_TABLE (PREFIX_VEX_0F53) },
6144     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6145     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
6146     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
6147     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6148     /* 58 */
6149     { PREFIX_TABLE (PREFIX_VEX_0F58) },
6150     { PREFIX_TABLE (PREFIX_VEX_0F59) },
6151     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
6152     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
6153     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
6154     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6155     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6156     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6157     /* 60 */
6158     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
6159     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
6160     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
6161     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
6162     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
6163     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
6164     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
6165     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
6166     /* 68 */
6167     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
6168     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6169     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6170     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6171     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6172     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6173     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6174     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6175     /* 70 */
6176     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6177     { MOD_TABLE (MOD_VEX_0F71) },
6178     { MOD_TABLE (MOD_VEX_0F72) },
6179     { MOD_TABLE (MOD_VEX_0F73) },
6180     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6181     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6182     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6183     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6184     /* 78 */
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6190     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6191     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6192     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6193     /* 80 */
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     /* 88 */
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     /* 90 */
6212     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6213     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6214     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6215     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     /* 98 */
6221     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6222     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     /* a0 */
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     /* a8 */
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { REG_TABLE (REG_VEX_0FAE) },
6246     { Bad_Opcode },
6247     /* b0 */
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     /* b8 */
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     /* c0 */
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6269     { Bad_Opcode },
6270     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6271     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6272     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6273     { Bad_Opcode },
6274     /* c8 */
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     /* d0 */
6284     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6285     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6286     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6287     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6288     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6289     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6290     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6291     { MOD_TABLE (MOD_VEX_0FD7) },
6292     /* d8 */
6293     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6294     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6295     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6296     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6297     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6298     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6299     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6300     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6301     /* e0 */
6302     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6303     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6304     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6305     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6306     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6307     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6308     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6309     { MOD_TABLE (MOD_VEX_0FE7) },
6310     /* e8 */
6311     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6312     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6313     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6314     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6315     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6316     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6317     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6318     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6319     /* f0 */
6320     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6321     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6322     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6323     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6324     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6325     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6326     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6327     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6328     /* f8 */
6329     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6330     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6331     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6332     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6333     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6334     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6335     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6336     { Bad_Opcode },
6337   },
6338   /* VEX_0F38 */
6339   {
6340     /* 00 */
6341     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6342     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6343     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6345     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6347     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6348     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6349     /* 08 */
6350     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6351     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6352     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6353     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6354     { VEX_W_TABLE (VEX_W_0F380C) },
6355     { VEX_W_TABLE (VEX_W_0F380D) },
6356     { VEX_W_TABLE (VEX_W_0F380E) },
6357     { VEX_W_TABLE (VEX_W_0F380F) },
6358     /* 10 */
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { VEX_W_TABLE (VEX_W_0F3813) },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6366     { "vptest",         { XM, EXx }, PREFIX_DATA },
6367     /* 18 */
6368     { VEX_W_TABLE (VEX_W_0F3818) },
6369     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6370     { MOD_TABLE (MOD_VEX_0F381A) },
6371     { Bad_Opcode },
6372     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6373     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6374     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6375     { Bad_Opcode },
6376     /* 20 */
6377     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6378     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6379     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6380     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6381     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6382     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     /* 28 */
6386     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6387     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6388     { MOD_TABLE (MOD_VEX_0F382A) },
6389     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6390     { MOD_TABLE (MOD_VEX_0F382C) },
6391     { MOD_TABLE (MOD_VEX_0F382D) },
6392     { MOD_TABLE (MOD_VEX_0F382E) },
6393     { MOD_TABLE (MOD_VEX_0F382F) },
6394     /* 30 */
6395     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6396     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6397     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6398     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6399     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6400     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6401     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6402     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6403     /* 38 */
6404     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6405     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6406     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6407     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6408     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6409     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6410     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6411     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6412     /* 40 */
6413     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6419     { VEX_W_TABLE (VEX_W_0F3846) },
6420     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6421     /* 48 */
6422     { Bad_Opcode },
6423     { X86_64_TABLE (X86_64_VEX_0F3849) },
6424     { Bad_Opcode },
6425     { X86_64_TABLE (X86_64_VEX_0F384B) },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     /* 50 */
6431     { VEX_W_TABLE (VEX_W_0F3850) },
6432     { VEX_W_TABLE (VEX_W_0F3851) },
6433     { VEX_W_TABLE (VEX_W_0F3852) },
6434     { VEX_W_TABLE (VEX_W_0F3853) },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     /* 58 */
6440     { VEX_W_TABLE (VEX_W_0F3858) },
6441     { VEX_W_TABLE (VEX_W_0F3859) },
6442     { MOD_TABLE (MOD_VEX_0F385A) },
6443     { Bad_Opcode },
6444     { X86_64_TABLE (X86_64_VEX_0F385C) },
6445     { Bad_Opcode },
6446     { X86_64_TABLE (X86_64_VEX_0F385E) },
6447     { Bad_Opcode },
6448     /* 60 */
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     /* 68 */
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     /* 70 */
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     /* 78 */
6476     { VEX_W_TABLE (VEX_W_0F3878) },
6477     { VEX_W_TABLE (VEX_W_0F3879) },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     /* 80 */
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     /* 88 */
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { MOD_TABLE (MOD_VEX_0F388C) },
6499     { Bad_Opcode },
6500     { MOD_TABLE (MOD_VEX_0F388E) },
6501     { Bad_Opcode },
6502     /* 90 */
6503     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6504     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6505     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6506     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6510     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6511     /* 98 */
6512     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6513     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6514     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6515     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6516     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6517     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6518     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6519     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6520     /* a0 */
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6528     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6529     /* a8 */
6530     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6531     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6532     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6533     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6534     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6535     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6536     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6537     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6538     /* b0 */
6539     { VEX_W_TABLE (VEX_W_0F38B0) },
6540     { VEX_W_TABLE (VEX_W_0F38B1) },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_W_TABLE (VEX_W_0F38B4) },
6544     { VEX_W_TABLE (VEX_W_0F38B5) },
6545     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6546     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6547     /* b8 */
6548     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6549     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6550     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6551     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6552     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6553     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6554     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6555     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6556     /* c0 */
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     /* c8 */
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_W_TABLE (VEX_W_0F38CF) },
6574     /* d0 */
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     /* d8 */
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6588     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6589     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6590     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6591     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6592     /* e0 */
6593     { X86_64_TABLE (X86_64_VEX_0F38E0) },
6594     { X86_64_TABLE (X86_64_VEX_0F38E1) },
6595     { X86_64_TABLE (X86_64_VEX_0F38E2) },
6596     { X86_64_TABLE (X86_64_VEX_0F38E3) },
6597     { X86_64_TABLE (X86_64_VEX_0F38E4) },
6598     { X86_64_TABLE (X86_64_VEX_0F38E5) },
6599     { X86_64_TABLE (X86_64_VEX_0F38E6) },
6600     { X86_64_TABLE (X86_64_VEX_0F38E7) },
6601     /* e8 */
6602     { X86_64_TABLE (X86_64_VEX_0F38E8) },
6603     { X86_64_TABLE (X86_64_VEX_0F38E9) },
6604     { X86_64_TABLE (X86_64_VEX_0F38EA) },
6605     { X86_64_TABLE (X86_64_VEX_0F38EB) },
6606     { X86_64_TABLE (X86_64_VEX_0F38EC) },
6607     { X86_64_TABLE (X86_64_VEX_0F38ED) },
6608     { X86_64_TABLE (X86_64_VEX_0F38EE) },
6609     { X86_64_TABLE (X86_64_VEX_0F38EF) },
6610     /* f0 */
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6614     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6615     { Bad_Opcode },
6616     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6617     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6618     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6619     /* f8 */
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628   },
6629   /* VEX_0F3A */
6630   {
6631     /* 00 */
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6633     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6634     { VEX_W_TABLE (VEX_W_0F3A02) },
6635     { Bad_Opcode },
6636     { VEX_W_TABLE (VEX_W_0F3A04) },
6637     { VEX_W_TABLE (VEX_W_0F3A05) },
6638     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6639     { Bad_Opcode },
6640     /* 08 */
6641     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6642     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6643     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6644     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6645     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6646     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6647     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6648     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6649     /* 10 */
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6655     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6656     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6658     /* 18 */
6659     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6660     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { VEX_W_TABLE (VEX_W_0F3A1D) },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     /* 20 */
6668     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6669     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     /* 28 */
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     /* 30 */
6686     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6687     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6688     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6689     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     /* 38 */
6695     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6696     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     /* 40 */
6704     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6706     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6707     { Bad_Opcode },
6708     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6709     { Bad_Opcode },
6710     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6711     { Bad_Opcode },
6712     /* 48 */
6713     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6714     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6715     { VEX_W_TABLE (VEX_W_0F3A4A) },
6716     { VEX_W_TABLE (VEX_W_0F3A4B) },
6717     { VEX_W_TABLE (VEX_W_0F3A4C) },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     /* 50 */
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     /* 58 */
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6736     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6737     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6738     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6739     /* 60 */
6740     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6741     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6742     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6743     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     /* 68 */
6749     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6750     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6751     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6752     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6753     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6754     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6755     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6756     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6757     /* 70 */
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     /* 78 */
6767     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6768     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6769     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6770     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6771     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6772     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6773     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6774     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6775     /* 80 */
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     /* 88 */
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     /* 90 */
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     /* 98 */
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     /* a0 */
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     /* a8 */
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     /* b0 */
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     /* b8 */
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     /* c0 */
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     /* c8 */
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { VEX_W_TABLE (VEX_W_0F3ACE) },
6864     { VEX_W_TABLE (VEX_W_0F3ACF) },
6865     /* d0 */
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     /* d8 */
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6883     /* e0 */
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     /* e8 */
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     /* f0 */
6902     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     /* f8 */
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919   },
6920 };
6921
6922 #include "i386-dis-evex.h"
6923
6924 static const struct dis386 vex_len_table[][2] = {
6925   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6926   {
6927     { "%XEvmovlpX",     { XM, Vex, EXq }, 0 },
6928   },
6929
6930   /* VEX_LEN_0F12_P_0_M_1 */
6931   {
6932     { "%XEvmovhlp%XS",  { XM, Vex, EXq }, 0 },
6933   },
6934
6935   /* VEX_LEN_0F13_M_0 */
6936   {
6937     { "%XEvmovlpX",     { EXq, XM }, PREFIX_OPCODE },
6938   },
6939
6940   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6941   {
6942     { "%XEvmovhpX",     { XM, Vex, EXq }, 0 },
6943   },
6944
6945   /* VEX_LEN_0F16_P_0_M_1 */
6946   {
6947     { "%XEvmovlhp%XS",  { XM, Vex, EXq }, 0 },
6948   },
6949
6950   /* VEX_LEN_0F17_M_0 */
6951   {
6952     { "%XEvmovhpX",     { EXq, XM }, PREFIX_OPCODE },
6953   },
6954
6955   /* VEX_LEN_0F41 */
6956   {
6957     { Bad_Opcode },
6958     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6959   },
6960
6961   /* VEX_LEN_0F42 */
6962   {
6963     { Bad_Opcode },
6964     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6965   },
6966
6967   /* VEX_LEN_0F44 */
6968   {
6969     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6970   },
6971
6972   /* VEX_LEN_0F45 */
6973   {
6974     { Bad_Opcode },
6975     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6976   },
6977
6978   /* VEX_LEN_0F46 */
6979   {
6980     { Bad_Opcode },
6981     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6982   },
6983
6984   /* VEX_LEN_0F47 */
6985   {
6986     { Bad_Opcode },
6987     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6988   },
6989
6990   /* VEX_LEN_0F4A */
6991   {
6992     { Bad_Opcode },
6993     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6994   },
6995
6996   /* VEX_LEN_0F4B */
6997   {
6998     { Bad_Opcode },
6999     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
7000   },
7001
7002   /* VEX_LEN_0F6E */
7003   {
7004     { "%XEvmovK",       { XMScalar, Edq }, PREFIX_DATA },
7005   },
7006
7007   /* VEX_LEN_0F77 */
7008   {
7009     { "vzeroupper",     { XX }, 0 },
7010     { "vzeroall",       { XX }, 0 },
7011   },
7012
7013   /* VEX_LEN_0F7E_P_1 */
7014   {
7015     { "%XEvmovq",       { XMScalar, EXq }, 0 },
7016   },
7017
7018   /* VEX_LEN_0F7E_P_2 */
7019   {
7020     { "%XEvmovK",       { Edq, XMScalar }, 0 },
7021   },
7022
7023   /* VEX_LEN_0F90 */
7024   {
7025     { VEX_W_TABLE (VEX_W_0F90_L_0) },
7026   },
7027
7028   /* VEX_LEN_0F91 */
7029   {
7030     { MOD_TABLE (MOD_VEX_0F91_L_0) },
7031   },
7032
7033   /* VEX_LEN_0F92 */
7034   {
7035     { MOD_TABLE (MOD_VEX_0F92_L_0) },
7036   },
7037
7038   /* VEX_LEN_0F93 */
7039   {
7040     { MOD_TABLE (MOD_VEX_0F93_L_0) },
7041   },
7042
7043   /* VEX_LEN_0F98 */
7044   {
7045     { MOD_TABLE (MOD_VEX_0F98_L_0) },
7046   },
7047
7048   /* VEX_LEN_0F99 */
7049   {
7050     { MOD_TABLE (MOD_VEX_0F99_L_0) },
7051   },
7052
7053   /* VEX_LEN_0FAE_R_2_M_0 */
7054   {
7055     { "vldmxcsr",       { Md }, 0 },
7056   },
7057
7058   /* VEX_LEN_0FAE_R_3_M_0 */
7059   {
7060     { "vstmxcsr",       { Md }, 0 },
7061   },
7062
7063   /* VEX_LEN_0FC4 */
7064   {
7065     { "%XEvpinsrw",     { XM, Vex, Edw, Ib }, PREFIX_DATA },
7066   },
7067
7068   /* VEX_LEN_0FC5 */
7069   {
7070     { "%XEvpextrw",     { Gd, XS, Ib }, PREFIX_DATA },
7071   },
7072
7073   /* VEX_LEN_0FD6 */
7074   {
7075     { "%XEvmovq",       { EXqS, XMScalar }, PREFIX_DATA },
7076   },
7077
7078   /* VEX_LEN_0FF7 */
7079   {
7080     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
7081   },
7082
7083   /* VEX_LEN_0F3816 */
7084   {
7085     { Bad_Opcode },
7086     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7087   },
7088
7089   /* VEX_LEN_0F3819 */
7090   {
7091     { Bad_Opcode },
7092     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7093   },
7094
7095   /* VEX_LEN_0F381A_M_0 */
7096   {
7097     { Bad_Opcode },
7098     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
7099   },
7100
7101   /* VEX_LEN_0F3836 */
7102   {
7103     { Bad_Opcode },
7104     { VEX_W_TABLE (VEX_W_0F3836) },
7105   },
7106
7107   /* VEX_LEN_0F3841 */
7108   {
7109     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
7110   },
7111
7112    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
7113   {
7114     { "ldtilecfg", { M }, 0 },
7115   },
7116
7117   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
7118   {
7119     { "tilerelease", { Skip_MODRM }, 0 },
7120   },
7121
7122   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7123   {
7124     { "sttilecfg", { M }, 0 },
7125   },
7126
7127   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7128   {
7129     { "tilezero", { TMM, Skip_MODRM }, 0 },
7130   },
7131
7132   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7133   {
7134     { "tilestored", { MVexSIBMEM, TMM }, 0 },
7135   },
7136   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7137   {
7138     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7139   },
7140
7141   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7142   {
7143     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7144   },
7145
7146   /* VEX_LEN_0F385A_M_0 */
7147   {
7148     { Bad_Opcode },
7149     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7150   },
7151
7152   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7153   {
7154     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7155   },
7156
7157   /* VEX_LEN_0F385C_X86_64_P_3_W_0_M_0 */
7158   {
7159     { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
7160   },
7161
7162   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7163   {
7164     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7165   },
7166
7167   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7168   {
7169     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7170   },
7171
7172   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7173   {
7174     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7175   },
7176
7177   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7178   {
7179     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7180   },
7181
7182   /* VEX_LEN_0F38DB */
7183   {
7184     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7185   },
7186
7187   /* VEX_LEN_0F38F2 */
7188   {
7189     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7190   },
7191
7192   /* VEX_LEN_0F38F3 */
7193   {
7194     { REG_TABLE(REG_VEX_0F38F3_L_0) },
7195   },
7196
7197   /* VEX_LEN_0F38F5 */
7198   {
7199     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7200   },
7201
7202   /* VEX_LEN_0F38F6 */
7203   {
7204     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7205   },
7206
7207   /* VEX_LEN_0F38F7 */
7208   {
7209     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7210   },
7211
7212   /* VEX_LEN_0F3A00 */
7213   {
7214     { Bad_Opcode },
7215     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7216   },
7217
7218   /* VEX_LEN_0F3A01 */
7219   {
7220     { Bad_Opcode },
7221     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7222   },
7223
7224   /* VEX_LEN_0F3A06 */
7225   {
7226     { Bad_Opcode },
7227     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7228   },
7229
7230   /* VEX_LEN_0F3A14 */
7231   {
7232     { "%XEvpextrb",     { Edb, XM, Ib }, PREFIX_DATA },
7233   },
7234
7235   /* VEX_LEN_0F3A15 */
7236   {
7237     { "%XEvpextrw",     { Edw, XM, Ib }, PREFIX_DATA },
7238   },
7239
7240   /* VEX_LEN_0F3A16  */
7241   {
7242     { "%XEvpextrK",     { Edq, XM, Ib }, PREFIX_DATA },
7243   },
7244
7245   /* VEX_LEN_0F3A17 */
7246   {
7247     { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7248   },
7249
7250   /* VEX_LEN_0F3A18 */
7251   {
7252     { Bad_Opcode },
7253     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7254   },
7255
7256   /* VEX_LEN_0F3A19 */
7257   {
7258     { Bad_Opcode },
7259     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7260   },
7261
7262   /* VEX_LEN_0F3A20 */
7263   {
7264     { "%XEvpinsrb",     { XM, Vex, Edb, Ib }, PREFIX_DATA },
7265   },
7266
7267   /* VEX_LEN_0F3A21 */
7268   {
7269     { "%XEvinsertps",   { XM, Vex, EXd, Ib }, PREFIX_DATA },
7270   },
7271
7272   /* VEX_LEN_0F3A22 */
7273   {
7274     { "%XEvpinsrK",     { XM, Vex, Edq, Ib }, PREFIX_DATA },
7275   },
7276
7277   /* VEX_LEN_0F3A30 */
7278   {
7279     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7280   },
7281
7282   /* VEX_LEN_0F3A31 */
7283   {
7284     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7285   },
7286
7287   /* VEX_LEN_0F3A32 */
7288   {
7289     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7290   },
7291
7292   /* VEX_LEN_0F3A33 */
7293   {
7294     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7295   },
7296
7297   /* VEX_LEN_0F3A38 */
7298   {
7299     { Bad_Opcode },
7300     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7301   },
7302
7303   /* VEX_LEN_0F3A39 */
7304   {
7305     { Bad_Opcode },
7306     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7307   },
7308
7309   /* VEX_LEN_0F3A41 */
7310   {
7311     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7312   },
7313
7314   /* VEX_LEN_0F3A46 */
7315   {
7316     { Bad_Opcode },
7317     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7318   },
7319
7320   /* VEX_LEN_0F3A60 */
7321   {
7322     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7323   },
7324
7325   /* VEX_LEN_0F3A61 */
7326   {
7327     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7328   },
7329
7330   /* VEX_LEN_0F3A62 */
7331   {
7332     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7333   },
7334
7335   /* VEX_LEN_0F3A63 */
7336   {
7337     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7338   },
7339
7340   /* VEX_LEN_0F3ADF */
7341   {
7342     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7343   },
7344
7345   /* VEX_LEN_0F3AF0 */
7346   {
7347     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7348   },
7349
7350   /* VEX_LEN_0FXOP_08_85 */
7351   {
7352     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7353   },
7354
7355   /* VEX_LEN_0FXOP_08_86 */
7356   {
7357     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7358   },
7359
7360   /* VEX_LEN_0FXOP_08_87 */
7361   {
7362     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7363   },
7364
7365   /* VEX_LEN_0FXOP_08_8E */
7366   {
7367     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7368   },
7369
7370   /* VEX_LEN_0FXOP_08_8F */
7371   {
7372     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7373   },
7374
7375   /* VEX_LEN_0FXOP_08_95 */
7376   {
7377     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7378   },
7379
7380   /* VEX_LEN_0FXOP_08_96 */
7381   {
7382     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7383   },
7384
7385   /* VEX_LEN_0FXOP_08_97 */
7386   {
7387     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7388   },
7389
7390   /* VEX_LEN_0FXOP_08_9E */
7391   {
7392     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7393   },
7394
7395   /* VEX_LEN_0FXOP_08_9F */
7396   {
7397     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7398   },
7399
7400   /* VEX_LEN_0FXOP_08_A3 */
7401   {
7402     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7403   },
7404
7405   /* VEX_LEN_0FXOP_08_A6 */
7406   {
7407     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7408   },
7409
7410   /* VEX_LEN_0FXOP_08_B6 */
7411   {
7412     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7413   },
7414
7415   /* VEX_LEN_0FXOP_08_C0 */
7416   {
7417     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7418   },
7419
7420   /* VEX_LEN_0FXOP_08_C1 */
7421   {
7422     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7423   },
7424
7425   /* VEX_LEN_0FXOP_08_C2 */
7426   {
7427     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7428   },
7429
7430   /* VEX_LEN_0FXOP_08_C3 */
7431   {
7432     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7433   },
7434
7435   /* VEX_LEN_0FXOP_08_CC */
7436   {
7437     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7438   },
7439
7440   /* VEX_LEN_0FXOP_08_CD */
7441   {
7442     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7443   },
7444
7445   /* VEX_LEN_0FXOP_08_CE */
7446   {
7447     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7448   },
7449
7450   /* VEX_LEN_0FXOP_08_CF */
7451   {
7452     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7453   },
7454
7455   /* VEX_LEN_0FXOP_08_EC */
7456   {
7457     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7458   },
7459
7460   /* VEX_LEN_0FXOP_08_ED */
7461   {
7462     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7463   },
7464
7465   /* VEX_LEN_0FXOP_08_EE */
7466   {
7467     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7468   },
7469
7470   /* VEX_LEN_0FXOP_08_EF */
7471   {
7472     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7473   },
7474
7475   /* VEX_LEN_0FXOP_09_01 */
7476   {
7477     { REG_TABLE (REG_XOP_09_01_L_0) },
7478   },
7479
7480   /* VEX_LEN_0FXOP_09_02 */
7481   {
7482     { REG_TABLE (REG_XOP_09_02_L_0) },
7483   },
7484
7485   /* VEX_LEN_0FXOP_09_12_M_1 */
7486   {
7487     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7488   },
7489
7490   /* VEX_LEN_0FXOP_09_82_W_0 */
7491   {
7492     { "vfrczss",        { XM, EXd }, 0 },
7493   },
7494
7495   /* VEX_LEN_0FXOP_09_83_W_0 */
7496   {
7497     { "vfrczsd",        { XM, EXq }, 0 },
7498   },
7499
7500   /* VEX_LEN_0FXOP_09_90 */
7501   {
7502     { "vprotb",         { XM, EXx, VexW }, 0 },
7503   },
7504
7505   /* VEX_LEN_0FXOP_09_91 */
7506   {
7507     { "vprotw",         { XM, EXx, VexW }, 0 },
7508   },
7509
7510   /* VEX_LEN_0FXOP_09_92 */
7511   {
7512     { "vprotd",         { XM, EXx, VexW }, 0 },
7513   },
7514
7515   /* VEX_LEN_0FXOP_09_93 */
7516   {
7517     { "vprotq",         { XM, EXx, VexW }, 0 },
7518   },
7519
7520   /* VEX_LEN_0FXOP_09_94 */
7521   {
7522     { "vpshlb",         { XM, EXx, VexW }, 0 },
7523   },
7524
7525   /* VEX_LEN_0FXOP_09_95 */
7526   {
7527     { "vpshlw",         { XM, EXx, VexW }, 0 },
7528   },
7529
7530   /* VEX_LEN_0FXOP_09_96 */
7531   {
7532     { "vpshld",         { XM, EXx, VexW }, 0 },
7533   },
7534
7535   /* VEX_LEN_0FXOP_09_97 */
7536   {
7537     { "vpshlq",         { XM, EXx, VexW }, 0 },
7538   },
7539
7540   /* VEX_LEN_0FXOP_09_98 */
7541   {
7542     { "vpshab",         { XM, EXx, VexW }, 0 },
7543   },
7544
7545   /* VEX_LEN_0FXOP_09_99 */
7546   {
7547     { "vpshaw",         { XM, EXx, VexW }, 0 },
7548   },
7549
7550   /* VEX_LEN_0FXOP_09_9A */
7551   {
7552     { "vpshad",         { XM, EXx, VexW }, 0 },
7553   },
7554
7555   /* VEX_LEN_0FXOP_09_9B */
7556   {
7557     { "vpshaq",         { XM, EXx, VexW }, 0 },
7558   },
7559
7560   /* VEX_LEN_0FXOP_09_C1 */
7561   {
7562     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7563   },
7564
7565   /* VEX_LEN_0FXOP_09_C2 */
7566   {
7567     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7568   },
7569
7570   /* VEX_LEN_0FXOP_09_C3 */
7571   {
7572     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7573   },
7574
7575   /* VEX_LEN_0FXOP_09_C6 */
7576   {
7577     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7578   },
7579
7580   /* VEX_LEN_0FXOP_09_C7 */
7581   {
7582     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7583   },
7584
7585   /* VEX_LEN_0FXOP_09_CB */
7586   {
7587     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7588   },
7589
7590   /* VEX_LEN_0FXOP_09_D1 */
7591   {
7592     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7593   },
7594
7595   /* VEX_LEN_0FXOP_09_D2 */
7596   {
7597     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7598   },
7599
7600   /* VEX_LEN_0FXOP_09_D3 */
7601   {
7602     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7603   },
7604
7605   /* VEX_LEN_0FXOP_09_D6 */
7606   {
7607     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7608   },
7609
7610   /* VEX_LEN_0FXOP_09_D7 */
7611   {
7612     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7613   },
7614
7615   /* VEX_LEN_0FXOP_09_DB */
7616   {
7617     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7618   },
7619
7620   /* VEX_LEN_0FXOP_09_E1 */
7621   {
7622     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7623   },
7624
7625   /* VEX_LEN_0FXOP_09_E2 */
7626   {
7627     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7628   },
7629
7630   /* VEX_LEN_0FXOP_09_E3 */
7631   {
7632     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7633   },
7634
7635   /* VEX_LEN_0FXOP_0A_12 */
7636   {
7637     { REG_TABLE (REG_XOP_0A_12_L_0) },
7638   },
7639 };
7640
7641 #include "i386-dis-evex-len.h"
7642
7643 static const struct dis386 vex_w_table[][2] = {
7644   {
7645     /* VEX_W_0F41_L_1_M_1 */
7646     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7647     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7648   },
7649   {
7650     /* VEX_W_0F42_L_1_M_1 */
7651     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7652     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7653   },
7654   {
7655     /* VEX_W_0F44_L_0_M_1 */
7656     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7657     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7658   },
7659   {
7660     /* VEX_W_0F45_L_1_M_1 */
7661     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7662     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7663   },
7664   {
7665     /* VEX_W_0F46_L_1_M_1 */
7666     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7667     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7668   },
7669   {
7670     /* VEX_W_0F47_L_1_M_1 */
7671     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7672     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7673   },
7674   {
7675     /* VEX_W_0F4A_L_1_M_1 */
7676     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7677     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7678   },
7679   {
7680     /* VEX_W_0F4B_L_1_M_1 */
7681     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7682     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7683   },
7684   {
7685     /* VEX_W_0F90_L_0 */
7686     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7687     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7688   },
7689   {
7690     /* VEX_W_0F91_L_0_M_0 */
7691     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7692     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7693   },
7694   {
7695     /* VEX_W_0F92_L_0_M_1 */
7696     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7697     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7698   },
7699   {
7700     /* VEX_W_0F93_L_0_M_1 */
7701     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7702     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7703   },
7704   {
7705     /* VEX_W_0F98_L_0_M_1 */
7706     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7707     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7708   },
7709   {
7710     /* VEX_W_0F99_L_0_M_1 */
7711     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7712     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7713   },
7714   {
7715     /* VEX_W_0F380C  */
7716     { "%XEvpermilps",   { XM, Vex, EXx }, PREFIX_DATA },
7717   },
7718   {
7719     /* VEX_W_0F380D  */
7720     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7721   },
7722   {
7723     /* VEX_W_0F380E  */
7724     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7725   },
7726   {
7727     /* VEX_W_0F380F  */
7728     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7729   },
7730   {
7731     /* VEX_W_0F3813 */
7732     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7733   },
7734   {
7735     /* VEX_W_0F3816_L_1  */
7736     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7737   },
7738   {
7739     /* VEX_W_0F3818 */
7740     { "%XEvbroadcastss",        { XM, EXd }, PREFIX_DATA },
7741   },
7742   {
7743     /* VEX_W_0F3819_L_1 */
7744     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7745   },
7746   {
7747     /* VEX_W_0F381A_M_0_L_1 */
7748     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7749   },
7750   {
7751     /* VEX_W_0F382C_M_0 */
7752     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7753   },
7754   {
7755     /* VEX_W_0F382D_M_0 */
7756     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7757   },
7758   {
7759     /* VEX_W_0F382E_M_0 */
7760     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7761   },
7762   {
7763     /* VEX_W_0F382F_M_0 */
7764     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7765   },
7766   {
7767     /* VEX_W_0F3836  */
7768     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7769   },
7770   {
7771     /* VEX_W_0F3846 */
7772     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7773   },
7774   {
7775     /* VEX_W_0F3849_X86_64_P_0 */
7776     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7777   },
7778   {
7779     /* VEX_W_0F3849_X86_64_P_2 */
7780     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7781   },
7782   {
7783     /* VEX_W_0F3849_X86_64_P_3 */
7784     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7785   },
7786   {
7787     /* VEX_W_0F384B_X86_64_P_1 */
7788     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7789   },
7790   {
7791     /* VEX_W_0F384B_X86_64_P_2 */
7792     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7793   },
7794   {
7795     /* VEX_W_0F384B_X86_64_P_3 */
7796     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7797   },
7798   {
7799     /* VEX_W_0F3850 */
7800     { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7801   },
7802   {
7803     /* VEX_W_0F3851 */
7804     { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7805   },
7806   {
7807     /* VEX_W_0F3852 */
7808     { "%XVvpdpwssd",    { XM, Vex, EXx }, PREFIX_DATA },
7809   },
7810   {
7811     /* VEX_W_0F3853 */
7812     { "%XVvpdpwssds",   { XM, Vex, EXx }, PREFIX_DATA },
7813   },
7814   {
7815     /* VEX_W_0F3858 */
7816     { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7817   },
7818   {
7819     /* VEX_W_0F3859 */
7820     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7821   },
7822   {
7823     /* VEX_W_0F385A_M_0_L_0 */
7824     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7825   },
7826   {
7827     /* VEX_W_0F385C_X86_64_P_1 */
7828     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7829   },
7830   {
7831     /* VEX_W_0F385C_X86_64_P_3 */
7832     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_3_W_0) },
7833   },
7834   {
7835     /* VEX_W_0F385E_X86_64_P_0 */
7836     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7837   },
7838   {
7839     /* VEX_W_0F385E_X86_64_P_1 */
7840     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7841   },
7842   {
7843     /* VEX_W_0F385E_X86_64_P_2 */
7844     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7845   },
7846   {
7847     /* VEX_W_0F385E_X86_64_P_3 */
7848     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7849   },
7850   {
7851     /* VEX_W_0F3872_P_1 */
7852     { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7853   },
7854   {
7855     /* VEX_W_0F3878 */
7856     { "%XEvpbroadcastb",        { XM, EXb }, PREFIX_DATA },
7857   },
7858   {
7859     /* VEX_W_0F3879 */
7860     { "%XEvpbroadcastw",        { XM, EXw }, PREFIX_DATA },
7861   },
7862   {
7863     /* VEX_W_0F38B0 */
7864     { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7865   },
7866   {
7867     /* VEX_W_0F38B1 */
7868     { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7869   },
7870   {
7871     /* VEX_W_0F38B4 */
7872     { Bad_Opcode },
7873     { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7874   },
7875   {
7876     /* VEX_W_0F38B5 */
7877     { Bad_Opcode },
7878     { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7879   },
7880   {
7881     /* VEX_W_0F38CF */
7882     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7883   },
7884   {
7885     /* VEX_W_0F3A00_L_1 */
7886     { Bad_Opcode },
7887     { "%XEvpermq",              { XM, EXx, Ib }, PREFIX_DATA },
7888   },
7889   {
7890     /* VEX_W_0F3A01_L_1 */
7891     { Bad_Opcode },
7892     { "%XEvpermpd",     { XM, EXx, Ib }, PREFIX_DATA },
7893   },
7894   {
7895     /* VEX_W_0F3A02 */
7896     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7897   },
7898   {
7899     /* VEX_W_0F3A04 */
7900     { "%XEvpermilps",   { XM, EXx, Ib }, PREFIX_DATA },
7901   },
7902   {
7903     /* VEX_W_0F3A05 */
7904     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7905   },
7906   {
7907     /* VEX_W_0F3A06_L_1 */
7908     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7909   },
7910   {
7911     /* VEX_W_0F3A18_L_1 */
7912     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7913   },
7914   {
7915     /* VEX_W_0F3A19_L_1 */
7916     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7917   },
7918   {
7919     /* VEX_W_0F3A1D */
7920     { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7921   },
7922   {
7923     /* VEX_W_0F3A38_L_1 */
7924     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7925   },
7926   {
7927     /* VEX_W_0F3A39_L_1 */
7928     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7929   },
7930   {
7931     /* VEX_W_0F3A46_L_1 */
7932     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7933   },
7934   {
7935     /* VEX_W_0F3A4A */
7936     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7937   },
7938   {
7939     /* VEX_W_0F3A4B */
7940     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7941   },
7942   {
7943     /* VEX_W_0F3A4C */
7944     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7945   },
7946   {
7947     /* VEX_W_0F3ACE */
7948     { Bad_Opcode },
7949     { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7950   },
7951   {
7952     /* VEX_W_0F3ACF */
7953     { Bad_Opcode },
7954     { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7955   },
7956   /* VEX_W_0FXOP_08_85_L_0 */
7957   {
7958     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7959   },
7960   /* VEX_W_0FXOP_08_86_L_0 */
7961   {
7962     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7963   },
7964   /* VEX_W_0FXOP_08_87_L_0 */
7965   {
7966     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7967   },
7968   /* VEX_W_0FXOP_08_8E_L_0 */
7969   {
7970     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7971   },
7972   /* VEX_W_0FXOP_08_8F_L_0 */
7973   {
7974     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7975   },
7976   /* VEX_W_0FXOP_08_95_L_0 */
7977   {
7978     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7979   },
7980   /* VEX_W_0FXOP_08_96_L_0 */
7981   {
7982     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7983   },
7984   /* VEX_W_0FXOP_08_97_L_0 */
7985   {
7986     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7987   },
7988   /* VEX_W_0FXOP_08_9E_L_0 */
7989   {
7990     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7991   },
7992   /* VEX_W_0FXOP_08_9F_L_0 */
7993   {
7994     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7995   },
7996   /* VEX_W_0FXOP_08_A6_L_0 */
7997   {
7998     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7999   },
8000   /* VEX_W_0FXOP_08_B6_L_0 */
8001   {
8002     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
8003   },
8004   /* VEX_W_0FXOP_08_C0_L_0 */
8005   {
8006     { "vprotb",         { XM, EXx, Ib }, 0 },
8007   },
8008   /* VEX_W_0FXOP_08_C1_L_0 */
8009   {
8010     { "vprotw",         { XM, EXx, Ib }, 0 },
8011   },
8012   /* VEX_W_0FXOP_08_C2_L_0 */
8013   {
8014     { "vprotd",         { XM, EXx, Ib }, 0 },
8015   },
8016   /* VEX_W_0FXOP_08_C3_L_0 */
8017   {
8018     { "vprotq",         { XM, EXx, Ib }, 0 },
8019   },
8020   /* VEX_W_0FXOP_08_CC_L_0 */
8021   {
8022      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
8023   },
8024   /* VEX_W_0FXOP_08_CD_L_0 */
8025   {
8026      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
8027   },
8028   /* VEX_W_0FXOP_08_CE_L_0 */
8029   {
8030      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
8031   },
8032   /* VEX_W_0FXOP_08_CF_L_0 */
8033   {
8034      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
8035   },
8036   /* VEX_W_0FXOP_08_EC_L_0 */
8037   {
8038      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
8039   },
8040   /* VEX_W_0FXOP_08_ED_L_0 */
8041   {
8042      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
8043   },
8044   /* VEX_W_0FXOP_08_EE_L_0 */
8045   {
8046      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
8047   },
8048   /* VEX_W_0FXOP_08_EF_L_0 */
8049   {
8050      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
8051   },
8052   /* VEX_W_0FXOP_09_80 */
8053   {
8054     { "vfrczps",        { XM, EXx }, 0 },
8055   },
8056   /* VEX_W_0FXOP_09_81 */
8057   {
8058     { "vfrczpd",        { XM, EXx }, 0 },
8059   },
8060   /* VEX_W_0FXOP_09_82 */
8061   {
8062     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
8063   },
8064   /* VEX_W_0FXOP_09_83 */
8065   {
8066     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
8067   },
8068   /* VEX_W_0FXOP_09_C1_L_0 */
8069   {
8070     { "vphaddbw",       { XM, EXxmm }, 0 },
8071   },
8072   /* VEX_W_0FXOP_09_C2_L_0 */
8073   {
8074     { "vphaddbd",       { XM, EXxmm }, 0 },
8075   },
8076   /* VEX_W_0FXOP_09_C3_L_0 */
8077   {
8078     { "vphaddbq",       { XM, EXxmm }, 0 },
8079   },
8080   /* VEX_W_0FXOP_09_C6_L_0 */
8081   {
8082     { "vphaddwd",       { XM, EXxmm }, 0 },
8083   },
8084   /* VEX_W_0FXOP_09_C7_L_0 */
8085   {
8086     { "vphaddwq",       { XM, EXxmm }, 0 },
8087   },
8088   /* VEX_W_0FXOP_09_CB_L_0 */
8089   {
8090     { "vphadddq",       { XM, EXxmm }, 0 },
8091   },
8092   /* VEX_W_0FXOP_09_D1_L_0 */
8093   {
8094     { "vphaddubw",      { XM, EXxmm }, 0 },
8095   },
8096   /* VEX_W_0FXOP_09_D2_L_0 */
8097   {
8098     { "vphaddubd",      { XM, EXxmm }, 0 },
8099   },
8100   /* VEX_W_0FXOP_09_D3_L_0 */
8101   {
8102     { "vphaddubq",      { XM, EXxmm }, 0 },
8103   },
8104   /* VEX_W_0FXOP_09_D6_L_0 */
8105   {
8106     { "vphadduwd",      { XM, EXxmm }, 0 },
8107   },
8108   /* VEX_W_0FXOP_09_D7_L_0 */
8109   {
8110     { "vphadduwq",      { XM, EXxmm }, 0 },
8111   },
8112   /* VEX_W_0FXOP_09_DB_L_0 */
8113   {
8114     { "vphaddudq",      { XM, EXxmm }, 0 },
8115   },
8116   /* VEX_W_0FXOP_09_E1_L_0 */
8117   {
8118     { "vphsubbw",       { XM, EXxmm }, 0 },
8119   },
8120   /* VEX_W_0FXOP_09_E2_L_0 */
8121   {
8122     { "vphsubwd",       { XM, EXxmm }, 0 },
8123   },
8124   /* VEX_W_0FXOP_09_E3_L_0 */
8125   {
8126     { "vphsubdq",       { XM, EXxmm }, 0 },
8127   },
8128
8129 #include "i386-dis-evex-w.h"
8130 };
8131
8132 static const struct dis386 mod_table[][2] = {
8133   {
8134     /* MOD_62_32BIT */
8135     { "bound{S|}",      { Gv, Ma }, 0 },
8136     { EVEX_TABLE (EVEX_0F) },
8137   },
8138   {
8139     /* MOD_8D */
8140     { "leaS",           { Gv, M }, 0 },
8141   },
8142   {
8143     /* MOD_C4_32BIT */
8144     { "lesS",           { Gv, Mp }, 0 },
8145     { VEX_C4_TABLE (VEX_0F) },
8146   },
8147   {
8148     /* MOD_C5_32BIT */
8149     { "ldsS",           { Gv, Mp }, 0 },
8150     { VEX_C5_TABLE (VEX_0F) },
8151   },
8152   {
8153     /* MOD_C6_REG_7 */
8154     { Bad_Opcode },
8155     { RM_TABLE (RM_C6_REG_7) },
8156   },
8157   {
8158     /* MOD_C7_REG_7 */
8159     { Bad_Opcode },
8160     { RM_TABLE (RM_C7_REG_7) },
8161   },
8162   {
8163     /* MOD_FF_REG_3 */
8164     { "{l|}call^", { indirEp }, 0 },
8165   },
8166   {
8167     /* MOD_FF_REG_5 */
8168     { "{l|}jmp^", { indirEp }, 0 },
8169   },
8170   {
8171     /* MOD_0F01_REG_0 */
8172     { X86_64_TABLE (X86_64_0F01_REG_0) },
8173     { RM_TABLE (RM_0F01_REG_0) },
8174   },
8175   {
8176     /* MOD_0F01_REG_1 */
8177     { X86_64_TABLE (X86_64_0F01_REG_1) },
8178     { RM_TABLE (RM_0F01_REG_1) },
8179   },
8180   {
8181     /* MOD_0F01_REG_2 */
8182     { X86_64_TABLE (X86_64_0F01_REG_2) },
8183     { RM_TABLE (RM_0F01_REG_2) },
8184   },
8185   {
8186     /* MOD_0F01_REG_3 */
8187     { X86_64_TABLE (X86_64_0F01_REG_3) },
8188     { RM_TABLE (RM_0F01_REG_3) },
8189   },
8190   {
8191     /* MOD_0F01_REG_5 */
8192     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8193     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8194   },
8195   {
8196     /* MOD_0F01_REG_7 */
8197     { "invlpg",         { Mb }, 0 },
8198     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8199   },
8200   {
8201     /* MOD_0F12_PREFIX_0 */
8202     { "movlpX",         { XM, EXq }, 0 },
8203     { "movhlps",        { XM, EXq }, 0 },
8204   },
8205   {
8206     /* MOD_0F12_PREFIX_2 */
8207     { "movlpX", { XM, EXq }, 0 },
8208   },
8209   {
8210     /* MOD_0F13 */
8211     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
8212   },
8213   {
8214     /* MOD_0F16_PREFIX_0 */
8215     { "movhpX",         { XM, EXq }, 0 },
8216     { "movlhps",        { XM, EXq }, 0 },
8217   },
8218   {
8219     /* MOD_0F16_PREFIX_2 */
8220     { "movhpX", { XM, EXq }, 0 },
8221   },
8222   {
8223     /* MOD_0F17 */
8224     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8225   },
8226   {
8227     /* MOD_0F18_REG_0 */
8228     { "prefetchnta",    { Mb }, 0 },
8229     { "nopQ",           { Ev }, 0 },
8230   },
8231   {
8232     /* MOD_0F18_REG_1 */
8233     { "prefetcht0",     { Mb }, 0 },
8234     { "nopQ",           { Ev }, 0 },
8235   },
8236   {
8237     /* MOD_0F18_REG_2 */
8238     { "prefetcht1",     { Mb }, 0 },
8239     { "nopQ",           { Ev }, 0 },
8240   },
8241   {
8242     /* MOD_0F18_REG_3 */
8243     { "prefetcht2",     { Mb }, 0 },
8244     { "nopQ",           { Ev }, 0 },
8245   },
8246   {
8247     /* MOD_0F18_REG_6 */
8248     { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8249     { "nopQ",           { Ev }, 0 },
8250   },
8251   {
8252     /* MOD_0F18_REG_7 */
8253     { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8254     { "nopQ",           { Ev }, 0 },
8255   },
8256   {
8257     /* MOD_0F1A_PREFIX_0 */
8258     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8259     { "nopQ",           { Ev }, 0 },
8260   },
8261   {
8262     /* MOD_0F1B_PREFIX_0 */
8263     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8264     { "nopQ",           { Ev }, 0 },
8265   },
8266   {
8267     /* MOD_0F1B_PREFIX_1 */
8268     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8269     { "nopQ",           { Ev }, PREFIX_IGNORED },
8270   },
8271   {
8272     /* MOD_0F1C_PREFIX_0 */
8273     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8274     { "nopQ",           { Ev }, 0 },
8275   },
8276   {
8277     /* MOD_0F1E_PREFIX_1 */
8278     { "nopQ",           { Ev }, PREFIX_IGNORED },
8279     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8280   },
8281   {
8282     /* MOD_0F2B_PREFIX_0 */
8283     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8284   },
8285   {
8286     /* MOD_0F2B_PREFIX_1 */
8287     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8288   },
8289   {
8290     /* MOD_0F2B_PREFIX_2 */
8291     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8292   },
8293   {
8294     /* MOD_0F2B_PREFIX_3 */
8295     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8296   },
8297   {
8298     /* MOD_0F50 */
8299     { Bad_Opcode },
8300     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8301   },
8302   {
8303     /* MOD_0F71 */
8304     { Bad_Opcode },
8305     { REG_TABLE (REG_0F71_MOD_0) },
8306   },
8307   {
8308     /* MOD_0F72 */
8309     { Bad_Opcode },
8310     { REG_TABLE (REG_0F72_MOD_0) },
8311   },
8312   {
8313     /* MOD_0F73 */
8314     { Bad_Opcode },
8315     { REG_TABLE (REG_0F73_MOD_0) },
8316   },
8317   {
8318     /* MOD_0FAE_REG_0 */
8319     { "fxsave",         { FXSAVE }, 0 },
8320     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8321   },
8322   {
8323     /* MOD_0FAE_REG_1 */
8324     { "fxrstor",        { FXSAVE }, 0 },
8325     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8326   },
8327   {
8328     /* MOD_0FAE_REG_2 */
8329     { "ldmxcsr",        { Md }, 0 },
8330     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8331   },
8332   {
8333     /* MOD_0FAE_REG_3 */
8334     { "stmxcsr",        { Md }, 0 },
8335     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8336   },
8337   {
8338     /* MOD_0FAE_REG_4 */
8339     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8340     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8341   },
8342   {
8343     /* MOD_0FAE_REG_5 */
8344     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8345     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8346   },
8347   {
8348     /* MOD_0FAE_REG_6 */
8349     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8350     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8351   },
8352   {
8353     /* MOD_0FAE_REG_7 */
8354     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8355     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8356   },
8357   {
8358     /* MOD_0FB2 */
8359     { "lssS",           { Gv, Mp }, 0 },
8360   },
8361   {
8362     /* MOD_0FB4 */
8363     { "lfsS",           { Gv, Mp }, 0 },
8364   },
8365   {
8366     /* MOD_0FB5 */
8367     { "lgsS",           { Gv, Mp }, 0 },
8368   },
8369   {
8370     /* MOD_0FC3 */
8371     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8372   },
8373   {
8374     /* MOD_0FC7_REG_3 */
8375     { "xrstors",        { FXSAVE }, 0 },
8376   },
8377   {
8378     /* MOD_0FC7_REG_4 */
8379     { "xsavec",         { FXSAVE }, 0 },
8380   },
8381   {
8382     /* MOD_0FC7_REG_5 */
8383     { "xsaves",         { FXSAVE }, 0 },
8384   },
8385   {
8386     /* MOD_0FC7_REG_6 */
8387     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8388     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8389   },
8390   {
8391     /* MOD_0FC7_REG_7 */
8392     { "vmptrst",        { Mq }, 0 },
8393     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8394   },
8395   {
8396     /* MOD_0FD7 */
8397     { Bad_Opcode },
8398     { "pmovmskb",       { Gdq, MS }, 0 },
8399   },
8400   {
8401     /* MOD_0FE7_PREFIX_2 */
8402     { "movntdq",        { Mx, XM }, 0 },
8403   },
8404   {
8405     /* MOD_0FF0_PREFIX_3 */
8406     { "lddqu",          { XM, M }, 0 },
8407   },
8408   {
8409     /* MOD_0F382A */
8410     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8411   },
8412   {
8413     /* MOD_0F38DC_PREFIX_1 */
8414     { "aesenc128kl",    { XM, M }, 0 },
8415     { "loadiwkey",      { XM, EXx }, 0 },
8416   },
8417   {
8418     /* MOD_0F38DD_PREFIX_1 */
8419     { "aesdec128kl",    { XM, M }, 0 },
8420   },
8421   {
8422     /* MOD_0F38DE_PREFIX_1 */
8423     { "aesenc256kl",    { XM, M }, 0 },
8424   },
8425   {
8426     /* MOD_0F38DF_PREFIX_1 */
8427     { "aesdec256kl",    { XM, M }, 0 },
8428   },
8429   {
8430     /* MOD_0F38F5 */
8431     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8432   },
8433   {
8434     /* MOD_0F38F6_PREFIX_0 */
8435     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8436   },
8437   {
8438     /* MOD_0F38F8_PREFIX_1 */
8439     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8440   },
8441   {
8442     /* MOD_0F38F8_PREFIX_2 */
8443     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8444   },
8445   {
8446     /* MOD_0F38F8_PREFIX_3 */
8447     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8448   },
8449   {
8450     /* MOD_0F38F9 */
8451     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8452   },
8453   {
8454     /* MOD_0F38FA_PREFIX_1 */
8455     { Bad_Opcode },
8456     { "encodekey128", { Gd, Ed }, 0 },
8457   },
8458   {
8459     /* MOD_0F38FB_PREFIX_1 */
8460     { Bad_Opcode },
8461     { "encodekey256", { Gd, Ed }, 0 },
8462   },
8463   {
8464     /* MOD_0F3A0F_PREFIX_1 */
8465     { Bad_Opcode },
8466     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8467   },
8468   {
8469     /* MOD_VEX_0F12_PREFIX_0 */
8470     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8471     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8472   },
8473   {
8474     /* MOD_VEX_0F12_PREFIX_2 */
8475     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8476   },
8477   {
8478     /* MOD_VEX_0F13 */
8479     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8480   },
8481   {
8482     /* MOD_VEX_0F16_PREFIX_0 */
8483     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8484     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8485   },
8486   {
8487     /* MOD_VEX_0F16_PREFIX_2 */
8488     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8489   },
8490   {
8491     /* MOD_VEX_0F17 */
8492     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8493   },
8494   {
8495     /* MOD_VEX_0F2B */
8496     { "%XEvmovntpX",    { Mx, XM }, PREFIX_OPCODE },
8497   },
8498   {
8499     /* MOD_VEX_0F41_L_1 */
8500     { Bad_Opcode },
8501     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8502   },
8503   {
8504     /* MOD_VEX_0F42_L_1 */
8505     { Bad_Opcode },
8506     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8507   },
8508   {
8509     /* MOD_VEX_0F44_L_0 */
8510     { Bad_Opcode },
8511     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8512   },
8513   {
8514     /* MOD_VEX_0F45_L_1 */
8515     { Bad_Opcode },
8516     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8517   },
8518   {
8519     /* MOD_VEX_0F46_L_1 */
8520     { Bad_Opcode },
8521     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8522   },
8523   {
8524     /* MOD_VEX_0F47_L_1 */
8525     { Bad_Opcode },
8526     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8527   },
8528   {
8529     /* MOD_VEX_0F4A_L_1 */
8530     { Bad_Opcode },
8531     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8532   },
8533   {
8534     /* MOD_VEX_0F4B_L_1 */
8535     { Bad_Opcode },
8536     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8537   },
8538   {
8539     /* MOD_VEX_0F50 */
8540     { Bad_Opcode },
8541     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8542   },
8543   {
8544     /* MOD_VEX_0F71 */
8545     { Bad_Opcode },
8546     { REG_TABLE (REG_VEX_0F71_M_0) },
8547   },
8548   {
8549     /* MOD_VEX_0F72 */
8550     { Bad_Opcode },
8551     { REG_TABLE (REG_VEX_0F72_M_0) },
8552   },
8553   {
8554     /* MOD_VEX_0F73 */
8555     { Bad_Opcode },
8556     { REG_TABLE (REG_VEX_0F73_M_0) },
8557   },
8558   {
8559     /* MOD_VEX_0F91_L_0 */
8560     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8561   },
8562   {
8563     /* MOD_VEX_0F92_L_0 */
8564     { Bad_Opcode },
8565     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8566   },
8567   {
8568     /* MOD_VEX_0F93_L_0 */
8569     { Bad_Opcode },
8570     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8571   },
8572   {
8573     /* MOD_VEX_0F98_L_0 */
8574     { Bad_Opcode },
8575     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8576   },
8577   {
8578     /* MOD_VEX_0F99_L_0 */
8579     { Bad_Opcode },
8580     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8581   },
8582   {
8583     /* MOD_VEX_0FAE_REG_2 */
8584     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8585   },
8586   {
8587     /* MOD_VEX_0FAE_REG_3 */
8588     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8589   },
8590   {
8591     /* MOD_VEX_0FD7 */
8592     { Bad_Opcode },
8593     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8594   },
8595   {
8596     /* MOD_VEX_0FE7 */
8597     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8598   },
8599   {
8600     /* MOD_VEX_0FF0_PREFIX_3 */
8601     { "vlddqu",         { XM, M }, 0 },
8602   },
8603   {
8604     /* MOD_VEX_0F381A */
8605     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8606   },
8607   {
8608     /* MOD_VEX_0F382A */
8609     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8610   },
8611   {
8612     /* MOD_VEX_0F382C */
8613     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8614   },
8615   {
8616     /* MOD_VEX_0F382D */
8617     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8618   },
8619   {
8620     /* MOD_VEX_0F382E */
8621     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8622   },
8623   {
8624     /* MOD_VEX_0F382F */
8625     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8626   },
8627   {
8628     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8629     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8630     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8631   },
8632   {
8633     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8634     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8635   },
8636   {
8637     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8638     { Bad_Opcode },
8639     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8640   },
8641   {
8642     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8643     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8644   },
8645   {
8646     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8647     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8648   },
8649   {
8650     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8651     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8652   },
8653   {
8654     /* MOD_VEX_0F385A */
8655     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8656   },
8657   {
8658     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8659     { Bad_Opcode },
8660     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8661   },
8662   {
8663     /* MOD_VEX_0F385C_X86_64_P_3_W_0 */
8664     { Bad_Opcode },
8665     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0) },
8666   },
8667   {
8668     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8669     { Bad_Opcode },
8670     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8671   },
8672   {
8673     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8674     { Bad_Opcode },
8675     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8676   },
8677   {
8678     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8679     { Bad_Opcode },
8680     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8681   },
8682   {
8683     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8684     { Bad_Opcode },
8685     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8686   },
8687   {
8688     /* MOD_VEX_0F388C */
8689     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8690   },
8691   {
8692     /* MOD_VEX_0F388E */
8693     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8694   },
8695   {
8696     /* MOD_VEX_0F3A30_L_0 */
8697     { Bad_Opcode },
8698     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8699   },
8700   {
8701     /* MOD_VEX_0F3A31_L_0 */
8702     { Bad_Opcode },
8703     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8704   },
8705   {
8706     /* MOD_VEX_0F3A32_L_0 */
8707     { Bad_Opcode },
8708     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8709   },
8710   {
8711     /* MOD_VEX_0F3A33_L_0 */
8712     { Bad_Opcode },
8713     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8714   },
8715   {
8716     /* MOD_XOP_09_12 */
8717     { Bad_Opcode },
8718     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8719   },
8720
8721 #include "i386-dis-evex-mod.h"
8722 };
8723
8724 static const struct dis386 rm_table[][8] = {
8725   {
8726     /* RM_C6_REG_7 */
8727     { "xabort",         { Skip_MODRM, Ib }, 0 },
8728   },
8729   {
8730     /* RM_C7_REG_7 */
8731     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8732   },
8733   {
8734     /* RM_0F01_REG_0 */
8735     { "enclv",          { Skip_MODRM }, 0 },
8736     { "vmcall",         { Skip_MODRM }, 0 },
8737     { "vmlaunch",       { Skip_MODRM }, 0 },
8738     { "vmresume",       { Skip_MODRM }, 0 },
8739     { "vmxoff",         { Skip_MODRM }, 0 },
8740     { "pconfig",        { Skip_MODRM }, 0 },
8741     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8742   },
8743   {
8744     /* RM_0F01_REG_1 */
8745     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8746     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8747     { "clac",           { Skip_MODRM }, 0 },
8748     { "stac",           { Skip_MODRM }, 0 },
8749     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8750     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8751     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8752     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8753   },
8754   {
8755     /* RM_0F01_REG_2 */
8756     { "xgetbv",         { Skip_MODRM }, 0 },
8757     { "xsetbv",         { Skip_MODRM }, 0 },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { "vmfunc",         { Skip_MODRM }, 0 },
8761     { "xend",           { Skip_MODRM }, 0 },
8762     { "xtest",          { Skip_MODRM }, 0 },
8763     { "enclu",          { Skip_MODRM }, 0 },
8764   },
8765   {
8766     /* RM_0F01_REG_3 */
8767     { "vmrun",          { Skip_MODRM }, 0 },
8768     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8769     { "vmload",         { Skip_MODRM }, 0 },
8770     { "vmsave",         { Skip_MODRM }, 0 },
8771     { "stgi",           { Skip_MODRM }, 0 },
8772     { "clgi",           { Skip_MODRM }, 0 },
8773     { "skinit",         { Skip_MODRM }, 0 },
8774     { "invlpga",        { Skip_MODRM }, 0 },
8775   },
8776   {
8777     /* RM_0F01_REG_5_MOD_3 */
8778     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8779     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8780     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8781     { Bad_Opcode },
8782     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8783     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8784     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8785     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8786   },
8787   {
8788     /* RM_0F01_REG_7_MOD_3 */
8789     { "swapgs",         { Skip_MODRM }, 0  },
8790     { "rdtscp",         { Skip_MODRM }, 0  },
8791     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8792     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8793     { "clzero",         { Skip_MODRM }, 0  },
8794     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8795     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8796     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8797   },
8798   {
8799     /* RM_0F1E_P_1_MOD_3_REG_7 */
8800     { "nopQ",           { Ev }, PREFIX_IGNORED },
8801     { "nopQ",           { Ev }, PREFIX_IGNORED },
8802     { "endbr64",        { Skip_MODRM }, 0 },
8803     { "endbr32",        { Skip_MODRM }, 0 },
8804     { "nopQ",           { Ev }, PREFIX_IGNORED },
8805     { "nopQ",           { Ev }, PREFIX_IGNORED },
8806     { "nopQ",           { Ev }, PREFIX_IGNORED },
8807     { "nopQ",           { Ev }, PREFIX_IGNORED },
8808   },
8809   {
8810     /* RM_0FAE_REG_6_MOD_3 */
8811     { "mfence",         { Skip_MODRM }, 0 },
8812   },
8813   {
8814     /* RM_0FAE_REG_7_MOD_3 */
8815     { "sfence",         { Skip_MODRM }, 0 },
8816   },
8817   {
8818     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8819     { "hreset",         { Skip_MODRM, Ib }, 0 },
8820   },
8821   {
8822     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8823     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8824   },
8825 };
8826
8827 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8828
8829 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8830    in conflict with actual prefix opcodes.  */
8831 #define REP_PREFIX      0x01
8832 #define XACQUIRE_PREFIX 0x02
8833 #define XRELEASE_PREFIX 0x03
8834 #define BND_PREFIX      0x04
8835 #define NOTRACK_PREFIX  0x05
8836
8837 static int
8838 ckprefix (instr_info *ins)
8839 {
8840   int newrex, i, length;
8841
8842   i = 0;
8843   length = 0;
8844   /* The maximum instruction length is 15bytes.  */
8845   while (length < MAX_CODE_LENGTH - 1)
8846     {
8847       FETCH_DATA (ins->info, ins->codep + 1);
8848       newrex = 0;
8849       switch (*ins->codep)
8850         {
8851         /* REX prefixes family.  */
8852         case 0x40:
8853         case 0x41:
8854         case 0x42:
8855         case 0x43:
8856         case 0x44:
8857         case 0x45:
8858         case 0x46:
8859         case 0x47:
8860         case 0x48:
8861         case 0x49:
8862         case 0x4a:
8863         case 0x4b:
8864         case 0x4c:
8865         case 0x4d:
8866         case 0x4e:
8867         case 0x4f:
8868           if (ins->address_mode == mode_64bit)
8869             newrex = *ins->codep;
8870           else
8871             return 1;
8872           ins->last_rex_prefix = i;
8873           break;
8874         case 0xf3:
8875           ins->prefixes |= PREFIX_REPZ;
8876           ins->last_repz_prefix = i;
8877           break;
8878         case 0xf2:
8879           ins->prefixes |= PREFIX_REPNZ;
8880           ins->last_repnz_prefix = i;
8881           break;
8882         case 0xf0:
8883           ins->prefixes |= PREFIX_LOCK;
8884           ins->last_lock_prefix = i;
8885           break;
8886         case 0x2e:
8887           ins->prefixes |= PREFIX_CS;
8888           ins->last_seg_prefix = i;
8889           if (ins->address_mode != mode_64bit)
8890             ins->active_seg_prefix = PREFIX_CS;
8891           break;
8892         case 0x36:
8893           ins->prefixes |= PREFIX_SS;
8894           ins->last_seg_prefix = i;
8895           if (ins->address_mode != mode_64bit)
8896             ins->active_seg_prefix = PREFIX_SS;
8897           break;
8898         case 0x3e:
8899           ins->prefixes |= PREFIX_DS;
8900           ins->last_seg_prefix = i;
8901           if (ins->address_mode != mode_64bit)
8902             ins->active_seg_prefix = PREFIX_DS;
8903           break;
8904         case 0x26:
8905           ins->prefixes |= PREFIX_ES;
8906           ins->last_seg_prefix = i;
8907           if (ins->address_mode != mode_64bit)
8908             ins->active_seg_prefix = PREFIX_ES;
8909           break;
8910         case 0x64:
8911           ins->prefixes |= PREFIX_FS;
8912           ins->last_seg_prefix = i;
8913           ins->active_seg_prefix = PREFIX_FS;
8914           break;
8915         case 0x65:
8916           ins->prefixes |= PREFIX_GS;
8917           ins->last_seg_prefix = i;
8918           ins->active_seg_prefix = PREFIX_GS;
8919           break;
8920         case 0x66:
8921           ins->prefixes |= PREFIX_DATA;
8922           ins->last_data_prefix = i;
8923           break;
8924         case 0x67:
8925           ins->prefixes |= PREFIX_ADDR;
8926           ins->last_addr_prefix = i;
8927           break;
8928         case FWAIT_OPCODE:
8929           /* fwait is really an instruction.  If there are prefixes
8930              before the fwait, they belong to the fwait, *not* to the
8931              following instruction.  */
8932           ins->fwait_prefix = i;
8933           if (ins->prefixes || ins->rex)
8934             {
8935               ins->prefixes |= PREFIX_FWAIT;
8936               ins->codep++;
8937               /* This ensures that the previous REX prefixes are noticed
8938                  as unused prefixes, as in the return case below.  */
8939               ins->rex_used = ins->rex;
8940               return 1;
8941             }
8942           ins->prefixes = PREFIX_FWAIT;
8943           break;
8944         default:
8945           return 1;
8946         }
8947       /* Rex is ignored when followed by another prefix.  */
8948       if (ins->rex)
8949         {
8950           ins->rex_used = ins->rex;
8951           return 1;
8952         }
8953       if (*ins->codep != FWAIT_OPCODE)
8954         ins->all_prefixes[i++] = *ins->codep;
8955       ins->rex = newrex;
8956       ins->codep++;
8957       length++;
8958     }
8959   return 0;
8960 }
8961
8962 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8963    prefix byte.  */
8964
8965 static const char *
8966 prefix_name (instr_info *ins, int pref, int sizeflag)
8967 {
8968   static const char *rexes [16] =
8969     {
8970       "rex",            /* 0x40 */
8971       "rex.B",          /* 0x41 */
8972       "rex.X",          /* 0x42 */
8973       "rex.XB",         /* 0x43 */
8974       "rex.R",          /* 0x44 */
8975       "rex.RB",         /* 0x45 */
8976       "rex.RX",         /* 0x46 */
8977       "rex.RXB",        /* 0x47 */
8978       "rex.W",          /* 0x48 */
8979       "rex.WB",         /* 0x49 */
8980       "rex.WX",         /* 0x4a */
8981       "rex.WXB",        /* 0x4b */
8982       "rex.WR",         /* 0x4c */
8983       "rex.WRB",        /* 0x4d */
8984       "rex.WRX",        /* 0x4e */
8985       "rex.WRXB",       /* 0x4f */
8986     };
8987
8988   switch (pref)
8989     {
8990     /* REX prefixes family.  */
8991     case 0x40:
8992     case 0x41:
8993     case 0x42:
8994     case 0x43:
8995     case 0x44:
8996     case 0x45:
8997     case 0x46:
8998     case 0x47:
8999     case 0x48:
9000     case 0x49:
9001     case 0x4a:
9002     case 0x4b:
9003     case 0x4c:
9004     case 0x4d:
9005     case 0x4e:
9006     case 0x4f:
9007       return rexes [pref - 0x40];
9008     case 0xf3:
9009       return "repz";
9010     case 0xf2:
9011       return "repnz";
9012     case 0xf0:
9013       return "lock";
9014     case 0x2e:
9015       return "cs";
9016     case 0x36:
9017       return "ss";
9018     case 0x3e:
9019       return "ds";
9020     case 0x26:
9021       return "es";
9022     case 0x64:
9023       return "fs";
9024     case 0x65:
9025       return "gs";
9026     case 0x66:
9027       return (sizeflag & DFLAG) ? "data16" : "data32";
9028     case 0x67:
9029       if (ins->address_mode == mode_64bit)
9030         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9031       else
9032         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9033     case FWAIT_OPCODE:
9034       return "fwait";
9035     case REP_PREFIX:
9036       return "rep";
9037     case XACQUIRE_PREFIX:
9038       return "xacquire";
9039     case XRELEASE_PREFIX:
9040       return "xrelease";
9041     case BND_PREFIX:
9042       return "bnd";
9043     case NOTRACK_PREFIX:
9044       return "notrack";
9045     default:
9046       return NULL;
9047     }
9048 }
9049
9050 void
9051 print_i386_disassembler_options (FILE *stream)
9052 {
9053   fprintf (stream, _("\n\
9054 The following i386/x86-64 specific disassembler options are supported for use\n\
9055 with the -M switch (multiple options should be separated by commas):\n"));
9056
9057   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9058   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9059   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9060   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9061   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9062   fprintf (stream, _("  att-mnemonic\n"
9063                      "              Display instruction in AT&T mnemonic\n"));
9064   fprintf (stream, _("  intel-mnemonic\n"
9065                      "              Display instruction in Intel mnemonic\n"));
9066   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9067   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9068   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9069   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9070   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9071   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9072   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9073   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9074 }
9075
9076 /* Bad opcode.  */
9077 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9078
9079 /* Get a pointer to struct dis386 with a valid name.  */
9080
9081 static const struct dis386 *
9082 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
9083 {
9084   int vindex, vex_table_index;
9085
9086   if (dp->name != NULL)
9087     return dp;
9088
9089   switch (dp->op[0].bytemode)
9090     {
9091     case USE_REG_TABLE:
9092       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
9093       break;
9094
9095     case USE_MOD_TABLE:
9096       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
9097       dp = &mod_table[dp->op[1].bytemode][vindex];
9098       break;
9099
9100     case USE_RM_TABLE:
9101       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
9102       break;
9103
9104     case USE_PREFIX_TABLE:
9105       if (ins->need_vex)
9106         {
9107           /* The prefix in VEX is implicit.  */
9108           switch (ins->vex.prefix)
9109             {
9110             case 0:
9111               vindex = 0;
9112               break;
9113             case REPE_PREFIX_OPCODE:
9114               vindex = 1;
9115               break;
9116             case DATA_PREFIX_OPCODE:
9117               vindex = 2;
9118               break;
9119             case REPNE_PREFIX_OPCODE:
9120               vindex = 3;
9121               break;
9122             default:
9123               abort ();
9124               break;
9125             }
9126         }
9127       else
9128         {
9129           int last_prefix = -1;
9130           int prefix = 0;
9131           vindex = 0;
9132           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9133              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9134              last one wins.  */
9135           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9136             {
9137               if (ins->last_repz_prefix > ins->last_repnz_prefix)
9138                 {
9139                   vindex = 1;
9140                   prefix = PREFIX_REPZ;
9141                   last_prefix = ins->last_repz_prefix;
9142                 }
9143               else
9144                 {
9145                   vindex = 3;
9146                   prefix = PREFIX_REPNZ;
9147                   last_prefix = ins->last_repnz_prefix;
9148                 }
9149
9150               /* Check if prefix should be ignored.  */
9151               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9152                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9153                    & prefix) != 0
9154                   && !prefix_table[dp->op[1].bytemode][vindex].name)
9155                 vindex = 0;
9156             }
9157
9158           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
9159             {
9160               vindex = 2;
9161               prefix = PREFIX_DATA;
9162               last_prefix = ins->last_data_prefix;
9163             }
9164
9165           if (vindex != 0)
9166             {
9167               ins->used_prefixes |= prefix;
9168               ins->all_prefixes[last_prefix] = 0;
9169             }
9170         }
9171       dp = &prefix_table[dp->op[1].bytemode][vindex];
9172       break;
9173
9174     case USE_X86_64_TABLE:
9175       vindex = ins->address_mode == mode_64bit ? 1 : 0;
9176       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9177       break;
9178
9179     case USE_3BYTE_TABLE:
9180       FETCH_DATA (ins->info, ins->codep + 2);
9181       vindex = *ins->codep++;
9182       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9183       ins->end_codep = ins->codep;
9184       ins->modrm.mod = (*ins->codep >> 6) & 3;
9185       ins->modrm.reg = (*ins->codep >> 3) & 7;
9186       ins->modrm.rm = *ins->codep & 7;
9187       break;
9188
9189     case USE_VEX_LEN_TABLE:
9190       if (!ins->need_vex)
9191         abort ();
9192
9193       switch (ins->vex.length)
9194         {
9195         case 128:
9196           vindex = 0;
9197           break;
9198         case 512:
9199           /* This allows re-using in particular table entries where only
9200              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9201           if (ins->vex.evex)
9202             {
9203         case 256:
9204               vindex = 1;
9205               break;
9206             }
9207         /* Fall through.  */
9208         default:
9209           abort ();
9210           break;
9211         }
9212
9213       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9214       break;
9215
9216     case USE_EVEX_LEN_TABLE:
9217       if (!ins->vex.evex)
9218         abort ();
9219
9220       switch (ins->vex.length)
9221         {
9222         case 128:
9223           vindex = 0;
9224           break;
9225         case 256:
9226           vindex = 1;
9227           break;
9228         case 512:
9229           vindex = 2;
9230           break;
9231         default:
9232           abort ();
9233           break;
9234         }
9235
9236       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9237       break;
9238
9239     case USE_XOP_8F_TABLE:
9240       FETCH_DATA (ins->info, ins->codep + 3);
9241       ins->rex = ~(*ins->codep >> 5) & 0x7;
9242
9243       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9244       switch ((*ins->codep & 0x1f))
9245         {
9246         default:
9247           dp = &bad_opcode;
9248           return dp;
9249         case 0x8:
9250           vex_table_index = XOP_08;
9251           break;
9252         case 0x9:
9253           vex_table_index = XOP_09;
9254           break;
9255         case 0xa:
9256           vex_table_index = XOP_0A;
9257           break;
9258         }
9259       ins->codep++;
9260       ins->vex.w = *ins->codep & 0x80;
9261       if (ins->vex.w && ins->address_mode == mode_64bit)
9262         ins->rex |= REX_W;
9263
9264       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9265       if (ins->address_mode != mode_64bit)
9266         {
9267           /* In 16/32-bit mode REX_B is silently ignored.  */
9268           ins->rex &= ~REX_B;
9269         }
9270
9271       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9272       switch ((*ins->codep & 0x3))
9273         {
9274         case 0:
9275           break;
9276         case 1:
9277           ins->vex.prefix = DATA_PREFIX_OPCODE;
9278           break;
9279         case 2:
9280           ins->vex.prefix = REPE_PREFIX_OPCODE;
9281           break;
9282         case 3:
9283           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9284           break;
9285         }
9286       ins->need_vex = true;
9287       ins->codep++;
9288       vindex = *ins->codep++;
9289       dp = &xop_table[vex_table_index][vindex];
9290
9291       ins->end_codep = ins->codep;
9292       FETCH_DATA (ins->info, ins->codep + 1);
9293       ins->modrm.mod = (*ins->codep >> 6) & 3;
9294       ins->modrm.reg = (*ins->codep >> 3) & 7;
9295       ins->modrm.rm = *ins->codep & 7;
9296
9297       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9298          having to decode the bits for every otherwise valid encoding.  */
9299       if (ins->vex.prefix)
9300         return &bad_opcode;
9301       break;
9302
9303     case USE_VEX_C4_TABLE:
9304       /* VEX prefix.  */
9305       FETCH_DATA (ins->info, ins->codep + 3);
9306       ins->rex = ~(*ins->codep >> 5) & 0x7;
9307       switch ((*ins->codep & 0x1f))
9308         {
9309         default:
9310           dp = &bad_opcode;
9311           return dp;
9312         case 0x1:
9313           vex_table_index = VEX_0F;
9314           break;
9315         case 0x2:
9316           vex_table_index = VEX_0F38;
9317           break;
9318         case 0x3:
9319           vex_table_index = VEX_0F3A;
9320           break;
9321         }
9322       ins->codep++;
9323       ins->vex.w = *ins->codep & 0x80;
9324       if (ins->address_mode == mode_64bit)
9325         {
9326           if (ins->vex.w)
9327             ins->rex |= REX_W;
9328         }
9329       else
9330         {
9331           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9332              is ignored, other REX bits are 0 and the highest bit in
9333              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9334           ins->rex = 0;
9335         }
9336       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9337       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9338       switch ((*ins->codep & 0x3))
9339         {
9340         case 0:
9341           break;
9342         case 1:
9343           ins->vex.prefix = DATA_PREFIX_OPCODE;
9344           break;
9345         case 2:
9346           ins->vex.prefix = REPE_PREFIX_OPCODE;
9347           break;
9348         case 3:
9349           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9350           break;
9351         }
9352       ins->need_vex = true;
9353       ins->codep++;
9354       vindex = *ins->codep++;
9355       dp = &vex_table[vex_table_index][vindex];
9356       ins->end_codep = ins->codep;
9357       /* There is no MODRM byte for VEX0F 77.  */
9358       if (vex_table_index != VEX_0F || vindex != 0x77)
9359         {
9360           FETCH_DATA (ins->info, ins->codep + 1);
9361           ins->modrm.mod = (*ins->codep >> 6) & 3;
9362           ins->modrm.reg = (*ins->codep >> 3) & 7;
9363           ins->modrm.rm = *ins->codep & 7;
9364         }
9365       break;
9366
9367     case USE_VEX_C5_TABLE:
9368       /* VEX prefix.  */
9369       FETCH_DATA (ins->info, ins->codep + 2);
9370       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9371
9372       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9373          VEX.vvvv is 1.  */
9374       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9375       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9376       switch ((*ins->codep & 0x3))
9377         {
9378         case 0:
9379           break;
9380         case 1:
9381           ins->vex.prefix = DATA_PREFIX_OPCODE;
9382           break;
9383         case 2:
9384           ins->vex.prefix = REPE_PREFIX_OPCODE;
9385           break;
9386         case 3:
9387           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9388           break;
9389         }
9390       ins->need_vex = true;
9391       ins->codep++;
9392       vindex = *ins->codep++;
9393       dp = &vex_table[dp->op[1].bytemode][vindex];
9394       ins->end_codep = ins->codep;
9395       /* There is no MODRM byte for VEX 77.  */
9396       if (vindex != 0x77)
9397         {
9398           FETCH_DATA (ins->info, ins->codep + 1);
9399           ins->modrm.mod = (*ins->codep >> 6) & 3;
9400           ins->modrm.reg = (*ins->codep >> 3) & 7;
9401           ins->modrm.rm = *ins->codep & 7;
9402         }
9403       break;
9404
9405     case USE_VEX_W_TABLE:
9406       if (!ins->need_vex)
9407         abort ();
9408
9409       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9410       break;
9411
9412     case USE_EVEX_TABLE:
9413       ins->two_source_ops = false;
9414       /* EVEX prefix.  */
9415       ins->vex.evex = true;
9416       FETCH_DATA (ins->info, ins->codep + 4);
9417       /* The first byte after 0x62.  */
9418       ins->rex = ~(*ins->codep >> 5) & 0x7;
9419       ins->vex.r = *ins->codep & 0x10;
9420       switch ((*ins->codep & 0xf))
9421         {
9422         default:
9423           return &bad_opcode;
9424         case 0x1:
9425           vex_table_index = EVEX_0F;
9426           break;
9427         case 0x2:
9428           vex_table_index = EVEX_0F38;
9429           break;
9430         case 0x3:
9431           vex_table_index = EVEX_0F3A;
9432           break;
9433         case 0x5:
9434           vex_table_index = EVEX_MAP5;
9435           break;
9436         case 0x6:
9437           vex_table_index = EVEX_MAP6;
9438           break;
9439         }
9440
9441       /* The second byte after 0x62.  */
9442       ins->codep++;
9443       ins->vex.w = *ins->codep & 0x80;
9444       if (ins->vex.w && ins->address_mode == mode_64bit)
9445         ins->rex |= REX_W;
9446
9447       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9448
9449       /* The U bit.  */
9450       if (!(*ins->codep & 0x4))
9451         return &bad_opcode;
9452
9453       switch ((*ins->codep & 0x3))
9454         {
9455         case 0:
9456           break;
9457         case 1:
9458           ins->vex.prefix = DATA_PREFIX_OPCODE;
9459           break;
9460         case 2:
9461           ins->vex.prefix = REPE_PREFIX_OPCODE;
9462           break;
9463         case 3:
9464           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9465           break;
9466         }
9467
9468       /* The third byte after 0x62.  */
9469       ins->codep++;
9470
9471       /* Remember the static rounding bits.  */
9472       ins->vex.ll = (*ins->codep >> 5) & 3;
9473       ins->vex.b = *ins->codep & 0x10;
9474
9475       ins->vex.v = *ins->codep & 0x8;
9476       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9477       ins->vex.zeroing = *ins->codep & 0x80;
9478
9479       if (ins->address_mode != mode_64bit)
9480         {
9481           /* In 16/32-bit mode silently ignore following bits.  */
9482           ins->rex &= ~REX_B;
9483           ins->vex.r = true;
9484         }
9485
9486       ins->need_vex = true;
9487       ins->codep++;
9488       vindex = *ins->codep++;
9489       dp = &evex_table[vex_table_index][vindex];
9490       ins->end_codep = ins->codep;
9491       FETCH_DATA (ins->info, ins->codep + 1);
9492       ins->modrm.mod = (*ins->codep >> 6) & 3;
9493       ins->modrm.reg = (*ins->codep >> 3) & 7;
9494       ins->modrm.rm = *ins->codep & 7;
9495
9496       /* Set vector length.  */
9497       if (ins->modrm.mod == 3 && ins->vex.b)
9498         ins->vex.length = 512;
9499       else
9500         {
9501           switch (ins->vex.ll)
9502             {
9503             case 0x0:
9504               ins->vex.length = 128;
9505               break;
9506             case 0x1:
9507               ins->vex.length = 256;
9508               break;
9509             case 0x2:
9510               ins->vex.length = 512;
9511               break;
9512             default:
9513               return &bad_opcode;
9514             }
9515         }
9516       break;
9517
9518     case 0:
9519       dp = &bad_opcode;
9520       break;
9521
9522     default:
9523       abort ();
9524     }
9525
9526   if (dp->name != NULL)
9527     return dp;
9528   else
9529     return get_valid_dis386 (dp, ins);
9530 }
9531
9532 static void
9533 get_sib (instr_info *ins, int sizeflag)
9534 {
9535   /* If modrm.mod == 3, operand must be register.  */
9536   if (ins->need_modrm
9537       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9538       && ins->modrm.mod != 3
9539       && ins->modrm.rm == 4)
9540     {
9541       FETCH_DATA (ins->info, ins->codep + 2);
9542       ins->sib.index = (ins->codep[1] >> 3) & 7;
9543       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9544       ins->sib.base = ins->codep[1] & 7;
9545       ins->has_sib = true;
9546     }
9547   else
9548     ins->has_sib = false;
9549 }
9550
9551 /* Like oappend (below), but S is a string starting with '%'.  In
9552    Intel syntax, the '%' is elided.  */
9553
9554 static void
9555 oappend_register (instr_info *ins, const char *s)
9556 {
9557   oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9558 }
9559
9560 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9561    STYLE is the default style to use in the fprintf_styled_func calls,
9562    however, FMT might include embedded style markers (see oappend_style),
9563    these embedded markers are not printed, but instead change the style
9564    used in the next fprintf_styled_func call.  */
9565
9566 static void ATTRIBUTE_PRINTF_3
9567 i386_dis_printf (instr_info *ins, enum disassembler_style style,
9568                  const char *fmt, ...)
9569 {
9570   va_list ap;
9571   enum disassembler_style curr_style = style;
9572   const char *start, *curr;
9573   char staging_area[40];
9574
9575   va_start (ap, fmt);
9576   /* In particular print_insn()'s processing of op_txt[] can hand rather long
9577      strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9578      with the staging area.  */
9579   if (strcmp (fmt, "%s"))
9580     {
9581       int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9582
9583       va_end (ap);
9584
9585       if (res < 0)
9586         return;
9587
9588       if ((size_t) res >= sizeof (staging_area))
9589         abort ();
9590
9591       start = curr = staging_area;
9592     }
9593   else
9594     {
9595       start = curr = va_arg (ap, const char *);
9596       va_end (ap);
9597     }
9598
9599   do
9600     {
9601       if (*curr == '\0'
9602           || (*curr == STYLE_MARKER_CHAR
9603               && ISXDIGIT (*(curr + 1))
9604               && *(curr + 2) == STYLE_MARKER_CHAR))
9605         {
9606           /* Output content between our START position and CURR.  */
9607           int len = curr - start;
9608           int n = (*ins->info->fprintf_styled_func) (ins->info->stream,
9609                                                      curr_style,
9610                                                      "%.*s", len, start);
9611           if (n < 0)
9612             break;
9613
9614           if (*curr == '\0')
9615             break;
9616
9617           /* Skip over the initial STYLE_MARKER_CHAR.  */
9618           ++curr;
9619
9620           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9621              is possible, that if the input is corrupted in some way, that
9622              we might set CURR_STYLE to an invalid value.  Don't worry
9623              though, we check for this situation.  */
9624           if (*curr >= '0' && *curr <= '9')
9625             curr_style = (enum disassembler_style) (*curr - '0');
9626           else if (*curr >= 'a' && *curr <= 'f')
9627             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9628           else
9629             curr_style = dis_style_text;
9630
9631           /* Check for an invalid style having been selected.  This should
9632              never happen, but it doesn't hurt to be a little paranoid.  */
9633           if (curr_style > dis_style_comment_start)
9634             curr_style = dis_style_text;
9635
9636           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9637           curr += 2;
9638
9639           /* Reset the START to after the style marker.  */
9640           start = curr;
9641         }
9642       else
9643         ++curr;
9644     }
9645   while (true);
9646 }
9647
9648 static int
9649 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9650 {
9651   const struct dis386 *dp;
9652   int i;
9653   char *op_txt[MAX_OPERANDS];
9654   int needcomma;
9655   bool intel_swap_2_3;
9656   int sizeflag, orig_sizeflag;
9657   const char *p;
9658   struct dis_private priv;
9659   int prefix_length;
9660   int op_count;
9661   instr_info ins = {
9662     .info = info,
9663     .intel_syntax = intel_syntax >= 0
9664                     ? intel_syntax
9665                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9666     .intel_mnemonic = !SYSV386_COMPAT,
9667     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9668     .start_pc = pc,
9669     .start_codep = priv.the_buffer,
9670     .codep = priv.the_buffer,
9671     .obufp = ins.obuf,
9672     .last_lock_prefix = -1,
9673     .last_repz_prefix = -1,
9674     .last_repnz_prefix = -1,
9675     .last_data_prefix = -1,
9676     .last_addr_prefix = -1,
9677     .last_rex_prefix = -1,
9678     .last_seg_prefix = -1,
9679     .fwait_prefix = -1,
9680   };
9681   char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9682
9683   priv.orig_sizeflag = AFLAG | DFLAG;
9684   if ((info->mach & bfd_mach_i386_i386) != 0)
9685     ins.address_mode = mode_32bit;
9686   else if (info->mach == bfd_mach_i386_i8086)
9687     {
9688       ins.address_mode = mode_16bit;
9689       priv.orig_sizeflag = 0;
9690     }
9691   else
9692     ins.address_mode = mode_64bit;
9693
9694   for (p = info->disassembler_options; p != NULL;)
9695     {
9696       if (startswith (p, "amd64"))
9697         ins.isa64 = amd64;
9698       else if (startswith (p, "intel64"))
9699         ins.isa64 = intel64;
9700       else if (startswith (p, "x86-64"))
9701         {
9702           ins.address_mode = mode_64bit;
9703           priv.orig_sizeflag |= AFLAG | DFLAG;
9704         }
9705       else if (startswith (p, "i386"))
9706         {
9707           ins.address_mode = mode_32bit;
9708           priv.orig_sizeflag |= AFLAG | DFLAG;
9709         }
9710       else if (startswith (p, "i8086"))
9711         {
9712           ins.address_mode = mode_16bit;
9713           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9714         }
9715       else if (startswith (p, "intel"))
9716         {
9717           ins.intel_syntax = 1;
9718           if (startswith (p + 5, "-mnemonic"))
9719             ins.intel_mnemonic = true;
9720         }
9721       else if (startswith (p, "att"))
9722         {
9723           ins.intel_syntax = 0;
9724           if (startswith (p + 3, "-mnemonic"))
9725             ins.intel_mnemonic = false;
9726         }
9727       else if (startswith (p, "addr"))
9728         {
9729           if (ins.address_mode == mode_64bit)
9730             {
9731               if (p[4] == '3' && p[5] == '2')
9732                 priv.orig_sizeflag &= ~AFLAG;
9733               else if (p[4] == '6' && p[5] == '4')
9734                 priv.orig_sizeflag |= AFLAG;
9735             }
9736           else
9737             {
9738               if (p[4] == '1' && p[5] == '6')
9739                 priv.orig_sizeflag &= ~AFLAG;
9740               else if (p[4] == '3' && p[5] == '2')
9741                 priv.orig_sizeflag |= AFLAG;
9742             }
9743         }
9744       else if (startswith (p, "data"))
9745         {
9746           if (p[4] == '1' && p[5] == '6')
9747             priv.orig_sizeflag &= ~DFLAG;
9748           else if (p[4] == '3' && p[5] == '2')
9749             priv.orig_sizeflag |= DFLAG;
9750         }
9751       else if (startswith (p, "suffix"))
9752         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9753
9754       p = strchr (p, ',');
9755       if (p != NULL)
9756         p++;
9757     }
9758
9759   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9760     {
9761       i386_dis_printf (&ins, dis_style_text, _("64-bit address is disabled"));
9762       return -1;
9763     }
9764
9765   if (ins.intel_syntax)
9766     {
9767       ins.open_char = '[';
9768       ins.close_char = ']';
9769       ins.separator_char = '+';
9770       ins.scale_char = '*';
9771     }
9772   else
9773     {
9774       ins.open_char = '(';
9775       ins.close_char =  ')';
9776       ins.separator_char = ',';
9777       ins.scale_char = ',';
9778     }
9779
9780   /* The output looks better if we put 7 bytes on a line, since that
9781      puts most long word instructions on a single line.  */
9782   info->bytes_per_line = 7;
9783
9784   info->private_data = &priv;
9785   priv.max_fetched = priv.the_buffer;
9786   priv.insn_start = pc;
9787
9788   for (i = 0; i < MAX_OPERANDS; ++i)
9789     {
9790       op_out[i][0] = 0;
9791       ins.op_out[i] = op_out[i];
9792     }
9793
9794   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9795     {
9796       /* Getting here means we tried for data but didn't get it.  That
9797          means we have an incomplete instruction of some sort.  Just
9798          print the first byte as a prefix or a .byte pseudo-op.  */
9799       if (ins.codep > priv.the_buffer)
9800         {
9801           const char *name = NULL;
9802
9803           if (ins.prefixes || ins.fwait_prefix >= 0 || (ins.rex & REX_OPCODE))
9804             name = prefix_name (&ins, priv.the_buffer[0], priv.orig_sizeflag);
9805           if (name != NULL)
9806             i386_dis_printf (&ins, dis_style_mnemonic, "%s", name);
9807           else
9808             {
9809               /* Just print the first byte as a .byte instruction.  */
9810               i386_dis_printf (&ins, dis_style_assembler_directive,
9811                                ".byte ");
9812               i386_dis_printf (&ins, dis_style_immediate, "0x%x",
9813                                (unsigned int) priv.the_buffer[0]);
9814             }
9815
9816           return 1;
9817         }
9818
9819       return -1;
9820     }
9821
9822   sizeflag = priv.orig_sizeflag;
9823
9824   if (!ckprefix (&ins) || ins.rex_used)
9825     {
9826       /* Too many prefixes or unused REX prefixes.  */
9827       for (i = 0;
9828            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9829            i++)
9830         i386_dis_printf (&ins, dis_style_mnemonic, "%s%s",
9831                          (i == 0 ? "" : " "),
9832                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9833       return i;
9834     }
9835
9836   ins.insn_codep = ins.codep;
9837
9838   FETCH_DATA (info, ins.codep + 1);
9839   ins.two_source_ops = (*ins.codep == 0x62) || (*ins.codep == 0xc8);
9840
9841   if (((ins.prefixes & PREFIX_FWAIT)
9842        && ((*ins.codep < 0xd8) || (*ins.codep > 0xdf))))
9843     {
9844       /* Handle ins.prefixes before fwait.  */
9845       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9846            i++)
9847         i386_dis_printf (&ins, dis_style_mnemonic, "%s ",
9848                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9849       i386_dis_printf (&ins, dis_style_mnemonic, "fwait");
9850       return i + 1;
9851     }
9852
9853   if (*ins.codep == 0x0f)
9854     {
9855       unsigned char threebyte;
9856
9857       ins.codep++;
9858       FETCH_DATA (info, ins.codep + 1);
9859       threebyte = *ins.codep;
9860       dp = &dis386_twobyte[threebyte];
9861       ins.need_modrm = twobyte_has_modrm[threebyte];
9862       ins.codep++;
9863     }
9864   else
9865     {
9866       dp = &dis386[*ins.codep];
9867       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9868       ins.codep++;
9869     }
9870
9871   /* Save sizeflag for printing the extra ins.prefixes later before updating
9872      it for mnemonic and operand processing.  The prefix names depend
9873      only on the address mode.  */
9874   orig_sizeflag = sizeflag;
9875   if (ins.prefixes & PREFIX_ADDR)
9876     sizeflag ^= AFLAG;
9877   if ((ins.prefixes & PREFIX_DATA))
9878     sizeflag ^= DFLAG;
9879
9880   ins.end_codep = ins.codep;
9881   if (ins.need_modrm)
9882     {
9883       FETCH_DATA (info, ins.codep + 1);
9884       ins.modrm.mod = (*ins.codep >> 6) & 3;
9885       ins.modrm.reg = (*ins.codep >> 3) & 7;
9886       ins.modrm.rm = *ins.codep & 7;
9887     }
9888
9889   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9890     {
9891       get_sib (&ins, sizeflag);
9892       dofloat (&ins, sizeflag);
9893     }
9894   else
9895     {
9896       dp = get_valid_dis386 (dp, &ins);
9897       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9898         {
9899           get_sib (&ins, sizeflag);
9900           for (i = 0; i < MAX_OPERANDS; ++i)
9901             {
9902               ins.obufp = ins.op_out[i];
9903               ins.op_ad = MAX_OPERANDS - 1 - i;
9904               if (dp->op[i].rtn)
9905                 (*dp->op[i].rtn) (&ins, dp->op[i].bytemode, sizeflag);
9906               /* For EVEX instruction after the last operand masking
9907                  should be printed.  */
9908               if (i == 0 && ins.vex.evex)
9909                 {
9910                   /* Don't print {%k0}.  */
9911                   if (ins.vex.mask_register_specifier)
9912                     {
9913                       const char *reg_name
9914                         = att_names_mask[ins.vex.mask_register_specifier];
9915
9916                       oappend (&ins, "{");
9917                       oappend_register (&ins, reg_name);
9918                       oappend (&ins, "}");
9919                     }
9920                   if (ins.vex.zeroing)
9921                     oappend (&ins, "{z}");
9922
9923                   /* S/G insns require a mask and don't allow
9924                      zeroing-masking.  */
9925                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9926                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9927                       && (ins.vex.mask_register_specifier == 0
9928                           || ins.vex.zeroing))
9929                     oappend (&ins, "/(bad)");
9930                 }
9931             }
9932
9933           /* Check whether rounding control was enabled for an insn not
9934              supporting it.  */
9935           if (ins.modrm.mod == 3 && ins.vex.b
9936               && !(ins.evex_used & EVEX_b_used))
9937             {
9938               for (i = 0; i < MAX_OPERANDS; ++i)
9939                 {
9940                   ins.obufp = ins.op_out[i];
9941                   if (*ins.obufp)
9942                     continue;
9943                   oappend (&ins, names_rounding[ins.vex.ll]);
9944                   oappend (&ins, "bad}");
9945                   break;
9946                 }
9947             }
9948         }
9949     }
9950
9951   /* Clear instruction information.  */
9952   info->insn_info_valid = 0;
9953   info->branch_delay_insns = 0;
9954   info->data_size = 0;
9955   info->insn_type = dis_noninsn;
9956   info->target = 0;
9957   info->target2 = 0;
9958
9959   /* Reset jump operation indicator.  */
9960   ins.op_is_jump = false;
9961   {
9962     int jump_detection = 0;
9963
9964     /* Extract flags.  */
9965     for (i = 0; i < MAX_OPERANDS; ++i)
9966       {
9967         if ((dp->op[i].rtn == OP_J)
9968             || (dp->op[i].rtn == OP_indirE))
9969           jump_detection |= 1;
9970         else if ((dp->op[i].rtn == BND_Fixup)
9971                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9972           jump_detection |= 2;
9973         else if ((dp->op[i].bytemode == cond_jump_mode)
9974                  || (dp->op[i].bytemode == loop_jcxz_mode))
9975           jump_detection |= 4;
9976       }
9977
9978     /* Determine if this is a jump or branch.  */
9979     if ((jump_detection & 0x3) == 0x3)
9980       {
9981         ins.op_is_jump = true;
9982         if (jump_detection & 0x4)
9983           info->insn_type = dis_condbranch;
9984         else
9985           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9986             ? dis_jsr : dis_branch;
9987       }
9988   }
9989
9990   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9991      are all 0s in inverted form.  */
9992   if (ins.need_vex && ins.vex.register_specifier != 0)
9993     {
9994       i386_dis_printf (&ins, dis_style_text, "(bad)");
9995       return ins.end_codep - priv.the_buffer;
9996     }
9997
9998   /* If EVEX.z is set, there must be an actual mask register in use.  */
9999   if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
10000     {
10001       i386_dis_printf (&ins, dis_style_text, "(bad)");
10002       return ins.end_codep - priv.the_buffer;
10003     }
10004
10005   switch (dp->prefix_requirement)
10006     {
10007     case PREFIX_DATA:
10008       /* If only the data prefix is marked as mandatory, its absence renders
10009          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
10010       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
10011         {
10012           i386_dis_printf (&ins, dis_style_text, "(bad)");
10013           return ins.end_codep - priv.the_buffer;
10014         }
10015       ins.used_prefixes |= PREFIX_DATA;
10016       /* Fall through.  */
10017     case PREFIX_OPCODE:
10018       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10019          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
10020          used by putop and MMX/SSE operand and may be overridden by the
10021          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10022          separately.  */
10023       if (((ins.need_vex
10024             ? ins.vex.prefix == REPE_PREFIX_OPCODE
10025               || ins.vex.prefix == REPNE_PREFIX_OPCODE
10026             : (ins.prefixes
10027                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10028            && (ins.used_prefixes
10029                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10030           || (((ins.need_vex
10031                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
10032                 : ((ins.prefixes
10033                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10034                    == PREFIX_DATA))
10035                && (ins.used_prefixes & PREFIX_DATA) == 0))
10036           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
10037               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
10038         {
10039           i386_dis_printf (&ins, dis_style_text, "(bad)");
10040           return ins.end_codep - priv.the_buffer;
10041         }
10042       break;
10043
10044     case PREFIX_IGNORED:
10045       /* Zap data size and rep prefixes from used_prefixes and reinstate their
10046          origins in all_prefixes.  */
10047       ins.used_prefixes &= ~PREFIX_OPCODE;
10048       if (ins.last_data_prefix >= 0)
10049         ins.all_prefixes[ins.last_data_prefix] = 0x66;
10050       if (ins.last_repz_prefix >= 0)
10051         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
10052       if (ins.last_repnz_prefix >= 0)
10053         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
10054       break;
10055     }
10056
10057   /* Check if the REX prefix is used.  */
10058   if ((ins.rex ^ ins.rex_used) == 0
10059       && !ins.need_vex && ins.last_rex_prefix >= 0)
10060     ins.all_prefixes[ins.last_rex_prefix] = 0;
10061
10062   /* Check if the SEG prefix is used.  */
10063   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10064                        | PREFIX_FS | PREFIX_GS)) != 0
10065       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
10066     ins.all_prefixes[ins.last_seg_prefix] = 0;
10067
10068   /* Check if the ADDR prefix is used.  */
10069   if ((ins.prefixes & PREFIX_ADDR) != 0
10070       && (ins.used_prefixes & PREFIX_ADDR) != 0)
10071     ins.all_prefixes[ins.last_addr_prefix] = 0;
10072
10073   /* Check if the DATA prefix is used.  */
10074   if ((ins.prefixes & PREFIX_DATA) != 0
10075       && (ins.used_prefixes & PREFIX_DATA) != 0
10076       && !ins.need_vex)
10077     ins.all_prefixes[ins.last_data_prefix] = 0;
10078
10079   /* Print the extra ins.prefixes.  */
10080   prefix_length = 0;
10081   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
10082     if (ins.all_prefixes[i])
10083       {
10084         const char *name;
10085         name = prefix_name (&ins, ins.all_prefixes[i], orig_sizeflag);
10086         if (name == NULL)
10087           abort ();
10088         prefix_length += strlen (name) + 1;
10089         i386_dis_printf (&ins, dis_style_mnemonic, "%s ", name);
10090       }
10091
10092   /* Check maximum code length.  */
10093   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
10094     {
10095       i386_dis_printf (&ins, dis_style_text, "(bad)");
10096       return MAX_CODE_LENGTH;
10097     }
10098
10099   /* Calculate the number of operands this instruction has.  */
10100   op_count = 0;
10101   for (i = 0; i < MAX_OPERANDS; ++i)
10102     if (*ins.op_out[i] != '\0')
10103       ++op_count;
10104
10105   /* Calculate the number of spaces to print after the mnemonic.  */
10106   ins.obufp = ins.mnemonicendp;
10107   if (op_count > 0)
10108     {
10109       i = strlen (ins.obuf) + prefix_length;
10110       if (i < 7)
10111         i = 7 - i;
10112       else
10113         i = 1;
10114     }
10115   else
10116     i = 0;
10117
10118   /* Print the instruction mnemonic along with any trailing whitespace.  */
10119   i386_dis_printf (&ins, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
10120
10121   /* The enter and bound instructions are printed with operands in the same
10122      order as the intel book; everything else is printed in reverse order.  */
10123   intel_swap_2_3 = false;
10124   if (ins.intel_syntax || ins.two_source_ops)
10125     {
10126       for (i = 0; i < MAX_OPERANDS; ++i)
10127         op_txt[i] = ins.op_out[i];
10128
10129       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10130           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10131         {
10132           op_txt[2] = ins.op_out[3];
10133           op_txt[3] = ins.op_out[2];
10134           intel_swap_2_3 = true;
10135         }
10136
10137       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10138         {
10139           bool riprel;
10140
10141           ins.op_ad = ins.op_index[i];
10142           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
10143           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
10144           riprel = ins.op_riprel[i];
10145           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
10146           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10147         }
10148     }
10149   else
10150     {
10151       for (i = 0; i < MAX_OPERANDS; ++i)
10152         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
10153     }
10154
10155   needcomma = 0;
10156   for (i = 0; i < MAX_OPERANDS; ++i)
10157     if (*op_txt[i])
10158       {
10159         /* In Intel syntax embedded rounding / SAE are not separate operands.
10160            Instead they're attached to the prior register operand.  Simply
10161            suppress emission of the comma to achieve that effect.  */
10162         switch (i & -(ins.intel_syntax && dp))
10163           {
10164           case 2:
10165             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
10166               needcomma = 0;
10167             break;
10168           case 3:
10169             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
10170               needcomma = 0;
10171             break;
10172           }
10173         if (needcomma)
10174           i386_dis_printf (&ins, dis_style_text, ",");
10175         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
10176           {
10177             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
10178
10179             if (ins.op_is_jump)
10180               {
10181                 info->insn_info_valid = 1;
10182                 info->branch_delay_insns = 0;
10183                 info->data_size = 0;
10184                 info->target = target;
10185                 info->target2 = 0;
10186               }
10187             (*info->print_address_func) (target, info);
10188           }
10189         else
10190           i386_dis_printf (&ins, dis_style_text, "%s", op_txt[i]);
10191         needcomma = 1;
10192       }
10193
10194   for (i = 0; i < MAX_OPERANDS; i++)
10195     if (ins.op_index[i] != -1 && ins.op_riprel[i])
10196       {
10197         i386_dis_printf (&ins, dis_style_comment_start, "        # ");
10198         (*info->print_address_func)
10199           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
10200                      + ins.op_address[ins.op_index[i]]),
10201           info);
10202         break;
10203       }
10204   return ins.codep - priv.the_buffer;
10205 }
10206
10207 /* Here for backwards compatibility.  When gdb stops using
10208    print_insn_i386_att and print_insn_i386_intel these functions can
10209    disappear, and print_insn_i386 be merged into print_insn.  */
10210 int
10211 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10212 {
10213   return print_insn (pc, info, 0);
10214 }
10215
10216 int
10217 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10218 {
10219   return print_insn (pc, info, 1);
10220 }
10221
10222 int
10223 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10224 {
10225   return print_insn (pc, info, -1);
10226 }
10227
10228 static const char *float_mem[] = {
10229   /* d8 */
10230   "fadd{s|}",
10231   "fmul{s|}",
10232   "fcom{s|}",
10233   "fcomp{s|}",
10234   "fsub{s|}",
10235   "fsubr{s|}",
10236   "fdiv{s|}",
10237   "fdivr{s|}",
10238   /* d9 */
10239   "fld{s|}",
10240   "(bad)",
10241   "fst{s|}",
10242   "fstp{s|}",
10243   "fldenv{C|C}",
10244   "fldcw",
10245   "fNstenv{C|C}",
10246   "fNstcw",
10247   /* da */
10248   "fiadd{l|}",
10249   "fimul{l|}",
10250   "ficom{l|}",
10251   "ficomp{l|}",
10252   "fisub{l|}",
10253   "fisubr{l|}",
10254   "fidiv{l|}",
10255   "fidivr{l|}",
10256   /* db */
10257   "fild{l|}",
10258   "fisttp{l|}",
10259   "fist{l|}",
10260   "fistp{l|}",
10261   "(bad)",
10262   "fld{t|}",
10263   "(bad)",
10264   "fstp{t|}",
10265   /* dc */
10266   "fadd{l|}",
10267   "fmul{l|}",
10268   "fcom{l|}",
10269   "fcomp{l|}",
10270   "fsub{l|}",
10271   "fsubr{l|}",
10272   "fdiv{l|}",
10273   "fdivr{l|}",
10274   /* dd */
10275   "fld{l|}",
10276   "fisttp{ll|}",
10277   "fst{l||}",
10278   "fstp{l|}",
10279   "frstor{C|C}",
10280   "(bad)",
10281   "fNsave{C|C}",
10282   "fNstsw",
10283   /* de */
10284   "fiadd{s|}",
10285   "fimul{s|}",
10286   "ficom{s|}",
10287   "ficomp{s|}",
10288   "fisub{s|}",
10289   "fisubr{s|}",
10290   "fidiv{s|}",
10291   "fidivr{s|}",
10292   /* df */
10293   "fild{s|}",
10294   "fisttp{s|}",
10295   "fist{s|}",
10296   "fistp{s|}",
10297   "fbld",
10298   "fild{ll|}",
10299   "fbstp",
10300   "fistp{ll|}",
10301 };
10302
10303 static const unsigned char float_mem_mode[] = {
10304   /* d8 */
10305   d_mode,
10306   d_mode,
10307   d_mode,
10308   d_mode,
10309   d_mode,
10310   d_mode,
10311   d_mode,
10312   d_mode,
10313   /* d9 */
10314   d_mode,
10315   0,
10316   d_mode,
10317   d_mode,
10318   0,
10319   w_mode,
10320   0,
10321   w_mode,
10322   /* da */
10323   d_mode,
10324   d_mode,
10325   d_mode,
10326   d_mode,
10327   d_mode,
10328   d_mode,
10329   d_mode,
10330   d_mode,
10331   /* db */
10332   d_mode,
10333   d_mode,
10334   d_mode,
10335   d_mode,
10336   0,
10337   t_mode,
10338   0,
10339   t_mode,
10340   /* dc */
10341   q_mode,
10342   q_mode,
10343   q_mode,
10344   q_mode,
10345   q_mode,
10346   q_mode,
10347   q_mode,
10348   q_mode,
10349   /* dd */
10350   q_mode,
10351   q_mode,
10352   q_mode,
10353   q_mode,
10354   0,
10355   0,
10356   0,
10357   w_mode,
10358   /* de */
10359   w_mode,
10360   w_mode,
10361   w_mode,
10362   w_mode,
10363   w_mode,
10364   w_mode,
10365   w_mode,
10366   w_mode,
10367   /* df */
10368   w_mode,
10369   w_mode,
10370   w_mode,
10371   w_mode,
10372   t_mode,
10373   q_mode,
10374   t_mode,
10375   q_mode
10376 };
10377
10378 #define ST { OP_ST, 0 }
10379 #define STi { OP_STi, 0 }
10380
10381 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10382 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10383 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10384 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10385 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10386 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10387 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10388 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10389 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10390
10391 static const struct dis386 float_reg[][8] = {
10392   /* d8 */
10393   {
10394     { "fadd",   { ST, STi }, 0 },
10395     { "fmul",   { ST, STi }, 0 },
10396     { "fcom",   { STi }, 0 },
10397     { "fcomp",  { STi }, 0 },
10398     { "fsub",   { ST, STi }, 0 },
10399     { "fsubr",  { ST, STi }, 0 },
10400     { "fdiv",   { ST, STi }, 0 },
10401     { "fdivr",  { ST, STi }, 0 },
10402   },
10403   /* d9 */
10404   {
10405     { "fld",    { STi }, 0 },
10406     { "fxch",   { STi }, 0 },
10407     { FGRPd9_2 },
10408     { Bad_Opcode },
10409     { FGRPd9_4 },
10410     { FGRPd9_5 },
10411     { FGRPd9_6 },
10412     { FGRPd9_7 },
10413   },
10414   /* da */
10415   {
10416     { "fcmovb", { ST, STi }, 0 },
10417     { "fcmove", { ST, STi }, 0 },
10418     { "fcmovbe",{ ST, STi }, 0 },
10419     { "fcmovu", { ST, STi }, 0 },
10420     { Bad_Opcode },
10421     { FGRPda_5 },
10422     { Bad_Opcode },
10423     { Bad_Opcode },
10424   },
10425   /* db */
10426   {
10427     { "fcmovnb",{ ST, STi }, 0 },
10428     { "fcmovne",{ ST, STi }, 0 },
10429     { "fcmovnbe",{ ST, STi }, 0 },
10430     { "fcmovnu",{ ST, STi }, 0 },
10431     { FGRPdb_4 },
10432     { "fucomi", { ST, STi }, 0 },
10433     { "fcomi",  { ST, STi }, 0 },
10434     { Bad_Opcode },
10435   },
10436   /* dc */
10437   {
10438     { "fadd",   { STi, ST }, 0 },
10439     { "fmul",   { STi, ST }, 0 },
10440     { Bad_Opcode },
10441     { Bad_Opcode },
10442     { "fsub{!M|r}",     { STi, ST }, 0 },
10443     { "fsub{M|}",       { STi, ST }, 0 },
10444     { "fdiv{!M|r}",     { STi, ST }, 0 },
10445     { "fdiv{M|}",       { STi, ST }, 0 },
10446   },
10447   /* dd */
10448   {
10449     { "ffree",  { STi }, 0 },
10450     { Bad_Opcode },
10451     { "fst",    { STi }, 0 },
10452     { "fstp",   { STi }, 0 },
10453     { "fucom",  { STi }, 0 },
10454     { "fucomp", { STi }, 0 },
10455     { Bad_Opcode },
10456     { Bad_Opcode },
10457   },
10458   /* de */
10459   {
10460     { "faddp",  { STi, ST }, 0 },
10461     { "fmulp",  { STi, ST }, 0 },
10462     { Bad_Opcode },
10463     { FGRPde_3 },
10464     { "fsub{!M|r}p",    { STi, ST }, 0 },
10465     { "fsub{M|}p",      { STi, ST }, 0 },
10466     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10467     { "fdiv{M|}p",      { STi, ST }, 0 },
10468   },
10469   /* df */
10470   {
10471     { "ffreep", { STi }, 0 },
10472     { Bad_Opcode },
10473     { Bad_Opcode },
10474     { Bad_Opcode },
10475     { FGRPdf_4 },
10476     { "fucomip", { ST, STi }, 0 },
10477     { "fcomip", { ST, STi }, 0 },
10478     { Bad_Opcode },
10479   },
10480 };
10481
10482 static const char *const fgrps[][8] = {
10483   /* Bad opcode 0 */
10484   {
10485     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10486   },
10487
10488   /* d9_2  1 */
10489   {
10490     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10491   },
10492
10493   /* d9_4  2 */
10494   {
10495     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10496   },
10497
10498   /* d9_5  3 */
10499   {
10500     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10501   },
10502
10503   /* d9_6  4 */
10504   {
10505     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10506   },
10507
10508   /* d9_7  5 */
10509   {
10510     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10511   },
10512
10513   /* da_5  6 */
10514   {
10515     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10516   },
10517
10518   /* db_4  7 */
10519   {
10520     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10521     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10522   },
10523
10524   /* de_3  8 */
10525   {
10526     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10527   },
10528
10529   /* df_4  9 */
10530   {
10531     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10532   },
10533 };
10534
10535 static void
10536 swap_operand (instr_info *ins)
10537 {
10538   ins->mnemonicendp[0] = '.';
10539   ins->mnemonicendp[1] = 's';
10540   ins->mnemonicendp[2] = '\0';
10541   ins->mnemonicendp += 2;
10542 }
10543
10544 static void
10545 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10546                int sizeflag ATTRIBUTE_UNUSED)
10547 {
10548   /* Skip mod/rm byte.  */
10549   MODRM_CHECK;
10550   ins->codep++;
10551 }
10552
10553 static void
10554 dofloat (instr_info *ins, int sizeflag)
10555 {
10556   const struct dis386 *dp;
10557   unsigned char floatop;
10558
10559   floatop = ins->codep[-1];
10560
10561   if (ins->modrm.mod != 3)
10562     {
10563       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10564
10565       putop (ins, float_mem[fp_indx], sizeflag);
10566       ins->obufp = ins->op_out[0];
10567       ins->op_ad = 2;
10568       OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10569       return;
10570     }
10571   /* Skip mod/rm byte.  */
10572   MODRM_CHECK;
10573   ins->codep++;
10574
10575   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10576   if (dp->name == NULL)
10577     {
10578       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10579
10580       /* Instruction fnstsw is only one with strange arg.  */
10581       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10582         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10583     }
10584   else
10585     {
10586       putop (ins, dp->name, sizeflag);
10587
10588       ins->obufp = ins->op_out[0];
10589       ins->op_ad = 2;
10590       if (dp->op[0].rtn)
10591         (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10592
10593       ins->obufp = ins->op_out[1];
10594       ins->op_ad = 1;
10595       if (dp->op[1].rtn)
10596         (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10597     }
10598 }
10599
10600 static void
10601 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10602        int sizeflag ATTRIBUTE_UNUSED)
10603 {
10604   oappend_register (ins, "%st");
10605 }
10606
10607 static void
10608 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10609         int sizeflag ATTRIBUTE_UNUSED)
10610 {
10611   char scratch[8];
10612   int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10613
10614   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10615     abort ();
10616   oappend_register (ins, scratch);
10617 }
10618
10619 /* Capital letters in template are macros.  */
10620 static int
10621 putop (instr_info *ins, const char *in_template, int sizeflag)
10622 {
10623   const char *p;
10624   int alt = 0;
10625   int cond = 1;
10626   unsigned int l = 0, len = 0;
10627   char last[4];
10628
10629   for (p = in_template; *p; p++)
10630     {
10631       if (len > l)
10632         {
10633           if (l >= sizeof (last) || !ISUPPER (*p))
10634             abort ();
10635           last[l++] = *p;
10636           continue;
10637         }
10638       switch (*p)
10639         {
10640         default:
10641           *ins->obufp++ = *p;
10642           break;
10643         case '%':
10644           len++;
10645           break;
10646         case '!':
10647           cond = 0;
10648           break;
10649         case '{':
10650           if (ins->intel_syntax)
10651             {
10652               while (*++p != '|')
10653                 if (*p == '}' || *p == '\0')
10654                   abort ();
10655               alt = 1;
10656             }
10657           break;
10658         case '|':
10659           while (*++p != '}')
10660             {
10661               if (*p == '\0')
10662                 abort ();
10663             }
10664           break;
10665         case '}':
10666           alt = 0;
10667           break;
10668         case 'A':
10669           if (ins->intel_syntax)
10670             break;
10671           if ((ins->need_modrm && ins->modrm.mod != 3)
10672               || (sizeflag & SUFFIX_ALWAYS))
10673             *ins->obufp++ = 'b';
10674           break;
10675         case 'B':
10676           if (l == 0)
10677             {
10678             case_B:
10679               if (ins->intel_syntax)
10680                 break;
10681               if (sizeflag & SUFFIX_ALWAYS)
10682                 *ins->obufp++ = 'b';
10683             }
10684           else if (l == 1 && last[0] == 'L')
10685             {
10686               if (ins->address_mode == mode_64bit
10687                   && !(ins->prefixes & PREFIX_ADDR))
10688                 {
10689                   *ins->obufp++ = 'a';
10690                   *ins->obufp++ = 'b';
10691                   *ins->obufp++ = 's';
10692                 }
10693
10694               goto case_B;
10695             }
10696           else
10697             abort ();
10698           break;
10699         case 'C':
10700           if (ins->intel_syntax && !alt)
10701             break;
10702           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10703             {
10704               if (sizeflag & DFLAG)
10705                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10706               else
10707                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10708               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10709             }
10710           break;
10711         case 'D':
10712           if (l == 1)
10713             {
10714               switch (last[0])
10715               {
10716               case 'X':
10717                 if (!ins->vex.evex || ins->vex.w)
10718                   *ins->obufp++ = 'd';
10719                 else
10720                   oappend (ins, "{bad}");
10721                 break;
10722               default:
10723                 abort ();
10724               }
10725               break;
10726             }
10727           if (l)
10728             abort ();
10729           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10730             break;
10731           USED_REX (REX_W);
10732           if (ins->modrm.mod == 3)
10733             {
10734               if (ins->rex & REX_W)
10735                 *ins->obufp++ = 'q';
10736               else
10737                 {
10738                   if (sizeflag & DFLAG)
10739                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10740                   else
10741                     *ins->obufp++ = 'w';
10742                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10743                 }
10744             }
10745           else
10746             *ins->obufp++ = 'w';
10747           break;
10748         case 'E':
10749           if (l == 1)
10750             {
10751               switch (last[0])
10752                 {
10753                 case 'X':
10754                   if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10755                       || !ins->vex.r
10756                       || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10757                       || !ins->vex.v || ins->vex.mask_register_specifier)
10758                     break;
10759                   /* AVX512 extends a number of V*D insns to also have V*Q variants,
10760                      merely distinguished by EVEX.W.  Look for a use of the
10761                      respective macro.  */
10762                   if (ins->vex.w)
10763                     {
10764                       const char *pct = strchr (p + 1, '%');
10765
10766                       if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10767                         break;
10768                     }
10769                   *ins->obufp++ = '{';
10770                   *ins->obufp++ = 'e';
10771                   *ins->obufp++ = 'v';
10772                   *ins->obufp++ = 'e';
10773                   *ins->obufp++ = 'x';
10774                   *ins->obufp++ = '}';
10775                   *ins->obufp++ = ' ';
10776                   break;
10777                 default:
10778                   abort ();
10779                 }
10780                 break;
10781             }
10782           /* For jcxz/jecxz */
10783           if (ins->address_mode == mode_64bit)
10784             {
10785               if (sizeflag & AFLAG)
10786                 *ins->obufp++ = 'r';
10787               else
10788                 *ins->obufp++ = 'e';
10789             }
10790           else
10791             if (sizeflag & AFLAG)
10792               *ins->obufp++ = 'e';
10793           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10794           break;
10795         case 'F':
10796           if (ins->intel_syntax)
10797             break;
10798           if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10799             {
10800               if (sizeflag & AFLAG)
10801                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10802               else
10803                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10804               ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10805             }
10806           break;
10807         case 'G':
10808           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10809                                     && !(sizeflag & SUFFIX_ALWAYS)))
10810             break;
10811           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10812             *ins->obufp++ = 'l';
10813           else
10814             *ins->obufp++ = 'w';
10815           if (!(ins->rex & REX_W))
10816             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10817           break;
10818         case 'H':
10819           if (l == 0)
10820             {
10821               if (ins->intel_syntax)
10822                 break;
10823               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10824                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10825                 {
10826                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10827                   *ins->obufp++ = ',';
10828                   *ins->obufp++ = 'p';
10829
10830                   /* Set active_seg_prefix even if not set in 64-bit mode
10831                      because here it is a valid branch hint. */
10832                   if (ins->prefixes & PREFIX_DS)
10833                     {
10834                       ins->active_seg_prefix = PREFIX_DS;
10835                       *ins->obufp++ = 't';
10836                     }
10837                   else
10838                     {
10839                       ins->active_seg_prefix = PREFIX_CS;
10840                       *ins->obufp++ = 'n';
10841                     }
10842                 }
10843             }
10844           else if (l == 1 && last[0] == 'X')
10845             {
10846               if (!ins->vex.w)
10847                 *ins->obufp++ = 'h';
10848               else
10849                 oappend (ins, "{bad}");
10850             }
10851           else
10852             abort ();
10853           break;
10854         case 'K':
10855           USED_REX (REX_W);
10856           if (ins->rex & REX_W)
10857             *ins->obufp++ = 'q';
10858           else
10859             *ins->obufp++ = 'd';
10860           break;
10861         case 'L':
10862           abort ();
10863         case 'M':
10864           if (ins->intel_mnemonic != cond)
10865             *ins->obufp++ = 'r';
10866           break;
10867         case 'N':
10868           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10869             *ins->obufp++ = 'n';
10870           else
10871             ins->used_prefixes |= PREFIX_FWAIT;
10872           break;
10873         case 'O':
10874           USED_REX (REX_W);
10875           if (ins->rex & REX_W)
10876             *ins->obufp++ = 'o';
10877           else if (ins->intel_syntax && (sizeflag & DFLAG))
10878             *ins->obufp++ = 'q';
10879           else
10880             *ins->obufp++ = 'd';
10881           if (!(ins->rex & REX_W))
10882             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10883           break;
10884         case '@':
10885           if (ins->address_mode == mode_64bit
10886               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10887                   || !(ins->prefixes & PREFIX_DATA)))
10888             {
10889               if (sizeflag & SUFFIX_ALWAYS)
10890                 *ins->obufp++ = 'q';
10891               break;
10892             }
10893           /* Fall through.  */
10894         case 'P':
10895           if (l == 0)
10896             {
10897               if ((ins->modrm.mod == 3 || !cond)
10898                   && !(sizeflag & SUFFIX_ALWAYS))
10899                 break;
10900           /* Fall through.  */
10901         case 'T':
10902               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10903                   || ((sizeflag & SUFFIX_ALWAYS)
10904                       && ins->address_mode != mode_64bit))
10905                 {
10906                   *ins->obufp++ = (sizeflag & DFLAG)
10907                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10908                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10909                 }
10910               else if (sizeflag & SUFFIX_ALWAYS)
10911                 *ins->obufp++ = 'q';
10912             }
10913           else if (l == 1 && last[0] == 'L')
10914             {
10915               if ((ins->prefixes & PREFIX_DATA)
10916                   || (ins->rex & REX_W)
10917                   || (sizeflag & SUFFIX_ALWAYS))
10918                 {
10919                   USED_REX (REX_W);
10920                   if (ins->rex & REX_W)
10921                     *ins->obufp++ = 'q';
10922                   else
10923                     {
10924                       if (sizeflag & DFLAG)
10925                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10926                       else
10927                         *ins->obufp++ = 'w';
10928                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10929                     }
10930                 }
10931             }
10932           else
10933             abort ();
10934           break;
10935         case 'Q':
10936           if (l == 0)
10937             {
10938               if (ins->intel_syntax && !alt)
10939                 break;
10940               USED_REX (REX_W);
10941               if ((ins->need_modrm && ins->modrm.mod != 3)
10942                   || (sizeflag & SUFFIX_ALWAYS))
10943                 {
10944                   if (ins->rex & REX_W)
10945                     *ins->obufp++ = 'q';
10946                   else
10947                     {
10948                       if (sizeflag & DFLAG)
10949                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10950                       else
10951                         *ins->obufp++ = 'w';
10952                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10953                     }
10954                 }
10955             }
10956           else if (l == 1 && last[0] == 'D')
10957             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10958           else if (l == 1 && last[0] == 'L')
10959             {
10960               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10961                        : ins->address_mode != mode_64bit)
10962                 break;
10963               if ((ins->rex & REX_W))
10964                 {
10965                   USED_REX (REX_W);
10966                   *ins->obufp++ = 'q';
10967                 }
10968               else if ((ins->address_mode == mode_64bit && cond)
10969                       || (sizeflag & SUFFIX_ALWAYS))
10970                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10971             }
10972           else
10973             abort ();
10974           break;
10975         case 'R':
10976           USED_REX (REX_W);
10977           if (ins->rex & REX_W)
10978             *ins->obufp++ = 'q';
10979           else if (sizeflag & DFLAG)
10980             {
10981               if (ins->intel_syntax)
10982                   *ins->obufp++ = 'd';
10983               else
10984                   *ins->obufp++ = 'l';
10985             }
10986           else
10987             *ins->obufp++ = 'w';
10988           if (ins->intel_syntax && !p[1]
10989               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10990             *ins->obufp++ = 'e';
10991           if (!(ins->rex & REX_W))
10992             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10993           break;
10994         case 'S':
10995           if (l == 0)
10996             {
10997             case_S:
10998               if (ins->intel_syntax)
10999                 break;
11000               if (sizeflag & SUFFIX_ALWAYS)
11001                 {
11002                   if (ins->rex & REX_W)
11003                     *ins->obufp++ = 'q';
11004                   else
11005                     {
11006                       if (sizeflag & DFLAG)
11007                         *ins->obufp++ = 'l';
11008                       else
11009                         *ins->obufp++ = 'w';
11010                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11011                     }
11012                 }
11013               break;
11014             }
11015           if (l != 1)
11016             abort ();
11017           switch (last[0])
11018             {
11019             case 'L':
11020               if (ins->address_mode == mode_64bit
11021                   && !(ins->prefixes & PREFIX_ADDR))
11022                 {
11023                   *ins->obufp++ = 'a';
11024                   *ins->obufp++ = 'b';
11025                   *ins->obufp++ = 's';
11026                 }
11027
11028               goto case_S;
11029             case 'X':
11030               if (!ins->vex.evex || !ins->vex.w)
11031                 *ins->obufp++ = 's';
11032               else
11033                 oappend (ins, "{bad}");
11034               break;
11035             default:
11036               abort ();
11037             }
11038           break;
11039         case 'V':
11040           if (l == 0)
11041             abort ();
11042           else if (l == 1)
11043             {
11044               switch (last[0])
11045                 {
11046                 case 'X':
11047                   if (ins->vex.evex)
11048                     break;
11049                   *ins->obufp++ = '{';
11050                   *ins->obufp++ = 'v';
11051                   *ins->obufp++ = 'e';
11052                   *ins->obufp++ = 'x';
11053                   *ins->obufp++ = '}';
11054                   *ins->obufp++ = ' ';
11055                   break;
11056                 case 'L':
11057                   if (!(ins->rex & REX_W))
11058                     break;
11059                   *ins->obufp++ = 'a';
11060                   *ins->obufp++ = 'b';
11061                   *ins->obufp++ = 's';
11062                   break;
11063                 default:
11064                   abort ();
11065                 }
11066             }
11067           else
11068             abort ();
11069           goto case_S;
11070         case 'W':
11071           if (l == 0)
11072             {
11073               /* operand size flag for cwtl, cbtw */
11074               USED_REX (REX_W);
11075               if (ins->rex & REX_W)
11076                 {
11077                   if (ins->intel_syntax)
11078                     *ins->obufp++ = 'd';
11079                   else
11080                     *ins->obufp++ = 'l';
11081                 }
11082               else if (sizeflag & DFLAG)
11083                 *ins->obufp++ = 'w';
11084               else
11085                 *ins->obufp++ = 'b';
11086               if (!(ins->rex & REX_W))
11087                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11088             }
11089           else if (l == 1)
11090             {
11091               if (!ins->need_vex)
11092                 abort ();
11093               if (last[0] == 'X')
11094                 *ins->obufp++ = ins->vex.w ? 'd': 's';
11095               else if (last[0] == 'B')
11096                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
11097               else
11098                 abort ();
11099             }
11100           else
11101             abort ();
11102           break;
11103         case 'X':
11104           if (l != 0)
11105             abort ();
11106           if (ins->need_vex
11107               ? ins->vex.prefix == DATA_PREFIX_OPCODE
11108               : ins->prefixes & PREFIX_DATA)
11109             {
11110               *ins->obufp++ = 'd';
11111               ins->used_prefixes |= PREFIX_DATA;
11112             }
11113           else
11114             *ins->obufp++ = 's';
11115           break;
11116         case 'Y':
11117           if (l == 1 && last[0] == 'X')
11118             {
11119               if (!ins->need_vex)
11120                 abort ();
11121               if (ins->intel_syntax
11122                   || ((ins->modrm.mod == 3 || ins->vex.b)
11123                       && !(sizeflag & SUFFIX_ALWAYS)))
11124                 break;
11125               switch (ins->vex.length)
11126                 {
11127                 case 128:
11128                   *ins->obufp++ = 'x';
11129                   break;
11130                 case 256:
11131                   *ins->obufp++ = 'y';
11132                   break;
11133                 case 512:
11134                   if (!ins->vex.evex)
11135                 default:
11136                     abort ();
11137                 }
11138             }
11139           else
11140             abort ();
11141           break;
11142         case 'Z':
11143           if (l == 0)
11144             {
11145               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11146               ins->modrm.mod = 3;
11147               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11148                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11149             }
11150           else if (l == 1 && last[0] == 'X')
11151             {
11152               if (!ins->vex.evex)
11153                 abort ();
11154               if (ins->intel_syntax
11155                   || ((ins->modrm.mod == 3 || ins->vex.b)
11156                       && !(sizeflag & SUFFIX_ALWAYS)))
11157                 break;
11158               switch (ins->vex.length)
11159                 {
11160                 case 128:
11161                   *ins->obufp++ = 'x';
11162                   break;
11163                 case 256:
11164                   *ins->obufp++ = 'y';
11165                   break;
11166                 case 512:
11167                   *ins->obufp++ = 'z';
11168                   break;
11169                 default:
11170                   abort ();
11171                 }
11172             }
11173           else
11174             abort ();
11175           break;
11176         case '^':
11177           if (ins->intel_syntax)
11178             break;
11179           if (ins->isa64 == intel64 && (ins->rex & REX_W))
11180             {
11181               USED_REX (REX_W);
11182               *ins->obufp++ = 'q';
11183               break;
11184             }
11185           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11186             {
11187               if (sizeflag & DFLAG)
11188                 *ins->obufp++ = 'l';
11189               else
11190                 *ins->obufp++ = 'w';
11191               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11192             }
11193           break;
11194         }
11195
11196       if (len == l)
11197         len = l = 0;
11198     }
11199   *ins->obufp = 0;
11200   ins->mnemonicendp = ins->obufp;
11201   return 0;
11202 }
11203
11204 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
11205    the buffer pointed to by INS->obufp has space.  A style marker is made
11206    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11207    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
11208    that the number of styles is not greater than 16.  */
11209
11210 static void
11211 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11212 {
11213   unsigned num = (unsigned) style;
11214
11215   /* We currently assume that STYLE can be encoded as a single hex
11216      character.  If more styles are added then this might start to fail,
11217      and we'll need to expand this code.  */
11218   if (num > 0xf)
11219     abort ();
11220
11221   *ins->obufp++ = STYLE_MARKER_CHAR;
11222   *ins->obufp++ = (num < 10 ? ('0' + num)
11223                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
11224   *ins->obufp++ = STYLE_MARKER_CHAR;
11225
11226   /* This final null character is not strictly necessary, after inserting a
11227      style marker we should always be inserting some additional content.
11228      However, having the buffer null terminated doesn't cost much, and make
11229      it easier to debug what's going on.  Also, if we do ever forget to add
11230      any additional content after this style marker, then the buffer will
11231      still be well formed.  */
11232   *ins->obufp = '\0';
11233 }
11234
11235 static void
11236 oappend_with_style (instr_info *ins, const char *s,
11237                     enum disassembler_style style)
11238 {
11239   oappend_insert_style (ins, style);
11240   ins->obufp = stpcpy (ins->obufp, s);
11241 }
11242
11243 /* Like oappend_with_style but always with text style.  */
11244
11245 static void
11246 oappend (instr_info *ins, const char *s)
11247 {
11248   oappend_with_style (ins, s, dis_style_text);
11249 }
11250
11251 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11252    the style for the character as STYLE.  */
11253
11254 static void
11255 oappend_char_with_style (instr_info *ins, const char c,
11256                          enum disassembler_style style)
11257 {
11258   oappend_insert_style (ins, style);
11259   *ins->obufp++ = c;
11260   *ins->obufp = '\0';
11261 }
11262
11263 /* Like oappend_char_with_style, but always uses dis_style_text.  */
11264
11265 static void
11266 oappend_char (instr_info *ins, const char c)
11267 {
11268   oappend_char_with_style (ins, c, dis_style_text);
11269 }
11270
11271 static void
11272 append_seg (instr_info *ins)
11273 {
11274   /* Only print the active segment register.  */
11275   if (!ins->active_seg_prefix)
11276     return;
11277
11278   ins->used_prefixes |= ins->active_seg_prefix;
11279   switch (ins->active_seg_prefix)
11280     {
11281     case PREFIX_CS:
11282       oappend_register (ins, "%cs");
11283       break;
11284     case PREFIX_DS:
11285       oappend_register (ins, "%ds");
11286       break;
11287     case PREFIX_SS:
11288       oappend_register (ins, "%ss");
11289       break;
11290     case PREFIX_ES:
11291       oappend_register (ins, "%es");
11292       break;
11293     case PREFIX_FS:
11294       oappend_register (ins, "%fs");
11295       break;
11296     case PREFIX_GS:
11297       oappend_register (ins, "%gs");
11298       break;
11299     default:
11300       break;
11301     }
11302   oappend_char (ins, ':');
11303 }
11304
11305 static void
11306 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
11307 {
11308   if (!ins->intel_syntax)
11309     oappend (ins, "*");
11310   OP_E (ins, bytemode, sizeflag);
11311 }
11312
11313 static void
11314 print_operand_value (instr_info *ins, bfd_vma disp,
11315                      enum disassembler_style style)
11316 {
11317   char tmp[30];
11318
11319   if (ins->address_mode == mode_64bit)
11320     sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11321   else
11322     sprintf (tmp, "0x%x", (unsigned int) disp);
11323   oappend_with_style (ins, tmp, style);
11324 }
11325
11326 /* Like oappend, but called for immediate operands.  */
11327
11328 static void
11329 oappend_immediate (instr_info *ins, bfd_vma imm)
11330 {
11331   if (!ins->intel_syntax)
11332     oappend_char_with_style (ins, '$', dis_style_immediate);
11333   print_operand_value (ins, imm, dis_style_immediate);
11334 }
11335
11336 /* Put DISP in BUF as signed hex number.  */
11337
11338 static void
11339 print_displacement (instr_info *ins, bfd_vma disp)
11340 {
11341   bfd_signed_vma val = disp;
11342   char tmp[30];
11343
11344   if (val < 0)
11345     {
11346       oappend_char_with_style (ins, '-', dis_style_address_offset);
11347       val = -disp;
11348
11349       /* Check for possible overflow.  */
11350       if (val < 0)
11351         {
11352           switch (ins->address_mode)
11353             {
11354             case mode_64bit:
11355               oappend_with_style (ins, "0x8000000000000000",
11356                                   dis_style_address_offset);
11357               break;
11358             case mode_32bit:
11359               oappend_with_style (ins, "0x80000000",
11360                                   dis_style_address_offset);
11361               break;
11362             case mode_16bit:
11363               oappend_with_style (ins, "0x8000",
11364                                   dis_style_address_offset);
11365               break;
11366             }
11367           return;
11368         }
11369     }
11370
11371   sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11372   oappend_with_style (ins, tmp, dis_style_address_offset);
11373 }
11374
11375 static void
11376 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11377 {
11378   if (ins->vex.b)
11379     {
11380       if (!ins->vex.no_broadcast)
11381         switch (bytemode)
11382           {
11383           case x_mode:
11384           case evex_half_bcst_xmmq_mode:
11385             if (ins->vex.w)
11386               oappend (ins, "QWORD BCST ");
11387             else
11388               oappend (ins, "DWORD BCST ");
11389             break;
11390           case xh_mode:
11391           case evex_half_bcst_xmmqh_mode:
11392           case evex_half_bcst_xmmqdh_mode:
11393             oappend (ins, "WORD BCST ");
11394             break;
11395           default:
11396             ins->vex.no_broadcast = true;
11397             break;
11398           }
11399       return;
11400     }
11401   switch (bytemode)
11402     {
11403     case b_mode:
11404     case b_swap_mode:
11405     case db_mode:
11406       oappend (ins, "BYTE PTR ");
11407       break;
11408     case w_mode:
11409     case w_swap_mode:
11410     case dw_mode:
11411       oappend (ins, "WORD PTR ");
11412       break;
11413     case indir_v_mode:
11414       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11415         {
11416           oappend (ins, "QWORD PTR ");
11417           break;
11418         }
11419       /* Fall through.  */
11420     case stack_v_mode:
11421       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11422                                               || (ins->rex & REX_W)))
11423         {
11424           oappend (ins, "QWORD PTR ");
11425           break;
11426         }
11427       /* Fall through.  */
11428     case v_mode:
11429     case v_swap_mode:
11430     case dq_mode:
11431       USED_REX (REX_W);
11432       if (ins->rex & REX_W)
11433         oappend (ins, "QWORD PTR ");
11434       else if (bytemode == dq_mode)
11435         oappend (ins, "DWORD PTR ");
11436       else
11437         {
11438           if (sizeflag & DFLAG)
11439             oappend (ins, "DWORD PTR ");
11440           else
11441             oappend (ins, "WORD PTR ");
11442           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11443         }
11444       break;
11445     case z_mode:
11446       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11447         *ins->obufp++ = 'D';
11448       oappend (ins, "WORD PTR ");
11449       if (!(ins->rex & REX_W))
11450         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11451       break;
11452     case a_mode:
11453       if (sizeflag & DFLAG)
11454         oappend (ins, "QWORD PTR ");
11455       else
11456         oappend (ins, "DWORD PTR ");
11457       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11458       break;
11459     case movsxd_mode:
11460       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11461         oappend (ins, "WORD PTR ");
11462       else
11463         oappend (ins, "DWORD PTR ");
11464       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11465       break;
11466     case d_mode:
11467     case d_swap_mode:
11468       oappend (ins, "DWORD PTR ");
11469       break;
11470     case q_mode:
11471     case q_swap_mode:
11472       oappend (ins, "QWORD PTR ");
11473       break;
11474     case m_mode:
11475       if (ins->address_mode == mode_64bit)
11476         oappend (ins, "QWORD PTR ");
11477       else
11478         oappend (ins, "DWORD PTR ");
11479       break;
11480     case f_mode:
11481       if (sizeflag & DFLAG)
11482         oappend (ins, "FWORD PTR ");
11483       else
11484         oappend (ins, "DWORD PTR ");
11485       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11486       break;
11487     case t_mode:
11488       oappend (ins, "TBYTE PTR ");
11489       break;
11490     case x_mode:
11491     case xh_mode:
11492     case x_swap_mode:
11493     case evex_x_gscat_mode:
11494     case evex_x_nobcst_mode:
11495     case bw_unit_mode:
11496       if (ins->need_vex)
11497         {
11498           switch (ins->vex.length)
11499             {
11500             case 128:
11501               oappend (ins, "XMMWORD PTR ");
11502               break;
11503             case 256:
11504               oappend (ins, "YMMWORD PTR ");
11505               break;
11506             case 512:
11507               oappend (ins, "ZMMWORD PTR ");
11508               break;
11509             default:
11510               abort ();
11511             }
11512         }
11513       else
11514         oappend (ins, "XMMWORD PTR ");
11515       break;
11516     case xmm_mode:
11517       oappend (ins, "XMMWORD PTR ");
11518       break;
11519     case ymm_mode:
11520       oappend (ins, "YMMWORD PTR ");
11521       break;
11522     case xmmq_mode:
11523     case evex_half_bcst_xmmqh_mode:
11524     case evex_half_bcst_xmmq_mode:
11525       if (!ins->need_vex)
11526         abort ();
11527
11528       switch (ins->vex.length)
11529         {
11530         case 128:
11531           oappend (ins, "QWORD PTR ");
11532           break;
11533         case 256:
11534           oappend (ins, "XMMWORD PTR ");
11535           break;
11536         case 512:
11537           oappend (ins, "YMMWORD PTR ");
11538           break;
11539         default:
11540           abort ();
11541         }
11542       break;
11543     case xmmdw_mode:
11544       if (!ins->need_vex)
11545         abort ();
11546
11547       switch (ins->vex.length)
11548         {
11549         case 128:
11550           oappend (ins, "WORD PTR ");
11551           break;
11552         case 256:
11553           oappend (ins, "DWORD PTR ");
11554           break;
11555         case 512:
11556           oappend (ins, "QWORD PTR ");
11557           break;
11558         default:
11559           abort ();
11560         }
11561       break;
11562     case xmmqd_mode:
11563     case evex_half_bcst_xmmqdh_mode:
11564       if (!ins->need_vex)
11565         abort ();
11566
11567       switch (ins->vex.length)
11568         {
11569         case 128:
11570           oappend (ins, "DWORD PTR ");
11571           break;
11572         case 256:
11573           oappend (ins, "QWORD PTR ");
11574           break;
11575         case 512:
11576           oappend (ins, "XMMWORD PTR ");
11577           break;
11578         default:
11579           abort ();
11580         }
11581       break;
11582     case ymmq_mode:
11583       if (!ins->need_vex)
11584         abort ();
11585
11586       switch (ins->vex.length)
11587         {
11588         case 128:
11589           oappend (ins, "QWORD PTR ");
11590           break;
11591         case 256:
11592           oappend (ins, "YMMWORD PTR ");
11593           break;
11594         case 512:
11595           oappend (ins, "ZMMWORD PTR ");
11596           break;
11597         default:
11598           abort ();
11599         }
11600       break;
11601     case o_mode:
11602       oappend (ins, "OWORD PTR ");
11603       break;
11604     case vex_vsib_d_w_dq_mode:
11605     case vex_vsib_q_w_dq_mode:
11606       if (!ins->need_vex)
11607         abort ();
11608       if (ins->vex.w)
11609         oappend (ins, "QWORD PTR ");
11610       else
11611         oappend (ins, "DWORD PTR ");
11612       break;
11613     case mask_bd_mode:
11614       if (!ins->need_vex || ins->vex.length != 128)
11615         abort ();
11616       if (ins->vex.w)
11617         oappend (ins, "DWORD PTR ");
11618       else
11619         oappend (ins, "BYTE PTR ");
11620       break;
11621     case mask_mode:
11622       if (!ins->need_vex)
11623         abort ();
11624       if (ins->vex.w)
11625         oappend (ins, "QWORD PTR ");
11626       else
11627         oappend (ins, "WORD PTR ");
11628       break;
11629     case v_bnd_mode:
11630     case v_bndmk_mode:
11631     default:
11632       break;
11633     }
11634 }
11635
11636 static void
11637 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11638                 int bytemode, int sizeflag)
11639 {
11640   const char *const *names;
11641
11642   USED_REX (rexmask);
11643   if (ins->rex & rexmask)
11644     reg += 8;
11645
11646   switch (bytemode)
11647     {
11648     case b_mode:
11649     case b_swap_mode:
11650       if (reg & 4)
11651         USED_REX (0);
11652       if (ins->rex)
11653         names = att_names8rex;
11654       else
11655         names = att_names8;
11656       break;
11657     case w_mode:
11658       names = att_names16;
11659       break;
11660     case d_mode:
11661     case dw_mode:
11662     case db_mode:
11663       names = att_names32;
11664       break;
11665     case q_mode:
11666       names = att_names64;
11667       break;
11668     case m_mode:
11669     case v_bnd_mode:
11670       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11671       break;
11672     case bnd_mode:
11673     case bnd_swap_mode:
11674       if (reg > 0x3)
11675         {
11676           oappend (ins, "(bad)");
11677           return;
11678         }
11679       names = att_names_bnd;
11680       break;
11681     case indir_v_mode:
11682       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11683         {
11684           names = att_names64;
11685           break;
11686         }
11687       /* Fall through.  */
11688     case stack_v_mode:
11689       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11690                                               || (ins->rex & REX_W)))
11691         {
11692           names = att_names64;
11693           break;
11694         }
11695       bytemode = v_mode;
11696       /* Fall through.  */
11697     case v_mode:
11698     case v_swap_mode:
11699     case dq_mode:
11700       USED_REX (REX_W);
11701       if (ins->rex & REX_W)
11702         names = att_names64;
11703       else if (bytemode != v_mode && bytemode != v_swap_mode)
11704         names = att_names32;
11705       else
11706         {
11707           if (sizeflag & DFLAG)
11708             names = att_names32;
11709           else
11710             names = att_names16;
11711           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11712         }
11713       break;
11714     case movsxd_mode:
11715       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11716         names = att_names16;
11717       else
11718         names = att_names32;
11719       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11720       break;
11721     case va_mode:
11722       names = (ins->address_mode == mode_64bit
11723                ? att_names64 : att_names32);
11724       if (!(ins->prefixes & PREFIX_ADDR))
11725         names = (ins->address_mode == mode_16bit
11726                      ? att_names16 : names);
11727       else
11728         {
11729           /* Remove "addr16/addr32".  */
11730           ins->all_prefixes[ins->last_addr_prefix] = 0;
11731           names = (ins->address_mode != mode_32bit
11732                        ? att_names32 : att_names16);
11733           ins->used_prefixes |= PREFIX_ADDR;
11734         }
11735       break;
11736     case mask_bd_mode:
11737     case mask_mode:
11738       if (reg > 0x7)
11739         {
11740           oappend (ins, "(bad)");
11741           return;
11742         }
11743       names = att_names_mask;
11744       break;
11745     case 0:
11746       return;
11747     default:
11748       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11749       return;
11750     }
11751   oappend_register (ins, names[reg]);
11752 }
11753
11754 static void
11755 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11756 {
11757   bfd_vma disp = 0;
11758   int add = (ins->rex & REX_B) ? 8 : 0;
11759   int riprel = 0;
11760   int shift;
11761
11762   if (ins->vex.evex)
11763     {
11764       switch (bytemode)
11765         {
11766         case dw_mode:
11767         case w_mode:
11768         case w_swap_mode:
11769           shift = 1;
11770           break;
11771         case db_mode:
11772         case b_mode:
11773           shift = 0;
11774           break;
11775         case dq_mode:
11776           if (ins->address_mode != mode_64bit)
11777             {
11778         case d_mode:
11779         case d_swap_mode:
11780               shift = 2;
11781               break;
11782             }
11783             /* fall through */
11784         case vex_vsib_d_w_dq_mode:
11785         case vex_vsib_q_w_dq_mode:
11786         case evex_x_gscat_mode:
11787           shift = ins->vex.w ? 3 : 2;
11788           break;
11789         case xh_mode:
11790         case evex_half_bcst_xmmqh_mode:
11791         case evex_half_bcst_xmmqdh_mode:
11792           if (ins->vex.b)
11793             {
11794               shift = ins->vex.w ? 2 : 1;
11795               break;
11796             }
11797           /* Fall through.  */
11798         case x_mode:
11799         case evex_half_bcst_xmmq_mode:
11800           if (ins->vex.b)
11801             {
11802               shift = ins->vex.w ? 3 : 2;
11803               break;
11804             }
11805           /* Fall through.  */
11806         case xmmqd_mode:
11807         case xmmdw_mode:
11808         case xmmq_mode:
11809         case ymmq_mode:
11810         case evex_x_nobcst_mode:
11811         case x_swap_mode:
11812           switch (ins->vex.length)
11813             {
11814             case 128:
11815               shift = 4;
11816               break;
11817             case 256:
11818               shift = 5;
11819               break;
11820             case 512:
11821               shift = 6;
11822               break;
11823             default:
11824               abort ();
11825             }
11826           /* Make necessary corrections to shift for modes that need it.  */
11827           if (bytemode == xmmq_mode
11828               || bytemode == evex_half_bcst_xmmqh_mode
11829               || bytemode == evex_half_bcst_xmmq_mode
11830               || (bytemode == ymmq_mode && ins->vex.length == 128))
11831             shift -= 1;
11832           else if (bytemode == xmmqd_mode
11833                    || bytemode == evex_half_bcst_xmmqdh_mode)
11834             shift -= 2;
11835           else if (bytemode == xmmdw_mode)
11836             shift -= 3;
11837           break;
11838         case ymm_mode:
11839           shift = 5;
11840           break;
11841         case xmm_mode:
11842           shift = 4;
11843           break;
11844         case q_mode:
11845         case q_swap_mode:
11846           shift = 3;
11847           break;
11848         case bw_unit_mode:
11849           shift = ins->vex.w ? 1 : 0;
11850           break;
11851         default:
11852           abort ();
11853         }
11854     }
11855   else
11856     shift = 0;
11857
11858   USED_REX (REX_B);
11859   if (ins->intel_syntax)
11860     intel_operand_size (ins, bytemode, sizeflag);
11861   append_seg (ins);
11862
11863   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11864     {
11865       /* 32/64 bit address mode */
11866       int havedisp;
11867       int havebase;
11868       int needindex;
11869       int needaddr32;
11870       int base, rbase;
11871       int vindex = 0;
11872       int scale = 0;
11873       int addr32flag = !((sizeflag & AFLAG)
11874                          || bytemode == v_bnd_mode
11875                          || bytemode == v_bndmk_mode
11876                          || bytemode == bnd_mode
11877                          || bytemode == bnd_swap_mode);
11878       bool check_gather = false;
11879       const char *const *indexes = NULL;
11880
11881       havebase = 1;
11882       base = ins->modrm.rm;
11883
11884       if (base == 4)
11885         {
11886           vindex = ins->sib.index;
11887           USED_REX (REX_X);
11888           if (ins->rex & REX_X)
11889             vindex += 8;
11890           switch (bytemode)
11891             {
11892             case vex_vsib_d_w_dq_mode:
11893             case vex_vsib_q_w_dq_mode:
11894               if (!ins->need_vex)
11895                 abort ();
11896               if (ins->vex.evex)
11897                 {
11898                   if (!ins->vex.v)
11899                     vindex += 16;
11900                   check_gather = ins->obufp == ins->op_out[1];
11901                 }
11902
11903               switch (ins->vex.length)
11904                 {
11905                 case 128:
11906                   indexes = att_names_xmm;
11907                   break;
11908                 case 256:
11909                   if (!ins->vex.w
11910                       || bytemode == vex_vsib_q_w_dq_mode)
11911                     indexes = att_names_ymm;
11912                   else
11913                     indexes = att_names_xmm;
11914                   break;
11915                 case 512:
11916                   if (!ins->vex.w
11917                       || bytemode == vex_vsib_q_w_dq_mode)
11918                     indexes = att_names_zmm;
11919                   else
11920                     indexes = att_names_ymm;
11921                   break;
11922                 default:
11923                   abort ();
11924                 }
11925               break;
11926             default:
11927               if (vindex != 4)
11928                 indexes = ins->address_mode == mode_64bit && !addr32flag
11929                           ? att_names64 : att_names32;
11930               break;
11931             }
11932           scale = ins->sib.scale;
11933           base = ins->sib.base;
11934           ins->codep++;
11935         }
11936       else
11937         {
11938           /* Check for mandatory SIB.  */
11939           if (bytemode == vex_vsib_d_w_dq_mode
11940               || bytemode == vex_vsib_q_w_dq_mode
11941               || bytemode == vex_sibmem_mode)
11942             {
11943               oappend (ins, "(bad)");
11944               return;
11945             }
11946         }
11947       rbase = base + add;
11948
11949       switch (ins->modrm.mod)
11950         {
11951         case 0:
11952           if (base == 5)
11953             {
11954               havebase = 0;
11955               if (ins->address_mode == mode_64bit && !ins->has_sib)
11956                 riprel = 1;
11957               disp = get32s (ins);
11958               if (riprel && bytemode == v_bndmk_mode)
11959                 {
11960                   oappend (ins, "(bad)");
11961                   return;
11962                 }
11963             }
11964           break;
11965         case 1:
11966           FETCH_DATA (ins->info, ins->codep + 1);
11967           disp = *ins->codep++;
11968           if ((disp & 0x80) != 0)
11969             disp -= 0x100;
11970           if (ins->vex.evex && shift > 0)
11971             disp <<= shift;
11972           break;
11973         case 2:
11974           disp = get32s (ins);
11975           break;
11976         }
11977
11978       needindex = 0;
11979       needaddr32 = 0;
11980       if (ins->has_sib
11981           && !havebase
11982           && !indexes
11983           && ins->address_mode != mode_16bit)
11984         {
11985           if (ins->address_mode == mode_64bit)
11986             {
11987               if (addr32flag)
11988                 {
11989                   /* Without base nor index registers, zero-extend the
11990                      lower 32-bit displacement to 64 bits.  */
11991                   disp = (unsigned int) disp;
11992                   needindex = 1;
11993                 }
11994               needaddr32 = 1;
11995             }
11996           else
11997             {
11998               /* In 32-bit mode, we need index register to tell [offset]
11999                  from [eiz*1 + offset].  */
12000               needindex = 1;
12001             }
12002         }
12003
12004       havedisp = (havebase
12005                   || needindex
12006                   || (ins->has_sib && (indexes || scale != 0)));
12007
12008       if (!ins->intel_syntax)
12009         if (ins->modrm.mod != 0 || base == 5)
12010           {
12011             if (havedisp || riprel)
12012               print_displacement (ins, disp);
12013             else
12014               print_operand_value (ins, disp, dis_style_address_offset);
12015             if (riprel)
12016               {
12017                 set_op (ins, disp, true);
12018                 oappend_char (ins, '(');
12019                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12020                                     dis_style_register);
12021                 oappend_char (ins, ')');
12022               }
12023           }
12024
12025       if ((havebase || indexes || needindex || needaddr32 || riprel)
12026           && (ins->address_mode != mode_64bit
12027               || ((bytemode != v_bnd_mode)
12028                   && (bytemode != v_bndmk_mode)
12029                   && (bytemode != bnd_mode)
12030                   && (bytemode != bnd_swap_mode))))
12031         ins->used_prefixes |= PREFIX_ADDR;
12032
12033       if (havedisp || (ins->intel_syntax && riprel))
12034         {
12035           oappend_char (ins, ins->open_char);
12036           if (ins->intel_syntax && riprel)
12037             {
12038               set_op (ins, disp, true);
12039               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12040                                   dis_style_register);
12041             }
12042           if (havebase)
12043             oappend_register
12044               (ins,
12045                (ins->address_mode == mode_64bit && !addr32flag
12046                 ? att_names64 : att_names32)[rbase]);
12047           if (ins->has_sib)
12048             {
12049               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12050                  print index to tell base + index from base.  */
12051               if (scale != 0
12052                   || needindex
12053                   || indexes
12054                   || (havebase && base != ESP_REG_NUM))
12055                 {
12056                   if (!ins->intel_syntax || havebase)
12057                     oappend_char (ins, ins->separator_char);
12058                   if (indexes)
12059                     {
12060                       if (ins->address_mode == mode_64bit || vindex < 16)
12061                         oappend_register (ins, indexes[vindex]);
12062                       else
12063                         oappend (ins, "(bad)");
12064                     }
12065                   else
12066                     oappend_register (ins,
12067                                       ins->address_mode == mode_64bit
12068                                       && !addr32flag
12069                                       ? att_index64
12070                                       : att_index32);
12071
12072                   oappend_char (ins, ins->scale_char);
12073                   oappend_char_with_style (ins, '0' + (1 << scale),
12074                                            dis_style_immediate);
12075                 }
12076             }
12077           if (ins->intel_syntax
12078               && (disp || ins->modrm.mod != 0 || base == 5))
12079             {
12080               if (!havedisp || (bfd_signed_vma) disp >= 0)
12081                   oappend_char (ins, '+');
12082               else if (ins->modrm.mod != 1 && disp != -disp)
12083                 {
12084                   oappend_char (ins, '-');
12085                   disp = -disp;
12086                 }
12087
12088               if (havedisp)
12089                 print_displacement (ins, disp);
12090               else
12091                 print_operand_value (ins, disp, dis_style_address_offset);
12092             }
12093
12094           oappend_char (ins, ins->close_char);
12095
12096           if (check_gather)
12097             {
12098               /* Both XMM/YMM/ZMM registers must be distinct.  */
12099               int modrm_reg = ins->modrm.reg;
12100
12101               if (ins->rex & REX_R)
12102                 modrm_reg += 8;
12103               if (!ins->vex.r)
12104                 modrm_reg += 16;
12105               if (vindex == modrm_reg)
12106                 oappend (ins, "/(bad)");
12107             }
12108         }
12109       else if (ins->intel_syntax)
12110         {
12111           if (ins->modrm.mod != 0 || base == 5)
12112             {
12113               if (!ins->active_seg_prefix)
12114                 {
12115                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12116                   oappend (ins, ":");
12117                 }
12118               print_operand_value (ins, disp, dis_style_text);
12119             }
12120         }
12121     }
12122   else if (bytemode == v_bnd_mode
12123            || bytemode == v_bndmk_mode
12124            || bytemode == bnd_mode
12125            || bytemode == bnd_swap_mode
12126            || bytemode == vex_vsib_d_w_dq_mode
12127            || bytemode == vex_vsib_q_w_dq_mode)
12128     {
12129       oappend (ins, "(bad)");
12130       return;
12131     }
12132   else
12133     {
12134       /* 16 bit address mode */
12135       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12136       switch (ins->modrm.mod)
12137         {
12138         case 0:
12139           if (ins->modrm.rm == 6)
12140             {
12141               disp = get16 (ins);
12142               if ((disp & 0x8000) != 0)
12143                 disp -= 0x10000;
12144             }
12145           break;
12146         case 1:
12147           FETCH_DATA (ins->info, ins->codep + 1);
12148           disp = *ins->codep++;
12149           if ((disp & 0x80) != 0)
12150             disp -= 0x100;
12151           if (ins->vex.evex && shift > 0)
12152             disp <<= shift;
12153           break;
12154         case 2:
12155           disp = get16 (ins);
12156           if ((disp & 0x8000) != 0)
12157             disp -= 0x10000;
12158           break;
12159         }
12160
12161       if (!ins->intel_syntax)
12162         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12163           print_displacement (ins, disp);
12164
12165       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12166         {
12167           oappend_char (ins, ins->open_char);
12168           oappend (ins, (ins->intel_syntax ? intel_index16
12169                          : att_index16)[ins->modrm.rm]);
12170           if (ins->intel_syntax
12171               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12172             {
12173               if ((bfd_signed_vma) disp >= 0)
12174                 oappend_char (ins, '+');
12175               else if (ins->modrm.mod != 1)
12176                 {
12177                   oappend_char (ins, '-');
12178                   disp = -disp;
12179                 }
12180
12181               print_displacement (ins, disp);
12182             }
12183
12184           oappend_char (ins, ins->close_char);
12185         }
12186       else if (ins->intel_syntax)
12187         {
12188           if (!ins->active_seg_prefix)
12189             {
12190               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12191               oappend (ins, ":");
12192             }
12193           print_operand_value (ins, disp & 0xffff, dis_style_text);
12194         }
12195     }
12196   if (ins->vex.b)
12197     {
12198       ins->evex_used |= EVEX_b_used;
12199
12200       /* Broadcast can only ever be valid for memory sources.  */
12201       if (ins->obufp == ins->op_out[0])
12202         ins->vex.no_broadcast = true;
12203
12204       if (!ins->vex.no_broadcast
12205           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12206         {
12207           if (bytemode == xh_mode)
12208             {
12209               if (ins->vex.w)
12210                 oappend (ins, "{bad}");
12211               else
12212                 {
12213                   switch (ins->vex.length)
12214                     {
12215                     case 128:
12216                       oappend (ins, "{1to8}");
12217                       break;
12218                     case 256:
12219                       oappend (ins, "{1to16}");
12220                       break;
12221                     case 512:
12222                       oappend (ins, "{1to32}");
12223                       break;
12224                     default:
12225                       abort ();
12226                     }
12227                 }
12228             }
12229           else if (bytemode == q_mode
12230                    || bytemode == ymmq_mode)
12231             ins->vex.no_broadcast = true;
12232           else if (ins->vex.w
12233                    || bytemode == evex_half_bcst_xmmqdh_mode
12234                    || bytemode == evex_half_bcst_xmmq_mode)
12235             {
12236               switch (ins->vex.length)
12237                 {
12238                 case 128:
12239                   oappend (ins, "{1to2}");
12240                   break;
12241                 case 256:
12242                   oappend (ins, "{1to4}");
12243                   break;
12244                 case 512:
12245                   oappend (ins, "{1to8}");
12246                   break;
12247                 default:
12248                   abort ();
12249                 }
12250             }
12251           else if (bytemode == x_mode
12252                    || bytemode == evex_half_bcst_xmmqh_mode)
12253             {
12254               switch (ins->vex.length)
12255                 {
12256                 case 128:
12257                   oappend (ins, "{1to4}");
12258                   break;
12259                 case 256:
12260                   oappend (ins, "{1to8}");
12261                   break;
12262                 case 512:
12263                   oappend (ins, "{1to16}");
12264                   break;
12265                 default:
12266                   abort ();
12267                 }
12268             }
12269           else
12270             ins->vex.no_broadcast = true;
12271         }
12272       if (ins->vex.no_broadcast)
12273         oappend (ins, "{bad}");
12274     }
12275 }
12276
12277 static void
12278 OP_E (instr_info *ins, int bytemode, int sizeflag)
12279 {
12280   /* Skip mod/rm byte.  */
12281   MODRM_CHECK;
12282   ins->codep++;
12283
12284   if (ins->modrm.mod == 3)
12285     {
12286       if ((sizeflag & SUFFIX_ALWAYS)
12287           && (bytemode == b_swap_mode
12288               || bytemode == bnd_swap_mode
12289               || bytemode == v_swap_mode))
12290         swap_operand (ins);
12291
12292       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12293     }
12294   else
12295     OP_E_memory (ins, bytemode, sizeflag);
12296 }
12297
12298 static void
12299 OP_G (instr_info *ins, int bytemode, int sizeflag)
12300 {
12301   if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
12302     {
12303       oappend (ins, "(bad)");
12304       return;
12305     }
12306
12307   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12308 }
12309
12310 #ifdef BFD64
12311 static bfd_vma
12312 get64 (instr_info *ins)
12313 {
12314   bfd_vma x;
12315   unsigned int a;
12316   unsigned int b;
12317
12318   FETCH_DATA (ins->info, ins->codep + 8);
12319   a = *ins->codep++ & 0xff;
12320   a |= (*ins->codep++ & 0xff) << 8;
12321   a |= (*ins->codep++ & 0xff) << 16;
12322   a |= (*ins->codep++ & 0xffu) << 24;
12323   b = *ins->codep++ & 0xff;
12324   b |= (*ins->codep++ & 0xff) << 8;
12325   b |= (*ins->codep++ & 0xff) << 16;
12326   b |= (*ins->codep++ & 0xffu) << 24;
12327   x = a + ((bfd_vma) b << 32);
12328   return x;
12329 }
12330 #else
12331 static bfd_vma
12332 get64 (instr_info *ins ATTRIBUTE_UNUSED)
12333 {
12334   abort ();
12335   return 0;
12336 }
12337 #endif
12338
12339 static bfd_signed_vma
12340 get32 (instr_info *ins)
12341 {
12342   bfd_vma x = 0;
12343
12344   FETCH_DATA (ins->info, ins->codep + 4);
12345   x = *ins->codep++ & (bfd_vma) 0xff;
12346   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12347   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12348   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12349   return x;
12350 }
12351
12352 static bfd_signed_vma
12353 get32s (instr_info *ins)
12354 {
12355   bfd_vma x = 0;
12356
12357   FETCH_DATA (ins->info, ins->codep + 4);
12358   x = *ins->codep++ & (bfd_vma) 0xff;
12359   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12360   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12361   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12362
12363   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12364
12365   return x;
12366 }
12367
12368 static int
12369 get16 (instr_info *ins)
12370 {
12371   int x = 0;
12372
12373   FETCH_DATA (ins->info, ins->codep + 2);
12374   x = *ins->codep++ & 0xff;
12375   x |= (*ins->codep++ & 0xff) << 8;
12376   return x;
12377 }
12378
12379 static void
12380 set_op (instr_info *ins, bfd_vma op, bool riprel)
12381 {
12382   ins->op_index[ins->op_ad] = ins->op_ad;
12383   if (ins->address_mode == mode_64bit)
12384     ins->op_address[ins->op_ad] = op;
12385   else /* Mask to get a 32-bit address.  */
12386     ins->op_address[ins->op_ad] = op & 0xffffffff;
12387   ins->op_riprel[ins->op_ad] = riprel;
12388 }
12389
12390 static void
12391 OP_REG (instr_info *ins, int code, int sizeflag)
12392 {
12393   const char *s;
12394   int add;
12395
12396   switch (code)
12397     {
12398     case es_reg: case ss_reg: case cs_reg:
12399     case ds_reg: case fs_reg: case gs_reg:
12400       oappend_register (ins, att_names_seg[code - es_reg]);
12401       return;
12402     }
12403
12404   USED_REX (REX_B);
12405   if (ins->rex & REX_B)
12406     add = 8;
12407   else
12408     add = 0;
12409
12410   switch (code)
12411     {
12412     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12413     case sp_reg: case bp_reg: case si_reg: case di_reg:
12414       s = att_names16[code - ax_reg + add];
12415       break;
12416     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12417       USED_REX (0);
12418       /* Fall through.  */
12419     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12420       if (ins->rex)
12421         s = att_names8rex[code - al_reg + add];
12422       else
12423         s = att_names8[code - al_reg];
12424       break;
12425     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12426     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12427       if (ins->address_mode == mode_64bit
12428           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12429         {
12430           s = att_names64[code - rAX_reg + add];
12431           break;
12432         }
12433       code += eAX_reg - rAX_reg;
12434       /* Fall through.  */
12435     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12436     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12437       USED_REX (REX_W);
12438       if (ins->rex & REX_W)
12439         s = att_names64[code - eAX_reg + add];
12440       else
12441         {
12442           if (sizeflag & DFLAG)
12443             s = att_names32[code - eAX_reg + add];
12444           else
12445             s = att_names16[code - eAX_reg + add];
12446           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12447         }
12448       break;
12449     default:
12450       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12451       return;
12452     }
12453   oappend_register (ins, s);
12454 }
12455
12456 static void
12457 OP_IMREG (instr_info *ins, int code, int sizeflag)
12458 {
12459   const char *s;
12460
12461   switch (code)
12462     {
12463     case indir_dx_reg:
12464       if (!ins->intel_syntax)
12465         {
12466           oappend (ins, "(%dx)");
12467           return;
12468         }
12469       s = att_names16[dx_reg - ax_reg];
12470       break;
12471     case al_reg: case cl_reg:
12472       s = att_names8[code - al_reg];
12473       break;
12474     case eAX_reg:
12475       USED_REX (REX_W);
12476       if (ins->rex & REX_W)
12477         {
12478           s = *att_names64;
12479           break;
12480         }
12481       /* Fall through.  */
12482     case z_mode_ax_reg:
12483       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12484         s = *att_names32;
12485       else
12486         s = *att_names16;
12487       if (!(ins->rex & REX_W))
12488         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12489       break;
12490     default:
12491       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12492       return;
12493     }
12494   oappend_register (ins, s);
12495 }
12496
12497 static void
12498 OP_I (instr_info *ins, int bytemode, int sizeflag)
12499 {
12500   bfd_signed_vma op;
12501   bfd_signed_vma mask = -1;
12502
12503   switch (bytemode)
12504     {
12505     case b_mode:
12506       FETCH_DATA (ins->info, ins->codep + 1);
12507       op = *ins->codep++;
12508       mask = 0xff;
12509       break;
12510     case v_mode:
12511       USED_REX (REX_W);
12512       if (ins->rex & REX_W)
12513         op = get32s (ins);
12514       else
12515         {
12516           if (sizeflag & DFLAG)
12517             {
12518               op = get32 (ins);
12519               mask = 0xffffffff;
12520             }
12521           else
12522             {
12523               op = get16 (ins);
12524               mask = 0xfffff;
12525             }
12526           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12527         }
12528       break;
12529     case d_mode:
12530       mask = 0xffffffff;
12531       op = get32 (ins);
12532       break;
12533     case w_mode:
12534       mask = 0xfffff;
12535       op = get16 (ins);
12536       break;
12537     case const_1_mode:
12538       if (ins->intel_syntax)
12539         oappend (ins, "1");
12540       return;
12541     default:
12542       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12543       return;
12544     }
12545
12546   op &= mask;
12547   oappend_immediate (ins, op);
12548 }
12549
12550 static void
12551 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12552 {
12553   if (bytemode != v_mode || ins->address_mode != mode_64bit
12554       || !(ins->rex & REX_W))
12555     {
12556       OP_I (ins, bytemode, sizeflag);
12557       return;
12558     }
12559
12560   USED_REX (REX_W);
12561
12562   oappend_immediate (ins, get64 (ins));
12563 }
12564
12565 static void
12566 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12567 {
12568   bfd_signed_vma op;
12569
12570   switch (bytemode)
12571     {
12572     case b_mode:
12573     case b_T_mode:
12574       FETCH_DATA (ins->info, ins->codep + 1);
12575       op = *ins->codep++;
12576       if ((op & 0x80) != 0)
12577         op -= 0x100;
12578       if (bytemode == b_T_mode)
12579         {
12580           if (ins->address_mode != mode_64bit
12581               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12582             {
12583               /* The operand-size prefix is overridden by a REX prefix.  */
12584               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12585                 op &= 0xffffffff;
12586               else
12587                 op &= 0xffff;
12588           }
12589         }
12590       else
12591         {
12592           if (!(ins->rex & REX_W))
12593             {
12594               if (sizeflag & DFLAG)
12595                 op &= 0xffffffff;
12596               else
12597                 op &= 0xffff;
12598             }
12599         }
12600       break;
12601     case v_mode:
12602       /* The operand-size prefix is overridden by a REX prefix.  */
12603       if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12604         op = get32s (ins);
12605       else
12606         op = get16 (ins);
12607       break;
12608     default:
12609       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12610       return;
12611     }
12612
12613   oappend_immediate (ins, op);
12614 }
12615
12616 static void
12617 OP_J (instr_info *ins, int bytemode, int sizeflag)
12618 {
12619   bfd_vma disp;
12620   bfd_vma mask = -1;
12621   bfd_vma segment = 0;
12622
12623   switch (bytemode)
12624     {
12625     case b_mode:
12626       FETCH_DATA (ins->info, ins->codep + 1);
12627       disp = *ins->codep++;
12628       if ((disp & 0x80) != 0)
12629         disp -= 0x100;
12630       break;
12631     case v_mode:
12632     case dqw_mode:
12633       if ((sizeflag & DFLAG)
12634           || (ins->address_mode == mode_64bit
12635               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12636                   || (ins->rex & REX_W))))
12637         disp = get32s (ins);
12638       else
12639         {
12640           disp = get16 (ins);
12641           if ((disp & 0x8000) != 0)
12642             disp -= 0x10000;
12643           /* In 16bit mode, address is wrapped around at 64k within
12644              the same segment.  Otherwise, a data16 prefix on a jump
12645              instruction means that the pc is masked to 16 bits after
12646              the displacement is added!  */
12647           mask = 0xffff;
12648           if ((ins->prefixes & PREFIX_DATA) == 0)
12649             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12650                        & ~((bfd_vma) 0xffff));
12651         }
12652       if (ins->address_mode != mode_64bit
12653           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12654         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12655       break;
12656     default:
12657       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12658       return;
12659     }
12660   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12661          | segment;
12662   set_op (ins, disp, false);
12663   print_operand_value (ins, disp, dis_style_text);
12664 }
12665
12666 static void
12667 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12668 {
12669   if (bytemode == w_mode)
12670     oappend_register (ins, att_names_seg[ins->modrm.reg]);
12671   else
12672     OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12673 }
12674
12675 static void
12676 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12677 {
12678   int seg, offset, res;
12679   char scratch[24];
12680
12681   if (sizeflag & DFLAG)
12682     {
12683       offset = get32 (ins);
12684       seg = get16 (ins);
12685     }
12686   else
12687     {
12688       offset = get16 (ins);
12689       seg = get16 (ins);
12690     }
12691   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12692
12693   res = snprintf (scratch, ARRAY_SIZE (scratch),
12694                   ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12695                   seg, offset);
12696   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12697     abort ();
12698   oappend (ins, scratch);
12699 }
12700
12701 static void
12702 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12703 {
12704   bfd_vma off;
12705
12706   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12707     intel_operand_size (ins, bytemode, sizeflag);
12708   append_seg (ins);
12709
12710   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12711     off = get32 (ins);
12712   else
12713     off = get16 (ins);
12714
12715   if (ins->intel_syntax)
12716     {
12717       if (!ins->active_seg_prefix)
12718         {
12719           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12720           oappend (ins, ":");
12721         }
12722     }
12723   print_operand_value (ins, off, dis_style_address_offset);
12724 }
12725
12726 static void
12727 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12728 {
12729   bfd_vma off;
12730
12731   if (ins->address_mode != mode_64bit
12732       || (ins->prefixes & PREFIX_ADDR))
12733     {
12734       OP_OFF (ins, bytemode, sizeflag);
12735       return;
12736     }
12737
12738   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12739     intel_operand_size (ins, bytemode, sizeflag);
12740   append_seg (ins);
12741
12742   off = get64 (ins);
12743
12744   if (ins->intel_syntax)
12745     {
12746       if (!ins->active_seg_prefix)
12747         {
12748           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12749           oappend (ins, ":");
12750         }
12751     }
12752   print_operand_value (ins, off, dis_style_address_offset);
12753 }
12754
12755 static void
12756 ptr_reg (instr_info *ins, int code, int sizeflag)
12757 {
12758   const char *s;
12759
12760   *ins->obufp++ = ins->open_char;
12761   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12762   if (ins->address_mode == mode_64bit)
12763     {
12764       if (!(sizeflag & AFLAG))
12765         s = att_names32[code - eAX_reg];
12766       else
12767         s = att_names64[code - eAX_reg];
12768     }
12769   else if (sizeflag & AFLAG)
12770     s = att_names32[code - eAX_reg];
12771   else
12772     s = att_names16[code - eAX_reg];
12773   oappend_register (ins, s);
12774   oappend_char (ins, ins->close_char);
12775 }
12776
12777 static void
12778 OP_ESreg (instr_info *ins, int code, int sizeflag)
12779 {
12780   if (ins->intel_syntax)
12781     {
12782       switch (ins->codep[-1])
12783         {
12784         case 0x6d:      /* insw/insl */
12785           intel_operand_size (ins, z_mode, sizeflag);
12786           break;
12787         case 0xa5:      /* movsw/movsl/movsq */
12788         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12789         case 0xab:      /* stosw/stosl */
12790         case 0xaf:      /* scasw/scasl */
12791           intel_operand_size (ins, v_mode, sizeflag);
12792           break;
12793         default:
12794           intel_operand_size (ins, b_mode, sizeflag);
12795         }
12796     }
12797   oappend_register (ins, "%es");
12798   oappend_char (ins, ':');
12799   ptr_reg (ins, code, sizeflag);
12800 }
12801
12802 static void
12803 OP_DSreg (instr_info *ins, int code, int sizeflag)
12804 {
12805   if (ins->intel_syntax)
12806     {
12807       switch (ins->codep[-1])
12808         {
12809         case 0x6f:      /* outsw/outsl */
12810           intel_operand_size (ins, z_mode, sizeflag);
12811           break;
12812         case 0xa5:      /* movsw/movsl/movsq */
12813         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12814         case 0xad:      /* lodsw/lodsl/lodsq */
12815           intel_operand_size (ins, v_mode, sizeflag);
12816           break;
12817         default:
12818           intel_operand_size (ins, b_mode, sizeflag);
12819         }
12820     }
12821   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12822      default segment register DS is printed.  */
12823   if (!ins->active_seg_prefix)
12824     ins->active_seg_prefix = PREFIX_DS;
12825   append_seg (ins);
12826   ptr_reg (ins, code, sizeflag);
12827 }
12828
12829 static void
12830 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12831       int sizeflag ATTRIBUTE_UNUSED)
12832 {
12833   int add, res;
12834   char scratch[8];
12835
12836   if (ins->rex & REX_R)
12837     {
12838       USED_REX (REX_R);
12839       add = 8;
12840     }
12841   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12842     {
12843       ins->all_prefixes[ins->last_lock_prefix] = 0;
12844       ins->used_prefixes |= PREFIX_LOCK;
12845       add = 8;
12846     }
12847   else
12848     add = 0;
12849   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12850                   ins->modrm.reg + add);
12851   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12852     abort ();
12853   oappend_register (ins, scratch);
12854 }
12855
12856 static void
12857 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12858       int sizeflag ATTRIBUTE_UNUSED)
12859 {
12860   int add, res;
12861   char scratch[8];
12862
12863   USED_REX (REX_R);
12864   if (ins->rex & REX_R)
12865     add = 8;
12866   else
12867     add = 0;
12868   res = snprintf (scratch, ARRAY_SIZE (scratch),
12869                   ins->intel_syntax ? "dr%d" : "%%db%d",
12870                   ins->modrm.reg + add);
12871   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12872     abort ();
12873   oappend (ins, scratch);
12874 }
12875
12876 static void
12877 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12878       int sizeflag ATTRIBUTE_UNUSED)
12879 {
12880   int res;
12881   char scratch[8];
12882
12883   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12884   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12885     abort ();
12886   oappend_register (ins, scratch);
12887 }
12888
12889 static void
12890 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12891         int sizeflag ATTRIBUTE_UNUSED)
12892 {
12893   int reg = ins->modrm.reg;
12894   const char *const *names;
12895
12896   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12897   if (ins->prefixes & PREFIX_DATA)
12898     {
12899       names = att_names_xmm;
12900       USED_REX (REX_R);
12901       if (ins->rex & REX_R)
12902         reg += 8;
12903     }
12904   else
12905     names = att_names_mm;
12906   oappend_register (ins, names[reg]);
12907 }
12908
12909 static void
12910 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12911 {
12912   const char *const *names;
12913
12914   if (bytemode == xmmq_mode
12915       || bytemode == evex_half_bcst_xmmqh_mode
12916       || bytemode == evex_half_bcst_xmmq_mode)
12917     {
12918       switch (ins->vex.length)
12919         {
12920         case 128:
12921         case 256:
12922           names = att_names_xmm;
12923           break;
12924         case 512:
12925           names = att_names_ymm;
12926           ins->evex_used |= EVEX_len_used;
12927           break;
12928         default:
12929           abort ();
12930         }
12931     }
12932   else if (bytemode == ymm_mode)
12933     names = att_names_ymm;
12934   else if (bytemode == tmm_mode)
12935     {
12936       if (reg >= 8)
12937         {
12938           oappend (ins, "(bad)");
12939           return;
12940         }
12941       names = att_names_tmm;
12942     }
12943   else if (ins->need_vex
12944            && bytemode != xmm_mode
12945            && bytemode != scalar_mode
12946            && bytemode != xmmdw_mode
12947            && bytemode != xmmqd_mode
12948            && bytemode != evex_half_bcst_xmmqdh_mode
12949            && bytemode != w_swap_mode
12950            && bytemode != b_mode
12951            && bytemode != w_mode
12952            && bytemode != d_mode
12953            && bytemode != q_mode)
12954     {
12955       ins->evex_used |= EVEX_len_used;
12956       switch (ins->vex.length)
12957         {
12958         case 128:
12959           names = att_names_xmm;
12960           break;
12961         case 256:
12962           if (ins->vex.w
12963               || bytemode != vex_vsib_q_w_dq_mode)
12964             names = att_names_ymm;
12965           else
12966             names = att_names_xmm;
12967           break;
12968         case 512:
12969           if (ins->vex.w
12970               || bytemode != vex_vsib_q_w_dq_mode)
12971             names = att_names_zmm;
12972           else
12973             names = att_names_ymm;
12974           break;
12975         default:
12976           abort ();
12977         }
12978     }
12979   else
12980     names = att_names_xmm;
12981   oappend_register (ins, names[reg]);
12982 }
12983
12984 static void
12985 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12986 {
12987   unsigned int reg = ins->modrm.reg;
12988
12989   USED_REX (REX_R);
12990   if (ins->rex & REX_R)
12991     reg += 8;
12992   if (ins->vex.evex)
12993     {
12994       if (!ins->vex.r)
12995         reg += 16;
12996     }
12997
12998   if (bytemode == tmm_mode)
12999     ins->modrm.reg = reg;
13000   else if (bytemode == scalar_mode)
13001     ins->vex.no_broadcast = true;
13002
13003   print_vector_reg (ins, reg, bytemode);
13004 }
13005
13006 static void
13007 OP_EM (instr_info *ins, int bytemode, int sizeflag)
13008 {
13009   int reg;
13010   const char *const *names;
13011
13012   if (ins->modrm.mod != 3)
13013     {
13014       if (ins->intel_syntax
13015           && (bytemode == v_mode || bytemode == v_swap_mode))
13016         {
13017           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13018           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13019         }
13020       OP_E (ins, bytemode, sizeflag);
13021       return;
13022     }
13023
13024   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13025     swap_operand (ins);
13026
13027   /* Skip mod/rm byte.  */
13028   MODRM_CHECK;
13029   ins->codep++;
13030   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13031   reg = ins->modrm.rm;
13032   if (ins->prefixes & PREFIX_DATA)
13033     {
13034       names = att_names_xmm;
13035       USED_REX (REX_B);
13036       if (ins->rex & REX_B)
13037         reg += 8;
13038     }
13039   else
13040     names = att_names_mm;
13041   oappend_register (ins, names[reg]);
13042 }
13043
13044 /* cvt* are the only instructions in sse2 which have
13045    both SSE and MMX operands and also have 0x66 prefix
13046    in their opcode. 0x66 was originally used to differentiate
13047    between SSE and MMX instruction(operands). So we have to handle the
13048    cvt* separately using OP_EMC and OP_MXC */
13049 static void
13050 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13051 {
13052   if (ins->modrm.mod != 3)
13053     {
13054       if (ins->intel_syntax && bytemode == v_mode)
13055         {
13056           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13057           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13058         }
13059       OP_E (ins, bytemode, sizeflag);
13060       return;
13061     }
13062
13063   /* Skip mod/rm byte.  */
13064   MODRM_CHECK;
13065   ins->codep++;
13066   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13067   oappend_register (ins, att_names_mm[ins->modrm.rm]);
13068 }
13069
13070 static void
13071 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13072         int sizeflag ATTRIBUTE_UNUSED)
13073 {
13074   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13075   oappend_register (ins, att_names_mm[ins->modrm.reg]);
13076 }
13077
13078 static void
13079 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13080 {
13081   int reg;
13082
13083   /* Skip mod/rm byte.  */
13084   MODRM_CHECK;
13085   ins->codep++;
13086
13087   if (bytemode == dq_mode)
13088     bytemode = ins->vex.w ? q_mode : d_mode;
13089
13090   if (ins->modrm.mod != 3)
13091     {
13092       OP_E_memory (ins, bytemode, sizeflag);
13093       return;
13094     }
13095
13096   reg = ins->modrm.rm;
13097   USED_REX (REX_B);
13098   if (ins->rex & REX_B)
13099     reg += 8;
13100   if (ins->vex.evex)
13101     {
13102       USED_REX (REX_X);
13103       if ((ins->rex & REX_X))
13104         reg += 16;
13105     }
13106
13107   if ((sizeflag & SUFFIX_ALWAYS)
13108       && (bytemode == x_swap_mode
13109           || bytemode == w_swap_mode
13110           || bytemode == d_swap_mode
13111           || bytemode == q_swap_mode))
13112     swap_operand (ins);
13113
13114   if (bytemode == tmm_mode)
13115     ins->modrm.rm = reg;
13116
13117   print_vector_reg (ins, reg, bytemode);
13118 }
13119
13120 static void
13121 OP_MS (instr_info *ins, int bytemode, int sizeflag)
13122 {
13123   if (ins->modrm.mod == 3)
13124     OP_EM (ins, bytemode, sizeflag);
13125   else
13126     BadOp (ins);
13127 }
13128
13129 static void
13130 OP_XS (instr_info *ins, int bytemode, int sizeflag)
13131 {
13132   if (ins->modrm.mod == 3)
13133     OP_EX (ins, bytemode, sizeflag);
13134   else
13135     BadOp (ins);
13136 }
13137
13138 static void
13139 OP_M (instr_info *ins, int bytemode, int sizeflag)
13140 {
13141   if (ins->modrm.mod == 3)
13142     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13143     BadOp (ins);
13144   else
13145     OP_E (ins, bytemode, sizeflag);
13146 }
13147
13148 static void
13149 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13150 {
13151   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13152     BadOp (ins);
13153   else
13154     OP_E (ins, bytemode, sizeflag);
13155 }
13156
13157 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13158    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13159
13160 static void
13161 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13162 {
13163   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13164     ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13165   else if (opnd == 0)
13166     OP_REG (ins, eAX_reg, sizeflag);
13167   else
13168     OP_IMREG (ins, eAX_reg, sizeflag);
13169 }
13170
13171 static const char *const Suffix3DNow[] = {
13172 /* 00 */        NULL,           NULL,           NULL,           NULL,
13173 /* 04 */        NULL,           NULL,           NULL,           NULL,
13174 /* 08 */        NULL,           NULL,           NULL,           NULL,
13175 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13176 /* 10 */        NULL,           NULL,           NULL,           NULL,
13177 /* 14 */        NULL,           NULL,           NULL,           NULL,
13178 /* 18 */        NULL,           NULL,           NULL,           NULL,
13179 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13180 /* 20 */        NULL,           NULL,           NULL,           NULL,
13181 /* 24 */        NULL,           NULL,           NULL,           NULL,
13182 /* 28 */        NULL,           NULL,           NULL,           NULL,
13183 /* 2C */        NULL,           NULL,           NULL,           NULL,
13184 /* 30 */        NULL,           NULL,           NULL,           NULL,
13185 /* 34 */        NULL,           NULL,           NULL,           NULL,
13186 /* 38 */        NULL,           NULL,           NULL,           NULL,
13187 /* 3C */        NULL,           NULL,           NULL,           NULL,
13188 /* 40 */        NULL,           NULL,           NULL,           NULL,
13189 /* 44 */        NULL,           NULL,           NULL,           NULL,
13190 /* 48 */        NULL,           NULL,           NULL,           NULL,
13191 /* 4C */        NULL,           NULL,           NULL,           NULL,
13192 /* 50 */        NULL,           NULL,           NULL,           NULL,
13193 /* 54 */        NULL,           NULL,           NULL,           NULL,
13194 /* 58 */        NULL,           NULL,           NULL,           NULL,
13195 /* 5C */        NULL,           NULL,           NULL,           NULL,
13196 /* 60 */        NULL,           NULL,           NULL,           NULL,
13197 /* 64 */        NULL,           NULL,           NULL,           NULL,
13198 /* 68 */        NULL,           NULL,           NULL,           NULL,
13199 /* 6C */        NULL,           NULL,           NULL,           NULL,
13200 /* 70 */        NULL,           NULL,           NULL,           NULL,
13201 /* 74 */        NULL,           NULL,           NULL,           NULL,
13202 /* 78 */        NULL,           NULL,           NULL,           NULL,
13203 /* 7C */        NULL,           NULL,           NULL,           NULL,
13204 /* 80 */        NULL,           NULL,           NULL,           NULL,
13205 /* 84 */        NULL,           NULL,           NULL,           NULL,
13206 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13207 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13208 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13209 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13210 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13211 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13212 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13213 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13214 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13215 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13216 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13217 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13218 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13219 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13220 /* C0 */        NULL,           NULL,           NULL,           NULL,
13221 /* C4 */        NULL,           NULL,           NULL,           NULL,
13222 /* C8 */        NULL,           NULL,           NULL,           NULL,
13223 /* CC */        NULL,           NULL,           NULL,           NULL,
13224 /* D0 */        NULL,           NULL,           NULL,           NULL,
13225 /* D4 */        NULL,           NULL,           NULL,           NULL,
13226 /* D8 */        NULL,           NULL,           NULL,           NULL,
13227 /* DC */        NULL,           NULL,           NULL,           NULL,
13228 /* E0 */        NULL,           NULL,           NULL,           NULL,
13229 /* E4 */        NULL,           NULL,           NULL,           NULL,
13230 /* E8 */        NULL,           NULL,           NULL,           NULL,
13231 /* EC */        NULL,           NULL,           NULL,           NULL,
13232 /* F0 */        NULL,           NULL,           NULL,           NULL,
13233 /* F4 */        NULL,           NULL,           NULL,           NULL,
13234 /* F8 */        NULL,           NULL,           NULL,           NULL,
13235 /* FC */        NULL,           NULL,           NULL,           NULL,
13236 };
13237
13238 static void
13239 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13240                 int sizeflag ATTRIBUTE_UNUSED)
13241 {
13242   const char *mnemonic;
13243
13244   FETCH_DATA (ins->info, ins->codep + 1);
13245   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13246      place where an 8-bit immediate would normally go.  ie. the last
13247      byte of the instruction.  */
13248   ins->obufp = ins->mnemonicendp;
13249   mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
13250   if (mnemonic)
13251     ins->obufp = stpcpy (ins->obufp, mnemonic);
13252   else
13253     {
13254       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13255          of the opcode (0x0f0f) and the opcode suffix, we need to do
13256          all the ins->modrm processing first, and don't know until now that
13257          we have a bad opcode.  This necessitates some cleaning up.  */
13258       ins->op_out[0][0] = '\0';
13259       ins->op_out[1][0] = '\0';
13260       BadOp (ins);
13261     }
13262   ins->mnemonicendp = ins->obufp;
13263 }
13264
13265 static const struct op simd_cmp_op[] =
13266 {
13267   { STRING_COMMA_LEN ("eq") },
13268   { STRING_COMMA_LEN ("lt") },
13269   { STRING_COMMA_LEN ("le") },
13270   { STRING_COMMA_LEN ("unord") },
13271   { STRING_COMMA_LEN ("neq") },
13272   { STRING_COMMA_LEN ("nlt") },
13273   { STRING_COMMA_LEN ("nle") },
13274   { STRING_COMMA_LEN ("ord") }
13275 };
13276
13277 static const struct op vex_cmp_op[] =
13278 {
13279   { STRING_COMMA_LEN ("eq_uq") },
13280   { STRING_COMMA_LEN ("nge") },
13281   { STRING_COMMA_LEN ("ngt") },
13282   { STRING_COMMA_LEN ("false") },
13283   { STRING_COMMA_LEN ("neq_oq") },
13284   { STRING_COMMA_LEN ("ge") },
13285   { STRING_COMMA_LEN ("gt") },
13286   { STRING_COMMA_LEN ("true") },
13287   { STRING_COMMA_LEN ("eq_os") },
13288   { STRING_COMMA_LEN ("lt_oq") },
13289   { STRING_COMMA_LEN ("le_oq") },
13290   { STRING_COMMA_LEN ("unord_s") },
13291   { STRING_COMMA_LEN ("neq_us") },
13292   { STRING_COMMA_LEN ("nlt_uq") },
13293   { STRING_COMMA_LEN ("nle_uq") },
13294   { STRING_COMMA_LEN ("ord_s") },
13295   { STRING_COMMA_LEN ("eq_us") },
13296   { STRING_COMMA_LEN ("nge_uq") },
13297   { STRING_COMMA_LEN ("ngt_uq") },
13298   { STRING_COMMA_LEN ("false_os") },
13299   { STRING_COMMA_LEN ("neq_os") },
13300   { STRING_COMMA_LEN ("ge_oq") },
13301   { STRING_COMMA_LEN ("gt_oq") },
13302   { STRING_COMMA_LEN ("true_us") },
13303 };
13304
13305 static void
13306 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13307            int sizeflag ATTRIBUTE_UNUSED)
13308 {
13309   unsigned int cmp_type;
13310
13311   FETCH_DATA (ins->info, ins->codep + 1);
13312   cmp_type = *ins->codep++ & 0xff;
13313   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13314     {
13315       char suffix[3];
13316       char *p = ins->mnemonicendp - 2;
13317       suffix[0] = p[0];
13318       suffix[1] = p[1];
13319       suffix[2] = '\0';
13320       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13321       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13322     }
13323   else if (ins->need_vex
13324            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13325     {
13326       char suffix[3];
13327       char *p = ins->mnemonicendp - 2;
13328       suffix[0] = p[0];
13329       suffix[1] = p[1];
13330       suffix[2] = '\0';
13331       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13332       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13333       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13334     }
13335   else
13336     {
13337       /* We have a reserved extension byte.  Output it directly.  */
13338       oappend_immediate (ins, cmp_type);
13339     }
13340 }
13341
13342 static void
13343 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13344 {
13345   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13346   if (!ins->intel_syntax)
13347     {
13348       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13349       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13350       if (bytemode == eBX_reg)
13351         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13352       ins->two_source_ops = true;
13353     }
13354   /* Skip mod/rm byte.  */
13355   MODRM_CHECK;
13356   ins->codep++;
13357 }
13358
13359 static void
13360 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13361             int sizeflag ATTRIBUTE_UNUSED)
13362 {
13363   /* monitor %{e,r,}ax,%ecx,%edx"  */
13364   if (!ins->intel_syntax)
13365     {
13366       const char *const *names = (ins->address_mode == mode_64bit
13367                                   ? att_names64 : att_names32);
13368
13369       if (ins->prefixes & PREFIX_ADDR)
13370         {
13371           /* Remove "addr16/addr32".  */
13372           ins->all_prefixes[ins->last_addr_prefix] = 0;
13373           names = (ins->address_mode != mode_32bit
13374                    ? att_names32 : att_names16);
13375           ins->used_prefixes |= PREFIX_ADDR;
13376         }
13377       else if (ins->address_mode == mode_16bit)
13378         names = att_names16;
13379       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13380       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13381       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13382       ins->two_source_ops = true;
13383     }
13384   /* Skip mod/rm byte.  */
13385   MODRM_CHECK;
13386   ins->codep++;
13387 }
13388
13389 static void
13390 BadOp (instr_info *ins)
13391 {
13392   /* Throw away prefixes and 1st. opcode byte.  */
13393   ins->codep = ins->insn_codep + 1;
13394   ins->obufp = stpcpy (ins->obufp, "(bad)");
13395 }
13396
13397 static void
13398 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13399 {
13400   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13401      lods and stos.  */
13402   if (ins->prefixes & PREFIX_REPZ)
13403     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13404
13405   switch (bytemode)
13406     {
13407     case al_reg:
13408     case eAX_reg:
13409     case indir_dx_reg:
13410       OP_IMREG (ins, bytemode, sizeflag);
13411       break;
13412     case eDI_reg:
13413       OP_ESreg (ins, bytemode, sizeflag);
13414       break;
13415     case eSI_reg:
13416       OP_DSreg (ins, bytemode, sizeflag);
13417       break;
13418     default:
13419       abort ();
13420       break;
13421     }
13422 }
13423
13424 static void
13425 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13426            int sizeflag ATTRIBUTE_UNUSED)
13427 {
13428   if (ins->isa64 != amd64)
13429     return;
13430
13431   ins->obufp = ins->obuf;
13432   BadOp (ins);
13433   ins->mnemonicendp = ins->obufp;
13434   ++ins->codep;
13435 }
13436
13437 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13438    "bnd".  */
13439
13440 static void
13441 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13442            int sizeflag ATTRIBUTE_UNUSED)
13443 {
13444   if (ins->prefixes & PREFIX_REPNZ)
13445     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13446 }
13447
13448 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13449    "notrack".  */
13450
13451 static void
13452 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13453                int sizeflag ATTRIBUTE_UNUSED)
13454 {
13455   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13456      we've seen a PREFIX_DS.  */
13457   if ((ins->prefixes & PREFIX_DS) != 0
13458       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13459     {
13460       /* NOTRACK prefix is only valid on indirect branch instructions.
13461          NB: DATA prefix is unsupported for Intel64.  */
13462       ins->active_seg_prefix = 0;
13463       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13464     }
13465 }
13466
13467 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13468    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13469  */
13470
13471 static void
13472 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13473 {
13474   if (ins->modrm.mod != 3
13475       && (ins->prefixes & PREFIX_LOCK) != 0)
13476     {
13477       if (ins->prefixes & PREFIX_REPZ)
13478         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13479       if (ins->prefixes & PREFIX_REPNZ)
13480         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13481     }
13482
13483   OP_E (ins, bytemode, sizeflag);
13484 }
13485
13486 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13487    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13488  */
13489
13490 static void
13491 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13492 {
13493   if (ins->modrm.mod != 3)
13494     {
13495       if (ins->prefixes & PREFIX_REPZ)
13496         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13497       if (ins->prefixes & PREFIX_REPNZ)
13498         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13499     }
13500
13501   OP_E (ins, bytemode, sizeflag);
13502 }
13503
13504 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13505    "xrelease" for memory operand.  No check for LOCK prefix.   */
13506
13507 static void
13508 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13509 {
13510   if (ins->modrm.mod != 3
13511       && ins->last_repz_prefix > ins->last_repnz_prefix
13512       && (ins->prefixes & PREFIX_REPZ) != 0)
13513     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13514
13515   OP_E (ins, bytemode, sizeflag);
13516 }
13517
13518 static void
13519 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13520 {
13521   USED_REX (REX_W);
13522   if (ins->rex & REX_W)
13523     {
13524       /* Change cmpxchg8b to cmpxchg16b.  */
13525       char *p = ins->mnemonicendp - 2;
13526       ins->mnemonicendp = stpcpy (p, "16b");
13527       bytemode = o_mode;
13528     }
13529   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13530     {
13531       if (ins->prefixes & PREFIX_REPZ)
13532         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13533       if (ins->prefixes & PREFIX_REPNZ)
13534         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13535     }
13536
13537   OP_M (ins, bytemode, sizeflag);
13538 }
13539
13540 static void
13541 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13542 {
13543   const char *const *names = att_names_xmm;
13544
13545   if (ins->need_vex)
13546     {
13547       switch (ins->vex.length)
13548         {
13549         case 128:
13550           break;
13551         case 256:
13552           names = att_names_ymm;
13553           break;
13554         default:
13555           abort ();
13556         }
13557     }
13558   oappend_register (ins, names[reg]);
13559 }
13560
13561 static void
13562 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13563 {
13564   /* Add proper suffix to "fxsave" and "fxrstor".  */
13565   USED_REX (REX_W);
13566   if (ins->rex & REX_W)
13567     {
13568       char *p = ins->mnemonicendp;
13569       *p++ = '6';
13570       *p++ = '4';
13571       *p = '\0';
13572       ins->mnemonicendp = p;
13573     }
13574   OP_M (ins, bytemode, sizeflag);
13575 }
13576
13577 /* Display the destination register operand for instructions with
13578    VEX. */
13579
13580 static void
13581 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13582 {
13583   int reg, modrm_reg, sib_index = -1;
13584   const char *const *names;
13585
13586   if (!ins->need_vex)
13587     abort ();
13588
13589   reg = ins->vex.register_specifier;
13590   ins->vex.register_specifier = 0;
13591   if (ins->address_mode != mode_64bit)
13592     {
13593       if (ins->vex.evex && !ins->vex.v)
13594         {
13595           oappend (ins, "(bad)");
13596           return;
13597         }
13598
13599       reg &= 7;
13600     }
13601   else if (ins->vex.evex && !ins->vex.v)
13602     reg += 16;
13603
13604   switch (bytemode)
13605     {
13606     case scalar_mode:
13607       oappend_register (ins, att_names_xmm[reg]);
13608       return;
13609
13610     case vex_vsib_d_w_dq_mode:
13611     case vex_vsib_q_w_dq_mode:
13612       /* This must be the 3rd operand.  */
13613       if (ins->obufp != ins->op_out[2])
13614         abort ();
13615       if (ins->vex.length == 128
13616           || (bytemode != vex_vsib_d_w_dq_mode
13617               && !ins->vex.w))
13618         oappend_register (ins, att_names_xmm[reg]);
13619       else
13620         oappend_register (ins, att_names_ymm[reg]);
13621
13622       /* All 3 XMM/YMM registers must be distinct.  */
13623       modrm_reg = ins->modrm.reg;
13624       if (ins->rex & REX_R)
13625         modrm_reg += 8;
13626
13627       if (ins->has_sib && ins->modrm.rm == 4)
13628         {
13629           sib_index = ins->sib.index;
13630           if (ins->rex & REX_X)
13631             sib_index += 8;
13632         }
13633
13634       if (reg == modrm_reg || reg == sib_index)
13635         strcpy (ins->obufp, "/(bad)");
13636       if (modrm_reg == sib_index || modrm_reg == reg)
13637         strcat (ins->op_out[0], "/(bad)");
13638       if (sib_index == modrm_reg || sib_index == reg)
13639         strcat (ins->op_out[1], "/(bad)");
13640
13641       return;
13642
13643     case tmm_mode:
13644       /* All 3 TMM registers must be distinct.  */
13645       if (reg >= 8)
13646         oappend (ins, "(bad)");
13647       else
13648         {
13649           /* This must be the 3rd operand.  */
13650           if (ins->obufp != ins->op_out[2])
13651             abort ();
13652           oappend_register (ins, att_names_tmm[reg]);
13653           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13654             strcpy (ins->obufp, "/(bad)");
13655         }
13656
13657       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13658           || ins->modrm.rm == reg)
13659         {
13660           if (ins->modrm.reg <= 8
13661               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13662             strcat (ins->op_out[0], "/(bad)");
13663           if (ins->modrm.rm <= 8
13664               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13665             strcat (ins->op_out[1], "/(bad)");
13666         }
13667
13668       return;
13669     }
13670
13671   switch (ins->vex.length)
13672     {
13673     case 128:
13674       switch (bytemode)
13675         {
13676         case x_mode:
13677           names = att_names_xmm;
13678           ins->evex_used |= EVEX_len_used;
13679           break;
13680         case dq_mode:
13681           if (ins->rex & REX_W)
13682             names = att_names64;
13683           else
13684             names = att_names32;
13685           break;
13686         case mask_bd_mode:
13687         case mask_mode:
13688           if (reg > 0x7)
13689             {
13690               oappend (ins, "(bad)");
13691               return;
13692             }
13693           names = att_names_mask;
13694           break;
13695         default:
13696           abort ();
13697           return;
13698         }
13699       break;
13700     case 256:
13701       switch (bytemode)
13702         {
13703         case x_mode:
13704           names = att_names_ymm;
13705           ins->evex_used |= EVEX_len_used;
13706           break;
13707         case mask_bd_mode:
13708         case mask_mode:
13709           if (reg > 0x7)
13710             {
13711               oappend (ins, "(bad)");
13712               return;
13713             }
13714           names = att_names_mask;
13715           break;
13716         default:
13717           /* See PR binutils/20893 for a reproducer.  */
13718           oappend (ins, "(bad)");
13719           return;
13720         }
13721       break;
13722     case 512:
13723       names = att_names_zmm;
13724       ins->evex_used |= EVEX_len_used;
13725       break;
13726     default:
13727       abort ();
13728       break;
13729     }
13730   oappend_register (ins, names[reg]);
13731 }
13732
13733 static void
13734 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13735 {
13736   if (ins->modrm.mod == 3)
13737     OP_VEX (ins, bytemode, sizeflag);
13738 }
13739
13740 static void
13741 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13742 {
13743   OP_VEX (ins, bytemode, sizeflag);
13744
13745   if (ins->vex.w)
13746     {
13747       /* Swap 2nd and 3rd operands.  */
13748       char *tmp = ins->op_out[2];
13749
13750       ins->op_out[2] = ins->op_out[1];
13751       ins->op_out[1] = tmp;
13752     }
13753 }
13754
13755 static void
13756 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13757 {
13758   int reg;
13759   const char *const *names = att_names_xmm;
13760
13761   FETCH_DATA (ins->info, ins->codep + 1);
13762   reg = *ins->codep++;
13763
13764   if (bytemode != x_mode && bytemode != scalar_mode)
13765     abort ();
13766
13767   reg >>= 4;
13768   if (ins->address_mode != mode_64bit)
13769     reg &= 7;
13770
13771   if (bytemode == x_mode && ins->vex.length == 256)
13772     names = att_names_ymm;
13773
13774   oappend_register (ins, names[reg]);
13775
13776   if (ins->vex.w)
13777     {
13778       /* Swap 3rd and 4th operands.  */
13779       char *tmp = ins->op_out[3];
13780
13781       ins->op_out[3] = ins->op_out[2];
13782       ins->op_out[2] = tmp;
13783     }
13784 }
13785
13786 static void
13787 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13788           int sizeflag ATTRIBUTE_UNUSED)
13789 {
13790   oappend_immediate (ins, ins->codep[-1] & 0xf);
13791 }
13792
13793 static void
13794 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13795              int sizeflag ATTRIBUTE_UNUSED)
13796 {
13797   unsigned int cmp_type;
13798
13799   if (!ins->vex.evex)
13800     abort ();
13801
13802   FETCH_DATA (ins->info, ins->codep + 1);
13803   cmp_type = *ins->codep++ & 0xff;
13804   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13805      If it's the case, print suffix, otherwise - print the immediate.  */
13806   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13807       && cmp_type != 3
13808       && cmp_type != 7)
13809     {
13810       char suffix[3];
13811       char *p = ins->mnemonicendp - 2;
13812
13813       /* vpcmp* can have both one- and two-lettered suffix.  */
13814       if (p[0] == 'p')
13815         {
13816           p++;
13817           suffix[0] = p[0];
13818           suffix[1] = '\0';
13819         }
13820       else
13821         {
13822           suffix[0] = p[0];
13823           suffix[1] = p[1];
13824           suffix[2] = '\0';
13825         }
13826
13827       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13828       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13829     }
13830   else
13831     {
13832       /* We have a reserved extension byte.  Output it directly.  */
13833       oappend_immediate (ins, cmp_type);
13834     }
13835 }
13836
13837 static const struct op xop_cmp_op[] =
13838 {
13839   { STRING_COMMA_LEN ("lt") },
13840   { STRING_COMMA_LEN ("le") },
13841   { STRING_COMMA_LEN ("gt") },
13842   { STRING_COMMA_LEN ("ge") },
13843   { STRING_COMMA_LEN ("eq") },
13844   { STRING_COMMA_LEN ("neq") },
13845   { STRING_COMMA_LEN ("false") },
13846   { STRING_COMMA_LEN ("true") }
13847 };
13848
13849 static void
13850 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13851              int sizeflag ATTRIBUTE_UNUSED)
13852 {
13853   unsigned int cmp_type;
13854
13855   FETCH_DATA (ins->info, ins->codep + 1);
13856   cmp_type = *ins->codep++ & 0xff;
13857   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13858     {
13859       char suffix[3];
13860       char *p = ins->mnemonicendp - 2;
13861
13862       /* vpcom* can have both one- and two-lettered suffix.  */
13863       if (p[0] == 'm')
13864         {
13865           p++;
13866           suffix[0] = p[0];
13867           suffix[1] = '\0';
13868         }
13869       else
13870         {
13871           suffix[0] = p[0];
13872           suffix[1] = p[1];
13873           suffix[2] = '\0';
13874         }
13875
13876       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13877       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13878     }
13879   else
13880     {
13881       /* We have a reserved extension byte.  Output it directly.  */
13882       oappend_immediate (ins, cmp_type);
13883     }
13884 }
13885
13886 static const struct op pclmul_op[] =
13887 {
13888   { STRING_COMMA_LEN ("lql") },
13889   { STRING_COMMA_LEN ("hql") },
13890   { STRING_COMMA_LEN ("lqh") },
13891   { STRING_COMMA_LEN ("hqh") }
13892 };
13893
13894 static void
13895 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13896               int sizeflag ATTRIBUTE_UNUSED)
13897 {
13898   unsigned int pclmul_type;
13899
13900   FETCH_DATA (ins->info, ins->codep + 1);
13901   pclmul_type = *ins->codep++ & 0xff;
13902   switch (pclmul_type)
13903     {
13904     case 0x10:
13905       pclmul_type = 2;
13906       break;
13907     case 0x11:
13908       pclmul_type = 3;
13909       break;
13910     default:
13911       break;
13912     }
13913   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13914     {
13915       char suffix[4];
13916       char *p = ins->mnemonicendp - 3;
13917       suffix[0] = p[0];
13918       suffix[1] = p[1];
13919       suffix[2] = p[2];
13920       suffix[3] = '\0';
13921       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13922       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13923     }
13924   else
13925     {
13926       /* We have a reserved extension byte.  Output it directly.  */
13927       oappend_immediate (ins, pclmul_type);
13928     }
13929 }
13930
13931 static void
13932 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13933 {
13934   /* Add proper suffix to "movsxd".  */
13935   char *p = ins->mnemonicendp;
13936
13937   switch (bytemode)
13938     {
13939     case movsxd_mode:
13940       if (!ins->intel_syntax)
13941         {
13942           USED_REX (REX_W);
13943           if (ins->rex & REX_W)
13944             {
13945               *p++ = 'l';
13946               *p++ = 'q';
13947               break;
13948             }
13949         }
13950
13951       *p++ = 'x';
13952       *p++ = 'd';
13953       break;
13954     default:
13955       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13956       break;
13957     }
13958
13959   ins->mnemonicendp = p;
13960   *p = '\0';
13961   OP_E (ins, bytemode, sizeflag);
13962 }
13963
13964 static void
13965 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13966 {
13967   unsigned int reg = ins->vex.register_specifier;
13968   unsigned int modrm_reg = ins->modrm.reg;
13969   unsigned int modrm_rm = ins->modrm.rm;
13970
13971   /* Calc destination register number.  */
13972   if (ins->rex & REX_R)
13973     modrm_reg += 8;
13974   if (!ins->vex.r)
13975     modrm_reg += 16;
13976
13977   /* Calc src1 register number.  */
13978   if (ins->address_mode != mode_64bit)
13979     reg &= 7;
13980   else if (ins->vex.evex && !ins->vex.v)
13981     reg += 16;
13982
13983   /* Calc src2 register number.  */
13984   if (ins->modrm.mod == 3)
13985     {
13986       if (ins->rex & REX_B)
13987         modrm_rm += 8;
13988       if (ins->rex & REX_X)
13989         modrm_rm += 16;
13990     }
13991
13992   /* Destination and source registers must be distinct, output bad if
13993      dest == src1 or dest == src2.  */
13994   if (modrm_reg == reg
13995       || (ins->modrm.mod == 3
13996           && modrm_reg == modrm_rm))
13997     {
13998       oappend (ins, "(bad)");
13999     }
14000   else
14001     OP_XMM (ins, bytemode, sizeflag);
14002 }
14003
14004 static void
14005 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14006 {
14007   if (ins->modrm.mod != 3 || !ins->vex.b)
14008     return;
14009
14010   switch (bytemode)
14011     {
14012     case evex_rounding_64_mode:
14013       if (ins->address_mode != mode_64bit || !ins->vex.w)
14014         return;
14015       /* Fall through.  */
14016     case evex_rounding_mode:
14017       ins->evex_used |= EVEX_b_used;
14018       oappend (ins, names_rounding[ins->vex.ll]);
14019       break;
14020     case evex_sae_mode:
14021       ins->evex_used |= EVEX_b_used;
14022       oappend (ins, "{");
14023       break;
14024     default:
14025       abort ();
14026     }
14027   oappend (ins, "sae}");
14028 }
14029
14030 static void
14031 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14032 {
14033   if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14034     {
14035       if (ins->intel_syntax)
14036         {
14037           ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
14038         }
14039       else
14040         {
14041           USED_REX (REX_W);
14042           if (ins->rex & REX_W)
14043             ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
14044           else
14045             {
14046               if (sizeflag & DFLAG)
14047                 ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
14048               else
14049                 ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
14050               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14051             }
14052         }
14053       bytemode = v_mode;
14054     }
14055
14056   OP_M (ins, bytemode, sizeflag);
14057 }