1 /* d30v-opc.c -- D30V opcode list
2 Copyright (C) 1997-2021 Free Software Foundation, Inc.
3 Written by Martin Hunt, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/d30v.h"
26 /* This table is sorted.
27 If you add anything, it MUST be in alphabetical order.
28 The first field is the name the assembler uses when looking
29 up orcodes. The second field is the name the disassembler will use.
30 This allows the assembler to assemble references to r63 (for example)
31 or "sp". The disassembler will always use the preferred form (sp). */
32 const struct pd_reg pre_defined_registers
[] =
34 { "a0", NULL
, OPERAND_ACC
+ 0 },
35 { "a1", NULL
, OPERAND_ACC
+ 1 },
36 { "bpc", NULL
, OPERAND_CONTROL
+ 3 },
37 { "bpsw", NULL
, OPERAND_CONTROL
+ 1 },
38 { "c", "c", OPERAND_FLAG
+ 7 },
39 { "cr0", "psw", OPERAND_CONTROL
},
40 { "cr1", "bpsw", OPERAND_CONTROL
+ 1 },
41 { "cr10", "mod_s", OPERAND_CONTROL
+ 10 },
42 { "cr11", "mod_e", OPERAND_CONTROL
+ 11 },
43 { "cr12", NULL
, OPERAND_CONTROL
+ 12 },
44 { "cr13", NULL
, OPERAND_CONTROL
+ 13 },
45 { "cr14", "iba", OPERAND_CONTROL
+ 14 },
46 { "cr15", "eit_vb", OPERAND_CONTROL
+ 15 },
47 { "cr16", "int_s", OPERAND_CONTROL
+ 16 },
48 { "cr17", "int_m", OPERAND_CONTROL
+ 17 },
49 { "cr18", NULL
, OPERAND_CONTROL
+ 18 },
50 { "cr19", NULL
, OPERAND_CONTROL
+ 19 },
51 { "cr2", "pc", OPERAND_CONTROL
+ 2 },
52 { "cr20", NULL
, OPERAND_CONTROL
+ 20 },
53 { "cr21", NULL
, OPERAND_CONTROL
+ 21 },
54 { "cr22", NULL
, OPERAND_CONTROL
+ 22 },
55 { "cr23", NULL
, OPERAND_CONTROL
+ 23 },
56 { "cr24", NULL
, OPERAND_CONTROL
+ 24 },
57 { "cr25", NULL
, OPERAND_CONTROL
+ 25 },
58 { "cr26", NULL
, OPERAND_CONTROL
+ 26 },
59 { "cr27", NULL
, OPERAND_CONTROL
+ 27 },
60 { "cr28", NULL
, OPERAND_CONTROL
+ 28 },
61 { "cr29", NULL
, OPERAND_CONTROL
+ 29 },
62 { "cr3", "bpc", OPERAND_CONTROL
+ 3 },
63 { "cr30", NULL
, OPERAND_CONTROL
+ 30 },
64 { "cr31", NULL
, OPERAND_CONTROL
+ 31 },
65 { "cr32", NULL
, OPERAND_CONTROL
+ 32 },
66 { "cr33", NULL
, OPERAND_CONTROL
+ 33 },
67 { "cr34", NULL
, OPERAND_CONTROL
+ 34 },
68 { "cr35", NULL
, OPERAND_CONTROL
+ 35 },
69 { "cr36", NULL
, OPERAND_CONTROL
+ 36 },
70 { "cr37", NULL
, OPERAND_CONTROL
+ 37 },
71 { "cr38", NULL
, OPERAND_CONTROL
+ 38 },
72 { "cr39", NULL
, OPERAND_CONTROL
+ 39 },
73 { "cr4", "dpsw", OPERAND_CONTROL
+ 4 },
74 { "cr40", NULL
, OPERAND_CONTROL
+ 40 },
75 { "cr41", NULL
, OPERAND_CONTROL
+ 41 },
76 { "cr42", NULL
, OPERAND_CONTROL
+ 42 },
77 { "cr43", NULL
, OPERAND_CONTROL
+ 43 },
78 { "cr44", NULL
, OPERAND_CONTROL
+ 44 },
79 { "cr45", NULL
, OPERAND_CONTROL
+ 45 },
80 { "cr46", NULL
, OPERAND_CONTROL
+ 46 },
81 { "cr47", NULL
, OPERAND_CONTROL
+ 47 },
82 { "cr48", NULL
, OPERAND_CONTROL
+ 48 },
83 { "cr49", NULL
, OPERAND_CONTROL
+ 49 },
84 { "cr5","dpc", OPERAND_CONTROL
+ 5 },
85 { "cr50", NULL
, OPERAND_CONTROL
+ 50 },
86 { "cr51", NULL
, OPERAND_CONTROL
+ 51 },
87 { "cr52", NULL
, OPERAND_CONTROL
+ 52 },
88 { "cr53", NULL
, OPERAND_CONTROL
+ 53 },
89 { "cr54", NULL
, OPERAND_CONTROL
+ 54 },
90 { "cr55", NULL
, OPERAND_CONTROL
+ 55 },
91 { "cr56", NULL
, OPERAND_CONTROL
+ 56 },
92 { "cr57", NULL
, OPERAND_CONTROL
+ 57 },
93 { "cr58", NULL
, OPERAND_CONTROL
+ 58 },
94 { "cr59", NULL
, OPERAND_CONTROL
+ 59 },
95 { "cr6", NULL
, OPERAND_CONTROL
+ 6 },
96 { "cr60", NULL
, OPERAND_CONTROL
+ 60 },
97 { "cr61", NULL
, OPERAND_CONTROL
+ 61 },
98 { "cr62", NULL
, OPERAND_CONTROL
+ 62 },
99 { "cr63", NULL
, OPERAND_CONTROL
+ 63 },
100 { "cr7", "rpt_c", OPERAND_CONTROL
+ 7 },
101 { "cr8", "rpt_s", OPERAND_CONTROL
+ 8 },
102 { "cr9", "rpt_e", OPERAND_CONTROL
+ 9 },
103 { "dpc", NULL
, OPERAND_CONTROL
+ 5 },
104 { "dpsw", NULL
, OPERAND_CONTROL
+ 4 },
105 { "eit_vb", NULL
, OPERAND_CONTROL
+ 15 },
106 { "f0", NULL
, OPERAND_FLAG
+ 0 },
107 { "f1", NULL
, OPERAND_FLAG
+ 1 },
108 { "f2", NULL
, OPERAND_FLAG
+ 2 },
109 { "f3", NULL
, OPERAND_FLAG
+ 3 },
110 { "f4", "s", OPERAND_FLAG
+ 4 },
111 { "f5", "v", OPERAND_FLAG
+ 5 },
112 { "f6", "va", OPERAND_FLAG
+ 6 },
113 { "f7", "c", OPERAND_FLAG
+ 7 },
114 { "iba", NULL
, OPERAND_CONTROL
+ 14 },
115 { "int_m", NULL
, OPERAND_CONTROL
+ 17 },
116 { "int_s", NULL
, OPERAND_CONTROL
+ 16 },
117 { "link", "r62", 62 },
118 { "mod_e", NULL
, OPERAND_CONTROL
+ 11 },
119 { "mod_s", NULL
, OPERAND_CONTROL
+ 10 },
120 { "pc", NULL
, OPERAND_CONTROL
+ 2 },
121 { "psw", NULL
, OPERAND_CONTROL
},
122 { "pswh", NULL
, OPERAND_CONTROL
+ MAX_CONTROL_REG
+ 2 },
123 { "pswl", NULL
, OPERAND_CONTROL
+ MAX_CONTROL_REG
+ 1 },
183 { "r62", "link", 62 },
188 { "rpt_c", NULL
, OPERAND_CONTROL
+ 7 },
189 { "rpt_e", NULL
, OPERAND_CONTROL
+ 9 },
190 { "rpt_s", NULL
, OPERAND_CONTROL
+ 8 },
191 { "s", NULL
, OPERAND_FLAG
+ 4 },
193 { "v", NULL
, OPERAND_FLAG
+ 5 },
194 { "va", NULL
, OPERAND_FLAG
+ 6 },
200 return sizeof (pre_defined_registers
) / sizeof (struct pd_reg
);
204 The format of this table is defined in opcode/d30v.h. */
206 const struct d30v_opcode d30v_opcode_table
[] =
208 { "abs", IALU1
, 0x8, { SHORT_U
}, EITHER
, 0, 0, 0 },
209 { "add", IALU1
, 0x0, { SHORT_A
, LONG
}, EITHER
, 0, FLAG_CVVA
, 0 },
210 { "add2h", IALU1
, 0x1, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
211 { "addc", IALU1
, 0x4, { SHORT_A
, LONG
}, EITHER
, FLAG_C
, FLAG_CVVA
, 0 },
212 { "addhlll", IALU1
, 0x10, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
213 { "addhllh", IALU1
, 0x11, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
214 { "addhlhl", IALU1
, 0x12, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
215 { "addhlhh", IALU1
, 0x13, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
216 { "addhhll", IALU1
, 0x14, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
217 { "addhhlh", IALU1
, 0x15, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
218 { "addhhhl", IALU1
, 0x16, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
219 { "addhhhh", IALU1
, 0x17, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
220 { "adds", IALU1
, 0x6, { SHORT_A
, LONG
}, EITHER
, 0, FLAG_CVVA
, 0 },
221 { "adds2h", IALU1
, 0x7, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
222 { "and", LOGIC
, 0x18, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
223 { "andfg", LOGIC
, 0x8, { SHORT_F
}, EITHER
, 0, 0, 0 },
224 { "avg", IALU1
, 0xa, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
225 { "avg2h", IALU1
, 0xb, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
226 { "bclr", LOGIC
, 0x3, { SHORT_A
}, EITHER_BUT_PREFER_MU
, 0, 0, 0 },
227 { "bnot", LOGIC
, 0x1, { SHORT_A
}, EITHER_BUT_PREFER_MU
, 0, 0, 0 },
228 { "bra", BRA
, 0, { SHORT_B1
, SHORT_B2r
, LONG_Ur
}, MU
, FLAG_JMP
, 0, RELOC_PCREL
},
229 { "bratnz", BRA
, 0x4, { SHORT_B3br
, LONG_2br
}, MU
, FLAG_JMP
, 0, RELOC_PCREL
},
230 { "bratzr", BRA
, 0x4, { SHORT_B3r
, LONG_2r
}, MU
, FLAG_JMP
, 0, RELOC_PCREL
},
231 { "bset", LOGIC
, 0x2, { SHORT_A
}, EITHER_BUT_PREFER_MU
, 0, 0, 0 },
232 { "bsr", BRA
, 0x2, { SHORT_B1
, SHORT_B2r
, LONG_Ur
}, MU
, FLAG_JSR
, 0, RELOC_PCREL
},
233 { "bsrtnz", BRA
, 0x6, { SHORT_B3br
, LONG_2br
}, MU
, FLAG_JSR
, 0, RELOC_PCREL
},
234 { "bsrtzr", BRA
, 0x6, { SHORT_B3r
, LONG_2r
}, MU
, FLAG_JSR
, 0, RELOC_PCREL
},
235 { "btst", LOGIC
, 0, { SHORT_AF
}, EITHER_BUT_PREFER_MU
, 0, 0, 0 },
236 { "cmp", LOGIC
, 0xC, { SHORT_CMP
, LONG_CMP
}, EITHER
, 0, 0, 0 },
237 { "cmpu", LOGIC
, 0xD, { SHORT_CMPU
, LONG_CMP
}, EITHER
, 0, 0, 0 },
238 { "dbra", BRA
, 0x10, { SHORT_B3r
, LONG_2r
}, MU
, FLAG_JMP
| FLAG_DELAY
, FLAG_RP
, RELOC_PCREL
},
239 { "dbrai", BRA
, 0x14, { SHORT_D2r
, LONG_Dr
}, MU
, FLAG_JMP
| FLAG_DELAY
, FLAG_RP
, RELOC_PCREL
},
240 { "dbsr", BRA
, 0x12, { SHORT_B3r
, LONG_2r
}, MU
, FLAG_JSR
| FLAG_DELAY
, FLAG_RP
, RELOC_PCREL
},
241 { "dbsri", BRA
, 0x16, { SHORT_D2r
, LONG_Dr
}, MU
, FLAG_JSR
| FLAG_DELAY
, FLAG_RP
, RELOC_PCREL
},
242 { "dbt", BRA
, 0xb, { SHORT_NONE
}, MU
, FLAG_JSR
, FLAG_LKR
, 0 },
243 { "djmp", BRA
, 0x11, { SHORT_B3
, LONG_2
}, MU
, FLAG_JMP
| FLAG_DELAY
, FLAG_RP
, RELOC_ABS
},
244 { "djmpi", BRA
, 0x15, { SHORT_D2
, LONG_D
}, MU
, FLAG_JMP
| FLAG_DELAY
, FLAG_RP
, RELOC_ABS
},
245 { "djsr", BRA
, 0x13, { SHORT_B3
, LONG_2
}, MU
, FLAG_JSR
| FLAG_DELAY
, FLAG_RP
, RELOC_ABS
},
246 { "djsri", BRA
, 0x17, { SHORT_D2
, LONG_D
}, MU
, FLAG_JSR
| FLAG_DELAY
, FLAG_RP
, RELOC_ABS
},
247 { "jmp", BRA
, 0x1, { SHORT_B1
, SHORT_B2
, LONG_U
}, MU
, FLAG_JMP
, 0, RELOC_ABS
},
248 { "jmptnz", BRA
, 0x5, { SHORT_B3b
, LONG_2b
}, MU
, FLAG_JMP
, 0, RELOC_ABS
},
249 { "jmptzr", BRA
, 0x5, { SHORT_B3
, LONG_2
}, MU
, FLAG_JMP
, 0, RELOC_ABS
},
250 { "joinll", IALU1
, 0xC, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
251 { "joinlh", IALU1
, 0xD, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
252 { "joinhl", IALU1
, 0xE, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
253 { "joinhh", IALU1
, 0xF, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
254 { "jsr", BRA
, 0x3, { SHORT_B1
, SHORT_B2
, LONG_U
}, MU
, FLAG_JSR
, 0, RELOC_ABS
},
255 { "jsrtnz", BRA
, 0x7, { SHORT_B3b
, LONG_2b
}, MU
, FLAG_JSR
, 0, RELOC_ABS
},
256 { "jsrtzr", BRA
, 0x7, { SHORT_B3
, LONG_2
}, MU
, FLAG_JSR
, 0, RELOC_ABS
},
257 { "ld2h", IMEM
, 0x3, { SHORT_M2
, LONG_M2
}, MU
, FLAG_MEM
, 0, 0 },
258 { "ld2w", IMEM
, 0x6, { SHORT_M2
, LONG_M2
}, MU
, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0, 0 },
259 { "ld4bh", IMEM
, 0x5, { SHORT_M2
, LONG_M2
}, MU
, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0, 0 },
260 { "ld4bhu", IMEM
, 0xd, { SHORT_M2
, LONG_M2
}, MU
, FLAG_MEM
, 0, 0 },
261 { "ldb", IMEM
, 0, { SHORT_M
, LONG_M
}, MU
, FLAG_MEM
, 0, 0 },
262 { "ldbu", IMEM
, 0x9, { SHORT_M
, LONG_M
}, MU
, FLAG_MEM
, 0, 0 },
263 { "ldh", IMEM
, 0x2, { SHORT_M
, LONG_M
}, MU
, FLAG_MEM
, 0, 0 },
264 { "ldhh", IMEM
, 0x1, { SHORT_M
, LONG_M
}, MU
, FLAG_MEM
, 0, 0 },
265 { "ldhu", IMEM
, 0xa, { SHORT_M
, LONG_M
}, MU
, FLAG_MEM
, 0, 0 },
266 { "ldw", IMEM
, 0x4, { SHORT_M
, LONG_M
}, MU
, FLAG_MEM
, 0, 0 },
267 { "mac0", IALU2
, 0x14, { SHORT_A
}, IU
, FLAG_MUL32
, 0, 0 },
268 { "mac1", IALU2
, 0x14, { SHORT_A1
}, IU
, FLAG_MUL32
, 0, 0 },
269 { "macs0", IALU2
, 0x15, { SHORT_A
}, IU
, FLAG_MUL32
, 0, 0 },
270 { "macs1", IALU2
, 0x15, { SHORT_A1
}, IU
, FLAG_MUL32
, 0, 0 },
271 { "moddec", IMEM
, 0x7, { SHORT_MODDEC
}, MU
, 0, 0, 0 },
272 { "modinc", IMEM
, 0x7, { SHORT_MODINC
}, MU
, 0, 0, 0 },
273 { "msub0", IALU2
, 0x16, { SHORT_A
}, IU
, FLAG_MUL32
, 0, 0 },
274 { "msub1", IALU2
, 0x16, { SHORT_A1
}, IU
, FLAG_MUL32
, 0, 0 },
275 { "msubs0", IALU2
, 0x17, { SHORT_A
}, IU
, FLAG_MUL32
, 0, 0 },
276 { "msubs1", IALU2
, 0x17, { SHORT_A1
}, IU
, FLAG_MUL32
, 0, 0 },
277 { "mul", IALU2
, 0x10, { SHORT_A
}, IU
, FLAG_MUL32
, 0, 0 },
278 { "mul2h", IALU2
, 0, { SHORT_A
}, IU
, FLAG_MUL16
, 0, 0 },
279 { "mulhxll", IALU2
, 0x4, { SHORT_A
}, IU
, FLAG_MUL16
, 0, 0 },
280 { "mulhxlh", IALU2
, 0x5, { SHORT_A
}, IU
, FLAG_MUL16
, 0, 0 },
281 { "mulhxhl", IALU2
, 0x6, { SHORT_A
}, IU
, FLAG_MUL16
, 0, 0 },
282 { "mulhxhh", IALU2
, 0x7, { SHORT_A
}, IU
, FLAG_MUL16
, 0, 0 },
283 { "mulx", IALU2
, 0x18, { SHORT_AA
}, IU
, FLAG_MUL32
, 0, 0 },
284 { "mulx2h", IALU2
, 0x1, { SHORT_A2
}, IU
, FLAG_MUL16
, 0, 0 },
285 { "mulxs", IALU2
, 0x19, { SHORT_AA
}, IU
, FLAG_MUL32
, 0, 0 },
286 { "mvfacc", IALU2
, 0x1f, { SHORT_RA
}, IU
, 0, 0, 0 },
287 { "mvfsys", BRA
, 0x1e, { SHORT_C1
}, MU
, FLAG_ALL
, FLAG_ALL
, 0 },
288 { "mvtacc", IALU2
, 0xf, { SHORT_AR
}, IU
, 0, 0, 0 },
289 { "mvtsys", BRA
, 0xe, { SHORT_C2
}, MU
, FLAG_ALL
, FLAG_ALL
, 0 },
290 { "nop", BRA
, 0xF, { SHORT_NONE
}, EITHER
, 0, 0, 0 },
291 { "not", LOGIC
, 0x19, { SHORT_U
}, EITHER
, 0, 0, 0 },
292 { "notfg", LOGIC
, 0x9, { SHORT_UF
}, EITHER
, 0, 0, 0 },
293 { "or", LOGIC
, 0x1a, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
294 { "orfg", LOGIC
, 0xa, { SHORT_F
}, EITHER
, 0, 0, 0 },
295 { "reit", BRA
, 0x8, { SHORT_NONE
}, MU
, FLAG_SM
| FLAG_JMP
, FLAG_SM
| FLAG_LKR
, 0 },
296 { "repeat", BRA
, 0x18, { SHORT_D1r
, LONG_2r
}, MU
, FLAG_RP
, FLAG_RP
, RELOC_PCREL
},
297 { "repeati", BRA
, 0x1a, { SHORT_D2Br
, LONG_Dbr
}, MU
, FLAG_RP
, FLAG_RP
, RELOC_PCREL
},
298 { "rot", LOGIC
, 0x14, { SHORT_A
}, EITHER
, 0, 0, 0 },
299 { "rot2h", LOGIC
, 0x15, { SHORT_A
}, EITHER
, 0, 0, 0 },
300 { "rtd", BRA
, 0xa, { SHORT_NONE
}, MU
, FLAG_JMP
, FLAG_LKR
, 0 },
301 { "sat", IALU2
, 0x8, { SHORT_A5
}, IU
, 0, 0, 0 },
302 { "sat2h", IALU2
, 0x9, { SHORT_A5
}, IU
, 0, 0, 0 },
303 { "sathl", IALU2
, 0x1c, { SHORT_A5
}, IU
, FLAG_ADDSUBppp
, 0, 0 },
304 { "sathh", IALU2
, 0x1d, { SHORT_A5
}, IU
, FLAG_ADDSUBppp
, 0, 0 },
305 { "satz", IALU2
, 0xa, { SHORT_A5
}, IU
, 0, 0, 0 },
306 { "satz2h", IALU2
, 0xb, { SHORT_A5
}, IU
, 0, 0, 0 },
307 { "sra", LOGIC
, 0x10, { SHORT_A
}, EITHER
, 0, 0, 0 },
308 { "sra2h", LOGIC
, 0x11, { SHORT_A
}, EITHER
, 0, 0, 0 },
309 { "srahh", LOGIC
, 0x5, { SHORT_A
}, EITHER
, 0, 0, 0 },
310 { "srahl", LOGIC
, 0x4, { SHORT_A
}, EITHER
, 0, 0, 0 },
311 { "src", LOGIC
, 0x16, { SHORT_A
}, EITHER
, FLAG_ADDSUBppp
, 0, 0 },
312 { "srl", LOGIC
, 0x12, { SHORT_A
}, EITHER
, 0, 0, 0 },
313 { "srl2h", LOGIC
, 0x13, { SHORT_A
}, EITHER
, 0, 0, 0 },
314 { "srlhh", LOGIC
, 0x7, { SHORT_A
}, EITHER
, 0, 0, 0 },
315 { "srlhl", LOGIC
, 0x6, { SHORT_A
}, EITHER
, 0, 0, 0 },
316 { "st2h", IMEM
, 0x13, { SHORT_M2
, LONG_M2
}, MU
, 0, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0 },
317 { "st2w", IMEM
, 0x16, { SHORT_M2
, LONG_M2
}, MU
, 0, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0 },
318 { "st4hb", IMEM
, 0x15, { SHORT_M2
, LONG_M2
}, MU
, 0, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0 },
319 { "stb", IMEM
, 0x10, { SHORT_M
, LONG_M
}, MU
, 0, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0 },
320 { "sth", IMEM
, 0x12, { SHORT_M
, LONG_M
}, MU
, 0, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0 },
321 { "sthh", IMEM
, 0x11, { SHORT_M
, LONG_M
}, MU
, 0, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0 },
322 { "stw", IMEM
, 0x14, { SHORT_M
, LONG_M
}, MU
, 0, FLAG_MEM
| FLAG_NOT_WITH_ADDSUBppp
, 0 },
323 { "sub", IALU1
, 0x2, { SHORT_A
, LONG
}, EITHER
, 0, FLAG_CVVA
, 0 },
324 { "sub2h", IALU1
, 0x3, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
325 { "subb", IALU1
, 0x5, { SHORT_A
, LONG
}, EITHER
, FLAG_C
, FLAG_CVVA
, 0 },
326 { "subhlll", IALU1
, 0x18, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
327 { "subhllh", IALU1
, 0x19, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
328 { "subhlhl", IALU1
, 0x1a, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
329 { "subhlhh", IALU1
, 0x1b, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
330 { "subhhll", IALU1
, 0x1c, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
331 { "subhhlh", IALU1
, 0x1d, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
332 { "subhhhl", IALU1
, 0x1e, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
333 { "subhhhh", IALU1
, 0x1f, { SHORT_A
, LONG
}, EITHER
, FLAG_ADDSUBppp
, FLAG_CVVA
, 0 },
334 { "trap", BRA
, 0x9, { SHORT_B1
, SHORT_T
}, MU
, FLAG_JSR
, FLAG_SM
| FLAG_LKR
, 0 },
335 { "xor", LOGIC
, 0x1b, { SHORT_A
, LONG
}, EITHER
, 0, 0, 0 },
336 { "xorfg", LOGIC
, 0xb, { SHORT_F
}, EITHER
, 0, 0, 0 },
337 { NULL
, 0, 0, { 0 }, 0, 0, 0, 0 },
341 /* Now define the operand types.
342 Format is length, bits, position, flags. */
344 const struct d30v_operand d30v_operand_table
[] =
348 #define Ra (UNUSED + 1)
349 { 6, 6, 0, OPERAND_REG
| OPERAND_DEST
},
351 { 6, 6, 0, OPERAND_REG
| OPERAND_DEST
| OPERAND_2REG
},
352 #define Ra3 (Ra2 + 1)
353 { 6, 6, 0, OPERAND_REG
},
355 { 6, 6, 6, OPERAND_REG
},
357 { 6, 6, 6, OPERAND_REG
| OPERAND_DEST
},
359 { 6, 6, 12, OPERAND_REG
},
361 { 6, 1, 0, OPERAND_ACC
| OPERAND_REG
| OPERAND_DEST
},
363 { 6, 1, 6, OPERAND_ACC
| OPERAND_REG
},
364 #define IMM5 (Ab + 1)
365 { 6, 5, 12, OPERAND_NUM
},
366 #define IMM5U (IMM5 + 1)
367 { 6, 5, 12, OPERAND_NUM
| OPERAND_SIGNED
}, /* Not used. */
368 #define IMM5S3 (IMM5U + 1)
369 { 6, 5, 12, OPERAND_NUM
| OPERAND_SIGNED
}, /* Not used. */
370 #define IMM6 (IMM5S3 + 1)
371 { 6, 6, 12, OPERAND_NUM
| OPERAND_SIGNED
},
372 #define IMM6U (IMM6 + 1)
373 { 6, 6, 0, OPERAND_NUM
},
374 #define IMM6U2 (IMM6U + 1)
375 { 6, 6, 12, OPERAND_NUM
},
376 #define REL6S3 (IMM6U2 + 1)
377 { 6, 6, 0, OPERAND_NUM
| OPERAND_SHIFT
| OPERAND_PCREL
},
378 #define REL12S3 (REL6S3 + 1)
379 { 12, 12, 12, OPERAND_NUM
| OPERAND_SIGNED
| OPERAND_SHIFT
| OPERAND_PCREL
},
380 #define IMM12S3 (REL12S3 + 1)
381 { 12, 12, 12, OPERAND_NUM
| OPERAND_SIGNED
| OPERAND_SHIFT
},
382 #define REL18S3 (IMM12S3 + 1)
383 { 18, 18, 12, OPERAND_NUM
| OPERAND_SIGNED
| OPERAND_SHIFT
| OPERAND_PCREL
},
384 #define IMM18S3 (REL18S3 + 1)
385 { 18, 18, 12, OPERAND_NUM
| OPERAND_SIGNED
| OPERAND_SHIFT
},
386 #define REL32 (IMM18S3 + 1)
387 { 32, 32, 0, OPERAND_NUM
| OPERAND_PCREL
},
388 #define IMM32 (REL32 + 1)
389 { 32, 32, 0, OPERAND_NUM
},
390 #define Fa (IMM32 + 1)
391 { 6, 3, 0, OPERAND_REG
| OPERAND_FLAG
| OPERAND_DEST
},
393 { 6, 3, 6, OPERAND_REG
| OPERAND_FLAG
},
395 { 6, 3, 12, OPERAND_REG
| OPERAND_FLAG
},
396 #define ATSIGN (Fc + 1)
397 { 0, 0, 0, OPERAND_ATSIGN
},
398 #define ATPAR (ATSIGN + 1) /* "@(" */
399 { 0, 0, 0, OPERAND_ATPAR
},
400 #define PLUS (ATPAR + 1) /* Postincrement. */
401 { 0, 0, 0, OPERAND_PLUS
},
402 #define MINUS (PLUS + 1) /* Postdecrement. */
403 { 0, 0, 0, OPERAND_MINUS
},
404 #define ATMINUS (MINUS + 1) /* Predecrement. */
405 { 0, 0, 0, OPERAND_ATMINUS
},
406 #define Ca (ATMINUS + 1) /* Control register. */
407 { 6, 6, 0, OPERAND_REG
| OPERAND_CONTROL
| OPERAND_DEST
},
408 #define Cb (Ca + 1) /* Control register. */
409 { 6, 6, 6, OPERAND_REG
| OPERAND_CONTROL
},
410 #define CC (Cb + 1) /* Condition code (CMPcc and CMPUcc). */
411 { 3, 3, -3, OPERAND_NAME
},
412 #define Fa2 (CC + 1) /* Flag register (CMPcc and CMPUcc). */
413 { 3, 3, 0, OPERAND_REG
| OPERAND_FLAG
| OPERAND_DEST
},
414 #define Fake (Fa2 + 1) /* Place holder for "id" field in mvfsys and mvtsys. */
415 { 6, 2, 12, OPERAND_SPECIAL
},
418 /* Now we need to define the instruction formats. */
420 const struct d30v_format d30v_format_table
[] =
423 { SHORT_M
, 0, { Ra
, ATPAR
, Rb
, Rc
} }, /* Ra,@(Rb,Rc) */
424 { SHORT_M
, 1, { Ra
, ATPAR
, Rb
, PLUS
, Rc
} }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M
, 2, { Ra
, ATPAR
, Rb
, IMM6
} }, /* Ra,@(Rb,imm6) */
426 { SHORT_M
, 3, { Ra
, ATPAR
, Rb
, MINUS
, Rc
} }, /* Ra,@(Rb-,Rc) */
427 { SHORT_M2
, 0, { Ra2
, ATPAR
, Rb
, Rc
} }, /* Ra,@(Rb,Rc) */
428 { SHORT_M2
, 1, { Ra2
, ATPAR
, Rb
, PLUS
, Rc
} },/* Ra,@(Rb+,Rc) */
429 { SHORT_M2
, 2, { Ra2
, ATPAR
, Rb
, IMM6
} }, /* Ra,@(Rb,imm6) */
430 { SHORT_M2
, 3, { Ra2
, ATPAR
, Rb
, MINUS
, Rc
} },/* Ra,@(Rb-,Rc) */
431 { SHORT_A
, 0, { Ra
, Rb
, Rc
} }, /* Ra,Rb,Rc */
432 { SHORT_A
, 2, { Ra
, Rb
, IMM6
} }, /* Ra,Rb,imm6 */
433 { SHORT_B1
, 0, { Rc
} }, /* Rc */
434 { SHORT_B2
, 2, { IMM18S3
} }, /* imm18 */
435 { SHORT_B2r
, 2, { REL18S3
} }, /* rel18 */
436 { SHORT_B3
, 0, { Ra3
, Rc
} }, /* Ra,Rc */
437 { SHORT_B3
, 2, { Ra3
, IMM12S3
} }, /* Ra,imm12 */
438 { SHORT_B3r
, 0, { Ra3
, Rc
} }, /* Ra,Rc */
439 { SHORT_B3r
, 2, { Ra3
, REL12S3
} }, /* Ra,rel12 */
440 { SHORT_B3b
, 1, { Ra3
, Rc
} }, /* Ra,Rc */
441 { SHORT_B3b
, 3, { Ra3
, IMM12S3
} }, /* Ra,imm12 */
442 { SHORT_B3br
, 1, { Ra3
, Rc
} }, /* Ra,Rc */
443 { SHORT_B3br
, 3, { Ra3
, REL12S3
} }, /* Ra,rel12 */
444 { SHORT_D1r
, 0, { Ra
, Rc
} }, /* Ra,Rc */
445 { SHORT_D1r
, 2, { Ra
, REL12S3
} }, /* Ra,rel12s3 */
446 { SHORT_D2
, 0, { REL6S3
, Rc
} }, /* rel6s3,Rc */
447 { SHORT_D2
, 2, { REL6S3
, IMM12S3
} }, /* rel6s3,imm12s3 */
448 { SHORT_D2r
, 0, { REL6S3
, Rc
} }, /* rel6s3,Rc */
449 { SHORT_D2r
, 2, { REL6S3
, REL12S3
} }, /* rel6s3,rel12s3 */
450 { SHORT_D2Br
, 0, { IMM6U
, Rc
} }, /* imm6u,Rc */
451 { SHORT_D2Br
, 2, { IMM6U
, REL12S3
} }, /* imm6u,rel12s3 */
452 { SHORT_U
, 0, { Ra
, Rb
} }, /* Ra,Rb */
453 { SHORT_F
, 0, { Fa
, Fb
, Fc
} }, /* Fa,Fb,Fc (orfg, xorfg) */
454 { SHORT_F
, 2, { Fa
, Fb
, IMM6
} }, /* Fa,Fb,imm6 */
455 { SHORT_AF
, 0, { Fa
, Rb
, Rc
} }, /* Fa,Rb,Rc */
456 { SHORT_AF
, 2, { Fa
, Rb
, IMM6
} }, /* Fa,Rb,imm6 */
457 { SHORT_T
, 2, { IMM5
} }, /* imm5s3 (trap) */
458 { SHORT_A5
, 0, { Ra
, Rb
, Rc
} }, /* Ra,Rb,Rc */
459 { SHORT_A5
, 2, { Ra
, Rb
, IMM5
} }, /* Ra,Rb,imm5 (sat*) */
460 { SHORT_CMP
, 0, { CC
, Fa2
, Rb
, Rc
} }, /* CC Fa2,Rb,Rc */
461 { SHORT_CMP
, 2, { CC
, Fa2
, Rb
, IMM6
} }, /* CC Fa2,Rb,imm6 */
462 { SHORT_CMPU
, 0, { CC
, Fa2
, Rb
, Rc
} }, /* CC Fa2,Rb,Rc */
463 { SHORT_CMPU
, 2, { CC
, Fa2
, Rb
, IMM6U2
} }, /* CC Fa2,Rb,imm6 */
464 { SHORT_A1
, 1, { Ra
, Rb
, Rc
} }, /* Ra,Rb,Rc for MAC where a=1 */
465 { SHORT_A1
, 3, { Ra
, Rb
, IMM6
} }, /* Ra,Rb,imm6 for MAC where a=1 */
466 { SHORT_AA
, 0, { Aa
, Rb
, Rc
} }, /* Aa,Rb,Rc */
467 { SHORT_AA
, 2, { Aa
, Rb
, IMM6
} }, /* Aa,Rb,imm6 */
468 { SHORT_RA
, 0, { Ra
, Ab
, Rc
} }, /* Ra,Ab,Rc */
469 { SHORT_RA
, 2, { Ra
, Ab
, IMM6U2
} }, /* Ra,Ab,imm6u */
470 { SHORT_MODINC
, 1, { Rb2
, IMM5
} }, /* Rb2,imm5 (modinc) */
471 { SHORT_MODDEC
, 3, { Rb2
, IMM5
} }, /* Rb2,imm5 (moddec) */
472 { SHORT_C1
, 0, { Ra
, Cb
, Fake
} }, /* Ra,Cb (mvfsys) */
473 { SHORT_C2
, 0, { Ca
, Rb
, Fake
} }, /* Ca,Rb (mvtsys) */
474 { SHORT_UF
, 0, { Fa
, Fb
} }, /* Fa,Fb (notfg) */
475 { SHORT_A2
, 0, { Ra2
, Rb
, Rc
} }, /* Ra2,Rb,Rc */
476 { SHORT_A2
, 2, { Ra2
, Rb
, IMM6
} }, /* Ra2,Rb,imm6 */
477 { SHORT_NONE
, 0, { 0 } }, /* no operands (nop, reit) */
478 { SHORT_AR
, 0, { Aa
, Rb
, Rc
} }, /* Aa,Rb,Rc */
479 { LONG
, 2, { Ra
, Rb
, IMM32
} }, /* Ra,Rb,imm32 */
480 { LONG_U
, 2, { IMM32
} }, /* imm32 */
481 { LONG_Ur
, 2, { REL32
} }, /* rel32 */
482 { LONG_CMP
, 2, { CC
, Fa2
, Rb
, IMM32
} }, /* CC Fa2,Rb,imm32 */
483 { LONG_M
, 2, { Ra
, ATPAR
, Rb
, IMM32
} }, /* Ra,@(Rb,imm32) */
484 { LONG_M2
, 2, { Ra2
, ATPAR
, Rb
, IMM32
} }, /* Ra,@(Rb,imm32) */
485 { LONG_2
, 2, { Ra3
, IMM32
} }, /* Ra,imm32 */
486 { LONG_2r
, 2, { Ra3
, REL32
} }, /* Ra,rel32 */
487 { LONG_2b
, 3, { Ra3
, IMM32
} }, /* Ra,imm32 */
488 { LONG_2br
, 3, { Ra3
, REL32
} }, /* Ra,rel32 */
489 { LONG_D
, 2, { REL6S3
, IMM32
} }, /* rel6s3,imm32 */
490 { LONG_Dr
, 2, { REL6S3
, REL32
} }, /* rel6s3,rel32 */
491 { LONG_Dbr
, 2, { IMM6U
, REL32
} }, /* imm6,rel32 */
495 const char *d30v_ecc_names
[] =
507 const char *d30v_cc_names
[] =