Add the SEC_ELF_OCTETS flag to debug sections created by the assembler.
[binutils-gdb.git] / opcodes / arc-dis.h
bloba2471e15c8ccda766d97e0dd7ec77000f74b1c48
1 /* Disassembler structures definitions for the ARC.
2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
22 #ifndef ARCDIS_H
23 #define ARCDIS_H
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
29 enum arc_ldst_writeback_mode
31 ARC_WRITEBACK_NO = 0,
32 ARC_WRITEBACK_AW = 1,
33 ARC_WRITEBACK_A = ARC_WRITEBACK_AW,
34 ARC_WRITEBACK_AB = 2,
35 ARC_WRITEBACK_AS = 3,
39 enum arc_ldst_data_size
41 ARC_SCALING_NONE = 4,
42 ARC_SCALING_B = 1,
43 ARC_SCALING_H = 2,
44 ARC_SCALING_D = 8,
48 enum arc_condition_code
50 ARC_CC_AL = 0x0,
51 ARC_CC_RA = ARC_CC_AL,
52 ARC_CC_EQ = 0x1,
53 ARC_CC_Z = ARC_CC_EQ,
54 ARC_CC_NE = 0x2,
55 ARC_CC_NZ = ARC_CC_NE,
56 ARC_CC_PL = 0x3,
57 ARC_CC_P = ARC_CC_PL,
58 ARC_CC_MI = 0x4,
59 ARC_CC_N = ARC_CC_MI,
60 ARC_CC_CS = 0x5,
61 ARC_CC_C = ARC_CC_CS,
62 ARC_CC_LO = ARC_CC_CS,
63 ARC_CC_CC = 0x6,
64 ARC_CC_NC = ARC_CC_CC,
65 ARC_CC_HS = ARC_CC_CC,
66 ARC_CC_VS = 0x7,
67 ARC_CC_V = ARC_CC_VS,
68 ARC_CC_VC = 0x8,
69 ARC_CC_NV = ARC_CC_VC,
70 ARC_CC_GT = 0x9,
71 ARC_CC_GE = 0xA,
72 ARC_CC_LT = 0xB,
73 ARC_CC_LE = 0xC,
74 ARC_CC_HI = 0xD,
75 ARC_CC_LS = 0xE,
76 ARC_CC_PNZ = 0xF,
77 ARC_CC_UNDEF0 = 0x10,
78 ARC_CC_UNDEF1 = 0x11,
79 ARC_CC_UNDEF2 = 0x12,
80 ARC_CC_UNDEF3 = 0x13,
81 ARC_CC_UNDEF4 = 0x14,
82 ARC_CC_UNDEF5 = 0x15,
83 ARC_CC_UNDEF6 = 0x16,
84 ARC_CC_UNDEF7 = 0x17,
85 ARC_CC_UNDEF8 = 0x18,
86 ARC_CC_UNDEF9 = 0x19,
87 ARC_CC_UNDEFA = 0x1A,
88 ARC_CC_UNDEFB = 0x1B,
89 ARC_CC_UNDEFC = 0x1C,
90 ARC_CC_UNDEFD = 0x1D,
91 ARC_CC_UNDEFE = 0x1E,
92 ARC_CC_UNDEFF = 0x1F
95 enum arc_operand_kind
97 ARC_OPERAND_KIND_UNKNOWN = 0,
98 ARC_OPERAND_KIND_REG,
99 ARC_OPERAND_KIND_SHIMM,
100 ARC_OPERAND_KIND_LIMM
103 struct arc_insn_operand
105 /* Operand value as encoded in instruction. */
106 unsigned long value;
108 enum arc_operand_kind kind;
111 /* Container for information about instruction. Provides a higher
112 level access to data that is contained in struct arc_opcode. */
114 struct arc_instruction
116 /* Address of this instruction. */
117 bfd_vma address;
119 /* Whether this is a valid instruction. */
120 bool valid;
122 insn_class_t insn_class;
124 /* Length (without LIMM). */
125 unsigned length;
127 /* Is there a LIMM in this instruction? */
128 int limm_p;
130 /* Long immediate value. */
131 unsigned limm_value;
133 /* Is it a branch/jump instruction? */
134 int is_control_flow;
136 /* Whether this instruction has a delay slot. */
137 int has_delay_slot;
139 /* Value of condition code field. */
140 enum arc_condition_code condition_code;
142 /* Load/store writeback mode. */
143 enum arc_ldst_writeback_mode writeback_mode;
145 /* Load/store data size. */
146 enum arc_ldst_data_size data_size_mode;
148 /* Amount of operands in instruction. Note that amount of operands
149 reported by opcodes disassembler can be different from the one
150 encoded in the instruction. Notable case is "ld a,[b,offset]",
151 when offset == 0. In this case opcodes disassembler presents
152 this instruction as "ld a,[b]", hence there are *two* operands,
153 not three. OPERANDS_COUNT and OPERANDS contain only those
154 explicit operands, hence it is up to invoker to handle the case
155 described above based on instruction opcodes. Another notable
156 thing is that in opcodes disassembler representation square
157 brackets (`[' and `]') are so called fake-operands - they are in
158 the list of operands, but do not have any value of they own.
159 Those "operands" are not present in this array. */
160 struct arc_insn_operand operands[MAX_INSN_ARGS];
162 unsigned int operands_count;
165 /* Fill INSN with data about instruction at specified ADDR. */
167 void arc_insn_decode (bfd_vma addr,
168 struct disassemble_info *di,
169 disassembler_ftype func,
170 struct arc_instruction *insn);
172 #ifdef __cplusplus
174 #endif
176 #endif