2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of the GNU opcodes library.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
24 #include "opcode/riscv.h"
27 /* Register names used by gas and objdump. */
29 const char riscv_gpr_names_numeric
[NGPR
][NRC
] =
31 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
32 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
33 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
34 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"
37 const char riscv_gpr_names_abi
[NGPR
][NRC
] =
39 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
40 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
41 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
42 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
45 const char riscv_fpr_names_numeric
[NFPR
][NRC
] =
47 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
48 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
49 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
50 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
53 const char riscv_fpr_names_abi
[NFPR
][NRC
] =
55 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
56 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
57 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
58 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
62 const char * const riscv_rm
[8] =
64 "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
67 /* FENCE: predecessor/successor sets. */
68 const char * const riscv_pred_succ
[16] =
70 0, "w", "r", "rw", "o", "ow", "or", "orw",
71 "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
75 const char riscv_vecr_names_numeric
[NVECR
][NRC
] =
77 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
78 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
79 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
80 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
83 /* RVV mask registers. */
84 const char riscv_vecm_names_numeric
[NVECM
][NRC
] =
89 /* The vsetvli vsew constants. */
90 const char * const riscv_vsew
[8] =
92 "e8", "e16", "e32", "e64", NULL
, NULL
, NULL
, NULL
95 /* The vsetvli vlmul constants. */
96 const char * const riscv_vlmul
[8] =
98 "m1", "m2", "m4", "m8", NULL
, "mf8", "mf4", "mf2"
101 /* The vsetvli vta constants. */
102 const char * const riscv_vta
[2] =
107 /* The vsetvli vma constants. */
108 const char * const riscv_vma
[2] =
113 /* The FLI.[HSDQ] symbolic constants (NULL for numeric constant). */
114 const char * const riscv_fli_symval
[32] =
116 NULL
, "min", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
117 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
118 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
119 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, "inf", "nan",
122 /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants).
123 The constants use the hex floating-point literal representation
124 that is printed when using the printf %a format specifier,
125 which matches the output that is generated by the disassembler. */
126 const float riscv_fli_numval
[32] =
128 -0x1p
+0, 0x0p
+0, 0x1p
-16, 0x1p
-15, 0x1p
-8, 0x1p
-7, 0x1p
-4, 0x1p
-3,
129 0x1p
-2, 0x1.4p
-2, 0x1.8p
-2, 0x1.cp
-2, 0x1p
-1, 0x1.4p
-1, 0x1.8p
-1, 0x1.cp
-1,
130 0x1p
+0, 0x1.4p
+0, 0x1.8p
+0, 0x1.cp
+0, 0x1p
+1, 0x1.4p
+1, 0x1.8p
+1, 0x1p
+2,
131 0x1p
+3, 0x1p
+4, 0x1p
+7, 0x1p
+8, 0x1p
+15, 0x1p
+16, 0x0p
+0, 0x0p
+0
134 #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1)
135 #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
136 #define MASK_RD (OP_MASK_RD << OP_SH_RD)
137 #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
138 #define MASK_IMM ENCODE_ITYPE_IMM (-1U)
139 #define MASK_RVC_IMM ENCODE_CITYPE_IMM (-1U)
140 #define MASK_UIMM ENCODE_UTYPE_IMM (-1U)
141 #define MASK_RM (OP_MASK_RM << OP_SH_RM)
142 #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
143 #define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC)
144 #define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
145 #define MASK_RL (OP_MASK_RL << OP_SH_RL)
146 #define MASK_AQRL (MASK_AQ | MASK_RL)
147 #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
148 #define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
149 #define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
150 #define MATCH_SHAMT_BREV8 (0b00111 << OP_SH_SHAMT)
151 #define MATCH_SHAMT_ZIP_32 (0b1111 << OP_SH_SHAMT)
152 #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
153 #define MASK_VD (OP_MASK_VD << OP_SH_VD)
154 #define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
155 #define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
156 #define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
159 match_opcode (const struct riscv_opcode
*op
, insn_t insn
)
161 return ((insn
^ op
->match
) & op
->mask
) == 0;
165 match_never (const struct riscv_opcode
*op ATTRIBUTE_UNUSED
,
166 insn_t insn ATTRIBUTE_UNUSED
)
172 match_rs1_eq_rs2 (const struct riscv_opcode
*op
, insn_t insn
)
174 int rs1
= (insn
& MASK_RS1
) >> OP_SH_RS1
;
175 int rs2
= (insn
& MASK_RS2
) >> OP_SH_RS2
;
176 return match_opcode (op
, insn
) && rs1
== rs2
;
180 match_rd_nonzero (const struct riscv_opcode
*op
, insn_t insn
)
182 return match_opcode (op
, insn
) && ((insn
& MASK_RD
) != 0);
186 match_c_add (const struct riscv_opcode
*op
, insn_t insn
)
188 return match_rd_nonzero (op
, insn
) && ((insn
& MASK_CRS2
) != 0);
191 /* We don't allow mv zero,X to become a c.mv hint, so we need a separate
192 matching function for this. */
195 match_c_add_with_hint (const struct riscv_opcode
*op
, insn_t insn
)
197 return match_opcode (op
, insn
) && ((insn
& MASK_CRS2
) != 0);
201 match_c_nop (const struct riscv_opcode
*op
, insn_t insn
)
203 return (match_opcode (op
, insn
)
204 && (((insn
& MASK_RD
) >> OP_SH_RD
) == 0));
208 match_c_addi16sp (const struct riscv_opcode
*op
, insn_t insn
)
210 return (match_opcode (op
, insn
)
211 && (((insn
& MASK_RD
) >> OP_SH_RD
) == 2));
215 match_c_lui (const struct riscv_opcode
*op
, insn_t insn
)
217 return (match_rd_nonzero (op
, insn
)
218 && (((insn
& MASK_RD
) >> OP_SH_RD
) != 2)
219 && EXTRACT_CITYPE_LUI_IMM (insn
) != 0);
222 /* We don't allow lui zero,X to become a c.lui hint, so we need a separate
223 matching function for this. */
226 match_c_lui_with_hint (const struct riscv_opcode
*op
, insn_t insn
)
228 return (match_opcode (op
, insn
)
229 && (((insn
& MASK_RD
) >> OP_SH_RD
) != 2)
230 && EXTRACT_CITYPE_LUI_IMM (insn
) != 0);
234 match_c_addi4spn (const struct riscv_opcode
*op
, insn_t insn
)
236 return match_opcode (op
, insn
) && EXTRACT_CIWTYPE_ADDI4SPN_IMM (insn
) != 0;
239 /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
242 match_c_slli (const struct riscv_opcode
*op
, insn_t insn
)
244 return match_opcode (op
, insn
) && EXTRACT_CITYPE_IMM (insn
) != 0;
247 /* This requires a non-zero rd, and a non-zero shift. */
250 match_slli_as_c_slli (const struct riscv_opcode
*op
, insn_t insn
)
252 return match_rd_nonzero (op
, insn
) && EXTRACT_CITYPE_IMM (insn
) != 0;
255 /* This requires a zero shift. A zero rd is a hint, so is allowed. */
258 match_c_slli64 (const struct riscv_opcode
*op
, insn_t insn
)
260 return match_opcode (op
, insn
) && EXTRACT_CITYPE_IMM (insn
) == 0;
263 /* This is used for both srli and srai. This requires a non-zero shift.
264 A zero rd is not possible. */
267 match_srxi_as_c_srxi (const struct riscv_opcode
*op
, insn_t insn
)
269 return match_opcode (op
, insn
) && EXTRACT_CITYPE_IMM (insn
) != 0;
273 match_vs1_eq_vs2 (const struct riscv_opcode
*op
,
276 int vs1
= (insn
& MASK_VS1
) >> OP_SH_VS1
;
277 int vs2
= (insn
& MASK_VS2
) >> OP_SH_VS2
;
279 return match_opcode (op
, insn
) && vs1
== vs2
;
283 match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode
*op
,
286 int vd
= (insn
& MASK_VD
) >> OP_SH_VD
;
287 int vs1
= (insn
& MASK_VS1
) >> OP_SH_VS1
;
288 int vs2
= (insn
& MASK_VS2
) >> OP_SH_VS2
;
290 return match_opcode (op
, insn
) && vd
== vs1
&& vs1
== vs2
;
294 match_th_load_inc(const struct riscv_opcode
*op
,
297 /* Load-increment has the following restriction:
298 * The values of rd and rs1 must not be the same. */
299 int rd
= (insn
& MASK_RD
) >> OP_SH_RD
;
300 int rs1
= (insn
& MASK_RS1
) >> OP_SH_RS1
;
302 return rd
!= rs1
&& match_opcode (op
, insn
);
306 match_th_load_pair(const struct riscv_opcode
*op
,
309 /* Load pair instructions use the following encoding:
310 * - rd1 = RD (insn[11:7])
311 * - rd2 = RS2 (insn[24:20])
312 * - rs = RS1 ([19:15])
313 * This function matches if the following restriction is met:
314 * The values of rd1, rd2, and rs1 must not be the same. */
315 int rd1
= (insn
& MASK_RD
) >> OP_SH_RD
;
316 int rd2
= (insn
& MASK_RS2
) >> OP_SH_RS2
;
317 int rs
= (insn
& MASK_RS1
) >> OP_SH_RS1
;
319 return rd1
!= rd2
&& rd1
!= rs
&& rd2
!= rs
&& match_opcode (op
, insn
);
322 /* The order of overloaded instructions matters. Label arguments and
323 register arguments look the same. Instructions that can have either
324 for arguments must apear in the correct order in this table for the
325 assembler to pick the right one. In other words, entries with
326 immediate operands must apear after the same instruction with
329 Because of the lookup algorithm used, entries with the same opcode
330 name must be contiguous. */
332 const struct riscv_opcode riscv_opcodes
[] =
334 /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
336 /* Standard hints. */
337 {"prefetch.i", 0, INSN_CLASS_ZICBOP
, "Wif(s)", MATCH_PREFETCH_I
, MASK_PREFETCH_I
, match_opcode
, 0 },
338 {"prefetch.r", 0, INSN_CLASS_ZICBOP
, "Wif(s)", MATCH_PREFETCH_R
, MASK_PREFETCH_R
, match_opcode
, 0 },
339 {"prefetch.w", 0, INSN_CLASS_ZICBOP
, "Wif(s)", MATCH_PREFETCH_W
, MASK_PREFETCH_W
, match_opcode
, 0 },
340 {"ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C
, "", MATCH_C_NTL_P1
, MASK_C_NTL_P1
, match_opcode
, INSN_ALIAS
},
341 {"ntl.p1", 0, INSN_CLASS_ZIHINTNTL
, "", MATCH_NTL_P1
, MASK_NTL_P1
, match_opcode
, 0 },
342 {"ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C
, "", MATCH_C_NTL_PALL
, MASK_C_NTL_PALL
, match_opcode
, INSN_ALIAS
},
343 {"ntl.pall", 0, INSN_CLASS_ZIHINTNTL
, "", MATCH_NTL_PALL
, MASK_NTL_PALL
, match_opcode
, 0 },
344 {"ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C
, "", MATCH_C_NTL_S1
, MASK_C_NTL_S1
, match_opcode
, INSN_ALIAS
},
345 {"ntl.s1", 0, INSN_CLASS_ZIHINTNTL
, "", MATCH_NTL_S1
, MASK_NTL_S1
, match_opcode
, 0 },
346 {"ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C
, "", MATCH_C_NTL_ALL
, MASK_C_NTL_ALL
, match_opcode
, INSN_ALIAS
},
347 {"ntl.all", 0, INSN_CLASS_ZIHINTNTL
, "", MATCH_NTL_ALL
, MASK_NTL_ALL
, match_opcode
, 0 },
348 {"c.ntl.p1", 0, INSN_CLASS_ZIHINTNTL_AND_C
, "", MATCH_C_NTL_P1
, MASK_C_NTL_P1
, match_opcode
, 0 },
349 {"c.ntl.pall", 0, INSN_CLASS_ZIHINTNTL_AND_C
, "", MATCH_C_NTL_PALL
, MASK_C_NTL_PALL
, match_opcode
, 0 },
350 {"c.ntl.s1", 0, INSN_CLASS_ZIHINTNTL_AND_C
, "", MATCH_C_NTL_S1
, MASK_C_NTL_S1
, match_opcode
, 0 },
351 {"c.ntl.all", 0, INSN_CLASS_ZIHINTNTL_AND_C
, "", MATCH_C_NTL_ALL
, MASK_C_NTL_ALL
, match_opcode
, 0 },
352 {"pause", 0, INSN_CLASS_ZIHINTPAUSE
, "", MATCH_PAUSE
, MASK_PAUSE
, match_opcode
, 0 },
354 /* Basic RVI instructions and aliases. */
355 {"unimp", 0, INSN_CLASS_C
, "", 0, 0xffffU
, match_opcode
, INSN_ALIAS
},
356 {"unimp", 0, INSN_CLASS_I
, "", MATCH_CSRRW
|(CSR_CYCLE
<< OP_SH_CSR
), 0xffffffffU
, match_opcode
, 0 }, /* csrw cycle, x0 */
357 {"ebreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, INSN_ALIAS
},
358 {"ebreak", 0, INSN_CLASS_I
, "", MATCH_EBREAK
, MASK_EBREAK
, match_opcode
, 0 },
359 {"sbreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, INSN_ALIAS
},
360 {"sbreak", 0, INSN_CLASS_I
, "", MATCH_EBREAK
, MASK_EBREAK
, match_opcode
, INSN_ALIAS
},
361 {"ret", 0, INSN_CLASS_C
, "", MATCH_C_JR
|(X_RA
<< OP_SH_RD
), MASK_C_JR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
362 {"ret", 0, INSN_CLASS_I
, "", MATCH_JALR
|(X_RA
<< OP_SH_RS1
), MASK_JALR
|MASK_RD
|MASK_RS1
|MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
363 {"jr", 0, INSN_CLASS_C
, "d", MATCH_C_JR
, MASK_C_JR
, match_rd_nonzero
, INSN_ALIAS
|INSN_BRANCH
},
364 {"jr", 0, INSN_CLASS_I
, "s", MATCH_JALR
, MASK_JALR
|MASK_RD
|MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
365 {"jr", 0, INSN_CLASS_I
, "o(s)", MATCH_JALR
, MASK_JALR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
366 {"jr", 0, INSN_CLASS_I
, "s,j", MATCH_JALR
, MASK_JALR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
367 {"jalr", 0, INSN_CLASS_C
, "d", MATCH_C_JALR
, MASK_C_JALR
, match_rd_nonzero
, INSN_ALIAS
|INSN_JSR
},
368 {"jalr", 0, INSN_CLASS_I
, "s", MATCH_JALR
|(X_RA
<< OP_SH_RD
), MASK_JALR
|MASK_RD
|MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
369 {"jalr", 0, INSN_CLASS_I
, "o(s)", MATCH_JALR
|(X_RA
<< OP_SH_RD
), MASK_JALR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
370 {"jalr", 0, INSN_CLASS_I
, "s,j", MATCH_JALR
|(X_RA
<< OP_SH_RD
), MASK_JALR
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
371 {"jalr", 0, INSN_CLASS_I
, "d,s", MATCH_JALR
, MASK_JALR
|MASK_IMM
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
372 {"jalr", 0, INSN_CLASS_I
, "d,o(s)", MATCH_JALR
, MASK_JALR
, match_opcode
, INSN_JSR
},
373 {"jalr", 0, INSN_CLASS_I
, "d,s,j", MATCH_JALR
, MASK_JALR
, match_opcode
, INSN_JSR
},
374 {"j", 0, INSN_CLASS_C
, "Ca", MATCH_C_J
, MASK_C_J
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
375 {"j", 0, INSN_CLASS_I
, "a", MATCH_JAL
, MASK_JAL
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_BRANCH
},
376 {"jal", 32, INSN_CLASS_C
, "Ca", MATCH_C_JAL
, MASK_C_JAL
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
377 {"jal", 0, INSN_CLASS_I
, "a", MATCH_JAL
|(X_RA
<< OP_SH_RD
), MASK_JAL
|MASK_RD
, match_opcode
, INSN_ALIAS
|INSN_JSR
},
378 {"jal", 0, INSN_CLASS_I
, "d,a", MATCH_JAL
, MASK_JAL
, match_opcode
, INSN_JSR
},
379 {"call", 0, INSN_CLASS_I
, "d,c", (X_T1
<< OP_SH_RS1
), (int) M_CALL
, match_never
, INSN_MACRO
},
380 {"call", 0, INSN_CLASS_I
, "c", (X_RA
<< OP_SH_RS1
)|(X_RA
<< OP_SH_RD
), (int) M_CALL
, match_never
, INSN_MACRO
},
381 {"tail", 0, INSN_CLASS_I
, "c", (X_T1
<< OP_SH_RS1
), (int) M_CALL
, match_never
, INSN_MACRO
},
382 {"jump", 0, INSN_CLASS_I
, "c,s", 0, (int) M_CALL
, match_never
, INSN_MACRO
},
383 {"nop", 0, INSN_CLASS_C
, "", MATCH_C_ADDI
, 0xffff, match_opcode
, INSN_ALIAS
},
384 {"nop", 0, INSN_CLASS_I
, "", MATCH_ADDI
, MASK_ADDI
|MASK_RD
|MASK_RS1
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
385 {"lui", 0, INSN_CLASS_C
, "d,Cu", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui
, INSN_ALIAS
},
386 {"lui", 0, INSN_CLASS_I
, "d,u", MATCH_LUI
, MASK_LUI
, match_opcode
, 0 },
387 {"li", 0, INSN_CLASS_C
, "d,Cv", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui
, INSN_ALIAS
},
388 {"li", 0, INSN_CLASS_C
, "d,Co", MATCH_C_LI
, MASK_C_LI
, match_rd_nonzero
, INSN_ALIAS
},
389 {"li", 0, INSN_CLASS_I
, "d,j", MATCH_ADDI
, MASK_ADDI
|MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* addi */
390 {"li", 0, INSN_CLASS_I
, "d,I", 0, (int) M_LI
, match_never
, INSN_MACRO
},
391 {"mv", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
392 {"mv", 0, INSN_CLASS_I
, "d,s", MATCH_ADDI
, MASK_ADDI
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
393 {"move", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
394 {"move", 0, INSN_CLASS_I
, "d,s", MATCH_ADDI
, MASK_ADDI
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
395 {"zext.b", 0, INSN_CLASS_ZCB
, "Cs,Cw", MATCH_C_ZEXT_B
, MASK_C_ZEXT_B
, match_opcode
, INSN_ALIAS
},
396 {"zext.b", 0, INSN_CLASS_I
, "d,s", MATCH_ANDI
|ENCODE_ITYPE_IMM (255), MASK_ANDI
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
397 {"andi", 0, INSN_CLASS_ZCB
, "Cs,Cw,Wcf",MATCH_C_ZEXT_B
, MASK_C_ZEXT_B
, match_opcode
, INSN_ALIAS
},
398 {"andi", 0, INSN_CLASS_C
, "Cs,Cw,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, INSN_ALIAS
},
399 {"andi", 0, INSN_CLASS_I
, "d,s,j", MATCH_ANDI
, MASK_ANDI
, match_opcode
, 0 },
400 {"and", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_AND
, MASK_C_AND
, match_opcode
, INSN_ALIAS
},
401 {"and", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_AND
, MASK_C_AND
, match_opcode
, INSN_ALIAS
},
402 {"and", 0, INSN_CLASS_C
, "Cs,Cw,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, INSN_ALIAS
},
403 {"and", 0, INSN_CLASS_I
, "d,s,t", MATCH_AND
, MASK_AND
, match_opcode
, 0 },
404 {"and", 0, INSN_CLASS_I
, "d,s,j", MATCH_ANDI
, MASK_ANDI
, match_opcode
, INSN_ALIAS
},
405 {"beqz", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
406 {"beqz", 0, INSN_CLASS_I
, "s,p", MATCH_BEQ
, MASK_BEQ
|MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
407 {"beq", 0, INSN_CLASS_C
, "Cs,Cz,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
408 {"beq", 0, INSN_CLASS_I
, "s,t,p", MATCH_BEQ
, MASK_BEQ
, match_opcode
, INSN_CONDBRANCH
},
409 {"blez", 0, INSN_CLASS_I
, "t,p", MATCH_BGE
, MASK_BGE
|MASK_RS1
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
410 {"bgez", 0, INSN_CLASS_I
, "s,p", MATCH_BGE
, MASK_BGE
|MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
411 {"bge", 0, INSN_CLASS_I
, "s,t,p", MATCH_BGE
, MASK_BGE
, match_opcode
, INSN_CONDBRANCH
},
412 {"bgeu", 0, INSN_CLASS_I
, "s,t,p", MATCH_BGEU
, MASK_BGEU
, match_opcode
, INSN_CONDBRANCH
},
413 {"ble", 0, INSN_CLASS_I
, "t,s,p", MATCH_BGE
, MASK_BGE
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
414 {"bleu", 0, INSN_CLASS_I
, "t,s,p", MATCH_BGEU
, MASK_BGEU
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
415 {"bltz", 0, INSN_CLASS_I
, "s,p", MATCH_BLT
, MASK_BLT
|MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
416 {"bgtz", 0, INSN_CLASS_I
, "t,p", MATCH_BLT
, MASK_BLT
|MASK_RS1
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
417 {"blt", 0, INSN_CLASS_I
, "s,t,p", MATCH_BLT
, MASK_BLT
, match_opcode
, INSN_CONDBRANCH
},
418 {"bltu", 0, INSN_CLASS_I
, "s,t,p", MATCH_BLTU
, MASK_BLTU
, match_opcode
, INSN_CONDBRANCH
},
419 {"bgt", 0, INSN_CLASS_I
, "t,s,p", MATCH_BLT
, MASK_BLT
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
420 {"bgtu", 0, INSN_CLASS_I
, "t,s,p", MATCH_BLTU
, MASK_BLTU
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
421 {"bnez", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
422 {"bnez", 0, INSN_CLASS_I
, "s,p", MATCH_BNE
, MASK_BNE
|MASK_RS2
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
423 {"bne", 0, INSN_CLASS_C
, "Cs,Cz,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_ALIAS
|INSN_CONDBRANCH
},
424 {"bne", 0, INSN_CLASS_I
, "s,t,p", MATCH_BNE
, MASK_BNE
, match_opcode
, INSN_CONDBRANCH
},
425 {"addi", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, INSN_ALIAS
},
426 {"addi", 0, INSN_CLASS_C
, "d,CU,Cj", MATCH_C_ADDI
, MASK_C_ADDI
, match_rd_nonzero
, INSN_ALIAS
},
427 {"addi", 0, INSN_CLASS_C
, "d,CU,z", MATCH_C_NOP
, MASK_C_ADDI
|MASK_RVC_IMM
, match_c_nop
, INSN_ALIAS
},
428 {"addi", 0, INSN_CLASS_C
, "Cc,Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, INSN_ALIAS
},
429 {"addi", 0, INSN_CLASS_C
, "d,Cz,Co", MATCH_C_LI
, MASK_C_LI
, match_rd_nonzero
, INSN_ALIAS
},
430 {"addi", 0, INSN_CLASS_C
, "d,CV,z", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
431 {"addi", 0, INSN_CLASS_I
, "d,s,j", MATCH_ADDI
, MASK_ADDI
, match_opcode
, 0 },
432 {"add", 0, INSN_CLASS_C
, "d,CU,CV", MATCH_C_ADD
, MASK_C_ADD
, match_c_add
, INSN_ALIAS
},
433 {"add", 0, INSN_CLASS_C
, "d,CV,CU", MATCH_C_ADD
, MASK_C_ADD
, match_c_add
, INSN_ALIAS
},
434 {"add", 0, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDI
, MASK_C_ADDI
, match_rd_nonzero
, INSN_ALIAS
},
435 {"add", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, INSN_ALIAS
},
436 {"add", 0, INSN_CLASS_C
, "Cc,Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, INSN_ALIAS
},
437 {"add", 0, INSN_CLASS_C
, "d,Cz,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add
, INSN_ALIAS
},
438 {"add", 0, INSN_CLASS_I
, "d,s,t", MATCH_ADD
, MASK_ADD
, match_opcode
, 0 },
439 {"add", 0, INSN_CLASS_I
, "d,s,t,1", MATCH_ADD
, MASK_ADD
, match_opcode
, 0 },
440 {"add", 0, INSN_CLASS_I
, "d,s,j", MATCH_ADDI
, MASK_ADDI
, match_opcode
, INSN_ALIAS
},
441 {"la", 0, INSN_CLASS_I
, "d,B", 0, (int) M_LA
, match_never
, INSN_MACRO
},
442 {"lla", 0, INSN_CLASS_I
, "d,B", 0, (int) M_LLA
, match_never
, INSN_MACRO
},
443 {"lga", 0, INSN_CLASS_I
, "d,B", 0, (int) M_LGA
, match_never
, INSN_MACRO
},
444 {"la.tls.gd", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LA_TLS_GD
, match_never
, INSN_MACRO
},
445 {"la.tls.ie", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LA_TLS_IE
, match_never
, INSN_MACRO
},
446 {"neg", 0, INSN_CLASS_I
, "d,t", MATCH_SUB
, MASK_SUB
|MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* sub 0 */
447 {"slli", 0, INSN_CLASS_C
, "d,CU,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_slli_as_c_slli
, INSN_ALIAS
},
448 {"slli", 0, INSN_CLASS_I
, "d,s,>", MATCH_SLLI
, MASK_SLLI
, match_opcode
, 0 },
449 {"sll", 0, INSN_CLASS_C
, "d,CU,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_slli_as_c_slli
, INSN_ALIAS
},
450 {"sll", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLL
, MASK_SLL
, match_opcode
, 0 },
451 {"sll", 0, INSN_CLASS_I
, "d,s,>", MATCH_SLLI
, MASK_SLLI
, match_opcode
, INSN_ALIAS
},
452 {"srli", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
453 {"srli", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRLI
, MASK_SRLI
, match_opcode
, 0 },
454 {"srl", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
455 {"srl", 0, INSN_CLASS_I
, "d,s,t", MATCH_SRL
, MASK_SRL
, match_opcode
, 0 },
456 {"srl", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRLI
, MASK_SRLI
, match_opcode
, INSN_ALIAS
},
457 {"srai", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
458 {"srai", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRAI
, MASK_SRAI
, match_opcode
, 0 },
459 {"sra", 0, INSN_CLASS_C
, "Cs,Cw,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_srxi_as_c_srxi
, INSN_ALIAS
},
460 {"sra", 0, INSN_CLASS_I
, "d,s,t", MATCH_SRA
, MASK_SRA
, match_opcode
, 0 },
461 {"sra", 0, INSN_CLASS_I
, "d,s,>", MATCH_SRAI
, MASK_SRAI
, match_opcode
, INSN_ALIAS
},
462 {"sub", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_SUB
, MASK_C_SUB
, match_opcode
, INSN_ALIAS
},
463 {"sub", 0, INSN_CLASS_I
, "d,s,t", MATCH_SUB
, MASK_SUB
, match_opcode
, 0 },
464 {"lb", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LB
, MASK_LB
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
465 {"lb", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LB
, match_never
, INSN_MACRO
},
466 {"lbu", 0, INSN_CLASS_ZCB
, "Ct,Wcb(Cs)", MATCH_C_LBU
, MASK_C_LBU
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_1_BYTE
},
467 {"lbu", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LBU
, MASK_LBU
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
468 {"lbu", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LBU
, match_never
, INSN_MACRO
},
469 {"lh", 0, INSN_CLASS_ZCB
, "Ct,Wch(Cs)", MATCH_C_LH
, MASK_C_LH
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_2_BYTE
},
470 {"lh", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LH
, MASK_LH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
471 {"lh", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LH
, match_never
, INSN_MACRO
},
472 {"lhu", 0, INSN_CLASS_ZCB
, "Ct,Wch(Cs)", MATCH_C_LHU
, MASK_C_LHU
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_2_BYTE
},
473 {"lhu", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LHU
, MASK_LHU
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
474 {"lhu", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LHU
, match_never
, INSN_MACRO
},
475 {"lw", 0, INSN_CLASS_C
, "d,Cm(Cc)", MATCH_C_LWSP
, MASK_C_LWSP
, match_rd_nonzero
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
476 {"lw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_LW
, MASK_C_LW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
477 {"lw", 0, INSN_CLASS_I
, "d,o(s)", MATCH_LW
, MASK_LW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
478 {"lw", 0, INSN_CLASS_I
, "d,A", 0, (int) M_LW
, match_never
, INSN_MACRO
},
479 {"not", 0, INSN_CLASS_ZCB
, "Cs,Cw", MATCH_C_NOT
, MASK_C_NOT
, match_opcode
, INSN_ALIAS
},
480 {"not", 0, INSN_CLASS_I
, "d,s", MATCH_XORI
|MASK_IMM
, MASK_XORI
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
481 {"ori", 0, INSN_CLASS_I
, "d,s,j", MATCH_ORI
, MASK_ORI
, match_opcode
, 0 },
482 {"or", 0, INSN_CLASS_I
, "d,s,j", MATCH_ORI
, MASK_ORI
, match_opcode
, INSN_ALIAS
},
483 {"or", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_OR
, MASK_C_OR
, match_opcode
, INSN_ALIAS
},
484 {"or", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_OR
, MASK_C_OR
, match_opcode
, INSN_ALIAS
},
485 {"or", 0, INSN_CLASS_I
, "d,s,t", MATCH_OR
, MASK_OR
, match_opcode
, 0 },
486 {"auipc", 0, INSN_CLASS_I
, "d,u", MATCH_AUIPC
, MASK_AUIPC
, match_opcode
, 0 },
487 {"seqz", 0, INSN_CLASS_I
, "d,s", MATCH_SLTIU
|ENCODE_ITYPE_IMM (1), MASK_SLTIU
| MASK_IMM
, match_opcode
, INSN_ALIAS
},
488 {"snez", 0, INSN_CLASS_I
, "d,t", MATCH_SLTU
, MASK_SLTU
|MASK_RS1
, match_opcode
, INSN_ALIAS
},
489 {"sltz", 0, INSN_CLASS_I
, "d,s", MATCH_SLT
, MASK_SLT
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
490 {"sgtz", 0, INSN_CLASS_I
, "d,t", MATCH_SLT
, MASK_SLT
|MASK_RS1
, match_opcode
, INSN_ALIAS
},
491 {"slti", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTI
, MASK_SLTI
, match_opcode
, 0 },
492 {"slt", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLT
, MASK_SLT
, match_opcode
, 0 },
493 {"slt", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTI
, MASK_SLTI
, match_opcode
, INSN_ALIAS
},
494 {"sltiu", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTIU
, MASK_SLTIU
, match_opcode
, 0 },
495 {"sltu", 0, INSN_CLASS_I
, "d,s,t", MATCH_SLTU
, MASK_SLTU
, match_opcode
, 0 },
496 {"sltu", 0, INSN_CLASS_I
, "d,s,j", MATCH_SLTIU
, MASK_SLTIU
, match_opcode
, INSN_ALIAS
},
497 {"sgt", 0, INSN_CLASS_I
, "d,t,s", MATCH_SLT
, MASK_SLT
, match_opcode
, INSN_ALIAS
},
498 {"sgtu", 0, INSN_CLASS_I
, "d,t,s", MATCH_SLTU
, MASK_SLTU
, match_opcode
, INSN_ALIAS
},
499 {"sb", 0, INSN_CLASS_ZCB
, "Ct,Wcb(Cs)", MATCH_C_SB
, MASK_C_SB
, match_opcode
, INSN_DREF
|INSN_1_BYTE
|INSN_ALIAS
},
500 {"sb", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SB
, MASK_SB
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
501 {"sb", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SB
, match_never
, INSN_MACRO
},
502 {"sh", 0, INSN_CLASS_ZCB
, "Ct,Wch(Cs)", MATCH_C_SH
, MASK_C_SH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
|INSN_ALIAS
},
503 {"sh", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SH
, MASK_SH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
504 {"sh", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SH
, match_never
, INSN_MACRO
},
505 {"sw", 0, INSN_CLASS_C
, "CV,CM(Cc)", MATCH_C_SWSP
, MASK_C_SWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
506 {"sw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_SW
, MASK_C_SW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
507 {"sw", 0, INSN_CLASS_I
, "t,q(s)", MATCH_SW
, MASK_SW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
508 {"sw", 0, INSN_CLASS_I
, "t,A,s", 0, (int) M_SW
, match_never
, INSN_MACRO
},
509 {"fence", 0, INSN_CLASS_I
, "", MATCH_FENCE
|MASK_PRED
|MASK_SUCC
, MASK_FENCE
|MASK_RD
|MASK_RS1
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
510 {"fence", 0, INSN_CLASS_I
, "P,Q", MATCH_FENCE
, MASK_FENCE
|MASK_RD
|MASK_RS1
|(MASK_IMM
& ~MASK_PRED
& ~MASK_SUCC
), match_opcode
, 0 },
511 {"fence.i", 0, INSN_CLASS_ZIFENCEI
, "", MATCH_FENCE_I
, MASK_FENCE
|MASK_RD
|MASK_RS1
|MASK_IMM
, match_opcode
, 0 },
512 {"fence.tso", 0, INSN_CLASS_I
, "", MATCH_FENCE_TSO
, MASK_FENCE_TSO
|MASK_RD
|MASK_RS1
, match_opcode
, 0 },
513 {"rdcycle", 0, INSN_CLASS_I
, "d", MATCH_RDCYCLE
, MASK_RDCYCLE
, match_opcode
, INSN_ALIAS
},
514 {"rdinstret", 0, INSN_CLASS_I
, "d", MATCH_RDINSTRET
, MASK_RDINSTRET
, match_opcode
, INSN_ALIAS
},
515 {"rdtime", 0, INSN_CLASS_I
, "d", MATCH_RDTIME
, MASK_RDTIME
, match_opcode
, INSN_ALIAS
},
516 {"rdcycleh", 32, INSN_CLASS_I
, "d", MATCH_RDCYCLEH
, MASK_RDCYCLEH
, match_opcode
, INSN_ALIAS
},
517 {"rdinstreth", 32, INSN_CLASS_I
, "d", MATCH_RDINSTRETH
, MASK_RDINSTRETH
, match_opcode
, INSN_ALIAS
},
518 {"rdtimeh", 32, INSN_CLASS_I
, "d", MATCH_RDTIMEH
, MASK_RDTIMEH
, match_opcode
, INSN_ALIAS
},
519 {"ecall", 0, INSN_CLASS_I
, "", MATCH_SCALL
, MASK_SCALL
, match_opcode
, 0 },
520 {"scall", 0, INSN_CLASS_I
, "", MATCH_SCALL
, MASK_SCALL
, match_opcode
, 0 },
521 {"xori", 0, INSN_CLASS_I
, "d,s,j", MATCH_XORI
, MASK_XORI
, match_opcode
, 0 },
522 {"xor", 0, INSN_CLASS_I
, "d,s,j", MATCH_XORI
, MASK_XORI
, match_opcode
, INSN_ALIAS
},
523 {"xor", 0, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, INSN_ALIAS
},
524 {"xor", 0, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, INSN_ALIAS
},
525 {"xor", 0, INSN_CLASS_I
, "d,s,t", MATCH_XOR
, MASK_XOR
, match_opcode
, 0 },
526 {"lwu", 64, INSN_CLASS_I
, "d,o(s)", MATCH_LWU
, MASK_LWU
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
527 {"lwu", 64, INSN_CLASS_I
, "d,A", 0, (int) M_LWU
, match_never
, INSN_MACRO
},
528 {"ld", 64, INSN_CLASS_C
, "d,Cn(Cc)", MATCH_C_LDSP
, MASK_C_LDSP
, match_rd_nonzero
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
529 {"ld", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_LD
, MASK_C_LD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
530 {"ld", 64, INSN_CLASS_I
, "d,o(s)", MATCH_LD
, MASK_LD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
531 {"ld", 64, INSN_CLASS_I
, "d,A", 0, (int) M_LD
, match_never
, INSN_MACRO
},
532 {"sd", 64, INSN_CLASS_C
, "CV,CN(Cc)", MATCH_C_SDSP
, MASK_C_SDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
533 {"sd", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_SD
, MASK_C_SD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
534 {"sd", 64, INSN_CLASS_I
, "t,q(s)", MATCH_SD
, MASK_SD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
535 {"sd", 64, INSN_CLASS_I
, "t,A,s", 0, (int) M_SD
, match_never
, INSN_MACRO
},
536 {"sext.w", 64, INSN_CLASS_C
, "d,CU", MATCH_C_ADDIW
, MASK_C_ADDIW
|MASK_RVC_IMM
, match_rd_nonzero
, INSN_ALIAS
},
537 {"sext.w", 64, INSN_CLASS_I
, "d,s", MATCH_ADDIW
, MASK_ADDIW
|MASK_IMM
, match_opcode
, INSN_ALIAS
},
538 {"addiw", 64, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, INSN_ALIAS
},
539 {"addiw", 64, INSN_CLASS_I
, "d,s,j", MATCH_ADDIW
, MASK_ADDIW
, match_opcode
, 0 },
540 {"addw", 64, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, INSN_ALIAS
},
541 {"addw", 64, INSN_CLASS_C
, "Cs,Ct,Cw", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, INSN_ALIAS
},
542 {"addw", 64, INSN_CLASS_C
, "d,CU,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, INSN_ALIAS
},
543 {"addw", 64, INSN_CLASS_I
, "d,s,t", MATCH_ADDW
, MASK_ADDW
, match_opcode
, 0 },
544 {"addw", 64, INSN_CLASS_I
, "d,s,j", MATCH_ADDIW
, MASK_ADDIW
, match_opcode
, INSN_ALIAS
},
545 {"negw", 64, INSN_CLASS_I
, "d,t", MATCH_SUBW
, MASK_SUBW
|MASK_RS1
, match_opcode
, INSN_ALIAS
}, /* sub 0 */
546 {"slliw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SLLIW
, MASK_SLLIW
, match_opcode
, 0 },
547 {"sllw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SLLW
, MASK_SLLW
, match_opcode
, 0 },
548 {"sllw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SLLIW
, MASK_SLLIW
, match_opcode
, INSN_ALIAS
},
549 {"srliw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRLIW
, MASK_SRLIW
, match_opcode
, 0 },
550 {"srlw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SRLW
, MASK_SRLW
, match_opcode
, 0 },
551 {"srlw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRLIW
, MASK_SRLIW
, match_opcode
, INSN_ALIAS
},
552 {"sraiw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRAIW
, MASK_SRAIW
, match_opcode
, 0 },
553 {"sraw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SRAW
, MASK_SRAW
, match_opcode
, 0 },
554 {"sraw", 64, INSN_CLASS_I
, "d,s,<", MATCH_SRAIW
, MASK_SRAIW
, match_opcode
, INSN_ALIAS
},
555 {"subw", 64, INSN_CLASS_C
, "Cs,Cw,Ct", MATCH_C_SUBW
, MASK_C_SUBW
, match_opcode
, INSN_ALIAS
},
556 {"subw", 64, INSN_CLASS_I
, "d,s,t", MATCH_SUBW
, MASK_SUBW
, match_opcode
, 0 },
558 /* Atomic memory operation instruction subset. */
559 {"lr.w", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
, MASK_LR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
560 {"sc.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
, MASK_SC_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
561 {"amoadd.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
, MASK_AMOADD_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
562 {"amoswap.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
, MASK_AMOSWAP_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
563 {"amoand.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
, MASK_AMOAND_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
564 {"amoor.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
, MASK_AMOOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
565 {"amoxor.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
, MASK_AMOXOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
566 {"amomax.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
, MASK_AMOMAX_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
567 {"amomaxu.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
, MASK_AMOMAXU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
568 {"amomin.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
, MASK_AMOMIN_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
569 {"amominu.w", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
, MASK_AMOMINU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
570 {"lr.w.aq", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
|MASK_AQ
, MASK_LR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
571 {"sc.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
|MASK_AQ
, MASK_SC_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
572 {"amoadd.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
|MASK_AQ
, MASK_AMOADD_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
573 {"amoswap.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
|MASK_AQ
, MASK_AMOSWAP_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
574 {"amoand.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
|MASK_AQ
, MASK_AMOAND_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
575 {"amoor.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
|MASK_AQ
, MASK_AMOOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
576 {"amoxor.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
|MASK_AQ
, MASK_AMOXOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
577 {"amomax.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
|MASK_AQ
, MASK_AMOMAX_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
578 {"amomaxu.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
|MASK_AQ
, MASK_AMOMAXU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
579 {"amomin.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
|MASK_AQ
, MASK_AMOMIN_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
580 {"amominu.w.aq", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
|MASK_AQ
, MASK_AMOMINU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
581 {"lr.w.rl", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
|MASK_RL
, MASK_LR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
582 {"sc.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
|MASK_RL
, MASK_SC_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
583 {"amoadd.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
|MASK_RL
, MASK_AMOADD_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
584 {"amoswap.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
|MASK_RL
, MASK_AMOSWAP_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
585 {"amoand.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
|MASK_RL
, MASK_AMOAND_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
586 {"amoor.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
|MASK_RL
, MASK_AMOOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
587 {"amoxor.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
|MASK_RL
, MASK_AMOXOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
588 {"amomax.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
|MASK_RL
, MASK_AMOMAX_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
589 {"amomaxu.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
|MASK_RL
, MASK_AMOMAXU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
590 {"amomin.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
|MASK_RL
, MASK_AMOMIN_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
591 {"amominu.w.rl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
|MASK_RL
, MASK_AMOMINU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
592 {"lr.w.aqrl", 0, INSN_CLASS_A
, "d,0(s)", MATCH_LR_W
|MASK_AQRL
, MASK_LR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
593 {"sc.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_W
|MASK_AQRL
, MASK_SC_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
594 {"amoadd.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_W
|MASK_AQRL
, MASK_AMOADD_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
595 {"amoswap.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_W
|MASK_AQRL
, MASK_AMOSWAP_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
596 {"amoand.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_W
|MASK_AQRL
, MASK_AMOAND_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
597 {"amoor.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_W
|MASK_AQRL
, MASK_AMOOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
598 {"amoxor.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_W
|MASK_AQRL
, MASK_AMOXOR_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
599 {"amomax.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_W
|MASK_AQRL
, MASK_AMOMAX_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
600 {"amomaxu.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_W
|MASK_AQRL
, MASK_AMOMAXU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
601 {"amomin.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_W
|MASK_AQRL
, MASK_AMOMIN_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
602 {"amominu.w.aqrl", 0, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_W
|MASK_AQRL
, MASK_AMOMINU_W
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
603 {"lr.d", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
, MASK_LR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
604 {"sc.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
, MASK_SC_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
605 {"amoadd.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
, MASK_AMOADD_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
606 {"amoswap.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
, MASK_AMOSWAP_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
607 {"amoand.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
, MASK_AMOAND_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
608 {"amoor.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
, MASK_AMOOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
609 {"amoxor.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
, MASK_AMOXOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
610 {"amomax.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
, MASK_AMOMAX_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
611 {"amomaxu.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
, MASK_AMOMAXU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
612 {"amomin.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
, MASK_AMOMIN_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
613 {"amominu.d", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
, MASK_AMOMINU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
614 {"lr.d.aq", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
|MASK_AQ
, MASK_LR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
615 {"sc.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
|MASK_AQ
, MASK_SC_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
616 {"amoadd.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
|MASK_AQ
, MASK_AMOADD_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
617 {"amoswap.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
|MASK_AQ
, MASK_AMOSWAP_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
618 {"amoand.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
|MASK_AQ
, MASK_AMOAND_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
619 {"amoor.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
|MASK_AQ
, MASK_AMOOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
620 {"amoxor.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
|MASK_AQ
, MASK_AMOXOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
621 {"amomax.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
|MASK_AQ
, MASK_AMOMAX_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
622 {"amomaxu.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
|MASK_AQ
, MASK_AMOMAXU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
623 {"amomin.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
|MASK_AQ
, MASK_AMOMIN_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
624 {"amominu.d.aq", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
|MASK_AQ
, MASK_AMOMINU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
625 {"lr.d.rl", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
|MASK_RL
, MASK_LR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
626 {"sc.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
|MASK_RL
, MASK_SC_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
627 {"amoadd.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
|MASK_RL
, MASK_AMOADD_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
628 {"amoswap.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
|MASK_RL
, MASK_AMOSWAP_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
629 {"amoand.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
|MASK_RL
, MASK_AMOAND_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
630 {"amoor.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
|MASK_RL
, MASK_AMOOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
631 {"amoxor.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
|MASK_RL
, MASK_AMOXOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
632 {"amomax.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
|MASK_RL
, MASK_AMOMAX_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
633 {"amomaxu.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
|MASK_RL
, MASK_AMOMAXU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
634 {"amomin.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
|MASK_RL
, MASK_AMOMIN_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
635 {"amominu.d.rl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
|MASK_RL
, MASK_AMOMINU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
636 {"lr.d.aqrl", 64, INSN_CLASS_A
, "d,0(s)", MATCH_LR_D
|MASK_AQRL
, MASK_LR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
637 {"sc.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_SC_D
|MASK_AQRL
, MASK_SC_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
638 {"amoadd.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOADD_D
|MASK_AQRL
, MASK_AMOADD_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
639 {"amoswap.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOSWAP_D
|MASK_AQRL
, MASK_AMOSWAP_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
640 {"amoand.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOAND_D
|MASK_AQRL
, MASK_AMOAND_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
641 {"amoor.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOOR_D
|MASK_AQRL
, MASK_AMOOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
642 {"amoxor.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOXOR_D
|MASK_AQRL
, MASK_AMOXOR_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
643 {"amomax.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAX_D
|MASK_AQRL
, MASK_AMOMAX_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
644 {"amomaxu.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMAXU_D
|MASK_AQRL
, MASK_AMOMAXU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
645 {"amomin.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMIN_D
|MASK_AQRL
, MASK_AMOMIN_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
646 {"amominu.d.aqrl", 64, INSN_CLASS_A
, "d,t,0(s)", MATCH_AMOMINU_D
|MASK_AQRL
, MASK_AMOMINU_D
|MASK_AQRL
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
648 /* Multiply/Divide instruction subset. */
649 {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL
, "Cs,Cw,Ct", MATCH_C_MUL
, MASK_C_MUL
, match_opcode
, INSN_ALIAS
},
650 {"mul", 0, INSN_CLASS_ZMMUL
, "d,s,t", MATCH_MUL
, MASK_MUL
, match_opcode
, 0 },
651 {"mulh", 0, INSN_CLASS_ZMMUL
, "d,s,t", MATCH_MULH
, MASK_MULH
, match_opcode
, 0 },
652 {"mulhu", 0, INSN_CLASS_ZMMUL
, "d,s,t", MATCH_MULHU
, MASK_MULHU
, match_opcode
, 0 },
653 {"mulhsu", 0, INSN_CLASS_ZMMUL
, "d,s,t", MATCH_MULHSU
, MASK_MULHSU
, match_opcode
, 0 },
654 {"div", 0, INSN_CLASS_M
, "d,s,t", MATCH_DIV
, MASK_DIV
, match_opcode
, 0 },
655 {"divu", 0, INSN_CLASS_M
, "d,s,t", MATCH_DIVU
, MASK_DIVU
, match_opcode
, 0 },
656 {"rem", 0, INSN_CLASS_M
, "d,s,t", MATCH_REM
, MASK_REM
, match_opcode
, 0 },
657 {"remu", 0, INSN_CLASS_M
, "d,s,t", MATCH_REMU
, MASK_REMU
, match_opcode
, 0 },
658 {"mulw", 64, INSN_CLASS_ZMMUL
, "d,s,t", MATCH_MULW
, MASK_MULW
, match_opcode
, 0 },
659 {"divw", 64, INSN_CLASS_M
, "d,s,t", MATCH_DIVW
, MASK_DIVW
, match_opcode
, 0 },
660 {"divuw", 64, INSN_CLASS_M
, "d,s,t", MATCH_DIVUW
, MASK_DIVUW
, match_opcode
, 0 },
661 {"remw", 64, INSN_CLASS_M
, "d,s,t", MATCH_REMW
, MASK_REMW
, match_opcode
, 0 },
662 {"remuw", 64, INSN_CLASS_M
, "d,s,t", MATCH_REMUW
, MASK_REMUW
, match_opcode
, 0 },
664 /* Half-precision floating-point instruction subset. */
665 {"flh", 0, INSN_CLASS_ZFHMIN
, "D,o(s)", MATCH_FLH
, MASK_FLH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
666 {"flh", 0, INSN_CLASS_ZFHMIN
, "D,A,s", 0, (int) M_FLH
, match_never
, INSN_MACRO
},
667 {"fsh", 0, INSN_CLASS_ZFHMIN
, "T,q(s)", MATCH_FSH
, MASK_FSH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
668 {"fsh", 0, INSN_CLASS_ZFHMIN
, "T,A,s", 0, (int) M_FSH
, match_never
, INSN_MACRO
},
669 {"fmv.x.h", 0, INSN_CLASS_ZFHMIN
, "d,S", MATCH_FMV_X_H
, MASK_FMV_X_H
, match_opcode
, 0 },
670 {"fmv.h.x", 0, INSN_CLASS_ZFHMIN
, "D,s", MATCH_FMV_H_X
, MASK_FMV_H_X
, match_opcode
, 0 },
671 {"fmv.h", 0, INSN_CLASS_ZFH_INX
, "D,U", MATCH_FSGNJ_H
, MASK_FSGNJ_H
, match_rs1_eq_rs2
, INSN_ALIAS
},
672 {"fneg.h", 0, INSN_CLASS_ZFH_INX
, "D,U", MATCH_FSGNJN_H
, MASK_FSGNJN_H
, match_rs1_eq_rs2
, INSN_ALIAS
},
673 {"fabs.h", 0, INSN_CLASS_ZFH_INX
, "D,U", MATCH_FSGNJX_H
, MASK_FSGNJX_H
, match_rs1_eq_rs2
, INSN_ALIAS
},
674 {"fsgnj.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FSGNJ_H
, MASK_FSGNJ_H
, match_opcode
, 0 },
675 {"fsgnjn.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FSGNJN_H
, MASK_FSGNJN_H
, match_opcode
, 0 },
676 {"fsgnjx.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FSGNJX_H
, MASK_FSGNJX_H
, match_opcode
, 0 },
677 {"fadd.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FADD_H
|MASK_RM
, MASK_FADD_H
|MASK_RM
, match_opcode
, 0 },
678 {"fadd.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,m", MATCH_FADD_H
, MASK_FADD_H
, match_opcode
, 0 },
679 {"fsub.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FSUB_H
|MASK_RM
, MASK_FSUB_H
|MASK_RM
, match_opcode
, 0 },
680 {"fsub.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,m", MATCH_FSUB_H
, MASK_FSUB_H
, match_opcode
, 0 },
681 {"fmul.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FMUL_H
|MASK_RM
, MASK_FMUL_H
|MASK_RM
, match_opcode
, 0 },
682 {"fmul.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,m", MATCH_FMUL_H
, MASK_FMUL_H
, match_opcode
, 0 },
683 {"fdiv.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FDIV_H
|MASK_RM
, MASK_FDIV_H
|MASK_RM
, match_opcode
, 0 },
684 {"fdiv.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,m", MATCH_FDIV_H
, MASK_FDIV_H
, match_opcode
, 0 },
685 {"fsqrt.h", 0, INSN_CLASS_ZFH_INX
, "D,S", MATCH_FSQRT_H
|MASK_RM
, MASK_FSQRT_H
|MASK_RM
, match_opcode
, 0 },
686 {"fsqrt.h", 0, INSN_CLASS_ZFH_INX
, "D,S,m", MATCH_FSQRT_H
, MASK_FSQRT_H
, match_opcode
, 0 },
687 {"fmin.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FMIN_H
, MASK_FMIN_H
, match_opcode
, 0 },
688 {"fmax.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T", MATCH_FMAX_H
, MASK_FMAX_H
, match_opcode
, 0 },
689 {"fmadd.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,R", MATCH_FMADD_H
|MASK_RM
, MASK_FMADD_H
|MASK_RM
, match_opcode
, 0 },
690 {"fmadd.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,R,m", MATCH_FMADD_H
, MASK_FMADD_H
, match_opcode
, 0 },
691 {"fnmadd.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,R", MATCH_FNMADD_H
|MASK_RM
, MASK_FNMADD_H
|MASK_RM
, match_opcode
, 0 },
692 {"fnmadd.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,R,m", MATCH_FNMADD_H
, MASK_FNMADD_H
, match_opcode
, 0 },
693 {"fmsub.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,R", MATCH_FMSUB_H
|MASK_RM
, MASK_FMSUB_H
|MASK_RM
, match_opcode
, 0 },
694 {"fmsub.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,R,m", MATCH_FMSUB_H
, MASK_FMSUB_H
, match_opcode
, 0 },
695 {"fnmsub.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,R", MATCH_FNMSUB_H
|MASK_RM
, MASK_FNMSUB_H
|MASK_RM
, match_opcode
, 0 },
696 {"fnmsub.h", 0, INSN_CLASS_ZFH_INX
, "D,S,T,R,m", MATCH_FNMSUB_H
, MASK_FNMSUB_H
, match_opcode
, 0 },
697 {"fcvt.w.h", 0, INSN_CLASS_ZFH_INX
, "d,S", MATCH_FCVT_W_H
|MASK_RM
, MASK_FCVT_W_H
|MASK_RM
, match_opcode
, 0 },
698 {"fcvt.w.h", 0, INSN_CLASS_ZFH_INX
, "d,S,m", MATCH_FCVT_W_H
, MASK_FCVT_W_H
, match_opcode
, 0 },
699 {"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX
, "d,S", MATCH_FCVT_WU_H
|MASK_RM
, MASK_FCVT_WU_H
|MASK_RM
, match_opcode
, 0 },
700 {"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX
, "d,S,m", MATCH_FCVT_WU_H
, MASK_FCVT_WU_H
, match_opcode
, 0 },
701 {"fcvt.h.w", 0, INSN_CLASS_ZFH_INX
, "D,s", MATCH_FCVT_H_W
|MASK_RM
, MASK_FCVT_H_W
|MASK_RM
, match_opcode
, 0 },
702 {"fcvt.h.w", 0, INSN_CLASS_ZFH_INX
, "D,s,m", MATCH_FCVT_H_W
, MASK_FCVT_H_W
, match_opcode
, 0 },
703 {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX
, "D,s", MATCH_FCVT_H_WU
|MASK_RM
, MASK_FCVT_H_WU
|MASK_RM
, match_opcode
, 0 },
704 {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX
, "D,s,m", MATCH_FCVT_H_WU
, MASK_FCVT_H_WU
, match_opcode
, 0 },
705 {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX
, "D,S", MATCH_FCVT_S_H
, MASK_FCVT_S_H
|MASK_RM
, match_opcode
, 0 },
706 {"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX
, "D,S", MATCH_FCVT_D_H
, MASK_FCVT_D_H
|MASK_RM
, match_opcode
, 0 },
707 {"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX
, "D,S", MATCH_FCVT_Q_H
, MASK_FCVT_Q_H
|MASK_RM
, match_opcode
, 0 },
708 {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX
, "D,S", MATCH_FCVT_H_S
|MASK_RM
, MASK_FCVT_H_S
|MASK_RM
, match_opcode
, 0 },
709 {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX
, "D,S,m", MATCH_FCVT_H_S
, MASK_FCVT_H_S
, match_opcode
, 0 },
710 {"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX
, "D,S", MATCH_FCVT_H_D
|MASK_RM
, MASK_FCVT_H_D
|MASK_RM
, match_opcode
, 0 },
711 {"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX
, "D,S,m", MATCH_FCVT_H_D
, MASK_FCVT_H_D
, match_opcode
, 0 },
712 {"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX
, "D,S", MATCH_FCVT_H_Q
|MASK_RM
, MASK_FCVT_H_Q
|MASK_RM
, match_opcode
, 0 },
713 {"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX
, "D,S,m", MATCH_FCVT_H_Q
, MASK_FCVT_H_Q
, match_opcode
, 0 },
714 {"fclass.h", 0, INSN_CLASS_ZFH_INX
, "d,S", MATCH_FCLASS_H
, MASK_FCLASS_H
, match_opcode
, 0 },
715 {"feq.h", 0, INSN_CLASS_ZFH_INX
, "d,S,T", MATCH_FEQ_H
, MASK_FEQ_H
, match_opcode
, 0 },
716 {"flt.h", 0, INSN_CLASS_ZFH_INX
, "d,S,T", MATCH_FLT_H
, MASK_FLT_H
, match_opcode
, 0 },
717 {"fle.h", 0, INSN_CLASS_ZFH_INX
, "d,S,T", MATCH_FLE_H
, MASK_FLE_H
, match_opcode
, 0 },
718 {"fgt.h", 0, INSN_CLASS_ZFH_INX
, "d,T,S", MATCH_FLT_H
, MASK_FLT_H
, match_opcode
, 0 },
719 {"fge.h", 0, INSN_CLASS_ZFH_INX
, "d,T,S", MATCH_FLE_H
, MASK_FLE_H
, match_opcode
, 0 },
720 {"fcvt.l.h", 64, INSN_CLASS_ZFH_INX
, "d,S", MATCH_FCVT_L_H
|MASK_RM
, MASK_FCVT_L_H
|MASK_RM
, match_opcode
, 0 },
721 {"fcvt.l.h", 64, INSN_CLASS_ZFH_INX
, "d,S,m", MATCH_FCVT_L_H
, MASK_FCVT_L_H
, match_opcode
, 0 },
722 {"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX
, "d,S", MATCH_FCVT_LU_H
|MASK_RM
, MASK_FCVT_LU_H
|MASK_RM
, match_opcode
, 0 },
723 {"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX
, "d,S,m", MATCH_FCVT_LU_H
, MASK_FCVT_LU_H
, match_opcode
, 0 },
724 {"fcvt.h.l", 64, INSN_CLASS_ZFH_INX
, "D,s", MATCH_FCVT_H_L
|MASK_RM
, MASK_FCVT_H_L
|MASK_RM
, match_opcode
, 0 },
725 {"fcvt.h.l", 64, INSN_CLASS_ZFH_INX
, "D,s,m", MATCH_FCVT_H_L
, MASK_FCVT_H_L
, match_opcode
, 0 },
726 {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX
, "D,s", MATCH_FCVT_H_LU
|MASK_RM
, MASK_FCVT_H_LU
|MASK_RM
, match_opcode
, 0 },
727 {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX
, "D,s,m", MATCH_FCVT_H_LU
, MASK_FCVT_H_LU
, match_opcode
, 0 },
729 /* Single-precision floating-point instruction subset. */
730 {"frcsr", 0, INSN_CLASS_F_INX
, "d", MATCH_FRCSR
, MASK_FRCSR
, match_opcode
, INSN_ALIAS
},
731 {"frsr", 0, INSN_CLASS_F_INX
, "d", MATCH_FRCSR
, MASK_FRCSR
, match_opcode
, INSN_ALIAS
},
732 {"fscsr", 0, INSN_CLASS_F_INX
, "s", MATCH_FSCSR
, MASK_FSCSR
|MASK_RD
, match_opcode
, INSN_ALIAS
},
733 {"fscsr", 0, INSN_CLASS_F_INX
, "d,s", MATCH_FSCSR
, MASK_FSCSR
, match_opcode
, INSN_ALIAS
},
734 {"fssr", 0, INSN_CLASS_F_INX
, "s", MATCH_FSCSR
, MASK_FSCSR
|MASK_RD
, match_opcode
, INSN_ALIAS
},
735 {"fssr", 0, INSN_CLASS_F_INX
, "d,s", MATCH_FSCSR
, MASK_FSCSR
, match_opcode
, INSN_ALIAS
},
736 {"frrm", 0, INSN_CLASS_F_INX
, "d", MATCH_FRRM
, MASK_FRRM
, match_opcode
, INSN_ALIAS
},
737 {"fsrm", 0, INSN_CLASS_F_INX
, "s", MATCH_FSRM
, MASK_FSRM
|MASK_RD
, match_opcode
, INSN_ALIAS
},
738 {"fsrm", 0, INSN_CLASS_F_INX
, "d,s", MATCH_FSRM
, MASK_FSRM
, match_opcode
, INSN_ALIAS
},
739 {"fsrmi", 0, INSN_CLASS_F_INX
, "d,Z", MATCH_FSRMI
, MASK_FSRMI
, match_opcode
, INSN_ALIAS
},
740 {"fsrmi", 0, INSN_CLASS_F_INX
, "Z", MATCH_FSRMI
, MASK_FSRMI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
741 {"frflags", 0, INSN_CLASS_F_INX
, "d", MATCH_FRFLAGS
, MASK_FRFLAGS
, match_opcode
, INSN_ALIAS
},
742 {"fsflags", 0, INSN_CLASS_F_INX
, "s", MATCH_FSFLAGS
, MASK_FSFLAGS
|MASK_RD
, match_opcode
, INSN_ALIAS
},
743 {"fsflags", 0, INSN_CLASS_F_INX
, "d,s", MATCH_FSFLAGS
, MASK_FSFLAGS
, match_opcode
, INSN_ALIAS
},
744 {"fsflagsi", 0, INSN_CLASS_F_INX
, "d,Z", MATCH_FSFLAGSI
, MASK_FSFLAGSI
, match_opcode
, INSN_ALIAS
},
745 {"fsflagsi", 0, INSN_CLASS_F_INX
, "Z", MATCH_FSFLAGSI
, MASK_FSFLAGSI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
746 {"flw", 32, INSN_CLASS_F_AND_C
, "D,Cm(Cc)", MATCH_C_FLWSP
, MASK_C_FLWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
747 {"flw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FLW
, MASK_C_FLW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
748 {"flw", 0, INSN_CLASS_F
, "D,o(s)", MATCH_FLW
, MASK_FLW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
749 {"flw", 0, INSN_CLASS_F
, "D,A,s", 0, (int) M_FLW
, match_never
, INSN_MACRO
},
750 {"fsw", 32, INSN_CLASS_F_AND_C
, "CT,CM(Cc)", MATCH_C_FSWSP
, MASK_C_FSWSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
751 {"fsw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FSW
, MASK_C_FSW
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_4_BYTE
},
752 {"fsw", 0, INSN_CLASS_F
, "T,q(s)", MATCH_FSW
, MASK_FSW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
753 {"fsw", 0, INSN_CLASS_F
, "T,A,s", 0, (int) M_FSW
, match_never
, INSN_MACRO
},
754 {"fmv.x.w", 0, INSN_CLASS_F
, "d,S", MATCH_FMV_X_S
, MASK_FMV_X_S
, match_opcode
, 0 },
755 {"fmv.w.x", 0, INSN_CLASS_F
, "D,s", MATCH_FMV_S_X
, MASK_FMV_S_X
, match_opcode
, 0 },
756 {"fmv.x.s", 0, INSN_CLASS_F
, "d,S", MATCH_FMV_X_S
, MASK_FMV_X_S
, match_opcode
, 0 },
757 {"fmv.s.x", 0, INSN_CLASS_F
, "D,s", MATCH_FMV_S_X
, MASK_FMV_S_X
, match_opcode
, 0 },
758 {"fmv.s", 0, INSN_CLASS_F_INX
, "D,U", MATCH_FSGNJ_S
, MASK_FSGNJ_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
759 {"fneg.s", 0, INSN_CLASS_F_INX
, "D,U", MATCH_FSGNJN_S
, MASK_FSGNJN_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
760 {"fabs.s", 0, INSN_CLASS_F_INX
, "D,U", MATCH_FSGNJX_S
, MASK_FSGNJX_S
, match_rs1_eq_rs2
, INSN_ALIAS
},
761 {"fsgnj.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FSGNJ_S
, MASK_FSGNJ_S
, match_opcode
, 0 },
762 {"fsgnjn.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FSGNJN_S
, MASK_FSGNJN_S
, match_opcode
, 0 },
763 {"fsgnjx.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FSGNJX_S
, MASK_FSGNJX_S
, match_opcode
, 0 },
764 {"fadd.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FADD_S
|MASK_RM
, MASK_FADD_S
|MASK_RM
, match_opcode
, 0 },
765 {"fadd.s", 0, INSN_CLASS_F_INX
, "D,S,T,m", MATCH_FADD_S
, MASK_FADD_S
, match_opcode
, 0 },
766 {"fsub.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FSUB_S
|MASK_RM
, MASK_FSUB_S
|MASK_RM
, match_opcode
, 0 },
767 {"fsub.s", 0, INSN_CLASS_F_INX
, "D,S,T,m", MATCH_FSUB_S
, MASK_FSUB_S
, match_opcode
, 0 },
768 {"fmul.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FMUL_S
|MASK_RM
, MASK_FMUL_S
|MASK_RM
, match_opcode
, 0 },
769 {"fmul.s", 0, INSN_CLASS_F_INX
, "D,S,T,m", MATCH_FMUL_S
, MASK_FMUL_S
, match_opcode
, 0 },
770 {"fdiv.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FDIV_S
|MASK_RM
, MASK_FDIV_S
|MASK_RM
, match_opcode
, 0 },
771 {"fdiv.s", 0, INSN_CLASS_F_INX
, "D,S,T,m", MATCH_FDIV_S
, MASK_FDIV_S
, match_opcode
, 0 },
772 {"fsqrt.s", 0, INSN_CLASS_F_INX
, "D,S", MATCH_FSQRT_S
|MASK_RM
, MASK_FSQRT_S
|MASK_RM
, match_opcode
, 0 },
773 {"fsqrt.s", 0, INSN_CLASS_F_INX
, "D,S,m", MATCH_FSQRT_S
, MASK_FSQRT_S
, match_opcode
, 0 },
774 {"fmin.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FMIN_S
, MASK_FMIN_S
, match_opcode
, 0 },
775 {"fmax.s", 0, INSN_CLASS_F_INX
, "D,S,T", MATCH_FMAX_S
, MASK_FMAX_S
, match_opcode
, 0 },
776 {"fmadd.s", 0, INSN_CLASS_F_INX
, "D,S,T,R", MATCH_FMADD_S
|MASK_RM
, MASK_FMADD_S
|MASK_RM
, match_opcode
, 0 },
777 {"fmadd.s", 0, INSN_CLASS_F_INX
, "D,S,T,R,m", MATCH_FMADD_S
, MASK_FMADD_S
, match_opcode
, 0 },
778 {"fnmadd.s", 0, INSN_CLASS_F_INX
, "D,S,T,R", MATCH_FNMADD_S
|MASK_RM
, MASK_FNMADD_S
|MASK_RM
, match_opcode
, 0 },
779 {"fnmadd.s", 0, INSN_CLASS_F_INX
, "D,S,T,R,m", MATCH_FNMADD_S
, MASK_FNMADD_S
, match_opcode
, 0 },
780 {"fmsub.s", 0, INSN_CLASS_F_INX
, "D,S,T,R", MATCH_FMSUB_S
|MASK_RM
, MASK_FMSUB_S
|MASK_RM
, match_opcode
, 0 },
781 {"fmsub.s", 0, INSN_CLASS_F_INX
, "D,S,T,R,m", MATCH_FMSUB_S
, MASK_FMSUB_S
, match_opcode
, 0 },
782 {"fnmsub.s", 0, INSN_CLASS_F_INX
, "D,S,T,R", MATCH_FNMSUB_S
|MASK_RM
, MASK_FNMSUB_S
|MASK_RM
, match_opcode
, 0 },
783 {"fnmsub.s", 0, INSN_CLASS_F_INX
, "D,S,T,R,m", MATCH_FNMSUB_S
, MASK_FNMSUB_S
, match_opcode
, 0 },
784 {"fcvt.w.s", 0, INSN_CLASS_F_INX
, "d,S", MATCH_FCVT_W_S
|MASK_RM
, MASK_FCVT_W_S
|MASK_RM
, match_opcode
, 0 },
785 {"fcvt.w.s", 0, INSN_CLASS_F_INX
, "d,S,m", MATCH_FCVT_W_S
, MASK_FCVT_W_S
, match_opcode
, 0 },
786 {"fcvt.wu.s", 0, INSN_CLASS_F_INX
, "d,S", MATCH_FCVT_WU_S
|MASK_RM
, MASK_FCVT_WU_S
|MASK_RM
, match_opcode
, 0 },
787 {"fcvt.wu.s", 0, INSN_CLASS_F_INX
, "d,S,m", MATCH_FCVT_WU_S
, MASK_FCVT_WU_S
, match_opcode
, 0 },
788 {"fcvt.s.w", 0, INSN_CLASS_F_INX
, "D,s", MATCH_FCVT_S_W
|MASK_RM
, MASK_FCVT_S_W
|MASK_RM
, match_opcode
, 0 },
789 {"fcvt.s.w", 0, INSN_CLASS_F_INX
, "D,s,m", MATCH_FCVT_S_W
, MASK_FCVT_S_W
, match_opcode
, 0 },
790 {"fcvt.s.wu", 0, INSN_CLASS_F_INX
, "D,s", MATCH_FCVT_S_WU
|MASK_RM
, MASK_FCVT_S_WU
|MASK_RM
, match_opcode
, 0 },
791 {"fcvt.s.wu", 0, INSN_CLASS_F_INX
, "D,s,m", MATCH_FCVT_S_WU
, MASK_FCVT_S_WU
, match_opcode
, 0 },
792 {"fclass.s", 0, INSN_CLASS_F_INX
, "d,S", MATCH_FCLASS_S
, MASK_FCLASS_S
, match_opcode
, 0 },
793 {"feq.s", 0, INSN_CLASS_F_INX
, "d,S,T", MATCH_FEQ_S
, MASK_FEQ_S
, match_opcode
, 0 },
794 {"flt.s", 0, INSN_CLASS_F_INX
, "d,S,T", MATCH_FLT_S
, MASK_FLT_S
, match_opcode
, 0 },
795 {"fle.s", 0, INSN_CLASS_F_INX
, "d,S,T", MATCH_FLE_S
, MASK_FLE_S
, match_opcode
, 0 },
796 {"fgt.s", 0, INSN_CLASS_F_INX
, "d,T,S", MATCH_FLT_S
, MASK_FLT_S
, match_opcode
, 0 },
797 {"fge.s", 0, INSN_CLASS_F_INX
, "d,T,S", MATCH_FLE_S
, MASK_FLE_S
, match_opcode
, 0 },
798 {"fcvt.l.s", 64, INSN_CLASS_F_INX
, "d,S", MATCH_FCVT_L_S
|MASK_RM
, MASK_FCVT_L_S
|MASK_RM
, match_opcode
, 0 },
799 {"fcvt.l.s", 64, INSN_CLASS_F_INX
, "d,S,m", MATCH_FCVT_L_S
, MASK_FCVT_L_S
, match_opcode
, 0 },
800 {"fcvt.lu.s", 64, INSN_CLASS_F_INX
, "d,S", MATCH_FCVT_LU_S
|MASK_RM
, MASK_FCVT_LU_S
|MASK_RM
, match_opcode
, 0 },
801 {"fcvt.lu.s", 64, INSN_CLASS_F_INX
, "d,S,m", MATCH_FCVT_LU_S
, MASK_FCVT_LU_S
, match_opcode
, 0 },
802 {"fcvt.s.l", 64, INSN_CLASS_F_INX
, "D,s", MATCH_FCVT_S_L
|MASK_RM
, MASK_FCVT_S_L
|MASK_RM
, match_opcode
, 0 },
803 {"fcvt.s.l", 64, INSN_CLASS_F_INX
, "D,s,m", MATCH_FCVT_S_L
, MASK_FCVT_S_L
, match_opcode
, 0 },
804 {"fcvt.s.lu", 64, INSN_CLASS_F_INX
, "D,s", MATCH_FCVT_S_LU
|MASK_RM
, MASK_FCVT_S_LU
|MASK_RM
, match_opcode
, 0 },
805 {"fcvt.s.lu", 64, INSN_CLASS_F_INX
, "D,s,m", MATCH_FCVT_S_LU
, MASK_FCVT_S_LU
, match_opcode
, 0 },
807 /* Double-precision floating-point instruction subset. */
808 {"fld", 0, INSN_CLASS_D_AND_C
, "D,Cn(Cc)", MATCH_C_FLDSP
, MASK_C_FLDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
809 {"fld", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FLD
, MASK_C_FLD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
810 {"fld", 0, INSN_CLASS_D
, "D,o(s)", MATCH_FLD
, MASK_FLD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
811 {"fld", 0, INSN_CLASS_D
, "D,A,s", 0, (int) M_FLD
, match_never
, INSN_MACRO
},
812 {"fsd", 0, INSN_CLASS_D_AND_C
, "CT,CN(Cc)", MATCH_C_FSDSP
, MASK_C_FSDSP
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
813 {"fsd", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FSD
, MASK_C_FSD
, match_opcode
, INSN_ALIAS
|INSN_DREF
|INSN_8_BYTE
},
814 {"fsd", 0, INSN_CLASS_D
, "T,q(s)", MATCH_FSD
, MASK_FSD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
815 {"fsd", 0, INSN_CLASS_D
, "T,A,s", 0, (int) M_FSD
, match_never
, INSN_MACRO
},
816 {"fmv.d", 0, INSN_CLASS_D_INX
, "D,U", MATCH_FSGNJ_D
, MASK_FSGNJ_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
817 {"fneg.d", 0, INSN_CLASS_D_INX
, "D,U", MATCH_FSGNJN_D
, MASK_FSGNJN_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
818 {"fabs.d", 0, INSN_CLASS_D_INX
, "D,U", MATCH_FSGNJX_D
, MASK_FSGNJX_D
, match_rs1_eq_rs2
, INSN_ALIAS
},
819 {"fsgnj.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FSGNJ_D
, MASK_FSGNJ_D
, match_opcode
, 0 },
820 {"fsgnjn.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FSGNJN_D
, MASK_FSGNJN_D
, match_opcode
, 0 },
821 {"fsgnjx.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FSGNJX_D
, MASK_FSGNJX_D
, match_opcode
, 0 },
822 {"fadd.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FADD_D
|MASK_RM
, MASK_FADD_D
|MASK_RM
, match_opcode
, 0 },
823 {"fadd.d", 0, INSN_CLASS_D_INX
, "D,S,T,m", MATCH_FADD_D
, MASK_FADD_D
, match_opcode
, 0 },
824 {"fsub.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FSUB_D
|MASK_RM
, MASK_FSUB_D
|MASK_RM
, match_opcode
, 0 },
825 {"fsub.d", 0, INSN_CLASS_D_INX
, "D,S,T,m", MATCH_FSUB_D
, MASK_FSUB_D
, match_opcode
, 0 },
826 {"fmul.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FMUL_D
|MASK_RM
, MASK_FMUL_D
|MASK_RM
, match_opcode
, 0 },
827 {"fmul.d", 0, INSN_CLASS_D_INX
, "D,S,T,m", MATCH_FMUL_D
, MASK_FMUL_D
, match_opcode
, 0 },
828 {"fdiv.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FDIV_D
|MASK_RM
, MASK_FDIV_D
|MASK_RM
, match_opcode
, 0 },
829 {"fdiv.d", 0, INSN_CLASS_D_INX
, "D,S,T,m", MATCH_FDIV_D
, MASK_FDIV_D
, match_opcode
, 0 },
830 {"fsqrt.d", 0, INSN_CLASS_D_INX
, "D,S", MATCH_FSQRT_D
|MASK_RM
, MASK_FSQRT_D
|MASK_RM
, match_opcode
, 0 },
831 {"fsqrt.d", 0, INSN_CLASS_D_INX
, "D,S,m", MATCH_FSQRT_D
, MASK_FSQRT_D
, match_opcode
, 0 },
832 {"fmin.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FMIN_D
, MASK_FMIN_D
, match_opcode
, 0 },
833 {"fmax.d", 0, INSN_CLASS_D_INX
, "D,S,T", MATCH_FMAX_D
, MASK_FMAX_D
, match_opcode
, 0 },
834 {"fmadd.d", 0, INSN_CLASS_D_INX
, "D,S,T,R", MATCH_FMADD_D
|MASK_RM
, MASK_FMADD_D
|MASK_RM
, match_opcode
, 0 },
835 {"fmadd.d", 0, INSN_CLASS_D_INX
, "D,S,T,R,m", MATCH_FMADD_D
, MASK_FMADD_D
, match_opcode
, 0 },
836 {"fnmadd.d", 0, INSN_CLASS_D_INX
, "D,S,T,R", MATCH_FNMADD_D
|MASK_RM
, MASK_FNMADD_D
|MASK_RM
, match_opcode
, 0 },
837 {"fnmadd.d", 0, INSN_CLASS_D_INX
, "D,S,T,R,m", MATCH_FNMADD_D
, MASK_FNMADD_D
, match_opcode
, 0 },
838 {"fmsub.d", 0, INSN_CLASS_D_INX
, "D,S,T,R", MATCH_FMSUB_D
|MASK_RM
, MASK_FMSUB_D
|MASK_RM
, match_opcode
, 0 },
839 {"fmsub.d", 0, INSN_CLASS_D_INX
, "D,S,T,R,m", MATCH_FMSUB_D
, MASK_FMSUB_D
, match_opcode
, 0 },
840 {"fnmsub.d", 0, INSN_CLASS_D_INX
, "D,S,T,R", MATCH_FNMSUB_D
|MASK_RM
, MASK_FNMSUB_D
|MASK_RM
, match_opcode
, 0 },
841 {"fnmsub.d", 0, INSN_CLASS_D_INX
, "D,S,T,R,m", MATCH_FNMSUB_D
, MASK_FNMSUB_D
, match_opcode
, 0 },
842 {"fcvt.w.d", 0, INSN_CLASS_D_INX
, "d,S", MATCH_FCVT_W_D
|MASK_RM
, MASK_FCVT_W_D
|MASK_RM
, match_opcode
, 0 },
843 {"fcvt.w.d", 0, INSN_CLASS_D_INX
, "d,S,m", MATCH_FCVT_W_D
, MASK_FCVT_W_D
, match_opcode
, 0 },
844 {"fcvt.wu.d", 0, INSN_CLASS_D_INX
, "d,S", MATCH_FCVT_WU_D
|MASK_RM
, MASK_FCVT_WU_D
|MASK_RM
, match_opcode
, 0 },
845 {"fcvt.wu.d", 0, INSN_CLASS_D_INX
, "d,S,m", MATCH_FCVT_WU_D
, MASK_FCVT_WU_D
, match_opcode
, 0 },
846 {"fcvt.d.w", 0, INSN_CLASS_D_INX
, "D,s", MATCH_FCVT_D_W
, MASK_FCVT_D_W
|MASK_RM
, match_opcode
, 0 },
847 {"fcvt.d.wu", 0, INSN_CLASS_D_INX
, "D,s", MATCH_FCVT_D_WU
, MASK_FCVT_D_WU
|MASK_RM
, match_opcode
, 0 },
848 {"fcvt.d.s", 0, INSN_CLASS_D_INX
, "D,S", MATCH_FCVT_D_S
, MASK_FCVT_D_S
|MASK_RM
, match_opcode
, 0 },
849 {"fcvt.s.d", 0, INSN_CLASS_D_INX
, "D,S", MATCH_FCVT_S_D
|MASK_RM
, MASK_FCVT_S_D
|MASK_RM
, match_opcode
, 0 },
850 {"fcvt.s.d", 0, INSN_CLASS_D_INX
, "D,S,m", MATCH_FCVT_S_D
, MASK_FCVT_S_D
, match_opcode
, 0 },
851 {"fclass.d", 0, INSN_CLASS_D_INX
, "d,S", MATCH_FCLASS_D
, MASK_FCLASS_D
, match_opcode
, 0 },
852 {"feq.d", 0, INSN_CLASS_D_INX
, "d,S,T", MATCH_FEQ_D
, MASK_FEQ_D
, match_opcode
, 0 },
853 {"flt.d", 0, INSN_CLASS_D_INX
, "d,S,T", MATCH_FLT_D
, MASK_FLT_D
, match_opcode
, 0 },
854 {"fle.d", 0, INSN_CLASS_D_INX
, "d,S,T", MATCH_FLE_D
, MASK_FLE_D
, match_opcode
, 0 },
855 {"fgt.d", 0, INSN_CLASS_D_INX
, "d,T,S", MATCH_FLT_D
, MASK_FLT_D
, match_opcode
, 0 },
856 {"fge.d", 0, INSN_CLASS_D_INX
, "d,T,S", MATCH_FLE_D
, MASK_FLE_D
, match_opcode
, 0 },
857 {"fmv.x.d", 64, INSN_CLASS_D
, "d,S", MATCH_FMV_X_D
, MASK_FMV_X_D
, match_opcode
, 0 },
858 {"fmv.d.x", 64, INSN_CLASS_D
, "D,s", MATCH_FMV_D_X
, MASK_FMV_D_X
, match_opcode
, 0 },
859 {"fcvt.l.d", 64, INSN_CLASS_D_INX
, "d,S", MATCH_FCVT_L_D
|MASK_RM
, MASK_FCVT_L_D
|MASK_RM
, match_opcode
, 0 },
860 {"fcvt.l.d", 64, INSN_CLASS_D_INX
, "d,S,m", MATCH_FCVT_L_D
, MASK_FCVT_L_D
, match_opcode
, 0 },
861 {"fcvt.lu.d", 64, INSN_CLASS_D_INX
, "d,S", MATCH_FCVT_LU_D
|MASK_RM
, MASK_FCVT_LU_D
|MASK_RM
, match_opcode
, 0 },
862 {"fcvt.lu.d", 64, INSN_CLASS_D_INX
, "d,S,m", MATCH_FCVT_LU_D
, MASK_FCVT_LU_D
, match_opcode
, 0 },
863 {"fcvt.d.l", 64, INSN_CLASS_D_INX
, "D,s", MATCH_FCVT_D_L
|MASK_RM
, MASK_FCVT_D_L
|MASK_RM
, match_opcode
, 0 },
864 {"fcvt.d.l", 64, INSN_CLASS_D_INX
, "D,s,m", MATCH_FCVT_D_L
, MASK_FCVT_D_L
, match_opcode
, 0 },
865 {"fcvt.d.lu", 64, INSN_CLASS_D_INX
, "D,s", MATCH_FCVT_D_LU
|MASK_RM
, MASK_FCVT_D_LU
|MASK_RM
, match_opcode
, 0 },
866 {"fcvt.d.lu", 64, INSN_CLASS_D_INX
, "D,s,m", MATCH_FCVT_D_LU
, MASK_FCVT_D_LU
, match_opcode
, 0 },
868 /* Quad-precision floating-point instruction subset. */
869 {"flq", 0, INSN_CLASS_Q
, "D,o(s)", MATCH_FLQ
, MASK_FLQ
, match_opcode
, INSN_DREF
|INSN_16_BYTE
},
870 {"flq", 0, INSN_CLASS_Q
, "D,A,s", 0, (int) M_FLQ
, match_never
, INSN_MACRO
},
871 {"fsq", 0, INSN_CLASS_Q
, "T,q(s)", MATCH_FSQ
, MASK_FSQ
, match_opcode
, INSN_DREF
|INSN_16_BYTE
},
872 {"fsq", 0, INSN_CLASS_Q
, "T,A,s", 0, (int) M_FSQ
, match_never
, INSN_MACRO
},
873 {"fmv.q", 0, INSN_CLASS_Q_INX
, "D,U", MATCH_FSGNJ_Q
, MASK_FSGNJ_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
874 {"fneg.q", 0, INSN_CLASS_Q_INX
, "D,U", MATCH_FSGNJN_Q
, MASK_FSGNJN_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
875 {"fabs.q", 0, INSN_CLASS_Q_INX
, "D,U", MATCH_FSGNJX_Q
, MASK_FSGNJX_Q
, match_rs1_eq_rs2
, INSN_ALIAS
},
876 {"fsgnj.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FSGNJ_Q
, MASK_FSGNJ_Q
, match_opcode
, 0 },
877 {"fsgnjn.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FSGNJN_Q
, MASK_FSGNJN_Q
, match_opcode
, 0 },
878 {"fsgnjx.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FSGNJX_Q
, MASK_FSGNJX_Q
, match_opcode
, 0 },
879 {"fadd.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FADD_Q
|MASK_RM
, MASK_FADD_Q
|MASK_RM
, match_opcode
, 0 },
880 {"fadd.q", 0, INSN_CLASS_Q_INX
, "D,S,T,m", MATCH_FADD_Q
, MASK_FADD_Q
, match_opcode
, 0 },
881 {"fsub.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FSUB_Q
|MASK_RM
, MASK_FSUB_Q
|MASK_RM
, match_opcode
, 0 },
882 {"fsub.q", 0, INSN_CLASS_Q_INX
, "D,S,T,m", MATCH_FSUB_Q
, MASK_FSUB_Q
, match_opcode
, 0 },
883 {"fmul.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FMUL_Q
|MASK_RM
, MASK_FMUL_Q
|MASK_RM
, match_opcode
, 0 },
884 {"fmul.q", 0, INSN_CLASS_Q_INX
, "D,S,T,m", MATCH_FMUL_Q
, MASK_FMUL_Q
, match_opcode
, 0 },
885 {"fdiv.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FDIV_Q
|MASK_RM
, MASK_FDIV_Q
|MASK_RM
, match_opcode
, 0 },
886 {"fdiv.q", 0, INSN_CLASS_Q_INX
, "D,S,T,m", MATCH_FDIV_Q
, MASK_FDIV_Q
, match_opcode
, 0 },
887 {"fsqrt.q", 0, INSN_CLASS_Q_INX
, "D,S", MATCH_FSQRT_Q
|MASK_RM
, MASK_FSQRT_Q
|MASK_RM
, match_opcode
, 0 },
888 {"fsqrt.q", 0, INSN_CLASS_Q_INX
, "D,S,m", MATCH_FSQRT_Q
, MASK_FSQRT_Q
, match_opcode
, 0 },
889 {"fmin.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FMIN_Q
, MASK_FMIN_Q
, match_opcode
, 0 },
890 {"fmax.q", 0, INSN_CLASS_Q_INX
, "D,S,T", MATCH_FMAX_Q
, MASK_FMAX_Q
, match_opcode
, 0 },
891 {"fmadd.q", 0, INSN_CLASS_Q_INX
, "D,S,T,R", MATCH_FMADD_Q
|MASK_RM
, MASK_FMADD_Q
|MASK_RM
, match_opcode
, 0 },
892 {"fmadd.q", 0, INSN_CLASS_Q_INX
, "D,S,T,R,m", MATCH_FMADD_Q
, MASK_FMADD_Q
, match_opcode
, 0 },
893 {"fnmadd.q", 0, INSN_CLASS_Q_INX
, "D,S,T,R", MATCH_FNMADD_Q
|MASK_RM
, MASK_FNMADD_Q
|MASK_RM
, match_opcode
, 0 },
894 {"fnmadd.q", 0, INSN_CLASS_Q_INX
, "D,S,T,R,m", MATCH_FNMADD_Q
, MASK_FNMADD_Q
, match_opcode
, 0 },
895 {"fmsub.q", 0, INSN_CLASS_Q_INX
, "D,S,T,R", MATCH_FMSUB_Q
|MASK_RM
, MASK_FMSUB_Q
|MASK_RM
, match_opcode
, 0 },
896 {"fmsub.q", 0, INSN_CLASS_Q_INX
, "D,S,T,R,m", MATCH_FMSUB_Q
, MASK_FMSUB_Q
, match_opcode
, 0 },
897 {"fnmsub.q", 0, INSN_CLASS_Q_INX
, "D,S,T,R", MATCH_FNMSUB_Q
|MASK_RM
, MASK_FNMSUB_Q
|MASK_RM
, match_opcode
, 0 },
898 {"fnmsub.q", 0, INSN_CLASS_Q_INX
, "D,S,T,R,m", MATCH_FNMSUB_Q
, MASK_FNMSUB_Q
, match_opcode
, 0 },
899 {"fcvt.w.q", 0, INSN_CLASS_Q_INX
, "d,S", MATCH_FCVT_W_Q
|MASK_RM
, MASK_FCVT_W_Q
|MASK_RM
, match_opcode
, 0 },
900 {"fcvt.w.q", 0, INSN_CLASS_Q_INX
, "d,S,m", MATCH_FCVT_W_Q
, MASK_FCVT_W_Q
, match_opcode
, 0 },
901 {"fcvt.wu.q", 0, INSN_CLASS_Q_INX
, "d,S", MATCH_FCVT_WU_Q
|MASK_RM
, MASK_FCVT_WU_Q
|MASK_RM
, match_opcode
, 0 },
902 {"fcvt.wu.q", 0, INSN_CLASS_Q_INX
, "d,S,m", MATCH_FCVT_WU_Q
, MASK_FCVT_WU_Q
, match_opcode
, 0 },
903 {"fcvt.q.w", 0, INSN_CLASS_Q_INX
, "D,s", MATCH_FCVT_Q_W
, MASK_FCVT_Q_W
|MASK_RM
, match_opcode
, 0 },
904 {"fcvt.q.wu", 0, INSN_CLASS_Q_INX
, "D,s", MATCH_FCVT_Q_WU
, MASK_FCVT_Q_WU
|MASK_RM
, match_opcode
, 0 },
905 {"fcvt.q.s", 0, INSN_CLASS_Q_INX
, "D,S", MATCH_FCVT_Q_S
, MASK_FCVT_Q_S
|MASK_RM
, match_opcode
, 0 },
906 {"fcvt.q.d", 0, INSN_CLASS_Q_INX
, "D,S", MATCH_FCVT_Q_D
, MASK_FCVT_Q_D
|MASK_RM
, match_opcode
, 0 },
907 {"fcvt.s.q", 0, INSN_CLASS_Q_INX
, "D,S", MATCH_FCVT_S_Q
|MASK_RM
, MASK_FCVT_S_Q
|MASK_RM
, match_opcode
, 0 },
908 {"fcvt.s.q", 0, INSN_CLASS_Q_INX
, "D,S,m", MATCH_FCVT_S_Q
, MASK_FCVT_S_Q
, match_opcode
, 0 },
909 {"fcvt.d.q", 0, INSN_CLASS_Q_INX
, "D,S", MATCH_FCVT_D_Q
|MASK_RM
, MASK_FCVT_D_Q
|MASK_RM
, match_opcode
, 0 },
910 {"fcvt.d.q", 0, INSN_CLASS_Q_INX
, "D,S,m", MATCH_FCVT_D_Q
, MASK_FCVT_D_Q
, match_opcode
, 0 },
911 {"fclass.q", 0, INSN_CLASS_Q_INX
, "d,S", MATCH_FCLASS_Q
, MASK_FCLASS_Q
, match_opcode
, 0 },
912 {"feq.q", 0, INSN_CLASS_Q_INX
, "d,S,T", MATCH_FEQ_Q
, MASK_FEQ_Q
, match_opcode
, 0 },
913 {"flt.q", 0, INSN_CLASS_Q_INX
, "d,S,T", MATCH_FLT_Q
, MASK_FLT_Q
, match_opcode
, 0 },
914 {"fle.q", 0, INSN_CLASS_Q_INX
, "d,S,T", MATCH_FLE_Q
, MASK_FLE_Q
, match_opcode
, 0 },
915 {"fgt.q", 0, INSN_CLASS_Q_INX
, "d,T,S", MATCH_FLT_Q
, MASK_FLT_Q
, match_opcode
, 0 },
916 {"fge.q", 0, INSN_CLASS_Q_INX
, "d,T,S", MATCH_FLE_Q
, MASK_FLE_Q
, match_opcode
, 0 },
917 {"fcvt.l.q", 64, INSN_CLASS_Q_INX
, "d,S", MATCH_FCVT_L_Q
|MASK_RM
, MASK_FCVT_L_Q
|MASK_RM
, match_opcode
, 0 },
918 {"fcvt.l.q", 64, INSN_CLASS_Q_INX
, "d,S,m", MATCH_FCVT_L_Q
, MASK_FCVT_L_Q
, match_opcode
, 0 },
919 {"fcvt.lu.q", 64, INSN_CLASS_Q_INX
, "d,S", MATCH_FCVT_LU_Q
|MASK_RM
, MASK_FCVT_LU_Q
|MASK_RM
, match_opcode
, 0 },
920 {"fcvt.lu.q", 64, INSN_CLASS_Q_INX
, "d,S,m", MATCH_FCVT_LU_Q
, MASK_FCVT_LU_Q
, match_opcode
, 0 },
921 {"fcvt.q.l", 64, INSN_CLASS_Q_INX
, "D,s", MATCH_FCVT_Q_L
, MASK_FCVT_Q_L
|MASK_RM
, match_opcode
, 0 },
922 {"fcvt.q.l", 64, INSN_CLASS_Q_INX
, "D,s,m", MATCH_FCVT_Q_L
, MASK_FCVT_Q_L
, match_opcode
, 0 },
923 {"fcvt.q.lu", 64, INSN_CLASS_Q_INX
, "D,s", MATCH_FCVT_Q_LU
, MASK_FCVT_Q_LU
|MASK_RM
, match_opcode
, 0 },
924 {"fcvt.q.lu", 64, INSN_CLASS_Q_INX
, "D,s,m", MATCH_FCVT_Q_LU
, MASK_FCVT_Q_LU
, match_opcode
, 0 },
926 /* Compressed instructions. */
927 {"c.unimp", 0, INSN_CLASS_C
, "", 0, 0xffffU
, match_opcode
, 0 },
928 {"c.ebreak", 0, INSN_CLASS_C
, "", MATCH_C_EBREAK
, MASK_C_EBREAK
, match_opcode
, 0 },
929 {"c.jr", 0, INSN_CLASS_C
, "d", MATCH_C_JR
, MASK_C_JR
, match_rd_nonzero
, INSN_BRANCH
},
930 {"c.jalr", 0, INSN_CLASS_C
, "d", MATCH_C_JALR
, MASK_C_JALR
, match_rd_nonzero
, INSN_JSR
},
931 {"c.j", 0, INSN_CLASS_C
, "Ca", MATCH_C_J
, MASK_C_J
, match_opcode
, INSN_BRANCH
},
932 {"c.jal", 32, INSN_CLASS_C
, "Ca", MATCH_C_JAL
, MASK_C_JAL
, match_opcode
, INSN_JSR
},
933 {"c.beqz", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BEQZ
, MASK_C_BEQZ
, match_opcode
, INSN_CONDBRANCH
},
934 {"c.bnez", 0, INSN_CLASS_C
, "Cs,Cp", MATCH_C_BNEZ
, MASK_C_BNEZ
, match_opcode
, INSN_CONDBRANCH
},
935 {"c.lwsp", 0, INSN_CLASS_C
, "d,Cm(Cc)", MATCH_C_LWSP
, MASK_C_LWSP
, match_rd_nonzero
, 0 },
936 {"c.lw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_LW
, MASK_C_LW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
937 {"c.swsp", 0, INSN_CLASS_C
, "CV,CM(Cc)", MATCH_C_SWSP
, MASK_C_SWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
938 {"c.sw", 0, INSN_CLASS_C
, "Ct,Ck(Cs)", MATCH_C_SW
, MASK_C_SW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
939 {"c.nop", 0, INSN_CLASS_C
, "", MATCH_C_ADDI
, 0xffff, match_opcode
, INSN_ALIAS
},
940 {"c.nop", 0, INSN_CLASS_C
, "Cj", MATCH_C_ADDI
, MASK_C_ADDI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
941 {"c.mv", 0, INSN_CLASS_C
, "d,CV", MATCH_C_MV
, MASK_C_MV
, match_c_add_with_hint
, 0 },
942 {"c.lui", 0, INSN_CLASS_C
, "d,Cu", MATCH_C_LUI
, MASK_C_LUI
, match_c_lui_with_hint
, 0 },
943 {"c.li", 0, INSN_CLASS_C
, "d,Co", MATCH_C_LI
, MASK_C_LI
, match_opcode
, 0 },
944 {"c.addi4spn", 0, INSN_CLASS_C
, "Ct,Cc,CK", MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
, match_c_addi4spn
, 0 },
945 {"c.addi16sp", 0, INSN_CLASS_C
, "Cc,CL", MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
, match_c_addi16sp
, 0 },
946 {"c.addi", 0, INSN_CLASS_C
, "d,Co", MATCH_C_ADDI
, MASK_C_ADDI
, match_opcode
, 0 },
947 {"c.add", 0, INSN_CLASS_C
, "d,CV", MATCH_C_ADD
, MASK_C_ADD
, match_c_add_with_hint
, 0 },
948 {"c.sub", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_SUB
, MASK_C_SUB
, match_opcode
, 0 },
949 {"c.and", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_AND
, MASK_C_AND
, match_opcode
, 0 },
950 {"c.or", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_OR
, MASK_C_OR
, match_opcode
, 0 },
951 {"c.xor", 0, INSN_CLASS_C
, "Cs,Ct", MATCH_C_XOR
, MASK_C_XOR
, match_opcode
, 0 },
952 {"c.slli", 0, INSN_CLASS_C
, "d,C>", MATCH_C_SLLI
, MASK_C_SLLI
, match_c_slli
, 0 },
953 {"c.srli", 0, INSN_CLASS_C
, "Cs,C>", MATCH_C_SRLI
, MASK_C_SRLI
, match_c_slli
, 0 },
954 {"c.srai", 0, INSN_CLASS_C
, "Cs,C>", MATCH_C_SRAI
, MASK_C_SRAI
, match_c_slli
, 0 },
955 {"c.slli64", 0, INSN_CLASS_C
, "d", MATCH_C_SLLI64
, MASK_C_SLLI64
, match_c_slli64
, 0 },
956 {"c.srli64", 0, INSN_CLASS_C
, "Cs", MATCH_C_SRLI64
, MASK_C_SRLI64
, match_c_slli64
, 0 },
957 {"c.srai64", 0, INSN_CLASS_C
, "Cs", MATCH_C_SRAI64
, MASK_C_SRAI64
, match_c_slli64
, 0 },
958 {"c.andi", 0, INSN_CLASS_C
, "Cs,Co", MATCH_C_ANDI
, MASK_C_ANDI
, match_opcode
, 0 },
959 {"c.addiw", 64, INSN_CLASS_C
, "d,Co", MATCH_C_ADDIW
, MASK_C_ADDIW
, match_rd_nonzero
, 0 },
960 {"c.addw", 64, INSN_CLASS_C
, "Cs,Ct", MATCH_C_ADDW
, MASK_C_ADDW
, match_opcode
, 0 },
961 {"c.subw", 64, INSN_CLASS_C
, "Cs,Ct", MATCH_C_SUBW
, MASK_C_SUBW
, match_opcode
, 0 },
962 {"c.ldsp", 64, INSN_CLASS_C
, "d,Cn(Cc)", MATCH_C_LDSP
, MASK_C_LDSP
, match_rd_nonzero
, INSN_DREF
|INSN_8_BYTE
},
963 {"c.ld", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_LD
, MASK_C_LD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
964 {"c.sdsp", 64, INSN_CLASS_C
, "CV,CN(Cc)", MATCH_C_SDSP
, MASK_C_SDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
965 {"c.sd", 64, INSN_CLASS_C
, "Ct,Cl(Cs)", MATCH_C_SD
, MASK_C_SD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
966 {"c.fldsp", 0, INSN_CLASS_D_AND_C
, "D,Cn(Cc)", MATCH_C_FLDSP
, MASK_C_FLDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
967 {"c.fld", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FLD
, MASK_C_FLD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
968 {"c.fsdsp", 0, INSN_CLASS_D_AND_C
, "CT,CN(Cc)", MATCH_C_FSDSP
, MASK_C_FSDSP
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
969 {"c.fsd", 0, INSN_CLASS_D_AND_C
, "CD,Cl(Cs)", MATCH_C_FSD
, MASK_C_FSD
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
970 {"c.flwsp", 32, INSN_CLASS_F_AND_C
, "D,Cm(Cc)", MATCH_C_FLWSP
, MASK_C_FLWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
971 {"c.flw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FLW
, MASK_C_FLW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
972 {"c.fswsp", 32, INSN_CLASS_F_AND_C
, "CT,CM(Cc)", MATCH_C_FSWSP
, MASK_C_FSWSP
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
973 {"c.fsw", 32, INSN_CLASS_F_AND_C
, "CD,Ck(Cs)", MATCH_C_FSW
, MASK_C_FSW
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
975 /* Zicbom and Zicboz instructions. */
976 {"cbo.clean", 0, INSN_CLASS_ZICBOM
, "0(s)", MATCH_CBO_CLEAN
, MASK_CBO_CLEAN
, match_opcode
, 0 },
977 {"cbo.flush", 0, INSN_CLASS_ZICBOM
, "0(s)", MATCH_CBO_FLUSH
, MASK_CBO_FLUSH
, match_opcode
, 0 },
978 {"cbo.inval", 0, INSN_CLASS_ZICBOM
, "0(s)", MATCH_CBO_INVAL
, MASK_CBO_INVAL
, match_opcode
, 0 },
979 {"cbo.zero", 0, INSN_CLASS_ZICBOZ
, "0(s)", MATCH_CBO_ZERO
, MASK_CBO_ZERO
, match_opcode
, 0 },
981 /* Zicond instructions. */
982 {"czero.eqz", 0, INSN_CLASS_ZICOND
, "d,s,t", MATCH_CZERO_EQZ
, MASK_CZERO_EQZ
, match_opcode
, 0 },
983 {"czero.nez", 0, INSN_CLASS_ZICOND
, "d,s,t", MATCH_CZERO_NEZ
, MASK_CZERO_NEZ
, match_opcode
, 0 },
985 /* Zawrs instructions. */
986 {"wrs.nto", 0, INSN_CLASS_ZAWRS
, "", MATCH_WRS_NTO
, MASK_WRS_NTO
, match_opcode
, 0 },
987 {"wrs.sto", 0, INSN_CLASS_ZAWRS
, "", MATCH_WRS_STO
, MASK_WRS_STO
, match_opcode
, 0 },
989 /* Zfa instructions. */
990 {"fli.s", 0, INSN_CLASS_ZFA
, "D,Wfv", MATCH_FLI_S
, MASK_FLI_S
, match_opcode
, 0 },
991 {"fli.d", 0, INSN_CLASS_D_AND_ZFA
, "D,Wfv", MATCH_FLI_D
, MASK_FLI_D
, match_opcode
, 0 },
992 {"fli.q", 0, INSN_CLASS_Q_AND_ZFA
, "D,Wfv", MATCH_FLI_Q
, MASK_FLI_Q
, match_opcode
, 0 },
993 {"fli.h", 0, INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA
, "D,Wfv", MATCH_FLI_H
, MASK_FLI_H
, match_opcode
, 0 },
994 {"fminm.s", 0, INSN_CLASS_ZFA
, "D,S,T", MATCH_FMINM_S
, MASK_FMINM_S
, match_opcode
, 0 },
995 {"fmaxm.s", 0, INSN_CLASS_ZFA
, "D,S,T", MATCH_FMAXM_S
, MASK_FMAXM_S
, match_opcode
, 0 },
996 {"fminm.d", 0, INSN_CLASS_D_AND_ZFA
, "D,S,T", MATCH_FMINM_D
, MASK_FMINM_D
, match_opcode
, 0 },
997 {"fmaxm.d", 0, INSN_CLASS_D_AND_ZFA
, "D,S,T", MATCH_FMAXM_D
, MASK_FMAXM_D
, match_opcode
, 0 },
998 {"fminm.q", 0, INSN_CLASS_Q_AND_ZFA
, "D,S,T", MATCH_FMINM_Q
, MASK_FMINM_Q
, match_opcode
, 0 },
999 {"fmaxm.q", 0, INSN_CLASS_Q_AND_ZFA
, "D,S,T", MATCH_FMAXM_Q
, MASK_FMAXM_Q
, match_opcode
, 0 },
1000 {"fminm.h", 0, INSN_CLASS_ZFH_AND_ZFA
, "D,S,T", MATCH_FMINM_H
, MASK_FMINM_H
, match_opcode
, 0 },
1001 {"fmaxm.h", 0, INSN_CLASS_ZFH_AND_ZFA
, "D,S,T", MATCH_FMAXM_H
, MASK_FMAXM_H
, match_opcode
, 0 },
1002 {"fround.s", 0, INSN_CLASS_ZFA
, "D,S", MATCH_FROUND_S
|MASK_RM
, MASK_FROUND_S
|MASK_RM
, match_opcode
, 0 },
1003 {"fround.s", 0, INSN_CLASS_ZFA
, "D,S,m", MATCH_FROUND_S
, MASK_FROUND_S
, match_opcode
, 0 },
1004 {"froundnx.s", 0, INSN_CLASS_ZFA
, "D,S", MATCH_FROUNDNX_S
|MASK_RM
, MASK_FROUNDNX_S
|MASK_RM
, match_opcode
, 0 },
1005 {"froundnx.s", 0, INSN_CLASS_ZFA
, "D,S,m", MATCH_FROUNDNX_S
, MASK_FROUNDNX_S
, match_opcode
, 0 },
1006 {"fround.d", 0, INSN_CLASS_D_AND_ZFA
, "D,S", MATCH_FROUND_D
|MASK_RM
, MASK_FROUND_D
|MASK_RM
, match_opcode
, 0 },
1007 {"fround.d", 0, INSN_CLASS_D_AND_ZFA
, "D,S,m", MATCH_FROUND_D
, MASK_FROUND_D
, match_opcode
, 0 },
1008 {"froundnx.d", 0, INSN_CLASS_D_AND_ZFA
, "D,S", MATCH_FROUNDNX_D
|MASK_RM
, MASK_FROUNDNX_D
|MASK_RM
, match_opcode
, 0 },
1009 {"froundnx.d", 0, INSN_CLASS_D_AND_ZFA
, "D,S,m", MATCH_FROUNDNX_D
, MASK_FROUNDNX_D
, match_opcode
, 0 },
1010 {"fround.q", 0, INSN_CLASS_Q_AND_ZFA
, "D,S", MATCH_FROUND_Q
|MASK_RM
, MASK_FROUND_Q
|MASK_RM
, match_opcode
, 0 },
1011 {"fround.q", 0, INSN_CLASS_Q_AND_ZFA
, "D,S,m", MATCH_FROUND_Q
, MASK_FROUND_Q
, match_opcode
, 0 },
1012 {"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA
, "D,S", MATCH_FROUNDNX_Q
|MASK_RM
, MASK_FROUNDNX_Q
|MASK_RM
, match_opcode
, 0 },
1013 {"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA
, "D,S,m", MATCH_FROUNDNX_Q
, MASK_FROUNDNX_Q
, match_opcode
, 0 },
1014 {"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA
, "D,S", MATCH_FROUND_H
|MASK_RM
, MASK_FROUND_H
|MASK_RM
, match_opcode
, 0 },
1015 {"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA
, "D,S,m", MATCH_FROUND_H
, MASK_FROUND_H
, match_opcode
, 0 },
1016 {"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA
, "D,S", MATCH_FROUNDNX_H
|MASK_RM
, MASK_FROUNDNX_H
|MASK_RM
, match_opcode
, 0 },
1017 {"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA
, "D,S,m", MATCH_FROUNDNX_H
, MASK_FROUNDNX_H
, match_opcode
, 0 },
1018 {"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA
, "d,S,m", MATCH_FCVTMOD_W_D
, MASK_FCVTMOD_W_D
, match_opcode
, 0 },
1019 {"fmvh.x.d", 32, INSN_CLASS_D_AND_ZFA
, "d,S", MATCH_FMVH_X_D
, MASK_FMVH_X_D
, match_opcode
, 0 },
1020 {"fmvp.d.x", 32, INSN_CLASS_D_AND_ZFA
, "D,s,t", MATCH_FMVP_D_X
, MASK_FMVP_D_X
, match_opcode
, 0 },
1021 {"fmvh.x.q", 64, INSN_CLASS_Q_AND_ZFA
, "d,S", MATCH_FMVH_X_Q
, MASK_FMVH_X_Q
, match_opcode
, 0 },
1022 {"fmvp.q.x", 64, INSN_CLASS_Q_AND_ZFA
, "D,s,t", MATCH_FMVP_Q_X
, MASK_FMVP_Q_X
, match_opcode
, 0 },
1023 {"fltq.s", 0, INSN_CLASS_ZFA
, "d,S,T", MATCH_FLTQ_S
, MASK_FLTQ_S
, match_opcode
, 0 },
1024 {"fleq.s", 0, INSN_CLASS_ZFA
, "d,S,T", MATCH_FLEQ_S
, MASK_FLEQ_S
, match_opcode
, 0 },
1025 {"fltq.d", 0, INSN_CLASS_D_AND_ZFA
, "d,S,T", MATCH_FLTQ_D
, MASK_FLTQ_D
, match_opcode
, 0 },
1026 {"fleq.d", 0, INSN_CLASS_D_AND_ZFA
, "d,S,T", MATCH_FLEQ_D
, MASK_FLEQ_D
, match_opcode
, 0 },
1027 {"fltq.q", 0, INSN_CLASS_Q_AND_ZFA
, "d,S,T", MATCH_FLTQ_Q
, MASK_FLTQ_Q
, match_opcode
, 0 },
1028 {"fleq.q", 0, INSN_CLASS_Q_AND_ZFA
, "d,S,T", MATCH_FLEQ_Q
, MASK_FLEQ_Q
, match_opcode
, 0 },
1029 {"fltq.h", 0, INSN_CLASS_ZFH_AND_ZFA
, "d,S,T", MATCH_FLTQ_H
, MASK_FLTQ_H
, match_opcode
, 0 },
1030 {"fleq.h", 0, INSN_CLASS_ZFH_AND_ZFA
, "d,S,T", MATCH_FLEQ_H
, MASK_FLEQ_H
, match_opcode
, 0 },
1032 /* Zbb or zbkb instructions. */
1033 {"clz", 0, INSN_CLASS_ZBB
, "d,s", MATCH_CLZ
, MASK_CLZ
, match_opcode
, 0 },
1034 {"ctz", 0, INSN_CLASS_ZBB
, "d,s", MATCH_CTZ
, MASK_CTZ
, match_opcode
, 0 },
1035 {"cpop", 0, INSN_CLASS_ZBB
, "d,s", MATCH_CPOP
, MASK_CPOP
, match_opcode
, 0 },
1036 {"min", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_MIN
, MASK_MIN
, match_opcode
, 0 },
1037 {"max", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_MAX
, MASK_MAX
, match_opcode
, 0 },
1038 {"minu", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_MINU
, MASK_MINU
, match_opcode
, 0 },
1039 {"maxu", 0, INSN_CLASS_ZBB
, "d,s,t", MATCH_MAXU
, MASK_MAXU
, match_opcode
, 0 },
1040 {"sext.b", 0, INSN_CLASS_ZCB_AND_ZBB
, "Cs,Cw", MATCH_C_SEXT_B
, MASK_C_SEXT_B
, match_opcode
, INSN_ALIAS
},
1041 {"sext.b", 0, INSN_CLASS_ZBB
, "d,s", MATCH_SEXT_B
, MASK_SEXT_B
, match_opcode
, 0 },
1042 {"sext.b", 0, INSN_CLASS_I
, "d,s", 0, (int) M_SEXTB
, match_never
, INSN_MACRO
},
1043 {"sext.h", 0, INSN_CLASS_ZCB_AND_ZBB
, "Cs,Cw", MATCH_C_SEXT_H
, MASK_C_SEXT_H
, match_opcode
, INSN_ALIAS
},
1044 {"sext.h", 0, INSN_CLASS_ZBB
, "d,s", MATCH_SEXT_H
, MASK_SEXT_H
, match_opcode
, 0 },
1045 {"sext.h", 0, INSN_CLASS_I
, "d,s", 0, (int) M_SEXTH
, match_never
, INSN_MACRO
},
1046 {"zext.h", 0, INSN_CLASS_ZCB_AND_ZBB
, "Cs,Cw", MATCH_C_ZEXT_H
, MASK_C_ZEXT_H
, match_opcode
, INSN_ALIAS
},
1047 {"zext.h", 32, INSN_CLASS_ZBB
, "d,s", MATCH_PACK
, MASK_PACK
| MASK_RS2
, match_opcode
, 0 },
1048 {"zext.h", 64, INSN_CLASS_ZBB
, "d,s", MATCH_PACKW
, MASK_PACKW
| MASK_RS2
, match_opcode
, 0 },
1049 {"zext.h", 0, INSN_CLASS_I
, "d,s", 0, (int) M_ZEXTH
, match_never
, INSN_MACRO
},
1050 {"orc.b", 0, INSN_CLASS_ZBB
, "d,s", MATCH_GORCI
| MATCH_SHAMT_ORC_B
, MASK_GORCI
| MASK_SHAMT
, match_opcode
, 0 },
1051 {"clzw", 64, INSN_CLASS_ZBB
, "d,s", MATCH_CLZW
, MASK_CLZW
, match_opcode
, 0 },
1052 {"ctzw", 64, INSN_CLASS_ZBB
, "d,s", MATCH_CTZW
, MASK_CTZW
, match_opcode
, 0 },
1053 {"cpopw", 64, INSN_CLASS_ZBB
, "d,s", MATCH_CPOPW
, MASK_CPOPW
, match_opcode
, 0 },
1054 {"brev8", 32, INSN_CLASS_ZBKB
, "d,s", MATCH_GREVI
| MATCH_SHAMT_BREV8
, MASK_GREVI
| MASK_SHAMT
, match_opcode
, 0 },
1055 {"brev8", 64, INSN_CLASS_ZBKB
, "d,s", MATCH_GREVI
| MATCH_SHAMT_BREV8
, MASK_GREVI
| MASK_SHAMT
, match_opcode
, 0 },
1056 {"zip", 32, INSN_CLASS_ZBKB
, "d,s", MATCH_SHFLI
|MATCH_SHAMT_ZIP_32
, MASK_SHFLI
|MASK_SHAMT
, match_opcode
, 0 },
1057 {"unzip", 32, INSN_CLASS_ZBKB
, "d,s", MATCH_UNSHFLI
|MATCH_SHAMT_ZIP_32
, MASK_UNSHFLI
|MASK_SHAMT
, match_opcode
, 0 },
1058 {"pack", 0, INSN_CLASS_ZBKB
, "d,s,t", MATCH_PACK
, MASK_PACK
, match_opcode
, 0 },
1059 {"packh", 0, INSN_CLASS_ZBKB
, "d,s,t", MATCH_PACKH
, MASK_PACKH
, match_opcode
, 0 },
1060 {"packw", 64, INSN_CLASS_ZBKB
, "d,s,t", MATCH_PACKW
, MASK_PACKW
, match_opcode
, 0 },
1061 {"andn", 0, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,t", MATCH_ANDN
, MASK_ANDN
, match_opcode
, 0 },
1062 {"orn", 0, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,t", MATCH_ORN
, MASK_ORN
, match_opcode
, 0 },
1063 {"xnor", 0, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,t", MATCH_XNOR
, MASK_XNOR
, match_opcode
, 0 },
1064 {"rol", 0, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,t", MATCH_ROL
, MASK_ROL
, match_opcode
, 0 },
1065 {"rori", 0, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,>", MATCH_RORI
, MASK_RORI
, match_opcode
, 0 },
1066 {"ror", 0, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,t", MATCH_ROR
, MASK_ROR
, match_opcode
, 0 },
1067 {"ror", 0, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,>", MATCH_RORI
, MASK_RORI
, match_opcode
, INSN_ALIAS
},
1068 {"rev8", 32, INSN_CLASS_ZBB_OR_ZBKB
, "d,s", MATCH_GREVI
| MATCH_SHAMT_REV8_32
, MASK_GREVI
| MASK_SHAMT
, match_opcode
, 0 },
1069 {"rev8", 64, INSN_CLASS_ZBB_OR_ZBKB
, "d,s", MATCH_GREVI
| MATCH_SHAMT_REV8_64
, MASK_GREVI
| MASK_SHAMT
, match_opcode
, 0 },
1070 {"rolw", 64, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,t", MATCH_ROLW
, MASK_ROLW
, match_opcode
, 0 },
1071 {"roriw", 64, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,<", MATCH_RORIW
, MASK_RORIW
, match_opcode
, 0 },
1072 {"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,t", MATCH_RORW
, MASK_RORW
, match_opcode
, 0 },
1073 {"rorw", 64, INSN_CLASS_ZBB_OR_ZBKB
, "d,s,<", MATCH_RORIW
, MASK_RORIW
, match_opcode
, INSN_ALIAS
},
1075 /* Zba instructions. */
1076 {"sh1add", 0, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH1ADD
, MASK_SH1ADD
, match_opcode
, 0 },
1077 {"sh2add", 0, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH2ADD
, MASK_SH2ADD
, match_opcode
, 0 },
1078 {"sh3add", 0, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH3ADD
, MASK_SH3ADD
, match_opcode
, 0 },
1079 {"sh1add.uw", 64, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH1ADD_UW
, MASK_SH1ADD_UW
, match_opcode
, 0 },
1080 {"sh2add.uw", 64, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH2ADD_UW
, MASK_SH2ADD_UW
, match_opcode
, 0 },
1081 {"sh3add.uw", 64, INSN_CLASS_ZBA
, "d,s,t", MATCH_SH3ADD_UW
, MASK_SH3ADD_UW
, match_opcode
, 0 },
1082 {"zext.w", 64, INSN_CLASS_ZCB_AND_ZBA
, "Cs,Cw", MATCH_C_ZEXT_W
, MASK_C_ZEXT_W
, match_opcode
, INSN_ALIAS
},
1083 {"zext.w", 64, INSN_CLASS_ZBA
, "d,s", MATCH_ADD_UW
, MASK_ADD_UW
| MASK_RS2
, match_opcode
, INSN_ALIAS
},
1084 {"zext.w", 64, INSN_CLASS_I
, "d,s", 0, (int) M_ZEXTW
, match_never
, INSN_MACRO
},
1085 {"add.uw", 64, INSN_CLASS_ZBA
, "d,s,t", MATCH_ADD_UW
, MASK_ADD_UW
, match_opcode
, 0 },
1086 {"slli.uw", 64, INSN_CLASS_ZBA
, "d,s,>", MATCH_SLLI_UW
, MASK_SLLI_UW
, match_opcode
, 0 },
1088 /* Zbc or zbkc instructions. */
1089 {"clmul", 0, INSN_CLASS_ZBC_OR_ZBKC
, "d,s,t", MATCH_CLMUL
, MASK_CLMUL
, match_opcode
, 0 },
1090 {"clmulh", 0, INSN_CLASS_ZBC_OR_ZBKC
, "d,s,t", MATCH_CLMULH
, MASK_CLMULH
, match_opcode
, 0 },
1091 {"clmulr", 0, INSN_CLASS_ZBC
, "d,s,t", MATCH_CLMULR
, MASK_CLMULR
, match_opcode
, 0 },
1093 /* Zbs instructions. */
1094 {"bclri", 0, INSN_CLASS_ZBS
, "d,s,>", MATCH_BCLRI
, MASK_BCLRI
, match_opcode
, 0 },
1095 {"bclr", 0, INSN_CLASS_ZBS
, "d,s,t", MATCH_BCLR
, MASK_BCLR
, match_opcode
, 0 },
1096 {"bclr", 0, INSN_CLASS_ZBS
, "d,s,>", MATCH_BCLRI
, MASK_BCLRI
, match_opcode
, INSN_ALIAS
},
1097 {"bseti", 0, INSN_CLASS_ZBS
, "d,s,>", MATCH_BSETI
, MASK_BSETI
, match_opcode
, 0 },
1098 {"bset", 0, INSN_CLASS_ZBS
, "d,s,t", MATCH_BSET
, MASK_BSET
, match_opcode
, 0 },
1099 {"bset", 0, INSN_CLASS_ZBS
, "d,s,>", MATCH_BSETI
, MASK_BSETI
, match_opcode
, INSN_ALIAS
},
1100 {"binvi", 0, INSN_CLASS_ZBS
, "d,s,>", MATCH_BINVI
, MASK_BINVI
, match_opcode
, 0 },
1101 {"binv", 0, INSN_CLASS_ZBS
, "d,s,t", MATCH_BINV
, MASK_BINV
, match_opcode
, 0 },
1102 {"binv", 0, INSN_CLASS_ZBS
, "d,s,>", MATCH_BINVI
, MASK_BINVI
, match_opcode
, INSN_ALIAS
},
1103 {"bexti", 0, INSN_CLASS_ZBS
, "d,s,>", MATCH_BEXTI
, MASK_BEXTI
, match_opcode
, 0 },
1104 {"bext", 0, INSN_CLASS_ZBS
, "d,s,t", MATCH_BEXT
, MASK_BEXT
, match_opcode
, 0 },
1105 {"bext", 0, INSN_CLASS_ZBS
, "d,s,>", MATCH_BEXTI
, MASK_BEXTI
, match_opcode
, INSN_ALIAS
},
1107 /* Zbkx instructions. */
1108 {"xperm4", 0, INSN_CLASS_ZBKX
, "d,s,t", MATCH_XPERM4
, MASK_XPERM4
, match_opcode
, 0 },
1109 {"xperm8", 0, INSN_CLASS_ZBKX
, "d,s,t", MATCH_XPERM8
, MASK_XPERM8
, match_opcode
, 0 },
1111 /* Zknd instructions. */
1112 {"aes32dsi", 32, INSN_CLASS_ZKND
, "d,s,t,y", MATCH_AES32DSI
, MASK_AES32DSI
, match_opcode
, 0 },
1113 {"aes32dsmi", 32, INSN_CLASS_ZKND
, "d,s,t,y", MATCH_AES32DSMI
, MASK_AES32DSMI
, match_opcode
, 0 },
1114 {"aes64ds", 64, INSN_CLASS_ZKND
, "d,s,t", MATCH_AES64DS
, MASK_AES64DS
, match_opcode
, 0 },
1115 {"aes64dsm", 64, INSN_CLASS_ZKND
, "d,s,t", MATCH_AES64DSM
, MASK_AES64DSM
, match_opcode
, 0 },
1116 {"aes64im", 64, INSN_CLASS_ZKND
, "d,s", MATCH_AES64IM
, MASK_AES64IM
, match_opcode
, 0 },
1117 {"aes64ks1i", 64, INSN_CLASS_ZKND_OR_ZKNE
, "d,s,Y", MATCH_AES64KS1I
, MASK_AES64KS1I
, match_opcode
, 0 },
1118 {"aes64ks2", 64, INSN_CLASS_ZKND_OR_ZKNE
, "d,s,t", MATCH_AES64KS2
, MASK_AES64KS2
, match_opcode
, 0 },
1120 /* Zkne instructions. */
1121 {"aes32esi", 32, INSN_CLASS_ZKNE
, "d,s,t,y", MATCH_AES32ESI
, MASK_AES32ESI
, match_opcode
, 0 },
1122 {"aes32esmi", 32, INSN_CLASS_ZKNE
, "d,s,t,y", MATCH_AES32ESMI
, MASK_AES32ESMI
, match_opcode
, 0 },
1123 {"aes64es", 64, INSN_CLASS_ZKNE
, "d,s,t", MATCH_AES64ES
, MASK_AES64ES
, match_opcode
, 0 },
1124 {"aes64esm", 64, INSN_CLASS_ZKNE
, "d,s,t", MATCH_AES64ESM
, MASK_AES64ESM
, match_opcode
, 0 },
1126 /* Zknh instructions. */
1127 {"sha256sig0", 0, INSN_CLASS_ZKNH
, "d,s", MATCH_SHA256SIG0
, MASK_SHA256SIG0
, match_opcode
, 0 },
1128 {"sha256sig1", 0, INSN_CLASS_ZKNH
, "d,s", MATCH_SHA256SIG1
, MASK_SHA256SIG1
, match_opcode
, 0 },
1129 {"sha256sum0", 0, INSN_CLASS_ZKNH
, "d,s", MATCH_SHA256SUM0
, MASK_SHA256SUM0
, match_opcode
, 0 },
1130 {"sha256sum1", 0, INSN_CLASS_ZKNH
, "d,s", MATCH_SHA256SUM1
, MASK_SHA256SUM1
, match_opcode
, 0 },
1131 {"sha512sig0h", 32, INSN_CLASS_ZKNH
, "d,s,t", MATCH_SHA512SIG0H
, MASK_SHA512SIG0H
, match_opcode
, 0 },
1132 {"sha512sig0l", 32, INSN_CLASS_ZKNH
, "d,s,t", MATCH_SHA512SIG0L
, MASK_SHA512SIG0L
, match_opcode
, 0 },
1133 {"sha512sig1h", 32, INSN_CLASS_ZKNH
, "d,s,t", MATCH_SHA512SIG1H
, MASK_SHA512SIG1H
, match_opcode
, 0 },
1134 {"sha512sig1l", 32, INSN_CLASS_ZKNH
, "d,s,t", MATCH_SHA512SIG1L
, MASK_SHA512SIG1L
, match_opcode
, 0 },
1135 {"sha512sum0r", 32, INSN_CLASS_ZKNH
, "d,s,t", MATCH_SHA512SUM0R
, MASK_SHA512SUM0R
, match_opcode
, 0 },
1136 {"sha512sum1r", 32, INSN_CLASS_ZKNH
, "d,s,t", MATCH_SHA512SUM1R
, MASK_SHA512SUM1R
, match_opcode
, 0 },
1137 {"sha512sig0", 64, INSN_CLASS_ZKNH
, "d,s", MATCH_SHA512SIG0
, MASK_SHA512SIG0
, match_opcode
, 0 },
1138 {"sha512sig1", 64, INSN_CLASS_ZKNH
, "d,s", MATCH_SHA512SIG1
, MASK_SHA512SIG1
, match_opcode
, 0 },
1139 {"sha512sum0", 64, INSN_CLASS_ZKNH
, "d,s", MATCH_SHA512SUM0
, MASK_SHA512SUM0
, match_opcode
, 0 },
1140 {"sha512sum1", 64, INSN_CLASS_ZKNH
, "d,s", MATCH_SHA512SUM1
, MASK_SHA512SUM1
, match_opcode
, 0 },
1142 /* Zksed instructions. */
1143 {"sm4ed", 0, INSN_CLASS_ZKSED
, "d,s,t,y", MATCH_SM4ED
, MASK_SM4ED
, match_opcode
, 0 },
1144 {"sm4ks", 0, INSN_CLASS_ZKSED
, "d,s,t,y", MATCH_SM4KS
, MASK_SM4KS
, match_opcode
, 0 },
1146 /* Zksh instructions */
1147 {"sm3p0", 0, INSN_CLASS_ZKSH
, "d,s", MATCH_SM3P0
, MASK_SM3P0
, match_opcode
, 0 },
1148 {"sm3p1", 0, INSN_CLASS_ZKSH
, "d,s", MATCH_SM3P1
, MASK_SM3P1
, match_opcode
, 0 },
1150 /* RVV instructions. */
1151 {"vsetvl", 0, INSN_CLASS_V
, "d,s,t", MATCH_VSETVL
, MASK_VSETVL
, match_opcode
, 0},
1152 {"vsetvli", 0, INSN_CLASS_V
, "d,s,Vc", MATCH_VSETVLI
, MASK_VSETVLI
, match_opcode
, 0},
1153 {"vsetivli", 0, INSN_CLASS_V
, "d,Z,Vb", MATCH_VSETIVLI
, MASK_VSETIVLI
, match_opcode
, 0},
1155 {"vlm.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VLMV
, MASK_VLMV
, match_opcode
, INSN_DREF
},
1156 {"vsm.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VSMV
, MASK_VSMV
, match_opcode
, INSN_DREF
},
1157 {"vle1.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VLMV
, MASK_VLMV
, match_opcode
, INSN_DREF
|INSN_ALIAS
},
1158 {"vse1.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VSMV
, MASK_VSMV
, match_opcode
, INSN_DREF
|INSN_ALIAS
},
1160 {"vle8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLE8V
, MASK_VLE8V
, match_opcode
, INSN_DREF
},
1161 {"vle16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLE16V
, MASK_VLE16V
, match_opcode
, INSN_DREF
},
1162 {"vle32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLE32V
, MASK_VLE32V
, match_opcode
, INSN_DREF
},
1163 {"vle64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLE64V
, MASK_VLE64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1165 {"vse8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSE8V
, MASK_VSE8V
, match_opcode
, INSN_DREF
},
1166 {"vse16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSE16V
, MASK_VSE16V
, match_opcode
, INSN_DREF
},
1167 {"vse32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSE32V
, MASK_VSE32V
, match_opcode
, INSN_DREF
},
1168 {"vse64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSE64V
, MASK_VSE64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1170 {"vlse8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSE8V
, MASK_VLSE8V
, match_opcode
, INSN_DREF
},
1171 {"vlse16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSE16V
, MASK_VLSE16V
, match_opcode
, INSN_DREF
},
1172 {"vlse32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSE32V
, MASK_VLSE32V
, match_opcode
, INSN_DREF
},
1173 {"vlse64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSE64V
, MASK_VLSE64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1175 {"vsse8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSE8V
, MASK_VSSE8V
, match_opcode
, INSN_DREF
},
1176 {"vsse16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSE16V
, MASK_VSSE16V
, match_opcode
, INSN_DREF
},
1177 {"vsse32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSE32V
, MASK_VSSE32V
, match_opcode
, INSN_DREF
},
1178 {"vsse64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSE64V
, MASK_VSSE64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1180 {"vloxei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXEI8V
, MASK_VLOXEI8V
, match_opcode
, INSN_DREF
},
1181 {"vloxei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXEI16V
, MASK_VLOXEI16V
, match_opcode
, INSN_DREF
},
1182 {"vloxei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXEI32V
, MASK_VLOXEI32V
, match_opcode
, INSN_DREF
},
1183 {"vloxei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXEI64V
, MASK_VLOXEI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1185 {"vsoxei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXEI8V
, MASK_VSOXEI8V
, match_opcode
, INSN_DREF
},
1186 {"vsoxei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXEI16V
, MASK_VSOXEI16V
, match_opcode
, INSN_DREF
},
1187 {"vsoxei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXEI32V
, MASK_VSOXEI32V
, match_opcode
, INSN_DREF
},
1188 {"vsoxei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXEI64V
, MASK_VSOXEI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1190 {"vluxei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXEI8V
, MASK_VLUXEI8V
, match_opcode
, INSN_DREF
},
1191 {"vluxei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXEI16V
, MASK_VLUXEI16V
, match_opcode
, INSN_DREF
},
1192 {"vluxei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXEI32V
, MASK_VLUXEI32V
, match_opcode
, INSN_DREF
},
1193 {"vluxei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXEI64V
, MASK_VLUXEI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1195 {"vsuxei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXEI8V
, MASK_VSUXEI8V
, match_opcode
, INSN_DREF
},
1196 {"vsuxei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXEI16V
, MASK_VSUXEI16V
, match_opcode
, INSN_DREF
},
1197 {"vsuxei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXEI32V
, MASK_VSUXEI32V
, match_opcode
, INSN_DREF
},
1198 {"vsuxei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXEI64V
, MASK_VSUXEI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1200 {"vle8ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLE8FFV
, MASK_VLE8FFV
, match_opcode
, INSN_DREF
},
1201 {"vle16ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLE16FFV
, MASK_VLE16FFV
, match_opcode
, INSN_DREF
},
1202 {"vle32ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLE32FFV
, MASK_VLE32FFV
, match_opcode
, INSN_DREF
},
1203 {"vle64ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLE64FFV
, MASK_VLE64FFV
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1205 {"vlseg2e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG2E8V
, MASK_VLSEG2E8V
, match_opcode
, INSN_DREF
},
1206 {"vsseg2e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG2E8V
, MASK_VSSEG2E8V
, match_opcode
, INSN_DREF
},
1207 {"vlseg3e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG3E8V
, MASK_VLSEG3E8V
, match_opcode
, INSN_DREF
},
1208 {"vsseg3e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG3E8V
, MASK_VSSEG3E8V
, match_opcode
, INSN_DREF
},
1209 {"vlseg4e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG4E8V
, MASK_VLSEG4E8V
, match_opcode
, INSN_DREF
},
1210 {"vsseg4e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG4E8V
, MASK_VSSEG4E8V
, match_opcode
, INSN_DREF
},
1211 {"vlseg5e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG5E8V
, MASK_VLSEG5E8V
, match_opcode
, INSN_DREF
},
1212 {"vsseg5e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG5E8V
, MASK_VSSEG5E8V
, match_opcode
, INSN_DREF
},
1213 {"vlseg6e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG6E8V
, MASK_VLSEG6E8V
, match_opcode
, INSN_DREF
},
1214 {"vsseg6e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG6E8V
, MASK_VSSEG6E8V
, match_opcode
, INSN_DREF
},
1215 {"vlseg7e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG7E8V
, MASK_VLSEG7E8V
, match_opcode
, INSN_DREF
},
1216 {"vsseg7e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG7E8V
, MASK_VSSEG7E8V
, match_opcode
, INSN_DREF
},
1217 {"vlseg8e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG8E8V
, MASK_VLSEG8E8V
, match_opcode
, INSN_DREF
},
1218 {"vsseg8e8.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG8E8V
, MASK_VSSEG8E8V
, match_opcode
, INSN_DREF
},
1220 {"vlseg2e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG2E16V
, MASK_VLSEG2E16V
, match_opcode
, INSN_DREF
},
1221 {"vsseg2e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG2E16V
, MASK_VSSEG2E16V
, match_opcode
, INSN_DREF
},
1222 {"vlseg3e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG3E16V
, MASK_VLSEG3E16V
, match_opcode
, INSN_DREF
},
1223 {"vsseg3e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG3E16V
, MASK_VSSEG3E16V
, match_opcode
, INSN_DREF
},
1224 {"vlseg4e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG4E16V
, MASK_VLSEG4E16V
, match_opcode
, INSN_DREF
},
1225 {"vsseg4e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG4E16V
, MASK_VSSEG4E16V
, match_opcode
, INSN_DREF
},
1226 {"vlseg5e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG5E16V
, MASK_VLSEG5E16V
, match_opcode
, INSN_DREF
},
1227 {"vsseg5e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG5E16V
, MASK_VSSEG5E16V
, match_opcode
, INSN_DREF
},
1228 {"vlseg6e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG6E16V
, MASK_VLSEG6E16V
, match_opcode
, INSN_DREF
},
1229 {"vsseg6e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG6E16V
, MASK_VSSEG6E16V
, match_opcode
, INSN_DREF
},
1230 {"vlseg7e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG7E16V
, MASK_VLSEG7E16V
, match_opcode
, INSN_DREF
},
1231 {"vsseg7e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG7E16V
, MASK_VSSEG7E16V
, match_opcode
, INSN_DREF
},
1232 {"vlseg8e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG8E16V
, MASK_VLSEG8E16V
, match_opcode
, INSN_DREF
},
1233 {"vsseg8e16.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG8E16V
, MASK_VSSEG8E16V
, match_opcode
, INSN_DREF
},
1235 {"vlseg2e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG2E32V
, MASK_VLSEG2E32V
, match_opcode
, INSN_DREF
},
1236 {"vsseg2e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG2E32V
, MASK_VSSEG2E32V
, match_opcode
, INSN_DREF
},
1237 {"vlseg3e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG3E32V
, MASK_VLSEG3E32V
, match_opcode
, INSN_DREF
},
1238 {"vsseg3e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG3E32V
, MASK_VSSEG3E32V
, match_opcode
, INSN_DREF
},
1239 {"vlseg4e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG4E32V
, MASK_VLSEG4E32V
, match_opcode
, INSN_DREF
},
1240 {"vsseg4e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG4E32V
, MASK_VSSEG4E32V
, match_opcode
, INSN_DREF
},
1241 {"vlseg5e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG5E32V
, MASK_VLSEG5E32V
, match_opcode
, INSN_DREF
},
1242 {"vsseg5e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG5E32V
, MASK_VSSEG5E32V
, match_opcode
, INSN_DREF
},
1243 {"vlseg6e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG6E32V
, MASK_VLSEG6E32V
, match_opcode
, INSN_DREF
},
1244 {"vsseg6e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG6E32V
, MASK_VSSEG6E32V
, match_opcode
, INSN_DREF
},
1245 {"vlseg7e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG7E32V
, MASK_VLSEG7E32V
, match_opcode
, INSN_DREF
},
1246 {"vsseg7e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG7E32V
, MASK_VSSEG7E32V
, match_opcode
, INSN_DREF
},
1247 {"vlseg8e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG8E32V
, MASK_VLSEG8E32V
, match_opcode
, INSN_DREF
},
1248 {"vsseg8e32.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG8E32V
, MASK_VSSEG8E32V
, match_opcode
, INSN_DREF
},
1250 {"vlseg2e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG2E64V
, MASK_VLSEG2E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1251 {"vsseg2e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG2E64V
, MASK_VSSEG2E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1252 {"vlseg3e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG3E64V
, MASK_VLSEG3E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1253 {"vsseg3e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG3E64V
, MASK_VSSEG3E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1254 {"vlseg4e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG4E64V
, MASK_VLSEG4E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1255 {"vsseg4e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG4E64V
, MASK_VSSEG4E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1256 {"vlseg5e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG5E64V
, MASK_VLSEG5E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1257 {"vsseg5e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG5E64V
, MASK_VSSEG5E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1258 {"vlseg6e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG6E64V
, MASK_VLSEG6E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1259 {"vsseg6e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG6E64V
, MASK_VSSEG6E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1260 {"vlseg7e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG7E64V
, MASK_VLSEG7E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1261 {"vsseg7e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG7E64V
, MASK_VSSEG7E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1262 {"vlseg8e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG8E64V
, MASK_VLSEG8E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1263 {"vsseg8e64.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VSSEG8E64V
, MASK_VSSEG8E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1265 {"vlsseg2e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG2E8V
, MASK_VLSSEG2E8V
, match_opcode
, INSN_DREF
},
1266 {"vssseg2e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG2E8V
, MASK_VSSSEG2E8V
, match_opcode
, INSN_DREF
},
1267 {"vlsseg3e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG3E8V
, MASK_VLSSEG3E8V
, match_opcode
, INSN_DREF
},
1268 {"vssseg3e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG3E8V
, MASK_VSSSEG3E8V
, match_opcode
, INSN_DREF
},
1269 {"vlsseg4e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG4E8V
, MASK_VLSSEG4E8V
, match_opcode
, INSN_DREF
},
1270 {"vssseg4e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG4E8V
, MASK_VSSSEG4E8V
, match_opcode
, INSN_DREF
},
1271 {"vlsseg5e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG5E8V
, MASK_VLSSEG5E8V
, match_opcode
, INSN_DREF
},
1272 {"vssseg5e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG5E8V
, MASK_VSSSEG5E8V
, match_opcode
, INSN_DREF
},
1273 {"vlsseg6e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG6E8V
, MASK_VLSSEG6E8V
, match_opcode
, INSN_DREF
},
1274 {"vssseg6e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG6E8V
, MASK_VSSSEG6E8V
, match_opcode
, INSN_DREF
},
1275 {"vlsseg7e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG7E8V
, MASK_VLSSEG7E8V
, match_opcode
, INSN_DREF
},
1276 {"vssseg7e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG7E8V
, MASK_VSSSEG7E8V
, match_opcode
, INSN_DREF
},
1277 {"vlsseg8e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG8E8V
, MASK_VLSSEG8E8V
, match_opcode
, INSN_DREF
},
1278 {"vssseg8e8.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG8E8V
, MASK_VSSSEG8E8V
, match_opcode
, INSN_DREF
},
1280 {"vlsseg2e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG2E16V
, MASK_VLSSEG2E16V
, match_opcode
, INSN_DREF
},
1281 {"vssseg2e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG2E16V
, MASK_VSSSEG2E16V
, match_opcode
, INSN_DREF
},
1282 {"vlsseg3e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG3E16V
, MASK_VLSSEG3E16V
, match_opcode
, INSN_DREF
},
1283 {"vssseg3e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG3E16V
, MASK_VSSSEG3E16V
, match_opcode
, INSN_DREF
},
1284 {"vlsseg4e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG4E16V
, MASK_VLSSEG4E16V
, match_opcode
, INSN_DREF
},
1285 {"vssseg4e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG4E16V
, MASK_VSSSEG4E16V
, match_opcode
, INSN_DREF
},
1286 {"vlsseg5e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG5E16V
, MASK_VLSSEG5E16V
, match_opcode
, INSN_DREF
},
1287 {"vssseg5e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG5E16V
, MASK_VSSSEG5E16V
, match_opcode
, INSN_DREF
},
1288 {"vlsseg6e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG6E16V
, MASK_VLSSEG6E16V
, match_opcode
, INSN_DREF
},
1289 {"vssseg6e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG6E16V
, MASK_VSSSEG6E16V
, match_opcode
, INSN_DREF
},
1290 {"vlsseg7e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG7E16V
, MASK_VLSSEG7E16V
, match_opcode
, INSN_DREF
},
1291 {"vssseg7e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG7E16V
, MASK_VSSSEG7E16V
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, INSN_DREF
},
1292 {"vlsseg8e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG8E16V
, MASK_VLSSEG8E16V
, match_opcode
, INSN_DREF
},
1293 {"vssseg8e16.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG8E16V
, MASK_VSSSEG8E16V
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, INSN_DREF
},
1295 {"vlsseg2e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG2E32V
, MASK_VLSSEG2E32V
, match_opcode
, INSN_DREF
},
1296 {"vssseg2e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG2E32V
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, INSN_DREF
},
1297 {"vlsseg3e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG3E32V
, MASK_VLSSEG3E32V
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, INSN_DREF
},
1298 {"vssseg3e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG3E32V
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},
1299 {"vlsseg4e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG4E32V
, MASK_VLSSEG4E32V
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},
1300 {"vssseg4e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG4E32V
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},
1301 {"vlsseg5e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG5E32V
, MASK_VLSSEG5E32V
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},
1302 {"vssseg5e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG5E32V
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},
1303 {"vlsseg6e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG6E32V
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},
1304 {"vssseg6e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG6E32V
, MASK_VSSSEG6E32V
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, INSN_DREF
},
1305 {"vlsseg7e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG7E32V
, MASK_VLSSEG7E32V
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, INSN_DREF
},
1306 {"vssseg7e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG7E32V
, MASK_VSSSEG7E32V
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, INSN_DREF
},
1307 {"vlsseg8e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG8E32V
, MASK_VLSSEG8E32V
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, INSN_DREF
},
1308 {"vssseg8e32.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG8E32V
, MASK_VSSSEG8E32V
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, INSN_DREF
},
1310 {"vlsseg2e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG2E64V
, MASK_VLSSEG2E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1311 {"vssseg2e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG2E64V
, MASK_VSSSEG2E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1312 {"vlsseg3e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG3E64V
, MASK_VLSSEG3E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1313 {"vssseg3e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG3E64V
, MASK_VSSSEG3E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1314 {"vlsseg4e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG4E64V
, MASK_VLSSEG4E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1315 {"vssseg4e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG4E64V
, MASK_VSSSEG4E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1316 {"vlsseg5e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG5E64V
, MASK_VLSSEG5E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1317 {"vssseg5e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG5E64V
, MASK_VSSSEG5E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1318 {"vlsseg6e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG6E64V
, MASK_VLSSEG6E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1319 {"vssseg6e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG6E64V
, MASK_VSSSEG6E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1320 {"vlsseg7e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG7E64V
, MASK_VLSSEG7E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1321 {"vssseg7e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG7E64V
, MASK_VSSSEG7E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1322 {"vlsseg8e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VLSSEG8E64V
, MASK_VLSSEG8E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1323 {"vssseg8e64.v", 0, INSN_CLASS_V
, "Vd,0(s),tVm", MATCH_VSSSEG8E64V
, MASK_VSSSEG8E64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1325 {"vloxseg2ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V
, MASK_VLOXSEG2EI8V
, match_opcode
, INSN_DREF
},
1326 {"vsoxseg2ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V
, MASK_VSOXSEG2EI8V
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, INSN_DREF
},
1327 {"vloxseg3ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V
, MASK_VLOXSEG3EI8V
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, INSN_DREF
},
1328 {"vsoxseg3ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V
, MASK_VSOXSEG3EI8V
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, INSN_DREF
},
1329 {"vloxseg4ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V
, MASK_VLOXSEG4EI8V
, match_opcode
, INSN_DREF
},
1330 {"vsoxseg4ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V
, MASK_VSOXSEG4EI8V
, match_opcode
, INSN_DREF
},
1331 {"vloxseg5ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V
, MASK_VLOXSEG5EI8V
, match_opcode
, INSN_DREF
},
1332 {"vsoxseg5ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V
, MASK_VSOXSEG5EI8V
, match_opcode
, INSN_DREF
},
1333 {"vloxseg6ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V
, MASK_VLOXSEG6EI8V
, match_opcode
, INSN_DREF
},
1334 {"vsoxseg6ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V
, MASK_VSOXSEG6EI8V
, match_opcode
, INSN_DREF
},
1335 {"vloxseg7ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V
, MASK_VLOXSEG7EI8V
, match_opcode
, INSN_DREF
},
1336 {"vsoxseg7ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V
, MASK_VSOXSEG7EI8V
, match_opcode
, INSN_DREF
},
1337 {"vloxseg8ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V
, MASK_VLOXSEG8EI8V
, match_opcode
, INSN_DREF
},
1338 {"vsoxseg8ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V
, MASK_VSOXSEG8EI8V
, match_opcode
, INSN_DREF
},
1340 {"vloxseg2ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V
, MASK_VLOXSEG2EI16V
, match_opcode
, INSN_DREF
},
1341 {"vsoxseg2ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V
, MASK_VSOXSEG2EI16V
, match_opcode
, INSN_DREF
},
1342 {"vloxseg3ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V
, MASK_VLOXSEG3EI16V
, match_opcode
, INSN_DREF
},
1343 {"vsoxseg3ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V
, MASK_VSOXSEG3EI16V
, match_opcode
, INSN_DREF
},
1344 {"vloxseg4ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V
, MASK_VLOXSEG4EI16V
, match_opcode
, INSN_DREF
},
1345 {"vsoxseg4ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V
, MASK_VSOXSEG4EI16V
, match_opcode
, INSN_DREF
},
1346 {"vloxseg5ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V
, MASK_VLOXSEG5EI16V
, match_opcode
, INSN_DREF
},
1347 {"vsoxseg5ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V
, MASK_VSOXSEG5EI16V
, match_opcode
, INSN_DREF
},
1348 {"vloxseg6ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V
, MASK_VLOXSEG6EI16V
, match_opcode
, INSN_DREF
},
1349 {"vsoxseg6ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V
, MASK_VSOXSEG6EI16V
, match_opcode
, INSN_DREF
},
1350 {"vloxseg7ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V
, MASK_VLOXSEG7EI16V
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, INSN_DREF
},
1351 {"vsoxseg7ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V
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, match_opcode
, INSN_DREF
},
1352 {"vloxseg8ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V
, MASK_VLOXSEG8EI16V
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, INSN_DREF
},
1353 {"vsoxseg8ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V
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, INSN_DREF
},
1355 {"vloxseg2ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V
, MASK_VLOXSEG2EI32V
, match_opcode
, INSN_DREF
},
1356 {"vsoxseg2ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V
, MASK_VSOXSEG2EI32V
, match_opcode
, INSN_DREF
},
1357 {"vloxseg3ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V
, MASK_VLOXSEG3EI32V
, match_opcode
, INSN_DREF
},
1358 {"vsoxseg3ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V
, MASK_VSOXSEG3EI32V
, match_opcode
, INSN_DREF
},
1359 {"vloxseg4ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V
, MASK_VLOXSEG4EI32V
, match_opcode
, INSN_DREF
},
1360 {"vsoxseg4ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V
, MASK_VSOXSEG4EI32V
, match_opcode
, INSN_DREF
},
1361 {"vloxseg5ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V
, MASK_VLOXSEG5EI32V
, match_opcode
, INSN_DREF
},
1362 {"vsoxseg5ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V
, MASK_VSOXSEG5EI32V
, match_opcode
, INSN_DREF
},
1363 {"vloxseg6ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V
, MASK_VLOXSEG6EI32V
, match_opcode
, INSN_DREF
},
1364 {"vsoxseg6ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V
, MASK_VSOXSEG6EI32V
, match_opcode
, INSN_DREF
},
1365 {"vloxseg7ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V
, MASK_VLOXSEG7EI32V
, match_opcode
, INSN_DREF
},
1366 {"vsoxseg7ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V
, MASK_VSOXSEG7EI32V
, match_opcode
, INSN_DREF
},
1367 {"vloxseg8ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V
, MASK_VLOXSEG8EI32V
, match_opcode
, INSN_DREF
},
1368 {"vsoxseg8ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V
, MASK_VSOXSEG8EI32V
, match_opcode
, INSN_DREF
},
1370 {"vloxseg2ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V
, MASK_VLOXSEG2EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1371 {"vsoxseg2ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V
, MASK_VSOXSEG2EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1372 {"vloxseg3ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V
, MASK_VLOXSEG3EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1373 {"vsoxseg3ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V
, MASK_VSOXSEG3EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1374 {"vloxseg4ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V
, MASK_VLOXSEG4EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1375 {"vsoxseg4ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V
, MASK_VSOXSEG4EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1376 {"vloxseg5ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V
, MASK_VLOXSEG5EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1377 {"vsoxseg5ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V
, MASK_VSOXSEG5EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1378 {"vloxseg6ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V
, MASK_VLOXSEG6EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1379 {"vsoxseg6ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V
, MASK_VSOXSEG6EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1380 {"vloxseg7ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V
, MASK_VLOXSEG7EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1381 {"vsoxseg7ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V
, MASK_VSOXSEG7EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1382 {"vloxseg8ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V
, MASK_VLOXSEG8EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1383 {"vsoxseg8ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V
, MASK_VSOXSEG8EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1385 {"vluxseg2ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V
, MASK_VLUXSEG2EI8V
, match_opcode
, INSN_DREF
},
1386 {"vsuxseg2ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V
, MASK_VSUXSEG2EI8V
, match_opcode
, INSN_DREF
},
1387 {"vluxseg3ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V
, MASK_VLUXSEG3EI8V
, match_opcode
, INSN_DREF
},
1388 {"vsuxseg3ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V
, MASK_VSUXSEG3EI8V
, match_opcode
, INSN_DREF
},
1389 {"vluxseg4ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V
, MASK_VLUXSEG4EI8V
, match_opcode
, INSN_DREF
},
1390 {"vsuxseg4ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V
, MASK_VSUXSEG4EI8V
, match_opcode
, INSN_DREF
},
1391 {"vluxseg5ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V
, MASK_VLUXSEG5EI8V
, match_opcode
, INSN_DREF
},
1392 {"vsuxseg5ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V
, MASK_VSUXSEG5EI8V
, match_opcode
, INSN_DREF
},
1393 {"vluxseg6ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V
, MASK_VLUXSEG6EI8V
, match_opcode
, INSN_DREF
},
1394 {"vsuxseg6ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V
, MASK_VSUXSEG6EI8V
, match_opcode
, INSN_DREF
},
1395 {"vluxseg7ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V
, MASK_VLUXSEG7EI8V
, match_opcode
, INSN_DREF
},
1396 {"vsuxseg7ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V
, MASK_VSUXSEG7EI8V
, match_opcode
, INSN_DREF
},
1397 {"vluxseg8ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V
, MASK_VLUXSEG8EI8V
, match_opcode
, INSN_DREF
},
1398 {"vsuxseg8ei8.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V
, MASK_VSUXSEG8EI8V
, match_opcode
, INSN_DREF
},
1400 {"vluxseg2ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V
, MASK_VLUXSEG2EI16V
, match_opcode
, INSN_DREF
},
1401 {"vsuxseg2ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V
, MASK_VSUXSEG2EI16V
, match_opcode
, INSN_DREF
},
1402 {"vluxseg3ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V
, MASK_VLUXSEG3EI16V
, match_opcode
, INSN_DREF
},
1403 {"vsuxseg3ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V
, MASK_VSUXSEG3EI16V
, match_opcode
, INSN_DREF
},
1404 {"vluxseg4ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V
, MASK_VLUXSEG4EI16V
, match_opcode
, INSN_DREF
},
1405 {"vsuxseg4ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V
, MASK_VSUXSEG4EI16V
, match_opcode
, INSN_DREF
},
1406 {"vluxseg5ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V
, MASK_VLUXSEG5EI16V
, match_opcode
, INSN_DREF
},
1407 {"vsuxseg5ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V
, MASK_VSUXSEG5EI16V
, match_opcode
, INSN_DREF
},
1408 {"vluxseg6ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V
, MASK_VLUXSEG6EI16V
, match_opcode
, INSN_DREF
},
1409 {"vsuxseg6ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V
, MASK_VSUXSEG6EI16V
, match_opcode
, INSN_DREF
},
1410 {"vluxseg7ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V
, MASK_VLUXSEG7EI16V
, match_opcode
, INSN_DREF
},
1411 {"vsuxseg7ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V
, MASK_VSUXSEG7EI16V
, match_opcode
, INSN_DREF
},
1412 {"vluxseg8ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V
, MASK_VLUXSEG8EI16V
, match_opcode
, INSN_DREF
},
1413 {"vsuxseg8ei16.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V
, MASK_VSUXSEG8EI16V
, match_opcode
, INSN_DREF
},
1415 {"vluxseg2ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V
, MASK_VLUXSEG2EI32V
, match_opcode
, INSN_DREF
},
1416 {"vsuxseg2ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V
, MASK_VSUXSEG2EI32V
, match_opcode
, INSN_DREF
},
1417 {"vluxseg3ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V
, MASK_VLUXSEG3EI32V
, match_opcode
, INSN_DREF
},
1418 {"vsuxseg3ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V
, MASK_VSUXSEG3EI32V
, match_opcode
, INSN_DREF
},
1419 {"vluxseg4ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V
, MASK_VLUXSEG4EI32V
, match_opcode
, INSN_DREF
},
1420 {"vsuxseg4ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V
, MASK_VSUXSEG4EI32V
, match_opcode
, INSN_DREF
},
1421 {"vluxseg5ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V
, MASK_VLUXSEG5EI32V
, match_opcode
, INSN_DREF
},
1422 {"vsuxseg5ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V
, MASK_VSUXSEG5EI32V
, match_opcode
, INSN_DREF
},
1423 {"vluxseg6ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V
, MASK_VLUXSEG6EI32V
, match_opcode
, INSN_DREF
},
1424 {"vsuxseg6ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V
, MASK_VSUXSEG6EI32V
, match_opcode
, INSN_DREF
},
1425 {"vluxseg7ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V
, MASK_VLUXSEG7EI32V
, match_opcode
, INSN_DREF
},
1426 {"vsuxseg7ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V
, MASK_VSUXSEG7EI32V
, match_opcode
, INSN_DREF
},
1427 {"vluxseg8ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V
, MASK_VLUXSEG8EI32V
, match_opcode
, INSN_DREF
},
1428 {"vsuxseg8ei32.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V
, MASK_VSUXSEG8EI32V
, match_opcode
, INSN_DREF
},
1430 {"vluxseg2ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V
, MASK_VLUXSEG2EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1431 {"vsuxseg2ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V
, MASK_VSUXSEG2EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1432 {"vluxseg3ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V
, MASK_VLUXSEG3EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1433 {"vsuxseg3ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V
, MASK_VSUXSEG3EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1434 {"vluxseg4ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V
, MASK_VLUXSEG4EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1435 {"vsuxseg4ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V
, MASK_VSUXSEG4EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1436 {"vluxseg5ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V
, MASK_VLUXSEG5EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1437 {"vsuxseg5ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V
, MASK_VSUXSEG5EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1438 {"vluxseg6ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V
, MASK_VLUXSEG6EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1439 {"vsuxseg6ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V
, MASK_VSUXSEG6EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1440 {"vluxseg7ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V
, MASK_VLUXSEG7EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1441 {"vsuxseg7ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V
, MASK_VSUXSEG7EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1442 {"vluxseg8ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V
, MASK_VLUXSEG8EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1443 {"vsuxseg8ei64.v", 0, INSN_CLASS_V
, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V
, MASK_VSUXSEG8EI64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1445 {"vlseg2e8ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV
, MASK_VLSEG2E8FFV
, match_opcode
, INSN_DREF
},
1446 {"vlseg3e8ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV
, MASK_VLSEG3E8FFV
, match_opcode
, INSN_DREF
},
1447 {"vlseg4e8ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG4E8FFV
, MASK_VLSEG4E8FFV
, match_opcode
, INSN_DREF
},
1448 {"vlseg5e8ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG5E8FFV
, MASK_VLSEG5E8FFV
, match_opcode
, INSN_DREF
},
1449 {"vlseg6e8ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG6E8FFV
, MASK_VLSEG6E8FFV
, match_opcode
, INSN_DREF
},
1450 {"vlseg7e8ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG7E8FFV
, MASK_VLSEG7E8FFV
, match_opcode
, INSN_DREF
},
1451 {"vlseg8e8ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG8E8FFV
, MASK_VLSEG8E8FFV
, match_opcode
, INSN_DREF
},
1453 {"vlseg2e16ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG2E16FFV
, MASK_VLSEG2E16FFV
, match_opcode
, INSN_DREF
},
1454 {"vlseg3e16ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG3E16FFV
, MASK_VLSEG3E16FFV
, match_opcode
, INSN_DREF
},
1455 {"vlseg4e16ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG4E16FFV
, MASK_VLSEG4E16FFV
, match_opcode
, INSN_DREF
},
1456 {"vlseg5e16ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG5E16FFV
, MASK_VLSEG5E16FFV
, match_opcode
, INSN_DREF
},
1457 {"vlseg6e16ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG6E16FFV
, MASK_VLSEG6E16FFV
, match_opcode
, INSN_DREF
},
1458 {"vlseg7e16ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG7E16FFV
, MASK_VLSEG7E16FFV
, match_opcode
, INSN_DREF
},
1459 {"vlseg8e16ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG8E16FFV
, MASK_VLSEG8E16FFV
, match_opcode
, INSN_DREF
},
1461 {"vlseg2e32ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG2E32FFV
, MASK_VLSEG2E32FFV
, match_opcode
, INSN_DREF
},
1462 {"vlseg3e32ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG3E32FFV
, MASK_VLSEG3E32FFV
, match_opcode
, INSN_DREF
},
1463 {"vlseg4e32ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG4E32FFV
, MASK_VLSEG4E32FFV
, match_opcode
, INSN_DREF
},
1464 {"vlseg5e32ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG5E32FFV
, MASK_VLSEG5E32FFV
, match_opcode
, INSN_DREF
},
1465 {"vlseg6e32ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG6E32FFV
, MASK_VLSEG6E32FFV
, match_opcode
, INSN_DREF
},
1466 {"vlseg7e32ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV
, MASK_VLSEG7E32FFV
, match_opcode
, INSN_DREF
},
1467 {"vlseg8e32ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV
, MASK_VLSEG8E32FFV
, match_opcode
, INSN_DREF
},
1469 {"vlseg2e64ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV
, MASK_VLSEG2E64FFV
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1470 {"vlseg3e64ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV
, MASK_VLSEG3E64FFV
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1471 {"vlseg4e64ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV
, MASK_VLSEG4E64FFV
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1472 {"vlseg5e64ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV
, MASK_VLSEG5E64FFV
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1473 {"vlseg6e64ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV
, MASK_VLSEG6E64FFV
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1474 {"vlseg7e64ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV
, MASK_VLSEG7E64FFV
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1475 {"vlseg8e64ff.v", 0, INSN_CLASS_V
, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV
, MASK_VLSEG8E64FFV
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1477 {"vl1r.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL1RE8V
, MASK_VL1RE8V
, match_opcode
, INSN_DREF
|INSN_ALIAS
},
1478 {"vl1re8.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL1RE8V
, MASK_VL1RE8V
, match_opcode
, INSN_DREF
},
1479 {"vl1re16.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL1RE16V
, MASK_VL1RE16V
, match_opcode
, INSN_DREF
},
1480 {"vl1re32.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL1RE32V
, MASK_VL1RE32V
, match_opcode
, INSN_DREF
},
1481 {"vl1re64.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL1RE64V
, MASK_VL1RE64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1483 {"vl2r.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL2RE8V
, MASK_VL2RE8V
, match_opcode
, INSN_DREF
|INSN_ALIAS
},
1484 {"vl2re8.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL2RE8V
, MASK_VL2RE8V
, match_opcode
, INSN_DREF
},
1485 {"vl2re16.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL2RE16V
, MASK_VL2RE16V
, match_opcode
, INSN_DREF
},
1486 {"vl2re32.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL2RE32V
, MASK_VL2RE32V
, match_opcode
, INSN_DREF
},
1487 {"vl2re64.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL2RE64V
, MASK_VL2RE64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1489 {"vl4r.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL4RE8V
, MASK_VL4RE8V
, match_opcode
, INSN_DREF
|INSN_ALIAS
},
1490 {"vl4re8.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL4RE8V
, MASK_VL4RE8V
, match_opcode
, INSN_DREF
},
1491 {"vl4re16.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL4RE16V
, MASK_VL4RE16V
, match_opcode
, INSN_DREF
},
1492 {"vl4re32.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL4RE32V
, MASK_VL4RE32V
, match_opcode
, INSN_DREF
},
1493 {"vl4re64.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL4RE64V
, MASK_VL4RE64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1495 {"vl8r.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL8RE8V
, MASK_VL8RE8V
, match_opcode
, INSN_DREF
|INSN_ALIAS
},
1496 {"vl8re8.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL8RE8V
, MASK_VL8RE8V
, match_opcode
, INSN_DREF
},
1497 {"vl8re16.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL8RE16V
, MASK_VL8RE16V
, match_opcode
, INSN_DREF
},
1498 {"vl8re32.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL8RE32V
, MASK_VL8RE32V
, match_opcode
, INSN_DREF
},
1499 {"vl8re64.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VL8RE64V
, MASK_VL8RE64V
, match_opcode
, INSN_DREF
|INSN_V_EEW64
},
1501 {"vs1r.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VS1RV
, MASK_VS1RV
, match_opcode
, INSN_DREF
},
1502 {"vs2r.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VS2RV
, MASK_VS2RV
, match_opcode
, INSN_DREF
},
1503 {"vs4r.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VS4RV
, MASK_VS4RV
, match_opcode
, INSN_DREF
},
1504 {"vs8r.v", 0, INSN_CLASS_V
, "Vd,0(s)", MATCH_VS8RV
, MASK_VS8RV
, match_opcode
, INSN_DREF
},
1506 {"vneg.v", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VRSUBVX
, MASK_VRSUBVX
| MASK_RS1
, match_opcode
, INSN_ALIAS
},
1508 {"vadd.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VADDVV
, MASK_VADDVV
, match_opcode
, 0 },
1509 {"vadd.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VADDVX
, MASK_VADDVX
, match_opcode
, 0 },
1510 {"vadd.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VADDVI
, MASK_VADDVI
, match_opcode
, 0 },
1511 {"vsub.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSUBVV
, MASK_VSUBVV
, match_opcode
, 0 },
1512 {"vsub.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSUBVX
, MASK_VSUBVX
, match_opcode
, 0 },
1513 {"vrsub.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VRSUBVX
, MASK_VRSUBVX
, match_opcode
, 0 },
1514 {"vrsub.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VRSUBVI
, MASK_VRSUBVI
, match_opcode
, 0 },
1516 {"vwcvt.x.x.v", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VWCVTXXV
, MASK_VWCVTXXV
, match_opcode
, INSN_ALIAS
},
1517 {"vwcvtu.x.x.v", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VWCVTUXXV
, MASK_VWCVTUXXV
, match_opcode
, INSN_ALIAS
},
1519 {"vwaddu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWADDUVV
, MASK_VWADDUVV
, match_opcode
, 0 },
1520 {"vwaddu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWADDUVX
, MASK_VWADDUVX
, match_opcode
, 0 },
1521 {"vwsubu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWSUBUVV
, MASK_VWSUBUVV
, match_opcode
, 0 },
1522 {"vwsubu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWSUBUVX
, MASK_VWSUBUVX
, match_opcode
, 0 },
1523 {"vwadd.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWADDVV
, MASK_VWADDVV
, match_opcode
, 0 },
1524 {"vwadd.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWADDVX
, MASK_VWADDVX
, match_opcode
, 0 },
1525 {"vwsub.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWSUBVV
, MASK_VWSUBVV
, match_opcode
, 0 },
1526 {"vwsub.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWSUBVX
, MASK_VWSUBVX
, match_opcode
, 0 },
1527 {"vwaddu.wv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWADDUWV
, MASK_VWADDUWV
, match_opcode
, 0 },
1528 {"vwaddu.wx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWADDUWX
, MASK_VWADDUWX
, match_opcode
, 0 },
1529 {"vwsubu.wv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWSUBUWV
, MASK_VWSUBUWV
, match_opcode
, 0 },
1530 {"vwsubu.wx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWSUBUWX
, MASK_VWSUBUWX
, match_opcode
, 0 },
1531 {"vwadd.wv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWADDWV
, MASK_VWADDWV
, match_opcode
, 0 },
1532 {"vwadd.wx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWADDWX
, MASK_VWADDWX
, match_opcode
, 0 },
1533 {"vwsub.wv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWSUBWV
, MASK_VWSUBWV
, match_opcode
, 0 },
1534 {"vwsub.wx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWSUBWX
, MASK_VWSUBWX
, match_opcode
, 0 },
1536 {"vzext.vf2", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VZEXT_VF2
, MASK_VZEXT_VF2
, match_opcode
, 0 },
1537 {"vsext.vf2", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VSEXT_VF2
, MASK_VSEXT_VF2
, match_opcode
, 0 },
1538 {"vzext.vf4", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VZEXT_VF4
, MASK_VZEXT_VF4
, match_opcode
, 0 },
1539 {"vsext.vf4", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VSEXT_VF4
, MASK_VSEXT_VF4
, match_opcode
, 0 },
1540 {"vzext.vf8", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VZEXT_VF8
, MASK_VZEXT_VF8
, match_opcode
, 0 },
1541 {"vsext.vf8", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VSEXT_VF8
, MASK_VSEXT_VF8
, match_opcode
, 0 },
1543 {"vadc.vvm", 0, INSN_CLASS_V
, "Vd,Vt,Vs,V0", MATCH_VADCVVM
, MASK_VADCVVM
, match_opcode
, 0 },
1544 {"vadc.vxm", 0, INSN_CLASS_V
, "Vd,Vt,s,V0", MATCH_VADCVXM
, MASK_VADCVXM
, match_opcode
, 0 },
1545 {"vadc.vim", 0, INSN_CLASS_V
, "Vd,Vt,Vi,V0", MATCH_VADCVIM
, MASK_VADCVIM
, match_opcode
, 0 },
1546 {"vmadc.vvm", 0, INSN_CLASS_V
, "Vd,Vt,Vs,V0", MATCH_VMADCVVM
, MASK_VMADCVVM
, match_opcode
, 0 },
1547 {"vmadc.vxm", 0, INSN_CLASS_V
, "Vd,Vt,s,V0", MATCH_VMADCVXM
, MASK_VMADCVXM
, match_opcode
, 0 },
1548 {"vmadc.vim", 0, INSN_CLASS_V
, "Vd,Vt,Vi,V0", MATCH_VMADCVIM
, MASK_VMADCVIM
, match_opcode
, 0 },
1549 {"vmadc.vv", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMADCVV
, MASK_VMADCVV
, match_opcode
, 0 },
1550 {"vmadc.vx", 0, INSN_CLASS_V
, "Vd,Vt,s", MATCH_VMADCVX
, MASK_VMADCVX
, match_opcode
, 0 },
1551 {"vmadc.vi", 0, INSN_CLASS_V
, "Vd,Vt,Vi", MATCH_VMADCVI
, MASK_VMADCVI
, match_opcode
, 0 },
1552 {"vsbc.vvm", 0, INSN_CLASS_V
, "Vd,Vt,Vs,V0", MATCH_VSBCVVM
, MASK_VSBCVVM
, match_opcode
, 0 },
1553 {"vsbc.vxm", 0, INSN_CLASS_V
, "Vd,Vt,s,V0", MATCH_VSBCVXM
, MASK_VSBCVXM
, match_opcode
, 0 },
1554 {"vmsbc.vvm", 0, INSN_CLASS_V
, "Vd,Vt,Vs,V0", MATCH_VMSBCVVM
, MASK_VMSBCVVM
, match_opcode
, 0 },
1555 {"vmsbc.vxm", 0, INSN_CLASS_V
, "Vd,Vt,s,V0", MATCH_VMSBCVXM
, MASK_VMSBCVXM
, match_opcode
, 0 },
1556 {"vmsbc.vv", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMSBCVV
, MASK_VMSBCVV
, match_opcode
, 0 },
1557 {"vmsbc.vx", 0, INSN_CLASS_V
, "Vd,Vt,s", MATCH_VMSBCVX
, MASK_VMSBCVX
, match_opcode
, 0 },
1559 {"vnot.v", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VNOTV
, MASK_VNOTV
, match_opcode
, INSN_ALIAS
},
1561 {"vand.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VANDVV
, MASK_VANDVV
, match_opcode
, 0 },
1562 {"vand.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VANDVX
, MASK_VANDVX
, match_opcode
, 0 },
1563 {"vand.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VANDVI
, MASK_VANDVI
, match_opcode
, 0 },
1564 {"vor.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VORVV
, MASK_VORVV
, match_opcode
, 0 },
1565 {"vor.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VORVX
, MASK_VORVX
, match_opcode
, 0 },
1566 {"vor.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VORVI
, MASK_VORVI
, match_opcode
, 0 },
1567 {"vxor.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VXORVV
, MASK_VXORVV
, match_opcode
, 0 },
1568 {"vxor.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VXORVX
, MASK_VXORVX
, match_opcode
, 0 },
1569 {"vxor.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VXORVI
, MASK_VXORVI
, match_opcode
, 0 },
1571 {"vsll.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSLLVV
, MASK_VSLLVV
, match_opcode
, 0 },
1572 {"vsll.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSLLVX
, MASK_VSLLVX
, match_opcode
, 0 },
1573 {"vsll.vi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VSLLVI
, MASK_VSLLVI
, match_opcode
, 0 },
1574 {"vsrl.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSRLVV
, MASK_VSRLVV
, match_opcode
, 0 },
1575 {"vsrl.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSRLVX
, MASK_VSRLVX
, match_opcode
, 0 },
1576 {"vsrl.vi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VSRLVI
, MASK_VSRLVI
, match_opcode
, 0 },
1577 {"vsra.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSRAVV
, MASK_VSRAVV
, match_opcode
, 0 },
1578 {"vsra.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSRAVX
, MASK_VSRAVX
, match_opcode
, 0 },
1579 {"vsra.vi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VSRAVI
, MASK_VSRAVI
, match_opcode
, 0 },
1581 {"vncvt.x.x.w",0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VNCVTXXW
, MASK_VNCVTXXW
, match_opcode
, INSN_ALIAS
},
1583 {"vnsrl.wv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VNSRLWV
, MASK_VNSRLWV
, match_opcode
, 0 },
1584 {"vnsrl.wx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VNSRLWX
, MASK_VNSRLWX
, match_opcode
, 0 },
1585 {"vnsrl.wi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VNSRLWI
, MASK_VNSRLWI
, match_opcode
, 0 },
1586 {"vnsra.wv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VNSRAWV
, MASK_VNSRAWV
, match_opcode
, 0 },
1587 {"vnsra.wx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VNSRAWX
, MASK_VNSRAWX
, match_opcode
, 0 },
1588 {"vnsra.wi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VNSRAWI
, MASK_VNSRAWI
, match_opcode
, 0 },
1590 {"vmseq.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMSEQVV
, MASK_VMSEQVV
, match_opcode
, 0 },
1591 {"vmseq.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMSEQVX
, MASK_VMSEQVX
, match_opcode
, 0 },
1592 {"vmseq.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VMSEQVI
, MASK_VMSEQVI
, match_opcode
, 0 },
1593 {"vmsne.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMSNEVV
, MASK_VMSNEVV
, match_opcode
, 0 },
1594 {"vmsne.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMSNEVX
, MASK_VMSNEVX
, match_opcode
, 0 },
1595 {"vmsne.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VMSNEVI
, MASK_VMSNEVI
, match_opcode
, 0 },
1596 {"vmsltu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMSLTUVV
, MASK_VMSLTUVV
, match_opcode
, 0 },
1597 {"vmsltu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMSLTUVX
, MASK_VMSLTUVX
, match_opcode
, 0 },
1598 {"vmslt.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMSLTVV
, MASK_VMSLTVV
, match_opcode
, 0 },
1599 {"vmslt.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMSLTVX
, MASK_VMSLTVX
, match_opcode
, 0 },
1600 {"vmsleu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMSLEUVV
, MASK_VMSLEUVV
, match_opcode
, 0 },
1601 {"vmsleu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMSLEUVX
, MASK_VMSLEUVX
, match_opcode
, 0 },
1602 {"vmsleu.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VMSLEUVI
, MASK_VMSLEUVI
, match_opcode
, 0 },
1603 {"vmsle.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMSLEVV
, MASK_VMSLEVV
, match_opcode
, 0 },
1604 {"vmsle.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMSLEVX
, MASK_VMSLEVX
, match_opcode
, 0 },
1605 {"vmsle.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VMSLEVI
, MASK_VMSLEVI
, match_opcode
, 0 },
1606 {"vmsgtu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMSGTUVX
, MASK_VMSGTUVX
, match_opcode
, 0 },
1607 {"vmsgtu.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VMSGTUVI
, MASK_VMSGTUVI
, match_opcode
, 0 },
1608 {"vmsgt.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMSGTVX
, MASK_VMSGTVX
, match_opcode
, 0 },
1609 {"vmsgt.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VMSGTVI
, MASK_VMSGTVI
, match_opcode
, 0 },
1610 {"vmsgt.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VMSLTVV
, MASK_VMSLTVV
, match_opcode
, INSN_ALIAS
},
1611 {"vmsgtu.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VMSLTUVV
, MASK_VMSLTUVV
, match_opcode
, INSN_ALIAS
},
1612 {"vmsge.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VMSLEVV
, MASK_VMSLEVV
, match_opcode
, INSN_ALIAS
},
1613 {"vmsgeu.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VMSLEUVV
, MASK_VMSLEUVV
, match_opcode
, INSN_ALIAS
},
1614 {"vmslt.vi", 0, INSN_CLASS_V
, "Vd,Vt,VkVm", MATCH_VMSLEVI
, MASK_VMSLEVI
, match_opcode
, INSN_ALIAS
},
1615 {"vmsltu.vi", 0, INSN_CLASS_V
, "Vd,Vu,0Vm", MATCH_VMSNEVV
, MASK_VMSNEVV
, match_vs1_eq_vs2
, INSN_ALIAS
},
1616 {"vmsltu.vi", 0, INSN_CLASS_V
, "Vd,Vt,VkVm", MATCH_VMSLEUVI
, MASK_VMSLEUVI
, match_opcode
, INSN_ALIAS
},
1617 {"vmsge.vi", 0, INSN_CLASS_V
, "Vd,Vt,VkVm", MATCH_VMSGTVI
, MASK_VMSGTVI
, match_opcode
, INSN_ALIAS
},
1618 {"vmsgeu.vi", 0, INSN_CLASS_V
, "Vd,Vu,0Vm", MATCH_VMSEQVV
, MASK_VMSEQVV
, match_vs1_eq_vs2
, INSN_ALIAS
},
1619 {"vmsgeu.vi", 0, INSN_CLASS_V
, "Vd,Vt,VkVm", MATCH_VMSGTUVI
, MASK_VMSGTUVI
, match_opcode
, INSN_ALIAS
},
1621 {"vmsge.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", 0, (int) M_VMSGE
, match_never
, INSN_MACRO
},
1622 {"vmsge.vx", 0, INSN_CLASS_V
, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE
, match_never
, INSN_MACRO
},
1623 {"vmsgeu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", 1, (int) M_VMSGE
, match_never
, INSN_MACRO
},
1624 {"vmsgeu.vx", 0, INSN_CLASS_V
, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE
, match_never
, INSN_MACRO
},
1626 {"vminu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMINUVV
, MASK_VMINUVV
, match_opcode
, 0},
1627 {"vminu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMINUVX
, MASK_VMINUVX
, match_opcode
, 0},
1628 {"vmin.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMINVV
, MASK_VMINVV
, match_opcode
, 0},
1629 {"vmin.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMINVX
, MASK_VMINVX
, match_opcode
, 0},
1630 {"vmaxu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMAXUVV
, MASK_VMAXUVV
, match_opcode
, 0},
1631 {"vmaxu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMAXUVX
, MASK_VMAXUVX
, match_opcode
, 0},
1632 {"vmax.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMAXVV
, MASK_VMAXVV
, match_opcode
, 0},
1633 {"vmax.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMAXVX
, MASK_VMAXVX
, match_opcode
, 0},
1635 {"vmul.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMULVV
, MASK_VMULVV
, match_opcode
, 0 },
1636 {"vmul.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMULVX
, MASK_VMULVX
, match_opcode
, 0 },
1637 {"vmulh.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMULHVV
, MASK_VMULHVV
, match_opcode
, 0 },
1638 {"vmulh.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMULHVX
, MASK_VMULHVX
, match_opcode
, 0 },
1639 {"vmulhu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMULHUVV
, MASK_VMULHUVV
, match_opcode
, 0 },
1640 {"vmulhu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMULHUVX
, MASK_VMULHUVX
, match_opcode
, 0 },
1641 {"vmulhsu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VMULHSUVV
, MASK_VMULHSUVV
, match_opcode
, 0 },
1642 {"vmulhsu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VMULHSUVX
, MASK_VMULHSUVX
, match_opcode
, 0 },
1644 {"vwmul.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWMULVV
, MASK_VWMULVV
, match_opcode
, 0 },
1645 {"vwmul.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWMULVX
, MASK_VWMULVX
, match_opcode
, 0 },
1646 {"vwmulu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWMULUVV
, MASK_VWMULUVV
, match_opcode
, 0 },
1647 {"vwmulu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWMULUVX
, MASK_VWMULUVX
, match_opcode
, 0 },
1648 {"vwmulsu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWMULSUVV
, MASK_VWMULSUVV
, match_opcode
, 0 },
1649 {"vwmulsu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VWMULSUVX
, MASK_VWMULSUVX
, match_opcode
, 0 },
1651 {"vmacc.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VMACCVV
, MASK_VMACCVV
, match_opcode
, 0},
1652 {"vmacc.vx", 0, INSN_CLASS_V
, "Vd,s,VtVm", MATCH_VMACCVX
, MASK_VMACCVX
, match_opcode
, 0},
1653 {"vnmsac.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VNMSACVV
, MASK_VNMSACVV
, match_opcode
, 0},
1654 {"vnmsac.vx", 0, INSN_CLASS_V
, "Vd,s,VtVm", MATCH_VNMSACVX
, MASK_VNMSACVX
, match_opcode
, 0},
1655 {"vmadd.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VMADDVV
, MASK_VMADDVV
, match_opcode
, 0},
1656 {"vmadd.vx", 0, INSN_CLASS_V
, "Vd,s,VtVm", MATCH_VMADDVX
, MASK_VMADDVX
, match_opcode
, 0},
1657 {"vnmsub.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VNMSUBVV
, MASK_VNMSUBVV
, match_opcode
, 0},
1658 {"vnmsub.vx", 0, INSN_CLASS_V
, "Vd,s,VtVm", MATCH_VNMSUBVX
, MASK_VNMSUBVX
, match_opcode
, 0},
1660 {"vwmaccu.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VWMACCUVV
, MASK_VWMACCUVV
, match_opcode
, 0},
1661 {"vwmaccu.vx", 0, INSN_CLASS_V
, "Vd,s,VtVm", MATCH_VWMACCUVX
, MASK_VWMACCUVX
, match_opcode
, 0},
1662 {"vwmacc.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VWMACCVV
, MASK_VWMACCVV
, match_opcode
, 0},
1663 {"vwmacc.vx", 0, INSN_CLASS_V
, "Vd,s,VtVm", MATCH_VWMACCVX
, MASK_VWMACCVX
, match_opcode
, 0},
1664 {"vwmaccsu.vv", 0, INSN_CLASS_V
, "Vd,Vs,VtVm", MATCH_VWMACCSUVV
, MASK_VWMACCSUVV
, match_opcode
, 0},
1665 {"vwmaccsu.vx", 0, INSN_CLASS_V
, "Vd,s,VtVm", MATCH_VWMACCSUVX
, MASK_VWMACCSUVX
, match_opcode
, 0},
1666 {"vwmaccus.vx", 0, INSN_CLASS_V
, "Vd,s,VtVm", MATCH_VWMACCUSVX
, MASK_VWMACCUSVX
, match_opcode
, 0},
1668 {"vdivu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VDIVUVV
, MASK_VDIVUVV
, match_opcode
, 0 },
1669 {"vdivu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VDIVUVX
, MASK_VDIVUVX
, match_opcode
, 0 },
1670 {"vdiv.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VDIVVV
, MASK_VDIVVV
, match_opcode
, 0 },
1671 {"vdiv.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VDIVVX
, MASK_VDIVVX
, match_opcode
, 0 },
1672 {"vremu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREMUVV
, MASK_VREMUVV
, match_opcode
, 0 },
1673 {"vremu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VREMUVX
, MASK_VREMUVX
, match_opcode
, 0 },
1674 {"vrem.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREMVV
, MASK_VREMVV
, match_opcode
, 0 },
1675 {"vrem.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VREMVX
, MASK_VREMVX
, match_opcode
, 0 },
1677 {"vmerge.vvm", 0, INSN_CLASS_V
, "Vd,Vt,Vs,V0", MATCH_VMERGEVVM
, MASK_VMERGEVVM
, match_opcode
, 0 },
1678 {"vmerge.vxm", 0, INSN_CLASS_V
, "Vd,Vt,s,V0", MATCH_VMERGEVXM
, MASK_VMERGEVXM
, match_opcode
, 0 },
1679 {"vmerge.vim", 0, INSN_CLASS_V
, "Vd,Vt,Vi,V0", MATCH_VMERGEVIM
, MASK_VMERGEVIM
, match_opcode
, 0 },
1681 {"vmv.v.v", 0, INSN_CLASS_V
, "Vd,Vs", MATCH_VMVVV
, MASK_VMVVV
, match_opcode
, 0 },
1682 {"vmv.v.x", 0, INSN_CLASS_V
, "Vd,s", MATCH_VMVVX
, MASK_VMVVX
, match_opcode
, 0 },
1683 {"vmv.v.i", 0, INSN_CLASS_V
, "Vd,Vi", MATCH_VMVVI
, MASK_VMVVI
, match_opcode
, 0 },
1685 {"vsaddu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSADDUVV
, MASK_VSADDUVV
, match_opcode
, 0 },
1686 {"vsaddu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSADDUVX
, MASK_VSADDUVX
, match_opcode
, 0 },
1687 {"vsaddu.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VSADDUVI
, MASK_VSADDUVI
, match_opcode
, 0 },
1688 {"vsadd.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSADDVV
, MASK_VSADDVV
, match_opcode
, 0 },
1689 {"vsadd.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSADDVX
, MASK_VSADDVX
, match_opcode
, 0 },
1690 {"vsadd.vi", 0, INSN_CLASS_V
, "Vd,Vt,ViVm", MATCH_VSADDVI
, MASK_VSADDVI
, match_opcode
, 0 },
1691 {"vssubu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSSUBUVV
, MASK_VSSUBUVV
, match_opcode
, 0 },
1692 {"vssubu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSSUBUVX
, MASK_VSSUBUVX
, match_opcode
, 0 },
1693 {"vssub.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSSUBVV
, MASK_VSSUBVV
, match_opcode
, 0 },
1694 {"vssub.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSSUBVX
, MASK_VSSUBVX
, match_opcode
, 0 },
1696 {"vaaddu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VAADDUVV
, MASK_VAADDUVV
, match_opcode
, 0 },
1697 {"vaaddu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VAADDUVX
, MASK_VAADDUVX
, match_opcode
, 0 },
1698 {"vaadd.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VAADDVV
, MASK_VAADDVV
, match_opcode
, 0 },
1699 {"vaadd.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VAADDVX
, MASK_VAADDVX
, match_opcode
, 0 },
1700 {"vasubu.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VASUBUVV
, MASK_VASUBUVV
, match_opcode
, 0 },
1701 {"vasubu.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VASUBUVX
, MASK_VASUBUVX
, match_opcode
, 0 },
1702 {"vasub.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VASUBVV
, MASK_VASUBVV
, match_opcode
, 0 },
1703 {"vasub.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VASUBVX
, MASK_VASUBVX
, match_opcode
, 0 },
1705 {"vsmul.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSMULVV
, MASK_VSMULVV
, match_opcode
, 0 },
1706 {"vsmul.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSMULVX
, MASK_VSMULVX
, match_opcode
, 0 },
1708 {"vssrl.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSSRLVV
, MASK_VSSRLVV
, match_opcode
, 0 },
1709 {"vssrl.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSSRLVX
, MASK_VSSRLVX
, match_opcode
, 0 },
1710 {"vssrl.vi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VSSRLVI
, MASK_VSSRLVI
, match_opcode
, 0 },
1711 {"vssra.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VSSRAVV
, MASK_VSSRAVV
, match_opcode
, 0 },
1712 {"vssra.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSSRAVX
, MASK_VSSRAVX
, match_opcode
, 0 },
1713 {"vssra.vi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VSSRAVI
, MASK_VSSRAVI
, match_opcode
, 0 },
1715 {"vnclipu.wv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VNCLIPUWV
, MASK_VNCLIPUWV
, match_opcode
, 0 },
1716 {"vnclipu.wx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VNCLIPUWX
, MASK_VNCLIPUWX
, match_opcode
, 0 },
1717 {"vnclipu.wi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VNCLIPUWI
, MASK_VNCLIPUWI
, match_opcode
, 0 },
1718 {"vnclip.wv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VNCLIPWV
, MASK_VNCLIPWV
, match_opcode
, 0 },
1719 {"vnclip.wx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VNCLIPWX
, MASK_VNCLIPWX
, match_opcode
, 0 },
1720 {"vnclip.wi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VNCLIPWI
, MASK_VNCLIPWI
, match_opcode
, 0 },
1722 {"vfadd.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFADDVV
, MASK_VFADDVV
, match_opcode
, 0},
1723 {"vfadd.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFADDVF
, MASK_VFADDVF
, match_opcode
, 0},
1724 {"vfsub.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFSUBVV
, MASK_VFSUBVV
, match_opcode
, 0},
1725 {"vfsub.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFSUBVF
, MASK_VFSUBVF
, match_opcode
, 0},
1726 {"vfrsub.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFRSUBVF
, MASK_VFRSUBVF
, match_opcode
, 0},
1728 {"vfwadd.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFWADDVV
, MASK_VFWADDVV
, match_opcode
, 0},
1729 {"vfwadd.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFWADDVF
, MASK_VFWADDVF
, match_opcode
, 0},
1730 {"vfwsub.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFWSUBVV
, MASK_VFWSUBVV
, match_opcode
, 0},
1731 {"vfwsub.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFWSUBVF
, MASK_VFWSUBVF
, match_opcode
, 0},
1732 {"vfwadd.wv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFWADDWV
, MASK_VFWADDWV
, match_opcode
, 0},
1733 {"vfwadd.wf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFWADDWF
, MASK_VFWADDWF
, match_opcode
, 0},
1734 {"vfwsub.wv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFWSUBWV
, MASK_VFWSUBWV
, match_opcode
, 0},
1735 {"vfwsub.wf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFWSUBWF
, MASK_VFWSUBWF
, match_opcode
, 0},
1737 {"vfmul.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFMULVV
, MASK_VFMULVV
, match_opcode
, 0},
1738 {"vfmul.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFMULVF
, MASK_VFMULVF
, match_opcode
, 0},
1739 {"vfdiv.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFDIVVV
, MASK_VFDIVVV
, match_opcode
, 0},
1740 {"vfdiv.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFDIVVF
, MASK_VFDIVVF
, match_opcode
, 0},
1741 {"vfrdiv.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFRDIVVF
, MASK_VFRDIVVF
, match_opcode
, 0},
1743 {"vfwmul.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFWMULVV
, MASK_VFWMULVV
, match_opcode
, 0},
1744 {"vfwmul.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFWMULVF
, MASK_VFWMULVF
, match_opcode
, 0},
1746 {"vfmadd.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFMADDVV
, MASK_VFMADDVV
, match_opcode
, 0},
1747 {"vfmadd.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFMADDVF
, MASK_VFMADDVF
, match_opcode
, 0},
1748 {"vfnmadd.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFNMADDVV
, MASK_VFNMADDVV
, match_opcode
, 0},
1749 {"vfnmadd.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFNMADDVF
, MASK_VFNMADDVF
, match_opcode
, 0},
1750 {"vfmsub.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFMSUBVV
, MASK_VFMSUBVV
, match_opcode
, 0},
1751 {"vfmsub.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFMSUBVF
, MASK_VFMSUBVF
, match_opcode
, 0},
1752 {"vfnmsub.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFNMSUBVV
, MASK_VFNMSUBVV
, match_opcode
, 0},
1753 {"vfnmsub.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFNMSUBVF
, MASK_VFNMSUBVF
, match_opcode
, 0},
1754 {"vfmacc.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFMACCVV
, MASK_VFMACCVV
, match_opcode
, 0},
1755 {"vfmacc.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFMACCVF
, MASK_VFMACCVF
, match_opcode
, 0},
1756 {"vfnmacc.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFNMACCVV
, MASK_VFNMACCVV
, match_opcode
, 0},
1757 {"vfnmacc.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFNMACCVF
, MASK_VFNMACCVF
, match_opcode
, 0},
1758 {"vfmsac.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFMSACVV
, MASK_VFMSACVV
, match_opcode
, 0},
1759 {"vfmsac.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFMSACVF
, MASK_VFMSACVF
, match_opcode
, 0},
1760 {"vfnmsac.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFNMSACVV
, MASK_VFNMSACVV
, match_opcode
, 0},
1761 {"vfnmsac.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFNMSACVF
, MASK_VFNMSACVF
, match_opcode
, 0},
1763 {"vfwmacc.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFWMACCVV
, MASK_VFWMACCVV
, match_opcode
, 0},
1764 {"vfwmacc.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFWMACCVF
, MASK_VFWMACCVF
, match_opcode
, 0},
1765 {"vfwnmacc.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFWNMACCVV
, MASK_VFWNMACCVV
, match_opcode
, 0},
1766 {"vfwnmacc.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFWNMACCVF
, MASK_VFWNMACCVF
, match_opcode
, 0},
1767 {"vfwmsac.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFWMSACVV
, MASK_VFWMSACVV
, match_opcode
, 0},
1768 {"vfwmsac.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFWMSACVF
, MASK_VFWMSACVF
, match_opcode
, 0},
1769 {"vfwnmsac.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VFWNMSACVV
, MASK_VFWNMSACVV
, match_opcode
, 0},
1770 {"vfwnmsac.vf", 0, INSN_CLASS_ZVEF
, "Vd,S,VtVm", MATCH_VFWNMSACVF
, MASK_VFWNMSACVF
, match_opcode
, 0},
1772 {"vfsqrt.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFSQRTV
, MASK_VFSQRTV
, match_opcode
, 0},
1773 {"vfrsqrt7.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFRSQRT7V
, MASK_VFRSQRT7V
, match_opcode
, 0},
1774 {"vfrsqrte7.v",0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFRSQRT7V
, MASK_VFRSQRT7V
, match_opcode
, 0},
1775 {"vfrec7.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFREC7V
, MASK_VFREC7V
, match_opcode
, 0},
1776 {"vfrece7.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFREC7V
, MASK_VFREC7V
, match_opcode
, 0},
1777 {"vfclass.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFCLASSV
, MASK_VFCLASSV
, match_opcode
, 0},
1779 {"vfmin.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFMINVV
, MASK_VFMINVV
, match_opcode
, 0},
1780 {"vfmin.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFMINVF
, MASK_VFMINVF
, match_opcode
, 0},
1781 {"vfmax.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFMAXVV
, MASK_VFMAXVV
, match_opcode
, 0},
1782 {"vfmax.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFMAXVF
, MASK_VFMAXVF
, match_opcode
, 0},
1784 {"vfneg.v", 0, INSN_CLASS_ZVEF
, "Vd,VuVm", MATCH_VFSGNJNVV
, MASK_VFSGNJNVV
, match_vs1_eq_vs2
, INSN_ALIAS
},
1785 {"vfabs.v", 0, INSN_CLASS_ZVEF
, "Vd,VuVm", MATCH_VFSGNJXVV
, MASK_VFSGNJXVV
, match_vs1_eq_vs2
, INSN_ALIAS
},
1787 {"vfsgnj.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFSGNJVV
, MASK_VFSGNJVV
, match_opcode
, 0},
1788 {"vfsgnj.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFSGNJVF
, MASK_VFSGNJVF
, match_opcode
, 0},
1789 {"vfsgnjn.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFSGNJNVV
, MASK_VFSGNJNVV
, match_opcode
, 0},
1790 {"vfsgnjn.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFSGNJNVF
, MASK_VFSGNJNVF
, match_opcode
, 0},
1791 {"vfsgnjx.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFSGNJXVV
, MASK_VFSGNJXVV
, match_opcode
, 0},
1792 {"vfsgnjx.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFSGNJXVF
, MASK_VFSGNJXVF
, match_opcode
, 0},
1794 {"vmfeq.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VMFEQVV
, MASK_VMFEQVV
, match_opcode
, 0},
1795 {"vmfeq.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VMFEQVF
, MASK_VMFEQVF
, match_opcode
, 0},
1796 {"vmfne.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VMFNEVV
, MASK_VMFNEVV
, match_opcode
, 0},
1797 {"vmfne.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VMFNEVF
, MASK_VMFNEVF
, match_opcode
, 0},
1798 {"vmflt.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VMFLTVV
, MASK_VMFLTVV
, match_opcode
, 0},
1799 {"vmflt.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VMFLTVF
, MASK_VMFLTVF
, match_opcode
, 0},
1800 {"vmfle.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VMFLEVV
, MASK_VMFLEVV
, match_opcode
, 0},
1801 {"vmfle.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VMFLEVF
, MASK_VMFLEVF
, match_opcode
, 0},
1802 {"vmfgt.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VMFGTVF
, MASK_VMFGTVF
, match_opcode
, 0},
1803 {"vmfge.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VMFGEVF
, MASK_VMFGEVF
, match_opcode
, 0},
1805 /* These aliases are for assembly but not disassembly. */
1806 {"vmfgt.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VMFLTVV
, MASK_VMFLTVV
, match_opcode
, INSN_ALIAS
},
1807 {"vmfge.vv", 0, INSN_CLASS_ZVEF
, "Vd,Vs,VtVm", MATCH_VMFLEVV
, MASK_VMFLEVV
, match_opcode
, INSN_ALIAS
},
1809 {"vfmerge.vfm",0, INSN_CLASS_ZVEF
, "Vd,Vt,S,V0", MATCH_VFMERGEVFM
, MASK_VFMERGEVFM
, match_opcode
, 0},
1810 {"vfmv.v.f", 0, INSN_CLASS_ZVEF
, "Vd,S", MATCH_VFMVVF
, MASK_VFMVVF
, match_opcode
, 0 },
1812 {"vfcvt.xu.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFCVTXUFV
, MASK_VFCVTXUFV
, match_opcode
, 0},
1813 {"vfcvt.x.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFCVTXFV
, MASK_VFCVTXFV
, match_opcode
, 0},
1814 {"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFCVTRTZXUFV
, MASK_VFCVTRTZXUFV
, match_opcode
, 0},
1815 {"vfcvt.rtz.x.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFCVTRTZXFV
, MASK_VFCVTRTZXFV
, match_opcode
, 0},
1816 {"vfcvt.f.xu.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFCVTFXUV
, MASK_VFCVTFXUV
, match_opcode
, 0},
1817 {"vfcvt.f.x.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFCVTFXV
, MASK_VFCVTFXV
, match_opcode
, 0},
1819 {"vfwcvt.xu.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFWCVTXUFV
, MASK_VFWCVTXUFV
, match_opcode
, 0},
1820 {"vfwcvt.x.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFWCVTXFV
, MASK_VFWCVTXFV
, match_opcode
, 0},
1821 {"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFWCVTRTZXUFV
, MASK_VFWCVTRTZXUFV
, match_opcode
, 0},
1822 {"vfwcvt.rtz.x.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFWCVTRTZXFV
, MASK_VFWCVTRTZXFV
, match_opcode
, 0},
1823 {"vfwcvt.f.xu.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFWCVTFXUV
, MASK_VFWCVTFXUV
, match_opcode
, 0},
1824 {"vfwcvt.f.x.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFWCVTFXV
, MASK_VFWCVTFXV
, match_opcode
, 0},
1825 {"vfwcvt.f.f.v", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFWCVTFFV
, MASK_VFWCVTFFV
, match_opcode
, 0},
1827 {"vfncvt.xu.f.w", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFNCVTXUFW
, MASK_VFNCVTXUFW
, match_opcode
, 0},
1828 {"vfncvt.x.f.w", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFNCVTXFW
, MASK_VFNCVTXFW
, match_opcode
, 0},
1829 {"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFNCVTRTZXUFW
, MASK_VFNCVTRTZXUFW
, match_opcode
, 0},
1830 {"vfncvt.rtz.x.f.w", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFNCVTRTZXFW
, MASK_VFNCVTRTZXFW
, match_opcode
, 0},
1831 {"vfncvt.f.xu.w", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFNCVTFXUW
, MASK_VFNCVTFXUW
, match_opcode
, 0},
1832 {"vfncvt.f.x.w", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFNCVTFXW
, MASK_VFNCVTFXW
, match_opcode
, 0},
1833 {"vfncvt.f.f.w", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFNCVTFFW
, MASK_VFNCVTFFW
, match_opcode
, 0},
1834 {"vfncvt.rod.f.f.w", 0, INSN_CLASS_ZVEF
, "Vd,VtVm", MATCH_VFNCVTRODFFW
, MASK_VFNCVTRODFFW
, match_opcode
, 0},
1836 {"vredsum.vs", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREDSUMVS
, MASK_VREDSUMVS
, match_opcode
, 0},
1837 {"vredmaxu.vs",0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREDMAXUVS
, MASK_VREDMAXUVS
, match_opcode
, 0},
1838 {"vredmax.vs", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREDMAXVS
, MASK_VREDMAXVS
, match_opcode
, 0},
1839 {"vredminu.vs",0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREDMINUVS
, MASK_VREDMINUVS
, match_opcode
, 0},
1840 {"vredmin.vs", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREDMINVS
, MASK_VREDMINVS
, match_opcode
, 0},
1841 {"vredand.vs", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREDANDVS
, MASK_VREDANDVS
, match_opcode
, 0},
1842 {"vredor.vs", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREDORVS
, MASK_VREDORVS
, match_opcode
, 0},
1843 {"vredxor.vs", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VREDXORVS
, MASK_VREDXORVS
, match_opcode
, 0},
1845 {"vwredsumu.vs",0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS
, MASK_VWREDSUMUVS
, match_opcode
, 0},
1846 {"vwredsum.vs",0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VWREDSUMVS
, MASK_VWREDSUMVS
, match_opcode
, 0},
1848 {"vfredosum.vs",0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS
, MASK_VFREDOSUMVS
, match_opcode
, 0},
1849 {"vfredusum.vs",0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS
, MASK_VFREDUSUMVS
, match_opcode
, 0},
1850 {"vfredsum.vs", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS
, MASK_VFREDUSUMVS
, match_opcode
, INSN_ALIAS
},
1851 {"vfredmax.vs", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFREDMAXVS
, MASK_VFREDMAXVS
, match_opcode
, 0},
1852 {"vfredmin.vs", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFREDMINVS
, MASK_VFREDMINVS
, match_opcode
, 0},
1854 {"vfwredosum.vs",0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS
, MASK_VFWREDOSUMVS
, match_opcode
, 0},
1855 {"vfwredusum.vs",0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS
, MASK_VFWREDUSUMVS
, match_opcode
, 0},
1856 {"vfwredsum.vs", 0, INSN_CLASS_ZVEF
, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS
, MASK_VFWREDUSUMVS
, match_opcode
, INSN_ALIAS
},
1858 {"vmmv.m", 0, INSN_CLASS_V
, "Vd,Vu", MATCH_VMANDMM
, MASK_VMANDMM
, match_vs1_eq_vs2
, INSN_ALIAS
},
1859 {"vmcpy.m", 0, INSN_CLASS_V
, "Vd,Vu", MATCH_VMANDMM
, MASK_VMANDMM
, match_vs1_eq_vs2
, INSN_ALIAS
},
1860 {"vmclr.m", 0, INSN_CLASS_V
, "Vv", MATCH_VMXORMM
, MASK_VMXORMM
, match_vd_eq_vs1_eq_vs2
, INSN_ALIAS
},
1861 {"vmset.m", 0, INSN_CLASS_V
, "Vv", MATCH_VMXNORMM
, MASK_VMXNORMM
, match_vd_eq_vs1_eq_vs2
, INSN_ALIAS
},
1862 {"vmnot.m", 0, INSN_CLASS_V
, "Vd,Vu", MATCH_VMNANDMM
, MASK_VMNANDMM
, match_vs1_eq_vs2
, INSN_ALIAS
},
1864 {"vmand.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMANDMM
, MASK_VMANDMM
, match_opcode
, 0},
1865 {"vmnand.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMNANDMM
, MASK_VMNANDMM
, match_opcode
, 0},
1866 {"vmandn.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMANDNMM
, MASK_VMANDNMM
, match_opcode
, 0},
1867 {"vmandnot.mm",0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMANDNMM
, MASK_VMANDNMM
, match_opcode
, INSN_ALIAS
},
1868 {"vmxor.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMXORMM
, MASK_VMXORMM
, match_opcode
, 0},
1869 {"vmor.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMORMM
, MASK_VMORMM
, match_opcode
, 0},
1870 {"vmnor.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMNORMM
, MASK_VMNORMM
, match_opcode
, 0},
1871 {"vmorn.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMORNMM
, MASK_VMORNMM
, match_opcode
, 0},
1872 {"vmornot.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMORNMM
, MASK_VMORNMM
, match_opcode
, INSN_ALIAS
},
1873 {"vmxnor.mm", 0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VMXNORMM
, MASK_VMXNORMM
, match_opcode
, 0},
1875 {"vcpop.m", 0, INSN_CLASS_V
, "d,VtVm", MATCH_VCPOPM
, MASK_VCPOPM
, match_opcode
, 0},
1876 {"vpopc.m", 0, INSN_CLASS_V
, "d,VtVm", MATCH_VCPOPM
, MASK_VCPOPM
, match_opcode
, INSN_ALIAS
},
1877 {"vfirst.m", 0, INSN_CLASS_V
, "d,VtVm", MATCH_VFIRSTM
, MASK_VFIRSTM
, match_opcode
, 0},
1878 {"vmsbf.m", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VMSBFM
, MASK_VMSBFM
, match_opcode
, 0},
1879 {"vmsif.m", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VMSIFM
, MASK_VMSIFM
, match_opcode
, 0},
1880 {"vmsof.m", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VMSOFM
, MASK_VMSOFM
, match_opcode
, 0},
1881 {"viota.m", 0, INSN_CLASS_V
, "Vd,VtVm", MATCH_VIOTAM
, MASK_VIOTAM
, match_opcode
, 0},
1882 {"vid.v", 0, INSN_CLASS_V
, "VdVm", MATCH_VIDV
, MASK_VIDV
, match_opcode
, 0},
1884 {"vmv.x.s", 0, INSN_CLASS_V
, "d,Vt", MATCH_VMVXS
, MASK_VMVXS
, match_opcode
, 0},
1885 {"vmv.s.x", 0, INSN_CLASS_V
, "Vd,s", MATCH_VMVSX
, MASK_VMVSX
, match_opcode
, 0},
1887 {"vfmv.f.s", 0, INSN_CLASS_ZVEF
, "D,Vt", MATCH_VFMVFS
, MASK_VFMVFS
, match_opcode
, 0},
1888 {"vfmv.s.f", 0, INSN_CLASS_ZVEF
, "Vd,S", MATCH_VFMVSF
, MASK_VFMVSF
, match_opcode
, 0},
1890 {"vslideup.vx",0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSLIDEUPVX
, MASK_VSLIDEUPVX
, match_opcode
, 0},
1891 {"vslideup.vi",0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI
, MASK_VSLIDEUPVI
, match_opcode
, 0},
1892 {"vslidedown.vx",0,INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX
, MASK_VSLIDEDOWNVX
, match_opcode
, 0},
1893 {"vslidedown.vi",0,INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI
, MASK_VSLIDEDOWNVI
, match_opcode
, 0},
1895 {"vslide1up.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX
, MASK_VSLIDE1UPVX
, match_opcode
, 0},
1896 {"vslide1down.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX
, MASK_VSLIDE1DOWNVX
, match_opcode
, 0},
1897 {"vfslide1up.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF
, MASK_VFSLIDE1UPVF
, match_opcode
, 0},
1898 {"vfslide1down.vf", 0, INSN_CLASS_ZVEF
, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF
, MASK_VFSLIDE1DOWNVF
, match_opcode
, 0},
1900 {"vrgather.vv", 0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VRGATHERVV
, MASK_VRGATHERVV
, match_opcode
, 0},
1901 {"vrgather.vx", 0, INSN_CLASS_V
, "Vd,Vt,sVm", MATCH_VRGATHERVX
, MASK_VRGATHERVX
, match_opcode
, 0},
1902 {"vrgather.vi", 0, INSN_CLASS_V
, "Vd,Vt,VjVm", MATCH_VRGATHERVI
, MASK_VRGATHERVI
, match_opcode
, 0},
1903 {"vrgatherei16.vv",0, INSN_CLASS_V
, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV
, MASK_VRGATHEREI16VV
, match_opcode
, 0},
1905 {"vcompress.vm",0, INSN_CLASS_V
, "Vd,Vt,Vs", MATCH_VCOMPRESSVM
, MASK_VCOMPRESSVM
, match_opcode
, 0},
1907 {"vmv1r.v", 0, INSN_CLASS_V
, "Vd,Vt", MATCH_VMV1RV
, MASK_VMV1RV
, match_opcode
, 0},
1908 {"vmv2r.v", 0, INSN_CLASS_V
, "Vd,Vt", MATCH_VMV2RV
, MASK_VMV2RV
, match_opcode
, 0},
1909 {"vmv4r.v", 0, INSN_CLASS_V
, "Vd,Vt", MATCH_VMV4RV
, MASK_VMV4RV
, match_opcode
, 0},
1910 {"vmv8r.v", 0, INSN_CLASS_V
, "Vd,Vt", MATCH_VMV8RV
, MASK_VMV8RV
, match_opcode
, 0},
1912 /* Zvbb instructions. */
1913 {"vandn.vv", 0, INSN_CLASS_ZVBB
, "Vd,Vt,VsVm", MATCH_VANDN_VV
, MASK_VANDN_VV
, match_opcode
, 0},
1914 {"vandn.vx", 0, INSN_CLASS_ZVBB
, "Vd,Vt,sVm", MATCH_VANDN_VX
, MASK_VANDN_VX
, match_opcode
, 0},
1915 {"vbrev.v", 0, INSN_CLASS_ZVBB
, "Vd,VtVm", MATCH_VBREV_V
, MASK_VBREV_V
, match_opcode
, 0},
1916 {"vbrev8.v", 0, INSN_CLASS_ZVBB
, "Vd,VtVm", MATCH_VBREV8_V
, MASK_VBREV8_V
, match_opcode
, 0},
1917 {"vrev8.v", 0, INSN_CLASS_ZVBB
, "Vd,VtVm", MATCH_VREV8_V
, MASK_VREV8_V
, match_opcode
, 0},
1918 {"vclz.v", 0, INSN_CLASS_ZVBB
, "Vd,VtVm", MATCH_VCLZ_V
, MASK_VCLZ_V
, match_opcode
, 0},
1919 {"vctz.v", 0, INSN_CLASS_ZVBB
, "Vd,VtVm", MATCH_VCTZ_V
, MASK_VCTZ_V
, match_opcode
, 0},
1920 {"vcpop.v", 0, INSN_CLASS_ZVBB
, "Vd,VtVm", MATCH_VCPOP_V
, MASK_VCPOP_V
, match_opcode
, 0},
1921 {"vrol.vv", 0, INSN_CLASS_ZVBB
, "Vd,Vt,VsVm", MATCH_VROL_VV
, MASK_VROL_VV
, match_opcode
, 0},
1922 {"vrol.vx", 0, INSN_CLASS_ZVBB
, "Vd,Vt,sVm", MATCH_VROL_VX
, MASK_VROL_VX
, match_opcode
, 0},
1923 {"vror.vv", 0, INSN_CLASS_ZVBB
, "Vd,Vt,VsVm", MATCH_VROR_VV
, MASK_VROR_VV
, match_opcode
, 0},
1924 {"vror.vx", 0, INSN_CLASS_ZVBB
, "Vd,Vt,sVm", MATCH_VROR_VX
, MASK_VROR_VX
, match_opcode
, 0},
1925 {"vror.vi", 0, INSN_CLASS_ZVBB
, "Vd,Vt,VlVm", MATCH_VROR_VI
, MASK_VROR_VI
, match_opcode
, 0},
1926 {"vwsll.vv", 0, INSN_CLASS_ZVBB
, "Vd,Vt,VsVm", MATCH_VWSLL_VV
, MASK_VWSLL_VV
, match_opcode
, 0},
1927 {"vwsll.vx", 0, INSN_CLASS_ZVBB
, "Vd,Vt,sVm", MATCH_VWSLL_VX
, MASK_VWSLL_VX
, match_opcode
, 0},
1928 {"vwsll.vi", 0, INSN_CLASS_ZVBB
, "Vd,Vt,VjVm", MATCH_VWSLL_VI
, MASK_VWSLL_VI
, match_opcode
, 0},
1930 /* Zvbc instructions. */
1931 {"vclmul.vv", 0, INSN_CLASS_ZVBC
, "Vd,Vt,VsVm", MATCH_VCLMUL_VV
, MASK_VCLMUL_VV
, match_opcode
, 0},
1932 {"vclmul.vx", 0, INSN_CLASS_ZVBC
, "Vd,Vt,sVm", MATCH_VCLMUL_VX
, MASK_VCLMUL_VX
, match_opcode
, 0},
1933 {"vclmulh.vv", 0, INSN_CLASS_ZVBC
, "Vd,Vt,VsVm", MATCH_VCLMULH_VV
, MASK_VCLMULH_VV
, match_opcode
, 0},
1934 {"vclmulh.vx", 0, INSN_CLASS_ZVBC
, "Vd,Vt,sVm", MATCH_VCLMULH_VX
, MASK_VCLMULH_VX
, match_opcode
, 0},
1936 /* Zvkg instructions. */
1937 {"vghsh.vv", 0, INSN_CLASS_ZVKG
, "Vd,Vt,Vs", MATCH_VGHSH_VV
, MASK_VGHSH_VV
, match_opcode
, 0},
1938 {"vgmul.vv", 0, INSN_CLASS_ZVKG
, "Vd,Vt", MATCH_VGMUL_VV
, MASK_VGMUL_VV
, match_opcode
, 0},
1940 /* Zvkned instructions. */
1941 {"vaesdf.vv", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESDF_VV
, MASK_VAESDF_VV
, match_opcode
, 0},
1942 {"vaesdf.vs", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESDF_VS
, MASK_VAESDF_VV
, match_opcode
, 0},
1943 {"vaesdm.vv", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESDM_VV
, MASK_VAESDM_VV
, match_opcode
, 0},
1944 {"vaesdm.vs", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESDM_VS
, MASK_VAESDM_VV
, match_opcode
, 0},
1945 {"vaesef.vv", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESEF_VV
, MASK_VAESEF_VV
, match_opcode
, 0},
1946 {"vaesef.vs", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESEF_VS
, MASK_VAESEF_VV
, match_opcode
, 0},
1947 {"vaesem.vv", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESEM_VV
, MASK_VAESEM_VV
, match_opcode
, 0},
1948 {"vaesem.vs", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESEM_VS
, MASK_VAESEM_VV
, match_opcode
, 0},
1949 {"vaeskf1.vi", 0, INSN_CLASS_ZVKNED
, "Vd,Vt,Vj", MATCH_VAESKF1_VI
, MASK_VAESKF1_VI
, match_opcode
, 0},
1950 {"vaeskf2.vi", 0, INSN_CLASS_ZVKNED
, "Vd,Vt,Vj", MATCH_VAESKF2_VI
, MASK_VAESKF2_VI
, match_opcode
, 0},
1951 {"vaesz.vs", 0, INSN_CLASS_ZVKNED
, "Vd,Vt", MATCH_VAESZ_VS
, MASK_VAESZ_VS
, match_opcode
, 0},
1953 /* Zvknh[a,b] instructions. */
1954 {"vsha2ch.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB
, "Vd,Vt,Vs", MATCH_VSHA2CH_VV
, MASK_VSHA2CH_VV
, match_opcode
, 0},
1955 {"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB
, "Vd,Vt,Vs", MATCH_VSHA2CL_VV
, MASK_VSHA2CL_VV
, match_opcode
, 0},
1956 {"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB
, "Vd,Vt,Vs", MATCH_VSHA2MS_VV
, MASK_VSHA2MS_VV
, match_opcode
, 0},
1958 /* Zvksed instructions. */
1959 {"vsm4k.vi", 0, INSN_CLASS_ZVKSED
, "Vd,Vt,Vj", MATCH_VSM4K_VI
, MASK_VSM4K_VI
, match_opcode
, 0},
1960 {"vsm4r.vv", 0, INSN_CLASS_ZVKSED
, "Vd,Vt", MATCH_VSM4R_VV
, MASK_VSM4R_VV
, match_opcode
, 0},
1961 {"vsm4r.vs", 0, INSN_CLASS_ZVKSED
, "Vd,Vt", MATCH_VSM4R_VS
, MASK_VSM4R_VS
, match_opcode
, 0},
1963 /* Zvksh instructions. */
1964 {"vsm3c.vi", 0, INSN_CLASS_ZVKSH
, "Vd,Vt,Vj", MATCH_VSM3C_VI
, MASK_VSM3C_VI
, match_opcode
, 0},
1965 {"vsm3me.vv", 0, INSN_CLASS_ZVKSH
, "Vd,Vt,Vs", MATCH_VSM3ME_VV
, MASK_VSM3ME_VV
, match_opcode
, 0},
1967 /* ZCB instructions. */
1968 {"c.lbu", 0, INSN_CLASS_ZCB
, "Ct,Wcb(Cs)", MATCH_C_LBU
, MASK_C_LBU
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
1969 {"c.lhu", 0, INSN_CLASS_ZCB
, "Ct,Wch(Cs)", MATCH_C_LHU
, MASK_C_LHU
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
1970 {"c.lh", 0, INSN_CLASS_ZCB
, "Ct,Wch(Cs)", MATCH_C_LH
, MASK_C_LH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
1971 {"c.sb", 0, INSN_CLASS_ZCB
, "Ct,Wcb(Cs)", MATCH_C_SB
, MASK_C_SB
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
1972 {"c.sh", 0, INSN_CLASS_ZCB
, "Ct,Wch(Cs)", MATCH_C_SH
, MASK_C_SH
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
1973 {"c.not", 0, INSN_CLASS_ZCB
, "Cs", MATCH_C_NOT
, MASK_C_NOT
, match_opcode
, 0 },
1974 {"c.mul", 0, INSN_CLASS_ZCB_AND_ZMMUL
, "Cs,Ct", MATCH_C_MUL
, MASK_C_MUL
, match_opcode
, 0 },
1975 {"c.sext.b", 0, INSN_CLASS_ZCB_AND_ZBB
, "Cs", MATCH_C_SEXT_B
, MASK_C_SEXT_B
, match_opcode
, 0 },
1976 {"c.sext.h", 0, INSN_CLASS_ZCB_AND_ZBB
, "Cs", MATCH_C_SEXT_H
, MASK_C_SEXT_H
, match_opcode
, 0 },
1977 {"c.zext.h", 0, INSN_CLASS_ZCB_AND_ZBB
, "Cs", MATCH_C_ZEXT_H
, MASK_C_ZEXT_H
, match_opcode
, 0 },
1978 {"c.zext.w", 64, INSN_CLASS_ZCB_AND_ZBA
, "Cs", MATCH_C_ZEXT_W
, MASK_C_ZEXT_W
, match_opcode
, 0 },
1979 {"c.zext.b", 0, INSN_CLASS_ZCB
, "Cs", MATCH_C_ZEXT_B
, MASK_C_ZEXT_B
, match_opcode
, 0 },
1980 {"c.sext.w", 64, INSN_CLASS_ZCB
, "d", MATCH_C_ADDIW
, MASK_C_ADDIW
|MASK_RVC_IMM
, match_rd_nonzero
, INSN_ALIAS
},
1982 /* Supervisor instructions. */
1983 {"csrr", 0, INSN_CLASS_ZICSR
, "d,E", MATCH_CSRRS
, MASK_CSRRS
|MASK_RS1
, match_opcode
, INSN_ALIAS
},
1984 {"csrwi", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRWI
, MASK_CSRRWI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1985 {"csrw", 0, INSN_CLASS_ZICSR
, "E,s", MATCH_CSRRW
, MASK_CSRRW
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1986 {"csrw", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRWI
, MASK_CSRRWI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1987 {"csrsi", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRSI
, MASK_CSRRSI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1988 {"csrs", 0, INSN_CLASS_ZICSR
, "E,s", MATCH_CSRRS
, MASK_CSRRS
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1989 {"csrs", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRSI
, MASK_CSRRSI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1990 {"csrci", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRCI
, MASK_CSRRCI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1991 {"csrc", 0, INSN_CLASS_ZICSR
, "E,s", MATCH_CSRRC
, MASK_CSRRC
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1992 {"csrc", 0, INSN_CLASS_ZICSR
, "E,Z", MATCH_CSRRCI
, MASK_CSRRCI
|MASK_RD
, match_opcode
, INSN_ALIAS
},
1993 {"csrrwi", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRWI
, MASK_CSRRWI
, match_opcode
, 0 },
1994 {"csrrw", 0, INSN_CLASS_ZICSR
, "d,E,s", MATCH_CSRRW
, MASK_CSRRW
, match_opcode
, 0 },
1995 {"csrrw", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRWI
, MASK_CSRRWI
, match_opcode
, INSN_ALIAS
},
1996 {"csrrsi", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRSI
, MASK_CSRRSI
, match_opcode
, 0 },
1997 {"csrrs", 0, INSN_CLASS_ZICSR
, "d,E,s", MATCH_CSRRS
, MASK_CSRRS
, match_opcode
, 0 },
1998 {"csrrs", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRSI
, MASK_CSRRSI
, match_opcode
, INSN_ALIAS
},
1999 {"csrrci", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRCI
, MASK_CSRRCI
, match_opcode
, 0 },
2000 {"csrrc", 0, INSN_CLASS_ZICSR
, "d,E,s", MATCH_CSRRC
, MASK_CSRRC
, match_opcode
, 0 },
2001 {"csrrc", 0, INSN_CLASS_ZICSR
, "d,E,Z", MATCH_CSRRCI
, MASK_CSRRCI
, match_opcode
, INSN_ALIAS
},
2002 {"uret", 0, INSN_CLASS_I
, "", MATCH_URET
, MASK_URET
, match_opcode
, 0 },
2003 {"sret", 0, INSN_CLASS_I
, "", MATCH_SRET
, MASK_SRET
, match_opcode
, 0 },
2004 {"hret", 0, INSN_CLASS_I
, "", MATCH_HRET
, MASK_HRET
, match_opcode
, 0 },
2005 {"mret", 0, INSN_CLASS_I
, "", MATCH_MRET
, MASK_MRET
, match_opcode
, 0 },
2006 {"dret", 0, INSN_CLASS_I
, "", MATCH_DRET
, MASK_DRET
, match_opcode
, 0 },
2007 {"sfence.vm", 0, INSN_CLASS_I
, "", MATCH_SFENCE_VM
, MASK_SFENCE_VM
| MASK_RS1
, match_opcode
, 0 },
2008 {"sfence.vm", 0, INSN_CLASS_I
, "s", MATCH_SFENCE_VM
, MASK_SFENCE_VM
, match_opcode
, 0 },
2009 {"sfence.vma", 0, INSN_CLASS_I
, "", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
|MASK_RS1
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
2010 {"sfence.vma", 0, INSN_CLASS_I
, "s", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
2011 {"sfence.vma", 0, INSN_CLASS_I
, "s,t", MATCH_SFENCE_VMA
, MASK_SFENCE_VMA
, match_opcode
, 0 },
2012 {"wfi", 0, INSN_CLASS_I
, "", MATCH_WFI
, MASK_WFI
, match_opcode
, 0 },
2014 /* Svinval instructions. */
2015 {"sinval.vma", 0, INSN_CLASS_SVINVAL
, "s,t", MATCH_SINVAL_VMA
, MASK_SINVAL_VMA
, match_opcode
, 0 },
2016 {"sfence.w.inval", 0, INSN_CLASS_SVINVAL
, "", MATCH_SFENCE_W_INVAL
, MASK_SFENCE_W_INVAL
, match_opcode
, 0 },
2017 {"sfence.inval.ir", 0, INSN_CLASS_SVINVAL
, "", MATCH_SFENCE_INVAL_IR
, MASK_SFENCE_INVAL_IR
, match_opcode
, 0 },
2018 {"hinval.vvma", 0, INSN_CLASS_SVINVAL
, "s,t", MATCH_HINVAL_VVMA
, MASK_HINVAL_VVMA
, match_opcode
, 0 },
2019 {"hinval.gvma", 0, INSN_CLASS_SVINVAL
, "s,t", MATCH_HINVAL_GVMA
, MASK_HINVAL_GVMA
, match_opcode
, 0 },
2021 /* Hypervisor instructions. */
2022 {"hfence.vvma", 0, INSN_CLASS_H
, "", MATCH_HFENCE_VVMA
, MASK_HFENCE_VVMA
|MASK_RS1
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
2023 {"hfence.vvma", 0, INSN_CLASS_H
, "s", MATCH_HFENCE_VVMA
, MASK_HFENCE_VVMA
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
2024 {"hfence.vvma", 0, INSN_CLASS_H
, "s,t", MATCH_HFENCE_VVMA
, MASK_HFENCE_VVMA
, match_opcode
, 0 },
2025 {"hfence.gvma", 0, INSN_CLASS_H
, "", MATCH_HFENCE_GVMA
, MASK_HFENCE_GVMA
|MASK_RS1
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
2026 {"hfence.gvma", 0, INSN_CLASS_H
, "s", MATCH_HFENCE_GVMA
, MASK_HFENCE_GVMA
|MASK_RS2
, match_opcode
, INSN_ALIAS
},
2027 {"hfence.gvma", 0, INSN_CLASS_H
, "s,t", MATCH_HFENCE_GVMA
, MASK_HFENCE_GVMA
, match_opcode
, 0 },
2028 {"hlv.b", 0, INSN_CLASS_H
, "d,0(s)", MATCH_HLV_B
, MASK_HLV_B
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
2029 {"hlv.bu", 0, INSN_CLASS_H
, "d,0(s)", MATCH_HLV_BU
, MASK_HLV_BU
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
2030 {"hlv.h", 0, INSN_CLASS_H
, "d,0(s)", MATCH_HLV_H
, MASK_HLV_H
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
2031 {"hlv.hu", 0, INSN_CLASS_H
, "d,0(s)", MATCH_HLV_HU
, MASK_HLV_HU
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
2032 {"hlvx.hu", 0, INSN_CLASS_H
, "d,0(s)", MATCH_HLVX_HU
, MASK_HLVX_HU
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
2033 {"hlv.w", 0, INSN_CLASS_H
, "d,0(s)", MATCH_HLV_W
, MASK_HLV_W
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
2034 {"hlv.wu", 64, INSN_CLASS_H
, "d,0(s)", MATCH_HLV_WU
, MASK_HLV_WU
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
2035 {"hlvx.wu", 0, INSN_CLASS_H
, "d,0(s)", MATCH_HLVX_WU
, MASK_HLVX_WU
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
2036 {"hlv.d", 64, INSN_CLASS_H
, "d,0(s)", MATCH_HLV_D
, MASK_HLV_D
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
2037 {"hsv.b", 0, INSN_CLASS_H
, "t,0(s)", MATCH_HSV_B
, MASK_HSV_B
, match_opcode
, INSN_DREF
|INSN_1_BYTE
},
2038 {"hsv.h", 0, INSN_CLASS_H
, "t,0(s)", MATCH_HSV_H
, MASK_HSV_H
, match_opcode
, INSN_DREF
|INSN_2_BYTE
},
2039 {"hsv.w", 0, INSN_CLASS_H
, "t,0(s)", MATCH_HSV_W
, MASK_HSV_W
, match_opcode
, INSN_DREF
|INSN_4_BYTE
},
2040 {"hsv.d", 64, INSN_CLASS_H
, "t,0(s)", MATCH_HSV_D
, MASK_HSV_D
, match_opcode
, INSN_DREF
|INSN_8_BYTE
},
2042 /* Vendor-specific (T-Head) XTheadBa instructions. */
2043 {"th.addsl", 0, INSN_CLASS_XTHEADBA
, "d,s,t,Xtu2@25", MATCH_TH_ADDSL
, MASK_TH_ADDSL
, match_opcode
, 0},
2045 /* Vendor-specific (T-Head) XTheadBb instructions. */
2046 {"th.srri", 0, INSN_CLASS_XTHEADBB
, "d,s,Xtu6@20", MATCH_TH_SRRI
, MASK_TH_SRRI
, match_opcode
, 0},
2047 {"th.srriw", 64, INSN_CLASS_XTHEADBB
, "d,s,Xtu5@20", MATCH_TH_SRRIW
, MASK_TH_SRRIW
, match_opcode
, 0},
2048 {"th.ext", 0, INSN_CLASS_XTHEADBB
, "d,s,Xtu6@26,Xtu6@20", MATCH_TH_EXT
, MASK_TH_EXT
, match_opcode
, 0},
2049 {"th.extu", 0, INSN_CLASS_XTHEADBB
, "d,s,Xtu6@26,Xtu6@20", MATCH_TH_EXTU
, MASK_TH_EXTU
, match_opcode
, 0},
2050 {"th.ff0", 0, INSN_CLASS_XTHEADBB
, "d,s", MATCH_TH_FF0
, MASK_TH_FF0
, match_opcode
, 0},
2051 {"th.ff1", 0, INSN_CLASS_XTHEADBB
, "d,s", MATCH_TH_FF1
, MASK_TH_FF1
, match_opcode
, 0},
2052 {"th.rev", 0, INSN_CLASS_XTHEADBB
, "d,s", MATCH_TH_REV
, MASK_TH_REV
, match_opcode
, 0},
2053 {"th.revw", 64, INSN_CLASS_XTHEADBB
, "d,s", MATCH_TH_REVW
, MASK_TH_REVW
, match_opcode
, 0},
2054 {"th.tstnbz", 0, INSN_CLASS_XTHEADBB
, "d,s", MATCH_TH_TSTNBZ
, MASK_TH_TSTNBZ
, match_opcode
, 0},
2056 /* Vendor-specific (T-Head) XTheadBs instructions. */
2057 {"th.tst", 0, INSN_CLASS_XTHEADBS
, "d,s,Xtu6@20", MATCH_TH_TST
, MASK_TH_TST
, match_opcode
, 0},
2059 /* Vendor-specific (T-Head) XTheadCmo instructions. */
2060 {"th.dcache.call", 0, INSN_CLASS_XTHEADCMO
, "", MATCH_TH_DCACHE_CALL
, MASK_TH_DCACHE_CALL
, match_opcode
, 0},
2061 {"th.dcache.ciall", 0, INSN_CLASS_XTHEADCMO
, "", MATCH_TH_DCACHE_CIALL
, MASK_TH_DCACHE_CIALL
, match_opcode
, 0},
2062 {"th.dcache.iall", 0, INSN_CLASS_XTHEADCMO
, "", MATCH_TH_DCACHE_IALL
, MASK_TH_DCACHE_IALL
, match_opcode
, 0},
2063 {"th.dcache.cpa", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_CPA
, MASK_TH_DCACHE_CPA
, match_opcode
, 0},
2064 {"th.dcache.cipa", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_CIPA
, MASK_TH_DCACHE_CIPA
, match_opcode
, 0},
2065 {"th.dcache.ipa", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_IPA
, MASK_TH_DCACHE_IPA
, match_opcode
, 0},
2066 {"th.dcache.cva", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_CVA
, MASK_TH_DCACHE_CVA
, match_opcode
, 0},
2067 {"th.dcache.civa", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_CIVA
, MASK_TH_DCACHE_CIVA
, match_opcode
, 0},
2068 {"th.dcache.iva", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_IVA
, MASK_TH_DCACHE_IVA
, match_opcode
, 0},
2069 {"th.dcache.csw", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_CSW
, MASK_TH_DCACHE_CSW
, match_opcode
, 0},
2070 {"th.dcache.cisw", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_CISW
, MASK_TH_DCACHE_CISW
, match_opcode
, 0},
2071 {"th.dcache.isw", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_ISW
, MASK_TH_DCACHE_ISW
, match_opcode
, 0},
2072 {"th.dcache.cpal1", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_CPAL1
, MASK_TH_DCACHE_CPAL1
, match_opcode
, 0},
2073 {"th.dcache.cval1", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_DCACHE_CVAL1
, MASK_TH_DCACHE_CVAL1
, match_opcode
, 0},
2075 {"th.icache.iall", 0, INSN_CLASS_XTHEADCMO
, "", MATCH_TH_ICACHE_IALL
, MASK_TH_ICACHE_IALL
, match_opcode
, 0},
2076 {"th.icache.ialls", 0, INSN_CLASS_XTHEADCMO
, "", MATCH_TH_ICACHE_IALLS
, MASK_TH_ICACHE_IALLS
, match_opcode
, 0},
2077 {"th.icache.ipa", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_ICACHE_IPA
, MASK_TH_ICACHE_IPA
, match_opcode
, 0},
2078 {"th.icache.iva", 0, INSN_CLASS_XTHEADCMO
, "s", MATCH_TH_ICACHE_IVA
, MASK_TH_ICACHE_IVA
, match_opcode
, 0},
2080 {"th.l2cache.call", 0, INSN_CLASS_XTHEADCMO
, "", MATCH_TH_L2CACHE_CALL
, MASK_TH_L2CACHE_CALL
, match_opcode
, 0},
2081 {"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO
, "", MATCH_TH_L2CACHE_CIALL
, MASK_TH_L2CACHE_CIALL
, match_opcode
, 0},
2082 {"th.l2cache.iall", 0, INSN_CLASS_XTHEADCMO
, "", MATCH_TH_L2CACHE_IALL
, MASK_TH_L2CACHE_IALL
, match_opcode
, 0},
2084 /* Vendor-specific (T-Head) XTheadCondMov instructions. */
2085 {"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV
, "d,s,t", MATCH_TH_MVEQZ
, MASK_TH_MVEQZ
, match_opcode
, 0},
2086 {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV
, "d,s,t", MATCH_TH_MVNEZ
, MASK_TH_MVNEZ
, match_opcode
, 0},
2088 /* Vendor-specific (T-Head) XTheadFMemIdx instructions. */
2089 {"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX
, "D,s,t,Xtu2@25", MATCH_TH_FLRD
, MASK_TH_FLRD
, match_opcode
, 0},
2090 {"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX
, "D,s,t,Xtu2@25", MATCH_TH_FLRW
, MASK_TH_FLRW
, match_opcode
, 0},
2091 {"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX
, "D,s,t,Xtu2@25", MATCH_TH_FLURD
, MASK_TH_FLURD
, match_opcode
, 0},
2092 {"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX
, "D,s,t,Xtu2@25", MATCH_TH_FLURW
, MASK_TH_FLURW
, match_opcode
, 0},
2093 {"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX
, "D,s,t,Xtu2@25", MATCH_TH_FSRD
, MASK_TH_FSRD
, match_opcode
, 0},
2094 {"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX
, "D,s,t,Xtu2@25", MATCH_TH_FSRW
, MASK_TH_FSRW
, match_opcode
, 0},
2095 {"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX
, "D,s,t,Xtu2@25", MATCH_TH_FSURD
, MASK_TH_FSURD
, match_opcode
, 0},
2096 {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX
, "D,s,t,Xtu2@25", MATCH_TH_FSURW
, MASK_TH_FSURW
, match_opcode
, 0},
2098 /* Vendor-specific (T-Head) XTheadFmv instructions. */
2099 {"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV
, "d,S", MATCH_TH_FMV_HW_X
, MASK_TH_FMV_HW_X
, match_opcode
, 0},
2100 {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV
, "d,S", MATCH_TH_FMV_X_HW
, MASK_TH_FMV_X_HW
, match_opcode
, 0},
2102 /* Vendor-specific (T-Head) XTheadInt instructions. */
2103 {"th.ipop", 0, INSN_CLASS_XTHEADINT
, "", MATCH_TH_IPOP
, MASK_TH_IPOP
, match_opcode
, 0},
2104 {"th.ipush", 0, INSN_CLASS_XTHEADINT
, "", MATCH_TH_IPUSH
, MASK_TH_IPUSH
, match_opcode
, 0},
2106 /* Vendor-specific (T-Head) XTheadMemIdx instructions. */
2107 {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIA
, MASK_TH_LDIA
, match_th_load_inc
, 0},
2108 {"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LDIB
, MASK_TH_LDIB
, match_th_load_inc
, 0},
2109 {"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIA
, MASK_TH_LWIA
, match_th_load_inc
, 0},
2110 {"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWIB
, MASK_TH_LWIB
, match_th_load_inc
, 0},
2111 {"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIA
, MASK_TH_LWUIA
, match_th_load_inc
, 0},
2112 {"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LWUIB
, MASK_TH_LWUIB
, match_th_load_inc
, 0},
2113 {"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIA
, MASK_TH_LHIA
, match_th_load_inc
, 0},
2114 {"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHIB
, MASK_TH_LHIB
, match_th_load_inc
, 0},
2115 {"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIA
, MASK_TH_LHUIA
, match_th_load_inc
, 0},
2116 {"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LHUIB
, MASK_TH_LHUIB
, match_th_load_inc
, 0},
2117 {"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIA
, MASK_TH_LBIA
, match_th_load_inc
, 0},
2118 {"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBIB
, MASK_TH_LBIB
, match_th_load_inc
, 0},
2119 {"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIA
, MASK_TH_LBUIA
, match_th_load_inc
, 0},
2120 {"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_LBUIB
, MASK_TH_LBUIB
, match_th_load_inc
, 0},
2121 {"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIA
, MASK_TH_SDIA
, match_opcode
, 0},
2122 {"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SDIB
, MASK_TH_SDIB
, match_opcode
, 0},
2123 {"th.swia", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIA
, MASK_TH_SWIA
, match_opcode
, 0},
2124 {"th.swib", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SWIB
, MASK_TH_SWIB
, match_opcode
, 0},
2125 {"th.shia", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIA
, MASK_TH_SHIA
, match_opcode
, 0},
2126 {"th.shib", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SHIB
, MASK_TH_SHIB
, match_opcode
, 0},
2127 {"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIA
, MASK_TH_SBIA
, match_opcode
, 0},
2128 {"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX
, "d,(s),Xts5@20,Xtu2@25", MATCH_TH_SBIB
, MASK_TH_SBIB
, match_opcode
, 0},
2130 {"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LRD
, MASK_TH_LRD
, match_opcode
, 0},
2131 {"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LRW
, MASK_TH_LRW
, match_opcode
, 0},
2132 {"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LRWU
, MASK_TH_LRWU
, match_opcode
, 0},
2133 {"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LRH
, MASK_TH_LRH
, match_opcode
, 0},
2134 {"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LRHU
, MASK_TH_LRHU
, match_opcode
, 0},
2135 {"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LRB
, MASK_TH_LRB
, match_opcode
, 0},
2136 {"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LRBU
, MASK_TH_LRBU
, match_opcode
, 0},
2137 {"th.srd", 64, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_SRD
, MASK_TH_SRD
, match_opcode
, 0},
2138 {"th.srw", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_SRW
, MASK_TH_SRW
, match_opcode
, 0},
2139 {"th.srh", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_SRH
, MASK_TH_SRH
, match_opcode
, 0},
2140 {"th.srb", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_SRB
, MASK_TH_SRB
, match_opcode
, 0},
2142 {"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LURD
, MASK_TH_LURD
, match_opcode
, 0},
2143 {"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LURW
, MASK_TH_LURW
, match_opcode
, 0},
2144 {"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LURWU
, MASK_TH_LURWU
, match_opcode
, 0},
2145 {"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LURH
, MASK_TH_LURH
, match_opcode
, 0},
2146 {"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LURHU
, MASK_TH_LURHU
, match_opcode
, 0},
2147 {"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LURB
, MASK_TH_LURB
, match_opcode
, 0},
2148 {"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_LURBU
, MASK_TH_LURBU
, match_opcode
, 0},
2149 {"th.surd", 64, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_SURD
, MASK_TH_SURD
, match_opcode
, 0},
2150 {"th.surw", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_SURW
, MASK_TH_SURW
, match_opcode
, 0},
2151 {"th.surh", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_SURH
, MASK_TH_SURH
, match_opcode
, 0},
2152 {"th.surb", 0, INSN_CLASS_XTHEADMEMIDX
, "d,s,t,Xtu2@25", MATCH_TH_SURB
, MASK_TH_SURB
, match_opcode
, 0},
2154 /* Vendor-specific (T-Head) XTheadMemPair instructions. */
2155 {"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR
, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_LDD
, MASK_TH_LDD
, match_th_load_pair
, 0},
2156 {"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR
, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWD
, MASK_TH_LWD
, match_th_load_pair
, 0},
2157 {"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR
, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_LWUD
, MASK_TH_LWUD
, match_th_load_pair
, 0},
2158 {"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR
, "d,t,(s),Xtu2@25,Xtl4", MATCH_TH_SDD
, MASK_TH_SDD
, match_opcode
, 0},
2159 {"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR
, "d,t,(s),Xtu2@25,Xtl3", MATCH_TH_SWD
, MASK_TH_SWD
, match_opcode
, 0},
2161 /* Vendor-specific (T-Head) XTheadMac instructions. */
2162 {"th.mula", 0, INSN_CLASS_XTHEADMAC
, "d,s,t", MATCH_TH_MULA
, MASK_TH_MULA
, match_opcode
, 0},
2163 {"th.mulah", 0, INSN_CLASS_XTHEADMAC
, "d,s,t", MATCH_TH_MULAH
, MASK_TH_MULAH
, match_opcode
, 0},
2164 {"th.mulaw", 64, INSN_CLASS_XTHEADMAC
, "d,s,t", MATCH_TH_MULAW
, MASK_TH_MULAW
, match_opcode
, 0},
2165 {"th.muls", 0, INSN_CLASS_XTHEADMAC
, "d,s,t", MATCH_TH_MULS
, MASK_TH_MULS
, match_opcode
, 0},
2166 {"th.mulsh", 0, INSN_CLASS_XTHEADMAC
, "d,s,t", MATCH_TH_MULSH
, MASK_TH_MULSH
, match_opcode
, 0},
2167 {"th.mulsw", 64, INSN_CLASS_XTHEADMAC
, "d,s,t", MATCH_TH_MULSW
, MASK_TH_MULSW
, match_opcode
, 0},
2169 /* Vendor-specific (T-Head) XTheadSync instructions. */
2170 {"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC
, "s,t",MATCH_TH_SFENCE_VMAS
, MASK_TH_SFENCE_VMAS
, match_opcode
, 0},
2171 {"th.sync", 0, INSN_CLASS_XTHEADSYNC
, "", MATCH_TH_SYNC
, MASK_TH_SYNC
, match_opcode
, 0},
2172 {"th.sync.i", 0, INSN_CLASS_XTHEADSYNC
, "", MATCH_TH_SYNC_I
, MASK_TH_SYNC_I
, match_opcode
, 0},
2173 {"th.sync.is", 0, INSN_CLASS_XTHEADSYNC
, "", MATCH_TH_SYNC_IS
, MASK_TH_SYNC_IS
, match_opcode
, 0},
2174 {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC
, "", MATCH_TH_SYNC_S
, MASK_TH_SYNC_S
, match_opcode
, 0},
2176 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
2177 {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS
, "d,s,t", MATCH_VT_MASKC
, MASK_VT_MASKC
, match_opcode
, 0 },
2178 {"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS
, "d,s,t", MATCH_VT_MASKCN
, MASK_VT_MASKCN
, match_opcode
, 0 },
2180 /* Terminate the list. */
2181 {0, 0, INSN_CLASS_NONE
, 0, 0, 0, 0, 0}
2184 /* Instruction format for .insn directive. */
2185 const struct riscv_opcode riscv_insn_types
[] =
2187 /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
2188 {"r", 0, INSN_CLASS_I
, "O4,F3,F7,d,s,t", 0, 0, match_opcode
, 0 },
2189 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,s,t", 0, 0, match_opcode
, 0 },
2190 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,S,t", 0, 0, match_opcode
, 0 },
2191 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,S,t", 0, 0, match_opcode
, 0 },
2192 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,s,T", 0, 0, match_opcode
, 0 },
2193 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,s,T", 0, 0, match_opcode
, 0 },
2194 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,d,S,T", 0, 0, match_opcode
, 0 },
2195 {"r", 0, INSN_CLASS_F
, "O4,F3,F7,D,S,T", 0, 0, match_opcode
, 0 },
2196 {"r", 0, INSN_CLASS_I
, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode
, 0 },
2197 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode
, 0 },
2198 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode
, 0 },
2199 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode
, 0 },
2200 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode
, 0 },
2201 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode
, 0 },
2202 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode
, 0 },
2203 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode
, 0 },
2204 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode
, 0 },
2205 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode
, 0 },
2206 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode
, 0 },
2207 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode
, 0 },
2208 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode
, 0 },
2209 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode
, 0 },
2210 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode
, 0 },
2211 {"r", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode
, 0 },
2213 {"r4", 0, INSN_CLASS_I
, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode
, 0 },
2214 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode
, 0 },
2215 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode
, 0 },
2216 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode
, 0 },
2217 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode
, 0 },
2218 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode
, 0 },
2219 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode
, 0 },
2220 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode
, 0 },
2221 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode
, 0 },
2222 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode
, 0 },
2223 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode
, 0 },
2224 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode
, 0 },
2225 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode
, 0 },
2226 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode
, 0 },
2227 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode
, 0 },
2228 {"r4", 0, INSN_CLASS_F
, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode
, 0 },
2230 {"i", 0, INSN_CLASS_I
, "O4,F3,d,s,j", 0, 0, match_opcode
, 0 },
2231 {"i", 0, INSN_CLASS_F
, "O4,F3,D,s,j", 0, 0, match_opcode
, 0 },
2232 {"i", 0, INSN_CLASS_F
, "O4,F3,d,S,j", 0, 0, match_opcode
, 0 },
2233 {"i", 0, INSN_CLASS_F
, "O4,F3,D,S,j", 0, 0, match_opcode
, 0 },
2234 {"i", 0, INSN_CLASS_I
, "O4,F3,d,o(s)", 0, 0, match_opcode
, 0 },
2235 {"i", 0, INSN_CLASS_F
, "O4,F3,D,o(s)", 0, 0, match_opcode
, 0 },
2237 {"s", 0, INSN_CLASS_I
, "O4,F3,t,q(s)", 0, 0, match_opcode
, 0 },
2238 {"s", 0, INSN_CLASS_F
, "O4,F3,T,q(s)", 0, 0, match_opcode
, 0 },
2240 {"sb", 0, INSN_CLASS_I
, "O4,F3,s,t,p", 0, 0, match_opcode
, 0 },
2241 {"sb", 0, INSN_CLASS_F
, "O4,F3,S,t,p", 0, 0, match_opcode
, 0 },
2242 {"sb", 0, INSN_CLASS_F
, "O4,F3,s,T,p", 0, 0, match_opcode
, 0 },
2243 {"sb", 0, INSN_CLASS_F
, "O4,F3,S,T,p", 0, 0, match_opcode
, 0 },
2244 {"b", 0, INSN_CLASS_I
, "O4,F3,s,t,p", 0, 0, match_opcode
, 0 },
2245 {"b", 0, INSN_CLASS_F
, "O4,F3,S,t,p", 0, 0, match_opcode
, 0 },
2246 {"b", 0, INSN_CLASS_F
, "O4,F3,s,T,p", 0, 0, match_opcode
, 0 },
2247 {"b", 0, INSN_CLASS_F
, "O4,F3,S,T,p", 0, 0, match_opcode
, 0 },
2249 {"u", 0, INSN_CLASS_I
, "O4,d,u", 0, 0, match_opcode
, 0 },
2250 {"u", 0, INSN_CLASS_F
, "O4,D,u", 0, 0, match_opcode
, 0 },
2252 {"uj", 0, INSN_CLASS_I
, "O4,d,a", 0, 0, match_opcode
, 0 },
2253 {"uj", 0, INSN_CLASS_F
, "O4,D,a", 0, 0, match_opcode
, 0 },
2254 {"j", 0, INSN_CLASS_I
, "O4,d,a", 0, 0, match_opcode
, 0 },
2255 {"j", 0, INSN_CLASS_F
, "O4,D,a", 0, 0, match_opcode
, 0 },
2257 {"cr", 0, INSN_CLASS_C
, "O2,CF4,d,CV", 0, 0, match_opcode
, 0 },
2258 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,D,CV", 0, 0, match_opcode
, 0 },
2259 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,d,CT", 0, 0, match_opcode
, 0 },
2260 {"cr", 0, INSN_CLASS_F_AND_C
, "O2,CF4,D,CT", 0, 0, match_opcode
, 0 },
2262 {"ci", 0, INSN_CLASS_C
, "O2,CF3,d,Co", 0, 0, match_opcode
, 0 },
2263 {"ci", 0, INSN_CLASS_F_AND_C
, "O2,CF3,D,Co", 0, 0, match_opcode
, 0 },
2265 {"ciw", 0, INSN_CLASS_C
, "O2,CF3,Ct,C8", 0, 0, match_opcode
, 0 },
2266 {"ciw", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CD,C8", 0, 0, match_opcode
, 0 },
2268 {"css", 0, INSN_CLASS_C
, "O2,CF3,CV,C6", 0, 0, match_opcode
, 0 },
2269 {"css", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CT,C6", 0, 0, match_opcode
, 0 },
2271 {"cl", 0, INSN_CLASS_C
, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode
, 0 },
2272 {"cl", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode
, 0 },
2273 {"cl", 0, INSN_CLASS_F_AND_C
, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode
, 0 },
2274 {"cl", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode
, 0 },
2276 {"cs", 0, INSN_CLASS_C
, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode
, 0 },
2277 {"cs", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode
, 0 },
2278 {"cs", 0, INSN_CLASS_F_AND_C
, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode
, 0 },
2279 {"cs", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode
, 0 },
2281 {"ca", 0, INSN_CLASS_C
, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode
, 0 },
2282 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode
, 0 },
2283 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode
, 0 },
2284 {"ca", 0, INSN_CLASS_F_AND_C
, "O2,CF6,CF2,CS,CD", 0, 0, match_opcode
, 0 },
2286 {"cb", 0, INSN_CLASS_C
, "O2,CF3,Cs,Cp", 0, 0, match_opcode
, 0 },
2287 {"cb", 0, INSN_CLASS_F_AND_C
, "O2,CF3,CS,Cp", 0, 0, match_opcode
, 0 },
2289 {"cj", 0, INSN_CLASS_C
, "O2,CF3,Ca", 0, 0, match_opcode
, 0 },
2291 /* Terminate the list. */
2292 {0, 0, INSN_CLASS_NONE
, 0, 0, 0, 0, 0}