1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2023 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep this sorted alphanumerically and synced with the fields array
30 enum aarch64_field_kind
213 /* Field description. */
220 typedef struct aarch64_field aarch64_field
;
222 extern const aarch64_field fields
[];
224 /* Operand description. */
226 struct aarch64_operand
228 enum aarch64_operand_class op_class
;
230 /* Name of the operand code; used mainly for the purpose of internal
236 /* The associated instruction bit-fields; no operand has more than 4
238 enum aarch64_field_kind fields
[5];
240 /* Brief description */
244 typedef struct aarch64_operand aarch64_operand
;
246 extern const aarch64_operand aarch64_operands
[];
249 verify_constraints (const struct aarch64_inst
*, const aarch64_insn
, bfd_vma
,
250 bool, aarch64_operand_error
*, aarch64_instr_sequence
*);
254 #define OPD_F_HAS_INSERTER 0x00000001
255 #define OPD_F_HAS_EXTRACTOR 0x00000002
256 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
257 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
258 value by 2 to get the value
259 of an immediate operand. */
260 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
261 #define OPD_F_OD_MASK 0x000001e0 /* Operand-dependent data. */
262 #define OPD_F_OD_LSB 5
263 #define OPD_F_NO_ZR 0x00000200 /* ZR index not allowed. */
264 #define OPD_F_SHIFT_BY_3 0x00000400 /* Need to left shift the field
265 value by 3 to get the value
266 of an immediate operand. */
267 #define OPD_F_SHIFT_BY_4 0x00000800 /* Need to left shift the field
268 value by 4 to get the value
269 of an immediate operand. */
272 /* Register flags. */
275 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */
278 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
281 #define F_HASXT (1 << 2) /* System instruction register <Xt>
285 #define F_REG_READ (1 << 3) /* Register can only be used to read values
289 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
293 #define F_REG_IN_CRM (1 << 5) /* Register extra encoding in CRm. */
296 #define F_REG_ALIAS (1 << 6) /* Register name aliases another. */
298 /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
299 Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
300 In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
301 macros to encode and decode CRm encoding.
303 #define PSTATE_ENCODE_CRM(val) (val << 6)
304 #define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f)
307 #define F_IMM_IN_CRM (1 << 10) /* Immediate extra encoding in CRm. */
309 /* Also CRm may contain, in addition to <pstatefield> immediate.
310 E.g. CRm[0] <imm1> at bit 0 for SME. Use below macros to encode and decode
313 #define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11)
314 #define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f)
316 /* Helper macro to ENCODE CRm and its immediate. */
317 #define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \
318 (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \
319 | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK))
321 /* Bits [15, 18] contain the maximum value for an immediate MSR. */
322 #define F_REG_MAX_VALUE(X) ((X) << 15)
323 #define F_GET_REG_MAX_VALUE(X) (((X) >> 15) & 0x0f)
325 /* HINT operand flags. */
326 #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
328 /* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
329 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
330 #define HINT_FLAG(val) (val >> 8)
331 #define HINT_VAL(val) (val & 0xff)
334 operand_has_inserter (const aarch64_operand
*operand
)
336 return (operand
->flags
& OPD_F_HAS_INSERTER
) != 0;
340 operand_has_extractor (const aarch64_operand
*operand
)
342 return (operand
->flags
& OPD_F_HAS_EXTRACTOR
) != 0;
346 operand_need_sign_extension (const aarch64_operand
*operand
)
348 return (operand
->flags
& OPD_F_SEXT
) != 0;
352 operand_need_shift_by_two (const aarch64_operand
*operand
)
354 return (operand
->flags
& OPD_F_SHIFT_BY_2
) != 0;
358 operand_need_shift_by_three (const aarch64_operand
*operand
)
360 return (operand
->flags
& OPD_F_SHIFT_BY_3
) != 0;
364 operand_need_shift_by_four (const aarch64_operand
*operand
)
366 return (operand
->flags
& OPD_F_SHIFT_BY_4
) != 0;
370 operand_maybe_stack_pointer (const aarch64_operand
*operand
)
372 return (operand
->flags
& OPD_F_MAYBE_SP
) != 0;
375 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
376 static inline unsigned int
377 get_operand_specific_data (const aarch64_operand
*operand
)
379 return (operand
->flags
& OPD_F_OD_MASK
) >> OPD_F_OD_LSB
;
382 /* Return the width of field number N of operand *OPERAND. */
383 static inline unsigned
384 get_operand_field_width (const aarch64_operand
*operand
, unsigned n
)
386 assert (operand
->fields
[n
] != FLD_NIL
);
387 return fields
[operand
->fields
[n
]].width
;
390 /* Return the total width of the operand *OPERAND. */
391 static inline unsigned
392 get_operand_fields_width (const aarch64_operand
*operand
)
396 while (operand
->fields
[i
] != FLD_NIL
)
397 width
+= fields
[operand
->fields
[i
++]].width
;
398 assert (width
> 0 && width
< 32);
402 static inline const aarch64_operand
*
403 get_operand_from_code (enum aarch64_opnd code
)
405 return aarch64_operands
+ code
;
408 /* Operand qualifier and operand constraint checking. */
410 int aarch64_match_operands_constraint (aarch64_inst
*,
411 aarch64_operand_error
*);
413 /* Operand qualifier related functions. */
414 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t
);
415 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t
);
416 aarch64_insn
aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t
);
417 int aarch64_find_best_match (const aarch64_inst
*,
418 const aarch64_opnd_qualifier_seq_t
*,
419 int, aarch64_opnd_qualifier_t
*, int *);
422 reset_operand_qualifier (aarch64_inst
*inst
, int idx
)
424 assert (idx
>=0 && idx
< aarch64_num_of_operands (inst
->opcode
));
425 inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
428 /* Inline functions operating on instruction bit-field(s). */
430 /* Generate a mask that has WIDTH number of consecutive 1s. */
432 static inline aarch64_insn
435 return ((aarch64_insn
) 1 << width
) - 1;
438 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
440 gen_sub_field (enum aarch64_field_kind kind
, int lsb_rel
, int width
, aarch64_field
*ret
)
442 const aarch64_field
*field
= &fields
[kind
];
443 if (lsb_rel
< 0 || width
<= 0 || lsb_rel
+ width
> field
->width
)
445 ret
->lsb
= field
->lsb
+ lsb_rel
;
450 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
454 insert_field_2 (const aarch64_field
*field
, aarch64_insn
*code
,
455 aarch64_insn value
, aarch64_insn mask
)
457 assert (field
->width
< 32 && field
->width
>= 1 && field
->lsb
>= 0
458 && field
->lsb
+ field
->width
<= 32);
459 value
&= gen_mask (field
->width
);
460 value
<<= field
->lsb
;
461 /* In some opcodes, field can be part of the base opcode, e.g. the size
462 field in FADD. The following helps avoid corrupt the base opcode. */
467 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
468 mask of the opcode. */
470 static inline aarch64_insn
471 extract_field_2 (const aarch64_field
*field
, aarch64_insn code
,
475 /* Clear any bit that is a part of the base opcode. */
477 value
= (code
>> field
->lsb
) & gen_mask (field
->width
);
481 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
485 insert_field (enum aarch64_field_kind kind
, aarch64_insn
*code
,
486 aarch64_insn value
, aarch64_insn mask
)
488 insert_field_2 (&fields
[kind
], code
, value
, mask
);
491 /* Extract field KIND of CODE and return the value. MASK can be zero or the
492 base mask of the opcode. */
494 static inline aarch64_insn
495 extract_field (enum aarch64_field_kind kind
, aarch64_insn code
,
498 return extract_field_2 (&fields
[kind
], code
, mask
);
502 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...);
504 /* Inline functions selecting operand to do the encoding/decoding for a
505 certain instruction bit-field. */
507 /* Select the operand to do the encoding/decoding of the 'sf' field.
508 The heuristic-based rule is that the result operand is respected more. */
511 select_operand_for_sf_field_coding (const aarch64_opcode
*opcode
)
514 if (aarch64_get_operand_class (opcode
->operands
[0])
515 == AARCH64_OPND_CLASS_INT_REG
)
518 else if (aarch64_get_operand_class (opcode
->operands
[1])
519 == AARCH64_OPND_CLASS_INT_REG
)
520 /* e.g. float2fix. */
523 { assert (0); abort (); }
527 /* Select the operand to do the encoding/decoding of the 'type' field in
528 the floating-point instructions.
529 The heuristic-based rule is that the source operand is respected more. */
532 select_operand_for_fptype_field_coding (const aarch64_opcode
*opcode
)
535 if (aarch64_get_operand_class (opcode
->operands
[1])
536 == AARCH64_OPND_CLASS_FP_REG
)
539 else if (aarch64_get_operand_class (opcode
->operands
[0])
540 == AARCH64_OPND_CLASS_FP_REG
)
541 /* e.g. float2fix. */
544 { assert (0); abort (); }
548 /* Select the operand to do the encoding/decoding of the 'size' field in
549 the AdvSIMD scalar instructions.
550 The heuristic-based rule is that the destination operand is respected
554 select_operand_for_scalar_size_field_coding (const aarch64_opcode
*opcode
)
556 int src_size
= 0, dst_size
= 0;
557 if (aarch64_get_operand_class (opcode
->operands
[0])
558 == AARCH64_OPND_CLASS_SISD_REG
)
559 dst_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][0]);
560 if (aarch64_get_operand_class (opcode
->operands
[1])
561 == AARCH64_OPND_CLASS_SISD_REG
)
562 src_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][1]);
563 if (src_size
== dst_size
&& src_size
== 0)
564 { assert (0); abort (); }
565 /* When the result is not a sisd register or it is a long operantion. */
566 if (dst_size
== 0 || dst_size
== src_size
<< 1)
572 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
573 the AdvSIMD instructions. */
575 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode
*);
579 aarch64_insn
aarch64_get_operand_modifier_value (enum aarch64_modifier_kind
);
580 enum aarch64_modifier_kind
581 aarch64_get_operand_modifier_from_value (aarch64_insn
, bool);
584 bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
585 bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn
*);
586 int aarch64_shrink_expanded_imm8 (uint64_t);
588 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
590 copy_operand_info (aarch64_inst
*inst
, int dst
, int src
)
592 assert (dst
>= 0 && src
>= 0 && dst
< AARCH64_MAX_OPND_NUM
593 && src
< AARCH64_MAX_OPND_NUM
);
594 memcpy (&inst
->operands
[dst
], &inst
->operands
[src
],
595 sizeof (aarch64_opnd_info
));
596 inst
->operands
[dst
].idx
= dst
;
599 /* A primitive log caculator. */
601 static inline unsigned int
602 get_logsz (unsigned int size
)
604 const unsigned char ls
[16] =
605 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
611 assert (ls
[size
- 1] != (unsigned char)-1);
615 #endif /* OPCODES_AARCH64_OPC_H */