sim/arm/armos.c

   1 /*  armos.c -- ARMulator OS interface:  ARM6 Instruction Emulator.
   2     Copyright (C) 1994 Advanced RISC Machines Ltd.
   3
   4     This program is free software; you can redistribute it and/or modify
   5     it under the terms of the GNU General Public License as published by
   6     the Free Software Foundation; either version 3 of the License, or
   7     (at your option) any later version.
   8
   9     This program is distributed in the hope that it will be useful,
  10     but WITHOUT ANY WARRANTY; without even the implied warranty of
  11     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12     GNU General Public License for more details.
  13
  14     You should have received a copy of the GNU General Public License
  15     along with this program; if not, see <http://www.gnu.org/licenses/>. */
  16
  17 /* This file contains a model of Demon, ARM Ltd's Debug Monitor,
  18    including all the SWI's required to support the C library. The code in
  19    it is not really for the faint-hearted (especially the abort handling
  20    code), but it is a complete example. Defining NOOS will disable all the
  21    fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
  22    0x11 to halt the emulator.  */
  23
  24 /* This must come before any other includes.  */
  25 #include "defs.h"
  26
  27 #include "ansidecl.h"
  28 #include "libiberty.h"
  29
  30 #include <time.h>
  31 #include <errno.h>
  32 #include <limits.h>
  33 #include <string.h>
  34 #include <unistd.h>             /* For SEEK_SET etc.  */
  35
  36 #include "armdefs.h"
  37 #include "armos.h"
  38 #include "armemu.h"
  39
  40 #ifndef NOOS
  41 #ifndef VALIDATE
  42 /* #ifndef ASIM */
  43 #include "armfpe.h"
  44 /* #endif */
  45 #endif
  46 #endif
  47
  48 /* For RDIError_BreakpointReached.  */
  49 #include "dbg_rdi.h"
  50
  51 #include "sim/callback.h"
  52 extern host_callback *sim_callback;
  53
  54 extern unsigned ARMul_OSInit       (ARMul_State *);
  55 extern unsigned ARMul_OSHandleSWI  (ARMul_State *, ARMword);
  56
  57 #ifndef FOPEN_MAX
  58 #define FOPEN_MAX 64
  59 #endif
  60 #ifndef PATH_MAX
  61 #define PATH_MAX 1024
  62 #endif
  63
  64 /* OS private Information.  */
  65
  66 struct OSblock
  67 {
  68   ARMword ErrorNo;
  69 };
  70
  71 /* Bit mask of enabled SWI implementations.  */
  72 unsigned int swi_mask = -1;
  73
  74
  75 static ARMword softvectorcode[] =
  76 {
  77   /* Installed instructions:
  78        swi    tidyexception + event;
  79        mov    lr, pc;
  80        ldmia  fp, {fp, pc};
  81        swi    generateexception  + event.  */
  82   0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
  83   0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
  84   0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */
  85   0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */
  86   0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */
  87   0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */
  88   0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */
  89   0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */
  90   0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */
  91   0xe1a0f00e                    /* Default handler */
  92 };
  93
  94 /* Time for the Operating System to initialise itself.  */
  95
  96 unsigned
  97 ARMul_OSInit (ARMul_State * state)
  98 {
  99 #ifndef NOOS
 100 #ifndef VALIDATE
 101   ARMword instr, i, j;
 102
 103   if (state->OSptr == NULL)
 104     {
 105       state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock));
 106       if (state->OSptr == NULL)
 107         {
 108           perror ("OS Memory");
 109           exit (15);
 110         }
 111     }
 112
 113   state->Reg[13] = ADDRSUPERSTACK;                      /* Set up a stack for the current mode...  */
 114   ARMul_SetReg (state, SVC32MODE,   13, ADDRSUPERSTACK);/* ...and for supervisor mode...  */
 115   ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode...  */
 116   ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode...  */
 117   ARMul_SetReg (state, SYSTEMMODE,  13, ADDRSUPERSTACK);/* ...and for system mode.  */
 118   instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8);           /* Load pc from soft vector */
 119
 120   for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
 121     /* Write hardware vectors.  */
 122     ARMul_WriteWord (state, i, instr);
 123
 124   SWI_vector_installed = 0;
 125
 126   for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4)
 127     {
 128       ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
 129       ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L,
 130                        SOFTVECTORCODE + sizeof (softvectorcode) - 4L);
 131     }
 132
 133   for (i = 0; i < sizeof (softvectorcode); i += 4)
 134     ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]);
 135
 136   ARMul_ConsolePrint (state, ", Demon 1.01");
 137
 138 /* #ifndef ASIM */
 139
 140   /* Install FPE.  */
 141   for (i = 0; i < fpesize; i += 4)
 142     /* Copy the code.  */
 143     ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
 144
 145   /* Scan backwards from the end of the code.  */
 146   for (i = FPESTART + fpesize;; i -= 4)
 147     {
 148       /* When we reach the marker value, break out of
 149          the loop, leaving i pointing at the maker.  */
 150       if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
 151         break;
 152
 153       /* If necessary, reverse the error strings.  */
 154       if (state->bigendSig && j < 0x80000000)
 155         {
 156           /* It's part of the string so swap it.  */
 157           j = ((j >> 0x18) & 0x000000ff) |
 158             ((j >> 0x08) & 0x0000ff00) |
 159             ((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000);
 160           ARMul_WriteWord (state, i, j);
 161         }
 162     }
 163
 164   /* Copy old illegal instr vector.  */
 165   ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV));
 166   /* Install new vector.  */
 167   ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4)));
 168   ARMul_ConsolePrint (state, ", FPE");
 169
 170 /* #endif  ASIM */
 171 #endif /* VALIDATE */
 172 #endif /* NOOS */
 173
 174   /* Intel do not want DEMON SWI support.  */
 175    if (state->is_XScale)
 176     swi_mask = SWI_MASK_ANGEL;
 177
 178    return TRUE;
 179 }
 180
 181 /* These are libgloss defines, but seem to be common across all supported ARM
 182    targets at the moment.  These should get moved to the callback open_map.  */
 183 #define TARGET_O_BINARY 0
 184 #define TARGET_O_APPEND 0x8
 185 #define TARGET_O_CREAT 0x200
 186 #define TARGET_O_RDONLY 0x0
 187 #define TARGET_O_RDWR 0x2
 188 #define TARGET_O_TRUNC 0x400
 189 #define TARGET_O_WRONLY 0x1
 190
 191 static const int translate_open_mode[] =
 192 {
 193   TARGET_O_RDONLY,              /* "r"   */
 194   TARGET_O_RDONLY + TARGET_O_BINARY,    /* "rb"  */
 195   TARGET_O_RDWR,                /* "r+"  */
 196   TARGET_O_RDWR + TARGET_O_BINARY,              /* "r+b" */
 197   TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC,    /* "w"   */
 198   TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC,  /* "wb"  */
 199   TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC,      /* "w+"  */
 200   TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC,    /* "w+b" */
 201   TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT,   /* "a"   */
 202   TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab"  */
 203   TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT,     /* "a+"  */
 204   TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT    /* "a+b" */
 205 };
 206
 207 static void
 208 SWIWrite0 (ARMul_State * state, ARMword addr)
 209 {
 210   ARMword temp;
 211   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 212
 213   while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)
 214     {
 215       char buffer = temp;
 216       /* Note - we cannot just cast 'temp' to a (char *) here,
 217          since on a big-endian host the byte value will end
 218          up in the wrong place and a nul character will be printed.  */
 219       (void) sim_callback->write_stdout (sim_callback, & buffer, 1);
 220     }
 221
 222   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 223 }
 224
 225 static void
 226 WriteCommandLineTo (ARMul_State * state, ARMword addr)
 227 {
 228   ARMword temp;
 229   char *cptr = state->CommandLine;
 230
 231   if (cptr == NULL)
 232     cptr = "\0";
 233   do
 234     {
 235       temp = (ARMword) * cptr++;
 236       ARMul_SafeWriteByte (state, addr++, temp);
 237     }
 238   while (temp != 0);
 239 }
 240
 241 static int
 242 ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n)
 243 {
 244   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 245   char *p = buf;
 246
 247   while (n--)
 248     if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0')
 249       return 0;
 250   OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG);
 251   state->Reg[0] = -1;
 252   return -1;
 253 }
 254
 255 static void
 256 SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
 257 {
 258   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 259   char buf[PATH_MAX];
 260   int flags;
 261
 262   if (ReadFileName (state, buf, name, sizeof buf) == -1)
 263     return;
 264
 265   /* Now we need to decode the Demon open mode.  */
 266   if (SWIflags >= ARRAY_SIZE (translate_open_mode))
 267     flags = 0;
 268   else
 269     flags = translate_open_mode[SWIflags];
 270
 271   /* Filename ":tt" is special: it denotes stdin/out.  */
 272   if (strcmp (buf, ":tt") == 0)
 273     {
 274       if (flags == TARGET_O_RDONLY) /* opening tty "r" */
 275         state->Reg[0] = 0;      /* stdin */
 276       else
 277         state->Reg[0] = 1;      /* stdout */
 278     }
 279   else
 280     {
 281       state->Reg[0] = sim_callback->open (sim_callback, buf, flags);
 282       OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 283     }
 284 }
 285
 286 static void
 287 SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
 288 {
 289   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 290   int res;
 291   int i;
 292   char *local = malloc (len);
 293
 294   if (local == NULL)
 295     {
 296       sim_callback->printf_filtered
 297         (sim_callback,
 298          "sim: Unable to read 0x%lx bytes - out of memory\n",
 299          (long)len);
 300       return;
 301     }
 302
 303   res = sim_callback->read (sim_callback, f, local, len);
 304   if (res > 0)
 305     for (i = 0; i < res; i++)
 306       ARMul_SafeWriteByte (state, ptr + i, local[i]);
 307
 308   free (local);
 309   state->Reg[0] = res == -1 ? -1 : len - res;
 310   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 311 }
 312
 313 static void
 314 SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
 315 {
 316   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 317   int res;
 318   ARMword i;
 319   char *local = malloc (len);
 320
 321   if (local == NULL)
 322     {
 323       sim_callback->printf_filtered
 324         (sim_callback,
 325          "sim: Unable to write 0x%lx bytes - out of memory\n",
 326          (long) len);
 327       return;
 328     }
 329
 330   for (i = 0; i < len; i++)
 331     local[i] = ARMul_SafeReadByte (state, ptr + i);
 332
 333   res = sim_callback->write (sim_callback, f, local, len);
 334   state->Reg[0] = res == -1 ? -1 : len - res;
 335   free (local);
 336
 337   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 338 }
 339
 340 static void
 341 SWIflen (ARMul_State * state, ARMword fh)
 342 {
 343   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 344   ARMword addr;
 345
 346   if (fh > FOPEN_MAX)
 347     {
 348       OSptr->ErrorNo = EBADF;
 349       state->Reg[0] = -1L;
 350       return;
 351     }
 352
 353   addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR);
 354
 355   state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END);
 356   (void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET);
 357
 358   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 359 }
 360
 361 static void
 362 SWIremove (ARMul_State * state, ARMword path)
 363 {
 364   char buf[PATH_MAX];
 365
 366   if (ReadFileName (state, buf, path, sizeof buf) != -1)
 367     {
 368       struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 369       state->Reg[0] = sim_callback->unlink (sim_callback, buf);
 370       OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 371     }
 372 }
 373
 374 static void
 375 SWIrename (ARMul_State * state, ARMword old, ARMword new)
 376 {
 377   char oldbuf[PATH_MAX], newbuf[PATH_MAX];
 378
 379   if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1
 380       && ReadFileName (state, newbuf, new, sizeof newbuf) != -1)
 381     {
 382       struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 383       state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf);
 384       OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 385     }
 386 }
 387
 388 /* The emulator calls this routine when a SWI instruction is encuntered.
 389    The parameter passed is the SWI number (lower 24 bits of the instruction).  */
 390
 391 unsigned
 392 ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
 393 {
 394   struct OSblock * OSptr = (struct OSblock *) state->OSptr;
 395   int              unhandled = FALSE;
 396
 397   switch (number)
 398     {
 399     case SWI_Read:
 400       if (swi_mask & SWI_MASK_DEMON)
 401         SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
 402       else
 403         unhandled = TRUE;
 404       break;
 405
 406     case SWI_Write:
 407       if (swi_mask & SWI_MASK_DEMON)
 408         SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
 409       else
 410         unhandled = TRUE;
 411       break;
 412
 413     case SWI_Open:
 414       if (swi_mask & SWI_MASK_DEMON)
 415         SWIopen (state, state->Reg[0], state->Reg[1]);
 416       else
 417         unhandled = TRUE;
 418       break;
 419
 420     case SWI_Clock:
 421       if (swi_mask & SWI_MASK_DEMON)
 422         {
 423           /* Return number of centi-seconds.  */
 424           state->Reg[0] =
 425 #ifdef CLOCKS_PER_SEC
 426             (CLOCKS_PER_SEC >= 100)
 427             ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
 428             : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
 429 #else
 430           /* Presume unix... clock() returns microseconds.  */
 431           (ARMword) (clock () / 10000);
 432 #endif
 433           OSptr->ErrorNo = errno;
 434         }
 435       else
 436         unhandled = TRUE;
 437       break;
 438
 439     case SWI_Time:
 440       if (swi_mask & SWI_MASK_DEMON)
 441         {
 442           state->Reg[0] = (ARMword) sim_callback->time (sim_callback);
 443           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 444         }
 445       else
 446         unhandled = TRUE;
 447       break;
 448
 449     case SWI_Close:
 450       if (swi_mask & SWI_MASK_DEMON)
 451         {
 452           state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]);
 453           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 454         }
 455       else
 456         unhandled = TRUE;
 457       break;
 458
 459     case SWI_Flen:
 460       if (swi_mask & SWI_MASK_DEMON)
 461         SWIflen (state, state->Reg[0]);
 462       else
 463         unhandled = TRUE;
 464       break;
 465
 466     case SWI_Exit:
 467       if (swi_mask & SWI_MASK_DEMON)
 468         state->Emulate = FALSE;
 469       else
 470         unhandled = TRUE;
 471       break;
 472
 473     case SWI_Seek:
 474       if (swi_mask & SWI_MASK_DEMON)
 475         {
 476           /* We must return non-zero for failure.  */
 477           state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET);
 478           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 479         }
 480       else
 481         unhandled = TRUE;
 482       break;
 483
 484     case SWI_WriteC:
 485       if (swi_mask & SWI_MASK_DEMON)
 486         {
 487           char tmp = state->Reg[0];
 488           (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
 489           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 490         }
 491       else
 492         unhandled = TRUE;
 493       break;
 494
 495     case SWI_Write0:
 496       if (swi_mask & SWI_MASK_DEMON)
 497         SWIWrite0 (state, state->Reg[0]);
 498       else
 499         unhandled = TRUE;
 500       break;
 501
 502     case SWI_GetErrno:
 503       if (swi_mask & SWI_MASK_DEMON)
 504         state->Reg[0] = OSptr->ErrorNo;
 505       else
 506         unhandled = TRUE;
 507       break;
 508
 509     case SWI_GetEnv:
 510       if (swi_mask & SWI_MASK_DEMON)
 511         {
 512           state->Reg[0] = ADDRCMDLINE;
 513           if (state->MemSize)
 514             state->Reg[1] = state->MemSize;
 515           else
 516             state->Reg[1] = ADDRUSERSTACK;
 517
 518           WriteCommandLineTo (state, state->Reg[0]);
 519         }
 520       else
 521         unhandled = TRUE;
 522       break;
 523
 524     case SWI_Breakpoint:
 525       state->EndCondition = RDIError_BreakpointReached;
 526       state->Emulate = FALSE;
 527       break;
 528
 529     case SWI_Remove:
 530       if (swi_mask & SWI_MASK_DEMON)
 531         SWIremove (state, state->Reg[0]);
 532       else
 533         unhandled = TRUE;
 534       break;
 535
 536     case SWI_Rename:
 537       if (swi_mask & SWI_MASK_DEMON)
 538         SWIrename (state, state->Reg[0], state->Reg[1]);
 539       else
 540         unhandled = TRUE;
 541       break;
 542
 543     case SWI_IsTTY:
 544       if (swi_mask & SWI_MASK_DEMON)
 545         {
 546           state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]);
 547           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 548         }
 549       else
 550         unhandled = TRUE;
 551       break;
 552
 553       /* Handle Angel SWIs as well as Demon ones.  */
 554     case AngelSWI_ARM:
 555     case AngelSWI_Thumb:
 556       if (swi_mask & SWI_MASK_ANGEL)
 557         {
 558           ARMword addr;
 559           ARMword temp;
 560
 561           /* R1 is almost always a parameter block.  */
 562           addr = state->Reg[1];
 563           /* R0 is a reason code.  */
 564           switch (state->Reg[0])
 565             {
 566             case -1:
 567               /* This can happen when a SWI is interrupted (eg receiving a
 568                  ctrl-C whilst processing SWIRead()).  The SWI will complete
 569                  returning -1 in r0 to the caller.  If GDB is then used to
 570                  resume the system call the reason code will now be -1.  */
 571               return TRUE;
 572
 573               /* Unimplemented reason codes.  */
 574             case AngelSWI_Reason_ReadC:
 575             case AngelSWI_Reason_TmpNam:
 576             case AngelSWI_Reason_System:
 577             case AngelSWI_Reason_EnterSVC:
 578             default:
 579               state->Emulate = FALSE;
 580               return FALSE;
 581
 582             case AngelSWI_Reason_Clock:
 583               /* Return number of centi-seconds.  */
 584               state->Reg[0] =
 585 #ifdef CLOCKS_PER_SEC
 586                 (CLOCKS_PER_SEC >= 100)
 587                 ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
 588                 : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
 589 #else
 590               /* Presume unix... clock() returns microseconds.  */
 591               (ARMword) (clock () / 10000);
 592 #endif
 593               OSptr->ErrorNo = errno;
 594               break;
 595
 596             case AngelSWI_Reason_Time:
 597               state->Reg[0] = (ARMword) sim_callback->time (sim_callback);
 598               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 599               break;
 600
 601             case AngelSWI_Reason_WriteC:
 602               {
 603                 char tmp = ARMul_SafeReadByte (state, addr);
 604                 (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
 605                 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 606                 break;
 607               }
 608
 609             case AngelSWI_Reason_Write0:
 610               SWIWrite0 (state, addr);
 611               break;
 612
 613             case AngelSWI_Reason_Close:
 614               state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr));
 615               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 616               break;
 617
 618             case AngelSWI_Reason_Seek:
 619               state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr),
 620                                                          ARMul_ReadWord (state, addr + 4),
 621                                                          SEEK_SET);
 622               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 623               break;
 624
 625             case AngelSWI_Reason_FLen:
 626               SWIflen (state, ARMul_ReadWord (state, addr));
 627               break;
 628
 629             case AngelSWI_Reason_GetCmdLine:
 630               WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
 631               break;
 632
 633             case AngelSWI_Reason_HeapInfo:
 634               /* R1 is a pointer to a pointer.  */
 635               addr = ARMul_ReadWord (state, addr);
 636
 637               /* Pick up the right memory limit.  */
 638               if (state->MemSize)
 639                 temp = state->MemSize;
 640               else
 641                 temp = ADDRUSERSTACK;
 642
 643               ARMul_WriteWord (state, addr, 0);         /* Heap base.  */
 644               ARMul_WriteWord (state, addr + 4, temp);  /* Heap limit.  */
 645               ARMul_WriteWord (state, addr + 8, temp);  /* Stack base.  */
 646               ARMul_WriteWord (state, addr + 12, temp); /* Stack limit.  */
 647               break;
 648
 649             case AngelSWI_Reason_ReportException:
 650               if (state->Reg[1] == ADP_Stopped_ApplicationExit)
 651                 state->Reg[0] = 0;
 652               else
 653                 state->Reg[0] = -1;
 654               state->Emulate = FALSE;
 655               break;
 656
 657             case ADP_Stopped_ApplicationExit:
 658               state->Reg[0] = 0;
 659               state->Emulate = FALSE;
 660               break;
 661
 662             case ADP_Stopped_RunTimeError:
 663               state->Reg[0] = -1;
 664               state->Emulate = FALSE;
 665               break;
 666
 667             case AngelSWI_Reason_Errno:
 668               state->Reg[0] = OSptr->ErrorNo;
 669               break;
 670
 671             case AngelSWI_Reason_Open:
 672               SWIopen (state,
 673                        ARMul_ReadWord (state, addr),
 674                        ARMul_ReadWord (state, addr + 4));
 675               break;
 676
 677             case AngelSWI_Reason_Read:
 678               SWIread (state,
 679                        ARMul_ReadWord (state, addr),
 680                        ARMul_ReadWord (state, addr + 4),
 681                        ARMul_ReadWord (state, addr + 8));
 682               break;
 683
 684             case AngelSWI_Reason_Write:
 685               SWIwrite (state,
 686                         ARMul_ReadWord (state, addr),
 687                         ARMul_ReadWord (state, addr + 4),
 688                         ARMul_ReadWord (state, addr + 8));
 689               break;
 690
 691             case AngelSWI_Reason_IsTTY:
 692               state->Reg[0] = sim_callback->isatty (sim_callback,
 693                                                     ARMul_ReadWord (state, addr));
 694               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 695               break;
 696
 697             case AngelSWI_Reason_Remove:
 698               SWIremove (state,
 699                          ARMul_ReadWord (state, addr));
 700               break;
 701
 702             case AngelSWI_Reason_Rename:
 703               SWIrename (state,
 704                          ARMul_ReadWord (state, addr),
 705                          ARMul_ReadWord (state, addr + 4));
 706               break;
 707             }
 708         }
 709       else
 710         unhandled = TRUE;
 711       break;
 712
 713       /* The following SWIs are generated by the softvectorcode[]
 714          installed by default by the simulator.  */
 715     case 0x91: /* Undefined Instruction.  */
 716       {
 717         ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
 718
 719         sim_callback->printf_filtered
 720           (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x.  Stopping.\n",
 721            ARMul_ReadWord (state, addr), addr);
 722         state->EndCondition = RDIError_SoftwareInterrupt;
 723         state->Emulate = FALSE;
 724         return FALSE;
 725       }
 726
 727     case 0x90: /* Reset.  */
 728     case 0x92: /* SWI.  */
 729       /* These two can be safely ignored.  */
 730       break;
 731
 732     case 0x93: /* Prefetch Abort.  */
 733     case 0x94: /* Data Abort.  */
 734     case 0x95: /* Address Exception.  */
 735     case 0x96: /* IRQ.  */
 736     case 0x97: /* FIQ.  */
 737     case 0x98: /* Error.  */
 738       unhandled = TRUE;
 739       break;
 740
 741     case -1:
 742       /* This can happen when a SWI is interrupted (eg receiving a
 743          ctrl-C whilst processing SWIRead()).  The SWI will complete
 744          returning -1 in r0 to the caller.  If GDB is then used to
 745          resume the system call the reason code will now be -1.  */
 746       return TRUE;
 747
 748     case 0x180001: /* RedBoot's Syscall SWI in ARM mode.  */
 749       if (swi_mask & SWI_MASK_REDBOOT)
 750         {
 751           switch (state->Reg[0])
 752             {
 753               /* These numbers are defined in libgloss/syscall.h
 754                  but the simulator should not be dependend upon
 755                  libgloss being installed.  */
 756             case 1:  /* Exit.  */
 757               state->Emulate = FALSE;
 758               /* Copy exit code into r0.  */
 759               state->Reg[0] = state->Reg[1];
 760               break;
 761
 762             case 2:  /* Open.  */
 763               SWIopen (state, state->Reg[1], state->Reg[2]);
 764               break;
 765
 766             case 3:  /* Close.  */
 767               state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]);
 768               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 769               break;
 770
 771             case 4:  /* Read.  */
 772               SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]);
 773               break;
 774
 775             case 5:  /* Write.  */
 776               SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]);
 777               break;
 778
 779             case 6:  /* Lseek.  */
 780               state->Reg[0] = sim_callback->lseek (sim_callback,
 781                                                    state->Reg[1],
 782                                                    state->Reg[2],
 783                                                    state->Reg[3]);
 784               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 785               break;
 786
 787             case 17: /* Utime.  */
 788               state->Reg[0] = state->Reg[1] = (ARMword) sim_callback->time (sim_callback);
 789               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 790               break;
 791
 792             case 7:  /* Unlink.  */
 793             case 8:  /* Getpid.  */
 794             case 9:  /* Kill.  */
 795             case 10: /* Fstat.  */
 796             case 11: /* Sbrk.  */
 797             case 12: /* Argvlen.  */
 798             case 13: /* Argv.  */
 799             case 14: /* ChDir.  */
 800             case 15: /* Stat.  */
 801             case 16: /* Chmod.  */
 802             case 18: /* Time.  */
 803               sim_callback->printf_filtered
 804                 (sim_callback,
 805                  "sim: unhandled RedBoot syscall `%d' encountered - "
 806                  "returning ENOSYS\n",
 807                  state->Reg[0]);
 808               state->Reg[0] = -1;
 809               OSptr->ErrorNo = cb_host_to_target_errno
 810                 (sim_callback, ENOSYS);
 811               break;
 812             case 1001: /* Meminfo. */
 813               {
 814                 ARMword totmem = state->Reg[1],
 815                         topmem = state->Reg[2];
 816                 ARMword stack = state->MemSize > 0
 817                   ? state->MemSize : ADDRUSERSTACK;
 818                 if (totmem != 0)
 819                   ARMul_WriteWord (state, totmem, stack);
 820                 if (topmem != 0)
 821                   ARMul_WriteWord (state, topmem, stack);
 822                 state->Reg[0] = 0;
 823                 break;
 824               }
 825
 826             default:
 827               sim_callback->printf_filtered
 828                 (sim_callback,
 829                  "sim: unknown RedBoot syscall '%d' encountered - ignoring\n",
 830                  state->Reg[0]);
 831               return FALSE;
 832             }
 833           break;
 834         }
 835       ATTRIBUTE_FALLTHROUGH;
 836
 837     default:
 838       unhandled = TRUE;
 839     }
 840
 841   if (unhandled)
 842     {
 843       if (SWI_vector_installed)
 844         {
 845           ARMword cpsr;
 846           ARMword i_size;
 847
 848           cpsr = ARMul_GetCPSR (state);
 849           i_size = INSN_SIZE;
 850
 851           ARMul_SetSPSR (state, SVC32MODE, cpsr);
 852
 853           cpsr &= ~0xbf;
 854           cpsr |= SVC32MODE | 0x80;
 855           ARMul_SetCPSR (state, cpsr);
 856
 857           state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
 858           state->NextInstr            = RESUME;
 859           state->Reg[15]              = state->pc = ARMSWIV;
 860           FLUSHPIPE;
 861         }
 862       else
 863         {
 864           sim_callback->printf_filtered
 865             (sim_callback,
 866              "sim: unknown SWI encountered - %x - ignoring\n",
 867              number);
 868           return FALSE;
 869         }
 870     }
 871
 872   return TRUE;
 873 }