1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2024 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
34 #include "arch-utils.h"
37 #include "mips-tdep.h"
39 #include "reggroups.h"
40 #include "opcode/mips.h"
44 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
52 #include "target-descriptions.h"
53 #include "dwarf2/frame.h"
54 #include "user-regs.h"
57 #include "target-float.h"
60 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
62 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
64 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
65 static int mips16_instruction_has_delay_slot (unsigned short inst
,
68 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
70 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 CORE_ADDR addr
, int mustbe32
);
72 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 CORE_ADDR addr
, int mustbe32
);
75 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
76 const frame_info_ptr
&, const char *);
78 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
79 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
80 #define ST0_FR (1 << 26)
82 /* The sizes of floating point registers. */
86 MIPS_FPU_SINGLE_REGSIZE
= 4,
87 MIPS_FPU_DOUBLE_REGSIZE
= 8
96 static const char *mips_abi_string
;
98 static const char *const mips_abi_strings
[] = {
109 /* Enum describing the different kinds of breakpoints. */
111 enum mips_breakpoint_kind
113 /* 16-bit MIPS16 mode breakpoint. */
114 MIPS_BP_KIND_MIPS16
= 2,
116 /* 16-bit microMIPS mode breakpoint. */
117 MIPS_BP_KIND_MICROMIPS16
= 3,
119 /* 32-bit standard MIPS mode breakpoint. */
120 MIPS_BP_KIND_MIPS32
= 4,
122 /* 32-bit microMIPS mode breakpoint. */
123 MIPS_BP_KIND_MICROMIPS32
= 5,
126 /* For backwards compatibility we default to MIPS16. This flag is
127 overridden as soon as unambiguous ELF file flags tell us the
128 compressed ISA encoding used. */
129 static const char mips_compression_mips16
[] = "mips16";
130 static const char mips_compression_micromips
[] = "micromips";
131 static const char *const mips_compression_strings
[] =
133 mips_compression_mips16
,
134 mips_compression_micromips
,
138 static const char *mips_compression_string
= mips_compression_mips16
;
140 /* The standard register names, and all the valid aliases for them. */
141 struct register_alias
147 /* Aliases for o32 and most other ABIs. */
148 const struct register_alias mips_o32_aliases
[] = {
155 /* Aliases for n32 and n64. */
156 const struct register_alias mips_n32_n64_aliases
[] = {
163 /* Aliases for ABI-independent registers. */
164 const struct register_alias mips_register_aliases
[] = {
165 /* The architecture manuals specify these ABI-independent names for
167 #define R(n) { "r" #n, n }
168 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
169 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
170 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
171 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
174 /* k0 and k1 are sometimes called these instead (for "kernel
179 /* This is the traditional GDB name for the CP0 status register. */
180 { "sr", MIPS_PS_REGNUM
},
182 /* This is the traditional GDB name for the CP0 BadVAddr register. */
183 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
185 /* This is the traditional GDB name for the FCSR. */
186 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
189 const struct register_alias mips_numeric_register_aliases
[] = {
190 #define R(n) { #n, n }
191 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
192 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
193 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
194 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
198 #ifndef MIPS_DEFAULT_FPU_TYPE
199 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
201 static int mips_fpu_type_auto
= 1;
202 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
204 static unsigned int mips_debug
= 0;
206 /* Properties (for struct target_desc) describing the g/G packet
208 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
209 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
211 struct target_desc
*mips_tdesc_gp32
;
212 struct target_desc
*mips_tdesc_gp64
;
214 /* The current set of options to be passed to the disassembler. */
215 static std::string mips_disassembler_options
;
217 /* Implicit disassembler options for individual ABIs. These tell
218 libopcodes to use general-purpose register names corresponding
219 to the ABI we have selected, perhaps via a `set mips abi ...'
220 override, rather than ones inferred from the ABI set in the ELF
221 headers of the binary file selected for debugging. */
222 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
223 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
224 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
226 const struct mips_regnum
*
227 mips_regnum (struct gdbarch
*gdbarch
)
229 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
234 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
236 return mips_regnum (gdbarch
)->fp0
+ 12;
239 /* Return 1 if REGNUM refers to a floating-point general register, raw
240 or cooked. Otherwise return 0. */
243 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
245 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
247 return (rawnum
>= mips_regnum (gdbarch
)->fp0
248 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
252 mips_eabi (gdbarch
*arch
)
254 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
255 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
256 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
260 mips_last_fp_arg_regnum (gdbarch
*arch
)
262 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
263 return tdep
->mips_last_fp_arg_regnum
;
267 mips_last_arg_regnum (gdbarch
*arch
)
269 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
270 return tdep
->mips_last_arg_regnum
;
273 static enum mips_fpu_type
274 mips_get_fpu_type (gdbarch
*arch
)
276 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
277 return tdep
->mips_fpu_type
;
280 /* Return the MIPS ABI associated with GDBARCH. */
282 mips_abi (struct gdbarch
*gdbarch
)
284 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
285 return tdep
->mips_abi
;
289 mips_isa_regsize (struct gdbarch
*gdbarch
)
291 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
293 /* If we know how big the registers are, use that size. */
294 if (tdep
->register_size_valid_p
)
295 return tdep
->register_size
;
297 /* Fall back to the previous behavior. */
298 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
299 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
302 /* Max saved register size. */
303 #define MAX_MIPS_ABI_REGSIZE 8
305 /* Return the currently configured (or set) saved register size. */
308 mips_abi_regsize (struct gdbarch
*gdbarch
)
310 switch (mips_abi (gdbarch
))
312 case MIPS_ABI_EABI32
:
318 case MIPS_ABI_EABI64
:
320 case MIPS_ABI_UNKNOWN
:
323 internal_error (_("bad switch"));
327 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
328 are some functions to handle addresses associated with compressed
329 code including but not limited to testing, setting, or clearing
330 bit 0 of such addresses. */
332 /* Return one iff compressed code is the MIPS16 instruction set. */
335 is_mips16_isa (struct gdbarch
*gdbarch
)
337 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
338 return tdep
->mips_isa
== ISA_MIPS16
;
341 /* Return one iff compressed code is the microMIPS instruction set. */
344 is_micromips_isa (struct gdbarch
*gdbarch
)
346 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
347 return tdep
->mips_isa
== ISA_MICROMIPS
;
350 /* Return one iff ADDR denotes compressed code. */
353 is_compact_addr (CORE_ADDR addr
)
358 /* Return one iff ADDR denotes standard ISA code. */
361 is_mips_addr (CORE_ADDR addr
)
363 return !is_compact_addr (addr
);
366 /* Return one iff ADDR denotes MIPS16 code. */
369 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
371 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
374 /* Return one iff ADDR denotes microMIPS code. */
377 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
379 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
382 /* Strip the ISA (compression) bit off from ADDR. */
385 unmake_compact_addr (CORE_ADDR addr
)
387 return ((addr
) & ~(CORE_ADDR
) 1);
390 /* Add the ISA (compression) bit to ADDR. */
393 make_compact_addr (CORE_ADDR addr
)
395 return ((addr
) | (CORE_ADDR
) 1);
398 /* Extern version of unmake_compact_addr; we use a separate function
399 so that unmake_compact_addr can be inlined throughout this file. */
402 mips_unmake_compact_addr (CORE_ADDR addr
)
404 return unmake_compact_addr (addr
);
407 /* Functions for setting and testing a bit in a minimal symbol that
408 marks it as MIPS16 or microMIPS function. The MSB of the minimal
409 symbol's "info" field is used for this purpose.
411 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
412 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
413 one of the "special" bits in a minimal symbol to mark it accordingly.
414 The test checks an ELF-private flag that is valid for true function
415 symbols only; for synthetic symbols such as for PLT stubs that have
416 no ELF-private part at all the MIPS BFD backend arranges for this
417 information to be carried in the asymbol's udata field instead.
419 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
420 in a minimal symbol. */
423 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
425 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
426 unsigned char st_other
;
428 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
429 st_other
= elfsym
->internal_elf_sym
.st_other
;
430 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
431 st_other
= sym
->udata
.i
;
435 if (ELF_ST_IS_MICROMIPS (st_other
))
437 SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
438 CORE_ADDR fixed
= CORE_ADDR (msym
->unrelocated_address ()) | 1;
439 msym
->set_unrelocated_address (unrelocated_addr (fixed
));
441 else if (ELF_ST_IS_MIPS16 (st_other
))
443 SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
444 CORE_ADDR fixed
= CORE_ADDR (msym
->unrelocated_address ()) | 1;
445 msym
->set_unrelocated_address (unrelocated_addr (fixed
));
449 /* Return one iff MSYM refers to standard ISA code. */
452 msymbol_is_mips (struct minimal_symbol
*msym
)
454 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
455 || MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
458 /* Return one iff MSYM refers to MIPS16 code. */
461 msymbol_is_mips16 (struct minimal_symbol
*msym
)
463 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
466 /* Return one iff MSYM refers to microMIPS code. */
469 msymbol_is_micromips (struct minimal_symbol
*msym
)
471 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
474 /* Set the ISA bit in the main symbol too, complementing the corresponding
475 minimal symbol setting and reflecting the run-time value of the symbol.
476 The need for comes from the ISA bit having been cleared as code in
477 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
478 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
479 of symbols referring to compressed code different in GDB to the values
480 used by actual code. That in turn makes them evaluate incorrectly in
481 expressions, producing results different to what the same expressions
482 yield when compiled into the program being debugged. */
485 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
487 if (sym
->aclass () == LOC_BLOCK
)
489 /* We are in symbol reading so it is OK to cast away constness. */
490 struct block
*block
= (struct block
*) sym
->value_block ();
491 CORE_ADDR compact_block_start
;
492 struct bound_minimal_symbol msym
;
494 compact_block_start
= block
->start () | 1;
495 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
496 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
498 block
->set_start (compact_block_start
);
503 /* XFER a value from the big/little/left end of the register.
504 Depending on the size of the value it might occupy the entire
505 register or just part of it. Make an allowance for this, aligning
506 things accordingly. */
509 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
510 int reg_num
, int length
,
511 enum bfd_endian endian
, gdb_byte
*in
,
512 const gdb_byte
*out
, int buf_offset
)
516 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
517 /* Need to transfer the left or right part of the register, based on
518 the targets byte order. */
522 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
524 case BFD_ENDIAN_LITTLE
:
527 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
531 internal_error (_("bad switch"));
534 gdb_printf (gdb_stderr
,
535 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
536 reg_num
, reg_offset
, buf_offset
, length
);
537 if (mips_debug
&& out
!= NULL
)
540 gdb_printf (gdb_stdlog
, "out ");
541 for (i
= 0; i
< length
; i
++)
542 gdb_printf (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
545 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
547 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
548 if (mips_debug
&& in
!= NULL
)
551 gdb_printf (gdb_stdlog
, "in ");
552 for (i
= 0; i
< length
; i
++)
553 gdb_printf (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
556 gdb_printf (gdb_stdlog
, "\n");
559 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
560 compatiblity mode. A return value of 1 means that we have
561 physical 64-bit registers, but should treat them as 32-bit registers. */
564 mips2_fp_compat (const frame_info_ptr
&frame
)
566 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
567 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
569 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
573 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
574 in all the places we deal with FP registers. PR gdb/413. */
575 /* Otherwise check the FR bit in the status register - it controls
576 the FP compatiblity mode. If it is clear we are in compatibility
578 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
585 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
587 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
589 /* The list of available "set mips " and "show mips " commands. */
591 static struct cmd_list_element
*setmipscmdlist
= NULL
;
592 static struct cmd_list_element
*showmipscmdlist
= NULL
;
594 /* Integer registers 0 thru 31 are handled explicitly by
595 mips_register_name(). Processor specific registers 32 and above
596 are listed in the following tables. */
599 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
603 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
604 "sr", "lo", "hi", "bad", "cause", "pc",
605 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
606 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
607 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
608 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
612 /* Names of tx39 registers. */
614 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
615 "sr", "lo", "hi", "bad", "cause", "pc",
616 "", "", "", "", "", "", "", "",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
619 "", "", "", "", "", "", "", "",
621 "", "", "", "", "", "", "", "",
622 "", "", "config", "cache", "debug", "depc", "epc",
625 /* Names of registers with Linux kernels. */
626 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
627 "sr", "lo", "hi", "bad", "cause", "pc",
628 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
629 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
630 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
631 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
636 /* Return the name of the register corresponding to REGNO. */
638 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
640 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
641 /* GPR names for all ABIs other than n32/n64. */
642 static const char *mips_gpr_names
[] = {
643 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
644 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
645 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
646 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
649 /* GPR names for n32 and n64 ABIs. */
650 static const char *mips_n32_n64_gpr_names
[] = {
651 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
652 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
653 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
654 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
657 enum mips_abi abi
= mips_abi (gdbarch
);
659 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
660 but then don't make the raw register names visible. This (upper)
661 range of user visible register numbers are the pseudo-registers.
663 This approach was adopted accommodate the following scenario:
664 It is possible to debug a 64-bit device using a 32-bit
665 programming model. In such instances, the raw registers are
666 configured to be 64-bits wide, while the pseudo registers are
667 configured to be 32-bits wide. The registers that the user
668 sees - the pseudo registers - match the users expectations
669 given the programming model being used. */
670 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
671 if (regno
< gdbarch_num_regs (gdbarch
))
674 /* The MIPS integer registers are always mapped from 0 to 31. The
675 names of the registers (which reflects the conventions regarding
676 register use) vary depending on the ABI. */
677 if (0 <= rawnum
&& rawnum
< 32)
679 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
680 return mips_n32_n64_gpr_names
[rawnum
];
682 return mips_gpr_names
[rawnum
];
684 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
685 return tdesc_register_name (gdbarch
, rawnum
);
686 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
688 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
689 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
690 return tdep
->mips_processor_reg_names
[rawnum
- 32];
694 internal_error (_("mips_register_name: bad register number %d"), rawnum
);
697 /* Return the groups that a MIPS register can be categorised into. */
700 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
701 const struct reggroup
*reggroup
)
706 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
707 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
708 if (reggroup
== all_reggroup
)
710 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
711 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
712 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
713 (gdbarch), as not all architectures are multi-arch. */
714 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
715 if (gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
717 if (reggroup
== float_reggroup
)
718 return float_p
&& pseudo
;
719 if (reggroup
== vector_reggroup
)
720 return vector_p
&& pseudo
;
721 if (reggroup
== general_reggroup
)
722 return (!vector_p
&& !float_p
) && pseudo
;
723 /* Save the pseudo registers. Need to make certain that any code
724 extracting register values from a saved register cache also uses
726 if (reggroup
== save_reggroup
)
727 return raw_p
&& pseudo
;
728 /* Restore the same pseudo register. */
729 if (reggroup
== restore_reggroup
)
730 return raw_p
&& pseudo
;
734 /* Return the groups that a MIPS register can be categorised into.
735 This version is only used if we have a target description which
736 describes real registers (and their groups). */
739 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
740 const struct reggroup
*reggroup
)
742 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
743 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
746 /* Only save, restore, and display the pseudo registers. Need to
747 make certain that any code extracting register values from a
748 saved register cache also uses pseudo registers.
750 Note: saving and restoring the pseudo registers is slightly
751 strange; if we have 64 bits, we should save and restore all
752 64 bits. But this is hard and has little benefit. */
756 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
760 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
763 /* Map the symbol table registers which live in the range [1 *
764 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
765 registers. Take care of alignment and size problems. */
767 static enum register_status
768 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
769 int cookednum
, gdb_byte
*buf
)
771 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
772 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
773 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
774 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
775 return regcache
->raw_read (rawnum
, buf
);
776 else if (register_size (gdbarch
, rawnum
) >
777 register_size (gdbarch
, cookednum
))
779 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
781 if (tdep
->mips64_transfers_32bit_regs_p
)
782 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
785 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
787 enum register_status status
;
789 status
= regcache
->raw_read (rawnum
, ®val
);
790 if (status
== REG_VALID
)
791 store_signed_integer (buf
, 4, byte_order
, regval
);
796 internal_error (_("bad register size"));
800 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
801 struct regcache
*regcache
, int cookednum
,
804 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
805 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
806 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
807 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
808 regcache
->raw_write (rawnum
, buf
);
809 else if (register_size (gdbarch
, rawnum
) >
810 register_size (gdbarch
, cookednum
))
812 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
814 if (tdep
->mips64_transfers_32bit_regs_p
)
815 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
818 /* Sign extend the shortened version of the register prior
819 to placing it in the raw register. This is required for
820 some mips64 parts in order to avoid unpredictable behavior. */
821 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
822 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
823 regcache_raw_write_signed (regcache
, rawnum
, regval
);
827 internal_error (_("bad register size"));
831 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
832 struct agent_expr
*ax
, int reg
)
834 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
835 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
836 && reg
< 2 * gdbarch_num_regs (gdbarch
));
838 ax_reg_mask (ax
, rawnum
);
844 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
845 struct agent_expr
*ax
, int reg
)
847 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
848 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
849 && reg
< 2 * gdbarch_num_regs (gdbarch
));
850 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
854 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
856 mips_gdbarch_tdep
*tdep
857 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
859 if (!tdep
->mips64_transfers_32bit_regs_p
860 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
863 ax_simple (ax
, aop_lsh
);
866 ax_simple (ax
, aop_rsh_signed
);
870 internal_error (_("bad register size"));
875 /* Table to translate 3-bit register field to actual register number. */
876 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
878 /* Heuristic_proc_start may hunt through the text section for a long
879 time across a 2400 baud serial line. Allows the user to limit this
882 static int heuristic_fence_post
= 0;
884 /* Number of bytes of storage in the actual machine representation for
885 register N. NOTE: This defines the pseudo register type so need to
886 rebuild the architecture vector. */
888 static bool mips64_transfers_32bit_regs_p
= false;
891 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
892 struct cmd_list_element
*c
)
894 struct gdbarch_info info
;
895 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
896 instead of relying on globals. Doing that would let generic code
897 handle the search for this specific architecture. */
898 if (!gdbarch_update_p (info
))
900 mips64_transfers_32bit_regs_p
= 0;
901 error (_("32-bit compatibility mode not supported"));
905 /* Convert to/from a register and the corresponding memory value. */
907 /* This predicate tests for the case of an 8 byte floating point
908 value that is being transferred to or from a pair of floating point
909 registers each of which are (or are considered to be) only 4 bytes
912 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
915 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
916 && register_size (gdbarch
, regnum
) == 4
917 && mips_float_register_p (gdbarch
, regnum
)
918 && type
->code () == TYPE_CODE_FLT
&& type
->length () == 8);
921 /* This predicate tests for the case of a value of less than 8
922 bytes in width that is being transfered to or from an 8 byte
923 general purpose register. */
925 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
928 int num_regs
= gdbarch_num_regs (gdbarch
);
930 return (register_size (gdbarch
, regnum
) == 8
931 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
932 && type
->length () < 8);
936 mips_convert_register_p (struct gdbarch
*gdbarch
,
937 int regnum
, struct type
*type
)
939 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
940 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
944 mips_register_to_value (const frame_info_ptr
&frame
, int regnum
,
945 struct type
*type
, gdb_byte
*to
,
946 int *optimizedp
, int *unavailablep
)
948 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
949 frame_info_ptr next_frame
= get_next_frame_sentinel_okay (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 get_frame_register (frame
, regnum
+ 0, to
+ 4);
954 get_frame_register (frame
, regnum
+ 1, to
+ 0);
956 if (!get_frame_register_bytes (next_frame
, regnum
+ 0, 0, { to
+ 4, 4 },
957 optimizedp
, unavailablep
))
960 if (!get_frame_register_bytes (next_frame
, regnum
+ 1, 0, { to
+ 0, 4 },
961 optimizedp
, unavailablep
))
963 *optimizedp
= *unavailablep
= 0;
966 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 size_t len
= type
->length ();
971 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
972 if (!get_frame_register_bytes (next_frame
, regnum
, offset
, { to
, len
},
973 optimizedp
, unavailablep
))
976 *optimizedp
= *unavailablep
= 0;
981 internal_error (_("mips_register_to_value: unrecognized case"));
986 mips_value_to_register (const frame_info_ptr
&frame
, int regnum
,
987 struct type
*type
, const gdb_byte
*from
)
989 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
991 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
993 auto from_view
= gdb::make_array_view (from
, 8);
994 frame_info_ptr next_frame
= get_next_frame_sentinel_okay (frame
);
995 put_frame_register (next_frame
, regnum
, from_view
.slice (4));
996 put_frame_register (next_frame
, regnum
+ 1, from_view
.slice (0, 4));
998 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
1001 size_t len
= type
->length ();
1002 frame_info_ptr next_frame
= get_next_frame_sentinel_okay (frame
);
1004 /* Sign extend values, irrespective of type, that are stored to
1005 a 64-bit general purpose register. (32-bit unsigned values
1006 are stored as signed quantities within a 64-bit register.
1007 When performing an operation, in compiled code, that combines
1008 a 32-bit unsigned value with a signed 64-bit value, a type
1009 conversion is first performed that zeroes out the high 32 bits.) */
1010 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1013 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1015 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1016 put_frame_register_bytes (next_frame
, regnum
, 0, {fill
, 8 - len
});
1017 put_frame_register_bytes (next_frame
, regnum
, 8 - len
, {from
, len
});
1021 if (from
[len
-1] & 0x80)
1022 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1024 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1025 put_frame_register_bytes (next_frame
, regnum
, 0, {from
, len
});
1026 put_frame_register_bytes (next_frame
, regnum
, len
, {fill
, 8 - len
});
1031 internal_error (_("mips_value_to_register: unrecognized case"));
1035 /* Return the GDB type object for the "standard" data type of data in
1038 static struct type
*
1039 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1041 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1042 if (mips_float_register_p (gdbarch
, regnum
))
1044 /* The floating-point registers raw, or cooked, always match
1045 mips_isa_regsize(), and also map 1:1, byte for byte. */
1046 if (mips_isa_regsize (gdbarch
) == 4)
1047 return builtin_type (gdbarch
)->builtin_float
;
1049 return builtin_type (gdbarch
)->builtin_double
;
1051 else if (regnum
< gdbarch_num_regs (gdbarch
))
1053 /* The raw or ISA registers. These are all sized according to
1055 if (mips_isa_regsize (gdbarch
) == 4)
1056 return builtin_type (gdbarch
)->builtin_int32
;
1058 return builtin_type (gdbarch
)->builtin_int64
;
1062 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1063 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1065 /* The cooked or ABI registers. These are sized according to
1066 the ABI (with a few complications). */
1067 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1068 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1069 return builtin_type (gdbarch
)->builtin_int32
;
1070 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1071 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1072 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1073 /* The pseudo/cooked view of the embedded registers is always
1074 32-bit. The raw view is handled below. */
1075 return builtin_type (gdbarch
)->builtin_int32
;
1076 else if (tdep
->mips64_transfers_32bit_regs_p
)
1077 /* The target, while possibly using a 64-bit register buffer,
1078 is only transfering 32-bits of each integer register.
1079 Reflect this in the cooked/pseudo (ABI) register value. */
1080 return builtin_type (gdbarch
)->builtin_int32
;
1081 else if (mips_abi_regsize (gdbarch
) == 4)
1082 /* The ABI is restricted to 32-bit registers (the ISA could be
1084 return builtin_type (gdbarch
)->builtin_int32
;
1087 return builtin_type (gdbarch
)->builtin_int64
;
1091 /* Return the GDB type for the pseudo register REGNUM, which is the
1092 ABI-level view. This function is only called if there is a target
1093 description which includes registers, so we know precisely the
1094 types of hardware registers. */
1096 static struct type
*
1097 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1099 const int num_regs
= gdbarch_num_regs (gdbarch
);
1100 int rawnum
= regnum
% num_regs
;
1101 struct type
*rawtype
;
1103 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1105 /* Absent registers are still absent. */
1106 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1107 if (rawtype
->length () == 0)
1110 /* Present the floating point registers however the hardware did;
1111 do not try to convert between FPU layouts. */
1112 if (mips_float_register_p (gdbarch
, rawnum
))
1115 /* Floating-point control registers are always 32-bit even though for
1116 backwards compatibility reasons 64-bit targets will transfer them
1117 as 64-bit quantities even if using XML descriptions. */
1118 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1119 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1120 return builtin_type (gdbarch
)->builtin_int32
;
1122 /* Use pointer types for registers if we can. For n32 we can not,
1123 since we do not have a 64-bit pointer type. */
1124 if (mips_abi_regsize (gdbarch
)
1125 == builtin_type (gdbarch
)->builtin_data_ptr
->length())
1127 if (rawnum
== MIPS_SP_REGNUM
1128 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1129 return builtin_type (gdbarch
)->builtin_data_ptr
;
1130 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1131 return builtin_type (gdbarch
)->builtin_func_ptr
;
1134 if (mips_abi_regsize (gdbarch
) == 4 && rawtype
->length () == 8
1135 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1136 || rawnum
== mips_regnum (gdbarch
)->lo
1137 || rawnum
== mips_regnum (gdbarch
)->hi
1138 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1139 || rawnum
== mips_regnum (gdbarch
)->cause
1140 || rawnum
== mips_regnum (gdbarch
)->pc
1141 || (mips_regnum (gdbarch
)->dspacc
!= -1
1142 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1143 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1144 return builtin_type (gdbarch
)->builtin_int32
;
1146 /* The pseudo/cooked view of embedded registers is always
1147 32-bit, even if the target transfers 64-bit values for them.
1148 New targets relying on XML descriptions should only transfer
1149 the necessary 32 bits, but older versions of GDB expected 64,
1150 so allow the target to provide 64 bits without interfering
1151 with the displayed type. */
1152 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1153 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1154 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1155 return builtin_type (gdbarch
)->builtin_int32
;
1157 /* For all other registers, pass through the hardware type. */
1161 /* Should the upper word of 64-bit addresses be zeroed? */
1162 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1165 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1167 switch (mask_address_var
)
1169 case AUTO_BOOLEAN_TRUE
:
1171 case AUTO_BOOLEAN_FALSE
:
1174 case AUTO_BOOLEAN_AUTO
:
1175 return tdep
->default_mask_address_p
;
1177 internal_error (_("mips_mask_address_p: bad switch"));
1183 show_mask_address (struct ui_file
*file
, int from_tty
,
1184 struct cmd_list_element
*c
, const char *value
)
1186 const char *additional_text
= "";
1187 if (mask_address_var
== AUTO_BOOLEAN_AUTO
)
1189 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
1191 additional_text
= _(" (current architecture is not MIPS)");
1194 mips_gdbarch_tdep
*tdep
1195 = gdbarch_tdep
<mips_gdbarch_tdep
> (current_inferior ()->arch ());
1197 if (mips_mask_address_p (tdep
))
1198 additional_text
= _(" (currently \"on\")");
1200 additional_text
= _(" (currently \"off\")");
1204 gdb_printf (file
, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"),
1205 value
, additional_text
);
1208 /* Tell if the program counter value in MEMADDR is in a standard ISA
1212 mips_pc_is_mips (CORE_ADDR memaddr
)
1214 struct bound_minimal_symbol sym
;
1216 /* Flags indicating that this is a MIPS16 or microMIPS function is
1217 stored by elfread.c in the high bit of the info field. Use this
1218 to decide if the function is standard MIPS. Otherwise if bit 0
1219 of the address is clear, then this is a standard MIPS function. */
1220 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1222 return msymbol_is_mips (sym
.minsym
);
1224 return is_mips_addr (memaddr
);
1227 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1230 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1232 struct bound_minimal_symbol sym
;
1234 /* A flag indicating that this is a MIPS16 function is stored by
1235 elfread.c in the high bit of the info field. Use this to decide
1236 if the function is MIPS16. Otherwise if bit 0 of the address is
1237 set, then ELF file flags will tell if this is a MIPS16 function. */
1238 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1240 return msymbol_is_mips16 (sym
.minsym
);
1242 return is_mips16_addr (gdbarch
, memaddr
);
1245 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1248 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1250 struct bound_minimal_symbol sym
;
1252 /* A flag indicating that this is a microMIPS function is stored by
1253 elfread.c in the high bit of the info field. Use this to decide
1254 if the function is microMIPS. Otherwise if bit 0 of the address
1255 is set, then ELF file flags will tell if this is a microMIPS
1257 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1259 return msymbol_is_micromips (sym
.minsym
);
1261 return is_micromips_addr (gdbarch
, memaddr
);
1264 /* Tell the ISA type of the function the program counter value in MEMADDR
1267 static enum mips_isa
1268 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1270 struct bound_minimal_symbol sym
;
1272 /* A flag indicating that this is a MIPS16 or a microMIPS function
1273 is stored by elfread.c in the high bit of the info field. Use
1274 this to decide if the function is MIPS16 or microMIPS or normal
1275 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1276 flags will tell if this is a MIPS16 or a microMIPS function. */
1277 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1280 if (msymbol_is_micromips (sym
.minsym
))
1281 return ISA_MICROMIPS
;
1282 else if (msymbol_is_mips16 (sym
.minsym
))
1289 if (is_mips_addr (memaddr
))
1291 else if (is_micromips_addr (gdbarch
, memaddr
))
1292 return ISA_MICROMIPS
;
1298 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1299 The need for comes from the ISA bit having been cleared, making
1300 addresses in FDE, range records, etc. referring to compressed code
1301 different to those in line information, the symbol table and finally
1302 the PC register. That in turn confuses many operations. */
1305 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1307 pc
= unmake_compact_addr (pc
);
1308 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1311 /* Recalculate the line record requested so that the resulting PC has
1312 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1313 this adjustment comes from some records associated with compressed
1314 code having the ISA bit cleared, most notably at function prologue
1315 ends. The ISA bit is in this context retrieved from the minimal
1316 symbol covering the address requested, which in turn has been
1317 constructed from the binary's symbol table rather than DWARF-2
1318 information. The correct setting of the ISA bit is required for
1319 breakpoint addresses to correctly match against the stop PC.
1321 As line entries can specify relative address adjustments we need to
1322 keep track of the absolute value of the last line address recorded
1323 in line information, so that we can calculate the actual address to
1324 apply the ISA bit adjustment to. We use PC for this tracking and
1325 keep the original address there.
1327 As such relative address adjustments can be odd within compressed
1328 code we need to keep track of the last line address with the ISA
1329 bit adjustment applied too, as the original address may or may not
1330 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1331 the adjusted address there.
1333 For relative address adjustments we then use these variables to
1334 calculate the address intended by line information, which will be
1335 PC-relative, and return an updated adjustment carrying ISA bit
1336 information, which will be ADJ_PC-relative. For absolute address
1337 adjustments we just return the same address that we store in ADJ_PC
1340 As the first line entry can be relative to an implied address value
1341 of 0 we need to have the initial address set up that we store in PC
1342 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1343 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1346 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1348 static CORE_ADDR adj_pc
;
1349 static CORE_ADDR pc
;
1352 pc
= rel
? pc
+ addr
: addr
;
1353 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1354 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1359 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1361 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1362 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1363 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1364 static const char mips_str_call_stub
[] = "__call_stub_";
1365 static const char mips_str_fn_stub
[] = "__fn_stub_";
1367 /* This is used as a PIC thunk prefix. */
1369 static const char mips_str_pic
[] = ".pic.";
1371 /* Return non-zero if the PC is inside a call thunk (aka stub or
1372 trampoline) that should be treated as a temporary frame. */
1375 mips_in_frame_stub (CORE_ADDR pc
)
1377 CORE_ADDR start_addr
;
1380 /* Find the starting address of the function containing the PC. */
1381 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1384 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1385 if (startswith (name
, mips_str_mips16_call_stub
))
1387 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1388 if (startswith (name
, mips_str_call_stub
))
1390 /* If the PC is in __fn_stub_*, this is a call stub. */
1391 if (startswith (name
, mips_str_fn_stub
))
1394 return 0; /* Not a stub. */
1397 /* MIPS believes that the PC has a sign extended value. Perhaps the
1398 all registers should be sign extended for simplicity? */
1401 mips_read_pc (readable_regcache
*regcache
)
1403 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1406 regcache
->cooked_read (regnum
, &pc
);
1411 mips_unwind_pc (struct gdbarch
*gdbarch
, const frame_info_ptr
&next_frame
)
1415 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1416 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1417 intermediate frames. In this case we can get the caller's address
1418 from $ra, or if $ra contains an address within a thunk as well, then
1419 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1420 and thus the caller's address is in $s2. */
1421 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1423 pc
= frame_unwind_register_signed
1424 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1425 if (mips_in_frame_stub (pc
))
1426 pc
= frame_unwind_register_signed
1427 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1433 mips_unwind_sp (struct gdbarch
*gdbarch
, const frame_info_ptr
&next_frame
)
1435 return frame_unwind_register_signed
1436 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1439 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1440 dummy frame. The frame ID's base needs to match the TOS value
1441 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1444 static struct frame_id
1445 mips_dummy_id (struct gdbarch
*gdbarch
, const frame_info_ptr
&this_frame
)
1447 return frame_id_build
1448 (get_frame_register_signed (this_frame
,
1449 gdbarch_num_regs (gdbarch
)
1451 get_frame_pc (this_frame
));
1454 /* Implement the "write_pc" gdbarch method. */
1457 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1459 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1461 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1464 /* Fetch and return instruction from the specified location. Handle
1465 MIPS16/microMIPS as appropriate. */
1468 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1469 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1471 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1472 gdb_byte buf
[MIPS_INSN32_SIZE
];
1480 instlen
= MIPS_INSN16_SIZE
;
1481 addr
= unmake_compact_addr (addr
);
1484 instlen
= MIPS_INSN32_SIZE
;
1487 internal_error (_("invalid ISA"));
1490 err
= target_read_memory (addr
, buf
, instlen
);
1496 memory_error (TARGET_XFER_E_IO
, addr
);
1499 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1502 /* These are the fields of 32 bit mips instructions. */
1503 #define mips32_op(x) (x >> 26)
1504 #define itype_op(x) (x >> 26)
1505 #define itype_rs(x) ((x >> 21) & 0x1f)
1506 #define itype_rt(x) ((x >> 16) & 0x1f)
1507 #define itype_immediate(x) (x & 0xffff)
1509 #define jtype_op(x) (x >> 26)
1510 #define jtype_target(x) (x & 0x03ffffff)
1512 #define rtype_op(x) (x >> 26)
1513 #define rtype_rs(x) ((x >> 21) & 0x1f)
1514 #define rtype_rt(x) ((x >> 16) & 0x1f)
1515 #define rtype_rd(x) ((x >> 11) & 0x1f)
1516 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1517 #define rtype_funct(x) (x & 0x3f)
1519 /* MicroMIPS instruction fields. */
1520 #define micromips_op(x) ((x) >> 10)
1522 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1523 bit and the size respectively of the field extracted. */
1524 #define b0s4_imm(x) ((x) & 0xf)
1525 #define b0s5_imm(x) ((x) & 0x1f)
1526 #define b0s5_reg(x) ((x) & 0x1f)
1527 #define b0s7_imm(x) ((x) & 0x7f)
1528 #define b0s10_imm(x) ((x) & 0x3ff)
1529 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1530 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1531 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1532 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1533 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1534 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1535 #define b6s4_op(x) (((x) >> 6) & 0xf)
1536 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1538 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1539 respectively of the field extracted. */
1540 #define b0s6_op(x) ((x) & 0x3f)
1541 #define b0s11_op(x) ((x) & 0x7ff)
1542 #define b0s12_imm(x) ((x) & 0xfff)
1543 #define b0s16_imm(x) ((x) & 0xffff)
1544 #define b0s26_imm(x) ((x) & 0x3ffffff)
1545 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1546 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1547 #define b12s4_op(x) (((x) >> 12) & 0xf)
1549 /* Return the size in bytes of the instruction INSN encoded in the ISA
1553 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1558 if ((micromips_op (insn
) & 0x4) == 0x4
1559 || (micromips_op (insn
) & 0x7) == 0x0)
1560 return 2 * MIPS_INSN16_SIZE
;
1562 return MIPS_INSN16_SIZE
;
1564 if ((insn
& 0xf800) == 0xf000)
1565 return 2 * MIPS_INSN16_SIZE
;
1567 return MIPS_INSN16_SIZE
;
1569 return MIPS_INSN32_SIZE
;
1571 internal_error (_("invalid ISA"));
1575 mips32_relative_offset (ULONGEST inst
)
1577 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1580 /* Determine the address of the next instruction executed after the INST
1581 floating condition branch instruction at PC. COUNT specifies the
1582 number of the floating condition bits tested by the branch. */
1585 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1586 ULONGEST inst
, CORE_ADDR pc
, int count
)
1588 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1589 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1590 int tf
= itype_rt (inst
) & 1;
1591 int mask
= (1 << count
) - 1;
1596 /* No way to handle; it'll most likely trap anyway. */
1599 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1600 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1602 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1603 pc
+= mips32_relative_offset (inst
);
1610 /* Return nonzero if the gdbarch is an Octeon series. */
1613 is_octeon (struct gdbarch
*gdbarch
)
1615 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1617 return (info
->mach
== bfd_mach_mips_octeon
1618 || info
->mach
== bfd_mach_mips_octeonp
1619 || info
->mach
== bfd_mach_mips_octeon2
);
1622 /* Return true if the OP represents the Octeon's BBIT instruction. */
1625 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1627 if (!is_octeon (gdbarch
))
1629 /* BBIT0 is encoded as LWC2: 110 010. */
1630 /* BBIT032 is encoded as LDC2: 110 110. */
1631 /* BBIT1 is encoded as SWC2: 111 010. */
1632 /* BBIT132 is encoded as SDC2: 111 110. */
1633 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1639 /* Determine where to set a single step breakpoint while considering
1640 branch prediction. */
1643 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1645 struct gdbarch
*gdbarch
= regcache
->arch ();
1648 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1649 op
= itype_op (inst
);
1650 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1654 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1665 goto greater_branch
;
1670 else if (op
== 17 && itype_rs (inst
) == 8)
1671 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1672 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1673 else if (op
== 17 && itype_rs (inst
) == 9
1674 && (itype_rt (inst
) & 2) == 0)
1675 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1676 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1677 else if (op
== 17 && itype_rs (inst
) == 10
1678 && (itype_rt (inst
) & 2) == 0)
1679 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1680 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1683 /* The new PC will be alternate mode. */
1687 reg
= jtype_target (inst
) << 2;
1688 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1689 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1691 else if (is_octeon_bbit_op (op
, gdbarch
))
1695 branch_if
= op
== 58 || op
== 62;
1696 bit
= itype_rt (inst
);
1698 /* Take into account the *32 instructions. */
1699 if (op
== 54 || op
== 62)
1702 if (((regcache_raw_get_signed (regcache
,
1703 itype_rs (inst
)) >> bit
) & 1)
1705 pc
+= mips32_relative_offset (inst
) + 4;
1707 pc
+= 8; /* After the delay slot. */
1711 pc
+= 4; /* Not a branch, next instruction is easy. */
1714 { /* This gets way messy. */
1716 /* Further subdivide into SPECIAL, REGIMM and other. */
1717 switch (op
& 0x07) /* Extract bits 28,27,26. */
1719 case 0: /* SPECIAL */
1720 op
= rtype_funct (inst
);
1725 /* Set PC to that address. */
1726 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1728 case 12: /* SYSCALL */
1730 mips_gdbarch_tdep
*tdep
1731 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1733 if (tdep
->syscall_next_pc
!= NULL
)
1734 pc
= tdep
->syscall_next_pc (get_current_frame ());
1743 break; /* end SPECIAL */
1744 case 1: /* REGIMM */
1746 op
= itype_rt (inst
); /* branch condition */
1751 case 16: /* BLTZAL */
1752 case 18: /* BLTZALL */
1754 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1755 pc
+= mips32_relative_offset (inst
) + 4;
1757 pc
+= 8; /* after the delay slot */
1761 case 17: /* BGEZAL */
1762 case 19: /* BGEZALL */
1763 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1764 pc
+= mips32_relative_offset (inst
) + 4;
1766 pc
+= 8; /* after the delay slot */
1768 case 0x1c: /* BPOSGE32 */
1769 case 0x1e: /* BPOSGE64 */
1771 if (itype_rs (inst
) == 0)
1773 unsigned int pos
= (op
& 2) ? 64 : 32;
1774 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1777 /* No way to handle; it'll most likely trap anyway. */
1780 if ((regcache_raw_get_unsigned (regcache
,
1781 dspctl
) & 0x7f) >= pos
)
1782 pc
+= mips32_relative_offset (inst
);
1787 /* All of the other instructions in the REGIMM category */
1792 break; /* end REGIMM */
1797 reg
= jtype_target (inst
) << 2;
1798 /* Upper four bits get never changed... */
1799 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1802 case 4: /* BEQ, BEQL */
1804 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1805 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1806 pc
+= mips32_relative_offset (inst
) + 4;
1810 case 5: /* BNE, BNEL */
1812 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1813 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1814 pc
+= mips32_relative_offset (inst
) + 4;
1818 case 6: /* BLEZ, BLEZL */
1819 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1820 pc
+= mips32_relative_offset (inst
) + 4;
1826 greater_branch
: /* BGTZ, BGTZL */
1827 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1828 pc
+= mips32_relative_offset (inst
) + 4;
1835 } /* mips32_next_pc */
1837 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1841 micromips_relative_offset7 (ULONGEST insn
)
1843 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1846 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1850 micromips_relative_offset10 (ULONGEST insn
)
1852 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1855 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1859 micromips_relative_offset16 (ULONGEST insn
)
1861 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1864 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1867 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1871 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1872 return mips_insn_size (ISA_MICROMIPS
, insn
);
1875 /* Calculate the address of the next microMIPS instruction to execute
1876 after the INSN coprocessor 1 conditional branch instruction at the
1877 address PC. COUNT denotes the number of coprocessor condition bits
1878 examined by the branch. */
1881 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1882 ULONGEST insn
, CORE_ADDR pc
, int count
)
1884 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1885 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1886 int tf
= b5s5_op (insn
>> 16) & 1;
1887 int mask
= (1 << count
) - 1;
1892 /* No way to handle; it'll most likely trap anyway. */
1895 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1896 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1898 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1899 pc
+= micromips_relative_offset16 (insn
);
1901 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1906 /* Calculate the address of the next microMIPS instruction to execute
1907 after the instruction at the address PC. */
1910 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1912 struct gdbarch
*gdbarch
= regcache
->arch ();
1915 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1916 pc
+= MIPS_INSN16_SIZE
;
1917 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1919 /* 32-bit instructions. */
1920 case 2 * MIPS_INSN16_SIZE
:
1922 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1923 pc
+= MIPS_INSN16_SIZE
;
1924 switch (micromips_op (insn
>> 16))
1926 case 0x00: /* POOL32A: bits 000000 */
1927 switch (b0s6_op (insn
))
1929 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1930 switch (b6s10_ext (insn
))
1932 case 0x3c: /* JALR: 000000 0000111100 111100 */
1933 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1934 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1935 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1936 pc
= regcache_raw_get_signed (regcache
,
1937 b0s5_reg (insn
>> 16));
1939 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1941 mips_gdbarch_tdep
*tdep
1942 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1944 if (tdep
->syscall_next_pc
!= NULL
)
1945 pc
= tdep
->syscall_next_pc (get_current_frame ());
1953 case 0x10: /* POOL32I: bits 010000 */
1954 switch (b5s5_op (insn
>> 16))
1956 case 0x00: /* BLTZ: bits 010000 00000 */
1957 case 0x01: /* BLTZAL: bits 010000 00001 */
1958 case 0x11: /* BLTZALS: bits 010000 10001 */
1959 if (regcache_raw_get_signed (regcache
,
1960 b0s5_reg (insn
>> 16)) < 0)
1961 pc
+= micromips_relative_offset16 (insn
);
1963 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1966 case 0x02: /* BGEZ: bits 010000 00010 */
1967 case 0x03: /* BGEZAL: bits 010000 00011 */
1968 case 0x13: /* BGEZALS: bits 010000 10011 */
1969 if (regcache_raw_get_signed (regcache
,
1970 b0s5_reg (insn
>> 16)) >= 0)
1971 pc
+= micromips_relative_offset16 (insn
);
1973 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1976 case 0x04: /* BLEZ: bits 010000 00100 */
1977 if (regcache_raw_get_signed (regcache
,
1978 b0s5_reg (insn
>> 16)) <= 0)
1979 pc
+= micromips_relative_offset16 (insn
);
1981 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1984 case 0x05: /* BNEZC: bits 010000 00101 */
1985 if (regcache_raw_get_signed (regcache
,
1986 b0s5_reg (insn
>> 16)) != 0)
1987 pc
+= micromips_relative_offset16 (insn
);
1990 case 0x06: /* BGTZ: bits 010000 00110 */
1991 if (regcache_raw_get_signed (regcache
,
1992 b0s5_reg (insn
>> 16)) > 0)
1993 pc
+= micromips_relative_offset16 (insn
);
1995 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1998 case 0x07: /* BEQZC: bits 010000 00111 */
1999 if (regcache_raw_get_signed (regcache
,
2000 b0s5_reg (insn
>> 16)) == 0)
2001 pc
+= micromips_relative_offset16 (insn
);
2004 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2005 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2006 if (((insn
>> 16) & 0x3) == 0x0)
2007 /* BC2F, BC2T: don't know how to handle these. */
2011 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2012 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2014 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2015 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2018 /* No way to handle; it'll most likely trap anyway. */
2021 if ((regcache_raw_get_unsigned (regcache
,
2022 dspctl
) & 0x7f) >= pos
)
2023 pc
+= micromips_relative_offset16 (insn
);
2025 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2029 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2030 /* BC1ANY2F: bits 010000 11100 xxx01 */
2031 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2032 /* BC1ANY2T: bits 010000 11101 xxx01 */
2033 if (((insn
>> 16) & 0x2) == 0x0)
2034 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2035 ((insn
>> 16) & 0x1) + 1);
2038 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2039 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2040 if (((insn
>> 16) & 0x3) == 0x1)
2041 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2046 case 0x1d: /* JALS: bits 011101 */
2047 case 0x35: /* J: bits 110101 */
2048 case 0x3d: /* JAL: bits 111101 */
2049 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2052 case 0x25: /* BEQ: bits 100101 */
2053 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2054 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2055 pc
+= micromips_relative_offset16 (insn
);
2057 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2060 case 0x2d: /* BNE: bits 101101 */
2061 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2062 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2063 pc
+= micromips_relative_offset16 (insn
);
2065 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2068 case 0x3c: /* JALX: bits 111100 */
2069 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2074 /* 16-bit instructions. */
2075 case MIPS_INSN16_SIZE
:
2076 switch (micromips_op (insn
))
2078 case 0x11: /* POOL16C: bits 010001 */
2079 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2080 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2081 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2082 else if (b5s5_op (insn
) == 0x18)
2083 /* JRADDIUSP: bits 010001 11000 */
2084 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2087 case 0x23: /* BEQZ16: bits 100011 */
2089 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2091 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2092 pc
+= micromips_relative_offset7 (insn
);
2094 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2098 case 0x2b: /* BNEZ16: bits 101011 */
2100 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2102 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2103 pc
+= micromips_relative_offset7 (insn
);
2105 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2109 case 0x33: /* B16: bits 110011 */
2110 pc
+= micromips_relative_offset10 (insn
);
2119 /* Decoding the next place to set a breakpoint is irregular for the
2120 mips 16 variant, but fortunately, there fewer instructions. We have
2121 to cope ith extensions for 16 bit instructions and a pair of actual
2122 32 bit instructions. We dont want to set a single step instruction
2123 on the extend instruction either. */
2125 /* Lots of mips16 instruction formats */
2126 /* Predicting jumps requires itype,ritype,i8type
2127 and their extensions extItype,extritype,extI8type. */
2128 enum mips16_inst_fmts
2130 itype
, /* 0 immediate 5,10 */
2131 ritype
, /* 1 5,3,8 */
2132 rrtype
, /* 2 5,3,3,5 */
2133 rritype
, /* 3 5,3,3,5 */
2134 rrrtype
, /* 4 5,3,3,3,2 */
2135 rriatype
, /* 5 5,3,3,1,4 */
2136 shifttype
, /* 6 5,3,3,3,2 */
2137 i8type
, /* 7 5,3,8 */
2138 i8movtype
, /* 8 5,3,3,5 */
2139 i8mov32rtype
, /* 9 5,3,5,3 */
2140 i64type
, /* 10 5,3,8 */
2141 ri64type
, /* 11 5,3,3,5 */
2142 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2143 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2144 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2145 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2146 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2147 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2148 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2149 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2150 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2151 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2153 /* I am heaping all the fields of the formats into one structure and
2154 then, only the fields which are involved in instruction extension. */
2158 unsigned int regx
; /* Function in i8 type. */
2163 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2164 for the bits which make up the immediate extension. */
2167 extended_offset (unsigned int extension
)
2171 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2173 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2175 value
|= extension
& 0x1f; /* Extract 4:0. */
2180 /* Only call this function if you know that this is an extendable
2181 instruction. It won't malfunction, but why make excess remote memory
2182 references? If the immediate operands get sign extended or something,
2183 do it after the extension is performed. */
2184 /* FIXME: Every one of these cases needs to worry about sign extension
2185 when the offset is to be used in relative addressing. */
2188 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2190 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2193 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2194 target_read_memory (pc
, buf
, 2);
2195 return extract_unsigned_integer (buf
, 2, byte_order
);
2199 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2200 unsigned int extension
,
2202 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2207 switch (insn_format
)
2214 value
= extended_offset ((extension
<< 16) | inst
);
2215 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2219 value
= inst
& 0x7ff;
2220 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2229 { /* A register identifier and an offset. */
2230 /* Most of the fields are the same as I type but the
2231 immediate value is of a different length. */
2235 value
= extended_offset ((extension
<< 16) | inst
);
2236 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2240 value
= inst
& 0xff; /* 8 bits */
2241 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2244 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2250 unsigned long value
;
2251 unsigned int nexthalf
;
2252 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2253 value
= value
<< 16;
2254 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2255 /* Low bit still set. */
2263 internal_error (_("bad switch"));
2265 upk
->offset
= offset
;
2271 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2272 and having a signed 16-bit OFFSET. */
2275 add_offset_16 (CORE_ADDR pc
, int offset
)
2277 return pc
+ (offset
<< 1) + 2;
2281 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2282 unsigned int extension
, unsigned int insn
)
2284 struct gdbarch
*gdbarch
= regcache
->arch ();
2285 int op
= (insn
>> 11);
2288 case 2: /* Branch */
2290 struct upk_mips16 upk
;
2291 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2292 pc
= add_offset_16 (pc
, upk
.offset
);
2295 case 3: /* JAL , JALX - Watch out, these are 32 bit
2298 struct upk_mips16 upk
;
2299 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2300 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2301 if ((insn
>> 10) & 0x01) /* Exchange mode */
2302 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2309 struct upk_mips16 upk
;
2311 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2312 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2314 pc
= add_offset_16 (pc
, upk
.offset
);
2321 struct upk_mips16 upk
;
2323 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2324 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2326 pc
= add_offset_16 (pc
, upk
.offset
);
2331 case 12: /* I8 Formats btez btnez */
2333 struct upk_mips16 upk
;
2335 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2336 /* upk.regx contains the opcode */
2337 /* Test register is 24 */
2338 reg
= regcache_raw_get_signed (regcache
, 24);
2339 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2340 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2341 pc
= add_offset_16 (pc
, upk
.offset
);
2346 case 29: /* RR Formats JR, JALR, JALR-RA */
2348 struct upk_mips16 upk
;
2349 /* upk.fmt = rrtype; */
2354 upk
.regx
= (insn
>> 8) & 0x07;
2355 upk
.regy
= (insn
>> 5) & 0x07;
2356 if ((upk
.regy
& 1) == 0)
2357 reg
= mips_reg3_to_reg
[upk
.regx
];
2359 reg
= 31; /* Function return instruction. */
2360 pc
= regcache_raw_get_signed (regcache
, reg
);
2367 /* This is an instruction extension. Fetch the real instruction
2368 (which follows the extension) and decode things based on
2372 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2373 fetch_mips_16 (gdbarch
, pc
));
2386 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2388 struct gdbarch
*gdbarch
= regcache
->arch ();
2389 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2390 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2393 /* The mips_next_pc function supports single_step when the remote
2394 target monitor or stub is not developed enough to do a single_step.
2395 It works by decoding the current instruction and predicting where a
2396 branch will go. This isn't hard because all the data is available.
2397 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2399 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2401 struct gdbarch
*gdbarch
= regcache
->arch ();
2403 if (mips_pc_is_mips16 (gdbarch
, pc
))
2404 return mips16_next_pc (regcache
, pc
);
2405 else if (mips_pc_is_micromips (gdbarch
, pc
))
2406 return micromips_next_pc (regcache
, pc
);
2408 return mips32_next_pc (regcache
, pc
);
2411 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2415 mips16_instruction_is_compact_branch (unsigned short insn
)
2417 switch (insn
& 0xf800)
2420 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2422 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2423 case 0x2800: /* BNEZ */
2424 case 0x2000: /* BEQZ */
2425 case 0x1000: /* B */
2432 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2436 micromips_instruction_is_compact_branch (unsigned short insn
)
2438 switch (micromips_op (insn
))
2440 case 0x11: /* POOL16C: bits 010001 */
2441 return (b5s5_op (insn
) == 0x18
2442 /* JRADDIUSP: bits 010001 11000 */
2443 || b5s5_op (insn
) == 0xd);
2444 /* JRC: bits 010011 01101 */
2445 case 0x10: /* POOL32I: bits 010000 */
2446 return (b5s5_op (insn
) & 0x1d) == 0x5;
2447 /* BEQZC/BNEZC: bits 010000 001x1 */
2453 struct mips_frame_cache
2456 trad_frame_saved_reg
*saved_regs
;
2459 /* Set a register's saved stack address in temp_saved_regs. If an
2460 address has already been set for this register, do nothing; this
2461 way we will only recognize the first save of a given register in a
2464 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2465 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2466 Strictly speaking, only the second range is used as it is only second
2467 range (the ABI instead of ISA registers) that comes into play when finding
2468 saved registers in a frame. */
2471 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2472 int regnum
, CORE_ADDR offset
)
2474 if (this_cache
!= NULL
2475 && this_cache
->saved_regs
[regnum
].is_realreg ()
2476 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2478 this_cache
->saved_regs
[regnum
+ 0
2479 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2480 this_cache
->saved_regs
[regnum
+ 1
2481 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2486 /* Fetch the immediate value from a MIPS16 instruction.
2487 If the previous instruction was an EXTEND, use it to extend
2488 the upper bits of the immediate value. This is a helper function
2489 for mips16_scan_prologue. */
2492 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2493 unsigned short inst
, /* current instruction */
2494 int nbits
, /* number of bits in imm field */
2495 int scale
, /* scale factor to be applied to imm */
2496 int is_signed
) /* is the imm field signed? */
2500 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2502 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2503 if (offset
& 0x8000) /* check for negative extend */
2504 offset
= 0 - (0x10000 - (offset
& 0xffff));
2505 return offset
| (inst
& 0x1f);
2509 int max_imm
= 1 << nbits
;
2510 int mask
= max_imm
- 1;
2511 int sign_bit
= max_imm
>> 1;
2513 offset
= inst
& mask
;
2514 if (is_signed
&& (offset
& sign_bit
))
2515 offset
= 0 - (max_imm
- offset
);
2516 return offset
* scale
;
2521 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2522 the associated FRAME_CACHE if not null.
2523 Return the address of the first instruction past the prologue. */
2526 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2527 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2528 const frame_info_ptr
&this_frame
,
2529 struct mips_frame_cache
*this_cache
)
2531 int prev_non_prologue_insn
= 0;
2532 int this_non_prologue_insn
;
2533 int non_prologue_insns
= 0;
2536 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2538 long frame_offset
= 0; /* Size of stack frame. */
2539 long frame_adjust
= 0; /* Offset of FP from SP. */
2540 int frame_reg
= MIPS_SP_REGNUM
;
2541 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2542 unsigned inst
= 0; /* current instruction */
2543 unsigned entry_inst
= 0; /* the entry instruction */
2544 unsigned save_inst
= 0; /* the save instruction */
2545 int prev_delay_slot
= 0;
2549 int extend_bytes
= 0;
2550 int prev_extend_bytes
= 0;
2551 CORE_ADDR end_prologue_addr
;
2553 /* Can be called when there's no process, and hence when there's no
2555 if (this_frame
!= NULL
)
2556 sp
= get_frame_register_signed (this_frame
,
2557 gdbarch_num_regs (gdbarch
)
2562 if (limit_pc
> start_pc
+ 200)
2563 limit_pc
= start_pc
+ 200;
2566 /* Permit at most one non-prologue non-control-transfer instruction
2567 in the middle which may have been reordered by the compiler for
2569 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2571 this_non_prologue_insn
= 0;
2574 /* Save the previous instruction. If it's an EXTEND, we'll extract
2575 the immediate offset extension from it in mips16_get_imm. */
2578 /* Fetch and decode the instruction. */
2579 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2582 /* Normally we ignore extend instructions. However, if it is
2583 not followed by a valid prologue instruction, then this
2584 instruction is not part of the prologue either. We must
2585 remember in this case to adjust the end_prologue_addr back
2587 if ((inst
& 0xf800) == 0xf000) /* extend */
2589 extend_bytes
= MIPS_INSN16_SIZE
;
2593 prev_extend_bytes
= extend_bytes
;
2596 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2597 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2599 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2600 if (offset
< 0) /* Negative stack adjustment? */
2601 frame_offset
-= offset
;
2603 /* Exit loop if a positive stack adjustment is found, which
2604 usually means that the stack cleanup code in the function
2605 epilogue is reached. */
2608 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2610 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2611 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2612 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2614 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2616 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2617 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2618 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2620 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2622 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2623 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2625 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2627 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2628 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2630 else if (inst
== 0x673d) /* move $s1, $sp */
2635 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2637 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2638 frame_addr
= sp
+ offset
;
2640 frame_adjust
= offset
;
2642 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2644 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2645 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2646 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2648 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2650 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2651 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2652 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2654 else if ((inst
& 0xf81f) == 0xe809
2655 && (inst
& 0x700) != 0x700) /* entry */
2656 entry_inst
= inst
; /* Save for later processing. */
2657 else if ((inst
& 0xff80) == 0x6480) /* save */
2659 save_inst
= inst
; /* Save for later processing. */
2660 if (prev_extend_bytes
) /* extend */
2661 save_inst
|= prev_inst
<< 16;
2663 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2665 /* This instruction is part of the prologue, but we don't
2666 need to do anything special to handle it. */
2668 else if (mips16_instruction_has_delay_slot (inst
, 0))
2669 /* JAL/JALR/JALX/JR */
2671 /* The instruction in the delay slot can be a part
2672 of the prologue, so move forward once more. */
2674 if (mips16_instruction_has_delay_slot (inst
, 1))
2677 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2678 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2683 this_non_prologue_insn
= 1;
2686 non_prologue_insns
+= this_non_prologue_insn
;
2688 /* A jump or branch, or enough non-prologue insns seen? If so,
2689 then we must have reached the end of the prologue by now. */
2690 if (prev_delay_slot
|| non_prologue_insns
> 1
2691 || mips16_instruction_is_compact_branch (inst
))
2694 prev_non_prologue_insn
= this_non_prologue_insn
;
2695 prev_delay_slot
= in_delay_slot
;
2696 prev_pc
= cur_pc
- prev_extend_bytes
;
2699 /* The entry instruction is typically the first instruction in a function,
2700 and it stores registers at offsets relative to the value of the old SP
2701 (before the prologue). But the value of the sp parameter to this
2702 function is the new SP (after the prologue has been executed). So we
2703 can't calculate those offsets until we've seen the entire prologue,
2704 and can calculate what the old SP must have been. */
2705 if (entry_inst
!= 0)
2707 int areg_count
= (entry_inst
>> 8) & 7;
2708 int sreg_count
= (entry_inst
>> 6) & 3;
2710 /* The entry instruction always subtracts 32 from the SP. */
2713 /* Now we can calculate what the SP must have been at the
2714 start of the function prologue. */
2717 /* Check if a0-a3 were saved in the caller's argument save area. */
2718 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2720 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2721 offset
+= mips_abi_regsize (gdbarch
);
2724 /* Check if the ra register was pushed on the stack. */
2726 if (entry_inst
& 0x20)
2728 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2729 offset
-= mips_abi_regsize (gdbarch
);
2732 /* Check if the s0 and s1 registers were pushed on the stack. */
2733 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2735 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2736 offset
-= mips_abi_regsize (gdbarch
);
2740 /* The SAVE instruction is similar to ENTRY, except that defined by the
2741 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2742 size of the frame is specified as an immediate field of instruction
2743 and an extended variation exists which lets additional registers and
2744 frame space to be specified. The instruction always treats registers
2745 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2746 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2748 static int args_table
[16] = {
2749 0, 0, 0, 0, 1, 1, 1, 1,
2750 2, 2, 2, 0, 3, 3, 4, -1,
2752 static int astatic_table
[16] = {
2753 0, 1, 2, 3, 0, 1, 2, 3,
2754 0, 1, 2, 4, 0, 1, 0, -1,
2756 int aregs
= (save_inst
>> 16) & 0xf;
2757 int xsregs
= (save_inst
>> 24) & 0x7;
2758 int args
= args_table
[aregs
];
2759 int astatic
= astatic_table
[aregs
];
2764 warning (_("Invalid number of argument registers encoded in SAVE."));
2769 warning (_("Invalid number of static registers encoded in SAVE."));
2773 /* For standard SAVE the frame size of 0 means 128. */
2774 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2775 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2778 frame_offset
+= frame_size
;
2780 /* Now we can calculate what the SP must have been at the
2781 start of the function prologue. */
2784 /* Check if A0-A3 were saved in the caller's argument save area. */
2785 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2787 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2788 offset
+= mips_abi_regsize (gdbarch
);
2793 /* Check if the RA register was pushed on the stack. */
2794 if (save_inst
& 0x40)
2796 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2797 offset
-= mips_abi_regsize (gdbarch
);
2800 /* Check if the S8 register was pushed on the stack. */
2803 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2804 offset
-= mips_abi_regsize (gdbarch
);
2807 /* Check if S2-S7 were pushed on the stack. */
2808 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2810 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2811 offset
-= mips_abi_regsize (gdbarch
);
2814 /* Check if the S1 register was pushed on the stack. */
2815 if (save_inst
& 0x10)
2817 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2818 offset
-= mips_abi_regsize (gdbarch
);
2820 /* Check if the S0 register was pushed on the stack. */
2821 if (save_inst
& 0x20)
2823 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2824 offset
-= mips_abi_regsize (gdbarch
);
2827 /* Check if A0-A3 were pushed on the stack. */
2828 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2830 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2831 offset
-= mips_abi_regsize (gdbarch
);
2835 if (this_cache
!= NULL
)
2838 (get_frame_register_signed (this_frame
,
2839 gdbarch_num_regs (gdbarch
) + frame_reg
)
2840 + frame_offset
- frame_adjust
);
2841 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2842 be able to get rid of the assignment below, evetually. But it's
2843 still needed for now. */
2844 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2845 + mips_regnum (gdbarch
)->pc
]
2846 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2849 /* Set end_prologue_addr to the address of the instruction immediately
2850 after the last one we scanned. Unless the last one looked like a
2851 non-prologue instruction (and we looked ahead), in which case use
2852 its address instead. */
2853 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2854 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2856 return end_prologue_addr
;
2859 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2860 Procedures that use the 32-bit instruction set are handled by the
2861 mips_insn32 unwinder. */
2863 static struct mips_frame_cache
*
2864 mips_insn16_frame_cache (const frame_info_ptr
&this_frame
, void **this_cache
)
2866 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2867 struct mips_frame_cache
*cache
;
2869 if ((*this_cache
) != NULL
)
2870 return (struct mips_frame_cache
*) (*this_cache
);
2871 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2872 (*this_cache
) = cache
;
2873 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2875 /* Analyze the function prologue. */
2877 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2878 CORE_ADDR start_addr
;
2880 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2881 if (start_addr
== 0)
2882 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2883 /* We can't analyze the prologue if we couldn't find the begining
2885 if (start_addr
== 0)
2888 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2889 (struct mips_frame_cache
*) *this_cache
);
2892 /* gdbarch_sp_regnum contains the value and not the address. */
2893 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2894 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2896 return (struct mips_frame_cache
*) (*this_cache
);
2900 mips_insn16_frame_this_id (const frame_info_ptr
&this_frame
, void **this_cache
,
2901 struct frame_id
*this_id
)
2903 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2905 /* This marks the outermost frame. */
2906 if (info
->base
== 0)
2908 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2911 static struct value
*
2912 mips_insn16_frame_prev_register (const frame_info_ptr
&this_frame
,
2913 void **this_cache
, int regnum
)
2915 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2917 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2921 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2922 const frame_info_ptr
&this_frame
, void **this_cache
)
2924 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2925 CORE_ADDR pc
= get_frame_pc (this_frame
);
2926 if (mips_pc_is_mips16 (gdbarch
, pc
))
2931 static const struct frame_unwind mips_insn16_frame_unwind
=
2933 "mips insn16 prologue",
2935 default_frame_unwind_stop_reason
,
2936 mips_insn16_frame_this_id
,
2937 mips_insn16_frame_prev_register
,
2939 mips_insn16_frame_sniffer
2943 mips_insn16_frame_base_address (const frame_info_ptr
&this_frame
,
2946 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2951 static const struct frame_base mips_insn16_frame_base
=
2953 &mips_insn16_frame_unwind
,
2954 mips_insn16_frame_base_address
,
2955 mips_insn16_frame_base_address
,
2956 mips_insn16_frame_base_address
2959 static const struct frame_base
*
2960 mips_insn16_frame_base_sniffer (const frame_info_ptr
&this_frame
)
2962 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2963 CORE_ADDR pc
= get_frame_pc (this_frame
);
2964 if (mips_pc_is_mips16 (gdbarch
, pc
))
2965 return &mips_insn16_frame_base
;
2970 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2971 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2972 interpreted directly, and then multiplied by 4. */
2975 micromips_decode_imm9 (int imm
)
2977 imm
= (imm
^ 0x100) - 0x100;
2978 if (imm
> -3 && imm
< 2)
2983 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2984 the address of the first instruction past the prologue. */
2987 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2988 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2989 const frame_info_ptr
&this_frame
,
2990 struct mips_frame_cache
*this_cache
)
2992 CORE_ADDR end_prologue_addr
;
2993 int prev_non_prologue_insn
= 0;
2994 int frame_reg
= MIPS_SP_REGNUM
;
2995 int this_non_prologue_insn
;
2996 int non_prologue_insns
= 0;
2997 long frame_offset
= 0; /* Size of stack frame. */
2998 long frame_adjust
= 0; /* Offset of FP from SP. */
2999 int prev_delay_slot
= 0;
3003 ULONGEST insn
; /* current instruction */
3007 long v1_off
= 0; /* The assumption is LUI will replace it. */
3018 /* Can be called when there's no process, and hence when there's no
3020 if (this_frame
!= NULL
)
3021 sp
= get_frame_register_signed (this_frame
,
3022 gdbarch_num_regs (gdbarch
)
3027 if (limit_pc
> start_pc
+ 200)
3028 limit_pc
= start_pc
+ 200;
3031 /* Permit at most one non-prologue non-control-transfer instruction
3032 in the middle which may have been reordered by the compiler for
3034 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3036 this_non_prologue_insn
= 0;
3040 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3041 loc
+= MIPS_INSN16_SIZE
;
3042 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3044 /* 32-bit instructions. */
3045 case 2 * MIPS_INSN16_SIZE
:
3047 insn
|= mips_fetch_instruction (gdbarch
,
3048 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3049 loc
+= MIPS_INSN16_SIZE
;
3050 switch (micromips_op (insn
>> 16))
3052 /* Record $sp/$fp adjustment. */
3053 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3054 case 0x0: /* POOL32A: bits 000000 */
3055 case 0x16: /* POOL32S: bits 010110 */
3056 op
= b0s11_op (insn
);
3057 sreg
= b0s5_reg (insn
>> 16);
3058 treg
= b5s5_reg (insn
>> 16);
3059 dreg
= b11s5_reg (insn
);
3061 /* SUBU: bits 000000 00111010000 */
3062 /* DSUBU: bits 010110 00111010000 */
3063 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3065 /* (D)SUBU $sp, $v1 */
3067 else if (op
!= 0x150
3068 /* ADDU: bits 000000 00101010000 */
3069 /* DADDU: bits 010110 00101010000 */
3070 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3071 this_non_prologue_insn
= 1;
3074 case 0x8: /* POOL32B: bits 001000 */
3075 op
= b12s4_op (insn
);
3076 breg
= b0s5_reg (insn
>> 16);
3077 reglist
= sreg
= b5s5_reg (insn
>> 16);
3078 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3079 if ((op
== 0x9 || op
== 0xc)
3080 /* SWP: bits 001000 1001 */
3081 /* SDP: bits 001000 1100 */
3082 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3083 /* S[DW]P reg,offset($sp) */
3085 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3086 set_reg_offset (gdbarch
, this_cache
,
3088 set_reg_offset (gdbarch
, this_cache
,
3089 sreg
+ 1, sp
+ offset
+ s
);
3091 else if ((op
== 0xd || op
== 0xf)
3092 /* SWM: bits 001000 1101 */
3093 /* SDM: bits 001000 1111 */
3094 && breg
== MIPS_SP_REGNUM
3095 /* SWM reglist,offset($sp) */
3096 && ((reglist
>= 1 && reglist
<= 9)
3097 || (reglist
>= 16 && reglist
<= 25)))
3099 int sreglist
= std::min(reglist
& 0xf, 8);
3101 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3102 for (i
= 0; i
< sreglist
; i
++)
3103 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3104 if ((reglist
& 0xf) > 8)
3105 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3106 if ((reglist
& 0x10) == 0x10)
3107 set_reg_offset (gdbarch
, this_cache
,
3108 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3111 this_non_prologue_insn
= 1;
3114 /* Record $sp/$fp adjustment. */
3115 /* Discard (D)ADDIU $gp used for PIC code. */
3116 case 0xc: /* ADDIU: bits 001100 */
3117 case 0x17: /* DADDIU: bits 010111 */
3118 sreg
= b0s5_reg (insn
>> 16);
3119 dreg
= b5s5_reg (insn
>> 16);
3120 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3121 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3122 /* (D)ADDIU $sp, imm */
3124 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3125 /* (D)ADDIU $fp, $sp, imm */
3127 frame_adjust
= offset
;
3130 else if (sreg
!= 28 || dreg
!= 28)
3131 /* (D)ADDIU $gp, imm */
3132 this_non_prologue_insn
= 1;
3135 /* LUI $v1 is used for larger $sp adjustments. */
3136 /* Discard LUI $gp used for PIC code. */
3137 case 0x10: /* POOL32I: bits 010000 */
3138 if (b5s5_op (insn
>> 16) == 0xd
3139 /* LUI: bits 010000 001101 */
3140 && b0s5_reg (insn
>> 16) == 3)
3142 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3143 else if (b5s5_op (insn
>> 16) != 0xd
3144 /* LUI: bits 010000 001101 */
3145 || b0s5_reg (insn
>> 16) != 28)
3147 this_non_prologue_insn
= 1;
3150 /* ORI $v1 is used for larger $sp adjustments. */
3151 case 0x14: /* ORI: bits 010100 */
3152 sreg
= b0s5_reg (insn
>> 16);
3153 dreg
= b5s5_reg (insn
>> 16);
3154 if (sreg
== 3 && dreg
== 3)
3156 v1_off
|= b0s16_imm (insn
);
3158 this_non_prologue_insn
= 1;
3161 case 0x26: /* SWC1: bits 100110 */
3162 case 0x2e: /* SDC1: bits 101110 */
3163 breg
= b0s5_reg (insn
>> 16);
3164 if (breg
!= MIPS_SP_REGNUM
)
3165 /* S[DW]C1 reg,offset($sp) */
3166 this_non_prologue_insn
= 1;
3169 case 0x36: /* SD: bits 110110 */
3170 case 0x3e: /* SW: bits 111110 */
3171 breg
= b0s5_reg (insn
>> 16);
3172 sreg
= b5s5_reg (insn
>> 16);
3173 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3174 if (breg
== MIPS_SP_REGNUM
)
3175 /* S[DW] reg,offset($sp) */
3176 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3178 this_non_prologue_insn
= 1;
3182 /* The instruction in the delay slot can be a part
3183 of the prologue, so move forward once more. */
3184 if (micromips_instruction_has_delay_slot (insn
, 0))
3187 this_non_prologue_insn
= 1;
3193 /* 16-bit instructions. */
3194 case MIPS_INSN16_SIZE
:
3195 switch (micromips_op (insn
))
3197 case 0x3: /* MOVE: bits 000011 */
3198 sreg
= b0s5_reg (insn
);
3199 dreg
= b5s5_reg (insn
);
3200 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3203 else if ((sreg
& 0x1c) != 0x4)
3204 /* MOVE reg, $a0-$a3 */
3205 this_non_prologue_insn
= 1;
3208 case 0x11: /* POOL16C: bits 010001 */
3209 if (b6s4_op (insn
) == 0x5)
3210 /* SWM: bits 010001 0101 */
3212 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3213 reglist
= b4s2_regl (insn
);
3214 for (i
= 0; i
<= reglist
; i
++)
3215 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3216 set_reg_offset (gdbarch
, this_cache
,
3217 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3220 this_non_prologue_insn
= 1;
3223 case 0x13: /* POOL16D: bits 010011 */
3224 if ((insn
& 0x1) == 0x1)
3225 /* ADDIUSP: bits 010011 1 */
3226 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3227 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3228 /* ADDIUS5: bits 010011 0 */
3229 /* ADDIUS5 $sp, imm */
3230 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3232 this_non_prologue_insn
= 1;
3235 case 0x32: /* SWSP: bits 110010 */
3236 offset
= b0s5_imm (insn
) << 2;
3237 sreg
= b5s5_reg (insn
);
3238 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3242 /* The instruction in the delay slot can be a part
3243 of the prologue, so move forward once more. */
3244 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3247 this_non_prologue_insn
= 1;
3253 frame_offset
-= sp_adj
;
3255 non_prologue_insns
+= this_non_prologue_insn
;
3257 /* A jump or branch, enough non-prologue insns seen or positive
3258 stack adjustment? If so, then we must have reached the end
3259 of the prologue by now. */
3260 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3261 || micromips_instruction_is_compact_branch (insn
))
3264 prev_non_prologue_insn
= this_non_prologue_insn
;
3265 prev_delay_slot
= in_delay_slot
;
3269 if (this_cache
!= NULL
)
3272 (get_frame_register_signed (this_frame
,
3273 gdbarch_num_regs (gdbarch
) + frame_reg
)
3274 + frame_offset
- frame_adjust
);
3275 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3276 be able to get rid of the assignment below, evetually. But it's
3277 still needed for now. */
3278 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3279 + mips_regnum (gdbarch
)->pc
]
3280 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3283 /* Set end_prologue_addr to the address of the instruction immediately
3284 after the last one we scanned. Unless the last one looked like a
3285 non-prologue instruction (and we looked ahead), in which case use
3286 its address instead. */
3288 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3290 return end_prologue_addr
;
3293 /* Heuristic unwinder for procedures using microMIPS instructions.
3294 Procedures that use the 32-bit instruction set are handled by the
3295 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3297 static struct mips_frame_cache
*
3298 mips_micro_frame_cache (const frame_info_ptr
&this_frame
, void **this_cache
)
3300 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3301 struct mips_frame_cache
*cache
;
3303 if ((*this_cache
) != NULL
)
3304 return (struct mips_frame_cache
*) (*this_cache
);
3306 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3307 (*this_cache
) = cache
;
3308 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3310 /* Analyze the function prologue. */
3312 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3313 CORE_ADDR start_addr
;
3315 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3316 if (start_addr
== 0)
3317 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3318 /* We can't analyze the prologue if we couldn't find the begining
3320 if (start_addr
== 0)
3323 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3324 (struct mips_frame_cache
*) *this_cache
);
3327 /* gdbarch_sp_regnum contains the value and not the address. */
3328 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3329 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3331 return (struct mips_frame_cache
*) (*this_cache
);
3335 mips_micro_frame_this_id (const frame_info_ptr
&this_frame
, void **this_cache
,
3336 struct frame_id
*this_id
)
3338 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3340 /* This marks the outermost frame. */
3341 if (info
->base
== 0)
3343 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3346 static struct value
*
3347 mips_micro_frame_prev_register (const frame_info_ptr
&this_frame
,
3348 void **this_cache
, int regnum
)
3350 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3352 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3356 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3357 const frame_info_ptr
&this_frame
, void **this_cache
)
3359 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3360 CORE_ADDR pc
= get_frame_pc (this_frame
);
3362 if (mips_pc_is_micromips (gdbarch
, pc
))
3367 static const struct frame_unwind mips_micro_frame_unwind
=
3369 "mips micro prologue",
3371 default_frame_unwind_stop_reason
,
3372 mips_micro_frame_this_id
,
3373 mips_micro_frame_prev_register
,
3375 mips_micro_frame_sniffer
3379 mips_micro_frame_base_address (const frame_info_ptr
&this_frame
,
3382 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3387 static const struct frame_base mips_micro_frame_base
=
3389 &mips_micro_frame_unwind
,
3390 mips_micro_frame_base_address
,
3391 mips_micro_frame_base_address
,
3392 mips_micro_frame_base_address
3395 static const struct frame_base
*
3396 mips_micro_frame_base_sniffer (const frame_info_ptr
&this_frame
)
3398 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3399 CORE_ADDR pc
= get_frame_pc (this_frame
);
3401 if (mips_pc_is_micromips (gdbarch
, pc
))
3402 return &mips_micro_frame_base
;
3407 /* Mark all the registers as unset in the saved_regs array
3408 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3411 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3413 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3417 const int num_regs
= gdbarch_num_regs (gdbarch
);
3420 /* Reset the register values to their default state. Register i's value
3421 is in register i. */
3422 for (i
= 0; i
< num_regs
; i
++)
3423 this_cache
->saved_regs
[i
].set_realreg (i
);
3427 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3428 the associated FRAME_CACHE if not null.
3429 Return the address of the first instruction past the prologue. */
3432 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3433 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3434 const frame_info_ptr
&this_frame
,
3435 struct mips_frame_cache
*this_cache
)
3437 int prev_non_prologue_insn
;
3438 int this_non_prologue_insn
;
3439 int non_prologue_insns
;
3440 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3442 int prev_delay_slot
;
3447 int frame_reg
= MIPS_SP_REGNUM
;
3449 CORE_ADDR end_prologue_addr
;
3450 int seen_sp_adjust
= 0;
3451 int load_immediate_bytes
= 0;
3453 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3455 /* Can be called when there's no process, and hence when there's no
3457 if (this_frame
!= NULL
)
3458 sp
= get_frame_register_signed (this_frame
,
3459 gdbarch_num_regs (gdbarch
)
3464 if (limit_pc
> start_pc
+ 200)
3465 limit_pc
= start_pc
+ 200;
3468 prev_non_prologue_insn
= 0;
3469 non_prologue_insns
= 0;
3470 prev_delay_slot
= 0;
3473 /* Permit at most one non-prologue non-control-transfer instruction
3474 in the middle which may have been reordered by the compiler for
3477 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3479 unsigned long inst
, high_word
;
3483 this_non_prologue_insn
= 0;
3486 /* Fetch the instruction. */
3487 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3490 /* Save some code by pre-extracting some useful fields. */
3491 high_word
= (inst
>> 16) & 0xffff;
3492 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3493 reg
= high_word
& 0x1f;
3495 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3496 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3497 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3499 if (offset
< 0) /* Negative stack adjustment? */
3500 frame_offset
-= offset
;
3502 /* Exit loop if a positive stack adjustment is found, which
3503 usually means that the stack cleanup code in the function
3504 epilogue is reached. */
3508 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3509 && !regsize_is_64_bits
)
3511 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3513 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3514 && regsize_is_64_bits
)
3516 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3517 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3519 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3521 /* Old gcc frame, r30 is virtual frame pointer. */
3522 if (offset
!= frame_offset
)
3523 frame_addr
= sp
+ offset
;
3524 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3526 unsigned alloca_adjust
;
3529 frame_addr
= get_frame_register_signed
3530 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3533 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3534 if (alloca_adjust
> 0)
3536 /* FP > SP + frame_size. This may be because of
3537 an alloca or somethings similar. Fix sp to
3538 "pre-alloca" value, and try again. */
3539 sp
+= alloca_adjust
;
3540 /* Need to reset the status of all registers. Otherwise,
3541 we will hit a guard that prevents the new address
3542 for each register to be recomputed during the second
3544 reset_saved_regs (gdbarch
, this_cache
);
3549 /* move $30,$sp. With different versions of gas this will be either
3550 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3551 Accept any one of these. */
3552 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3554 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3555 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3557 unsigned alloca_adjust
;
3560 frame_addr
= get_frame_register_signed
3561 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3563 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3564 if (alloca_adjust
> 0)
3566 /* FP > SP + frame_size. This may be because of
3567 an alloca or somethings similar. Fix sp to
3568 "pre-alloca" value, and try again. */
3570 /* Need to reset the status of all registers. Otherwise,
3571 we will hit a guard that prevents the new address
3572 for each register to be recomputed during the second
3574 reset_saved_regs (gdbarch
, this_cache
);
3579 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3580 && !regsize_is_64_bits
)
3582 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3584 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3585 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3586 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3587 || high_word
== 0x3c1c /* lui $gp,n */
3588 || high_word
== 0x279c /* addiu $gp,$gp,n */
3589 || high_word
== 0x679c /* daddiu $gp,$gp,n */
3590 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3591 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3592 || inst
== 0x0399e02d /* daddu $gp,$gp,$t9 */
3593 || inst
== 0x033ce02d /* daddu $gp,$t9,$gp */
3596 /* These instructions are part of the prologue, but we don't
3597 need to do anything special to handle them. */
3599 /* The instructions below load $at or $t0 with an immediate
3600 value in preparation for a stack adjustment via
3601 subu $sp,$sp,[$at,$t0]. These instructions could also
3602 initialize a local variable, so we accept them only before
3603 a stack adjustment instruction was seen. */
3604 else if (!seen_sp_adjust
3606 && (high_word
== 0x3c01 /* lui $at,n */
3607 || high_word
== 0x3c08 /* lui $t0,n */
3608 || high_word
== 0x3421 /* ori $at,$at,n */
3609 || high_word
== 0x3508 /* ori $t0,$t0,n */
3610 || high_word
== 0x3401 /* ori $at,$zero,n */
3611 || high_word
== 0x3408 /* ori $t0,$zero,n */
3614 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3616 /* Check for branches and jumps. The instruction in the delay
3617 slot can be a part of the prologue, so move forward once more. */
3618 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3622 /* This instruction is not an instruction typically found
3623 in a prologue, so we must have reached the end of the
3627 this_non_prologue_insn
= 1;
3630 non_prologue_insns
+= this_non_prologue_insn
;
3632 /* A jump or branch, or enough non-prologue insns seen? If so,
3633 then we must have reached the end of the prologue by now. */
3634 if (prev_delay_slot
|| non_prologue_insns
> 1)
3637 prev_non_prologue_insn
= this_non_prologue_insn
;
3638 prev_delay_slot
= in_delay_slot
;
3642 if (this_cache
!= NULL
)
3645 (get_frame_register_signed (this_frame
,
3646 gdbarch_num_regs (gdbarch
) + frame_reg
)
3648 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3649 this assignment below, eventually. But it's still needed
3651 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3652 + mips_regnum (gdbarch
)->pc
]
3653 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3657 /* Set end_prologue_addr to the address of the instruction immediately
3658 after the last one we scanned. Unless the last one looked like a
3659 non-prologue instruction (and we looked ahead), in which case use
3660 its address instead. */
3662 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3664 /* In a frameless function, we might have incorrectly
3665 skipped some load immediate instructions. Undo the skipping
3666 if the load immediate was not followed by a stack adjustment. */
3667 if (load_immediate_bytes
&& !seen_sp_adjust
)
3668 end_prologue_addr
-= load_immediate_bytes
;
3670 return end_prologue_addr
;
3673 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3674 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3675 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3676 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3678 static struct mips_frame_cache
*
3679 mips_insn32_frame_cache (const frame_info_ptr
&this_frame
, void **this_cache
)
3681 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3682 struct mips_frame_cache
*cache
;
3684 if ((*this_cache
) != NULL
)
3685 return (struct mips_frame_cache
*) (*this_cache
);
3687 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3688 (*this_cache
) = cache
;
3689 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3691 /* Analyze the function prologue. */
3693 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3694 CORE_ADDR start_addr
;
3696 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3697 if (start_addr
== 0)
3698 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3699 /* We can't analyze the prologue if we couldn't find the begining
3701 if (start_addr
== 0)
3704 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3705 (struct mips_frame_cache
*) *this_cache
);
3708 /* gdbarch_sp_regnum contains the value and not the address. */
3709 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3710 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3712 return (struct mips_frame_cache
*) (*this_cache
);
3716 mips_insn32_frame_this_id (const frame_info_ptr
&this_frame
, void **this_cache
,
3717 struct frame_id
*this_id
)
3719 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3721 /* This marks the outermost frame. */
3722 if (info
->base
== 0)
3724 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3727 static struct value
*
3728 mips_insn32_frame_prev_register (const frame_info_ptr
&this_frame
,
3729 void **this_cache
, int regnum
)
3731 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3733 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3737 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3738 const frame_info_ptr
&this_frame
, void **this_cache
)
3740 CORE_ADDR pc
= get_frame_pc (this_frame
);
3741 if (mips_pc_is_mips (pc
))
3746 static const struct frame_unwind mips_insn32_frame_unwind
=
3748 "mips insn32 prologue",
3750 default_frame_unwind_stop_reason
,
3751 mips_insn32_frame_this_id
,
3752 mips_insn32_frame_prev_register
,
3754 mips_insn32_frame_sniffer
3758 mips_insn32_frame_base_address (const frame_info_ptr
&this_frame
,
3761 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3766 static const struct frame_base mips_insn32_frame_base
=
3768 &mips_insn32_frame_unwind
,
3769 mips_insn32_frame_base_address
,
3770 mips_insn32_frame_base_address
,
3771 mips_insn32_frame_base_address
3774 static const struct frame_base
*
3775 mips_insn32_frame_base_sniffer (const frame_info_ptr
&this_frame
)
3777 CORE_ADDR pc
= get_frame_pc (this_frame
);
3778 if (mips_pc_is_mips (pc
))
3779 return &mips_insn32_frame_base
;
3784 static struct trad_frame_cache
*
3785 mips_stub_frame_cache (const frame_info_ptr
&this_frame
, void **this_cache
)
3788 CORE_ADDR start_addr
;
3789 CORE_ADDR stack_addr
;
3790 struct trad_frame_cache
*this_trad_cache
;
3791 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3792 int num_regs
= gdbarch_num_regs (gdbarch
);
3794 if ((*this_cache
) != NULL
)
3795 return (struct trad_frame_cache
*) (*this_cache
);
3796 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3797 (*this_cache
) = this_trad_cache
;
3799 /* The return address is in the link register. */
3800 trad_frame_set_reg_realreg (this_trad_cache
,
3801 gdbarch_pc_regnum (gdbarch
),
3802 num_regs
+ MIPS_RA_REGNUM
);
3804 /* Frame ID, since it's a frameless / stackless function, no stack
3805 space is allocated and SP on entry is the current SP. */
3806 pc
= get_frame_pc (this_frame
);
3807 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3808 stack_addr
= get_frame_register_signed (this_frame
,
3809 num_regs
+ MIPS_SP_REGNUM
);
3810 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3812 /* Assume that the frame's base is the same as the
3814 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3816 return this_trad_cache
;
3820 mips_stub_frame_this_id (const frame_info_ptr
&this_frame
, void **this_cache
,
3821 struct frame_id
*this_id
)
3823 struct trad_frame_cache
*this_trad_cache
3824 = mips_stub_frame_cache (this_frame
, this_cache
);
3825 trad_frame_get_id (this_trad_cache
, this_id
);
3828 static struct value
*
3829 mips_stub_frame_prev_register (const frame_info_ptr
&this_frame
,
3830 void **this_cache
, int regnum
)
3832 struct trad_frame_cache
*this_trad_cache
3833 = mips_stub_frame_cache (this_frame
, this_cache
);
3834 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3838 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3839 const frame_info_ptr
&this_frame
, void **this_cache
)
3842 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3843 struct bound_minimal_symbol msym
;
3845 /* Use the stub unwinder for unreadable code. */
3846 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3849 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3852 /* Calling a PIC function from a non-PIC function passes through a
3853 stub. The stub for foo is named ".pic.foo". */
3854 msym
= lookup_minimal_symbol_by_pc (pc
);
3855 if (msym
.minsym
!= NULL
3856 && msym
.minsym
->linkage_name () != NULL
3857 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3863 static const struct frame_unwind mips_stub_frame_unwind
=
3867 default_frame_unwind_stop_reason
,
3868 mips_stub_frame_this_id
,
3869 mips_stub_frame_prev_register
,
3871 mips_stub_frame_sniffer
3875 mips_stub_frame_base_address (const frame_info_ptr
&this_frame
,
3878 struct trad_frame_cache
*this_trad_cache
3879 = mips_stub_frame_cache (this_frame
, this_cache
);
3880 return trad_frame_get_this_base (this_trad_cache
);
3883 static const struct frame_base mips_stub_frame_base
=
3885 &mips_stub_frame_unwind
,
3886 mips_stub_frame_base_address
,
3887 mips_stub_frame_base_address
,
3888 mips_stub_frame_base_address
3891 static const struct frame_base
*
3892 mips_stub_frame_base_sniffer (const frame_info_ptr
&this_frame
)
3894 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3895 return &mips_stub_frame_base
;
3900 /* mips_addr_bits_remove - remove useless address bits */
3903 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3905 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
3907 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3908 /* This hack is a work-around for existing boards using PMON, the
3909 simulator, and any other 64-bit targets that doesn't have true
3910 64-bit addressing. On these targets, the upper 32 bits of
3911 addresses are ignored by the hardware. Thus, the PC or SP are
3912 likely to have been sign extended to all 1s by instruction
3913 sequences that load 32-bit addresses. For example, a typical
3914 piece of code that loads an address is this:
3916 lui $r2, <upper 16 bits>
3917 ori $r2, <lower 16 bits>
3919 But the lui sign-extends the value such that the upper 32 bits
3920 may be all 1s. The workaround is simply to mask off these
3921 bits. In the future, gcc may be changed to support true 64-bit
3922 addressing, and this masking will have to be disabled. */
3923 return addr
&= 0xffffffffUL
;
3929 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3930 instruction and ending with a SC/SCD instruction. If such a sequence
3931 is found, attempt to step through it. A breakpoint is placed at the end of
3934 /* Instructions used during single-stepping of atomic sequences, standard
3936 #define LL_OPCODE 0x30
3937 #define LLD_OPCODE 0x34
3938 #define SC_OPCODE 0x38
3939 #define SCD_OPCODE 0x3c
3941 static std::vector
<CORE_ADDR
>
3942 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3944 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3946 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3950 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3951 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3953 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3954 /* Assume all atomic sequences start with a ll/lld instruction. */
3955 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3958 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3960 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3963 loc
+= MIPS_INSN32_SIZE
;
3964 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3966 /* Assume that there is at most one branch in the atomic
3967 sequence. If a branch is found, put a breakpoint in its
3968 destination address. */
3969 switch (itype_op (insn
))
3971 case 0: /* SPECIAL */
3972 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3973 return {}; /* fallback to the standard single-step code. */
3975 case 1: /* REGIMM */
3976 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3977 || ((itype_rt (insn
) & 0x1e) == 0
3978 && itype_rs (insn
) == 0)); /* BPOSGE* */
3982 return {}; /* fallback to the standard single-step code. */
3989 case 22: /* BLEZL */
3990 case 23: /* BGTTL */
3994 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3995 && (itype_rt (insn
) & 0x2) == 0);
3996 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
4001 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4006 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4007 if (last_breakpoint
>= 1)
4008 return {}; /* More than one branch found, fallback to the
4009 standard single-step code. */
4010 breaks
[1] = branch_bp
;
4014 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4018 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4019 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4022 loc
+= MIPS_INSN32_SIZE
;
4024 /* Insert a breakpoint right after the end of the atomic sequence. */
4027 /* Check for duplicated breakpoints. Check also for a breakpoint
4028 placed (branch instruction's destination) in the atomic sequence. */
4029 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4030 last_breakpoint
= 0;
4032 std::vector
<CORE_ADDR
> next_pcs
;
4034 /* Effectively inserts the breakpoints. */
4035 for (index
= 0; index
<= last_breakpoint
; index
++)
4036 next_pcs
.push_back (breaks
[index
]);
4041 static std::vector
<CORE_ADDR
>
4042 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4045 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4046 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4047 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4048 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4056 /* Assume all atomic sequences start with a ll/lld instruction. */
4057 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4058 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4060 loc
+= MIPS_INSN16_SIZE
;
4062 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4063 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4065 loc
+= MIPS_INSN16_SIZE
;
4067 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4068 that no atomic sequence is longer than "atomic_sequence_length"
4070 for (insn_count
= 0;
4071 !sc_found
&& insn_count
< atomic_sequence_length
;
4076 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4077 loc
+= MIPS_INSN16_SIZE
;
4079 /* Assume that there is at most one conditional branch in the
4080 atomic sequence. If a branch is found, put a breakpoint in
4081 its destination address. */
4082 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4084 /* 32-bit instructions. */
4085 case 2 * MIPS_INSN16_SIZE
:
4086 switch (micromips_op (insn
))
4088 case 0x10: /* POOL32I: bits 010000 */
4089 if ((b5s5_op (insn
) & 0x18) != 0x0
4090 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4091 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4092 && (b5s5_op (insn
) & 0x1d) != 0x11
4093 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4094 && ((b5s5_op (insn
) & 0x1e) != 0x14
4095 || (insn
& 0x3) != 0x0)
4096 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4097 && (b5s5_op (insn
) & 0x1e) != 0x1a
4098 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4099 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4100 || (insn
& 0x3) != 0x0)
4101 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4102 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4103 || (insn
& 0x3) != 0x1))
4104 /* BC1ANY*: bits 010000 111xx xxx01 */
4108 case 0x25: /* BEQ: bits 100101 */
4109 case 0x2d: /* BNE: bits 101101 */
4111 insn
|= mips_fetch_instruction (gdbarch
,
4112 ISA_MICROMIPS
, loc
, NULL
);
4113 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4114 + micromips_relative_offset16 (insn
));
4118 case 0x00: /* POOL32A: bits 000000 */
4120 insn
|= mips_fetch_instruction (gdbarch
,
4121 ISA_MICROMIPS
, loc
, NULL
);
4122 if (b0s6_op (insn
) != 0x3c
4123 /* POOL32Axf: bits 000000 ... 111100 */
4124 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4125 /* JALR, JALR.HB: 000000 000x111100 111100 */
4126 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4130 case 0x1d: /* JALS: bits 011101 */
4131 case 0x35: /* J: bits 110101 */
4132 case 0x3d: /* JAL: bits 111101 */
4133 case 0x3c: /* JALX: bits 111100 */
4134 return {}; /* Fall back to the standard single-step code. */
4136 case 0x18: /* POOL32C: bits 011000 */
4137 if ((b12s4_op (insn
) & 0xb) == 0xb)
4138 /* SC, SCD: bits 011000 1x11 */
4142 loc
+= MIPS_INSN16_SIZE
;
4145 /* 16-bit instructions. */
4146 case MIPS_INSN16_SIZE
:
4147 switch (micromips_op (insn
))
4149 case 0x23: /* BEQZ16: bits 100011 */
4150 case 0x2b: /* BNEZ16: bits 101011 */
4151 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4155 case 0x11: /* POOL16C: bits 010001 */
4156 if ((b5s5_op (insn
) & 0x1c) != 0xc
4157 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4158 && b5s5_op (insn
) != 0x18)
4159 /* JRADDIUSP: bits 010001 11000 */
4161 return {}; /* Fall back to the standard single-step code. */
4163 case 0x33: /* B16: bits 110011 */
4164 return {}; /* Fall back to the standard single-step code. */
4170 if (last_breakpoint
>= 1)
4171 return {}; /* More than one branch found, fallback to the
4172 standard single-step code. */
4173 breaks
[1] = branch_bp
;
4180 /* Insert a breakpoint right after the end of the atomic sequence. */
4183 /* Check for duplicated breakpoints. Check also for a breakpoint
4184 placed (branch instruction's destination) in the atomic sequence */
4185 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4186 last_breakpoint
= 0;
4188 std::vector
<CORE_ADDR
> next_pcs
;
4190 /* Effectively inserts the breakpoints. */
4191 for (index
= 0; index
<= last_breakpoint
; index
++)
4192 next_pcs
.push_back (breaks
[index
]);
4197 static std::vector
<CORE_ADDR
>
4198 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4200 if (mips_pc_is_mips (pc
))
4201 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4202 else if (mips_pc_is_micromips (gdbarch
, pc
))
4203 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4208 /* mips_software_single_step() is called just before we want to resume
4209 the inferior, if we want to single-step it but there is no hardware
4210 or kernel single-step support (MIPS on GNU/Linux for example). We find
4211 the target of the coming instruction and breakpoint it. */
4213 std::vector
<CORE_ADDR
>
4214 mips_software_single_step (struct regcache
*regcache
)
4216 struct gdbarch
*gdbarch
= regcache
->arch ();
4217 CORE_ADDR pc
, next_pc
;
4219 pc
= regcache_read_pc (regcache
);
4220 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4222 if (!next_pcs
.empty ())
4225 next_pc
= mips_next_pc (regcache
, pc
);
4230 /* Test whether the PC points to the return instruction at the
4231 end of a function. */
4234 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4239 /* This used to check for MIPS16, but this piece of code is never
4240 called for MIPS16 functions. And likewise microMIPS ones. */
4241 gdb_assert (mips_pc_is_mips (pc
));
4243 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4245 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4249 /* This fencepost looks highly suspicious to me. Removing it also
4250 seems suspicious as it could affect remote debugging across serial
4254 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4260 struct inferior
*inf
;
4262 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4264 fence
= start_pc
- heuristic_fence_post
;
4268 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4269 fence
= VM_MIN_ADDRESS
;
4271 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4273 inf
= current_inferior ();
4275 /* Search back for previous return. */
4276 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4277 if (start_pc
< fence
)
4279 /* It's not clear to me why we reach this point when
4280 stop_soon, but with this test, at least we
4281 don't print out warnings for every child forked (eg, on
4282 decstation). 22apr93 rich@cygnus.com. */
4283 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4285 static int blurb_printed
= 0;
4287 warning (_("GDB can't find the start of the function at %s."),
4288 paddress (gdbarch
, pc
));
4292 /* This actually happens frequently in embedded
4293 development, when you first connect to a board
4294 and your stack pointer and pc are nowhere in
4295 particular. This message needs to give people
4296 in that situation enough information to
4297 determine that it's no big deal. */
4299 GDB is unable to find the start of the function at %s\n\
4300 and thus can't determine the size of that function's stack frame.\n\
4301 This means that GDB may be unable to access that stack frame, or\n\
4302 the frames below it.\n\
4303 This problem is most likely caused by an invalid program counter or\n\
4305 However, if you think GDB should simply search farther back\n\
4306 from %s for code which looks like the beginning of a\n\
4307 function, you can increase the range of the search using the `set\n\
4308 heuristic-fence-post' command.\n",
4309 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4316 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4318 unsigned short inst
;
4320 /* On MIPS16, any one of the following is likely to be the
4321 start of a function:
4327 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4328 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4329 if ((inst
& 0xff80) == 0x6480) /* save */
4331 if (start_pc
- instlen
>= fence
)
4333 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4334 start_pc
- instlen
, NULL
);
4335 if ((inst
& 0xf800) == 0xf000) /* extend */
4336 start_pc
-= instlen
;
4340 else if (((inst
& 0xf81f) == 0xe809
4341 && (inst
& 0x700) != 0x700) /* entry */
4342 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4343 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4344 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4346 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4347 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4352 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4360 /* On microMIPS, any one of the following is likely to be the
4361 start of a function:
4365 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4366 switch (micromips_op (insn
))
4368 case 0xc: /* ADDIU: bits 001100 */
4369 case 0x17: /* DADDIU: bits 010111 */
4370 sreg
= b0s5_reg (insn
);
4371 dreg
= b5s5_reg (insn
);
4373 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4374 pc
+ MIPS_INSN16_SIZE
, NULL
);
4375 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4376 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4377 /* (D)ADDIU $sp, imm */
4382 case 0x10: /* POOL32I: bits 010000 */
4383 if (b5s5_op (insn
) == 0xd
4384 /* LUI: bits 010000 001101 */
4385 && b0s5_reg (insn
>> 16) == 28)
4390 case 0x13: /* POOL16D: bits 010011 */
4391 if ((insn
& 0x1) == 0x1)
4392 /* ADDIUSP: bits 010011 1 */
4394 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4400 /* ADDIUS5: bits 010011 0 */
4402 dreg
= b5s5_reg (insn
);
4403 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4404 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4405 /* ADDIUS5 $sp, -imm */
4413 else if (mips_about_to_return (gdbarch
, start_pc
))
4415 /* Skip return and its delay slot. */
4416 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4423 struct mips_objfile_private
4429 /* According to the current ABI, should the type be passed in a
4430 floating-point register (assuming that there is space)? When there
4431 is no FPU, FP are not even considered as possible candidates for
4432 FP registers and, consequently this returns false - forces FP
4433 arguments into integer registers. */
4436 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4437 struct type
*arg_type
)
4439 return ((typecode
== TYPE_CODE_FLT
4440 || (mips_eabi (gdbarch
)
4441 && (typecode
== TYPE_CODE_STRUCT
4442 || typecode
== TYPE_CODE_UNION
)
4443 && arg_type
->num_fields () == 1
4444 && check_typedef (arg_type
->field (0).type ())->code ()
4446 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4449 /* On o32, argument passing in GPRs depends on the alignment of the type being
4450 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4453 mips_type_needs_double_align (struct type
*type
)
4455 enum type_code typecode
= type
->code ();
4457 if (typecode
== TYPE_CODE_FLT
&& type
->length () == 8)
4459 else if (typecode
== TYPE_CODE_STRUCT
)
4461 if (type
->num_fields () < 1)
4463 return mips_type_needs_double_align (type
->field (0).type ());
4465 else if (typecode
== TYPE_CODE_UNION
)
4469 n
= type
->num_fields ();
4470 for (i
= 0; i
< n
; i
++)
4471 if (mips_type_needs_double_align (type
->field (i
).type ()))
4478 /* Adjust the address downward (direction of stack growth) so that it
4479 is correctly aligned for a new stack frame. */
4481 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4483 return align_down (addr
, 16);
4486 /* Implement the "push_dummy_code" gdbarch method. */
4489 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4490 CORE_ADDR funaddr
, struct value
**args
,
4491 int nargs
, struct type
*value_type
,
4492 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4493 struct regcache
*regcache
)
4495 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4499 /* Reserve enough room on the stack for our breakpoint instruction. */
4500 bp_slot
= sp
- sizeof (nop_insn
);
4502 /* Return to microMIPS mode if calling microMIPS code to avoid
4503 triggering an address error exception on processors that only
4504 support microMIPS execution. */
4505 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4506 ? make_compact_addr (bp_slot
) : bp_slot
);
4508 /* The breakpoint layer automatically adjusts the address of
4509 breakpoints inserted in a branch delay slot. With enough
4510 bad luck, the 4 bytes located just before our breakpoint
4511 instruction could look like a branch instruction, and thus
4512 trigger the adjustement, and break the function call entirely.
4513 So, we reserve those 4 bytes and write a nop instruction
4514 to prevent that from happening. */
4515 nop_addr
= bp_slot
- sizeof (nop_insn
);
4516 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4517 sp
= mips_frame_align (gdbarch
, nop_addr
);
4519 /* Inferior resumes at the function entry point. */
4526 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4527 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4528 int nargs
, struct value
**args
, CORE_ADDR sp
,
4529 function_call_return_method return_method
,
4530 CORE_ADDR struct_addr
)
4536 int stack_offset
= 0;
4537 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4538 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4539 int abi_regsize
= mips_abi_regsize (gdbarch
);
4541 /* For shared libraries, "t9" needs to point at the function
4543 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4545 /* Set the return address register to point to the entry point of
4546 the program, where a breakpoint lies in wait. */
4547 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4549 /* First ensure that the stack and structure return address (if any)
4550 are properly aligned. The stack has to be at least 64-bit
4551 aligned even on 32-bit machines, because doubles must be 64-bit
4552 aligned. For n32 and n64, stack frames need to be 128-bit
4553 aligned, so we round to this widest known alignment. */
4555 sp
= align_down (sp
, 16);
4556 struct_addr
= align_down (struct_addr
, 16);
4558 /* Now make space on the stack for the args. We allocate more
4559 than necessary for EABI, because the first few arguments are
4560 passed in registers, but that's OK. */
4561 for (argnum
= 0; argnum
< nargs
; argnum
++)
4562 arg_space
+= align_up (args
[argnum
]->type ()->length (),
4564 sp
-= align_up (arg_space
, 16);
4567 gdb_printf (gdb_stdlog
,
4568 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4569 paddress (gdbarch
, sp
),
4570 (long) align_up (arg_space
, 16));
4572 /* Initialize the integer and float register pointers. */
4573 argreg
= MIPS_A0_REGNUM
;
4574 float_argreg
= mips_fpa0_regnum (gdbarch
);
4576 /* The struct_return pointer occupies the first parameter-passing reg. */
4577 if (return_method
== return_method_struct
)
4580 gdb_printf (gdb_stdlog
,
4581 "mips_eabi_push_dummy_call: "
4582 "struct_return reg=%d %s\n",
4583 argreg
, paddress (gdbarch
, struct_addr
));
4584 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4587 /* Now load as many as possible of the first arguments into
4588 registers, and push the rest onto the stack. Loop thru args
4589 from first to last. */
4590 for (argnum
= 0; argnum
< nargs
; argnum
++)
4592 const gdb_byte
*val
;
4593 /* This holds the address of structures that are passed by
4595 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4596 struct value
*arg
= args
[argnum
];
4597 struct type
*arg_type
= check_typedef (arg
->type ());
4598 int len
= arg_type
->length ();
4599 enum type_code typecode
= arg_type
->code ();
4602 gdb_printf (gdb_stdlog
,
4603 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4604 argnum
+ 1, len
, (int) typecode
);
4606 /* The EABI passes structures that do not fit in a register by
4608 if (len
> abi_regsize
4609 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4611 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4612 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4614 typecode
= TYPE_CODE_PTR
;
4618 gdb_printf (gdb_stdlog
, " push");
4621 val
= arg
->contents ().data ();
4623 /* 32-bit ABIs always start floating point arguments in an
4624 even-numbered floating point register. Round the FP register
4625 up before the check to see if there are any FP registers
4626 left. Non MIPS_EABI targets also pass the FP in the integer
4627 registers so also round up normal registers. */
4628 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4630 if ((float_argreg
& 1))
4634 /* Floating point arguments passed in registers have to be
4635 treated specially. On 32-bit architectures, doubles
4636 are passed in register pairs; the even register gets
4637 the low word, and the odd register gets the high word.
4638 On non-EABI processors, the first two floating point arguments are
4639 also copied to general registers, because MIPS16 functions
4640 don't use float registers for arguments. This duplication of
4641 arguments in general registers can't hurt non-MIPS16 functions
4642 because those registers are normally skipped. */
4643 /* MIPS_EABI squeezes a struct that contains a single floating
4644 point value into an FP register instead of pushing it onto the
4646 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4647 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4649 /* EABI32 will pass doubles in consecutive registers, even on
4650 64-bit cores. At one time, we used to check the size of
4651 `float_argreg' to determine whether or not to pass doubles
4652 in consecutive registers, but this is not sufficient for
4653 making the ABI determination. */
4654 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4656 int low_offset
= gdbarch_byte_order (gdbarch
)
4657 == BFD_ENDIAN_BIG
? 4 : 0;
4660 /* Write the low word of the double to the even register(s). */
4661 regval
= extract_signed_integer (val
+ low_offset
,
4664 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4665 float_argreg
, phex (regval
, 4));
4666 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4668 /* Write the high word of the double to the odd register(s). */
4669 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4672 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4673 float_argreg
, phex (regval
, 4));
4674 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4678 /* This is a floating point value that fits entirely
4679 in a single register. */
4680 /* On 32 bit ABI's the float_argreg is further adjusted
4681 above to ensure that it is even register aligned. */
4682 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4684 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4685 float_argreg
, phex (regval
, len
));
4686 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4691 /* Copy the argument to general registers or the stack in
4692 register-sized pieces. Large arguments are split between
4693 registers and stack. */
4694 /* Note: structs whose size is not a multiple of abi_regsize
4695 are treated specially: Irix cc passes
4696 them in registers where gcc sometimes puts them on the
4697 stack. For maximum compatibility, we will put them in
4699 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4701 /* Note: Floating-point values that didn't fit into an FP
4702 register are only written to memory. */
4705 /* Remember if the argument was written to the stack. */
4706 int stack_used_p
= 0;
4707 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4710 gdb_printf (gdb_stdlog
, " -- partial=%d",
4713 /* Write this portion of the argument to the stack. */
4714 if (argreg
> mips_last_arg_regnum (gdbarch
)
4716 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4718 /* Should shorter than int integer values be
4719 promoted to int before being stored? */
4720 int longword_offset
= 0;
4723 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4725 if (abi_regsize
== 8
4726 && (typecode
== TYPE_CODE_INT
4727 || typecode
== TYPE_CODE_PTR
4728 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4729 longword_offset
= abi_regsize
- len
;
4730 else if ((typecode
== TYPE_CODE_STRUCT
4731 || typecode
== TYPE_CODE_UNION
)
4732 && arg_type
->length () < abi_regsize
)
4733 longword_offset
= abi_regsize
- len
;
4738 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
4739 paddress (gdbarch
, stack_offset
));
4740 gdb_printf (gdb_stdlog
, " longword_offset=%s",
4741 paddress (gdbarch
, longword_offset
));
4744 addr
= sp
+ stack_offset
+ longword_offset
;
4749 gdb_printf (gdb_stdlog
, " @%s ",
4750 paddress (gdbarch
, addr
));
4751 for (i
= 0; i
< partial_len
; i
++)
4753 gdb_printf (gdb_stdlog
, "%02x",
4757 write_memory (addr
, val
, partial_len
);
4760 /* Note!!! This is NOT an else clause. Odd sized
4761 structs may go thru BOTH paths. Floating point
4762 arguments will not. */
4763 /* Write this portion of the argument to a general
4764 purpose register. */
4765 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4766 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4769 extract_signed_integer (val
, partial_len
, byte_order
);
4772 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
4774 phex (regval
, abi_regsize
));
4775 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4782 /* Compute the offset into the stack at which we will
4783 copy the next parameter.
4785 In the new EABI (and the NABI32), the stack_offset
4786 only needs to be adjusted when it has been used. */
4789 stack_offset
+= align_up (partial_len
, abi_regsize
);
4793 gdb_printf (gdb_stdlog
, "\n");
4796 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4798 /* Return adjusted stack pointer. */
4802 /* Determine the return value convention being used. */
4804 static enum return_value_convention
4805 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4806 struct type
*type
, struct regcache
*regcache
,
4807 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4809 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
4810 int fp_return_type
= 0;
4811 int offset
, regnum
, xfer
;
4813 if (type
->length () > 2 * mips_abi_regsize (gdbarch
))
4814 return RETURN_VALUE_STRUCT_CONVENTION
;
4816 /* Floating point type? */
4817 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4819 if (type
->code () == TYPE_CODE_FLT
)
4821 /* Structs with a single field of float type
4822 are returned in a floating point register. */
4823 if ((type
->code () == TYPE_CODE_STRUCT
4824 || type
->code () == TYPE_CODE_UNION
)
4825 && type
->num_fields () == 1)
4827 struct type
*fieldtype
= type
->field (0).type ();
4829 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4836 /* A floating-point value belongs in the least significant part
4839 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
4840 regnum
= mips_regnum (gdbarch
)->fp0
;
4844 /* An integer value goes in V0/V1. */
4846 gdb_printf (gdb_stderr
, "Return scalar in $v0\n");
4847 regnum
= MIPS_V0_REGNUM
;
4850 offset
< type
->length ();
4851 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4853 xfer
= mips_abi_regsize (gdbarch
);
4854 if (offset
+ xfer
> type
->length ())
4855 xfer
= type
->length () - offset
;
4856 mips_xfer_register (gdbarch
, regcache
,
4857 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4858 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4862 return RETURN_VALUE_REGISTER_CONVENTION
;
4866 /* N32/N64 ABI stuff. */
4868 /* Search for a naturally aligned double at OFFSET inside a struct
4869 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4873 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4878 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4881 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4884 if (arg_type
->length () < offset
+ MIPS64_REGSIZE
)
4887 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4890 struct type
*field_type
;
4892 /* We're only looking at normal fields. */
4893 if (arg_type
->field (i
).is_static ()
4894 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4897 /* If we have gone past the offset, there is no double to pass. */
4898 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4902 field_type
= check_typedef (arg_type
->field (i
).type ());
4904 /* If this field is entirely before the requested offset, go
4905 on to the next one. */
4906 if (pos
+ field_type
->length () <= offset
)
4909 /* If this is our special aligned double, we can stop. */
4910 if (field_type
->code () == TYPE_CODE_FLT
4911 && field_type
->length () == MIPS64_REGSIZE
)
4914 /* This field starts at or before the requested offset, and
4915 overlaps it. If it is a structure, recurse inwards. */
4916 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4923 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4924 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4925 int nargs
, struct value
**args
, CORE_ADDR sp
,
4926 function_call_return_method return_method
,
4927 CORE_ADDR struct_addr
)
4933 int stack_offset
= 0;
4934 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4935 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4937 /* For shared libraries, "t9" needs to point at the function
4939 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4941 /* Set the return address register to point to the entry point of
4942 the program, where a breakpoint lies in wait. */
4943 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4945 /* First ensure that the stack and structure return address (if any)
4946 are properly aligned. The stack has to be at least 64-bit
4947 aligned even on 32-bit machines, because doubles must be 64-bit
4948 aligned. For n32 and n64, stack frames need to be 128-bit
4949 aligned, so we round to this widest known alignment. */
4951 sp
= align_down (sp
, 16);
4952 struct_addr
= align_down (struct_addr
, 16);
4954 /* Now make space on the stack for the args. */
4955 for (argnum
= 0; argnum
< nargs
; argnum
++)
4956 arg_space
+= align_up (args
[argnum
]->type ()->length (),
4958 sp
-= align_up (arg_space
, 16);
4961 gdb_printf (gdb_stdlog
,
4962 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4963 paddress (gdbarch
, sp
),
4964 (long) align_up (arg_space
, 16));
4966 /* Initialize the integer and float register pointers. */
4967 argreg
= MIPS_A0_REGNUM
;
4968 float_argreg
= mips_fpa0_regnum (gdbarch
);
4970 /* The struct_return pointer occupies the first parameter-passing reg. */
4971 if (return_method
== return_method_struct
)
4974 gdb_printf (gdb_stdlog
,
4975 "mips_n32n64_push_dummy_call: "
4976 "struct_return reg=%d %s\n",
4977 argreg
, paddress (gdbarch
, struct_addr
));
4978 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4981 /* Now load as many as possible of the first arguments into
4982 registers, and push the rest onto the stack. Loop thru args
4983 from first to last. */
4984 for (argnum
= 0; argnum
< nargs
; argnum
++)
4986 const gdb_byte
*val
;
4987 struct value
*arg
= args
[argnum
];
4988 struct type
*arg_type
= check_typedef (arg
->type ());
4989 int len
= arg_type
->length ();
4990 enum type_code typecode
= arg_type
->code ();
4993 gdb_printf (gdb_stdlog
,
4994 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4995 argnum
+ 1, len
, (int) typecode
);
4997 val
= arg
->contents ().data ();
4999 /* A 128-bit long double value requires an even-odd pair of
5000 floating-point registers. */
5002 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5003 && (float_argreg
& 1))
5009 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5010 && argreg
<= mips_last_arg_regnum (gdbarch
))
5012 /* This is a floating point value that fits entirely
5013 in a single register or a pair of registers. */
5014 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5015 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5017 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5018 float_argreg
, phex (regval
, reglen
));
5019 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5022 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5023 argreg
, phex (regval
, reglen
));
5024 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5029 regval
= extract_unsigned_integer (val
+ reglen
,
5030 reglen
, byte_order
);
5032 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5033 float_argreg
, phex (regval
, reglen
));
5034 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5037 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5038 argreg
, phex (regval
, reglen
));
5039 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5046 /* Copy the argument to general registers or the stack in
5047 register-sized pieces. Large arguments are split between
5048 registers and stack. */
5049 /* For N32/N64, structs, unions, or other composite types are
5050 treated as a sequence of doublewords, and are passed in integer
5051 or floating point registers as though they were simple scalar
5052 parameters to the extent that they fit, with any excess on the
5053 stack packed according to the normal memory layout of the
5055 The caller does not reserve space for the register arguments;
5056 the callee is responsible for reserving it if required. */
5057 /* Note: Floating-point values that didn't fit into an FP
5058 register are only written to memory. */
5061 /* Remember if the argument was written to the stack. */
5062 int stack_used_p
= 0;
5063 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5066 gdb_printf (gdb_stdlog
, " -- partial=%d",
5069 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5070 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5072 /* Write this portion of the argument to the stack. */
5073 if (argreg
> mips_last_arg_regnum (gdbarch
))
5075 /* Should shorter than int integer values be
5076 promoted to int before being stored? */
5077 int longword_offset
= 0;
5080 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5082 if ((typecode
== TYPE_CODE_INT
5083 || typecode
== TYPE_CODE_PTR
)
5085 longword_offset
= MIPS64_REGSIZE
- len
;
5090 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5091 paddress (gdbarch
, stack_offset
));
5092 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5093 paddress (gdbarch
, longword_offset
));
5096 addr
= sp
+ stack_offset
+ longword_offset
;
5101 gdb_printf (gdb_stdlog
, " @%s ",
5102 paddress (gdbarch
, addr
));
5103 for (i
= 0; i
< partial_len
; i
++)
5105 gdb_printf (gdb_stdlog
, "%02x",
5109 write_memory (addr
, val
, partial_len
);
5112 /* Note!!! This is NOT an else clause. Odd sized
5113 structs may go thru BOTH paths. */
5114 /* Write this portion of the argument to a general
5115 purpose register. */
5116 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5120 /* Sign extend pointers, 32-bit integers and signed
5121 16-bit and 8-bit integers; everything else is taken
5124 if ((partial_len
== 4
5125 && (typecode
== TYPE_CODE_PTR
5126 || typecode
== TYPE_CODE_INT
))
5128 && typecode
== TYPE_CODE_INT
5129 && !arg_type
->is_unsigned ()))
5130 regval
= extract_signed_integer (val
, partial_len
,
5133 regval
= extract_unsigned_integer (val
, partial_len
,
5136 /* A non-floating-point argument being passed in a
5137 general register. If a struct or union, and if
5138 the remaining length is smaller than the register
5139 size, we have to adjust the register value on
5142 It does not seem to be necessary to do the
5143 same for integral types. */
5145 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5146 && partial_len
< MIPS64_REGSIZE
5147 && (typecode
== TYPE_CODE_STRUCT
5148 || typecode
== TYPE_CODE_UNION
))
5149 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5153 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5155 phex (regval
, MIPS64_REGSIZE
));
5156 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5158 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5159 arg_type
->length () - len
))
5162 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5164 phex (regval
, MIPS64_REGSIZE
));
5165 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5176 /* Compute the offset into the stack at which we will
5177 copy the next parameter.
5179 In N32 (N64?), the stack_offset only needs to be
5180 adjusted when it has been used. */
5183 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5187 gdb_printf (gdb_stdlog
, "\n");
5190 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5192 /* Return adjusted stack pointer. */
5196 static enum return_value_convention
5197 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5198 struct type
*type
, struct regcache
*regcache
,
5199 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5201 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5203 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5205 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5206 if needed), as appropriate for the type. Composite results (struct,
5207 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5210 * A struct with only one or two floating point fields is returned in $f0
5211 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5214 * Any other composite results of at most 128 bits are returned in
5215 $2 (first 64 bits) and $3 (remainder, if necessary).
5217 * Larger composite results are handled by converting the function to a
5218 procedure with an implicit first parameter, which is a pointer to an area
5219 reserved by the caller to receive the result. [The o32-bit ABI requires
5220 that all composite results be handled by conversion to implicit first
5221 parameters. The MIPS/SGI Fortran implementation has always made a
5222 specific exception to return COMPLEX results in the floating point
5225 From MIPSpro Assembly Language Programmer's Guide, Document Number:
5230 Name fgregdef.h) Use and Linkage
5231 -----------------------------------------------------------------
5232 $f0, $f2 fv0, fv1 Hold results of floating-point type function
5233 ($f0) and complex type function ($f0 has the
5234 real part, $f2 has the imaginary part.) */
5236 if (type
->length () > 2 * MIPS64_REGSIZE
)
5237 return RETURN_VALUE_STRUCT_CONVENTION
;
5238 else if ((type
->code () == TYPE_CODE_COMPLEX
5239 || (type
->code () == TYPE_CODE_FLT
&& type
->length () == 16))
5240 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5242 /* A complex value of up to 128 bits in width as well as a 128-bit
5243 floating-point value goes in both $f0 and $f2. A single complex
5244 value is held in the lower halves only of the respective registers.
5245 The two registers are used in the same as memory order, so the
5246 bytes with the lower memory address are in $f0. */
5248 gdb_printf (gdb_stderr
, "Return float in $f0 and $f2\n");
5249 mips_xfer_register (gdbarch
, regcache
,
5250 (gdbarch_num_regs (gdbarch
)
5251 + mips_regnum (gdbarch
)->fp0
),
5252 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5253 readbuf
, writebuf
, 0);
5254 mips_xfer_register (gdbarch
, regcache
,
5255 (gdbarch_num_regs (gdbarch
)
5256 + mips_regnum (gdbarch
)->fp0
+ 2),
5257 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5258 readbuf
? readbuf
+ type
->length () / 2 : readbuf
,
5260 ? writebuf
+ type
->length () / 2 : writebuf
), 0);
5261 return RETURN_VALUE_REGISTER_CONVENTION
;
5263 else if (type
->code () == TYPE_CODE_FLT
5264 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5266 /* A single or double floating-point value that fits in FP0. */
5268 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5269 mips_xfer_register (gdbarch
, regcache
,
5270 (gdbarch_num_regs (gdbarch
)
5271 + mips_regnum (gdbarch
)->fp0
),
5273 gdbarch_byte_order (gdbarch
),
5274 readbuf
, writebuf
, 0);
5275 return RETURN_VALUE_REGISTER_CONVENTION
;
5277 else if (type
->code () == TYPE_CODE_STRUCT
5278 && type
->num_fields () <= 2
5279 && type
->num_fields () >= 1
5280 && ((type
->num_fields () == 1
5281 && (check_typedef (type
->field (0).type ())->code ()
5283 || (type
->num_fields () == 2
5284 && (check_typedef (type
->field (0).type ())->code ()
5286 && (check_typedef (type
->field (1).type ())->code ()
5287 == TYPE_CODE_FLT
))))
5289 /* A struct that contains one or two floats. Each value is part
5290 in the least significant part of their floating point
5291 register (or GPR, for soft float). */
5294 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5295 ? mips_regnum (gdbarch
)->fp0
5297 field
< type
->num_fields (); field
++, regnum
+= 2)
5299 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5301 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5303 if (type
->field (field
).type ()->length () == 16)
5305 /* A 16-byte long double field goes in two consecutive
5307 mips_xfer_register (gdbarch
, regcache
,
5308 gdbarch_num_regs (gdbarch
) + regnum
,
5310 gdbarch_byte_order (gdbarch
),
5311 readbuf
, writebuf
, offset
);
5312 mips_xfer_register (gdbarch
, regcache
,
5313 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5315 gdbarch_byte_order (gdbarch
),
5316 readbuf
, writebuf
, offset
+ 8);
5319 mips_xfer_register (gdbarch
, regcache
,
5320 gdbarch_num_regs (gdbarch
) + regnum
,
5321 type
->field (field
).type ()->length (),
5322 gdbarch_byte_order (gdbarch
),
5323 readbuf
, writebuf
, offset
);
5325 return RETURN_VALUE_REGISTER_CONVENTION
;
5327 else if (type
->code () == TYPE_CODE_STRUCT
5328 || type
->code () == TYPE_CODE_UNION
5329 || type
->code () == TYPE_CODE_ARRAY
)
5331 /* A composite type. Extract the left justified value,
5332 regardless of the byte order. I.e. DO NOT USE
5336 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5337 offset
< type
->length ();
5338 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5340 int xfer
= register_size (gdbarch
, regnum
);
5341 if (offset
+ xfer
> type
->length ())
5342 xfer
= type
->length () - offset
;
5344 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5345 offset
, xfer
, regnum
);
5346 mips_xfer_register (gdbarch
, regcache
,
5347 gdbarch_num_regs (gdbarch
) + regnum
,
5348 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5351 return RETURN_VALUE_REGISTER_CONVENTION
;
5355 /* A scalar extract each part but least-significant-byte
5359 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5360 offset
< type
->length ();
5361 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5363 int xfer
= register_size (gdbarch
, regnum
);
5364 if (offset
+ xfer
> type
->length ())
5365 xfer
= type
->length () - offset
;
5367 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5368 offset
, xfer
, regnum
);
5369 mips_xfer_register (gdbarch
, regcache
,
5370 gdbarch_num_regs (gdbarch
) + regnum
,
5371 xfer
, gdbarch_byte_order (gdbarch
),
5372 readbuf
, writebuf
, offset
);
5374 return RETURN_VALUE_REGISTER_CONVENTION
;
5378 /* Which registers to use for passing floating-point values between
5379 function calls, one of floating-point, general and both kinds of
5380 registers. O32 and O64 use different register kinds for standard
5381 MIPS and MIPS16 code; to make the handling of cases where we may
5382 not know what kind of code is being used (e.g. no debug information)
5383 easier we sometimes use both kinds. */
5392 /* O32 ABI stuff. */
5395 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5396 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5397 int nargs
, struct value
**args
, CORE_ADDR sp
,
5398 function_call_return_method return_method
,
5399 CORE_ADDR struct_addr
)
5405 int stack_offset
= 0;
5406 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5407 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5409 /* For shared libraries, "t9" needs to point at the function
5411 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5413 /* Set the return address register to point to the entry point of
5414 the program, where a breakpoint lies in wait. */
5415 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5417 /* First ensure that the stack and structure return address (if any)
5418 are properly aligned. The stack has to be at least 64-bit
5419 aligned even on 32-bit machines, because doubles must be 64-bit
5420 aligned. For n32 and n64, stack frames need to be 128-bit
5421 aligned, so we round to this widest known alignment. */
5423 sp
= align_down (sp
, 16);
5424 struct_addr
= align_down (struct_addr
, 16);
5426 /* Now make space on the stack for the args. */
5427 for (argnum
= 0; argnum
< nargs
; argnum
++)
5429 struct type
*arg_type
= check_typedef (args
[argnum
]->type ());
5431 /* Align to double-word if necessary. */
5432 if (mips_type_needs_double_align (arg_type
))
5433 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5434 /* Allocate space on the stack. */
5435 arg_space
+= align_up (arg_type
->length (), MIPS32_REGSIZE
);
5437 sp
-= align_up (arg_space
, 16);
5440 gdb_printf (gdb_stdlog
,
5441 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5442 paddress (gdbarch
, sp
),
5443 (long) align_up (arg_space
, 16));
5445 /* Initialize the integer and float register pointers. */
5446 argreg
= MIPS_A0_REGNUM
;
5447 float_argreg
= mips_fpa0_regnum (gdbarch
);
5449 /* The struct_return pointer occupies the first parameter-passing reg. */
5450 if (return_method
== return_method_struct
)
5453 gdb_printf (gdb_stdlog
,
5454 "mips_o32_push_dummy_call: "
5455 "struct_return reg=%d %s\n",
5456 argreg
, paddress (gdbarch
, struct_addr
));
5457 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5458 stack_offset
+= MIPS32_REGSIZE
;
5461 /* Now load as many as possible of the first arguments into
5462 registers, and push the rest onto the stack. Loop thru args
5463 from first to last. */
5464 for (argnum
= 0; argnum
< nargs
; argnum
++)
5466 const gdb_byte
*val
;
5467 struct value
*arg
= args
[argnum
];
5468 struct type
*arg_type
= check_typedef (arg
->type ());
5469 int len
= arg_type
->length ();
5470 enum type_code typecode
= arg_type
->code ();
5473 gdb_printf (gdb_stdlog
,
5474 "mips_o32_push_dummy_call: %d len=%d type=%d",
5475 argnum
+ 1, len
, (int) typecode
);
5477 val
= arg
->contents ().data ();
5479 /* 32-bit ABIs always start floating point arguments in an
5480 even-numbered floating point register. Round the FP register
5481 up before the check to see if there are any FP registers
5482 left. O32 targets also pass the FP in the integer registers
5483 so also round up normal registers. */
5484 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5486 if ((float_argreg
& 1))
5490 /* Floating point arguments passed in registers have to be
5491 treated specially. On 32-bit architectures, doubles are
5492 passed in register pairs; the even FP register gets the
5493 low word, and the odd FP register gets the high word.
5494 On O32, the first two floating point arguments are also
5495 copied to general registers, following their memory order,
5496 because MIPS16 functions don't use float registers for
5497 arguments. This duplication of arguments in general
5498 registers can't hurt non-MIPS16 functions, because those
5499 registers are normally skipped. */
5501 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5502 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5504 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5506 int freg_offset
= gdbarch_byte_order (gdbarch
)
5507 == BFD_ENDIAN_BIG
? 1 : 0;
5508 unsigned long regval
;
5511 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5513 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5514 float_argreg
+ freg_offset
,
5516 regcache_cooked_write_unsigned (regcache
,
5517 float_argreg
++ + freg_offset
,
5520 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5521 argreg
, phex (regval
, 4));
5522 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5525 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5527 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5528 float_argreg
- freg_offset
,
5530 regcache_cooked_write_unsigned (regcache
,
5531 float_argreg
++ - freg_offset
,
5534 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5535 argreg
, phex (regval
, 4));
5536 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5540 /* This is a floating point value that fits entirely
5541 in a single register. */
5542 /* On 32 bit ABI's the float_argreg is further adjusted
5543 above to ensure that it is even register aligned. */
5544 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5546 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5547 float_argreg
, phex (regval
, len
));
5548 regcache_cooked_write_unsigned (regcache
,
5549 float_argreg
++, regval
);
5550 /* Although two FP registers are reserved for each
5551 argument, only one corresponding integer register is
5554 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5555 argreg
, phex (regval
, len
));
5556 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5558 /* Reserve space for the FP register. */
5559 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5563 /* Copy the argument to general registers or the stack in
5564 register-sized pieces. Large arguments are split between
5565 registers and stack. */
5566 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5567 are treated specially: Irix cc passes
5568 them in registers where gcc sometimes puts them on the
5569 stack. For maximum compatibility, we will put them in
5571 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5572 && len
% MIPS32_REGSIZE
!= 0);
5573 /* Structures should be aligned to eight bytes (even arg registers)
5574 on MIPS_ABI_O32, if their first member has double precision. */
5575 if (mips_type_needs_double_align (arg_type
))
5580 stack_offset
+= MIPS32_REGSIZE
;
5585 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5588 gdb_printf (gdb_stdlog
, " -- partial=%d",
5591 /* Write this portion of the argument to the stack. */
5592 if (argreg
> mips_last_arg_regnum (gdbarch
)
5593 || odd_sized_struct
)
5595 /* Should shorter than int integer values be
5596 promoted to int before being stored? */
5597 int longword_offset
= 0;
5602 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5603 paddress (gdbarch
, stack_offset
));
5604 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5605 paddress (gdbarch
, longword_offset
));
5608 addr
= sp
+ stack_offset
+ longword_offset
;
5613 gdb_printf (gdb_stdlog
, " @%s ",
5614 paddress (gdbarch
, addr
));
5615 for (i
= 0; i
< partial_len
; i
++)
5617 gdb_printf (gdb_stdlog
, "%02x",
5621 write_memory (addr
, val
, partial_len
);
5624 /* Note!!! This is NOT an else clause. Odd sized
5625 structs may go thru BOTH paths. */
5626 /* Write this portion of the argument to a general
5627 purpose register. */
5628 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5630 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5632 /* Value may need to be sign extended, because
5633 mips_isa_regsize() != mips_abi_regsize(). */
5635 /* A non-floating-point argument being passed in a
5636 general register. If a struct or union, and if
5637 the remaining length is smaller than the register
5638 size, we have to adjust the register value on
5641 It does not seem to be necessary to do the
5642 same for integral types.
5644 Also don't do this adjustment on O64 binaries.
5646 cagney/2001-07-23: gdb/179: Also, GCC, when
5647 outputting LE O32 with sizeof (struct) <
5648 mips_abi_regsize(), generates a left shift
5649 as part of storing the argument in a register
5650 (the left shift isn't generated when
5651 sizeof (struct) >= mips_abi_regsize()). Since
5652 it is quite possible that this is GCC
5653 contradicting the LE/O32 ABI, GDB has not been
5654 adjusted to accommodate this. Either someone
5655 needs to demonstrate that the LE/O32 ABI
5656 specifies such a left shift OR this new ABI gets
5657 identified as such and GDB gets tweaked
5660 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5661 && partial_len
< MIPS32_REGSIZE
5662 && (typecode
== TYPE_CODE_STRUCT
5663 || typecode
== TYPE_CODE_UNION
))
5664 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5668 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5670 phex (regval
, MIPS32_REGSIZE
));
5671 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5674 /* Prevent subsequent floating point arguments from
5675 being passed in floating point registers. */
5676 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5682 /* Compute the offset into the stack at which we will
5683 copy the next parameter.
5685 In older ABIs, the caller reserved space for
5686 registers that contained arguments. This was loosely
5687 referred to as their "home". Consequently, space is
5688 always allocated. */
5690 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5694 gdb_printf (gdb_stdlog
, "\n");
5697 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5699 /* Return adjusted stack pointer. */
5703 static enum return_value_convention
5704 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5705 struct type
*type
, struct regcache
*regcache
,
5706 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5708 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5709 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5710 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5711 enum mips_fval_reg fval_reg
;
5713 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5714 if (type
->code () == TYPE_CODE_STRUCT
5715 || type
->code () == TYPE_CODE_UNION
5716 || type
->code () == TYPE_CODE_ARRAY
)
5717 return RETURN_VALUE_STRUCT_CONVENTION
;
5718 else if (type
->code () == TYPE_CODE_FLT
5719 && type
->length () == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5721 /* A single-precision floating-point value. If reading in or copying,
5722 then we get it from/put it to FP0 for standard MIPS code or GPR2
5723 for MIPS16 code. If writing out only, then we put it to both FP0
5724 and GPR2. We do not support reading in with no function known, if
5725 this safety check ever triggers, then we'll have to try harder. */
5726 gdb_assert (function
|| !readbuf
);
5731 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5734 gdb_printf (gdb_stderr
, "Return float in $2\n");
5736 case mips_fval_both
:
5737 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
5740 if (fval_reg
!= mips_fval_gpr
)
5741 mips_xfer_register (gdbarch
, regcache
,
5742 (gdbarch_num_regs (gdbarch
)
5743 + mips_regnum (gdbarch
)->fp0
),
5745 gdbarch_byte_order (gdbarch
),
5746 readbuf
, writebuf
, 0);
5747 if (fval_reg
!= mips_fval_fpr
)
5748 mips_xfer_register (gdbarch
, regcache
,
5749 gdbarch_num_regs (gdbarch
) + 2,
5751 gdbarch_byte_order (gdbarch
),
5752 readbuf
, writebuf
, 0);
5753 return RETURN_VALUE_REGISTER_CONVENTION
;
5755 else if (type
->code () == TYPE_CODE_FLT
5756 && type
->length () == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5758 /* A double-precision floating-point value. If reading in or copying,
5759 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5760 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5761 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5762 no function known, if this safety check ever triggers, then we'll
5763 have to try harder. */
5764 gdb_assert (function
|| !readbuf
);
5769 gdb_printf (gdb_stderr
, "Return float in $fp1/$fp0\n");
5772 gdb_printf (gdb_stderr
, "Return float in $2/$3\n");
5774 case mips_fval_both
:
5775 gdb_printf (gdb_stderr
,
5776 "Return float in $fp1/$fp0 and $2/$3\n");
5779 if (fval_reg
!= mips_fval_gpr
)
5781 /* The most significant part goes in FP1, and the least significant
5783 switch (gdbarch_byte_order (gdbarch
))
5785 case BFD_ENDIAN_LITTLE
:
5786 mips_xfer_register (gdbarch
, regcache
,
5787 (gdbarch_num_regs (gdbarch
)
5788 + mips_regnum (gdbarch
)->fp0
+ 0),
5789 4, gdbarch_byte_order (gdbarch
),
5790 readbuf
, writebuf
, 0);
5791 mips_xfer_register (gdbarch
, regcache
,
5792 (gdbarch_num_regs (gdbarch
)
5793 + mips_regnum (gdbarch
)->fp0
+ 1),
5794 4, gdbarch_byte_order (gdbarch
),
5795 readbuf
, writebuf
, 4);
5797 case BFD_ENDIAN_BIG
:
5798 mips_xfer_register (gdbarch
, regcache
,
5799 (gdbarch_num_regs (gdbarch
)
5800 + mips_regnum (gdbarch
)->fp0
+ 1),
5801 4, gdbarch_byte_order (gdbarch
),
5802 readbuf
, writebuf
, 0);
5803 mips_xfer_register (gdbarch
, regcache
,
5804 (gdbarch_num_regs (gdbarch
)
5805 + mips_regnum (gdbarch
)->fp0
+ 0),
5806 4, gdbarch_byte_order (gdbarch
),
5807 readbuf
, writebuf
, 4);
5810 internal_error (_("bad switch"));
5813 if (fval_reg
!= mips_fval_fpr
)
5815 /* The two 32-bit parts are always placed in GPR2 and GPR3
5816 following these registers' memory order. */
5817 mips_xfer_register (gdbarch
, regcache
,
5818 gdbarch_num_regs (gdbarch
) + 2,
5819 4, gdbarch_byte_order (gdbarch
),
5820 readbuf
, writebuf
, 0);
5821 mips_xfer_register (gdbarch
, regcache
,
5822 gdbarch_num_regs (gdbarch
) + 3,
5823 4, gdbarch_byte_order (gdbarch
),
5824 readbuf
, writebuf
, 4);
5826 return RETURN_VALUE_REGISTER_CONVENTION
;
5829 else if (type
->code () == TYPE_CODE_STRUCT
5830 && type
->num_fields () <= 2
5831 && type
->num_fields () >= 1
5832 && ((type
->num_fields () == 1
5833 && (TYPE_CODE (type
->field (0).type ())
5835 || (type
->num_fields () == 2
5836 && (TYPE_CODE (type
->field (0).type ())
5838 && (TYPE_CODE (type
->field (1).type ())
5840 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5842 /* A struct that contains one or two floats. Each value is part
5843 in the least significant part of their floating point
5847 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5848 field
< type
->num_fields (); field
++, regnum
+= 2)
5850 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5852 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5854 mips_xfer_register (gdbarch
, regcache
,
5855 gdbarch_num_regs (gdbarch
) + regnum
,
5856 TYPE_LENGTH (type
->field (field
).type ()),
5857 gdbarch_byte_order (gdbarch
),
5858 readbuf
, writebuf
, offset
);
5860 return RETURN_VALUE_REGISTER_CONVENTION
;
5864 else if (type
->code () == TYPE_CODE_STRUCT
5865 || type
->code () == TYPE_CODE_UNION
)
5867 /* A structure or union. Extract the left justified value,
5868 regardless of the byte order. I.e. DO NOT USE
5872 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5873 offset
< type
->length ();
5874 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5876 int xfer
= register_size (gdbarch
, regnum
);
5877 if (offset
+ xfer
> type
->length ())
5878 xfer
= type
->length () - offset
;
5880 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5881 offset
, xfer
, regnum
);
5882 mips_xfer_register (gdbarch
, regcache
,
5883 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5884 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5886 return RETURN_VALUE_REGISTER_CONVENTION
;
5891 /* A scalar extract each part but least-significant-byte
5892 justified. o32 thinks registers are 4 byte, regardless of
5896 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5897 offset
< type
->length ();
5898 offset
+= MIPS32_REGSIZE
, regnum
++)
5900 int xfer
= MIPS32_REGSIZE
;
5901 if (offset
+ xfer
> type
->length ())
5902 xfer
= type
->length () - offset
;
5904 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5905 offset
, xfer
, regnum
);
5906 mips_xfer_register (gdbarch
, regcache
,
5907 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5908 gdbarch_byte_order (gdbarch
),
5909 readbuf
, writebuf
, offset
);
5911 return RETURN_VALUE_REGISTER_CONVENTION
;
5915 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5919 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5920 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5922 struct value
**args
, CORE_ADDR sp
,
5923 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5929 int stack_offset
= 0;
5930 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5931 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5933 /* For shared libraries, "t9" needs to point at the function
5935 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5937 /* Set the return address register to point to the entry point of
5938 the program, where a breakpoint lies in wait. */
5939 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5941 /* First ensure that the stack and structure return address (if any)
5942 are properly aligned. The stack has to be at least 64-bit
5943 aligned even on 32-bit machines, because doubles must be 64-bit
5944 aligned. For n32 and n64, stack frames need to be 128-bit
5945 aligned, so we round to this widest known alignment. */
5947 sp
= align_down (sp
, 16);
5948 struct_addr
= align_down (struct_addr
, 16);
5950 /* Now make space on the stack for the args. */
5951 for (argnum
= 0; argnum
< nargs
; argnum
++)
5953 struct type
*arg_type
= check_typedef (args
[argnum
]->type ());
5955 /* Allocate space on the stack. */
5956 arg_space
+= align_up (arg_type
->length (), MIPS64_REGSIZE
);
5958 sp
-= align_up (arg_space
, 16);
5961 gdb_printf (gdb_stdlog
,
5962 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5963 paddress (gdbarch
, sp
),
5964 (long) align_up (arg_space
, 16));
5966 /* Initialize the integer and float register pointers. */
5967 argreg
= MIPS_A0_REGNUM
;
5968 float_argreg
= mips_fpa0_regnum (gdbarch
);
5970 /* The struct_return pointer occupies the first parameter-passing reg. */
5971 if (return_method
== return_method_struct
)
5974 gdb_printf (gdb_stdlog
,
5975 "mips_o64_push_dummy_call: "
5976 "struct_return reg=%d %s\n",
5977 argreg
, paddress (gdbarch
, struct_addr
));
5978 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5979 stack_offset
+= MIPS64_REGSIZE
;
5982 /* Now load as many as possible of the first arguments into
5983 registers, and push the rest onto the stack. Loop thru args
5984 from first to last. */
5985 for (argnum
= 0; argnum
< nargs
; argnum
++)
5987 const gdb_byte
*val
;
5988 struct value
*arg
= args
[argnum
];
5989 struct type
*arg_type
= check_typedef (arg
->type ());
5990 int len
= arg_type
->length ();
5991 enum type_code typecode
= arg_type
->code ();
5994 gdb_printf (gdb_stdlog
,
5995 "mips_o64_push_dummy_call: %d len=%d type=%d",
5996 argnum
+ 1, len
, (int) typecode
);
5998 val
= arg
->contents ().data ();
6000 /* Floating point arguments passed in registers have to be
6001 treated specially. On 32-bit architectures, doubles are
6002 passed in register pairs; the even FP register gets the
6003 low word, and the odd FP register gets the high word.
6004 On O64, the first two floating point arguments are also
6005 copied to general registers, because MIPS16 functions
6006 don't use float registers for arguments. This duplication
6007 of arguments in general registers can't hurt non-MIPS16
6008 functions because those registers are normally skipped. */
6010 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
6011 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
6013 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
6015 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
6016 float_argreg
, phex (regval
, len
));
6017 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6019 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6020 argreg
, phex (regval
, len
));
6021 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6023 /* Reserve space for the FP register. */
6024 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6028 /* Copy the argument to general registers or the stack in
6029 register-sized pieces. Large arguments are split between
6030 registers and stack. */
6031 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6032 are treated specially: Irix cc passes them in registers
6033 where gcc sometimes puts them on the stack. For maximum
6034 compatibility, we will put them in both places. */
6035 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6036 && len
% MIPS64_REGSIZE
!= 0);
6039 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6042 gdb_printf (gdb_stdlog
, " -- partial=%d",
6045 /* Write this portion of the argument to the stack. */
6046 if (argreg
> mips_last_arg_regnum (gdbarch
)
6047 || odd_sized_struct
)
6049 /* Should shorter than int integer values be
6050 promoted to int before being stored? */
6051 int longword_offset
= 0;
6053 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6055 if ((typecode
== TYPE_CODE_INT
6056 || typecode
== TYPE_CODE_PTR
6057 || typecode
== TYPE_CODE_FLT
)
6059 longword_offset
= MIPS64_REGSIZE
- len
;
6064 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
6065 paddress (gdbarch
, stack_offset
));
6066 gdb_printf (gdb_stdlog
, " longword_offset=%s",
6067 paddress (gdbarch
, longword_offset
));
6070 addr
= sp
+ stack_offset
+ longword_offset
;
6075 gdb_printf (gdb_stdlog
, " @%s ",
6076 paddress (gdbarch
, addr
));
6077 for (i
= 0; i
< partial_len
; i
++)
6079 gdb_printf (gdb_stdlog
, "%02x",
6083 write_memory (addr
, val
, partial_len
);
6086 /* Note!!! This is NOT an else clause. Odd sized
6087 structs may go thru BOTH paths. */
6088 /* Write this portion of the argument to a general
6089 purpose register. */
6090 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6092 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6094 /* Value may need to be sign extended, because
6095 mips_isa_regsize() != mips_abi_regsize(). */
6097 /* A non-floating-point argument being passed in a
6098 general register. If a struct or union, and if
6099 the remaining length is smaller than the register
6100 size, we have to adjust the register value on
6103 It does not seem to be necessary to do the
6104 same for integral types. */
6106 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6107 && partial_len
< MIPS64_REGSIZE
6108 && (typecode
== TYPE_CODE_STRUCT
6109 || typecode
== TYPE_CODE_UNION
))
6110 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6114 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6116 phex (regval
, MIPS64_REGSIZE
));
6117 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6120 /* Prevent subsequent floating point arguments from
6121 being passed in floating point registers. */
6122 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6128 /* Compute the offset into the stack at which we will
6129 copy the next parameter.
6131 In older ABIs, the caller reserved space for
6132 registers that contained arguments. This was loosely
6133 referred to as their "home". Consequently, space is
6134 always allocated. */
6136 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6140 gdb_printf (gdb_stdlog
, "\n");
6143 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6145 /* Return adjusted stack pointer. */
6149 static enum return_value_convention
6150 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6151 struct type
*type
, struct regcache
*regcache
,
6152 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6154 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6155 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6156 enum mips_fval_reg fval_reg
;
6158 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6159 if (type
->code () == TYPE_CODE_STRUCT
6160 || type
->code () == TYPE_CODE_UNION
6161 || type
->code () == TYPE_CODE_ARRAY
)
6162 return RETURN_VALUE_STRUCT_CONVENTION
;
6163 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6165 /* A floating-point value. If reading in or copying, then we get it
6166 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6167 If writing out only, then we put it to both FP0 and GPR2. We do
6168 not support reading in with no function known, if this safety
6169 check ever triggers, then we'll have to try harder. */
6170 gdb_assert (function
|| !readbuf
);
6175 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
6178 gdb_printf (gdb_stderr
, "Return float in $2\n");
6180 case mips_fval_both
:
6181 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
6184 if (fval_reg
!= mips_fval_gpr
)
6185 mips_xfer_register (gdbarch
, regcache
,
6186 (gdbarch_num_regs (gdbarch
)
6187 + mips_regnum (gdbarch
)->fp0
),
6189 gdbarch_byte_order (gdbarch
),
6190 readbuf
, writebuf
, 0);
6191 if (fval_reg
!= mips_fval_fpr
)
6192 mips_xfer_register (gdbarch
, regcache
,
6193 gdbarch_num_regs (gdbarch
) + 2,
6195 gdbarch_byte_order (gdbarch
),
6196 readbuf
, writebuf
, 0);
6197 return RETURN_VALUE_REGISTER_CONVENTION
;
6201 /* A scalar extract each part but least-significant-byte
6205 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6206 offset
< type
->length ();
6207 offset
+= MIPS64_REGSIZE
, regnum
++)
6209 int xfer
= MIPS64_REGSIZE
;
6210 if (offset
+ xfer
> type
->length ())
6211 xfer
= type
->length () - offset
;
6213 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6214 offset
, xfer
, regnum
);
6215 mips_xfer_register (gdbarch
, regcache
,
6216 gdbarch_num_regs (gdbarch
) + regnum
,
6217 xfer
, gdbarch_byte_order (gdbarch
),
6218 readbuf
, writebuf
, offset
);
6220 return RETURN_VALUE_REGISTER_CONVENTION
;
6224 /* Floating point register management.
6226 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6227 64bit operations, these early MIPS cpus treat fp register pairs
6228 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6229 registers and offer a compatibility mode that emulates the MIPS2 fp
6230 model. When operating in MIPS2 fp compat mode, later cpu's split
6231 double precision floats into two 32-bit chunks and store them in
6232 consecutive fp regs. To display 64-bit floats stored in this
6233 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6234 Throw in user-configurable endianness and you have a real mess.
6236 The way this works is:
6237 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6238 double-precision value will be split across two logical registers.
6239 The lower-numbered logical register will hold the low-order bits,
6240 regardless of the processor's endianness.
6241 - If we are on a 64-bit processor, and we are looking for a
6242 single-precision value, it will be in the low ordered bits
6243 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6244 save slot in memory.
6245 - If we are in 64-bit mode, everything is straightforward.
6247 Note that this code only deals with "live" registers at the top of the
6248 stack. We will attempt to deal with saved registers later, when
6249 the raw/cooked register interface is in place. (We need a general
6250 interface that can deal with dynamic saved register sizes -- fp
6251 regs could be 32 bits wide in one frame and 64 on the frame above
6254 /* Copy a 32-bit single-precision value from the current frame
6255 into rare_buffer. */
6258 mips_read_fp_register_single (const frame_info_ptr
&frame
, int regno
,
6259 gdb_byte
*rare_buffer
)
6261 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6262 int raw_size
= register_size (gdbarch
, regno
);
6263 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6265 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6266 error (_("can't read register %d (%s)"),
6267 regno
, gdbarch_register_name (gdbarch
, regno
));
6270 /* We have a 64-bit value for this register. Find the low-order
6274 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6279 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6283 memcpy (rare_buffer
, raw_buffer
, 4);
6287 /* Copy a 64-bit double-precision value from the current frame into
6288 rare_buffer. This may include getting half of it from the next
6292 mips_read_fp_register_double (const frame_info_ptr
&frame
, int regno
,
6293 gdb_byte
*rare_buffer
)
6295 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6296 int raw_size
= register_size (gdbarch
, regno
);
6298 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6300 /* We have a 64-bit value for this register, and we should use
6302 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6303 error (_("can't read register %d (%s)"),
6304 regno
, gdbarch_register_name (gdbarch
, regno
));
6308 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6310 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6311 internal_error (_("mips_read_fp_register_double: bad access to "
6312 "odd-numbered FP register"));
6314 /* mips_read_fp_register_single will find the correct 32 bits from
6316 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6318 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6319 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6323 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6324 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6330 mips_print_fp_register (struct ui_file
*file
, const frame_info_ptr
&frame
,
6332 { /* Do values for FP (float) regs. */
6333 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6334 gdb_byte
*raw_buffer
;
6335 std::string flt_str
, dbl_str
;
6337 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6338 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6342 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6344 gdb_printf (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6345 gdb_printf (file
, "%*s",
6346 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6349 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6351 struct value_print_options opts
;
6353 /* 4-byte registers: Print hex and floating. Also print even
6354 numbered registers as doubles. */
6355 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6356 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6358 get_formatted_print_options (&opts
, 'x');
6359 print_scalar_formatted (raw_buffer
,
6360 builtin_type (gdbarch
)->builtin_uint32
,
6363 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6365 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6367 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6368 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6370 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6375 struct value_print_options opts
;
6377 /* Eight byte registers: print each one as hex, float and double. */
6378 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6379 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6381 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6382 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6384 get_formatted_print_options (&opts
, 'x');
6385 print_scalar_formatted (raw_buffer
,
6386 builtin_type (gdbarch
)->builtin_uint64
,
6389 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6390 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6395 mips_print_register (struct ui_file
*file
, const frame_info_ptr
&frame
,
6398 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6399 struct value_print_options opts
;
6402 if (mips_float_register_p (gdbarch
, regnum
))
6404 mips_print_fp_register (file
, frame
, regnum
);
6408 val
= get_frame_register_value (frame
, regnum
);
6410 gdb_puts (gdbarch_register_name (gdbarch
, regnum
), file
);
6412 /* The problem with printing numeric register names (r26, etc.) is that
6413 the user can't use them on input. Probably the best solution is to
6414 fix it so that either the numeric or the funky (a2, etc.) names
6415 are accepted on input. */
6416 if (regnum
< MIPS_NUMREGS
)
6417 gdb_printf (file
, "(r%d): ", regnum
);
6419 gdb_printf (file
, ": ");
6421 get_formatted_print_options (&opts
, 'x');
6422 value_print_scalar_formatted (val
, &opts
, 0, file
);
6425 /* Print IEEE exception condition bits in FLAGS. */
6428 print_fpu_flags (struct ui_file
*file
, int flags
)
6430 if (flags
& (1 << 0))
6431 gdb_puts (" inexact", file
);
6432 if (flags
& (1 << 1))
6433 gdb_puts (" uflow", file
);
6434 if (flags
& (1 << 2))
6435 gdb_puts (" oflow", file
);
6436 if (flags
& (1 << 3))
6437 gdb_puts (" div0", file
);
6438 if (flags
& (1 << 4))
6439 gdb_puts (" inval", file
);
6440 if (flags
& (1 << 5))
6441 gdb_puts (" unimp", file
);
6442 gdb_putc ('\n', file
);
6445 /* Print interesting information about the floating point processor
6446 (if present) or emulator. */
6449 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6450 const frame_info_ptr
&frame
, const char *args
)
6452 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6453 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6457 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6458 type
= MIPS_FPU_NONE
;
6460 gdb_printf (file
, "fpu type: %s\n",
6461 type
== MIPS_FPU_DOUBLE
? "double-precision"
6462 : type
== MIPS_FPU_SINGLE
? "single-precision"
6465 if (type
== MIPS_FPU_NONE
)
6468 gdb_printf (file
, "reg size: %d bits\n",
6469 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6471 gdb_puts ("cond :", file
);
6472 if (fcs
& (1 << 23))
6473 gdb_puts (" 0", file
);
6474 for (i
= 1; i
<= 7; i
++)
6475 if (fcs
& (1 << (24 + i
)))
6476 gdb_printf (file
, " %d", i
);
6477 gdb_putc ('\n', file
);
6479 gdb_puts ("cause :", file
);
6480 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6481 fputs ("mask :", stdout
);
6482 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6483 fputs ("flags :", stdout
);
6484 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6486 gdb_puts ("rounding: ", file
);
6489 case 0: gdb_puts ("nearest\n", file
); break;
6490 case 1: gdb_puts ("zero\n", file
); break;
6491 case 2: gdb_puts ("+inf\n", file
); break;
6492 case 3: gdb_puts ("-inf\n", file
); break;
6495 gdb_puts ("flush :", file
);
6496 if (fcs
& (1 << 21))
6497 gdb_puts (" nearest", file
);
6498 if (fcs
& (1 << 22))
6499 gdb_puts (" override", file
);
6500 if (fcs
& (1 << 24))
6501 gdb_puts (" zero", file
);
6502 if ((fcs
& (0xb << 21)) == 0)
6503 gdb_puts (" no", file
);
6504 gdb_putc ('\n', file
);
6506 gdb_printf (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6507 gdb_printf (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6508 gdb_putc ('\n', file
);
6510 default_print_float_info (gdbarch
, file
, frame
, args
);
6513 /* Replacement for generic do_registers_info.
6514 Print regs in pretty columns. */
6517 print_fp_register_row (struct ui_file
*file
, const frame_info_ptr
&frame
,
6520 gdb_printf (file
, " ");
6521 mips_print_fp_register (file
, frame
, regnum
);
6522 gdb_printf (file
, "\n");
6527 /* Print a row's worth of GP (int) registers, with name labels above. */
6530 print_gp_register_row (struct ui_file
*file
, const frame_info_ptr
&frame
,
6533 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6534 /* Do values for GP (int) regs. */
6535 const gdb_byte
*raw_buffer
;
6536 struct value
*value
;
6537 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6542 /* For GP registers, we print a separate row of names above the vals. */
6543 for (col
= 0, regnum
= start_regnum
;
6544 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6547 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6548 continue; /* unused register */
6549 if (mips_float_register_p (gdbarch
, regnum
))
6550 break; /* End the row: reached FP register. */
6551 /* Large registers are handled separately. */
6552 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6555 break; /* End the row before this register. */
6557 /* Print this register on a row by itself. */
6558 mips_print_register (file
, frame
, regnum
);
6559 gdb_printf (file
, "\n");
6563 gdb_printf (file
, " ");
6565 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6566 gdbarch_register_name (gdbarch
, regnum
));
6573 /* Print the R0 to R31 names. */
6574 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6575 gdb_printf (file
, "\n R%-4d",
6576 start_regnum
% gdbarch_num_regs (gdbarch
));
6578 gdb_printf (file
, "\n ");
6580 /* Now print the values in hex, 4 or 8 to the row. */
6581 for (col
= 0, regnum
= start_regnum
;
6582 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6585 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6586 continue; /* unused register */
6587 if (mips_float_register_p (gdbarch
, regnum
))
6588 break; /* End row: reached FP register. */
6589 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6590 break; /* End row: large register. */
6592 /* OK: get the data in raw format. */
6593 value
= get_frame_register_value (frame
, regnum
);
6594 if (value
->optimized_out ()
6595 || !value
->entirely_available ())
6597 gdb_printf (file
, "%*s ",
6598 (int) mips_abi_regsize (gdbarch
) * 2,
6599 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6600 : "<unavailable>"));
6604 raw_buffer
= value
->contents_all ().data ();
6605 /* pad small registers */
6607 byte
< (mips_abi_regsize (gdbarch
)
6608 - register_size (gdbarch
, regnum
)); byte
++)
6609 gdb_printf (file
, " ");
6610 /* Now print the register value in hex, endian order. */
6611 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6613 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6614 byte
< register_size (gdbarch
, regnum
); byte
++)
6615 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6617 for (byte
= register_size (gdbarch
, regnum
) - 1;
6619 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6620 gdb_printf (file
, " ");
6623 if (col
> 0) /* ie. if we actually printed anything... */
6624 gdb_printf (file
, "\n");
6629 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6632 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6633 const frame_info_ptr
&frame
, int regnum
, int all
)
6635 if (regnum
!= -1) /* Do one specified register. */
6637 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6638 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6639 error (_("Not a valid register for the current processor type"));
6641 mips_print_register (file
, frame
, regnum
);
6642 gdb_printf (file
, "\n");
6645 /* Do all (or most) registers. */
6647 regnum
= gdbarch_num_regs (gdbarch
);
6648 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6650 if (mips_float_register_p (gdbarch
, regnum
))
6652 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6653 regnum
= print_fp_register_row (file
, frame
, regnum
);
6655 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6658 regnum
= print_gp_register_row (file
, frame
, regnum
);
6664 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6665 const frame_info_ptr
&frame
)
6667 CORE_ADDR pc
= get_frame_pc (frame
);
6672 if ((mips_pc_is_mips (pc
)
6673 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6674 || (mips_pc_is_micromips (gdbarch
, pc
)
6675 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6676 || (mips_pc_is_mips16 (gdbarch
, pc
)
6677 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6680 isa
= mips_pc_isa (gdbarch
, pc
);
6681 /* _has_delay_slot above will have validated the read. */
6682 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6683 size
= mips_insn_size (isa
, insn
);
6685 const address_space
*aspace
= get_frame_address_space (frame
);
6687 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6690 /* To skip prologues, I use this predicate. Returns either PC itself
6691 if the code at PC does not look like a function prologue; otherwise
6692 returns an address that (if we're lucky) follows the prologue. If
6693 LENIENT, then we must skip everything which is involved in setting
6694 up the frame (it's OK to skip more, just so long as we don't skip
6695 anything which might clobber the registers which are being saved.
6696 We must skip more in the case where part of the prologue is in the
6697 delay slot of a non-prologue instruction). */
6700 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6703 CORE_ADDR func_addr
;
6705 /* See if we can determine the end of the prologue via the symbol table.
6706 If so, then return either PC, or the PC after the prologue, whichever
6708 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6710 CORE_ADDR post_prologue_pc
6711 = skip_prologue_using_sal (gdbarch
, func_addr
);
6712 if (post_prologue_pc
!= 0)
6713 return std::max (pc
, post_prologue_pc
);
6716 /* Can't determine prologue from the symbol table, need to examine
6719 /* Find an upper limit on the function prologue using the debug
6720 information. If the debug information could not be used to provide
6721 that bound, then use an arbitrary large number as the upper bound. */
6722 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6724 limit_pc
= pc
+ 100; /* Magic. */
6726 if (mips_pc_is_mips16 (gdbarch
, pc
))
6727 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6728 else if (mips_pc_is_micromips (gdbarch
, pc
))
6729 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6731 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6734 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6735 This is a helper function for mips_stack_frame_destroyed_p. */
6738 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6740 CORE_ADDR func_addr
= 0, func_end
= 0;
6742 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6744 /* The MIPS epilogue is max. 12 bytes long. */
6745 CORE_ADDR addr
= func_end
- 12;
6747 if (addr
< func_addr
+ 4)
6748 addr
= func_addr
+ 4;
6752 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6754 unsigned long high_word
;
6757 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6758 high_word
= (inst
>> 16) & 0xffff;
6760 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6761 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6762 && inst
!= 0x03e00008 /* jr $ra */
6763 && inst
!= 0x00000000) /* nop */
6773 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6774 This is a helper function for mips_stack_frame_destroyed_p. */
6777 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6779 CORE_ADDR func_addr
= 0;
6780 CORE_ADDR func_end
= 0;
6788 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6791 /* The microMIPS epilogue is max. 12 bytes long. */
6792 addr
= func_end
- 12;
6794 if (addr
< func_addr
+ 2)
6795 addr
= func_addr
+ 2;
6799 for (; pc
< func_end
; pc
+= loc
)
6802 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6803 loc
+= MIPS_INSN16_SIZE
;
6804 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6806 /* 32-bit instructions. */
6807 case 2 * MIPS_INSN16_SIZE
:
6809 insn
|= mips_fetch_instruction (gdbarch
,
6810 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6811 loc
+= MIPS_INSN16_SIZE
;
6812 switch (micromips_op (insn
>> 16))
6814 case 0xc: /* ADDIU: bits 001100 */
6815 case 0x17: /* DADDIU: bits 010111 */
6816 sreg
= b0s5_reg (insn
>> 16);
6817 dreg
= b5s5_reg (insn
>> 16);
6818 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6819 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6820 /* (D)ADDIU $sp, imm */
6830 /* 16-bit instructions. */
6831 case MIPS_INSN16_SIZE
:
6832 switch (micromips_op (insn
))
6834 case 0x3: /* MOVE: bits 000011 */
6835 sreg
= b0s5_reg (insn
);
6836 dreg
= b5s5_reg (insn
);
6837 if (sreg
== 0 && dreg
== 0)
6838 /* MOVE $zero, $zero aka NOP */
6842 case 0x11: /* POOL16C: bits 010001 */
6843 if (b5s5_op (insn
) == 0x18
6844 /* JRADDIUSP: bits 010011 11000 */
6845 || (b5s5_op (insn
) == 0xd
6846 /* JRC: bits 010011 01101 */
6847 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6852 case 0x13: /* POOL16D: bits 010011 */
6853 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6854 if ((insn
& 0x1) == 0x1
6855 /* ADDIUSP: bits 010011 1 */
6869 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6870 This is a helper function for mips_stack_frame_destroyed_p. */
6873 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6875 CORE_ADDR func_addr
= 0, func_end
= 0;
6877 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6879 /* The MIPS epilogue is max. 12 bytes long. */
6880 CORE_ADDR addr
= func_end
- 12;
6882 if (addr
< func_addr
+ 4)
6883 addr
= func_addr
+ 4;
6887 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6889 unsigned short inst
;
6891 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6893 if ((inst
& 0xf800) == 0xf000) /* extend */
6896 if (inst
!= 0x6300 /* addiu $sp,offset */
6897 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6898 && inst
!= 0xe820 /* jr $ra */
6899 && inst
!= 0xe8a0 /* jrc $ra */
6900 && inst
!= 0x6500) /* nop */
6910 /* Implement the stack_frame_destroyed_p gdbarch method.
6912 The epilogue is defined here as the area at the end of a function,
6913 after an instruction which destroys the function's stack frame. */
6916 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6918 if (mips_pc_is_mips16 (gdbarch
, pc
))
6919 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6920 else if (mips_pc_is_micromips (gdbarch
, pc
))
6921 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6923 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6926 /* Commands to show/set the MIPS FPU type. */
6929 show_mipsfpu_command (const char *args
, int from_tty
)
6933 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
6937 ("The MIPS floating-point coprocessor is unknown "
6938 "because the current architecture is not MIPS.\n");
6942 switch (mips_get_fpu_type (current_inferior ()->arch ()))
6944 case MIPS_FPU_SINGLE
:
6945 fpu
= "single-precision";
6947 case MIPS_FPU_DOUBLE
:
6948 fpu
= "double-precision";
6951 fpu
= "absent (none)";
6954 internal_error (_("bad switch"));
6956 if (mips_fpu_type_auto
)
6957 gdb_printf ("The MIPS floating-point coprocessor "
6958 "is set automatically (currently %s)\n",
6962 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6967 set_mipsfpu_single_command (const char *args
, int from_tty
)
6969 struct gdbarch_info info
;
6970 mips_fpu_type
= MIPS_FPU_SINGLE
;
6971 mips_fpu_type_auto
= 0;
6972 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6973 instead of relying on globals. Doing that would let generic code
6974 handle the search for this specific architecture. */
6975 if (!gdbarch_update_p (info
))
6976 internal_error (_("set mipsfpu failed"));
6980 set_mipsfpu_double_command (const char *args
, int from_tty
)
6982 struct gdbarch_info info
;
6983 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6984 mips_fpu_type_auto
= 0;
6985 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6986 instead of relying on globals. Doing that would let generic code
6987 handle the search for this specific architecture. */
6988 if (!gdbarch_update_p (info
))
6989 internal_error (_("set mipsfpu failed"));
6993 set_mipsfpu_none_command (const char *args
, int from_tty
)
6995 struct gdbarch_info info
;
6996 mips_fpu_type
= MIPS_FPU_NONE
;
6997 mips_fpu_type_auto
= 0;
6998 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6999 instead of relying on globals. Doing that would let generic code
7000 handle the search for this specific architecture. */
7001 if (!gdbarch_update_p (info
))
7002 internal_error (_("set mipsfpu failed"));
7006 set_mipsfpu_auto_command (const char *args
, int from_tty
)
7008 mips_fpu_type_auto
= 1;
7011 /* Just like reinit_frame_cache, but with the right arguments to be
7012 callable as an sfunc. */
7015 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
7016 struct cmd_list_element
*c
)
7018 reinit_frame_cache ();
7022 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7024 gdb_disassemble_info
*di
7025 = static_cast<gdb_disassemble_info
*> (info
->application_data
);
7026 struct gdbarch
*gdbarch
= di
->arch ();
7028 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7029 disassembler needs to be able to locally determine the ISA, and
7030 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7032 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7033 info
->mach
= bfd_mach_mips16
;
7034 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7035 info
->mach
= bfd_mach_mips_micromips
;
7037 /* Round down the instruction address to the appropriate boundary. */
7038 memaddr
&= (info
->mach
== bfd_mach_mips16
7039 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7041 return default_print_insn (memaddr
, info
);
7044 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7047 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7049 CORE_ADDR pc
= *pcptr
;
7051 if (mips_pc_is_mips16 (gdbarch
, pc
))
7053 *pcptr
= unmake_compact_addr (pc
);
7054 return MIPS_BP_KIND_MIPS16
;
7056 else if (mips_pc_is_micromips (gdbarch
, pc
))
7061 *pcptr
= unmake_compact_addr (pc
);
7062 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7063 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7064 return MIPS_BP_KIND_MICROMIPS16
;
7066 return MIPS_BP_KIND_MICROMIPS32
;
7069 return MIPS_BP_KIND_MIPS32
;
7072 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7074 static const gdb_byte
*
7075 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7077 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7081 case MIPS_BP_KIND_MIPS16
:
7083 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7084 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7087 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7088 return mips16_big_breakpoint
;
7090 return mips16_little_breakpoint
;
7092 case MIPS_BP_KIND_MICROMIPS16
:
7094 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7095 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7099 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7100 return micromips16_big_breakpoint
;
7102 return micromips16_little_breakpoint
;
7104 case MIPS_BP_KIND_MICROMIPS32
:
7106 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7107 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7110 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7111 return micromips32_big_breakpoint
;
7113 return micromips32_little_breakpoint
;
7115 case MIPS_BP_KIND_MIPS32
:
7117 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7118 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7121 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7122 return big_breakpoint
;
7124 return little_breakpoint
;
7127 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7131 /* Return non-zero if the standard MIPS instruction INST has a branch
7132 delay slot (i.e. it is a jump or branch instruction). This function
7133 is based on mips32_next_pc. */
7136 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7142 op
= itype_op (inst
);
7143 if ((inst
& 0xe0000000) != 0)
7145 rs
= itype_rs (inst
);
7146 rt
= itype_rt (inst
);
7147 return (is_octeon_bbit_op (op
, gdbarch
)
7148 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7149 || op
== 29 /* JALX: bits 011101 */
7152 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7153 || (rs
== 9 && (rt
& 0x2) == 0)
7154 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7155 || (rs
== 10 && (rt
& 0x2) == 0))));
7156 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7159 switch (op
& 0x07) /* extract bits 28,27,26 */
7161 case 0: /* SPECIAL */
7162 op
= rtype_funct (inst
);
7163 return (op
== 8 /* JR */
7164 || op
== 9); /* JALR */
7165 break; /* end SPECIAL */
7166 case 1: /* REGIMM */
7167 rs
= itype_rs (inst
);
7168 rt
= itype_rt (inst
); /* branch condition */
7169 return ((rt
& 0xc) == 0
7170 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7171 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7172 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7173 /* BPOSGE32, BPOSGE64: bits 1110x */
7174 break; /* end REGIMM */
7175 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7181 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7182 delay slot (i.e. it is a jump or branch instruction). */
7185 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7190 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7194 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7197 /* Return non-zero if the microMIPS instruction INSN, comprising the
7198 16-bit major opcode word in the high 16 bits and any second word
7199 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7200 jump or branch instruction). The instruction must be 32-bit if
7201 MUSTBE32 is set or can be any instruction otherwise. */
7204 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7206 ULONGEST major
= insn
>> 16;
7208 switch (micromips_op (major
))
7210 /* 16-bit instructions. */
7211 case 0x33: /* B16: bits 110011 */
7212 case 0x2b: /* BNEZ16: bits 101011 */
7213 case 0x23: /* BEQZ16: bits 100011 */
7215 case 0x11: /* POOL16C: bits 010001 */
7217 && ((b5s5_op (major
) == 0xc
7218 /* JR16: bits 010001 01100 */
7219 || (b5s5_op (major
) & 0x1e) == 0xe)));
7220 /* JALR16, JALRS16: bits 010001 0111x */
7221 /* 32-bit instructions. */
7222 case 0x3d: /* JAL: bits 111101 */
7223 case 0x3c: /* JALX: bits 111100 */
7224 case 0x35: /* J: bits 110101 */
7225 case 0x2d: /* BNE: bits 101101 */
7226 case 0x25: /* BEQ: bits 100101 */
7227 case 0x1d: /* JALS: bits 011101 */
7229 case 0x10: /* POOL32I: bits 010000 */
7230 return ((b5s5_op (major
) & 0x1c) == 0x0
7231 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7232 || (b5s5_op (major
) & 0x1d) == 0x4
7233 /* BLEZ, BGTZ: bits 010000 001x0 */
7234 || (b5s5_op (major
) & 0x1d) == 0x11
7235 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7236 || ((b5s5_op (major
) & 0x1e) == 0x14
7237 && (major
& 0x3) == 0x0)
7238 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7239 || (b5s5_op (major
) & 0x1e) == 0x1a
7240 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7241 || ((b5s5_op (major
) & 0x1e) == 0x1c
7242 && (major
& 0x3) == 0x0)
7243 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7244 || ((b5s5_op (major
) & 0x1c) == 0x1c
7245 && (major
& 0x3) == 0x1));
7246 /* BC1ANY*: bits 010000 111xx xxx01 */
7247 case 0x0: /* POOL32A: bits 000000 */
7248 return (b0s6_op (insn
) == 0x3c
7249 /* POOL32Axf: bits 000000 ... 111100 */
7250 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7251 /* JALR, JALR.HB: 000000 000x111100 111100 */
7252 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7258 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7259 slot (i.e. it is a non-compact jump instruction). The instruction
7260 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7263 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7264 CORE_ADDR addr
, int mustbe32
)
7270 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7273 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7275 if (size
== 2 * MIPS_INSN16_SIZE
)
7277 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7282 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7285 /* Return non-zero if the MIPS16 instruction INST, which must be
7286 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7287 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7288 instruction). This function is based on mips16_next_pc. */
7291 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7293 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7295 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7298 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7299 slot (i.e. it is a non-compact jump instruction). The instruction
7300 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7303 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7304 CORE_ADDR addr
, int mustbe32
)
7306 unsigned short insn
;
7309 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7313 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7316 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7317 This assumes KSSEG exists. */
7320 mips_segment_boundary (CORE_ADDR bpaddr
)
7322 CORE_ADDR mask
= CORE_ADDR_MAX
;
7325 if (sizeof (CORE_ADDR
) == 8)
7326 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7327 a compiler warning produced where CORE_ADDR is a 32-bit type even
7328 though in that case this is dead code). */
7329 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7332 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7333 segsize
= 29; /* 32-bit compatibility segment */
7335 segsize
= 62; /* xkseg */
7337 case 2: /* xkphys */
7340 default: /* xksseg (1), xkuseg/kuseg (0) */
7344 else if (bpaddr
& 0x80000000) /* kernel segment */
7347 segsize
= 31; /* user segment */
7349 return bpaddr
& mask
;
7352 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7353 it backwards if necessary. Return the address of the new location. */
7356 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7358 CORE_ADDR prev_addr
;
7360 CORE_ADDR func_addr
;
7362 /* If a breakpoint is set on the instruction in a branch delay slot,
7363 GDB gets confused. When the breakpoint is hit, the PC isn't on
7364 the instruction in the branch delay slot, the PC will point to
7365 the branch instruction. Since the PC doesn't match any known
7366 breakpoints, GDB reports a trap exception.
7368 There are two possible fixes for this problem.
7370 1) When the breakpoint gets hit, see if the BD bit is set in the
7371 Cause register (which indicates the last exception occurred in a
7372 branch delay slot). If the BD bit is set, fix the PC to point to
7373 the instruction in the branch delay slot.
7375 2) When the user sets the breakpoint, don't allow him to set the
7376 breakpoint on the instruction in the branch delay slot. Instead
7377 move the breakpoint to the branch instruction (which will have
7380 The problem with the first solution is that if the user then
7381 single-steps the processor, the branch instruction will get
7382 skipped (since GDB thinks the PC is on the instruction in the
7385 So, we'll use the second solution. To do this we need to know if
7386 the instruction we're trying to set the breakpoint on is in the
7387 branch delay slot. */
7389 boundary
= mips_segment_boundary (bpaddr
);
7391 /* Make sure we don't scan back before the beginning of the current
7392 function, since we may fetch constant data or insns that look like
7393 a jump. Of course we might do that anyway if the compiler has
7394 moved constants inline. :-( */
7395 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7396 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7397 boundary
= func_addr
;
7399 if (mips_pc_is_mips (bpaddr
))
7401 if (bpaddr
== boundary
)
7404 /* If the previous instruction has a branch delay slot, we have
7405 to move the breakpoint to the branch instruction. */
7406 prev_addr
= bpaddr
- 4;
7407 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7412 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7413 CORE_ADDR addr
, jmpaddr
;
7416 boundary
= unmake_compact_addr (boundary
);
7418 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7419 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7420 so try for that first, then try the 2 byte JALR/JR.
7421 The microMIPS ASE has a whole range of jumps and branches
7422 with delay slots, some of which take 4 bytes and some take
7423 2 bytes, so the idea is the same.
7424 FIXME: We have to assume that bpaddr is not the second half
7425 of an extended instruction. */
7426 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7427 ? micromips_insn_at_pc_has_delay_slot
7428 : mips16_insn_at_pc_has_delay_slot
);
7432 for (i
= 1; i
< 4; i
++)
7434 if (unmake_compact_addr (addr
) == boundary
)
7436 addr
-= MIPS_INSN16_SIZE
;
7437 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7438 /* Looks like a JR/JALR at [target-1], but it could be
7439 the second word of a previous JAL/JALX, so record it
7440 and check back one more. */
7442 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7445 /* Looks like a JAL/JALX at [target-2], but it could also
7446 be the second word of a previous JAL/JALX, record it,
7447 and check back one more. */
7450 /* Looks like a JAL/JALX at [target-3], so any previously
7451 recorded JAL/JALX or JR/JALR must be wrong, because:
7454 -2: JAL-ext (can't be JAL/JALX)
7455 -1: bdslot (can't be JR/JALR)
7458 Of course it could be another JAL-ext which looks
7459 like a JAL, but in that case we'd have broken out
7460 of this loop at [target-2]:
7464 -2: bdslot (can't be jmp)
7471 /* Not a jump instruction: if we're at [target-1] this
7472 could be the second word of a JAL/JALX, so continue;
7473 otherwise we're done. */
7486 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7487 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7490 mips_is_stub_suffix (const char *suffix
, int zero
)
7495 return zero
&& suffix
[1] == '\0';
7497 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7502 return suffix
[1] == '\0';
7508 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7509 call stubs, one of sf, df, sc, or dc. */
7512 mips_is_stub_mode (const char *mode
)
7514 return ((mode
[0] == 's' || mode
[0] == 'd')
7515 && (mode
[1] == 'f' || mode
[1] == 'c'));
7518 /* Code at PC is a compiler-generated stub. Such a stub for a function
7519 bar might have a name like __fn_stub_bar, and might look like this:
7526 followed by (or interspersed with):
7533 addiu $25, $25, %lo(bar)
7536 ($1 may be used in old code; for robustness we accept any register)
7539 lui $28, %hi(_gp_disp)
7540 addiu $28, $28, %lo(_gp_disp)
7543 addiu $25, $25, %lo(bar)
7546 In the case of a __call_stub_bar stub, the sequence to set up
7547 arguments might look like this:
7554 followed by (or interspersed with) one of the jump sequences above.
7556 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7557 of J or JR, respectively, followed by:
7563 We are at the beginning of the stub here, and scan down and extract
7564 the target address from the jump immediate instruction or, if a jump
7565 register instruction is used, from the register referred. Return
7566 the value of PC calculated or 0 if inconclusive.
7568 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7571 mips_get_mips16_fn_stub_pc (const frame_info_ptr
&frame
, CORE_ADDR pc
)
7573 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7574 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7575 int addrreg
= MIPS_ZERO_REGNUM
;
7576 CORE_ADDR start_pc
= pc
;
7577 CORE_ADDR target_pc
= 0;
7584 status
== 0 && target_pc
== 0 && i
< 20;
7585 i
++, pc
+= MIPS_INSN32_SIZE
)
7587 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7593 switch (itype_op (inst
))
7595 case 0: /* SPECIAL */
7596 switch (rtype_funct (inst
))
7600 rs
= rtype_rs (inst
);
7601 if (rs
== MIPS_GP_REGNUM
)
7602 target_pc
= gp
; /* Hmm... */
7603 else if (rs
== addrreg
)
7607 case 0x21: /* ADDU */
7608 rt
= rtype_rt (inst
);
7609 rs
= rtype_rs (inst
);
7610 rd
= rtype_rd (inst
);
7611 if (rd
== MIPS_GP_REGNUM
7612 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7613 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7621 target_pc
= jtype_target (inst
) << 2;
7622 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7626 rt
= itype_rt (inst
);
7627 rs
= itype_rs (inst
);
7630 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7631 if (rt
== MIPS_GP_REGNUM
)
7633 else if (rt
== addrreg
)
7639 rt
= itype_rt (inst
);
7640 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7641 if (rt
== MIPS_GP_REGNUM
)
7643 else if (rt
!= MIPS_ZERO_REGNUM
)
7651 rt
= itype_rt (inst
);
7652 rs
= itype_rs (inst
);
7653 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7654 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7658 memset (buf
, 0, sizeof (buf
));
7659 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7661 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7670 /* If PC is in a MIPS16 call or return stub, return the address of the
7671 target PC, which is either the callee or the caller. There are several
7672 cases which must be handled:
7674 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7675 and the target PC is in $31 ($ra).
7676 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7677 and the target PC is in $2.
7678 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7679 i.e. before the JALR instruction, this is effectively a call stub
7680 and the target PC is in $2. Otherwise this is effectively
7681 a return stub and the target PC is in $18.
7682 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7683 JAL or JALR instruction, this is effectively a call stub and the
7684 target PC is buried in the instruction stream. Otherwise this
7685 is effectively a return stub and the target PC is in $18.
7686 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7687 stub and the target PC is buried in the instruction stream.
7689 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7690 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7694 mips_skip_mips16_trampoline_code (const frame_info_ptr
&frame
, CORE_ADDR pc
)
7696 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7697 CORE_ADDR start_addr
;
7701 /* Find the starting address and name of the function containing the PC. */
7702 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7705 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7706 and the target PC is in $31 ($ra). */
7707 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7708 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7709 && mips_is_stub_mode (name
+ prefixlen
)
7710 && name
[prefixlen
+ 2] == '\0')
7711 return get_frame_register_signed
7712 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7714 /* If the PC is in __mips16_call_stub_*, this is one of the call
7715 call/return stubs. */
7716 prefixlen
= strlen (mips_str_mips16_call_stub
);
7717 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7719 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7720 and the target PC is in $2. */
7721 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7722 return get_frame_register_signed
7723 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7725 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7726 i.e. before the JALR instruction, this is effectively a call stub
7727 and the target PC is in $2. Otherwise this is effectively
7728 a return stub and the target PC is in $18. */
7729 else if (mips_is_stub_mode (name
+ prefixlen
)
7730 && name
[prefixlen
+ 2] == '_'
7731 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7733 if (pc
== start_addr
)
7734 /* This is the 'call' part of a call stub. The return
7735 address is in $2. */
7736 return get_frame_register_signed
7737 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7739 /* This is the 'return' part of a call stub. The return
7740 address is in $18. */
7741 return get_frame_register_signed
7742 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7745 return 0; /* Not a stub. */
7748 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7749 compiler-generated call or call/return stubs. */
7750 if (startswith (name
, mips_str_fn_stub
)
7751 || startswith (name
, mips_str_call_stub
))
7753 if (pc
== start_addr
)
7754 /* This is the 'call' part of a call stub. Call this helper
7755 to scan through this code for interesting instructions
7756 and determine the final PC. */
7757 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7759 /* This is the 'return' part of a call stub. The return address
7761 return get_frame_register_signed
7762 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7765 return 0; /* Not a stub. */
7768 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7769 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7772 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7774 CORE_ADDR start_addr
;
7777 /* Find the starting address of the function containing the PC. */
7778 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7781 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7782 the start, i.e. after the JALR instruction, this is effectively
7784 prefixlen
= strlen (mips_str_mips16_call_stub
);
7785 if (pc
!= start_addr
7786 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7787 && mips_is_stub_mode (name
+ prefixlen
)
7788 && name
[prefixlen
+ 2] == '_'
7789 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7792 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7793 the JAL or JALR instruction, this is effectively a return stub. */
7794 prefixlen
= strlen (mips_str_call_fp_stub
);
7795 if (pc
!= start_addr
7796 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7799 /* Consume the .pic. prefix of any PIC stub, this function must return
7800 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7801 or the call stub path will trigger in handle_inferior_event causing
7803 prefixlen
= strlen (mips_str_pic
);
7804 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7807 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7808 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7809 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7810 && mips_is_stub_mode (name
+ prefixlen
)
7811 && name
[prefixlen
+ 2] == '\0')
7814 return 0; /* Not a stub. */
7817 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7818 PC of the stub target. The stub just loads $t9 and jumps to it,
7819 so that $t9 has the correct value at function entry. */
7822 mips_skip_pic_trampoline_code (const frame_info_ptr
&frame
, CORE_ADDR pc
)
7824 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7825 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7826 struct bound_minimal_symbol msym
;
7828 gdb_byte stub_code
[16];
7829 int32_t stub_words
[4];
7831 /* The stub for foo is named ".pic.foo", and is either two
7832 instructions inserted before foo or a three instruction sequence
7833 which jumps to foo. */
7834 msym
= lookup_minimal_symbol_by_pc (pc
);
7835 if (msym
.minsym
== NULL
7836 || msym
.value_address () != pc
7837 || msym
.minsym
->linkage_name () == NULL
7838 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7841 /* A two-instruction header. */
7842 if (msym
.minsym
->size () == 8)
7845 /* A three-instruction (plus delay slot) trampoline. */
7846 if (msym
.minsym
->size () == 16)
7848 if (target_read_memory (pc
, stub_code
, 16) != 0)
7850 for (i
= 0; i
< 4; i
++)
7851 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7854 /* A stub contains these instructions:
7857 addiu t9, t9, %lo(target)
7860 This works even for N64, since stubs are only generated with
7862 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7863 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7864 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7865 && stub_words
[3] == 0x00000000)
7866 return ((((stub_words
[0] & 0x0000ffff) << 16)
7867 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7870 /* Not a recognized stub. */
7875 mips_skip_trampoline_code (const frame_info_ptr
&frame
, CORE_ADDR pc
)
7877 CORE_ADDR requested_pc
= pc
;
7878 CORE_ADDR target_pc
;
7885 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7889 new_pc
= find_solib_trampoline_target (frame
, pc
);
7893 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7897 while (pc
!= target_pc
);
7899 return pc
!= requested_pc
? pc
: 0;
7902 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7903 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7906 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7909 if (num
>= 0 && num
< 32)
7911 else if (num
>= 38 && num
< 70)
7912 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7914 regnum
= mips_regnum (gdbarch
)->hi
;
7916 regnum
= mips_regnum (gdbarch
)->lo
;
7917 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7918 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7921 return gdbarch_num_regs (gdbarch
) + regnum
;
7925 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7926 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7929 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7932 if (num
>= 0 && num
< 32)
7934 else if (num
>= 32 && num
< 64)
7935 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7937 regnum
= mips_regnum (gdbarch
)->hi
;
7939 regnum
= mips_regnum (gdbarch
)->lo
;
7940 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7941 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7944 return gdbarch_num_regs (gdbarch
) + regnum
;
7948 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7950 /* Only makes sense to supply raw registers. */
7951 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7952 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7953 decide if it is valid. Should instead define a standard sim/gdb
7954 register numbering scheme. */
7955 if (gdbarch_register_name (gdbarch
,
7956 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
7959 return LEGACY_SIM_REGNO_IGNORE
;
7963 /* Convert an integer into an address. Extracting the value signed
7964 guarantees a correctly sign extended address. */
7967 mips_integer_to_address (struct gdbarch
*gdbarch
,
7968 struct type
*type
, const gdb_byte
*buf
)
7970 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7971 return extract_signed_integer (buf
, type
->length (), byte_order
);
7974 /* Dummy virtual frame pointer method. This is no more or less accurate
7975 than most other architectures; we just need to be explicit about it,
7976 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7977 an assertion failure. */
7980 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7981 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7983 *reg
= MIPS_SP_REGNUM
;
7988 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7990 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7991 const char *name
= bfd_section_name (sect
);
7993 if (*abip
!= MIPS_ABI_UNKNOWN
)
7996 if (!startswith (name
, ".mdebug."))
7999 if (strcmp (name
, ".mdebug.abi32") == 0)
8000 *abip
= MIPS_ABI_O32
;
8001 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8002 *abip
= MIPS_ABI_N32
;
8003 else if (strcmp (name
, ".mdebug.abi64") == 0)
8004 *abip
= MIPS_ABI_N64
;
8005 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8006 *abip
= MIPS_ABI_O64
;
8007 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8008 *abip
= MIPS_ABI_EABI32
;
8009 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8010 *abip
= MIPS_ABI_EABI64
;
8012 warning (_("unsupported ABI %s."), name
+ 8);
8016 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8018 int *lbp
= (int *) obj
;
8019 const char *name
= bfd_section_name (sect
);
8021 if (startswith (name
, ".gcc_compiled_long32"))
8023 else if (startswith (name
, ".gcc_compiled_long64"))
8025 else if (startswith (name
, ".gcc_compiled_long"))
8026 warning (_("unrecognized .gcc_compiled_longXX"));
8029 static enum mips_abi
8030 global_mips_abi (void)
8034 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8035 if (mips_abi_strings
[i
] == mips_abi_string
)
8036 return (enum mips_abi
) i
;
8038 internal_error (_("unknown ABI string"));
8041 /* Return the default compressed instruction set, either of MIPS16
8042 or microMIPS, selected when none could have been determined from
8043 the ELF header of the binary being executed (or no binary has been
8046 static enum mips_isa
8047 global_mips_compression (void)
8051 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8052 if (mips_compression_strings
[i
] == mips_compression_string
)
8053 return (enum mips_isa
) i
;
8055 internal_error (_("unknown compressed ISA string"));
8059 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8061 /* If the size matches the set of 32-bit or 64-bit integer registers,
8062 assume that's what we've got. */
8063 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8064 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8066 /* If the size matches the full set of registers GDB traditionally
8067 knows about, including floating point, for either 32-bit or
8068 64-bit, assume that's what we've got. */
8069 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8070 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8072 /* Otherwise we don't have a useful guess. */
8075 static struct value
*
8076 value_of_mips_user_reg (const frame_info_ptr
&frame
, const void *baton
)
8078 const int *reg_p
= (const int *) baton
;
8079 return value_of_register (*reg_p
, get_next_frame_sentinel_okay (frame
));
8082 static struct gdbarch
*
8083 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8086 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8088 enum mips_fpu_type fpu_type
;
8089 tdesc_arch_data_up tdesc_data
;
8090 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8091 const char * const *reg_names
;
8092 struct mips_regnum mips_regnum
, *regnum
;
8093 enum mips_isa mips_isa
;
8097 /* First of all, extract the elf_flags, if available. */
8098 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8099 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8100 else if (arches
!= NULL
)
8102 mips_gdbarch_tdep
*tdep
8103 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8104 elf_flags
= tdep
->elf_flags
;
8109 gdb_printf (gdb_stdlog
,
8110 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8112 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8113 switch ((elf_flags
& EF_MIPS_ABI
))
8115 case EF_MIPS_ABI_O32
:
8116 found_abi
= MIPS_ABI_O32
;
8118 case EF_MIPS_ABI_O64
:
8119 found_abi
= MIPS_ABI_O64
;
8121 case EF_MIPS_ABI_EABI32
:
8122 found_abi
= MIPS_ABI_EABI32
;
8124 case EF_MIPS_ABI_EABI64
:
8125 found_abi
= MIPS_ABI_EABI64
;
8128 if ((elf_flags
& EF_MIPS_ABI2
))
8129 found_abi
= MIPS_ABI_N32
;
8131 found_abi
= MIPS_ABI_UNKNOWN
;
8135 /* GCC creates a pseudo-section whose name describes the ABI. */
8136 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8137 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8139 /* If we have no useful BFD information, use the ABI from the last
8140 MIPS architecture (if there is one). */
8141 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8143 mips_gdbarch_tdep
*tdep
8144 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8145 found_abi
= tdep
->found_abi
;
8148 /* Try the architecture for any hint of the correct ABI. */
8149 if (found_abi
== MIPS_ABI_UNKNOWN
8150 && info
.bfd_arch_info
!= NULL
8151 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8153 switch (info
.bfd_arch_info
->mach
)
8155 case bfd_mach_mips3900
:
8156 found_abi
= MIPS_ABI_EABI32
;
8158 case bfd_mach_mips4100
:
8159 case bfd_mach_mips5000
:
8160 found_abi
= MIPS_ABI_EABI64
;
8162 case bfd_mach_mips8000
:
8163 case bfd_mach_mips10000
:
8164 /* On Irix, ELF64 executables use the N64 ABI. The
8165 pseudo-sections which describe the ABI aren't present
8166 on IRIX. (Even for executables created by gcc.) */
8167 if (info
.abfd
!= NULL
8168 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8169 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8170 found_abi
= MIPS_ABI_N64
;
8172 found_abi
= MIPS_ABI_N32
;
8177 /* Default 64-bit objects to N64 instead of O32. */
8178 if (found_abi
== MIPS_ABI_UNKNOWN
8179 && info
.abfd
!= NULL
8180 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8181 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8182 found_abi
= MIPS_ABI_N64
;
8185 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8188 /* What has the user specified from the command line? */
8189 wanted_abi
= global_mips_abi ();
8191 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8194 /* Now that we have found what the ABI for this binary would be,
8195 check whether the user is overriding it. */
8196 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8197 mips_abi
= wanted_abi
;
8198 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8199 mips_abi
= found_abi
;
8201 mips_abi
= MIPS_ABI_O32
;
8203 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8206 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8207 if (mips_abi
!= MIPS_ABI_EABI32
8208 && mips_abi
!= MIPS_ABI_O32
8209 && info
.bfd_arch_info
!= NULL
8210 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8211 && info
.bfd_arch_info
->bits_per_word
< 64)
8212 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8214 /* Determine the default compressed ISA. */
8215 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8216 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8217 mips_isa
= ISA_MICROMIPS
;
8218 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8219 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8220 mips_isa
= ISA_MIPS16
;
8222 mips_isa
= global_mips_compression ();
8223 mips_compression_string
= mips_compression_strings
[mips_isa
];
8225 /* Also used when doing an architecture lookup. */
8227 gdb_printf (gdb_stdlog
,
8228 "mips_gdbarch_init: "
8229 "mips64_transfers_32bit_regs_p = %d\n",
8230 mips64_transfers_32bit_regs_p
);
8232 /* Determine the MIPS FPU type. */
8235 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8236 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8237 Tag_GNU_MIPS_ABI_FP
);
8238 #endif /* HAVE_ELF */
8240 if (!mips_fpu_type_auto
)
8241 fpu_type
= mips_fpu_type
;
8242 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8244 switch (elf_fpu_type
)
8246 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8247 fpu_type
= MIPS_FPU_DOUBLE
;
8249 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8250 fpu_type
= MIPS_FPU_SINGLE
;
8252 case Val_GNU_MIPS_ABI_FP_SOFT
:
8254 /* Soft float or unknown. */
8255 fpu_type
= MIPS_FPU_NONE
;
8259 else if (info
.bfd_arch_info
!= NULL
8260 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8261 switch (info
.bfd_arch_info
->mach
)
8263 case bfd_mach_mips3900
:
8264 case bfd_mach_mips4100
:
8265 case bfd_mach_mips4111
:
8266 case bfd_mach_mips4120
:
8267 fpu_type
= MIPS_FPU_NONE
;
8269 case bfd_mach_mips4650
:
8270 fpu_type
= MIPS_FPU_SINGLE
;
8273 fpu_type
= MIPS_FPU_DOUBLE
;
8276 else if (arches
!= NULL
)
8277 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8279 fpu_type
= MIPS_FPU_DOUBLE
;
8281 gdb_printf (gdb_stdlog
,
8282 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8284 /* Check for blatant incompatibilities. */
8286 /* If we have only 32-bit registers, then we can't debug a 64-bit
8288 if (info
.target_desc
8289 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8290 && mips_abi
!= MIPS_ABI_EABI32
8291 && mips_abi
!= MIPS_ABI_O32
)
8294 /* Fill in the OS dependent register numbers and names. */
8295 if (info
.osabi
== GDB_OSABI_LINUX
)
8297 mips_regnum
.fp0
= 38;
8298 mips_regnum
.pc
= 37;
8299 mips_regnum
.cause
= 36;
8300 mips_regnum
.badvaddr
= 35;
8301 mips_regnum
.hi
= 34;
8302 mips_regnum
.lo
= 33;
8303 mips_regnum
.fp_control_status
= 70;
8304 mips_regnum
.fp_implementation_revision
= 71;
8305 mips_regnum
.dspacc
= -1;
8306 mips_regnum
.dspctl
= -1;
8310 reg_names
= mips_linux_reg_names
;
8314 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8315 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8316 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8317 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8318 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8319 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8320 mips_regnum
.fp_control_status
= 70;
8321 mips_regnum
.fp_implementation_revision
= 71;
8322 mips_regnum
.dspacc
= dspacc
= -1;
8323 mips_regnum
.dspctl
= dspctl
= -1;
8324 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8325 if (info
.bfd_arch_info
!= NULL
8326 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8327 reg_names
= mips_tx39_reg_names
;
8329 reg_names
= mips_generic_reg_names
;
8332 /* Check any target description for validity. */
8333 if (tdesc_has_registers (info
.target_desc
))
8335 static const char *const mips_gprs
[] = {
8336 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8337 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8338 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8339 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8341 static const char *const mips_fprs
[] = {
8342 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8343 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8344 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8345 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8348 const struct tdesc_feature
*feature
;
8351 feature
= tdesc_find_feature (info
.target_desc
,
8352 "org.gnu.gdb.mips.cpu");
8353 if (feature
== NULL
)
8356 tdesc_data
= tdesc_data_alloc ();
8359 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8360 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8364 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8365 mips_regnum
.lo
, "lo");
8366 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8367 mips_regnum
.hi
, "hi");
8368 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8369 mips_regnum
.pc
, "pc");
8374 feature
= tdesc_find_feature (info
.target_desc
,
8375 "org.gnu.gdb.mips.cp0");
8376 if (feature
== NULL
)
8380 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8381 mips_regnum
.badvaddr
, "badvaddr");
8382 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8383 MIPS_PS_REGNUM
, "status");
8384 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8385 mips_regnum
.cause
, "cause");
8390 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8391 backend is not prepared for that, though. */
8392 feature
= tdesc_find_feature (info
.target_desc
,
8393 "org.gnu.gdb.mips.fpu");
8394 if (feature
== NULL
)
8398 for (i
= 0; i
< 32; i
++)
8399 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8400 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8402 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8403 mips_regnum
.fp_control_status
,
8406 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8407 mips_regnum
.fp_implementation_revision
,
8413 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8417 feature
= tdesc_find_feature (info
.target_desc
,
8418 "org.gnu.gdb.mips.dsp");
8419 /* The DSP registers are optional; it's OK if they are absent. */
8420 if (feature
!= NULL
)
8424 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8425 dspacc
+ i
++, "hi1");
8426 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8427 dspacc
+ i
++, "lo1");
8428 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8429 dspacc
+ i
++, "hi2");
8430 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8431 dspacc
+ i
++, "lo2");
8432 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8433 dspacc
+ i
++, "hi3");
8434 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8435 dspacc
+ i
++, "lo3");
8437 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8443 mips_regnum
.dspacc
= dspacc
;
8444 mips_regnum
.dspctl
= dspctl
;
8446 num_regs
= mips_regnum
.dspctl
+ 1;
8450 /* It would be nice to detect an attempt to use a 64-bit ABI
8451 when only 32-bit registers are provided. */
8455 /* Try to find a pre-existing architecture. */
8456 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8458 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8460 mips_gdbarch_tdep
*tdep
8461 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8463 /* MIPS needs to be pedantic about which ABI and the compressed
8464 ISA variation the object is using. */
8465 if (tdep
->elf_flags
!= elf_flags
)
8467 if (tdep
->mips_abi
!= mips_abi
)
8469 if (tdep
->mips_isa
!= mips_isa
)
8471 /* Need to be pedantic about which register virtual size is
8473 if (tdep
->mips64_transfers_32bit_regs_p
8474 != mips64_transfers_32bit_regs_p
)
8476 /* Be pedantic about which FPU is selected. */
8477 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8480 return arches
->gdbarch
;
8483 /* Need a new architecture. Fill in a target specific vector. */
8485 = gdbarch_alloc (&info
, gdbarch_tdep_up (new mips_gdbarch_tdep
));
8486 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8488 tdep
->elf_flags
= elf_flags
;
8489 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8490 tdep
->found_abi
= found_abi
;
8491 tdep
->mips_abi
= mips_abi
;
8492 tdep
->mips_isa
= mips_isa
;
8493 tdep
->mips_fpu_type
= fpu_type
;
8494 tdep
->register_size_valid_p
= 0;
8495 tdep
->register_size
= 0;
8497 if (info
.target_desc
)
8499 /* Some useful properties can be inferred from the target. */
8500 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8502 tdep
->register_size_valid_p
= 1;
8503 tdep
->register_size
= 4;
8505 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8507 tdep
->register_size_valid_p
= 1;
8508 tdep
->register_size
= 8;
8512 /* Initially set everything according to the default ABI/ISA. */
8513 set_gdbarch_short_bit (gdbarch
, 16);
8514 set_gdbarch_int_bit (gdbarch
, 32);
8515 set_gdbarch_float_bit (gdbarch
, 32);
8516 set_gdbarch_double_bit (gdbarch
, 64);
8517 set_gdbarch_long_double_bit (gdbarch
, 64);
8518 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8519 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8520 set_gdbarch_deprecated_pseudo_register_write (gdbarch
,
8521 mips_pseudo_register_write
);
8523 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8524 mips_ax_pseudo_register_collect
);
8525 set_gdbarch_ax_pseudo_register_push_stack
8526 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8528 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8529 mips_elf_make_msymbol_special
);
8530 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8531 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8532 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8534 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8535 *regnum
= mips_regnum
;
8536 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8537 set_gdbarch_num_regs (gdbarch
, num_regs
);
8538 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8539 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8540 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8541 tdep
->mips_processor_reg_names
= reg_names
;
8542 tdep
->regnum
= regnum
;
8547 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8548 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8549 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8550 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8551 tdep
->default_mask_address_p
= 0;
8552 set_gdbarch_long_bit (gdbarch
, 32);
8553 set_gdbarch_ptr_bit (gdbarch
, 32);
8554 set_gdbarch_long_long_bit (gdbarch
, 64);
8557 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8558 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8559 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8560 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8561 tdep
->default_mask_address_p
= 0;
8562 set_gdbarch_long_bit (gdbarch
, 32);
8563 set_gdbarch_ptr_bit (gdbarch
, 32);
8564 set_gdbarch_long_long_bit (gdbarch
, 64);
8566 case MIPS_ABI_EABI32
:
8567 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8568 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8569 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8570 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8571 tdep
->default_mask_address_p
= 0;
8572 set_gdbarch_long_bit (gdbarch
, 32);
8573 set_gdbarch_ptr_bit (gdbarch
, 32);
8574 set_gdbarch_long_long_bit (gdbarch
, 64);
8576 case MIPS_ABI_EABI64
:
8577 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8578 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8579 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8580 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8581 tdep
->default_mask_address_p
= 0;
8582 set_gdbarch_long_bit (gdbarch
, 64);
8583 set_gdbarch_ptr_bit (gdbarch
, 64);
8584 set_gdbarch_long_long_bit (gdbarch
, 64);
8587 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8588 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8589 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8590 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8591 tdep
->default_mask_address_p
= 0;
8592 set_gdbarch_long_bit (gdbarch
, 32);
8593 set_gdbarch_ptr_bit (gdbarch
, 32);
8594 set_gdbarch_long_long_bit (gdbarch
, 64);
8595 set_gdbarch_long_double_bit (gdbarch
, 128);
8596 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8599 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8600 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8601 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8602 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8603 tdep
->default_mask_address_p
= 0;
8604 set_gdbarch_long_bit (gdbarch
, 64);
8605 set_gdbarch_ptr_bit (gdbarch
, 64);
8606 set_gdbarch_long_long_bit (gdbarch
, 64);
8607 set_gdbarch_long_double_bit (gdbarch
, 128);
8608 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8611 internal_error (_("unknown ABI in switch"));
8614 /* GCC creates a pseudo-section whose name specifies the size of
8615 longs, since -mlong32 or -mlong64 may be used independent of
8616 other options. How those options affect pointer sizes is ABI and
8617 architecture dependent, so use them to override the default sizes
8618 set by the ABI. This table shows the relationship between ABI,
8619 -mlongXX, and size of pointers:
8621 ABI -mlongXX ptr bits
8622 --- -------- --------
8636 Note that for o32 and eabi32, pointers are always 32 bits
8637 regardless of any -mlongXX option. For all others, pointers and
8638 longs are the same, as set by -mlongXX or set by defaults. */
8640 if (info
.abfd
!= NULL
)
8644 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8647 set_gdbarch_long_bit (gdbarch
, long_bit
);
8651 case MIPS_ABI_EABI32
:
8656 case MIPS_ABI_EABI64
:
8657 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8660 internal_error (_("unknown ABI in switch"));
8665 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8666 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8669 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8670 flag in object files because to do so would make it impossible to
8671 link with libraries compiled without "-gp32". This is
8672 unnecessarily restrictive.
8674 We could solve this problem by adding "-gp32" multilibs to gcc,
8675 but to set this flag before gcc is built with such multilibs will
8676 break too many systems.''
8678 But even more unhelpfully, the default linker output target for
8679 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8680 for 64-bit programs - you need to change the ABI to change this,
8681 and not all gcc targets support that currently. Therefore using
8682 this flag to detect 32-bit mode would do the wrong thing given
8683 the current gcc - it would make GDB treat these 64-bit programs
8684 as 32-bit programs by default. */
8686 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8687 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8689 /* Add/remove bits from an address. The MIPS needs be careful to
8690 ensure that all 32 bit addresses are sign extended to 64 bits. */
8691 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8693 /* Unwind the frame. */
8694 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8695 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8696 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8698 /* Map debug register numbers onto internal register numbers. */
8699 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8700 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8701 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8702 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8703 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8704 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8706 /* MIPS version of CALL_DUMMY. */
8708 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8709 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8710 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8712 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8714 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8715 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8716 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8718 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8719 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8720 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8721 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8722 mips_adjust_breakpoint_address
);
8724 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8726 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8728 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8729 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8730 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8732 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8734 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8736 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8737 if (mips_abi
== MIPS_ABI_N64
)
8738 set_gdbarch_disassembler_options_implicit (gdbarch
,
8739 mips_disassembler_options_n64
);
8740 else if (mips_abi
== MIPS_ABI_N32
)
8741 set_gdbarch_disassembler_options_implicit (gdbarch
,
8742 mips_disassembler_options_n32
);
8744 set_gdbarch_disassembler_options_implicit (gdbarch
,
8745 mips_disassembler_options_o32
);
8746 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8747 set_gdbarch_valid_disassembler_options (gdbarch
,
8748 disassembler_options_mips ());
8750 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8751 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8752 need to all be folded into the target vector. Since they are
8753 being used as guards for target_stopped_by_watchpoint, why not have
8754 target_stopped_by_watchpoint return the type of watchpoint that the code
8756 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8758 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8760 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8761 to support MIPS16. This is a bad thing. Make sure not to do it
8762 if we have an OS ABI that actually supports shared libraries, since
8763 shared library support is more important. If we have an OS someday
8764 that supports both shared libraries and MIPS16, we'll have to find
8765 a better place for these.
8766 macro/2012-04-25: But that applies to return trampolines only and
8767 currently no MIPS OS ABI uses shared libraries that have them. */
8768 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8770 set_gdbarch_single_step_through_delay (gdbarch
,
8771 mips_single_step_through_delay
);
8773 /* Virtual tables. */
8774 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8776 mips_register_g_packet_guesses (gdbarch
);
8778 /* Hook in OS ABI-specific overrides, if they have been registered. */
8779 info
.tdesc_data
= tdesc_data
.get ();
8780 gdbarch_init_osabi (info
, gdbarch
);
8782 /* The hook may have adjusted num_regs, fetch the final value and
8783 set pc_regnum and sp_regnum now that it has been fixed. */
8784 num_regs
= gdbarch_num_regs (gdbarch
);
8785 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8786 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8788 /* Unwind the frame. */
8789 dwarf2_append_unwinders (gdbarch
);
8790 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8791 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8792 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8793 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8794 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8795 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8796 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8797 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8798 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8800 if (tdesc_data
!= nullptr)
8802 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8803 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8805 /* Override the normal target description methods to handle our
8806 dual real and pseudo registers. */
8807 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8808 set_gdbarch_register_reggroup_p (gdbarch
,
8809 mips_tdesc_register_reggroup_p
);
8811 num_regs
= gdbarch_num_regs (gdbarch
);
8812 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8813 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8814 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8817 /* Add ABI-specific aliases for the registers. */
8818 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8819 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8820 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8821 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8823 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8824 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8825 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8827 /* Add some other standard aliases. */
8828 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8829 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8830 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8832 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8833 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8834 value_of_mips_user_reg
,
8835 &mips_numeric_register_aliases
[i
].regnum
);
8841 mips_abi_update (const char *ignore_args
,
8842 int from_tty
, struct cmd_list_element
*c
)
8844 struct gdbarch_info info
;
8846 /* Force the architecture to update, and (if it's a MIPS architecture)
8847 mips_gdbarch_init will take care of the rest. */
8848 gdbarch_update_p (info
);
8851 /* Print out which MIPS ABI is in use. */
8854 show_mips_abi (struct ui_file
*file
,
8856 struct cmd_list_element
*ignored_cmd
,
8857 const char *ignored_value
)
8859 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
8863 "The MIPS ABI is unknown because the current architecture "
8867 enum mips_abi global_abi
= global_mips_abi ();
8868 enum mips_abi actual_abi
= mips_abi (current_inferior ()->arch ());
8869 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8871 if (global_abi
== MIPS_ABI_UNKNOWN
)
8874 "The MIPS ABI is set automatically (currently \"%s\").\n",
8876 else if (global_abi
== actual_abi
)
8879 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8883 /* Probably shouldn't happen... */
8885 "The (auto detected) MIPS ABI \"%s\" is in use "
8886 "even though the user setting was \"%s\".\n",
8887 actual_abi_str
, mips_abi_strings
[global_abi
]);
8892 /* Print out which MIPS compressed ISA encoding is used. */
8895 show_mips_compression (struct ui_file
*file
, int from_tty
,
8896 struct cmd_list_element
*c
, const char *value
)
8898 gdb_printf (file
, _("The compressed ISA encoding used is %s.\n"),
8902 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8905 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8911 case MIPS_FPU_SINGLE
:
8913 case MIPS_FPU_DOUBLE
:
8921 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8923 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8927 int ef_mips_32bitmode
;
8928 /* Determine the ISA. */
8929 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8931 case EF_MIPS_ARCH_1
:
8934 case EF_MIPS_ARCH_2
:
8937 case EF_MIPS_ARCH_3
:
8940 case EF_MIPS_ARCH_4
:
8947 /* Determine the size of a pointer. */
8948 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8950 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8953 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8956 "mips_dump_tdep: ef_mips_arch = %d\n",
8959 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8960 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8963 "mips_mask_address_p() %d (default %d)\n",
8964 mips_mask_address_p (tdep
),
8965 tdep
->default_mask_address_p
);
8968 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8969 MIPS_DEFAULT_FPU_TYPE
,
8970 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8971 gdb_printf (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8972 mips_eabi (gdbarch
));
8974 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8975 mips_get_fpu_type (gdbarch
),
8976 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8979 void _initialize_mips_tdep ();
8981 _initialize_mips_tdep ()
8983 static struct cmd_list_element
*mipsfpulist
= NULL
;
8985 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8986 if (MIPS_ABI_LAST
+ 1
8987 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8988 internal_error (_("mips_abi_strings out of sync"));
8990 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8992 /* Create feature sets with the appropriate properties. The values
8993 are not important. */
8994 mips_tdesc_gp32
= allocate_target_description ().release ();
8995 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8997 mips_tdesc_gp64
= allocate_target_description ().release ();
8998 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9000 /* Add root prefix command for all "set mips"/"show mips" commands. */
9001 add_setshow_prefix_cmd ("mips", no_class
,
9002 _("Various MIPS specific commands."),
9003 _("Various MIPS specific commands."),
9004 &setmipscmdlist
, &showmipscmdlist
,
9005 &setlist
, &showlist
);
9007 /* Allow the user to override the ABI. */
9008 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9009 &mips_abi_string
, _("\
9010 Set the MIPS ABI used by this program."), _("\
9011 Show the MIPS ABI used by this program."), _("\
9012 This option can be set to one of:\n\
9013 auto - the default ABI associated with the current binary\n\
9022 &setmipscmdlist
, &showmipscmdlist
);
9024 /* Allow the user to set the ISA to assume for compressed code if ELF
9025 file flags don't tell or there is no program file selected. This
9026 setting is updated whenever unambiguous ELF file flags are interpreted,
9027 and carried over to subsequent sessions. */
9028 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9029 &mips_compression_string
, _("\
9030 Set the compressed ISA encoding used by MIPS code."), _("\
9031 Show the compressed ISA encoding used by MIPS code."), _("\
9032 Select the compressed ISA encoding used in functions that have no symbol\n\
9033 information available. The encoding can be set to either of:\n\
9036 and is updated automatically from ELF file flags if available."),
9038 show_mips_compression
,
9039 &setmipscmdlist
, &showmipscmdlist
);
9041 /* Let the user turn off floating point and set the fence post for
9042 heuristic_proc_start. */
9044 add_basic_prefix_cmd ("mipsfpu", class_support
,
9045 _("Set use of MIPS floating-point coprocessor."),
9046 &mipsfpulist
, 0, &setlist
);
9047 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9048 _("Select single-precision MIPS floating-point coprocessor."),
9050 cmd_list_element
*set_mipsfpu_double_cmd
9051 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9052 _("Select double-precision MIPS floating-point coprocessor."),
9054 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9055 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9056 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9058 cmd_list_element
*set_mipsfpu_none_cmd
9059 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9060 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9061 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9062 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9063 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9064 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9065 _("Select MIPS floating-point coprocessor automatically."),
9067 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9068 _("Show current use of MIPS floating-point coprocessor target."),
9071 /* We really would like to have both "0" and "unlimited" work, but
9072 command.c doesn't deal with that. So make it a var_zinteger
9073 because the user can always use "999999" or some such for unlimited. */
9074 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9075 &heuristic_fence_post
, _("\
9076 Set the distance searched for the start of a function."), _("\
9077 Show the distance searched for the start of a function."), _("\
9078 If you are debugging a stripped executable, GDB needs to search through the\n\
9079 program for the start of a function. This command sets the distance of the\n\
9080 search. The only need to set it is when debugging a stripped executable."),
9081 reinit_frame_cache_sfunc
,
9082 NULL
, /* FIXME: i18n: The distance searched for
9083 the start of a function is %s. */
9084 &setlist
, &showlist
);
9086 /* Allow the user to control whether the upper bits of 64-bit
9087 addresses should be zeroed. */
9088 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9089 &mask_address_var
, _("\
9090 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9091 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9092 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9093 allow GDB to determine the correct value."),
9094 NULL
, show_mask_address
,
9095 &setmipscmdlist
, &showmipscmdlist
);
9097 /* Allow the user to control the size of 32 bit registers within the
9098 raw remote packet. */
9099 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9100 &mips64_transfers_32bit_regs_p
, _("\
9101 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9103 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9105 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9106 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9107 64 bits for others. Use \"off\" to disable compatibility mode"),
9108 set_mips64_transfers_32bit_regs
,
9109 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9110 MIPS target that transfers 32-bit
9111 quantities is %s. */
9112 &setlist
, &showlist
);
9114 /* Debug this files internals. */
9115 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9117 Set mips debugging."), _("\
9118 Show mips debugging."), _("\
9119 When non-zero, mips specific debugging is enabled."),
9121 NULL
, /* FIXME: i18n: Mips debugging is
9123 &setdebuglist
, &showdebuglist
);