1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2024 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 frame_info_ptr
, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
235 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
237 return mips_regnum (gdbarch
)->fp0
+ 12;
240 /* Return 1 if REGNUM refers to a floating-point general register, raw
241 or cooked. Otherwise return 0. */
244 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
246 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
248 return (rawnum
>= mips_regnum (gdbarch
)->fp0
249 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
253 mips_eabi (gdbarch
*arch
)
255 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
256 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
257 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
261 mips_last_fp_arg_regnum (gdbarch
*arch
)
263 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
264 return tdep
->mips_last_fp_arg_regnum
;
268 mips_last_arg_regnum (gdbarch
*arch
)
270 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
271 return tdep
->mips_last_arg_regnum
;
274 static enum mips_fpu_type
275 mips_get_fpu_type (gdbarch
*arch
)
277 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
278 return tdep
->mips_fpu_type
;
281 /* Return the MIPS ABI associated with GDBARCH. */
283 mips_abi (struct gdbarch
*gdbarch
)
285 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
286 return tdep
->mips_abi
;
290 mips_isa_regsize (struct gdbarch
*gdbarch
)
292 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
294 /* If we know how big the registers are, use that size. */
295 if (tdep
->register_size_valid_p
)
296 return tdep
->register_size
;
298 /* Fall back to the previous behavior. */
299 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
300 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
303 /* Max saved register size. */
304 #define MAX_MIPS_ABI_REGSIZE 8
306 /* Return the currently configured (or set) saved register size. */
309 mips_abi_regsize (struct gdbarch
*gdbarch
)
311 switch (mips_abi (gdbarch
))
313 case MIPS_ABI_EABI32
:
319 case MIPS_ABI_EABI64
:
321 case MIPS_ABI_UNKNOWN
:
324 internal_error (_("bad switch"));
328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
329 are some functions to handle addresses associated with compressed
330 code including but not limited to testing, setting, or clearing
331 bit 0 of such addresses. */
333 /* Return one iff compressed code is the MIPS16 instruction set. */
336 is_mips16_isa (struct gdbarch
*gdbarch
)
338 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
339 return tdep
->mips_isa
== ISA_MIPS16
;
342 /* Return one iff compressed code is the microMIPS instruction set. */
345 is_micromips_isa (struct gdbarch
*gdbarch
)
347 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
348 return tdep
->mips_isa
== ISA_MICROMIPS
;
351 /* Return one iff ADDR denotes compressed code. */
354 is_compact_addr (CORE_ADDR addr
)
359 /* Return one iff ADDR denotes standard ISA code. */
362 is_mips_addr (CORE_ADDR addr
)
364 return !is_compact_addr (addr
);
367 /* Return one iff ADDR denotes MIPS16 code. */
370 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
372 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
375 /* Return one iff ADDR denotes microMIPS code. */
378 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
380 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
383 /* Strip the ISA (compression) bit off from ADDR. */
386 unmake_compact_addr (CORE_ADDR addr
)
388 return ((addr
) & ~(CORE_ADDR
) 1);
391 /* Add the ISA (compression) bit to ADDR. */
394 make_compact_addr (CORE_ADDR addr
)
396 return ((addr
) | (CORE_ADDR
) 1);
399 /* Extern version of unmake_compact_addr; we use a separate function
400 so that unmake_compact_addr can be inlined throughout this file. */
403 mips_unmake_compact_addr (CORE_ADDR addr
)
405 return unmake_compact_addr (addr
);
408 /* Functions for setting and testing a bit in a minimal symbol that
409 marks it as MIPS16 or microMIPS function. The MSB of the minimal
410 symbol's "info" field is used for this purpose.
412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
414 one of the "special" bits in a minimal symbol to mark it accordingly.
415 The test checks an ELF-private flag that is valid for true function
416 symbols only; for synthetic symbols such as for PLT stubs that have
417 no ELF-private part at all the MIPS BFD backend arranges for this
418 information to be carried in the asymbol's udata field instead.
420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
421 in a minimal symbol. */
424 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
426 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
427 unsigned char st_other
;
429 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
430 st_other
= elfsym
->internal_elf_sym
.st_other
;
431 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
432 st_other
= sym
->udata
.i
;
436 if (ELF_ST_IS_MICROMIPS (st_other
))
438 SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
439 CORE_ADDR fixed
= CORE_ADDR (msym
->unrelocated_address ()) | 1;
440 msym
->set_unrelocated_address (unrelocated_addr (fixed
));
442 else if (ELF_ST_IS_MIPS16 (st_other
))
444 SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
445 CORE_ADDR fixed
= CORE_ADDR (msym
->unrelocated_address ()) | 1;
446 msym
->set_unrelocated_address (unrelocated_addr (fixed
));
450 /* Return one iff MSYM refers to standard ISA code. */
453 msymbol_is_mips (struct minimal_symbol
*msym
)
455 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
456 || MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
459 /* Return one iff MSYM refers to MIPS16 code. */
462 msymbol_is_mips16 (struct minimal_symbol
*msym
)
464 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
467 /* Return one iff MSYM refers to microMIPS code. */
470 msymbol_is_micromips (struct minimal_symbol
*msym
)
472 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
475 /* Set the ISA bit in the main symbol too, complementing the corresponding
476 minimal symbol setting and reflecting the run-time value of the symbol.
477 The need for comes from the ISA bit having been cleared as code in
478 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
479 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
480 of symbols referring to compressed code different in GDB to the values
481 used by actual code. That in turn makes them evaluate incorrectly in
482 expressions, producing results different to what the same expressions
483 yield when compiled into the program being debugged. */
486 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
488 if (sym
->aclass () == LOC_BLOCK
)
490 /* We are in symbol reading so it is OK to cast away constness. */
491 struct block
*block
= (struct block
*) sym
->value_block ();
492 CORE_ADDR compact_block_start
;
493 struct bound_minimal_symbol msym
;
495 compact_block_start
= block
->start () | 1;
496 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
497 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
499 block
->set_start (compact_block_start
);
504 /* XFER a value from the big/little/left end of the register.
505 Depending on the size of the value it might occupy the entire
506 register or just part of it. Make an allowance for this, aligning
507 things accordingly. */
510 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
511 int reg_num
, int length
,
512 enum bfd_endian endian
, gdb_byte
*in
,
513 const gdb_byte
*out
, int buf_offset
)
517 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
518 /* Need to transfer the left or right part of the register, based on
519 the targets byte order. */
523 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
525 case BFD_ENDIAN_LITTLE
:
528 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
532 internal_error (_("bad switch"));
535 gdb_printf (gdb_stderr
,
536 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
537 reg_num
, reg_offset
, buf_offset
, length
);
538 if (mips_debug
&& out
!= NULL
)
541 gdb_printf (gdb_stdlog
, "out ");
542 for (i
= 0; i
< length
; i
++)
543 gdb_printf (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
546 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
548 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
549 if (mips_debug
&& in
!= NULL
)
552 gdb_printf (gdb_stdlog
, "in ");
553 for (i
= 0; i
< length
; i
++)
554 gdb_printf (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
557 gdb_printf (gdb_stdlog
, "\n");
560 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
561 compatiblity mode. A return value of 1 means that we have
562 physical 64-bit registers, but should treat them as 32-bit registers. */
565 mips2_fp_compat (frame_info_ptr frame
)
567 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
568 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
570 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
574 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
575 in all the places we deal with FP registers. PR gdb/413. */
576 /* Otherwise check the FR bit in the status register - it controls
577 the FP compatiblity mode. If it is clear we are in compatibility
579 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
586 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
588 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
590 /* The list of available "set mips " and "show mips " commands. */
592 static struct cmd_list_element
*setmipscmdlist
= NULL
;
593 static struct cmd_list_element
*showmipscmdlist
= NULL
;
595 /* Integer registers 0 thru 31 are handled explicitly by
596 mips_register_name(). Processor specific registers 32 and above
597 are listed in the following tables. */
600 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
604 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
605 "sr", "lo", "hi", "bad", "cause", "pc",
606 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
607 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
608 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
609 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
613 /* Names of tx39 registers. */
615 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
616 "sr", "lo", "hi", "bad", "cause", "pc",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
619 "", "", "", "", "", "", "", "",
620 "", "", "", "", "", "", "", "",
622 "", "", "", "", "", "", "", "",
623 "", "", "config", "cache", "debug", "depc", "epc",
626 /* Names of registers with Linux kernels. */
627 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
628 "sr", "lo", "hi", "bad", "cause", "pc",
629 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
630 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
631 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
632 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
637 /* Return the name of the register corresponding to REGNO. */
639 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
641 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
642 /* GPR names for all ABIs other than n32/n64. */
643 static const char *mips_gpr_names
[] = {
644 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
645 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
646 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
647 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
650 /* GPR names for n32 and n64 ABIs. */
651 static const char *mips_n32_n64_gpr_names
[] = {
652 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
653 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
654 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
655 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
658 enum mips_abi abi
= mips_abi (gdbarch
);
660 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
661 but then don't make the raw register names visible. This (upper)
662 range of user visible register numbers are the pseudo-registers.
664 This approach was adopted accommodate the following scenario:
665 It is possible to debug a 64-bit device using a 32-bit
666 programming model. In such instances, the raw registers are
667 configured to be 64-bits wide, while the pseudo registers are
668 configured to be 32-bits wide. The registers that the user
669 sees - the pseudo registers - match the users expectations
670 given the programming model being used. */
671 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
672 if (regno
< gdbarch_num_regs (gdbarch
))
675 /* The MIPS integer registers are always mapped from 0 to 31. The
676 names of the registers (which reflects the conventions regarding
677 register use) vary depending on the ABI. */
678 if (0 <= rawnum
&& rawnum
< 32)
680 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
681 return mips_n32_n64_gpr_names
[rawnum
];
683 return mips_gpr_names
[rawnum
];
685 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
686 return tdesc_register_name (gdbarch
, rawnum
);
687 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
689 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
690 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
691 return tdep
->mips_processor_reg_names
[rawnum
- 32];
695 internal_error (_("mips_register_name: bad register number %d"), rawnum
);
698 /* Return the groups that a MIPS register can be categorised into. */
701 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
702 const struct reggroup
*reggroup
)
707 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
708 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
709 if (reggroup
== all_reggroup
)
711 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
712 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
713 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
714 (gdbarch), as not all architectures are multi-arch. */
715 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
716 if (gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
718 if (reggroup
== float_reggroup
)
719 return float_p
&& pseudo
;
720 if (reggroup
== vector_reggroup
)
721 return vector_p
&& pseudo
;
722 if (reggroup
== general_reggroup
)
723 return (!vector_p
&& !float_p
) && pseudo
;
724 /* Save the pseudo registers. Need to make certain that any code
725 extracting register values from a saved register cache also uses
727 if (reggroup
== save_reggroup
)
728 return raw_p
&& pseudo
;
729 /* Restore the same pseudo register. */
730 if (reggroup
== restore_reggroup
)
731 return raw_p
&& pseudo
;
735 /* Return the groups that a MIPS register can be categorised into.
736 This version is only used if we have a target description which
737 describes real registers (and their groups). */
740 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
741 const struct reggroup
*reggroup
)
743 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
744 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
747 /* Only save, restore, and display the pseudo registers. Need to
748 make certain that any code extracting register values from a
749 saved register cache also uses pseudo registers.
751 Note: saving and restoring the pseudo registers is slightly
752 strange; if we have 64 bits, we should save and restore all
753 64 bits. But this is hard and has little benefit. */
757 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
761 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
764 /* Map the symbol table registers which live in the range [1 *
765 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
766 registers. Take care of alignment and size problems. */
768 static enum register_status
769 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
770 int cookednum
, gdb_byte
*buf
)
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 return regcache
->raw_read (rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
782 if (tdep
->mips64_transfers_32bit_regs_p
)
783 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 enum register_status status
;
790 status
= regcache
->raw_read (rawnum
, ®val
);
791 if (status
== REG_VALID
)
792 store_signed_integer (buf
, 4, byte_order
, regval
);
797 internal_error (_("bad register size"));
801 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
802 struct regcache
*regcache
, int cookednum
,
805 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
807 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
808 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
809 regcache
->raw_write (rawnum
, buf
);
810 else if (register_size (gdbarch
, rawnum
) >
811 register_size (gdbarch
, cookednum
))
813 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
815 if (tdep
->mips64_transfers_32bit_regs_p
)
816 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
819 /* Sign extend the shortened version of the register prior
820 to placing it in the raw register. This is required for
821 some mips64 parts in order to avoid unpredictable behavior. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
823 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
824 regcache_raw_write_signed (regcache
, rawnum
, regval
);
828 internal_error (_("bad register size"));
832 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
833 struct agent_expr
*ax
, int reg
)
835 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
836 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
837 && reg
< 2 * gdbarch_num_regs (gdbarch
));
839 ax_reg_mask (ax
, rawnum
);
845 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
846 struct agent_expr
*ax
, int reg
)
848 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
849 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
850 && reg
< 2 * gdbarch_num_regs (gdbarch
));
851 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
855 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
857 mips_gdbarch_tdep
*tdep
858 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
860 if (!tdep
->mips64_transfers_32bit_regs_p
861 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
864 ax_simple (ax
, aop_lsh
);
867 ax_simple (ax
, aop_rsh_signed
);
871 internal_error (_("bad register size"));
876 /* Table to translate 3-bit register field to actual register number. */
877 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
879 /* Heuristic_proc_start may hunt through the text section for a long
880 time across a 2400 baud serial line. Allows the user to limit this
883 static int heuristic_fence_post
= 0;
885 /* Number of bytes of storage in the actual machine representation for
886 register N. NOTE: This defines the pseudo register type so need to
887 rebuild the architecture vector. */
889 static bool mips64_transfers_32bit_regs_p
= false;
892 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
893 struct cmd_list_element
*c
)
895 struct gdbarch_info info
;
896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
897 instead of relying on globals. Doing that would let generic code
898 handle the search for this specific architecture. */
899 if (!gdbarch_update_p (info
))
901 mips64_transfers_32bit_regs_p
= 0;
902 error (_("32-bit compatibility mode not supported"));
906 /* Convert to/from a register and the corresponding memory value. */
908 /* This predicate tests for the case of an 8 byte floating point
909 value that is being transferred to or from a pair of floating point
910 registers each of which are (or are considered to be) only 4 bytes
913 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
916 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
917 && register_size (gdbarch
, regnum
) == 4
918 && mips_float_register_p (gdbarch
, regnum
)
919 && type
->code () == TYPE_CODE_FLT
&& type
->length () == 8);
922 /* This predicate tests for the case of a value of less than 8
923 bytes in width that is being transfered to or from an 8 byte
924 general purpose register. */
926 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
929 int num_regs
= gdbarch_num_regs (gdbarch
);
931 return (register_size (gdbarch
, regnum
) == 8
932 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
933 && type
->length () < 8);
937 mips_convert_register_p (struct gdbarch
*gdbarch
,
938 int regnum
, struct type
*type
)
940 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
941 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
945 mips_register_to_value (frame_info_ptr frame
, int regnum
,
946 struct type
*type
, gdb_byte
*to
,
947 int *optimizedp
, int *unavailablep
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
950 frame_info_ptr next_frame
= get_next_frame_sentinel_okay (frame
);
952 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
954 get_frame_register (frame
, regnum
+ 0, to
+ 4);
955 get_frame_register (frame
, regnum
+ 1, to
+ 0);
957 if (!get_frame_register_bytes (next_frame
, regnum
+ 0, 0, { to
+ 4, 4 },
958 optimizedp
, unavailablep
))
961 if (!get_frame_register_bytes (next_frame
, regnum
+ 1, 0, { to
+ 0, 4 },
962 optimizedp
, unavailablep
))
964 *optimizedp
= *unavailablep
= 0;
967 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
969 size_t len
= type
->length ();
972 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
973 if (!get_frame_register_bytes (next_frame
, regnum
, offset
, { to
, len
},
974 optimizedp
, unavailablep
))
977 *optimizedp
= *unavailablep
= 0;
982 internal_error (_("mips_register_to_value: unrecognized case"));
987 mips_value_to_register (frame_info_ptr frame
, int regnum
,
988 struct type
*type
, const gdb_byte
*from
)
990 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
992 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
994 auto from_view
= gdb::make_array_view (from
, 8);
995 frame_info_ptr next_frame
= get_next_frame_sentinel_okay (frame
);
996 put_frame_register (next_frame
, regnum
, from_view
.slice (4));
997 put_frame_register (next_frame
, regnum
+ 1, from_view
.slice (0, 4));
999 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
1002 size_t len
= type
->length ();
1003 frame_info_ptr next_frame
= get_next_frame_sentinel_okay (frame
);
1005 /* Sign extend values, irrespective of type, that are stored to
1006 a 64-bit general purpose register. (32-bit unsigned values
1007 are stored as signed quantities within a 64-bit register.
1008 When performing an operation, in compiled code, that combines
1009 a 32-bit unsigned value with a signed 64-bit value, a type
1010 conversion is first performed that zeroes out the high 32 bits.) */
1011 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1014 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1016 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1017 put_frame_register_bytes (next_frame
, regnum
, 0, {fill
, 8 - len
});
1018 put_frame_register_bytes (next_frame
, regnum
, 8 - len
, {from
, len
});
1022 if (from
[len
-1] & 0x80)
1023 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1025 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1026 put_frame_register_bytes (next_frame
, regnum
, 0, {from
, len
});
1027 put_frame_register_bytes (next_frame
, regnum
, len
, {fill
, 8 - len
});
1032 internal_error (_("mips_value_to_register: unrecognized case"));
1036 /* Return the GDB type object for the "standard" data type of data in
1039 static struct type
*
1040 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1042 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1043 if (mips_float_register_p (gdbarch
, regnum
))
1045 /* The floating-point registers raw, or cooked, always match
1046 mips_isa_regsize(), and also map 1:1, byte for byte. */
1047 if (mips_isa_regsize (gdbarch
) == 4)
1048 return builtin_type (gdbarch
)->builtin_float
;
1050 return builtin_type (gdbarch
)->builtin_double
;
1052 else if (regnum
< gdbarch_num_regs (gdbarch
))
1054 /* The raw or ISA registers. These are all sized according to
1056 if (mips_isa_regsize (gdbarch
) == 4)
1057 return builtin_type (gdbarch
)->builtin_int32
;
1059 return builtin_type (gdbarch
)->builtin_int64
;
1063 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1064 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1066 /* The cooked or ABI registers. These are sized according to
1067 the ABI (with a few complications). */
1068 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1069 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1070 return builtin_type (gdbarch
)->builtin_int32
;
1071 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1072 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1073 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1074 /* The pseudo/cooked view of the embedded registers is always
1075 32-bit. The raw view is handled below. */
1076 return builtin_type (gdbarch
)->builtin_int32
;
1077 else if (tdep
->mips64_transfers_32bit_regs_p
)
1078 /* The target, while possibly using a 64-bit register buffer,
1079 is only transfering 32-bits of each integer register.
1080 Reflect this in the cooked/pseudo (ABI) register value. */
1081 return builtin_type (gdbarch
)->builtin_int32
;
1082 else if (mips_abi_regsize (gdbarch
) == 4)
1083 /* The ABI is restricted to 32-bit registers (the ISA could be
1085 return builtin_type (gdbarch
)->builtin_int32
;
1088 return builtin_type (gdbarch
)->builtin_int64
;
1092 /* Return the GDB type for the pseudo register REGNUM, which is the
1093 ABI-level view. This function is only called if there is a target
1094 description which includes registers, so we know precisely the
1095 types of hardware registers. */
1097 static struct type
*
1098 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1100 const int num_regs
= gdbarch_num_regs (gdbarch
);
1101 int rawnum
= regnum
% num_regs
;
1102 struct type
*rawtype
;
1104 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1106 /* Absent registers are still absent. */
1107 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1108 if (rawtype
->length () == 0)
1111 /* Present the floating point registers however the hardware did;
1112 do not try to convert between FPU layouts. */
1113 if (mips_float_register_p (gdbarch
, rawnum
))
1116 /* Floating-point control registers are always 32-bit even though for
1117 backwards compatibility reasons 64-bit targets will transfer them
1118 as 64-bit quantities even if using XML descriptions. */
1119 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1120 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1121 return builtin_type (gdbarch
)->builtin_int32
;
1123 /* Use pointer types for registers if we can. For n32 we can not,
1124 since we do not have a 64-bit pointer type. */
1125 if (mips_abi_regsize (gdbarch
)
1126 == builtin_type (gdbarch
)->builtin_data_ptr
->length())
1128 if (rawnum
== MIPS_SP_REGNUM
1129 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1130 return builtin_type (gdbarch
)->builtin_data_ptr
;
1131 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1132 return builtin_type (gdbarch
)->builtin_func_ptr
;
1135 if (mips_abi_regsize (gdbarch
) == 4 && rawtype
->length () == 8
1136 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1137 || rawnum
== mips_regnum (gdbarch
)->lo
1138 || rawnum
== mips_regnum (gdbarch
)->hi
1139 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1140 || rawnum
== mips_regnum (gdbarch
)->cause
1141 || rawnum
== mips_regnum (gdbarch
)->pc
1142 || (mips_regnum (gdbarch
)->dspacc
!= -1
1143 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1144 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1145 return builtin_type (gdbarch
)->builtin_int32
;
1147 /* The pseudo/cooked view of embedded registers is always
1148 32-bit, even if the target transfers 64-bit values for them.
1149 New targets relying on XML descriptions should only transfer
1150 the necessary 32 bits, but older versions of GDB expected 64,
1151 so allow the target to provide 64 bits without interfering
1152 with the displayed type. */
1153 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1154 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1155 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1156 return builtin_type (gdbarch
)->builtin_int32
;
1158 /* For all other registers, pass through the hardware type. */
1162 /* Should the upper word of 64-bit addresses be zeroed? */
1163 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1166 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1168 switch (mask_address_var
)
1170 case AUTO_BOOLEAN_TRUE
:
1172 case AUTO_BOOLEAN_FALSE
:
1175 case AUTO_BOOLEAN_AUTO
:
1176 return tdep
->default_mask_address_p
;
1178 internal_error (_("mips_mask_address_p: bad switch"));
1184 show_mask_address (struct ui_file
*file
, int from_tty
,
1185 struct cmd_list_element
*c
, const char *value
)
1187 const char *additional_text
= "";
1188 if (mask_address_var
== AUTO_BOOLEAN_AUTO
)
1190 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
1192 additional_text
= _(" (current architecture is not MIPS)");
1195 mips_gdbarch_tdep
*tdep
1196 = gdbarch_tdep
<mips_gdbarch_tdep
> (current_inferior ()->arch ());
1198 if (mips_mask_address_p (tdep
))
1199 additional_text
= _(" (currently \"on\")");
1201 additional_text
= _(" (currently \"off\")");
1205 gdb_printf (file
, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"),
1206 value
, additional_text
);
1209 /* Tell if the program counter value in MEMADDR is in a standard ISA
1213 mips_pc_is_mips (CORE_ADDR memaddr
)
1215 struct bound_minimal_symbol sym
;
1217 /* Flags indicating that this is a MIPS16 or microMIPS function is
1218 stored by elfread.c in the high bit of the info field. Use this
1219 to decide if the function is standard MIPS. Otherwise if bit 0
1220 of the address is clear, then this is a standard MIPS function. */
1221 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1223 return msymbol_is_mips (sym
.minsym
);
1225 return is_mips_addr (memaddr
);
1228 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1231 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1233 struct bound_minimal_symbol sym
;
1235 /* A flag indicating that this is a MIPS16 function is stored by
1236 elfread.c in the high bit of the info field. Use this to decide
1237 if the function is MIPS16. Otherwise if bit 0 of the address is
1238 set, then ELF file flags will tell if this is a MIPS16 function. */
1239 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1241 return msymbol_is_mips16 (sym
.minsym
);
1243 return is_mips16_addr (gdbarch
, memaddr
);
1246 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1249 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1251 struct bound_minimal_symbol sym
;
1253 /* A flag indicating that this is a microMIPS function is stored by
1254 elfread.c in the high bit of the info field. Use this to decide
1255 if the function is microMIPS. Otherwise if bit 0 of the address
1256 is set, then ELF file flags will tell if this is a microMIPS
1258 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1260 return msymbol_is_micromips (sym
.minsym
);
1262 return is_micromips_addr (gdbarch
, memaddr
);
1265 /* Tell the ISA type of the function the program counter value in MEMADDR
1268 static enum mips_isa
1269 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1271 struct bound_minimal_symbol sym
;
1273 /* A flag indicating that this is a MIPS16 or a microMIPS function
1274 is stored by elfread.c in the high bit of the info field. Use
1275 this to decide if the function is MIPS16 or microMIPS or normal
1276 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1277 flags will tell if this is a MIPS16 or a microMIPS function. */
1278 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1281 if (msymbol_is_micromips (sym
.minsym
))
1282 return ISA_MICROMIPS
;
1283 else if (msymbol_is_mips16 (sym
.minsym
))
1290 if (is_mips_addr (memaddr
))
1292 else if (is_micromips_addr (gdbarch
, memaddr
))
1293 return ISA_MICROMIPS
;
1299 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1300 The need for comes from the ISA bit having been cleared, making
1301 addresses in FDE, range records, etc. referring to compressed code
1302 different to those in line information, the symbol table and finally
1303 the PC register. That in turn confuses many operations. */
1306 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1308 pc
= unmake_compact_addr (pc
);
1309 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1312 /* Recalculate the line record requested so that the resulting PC has
1313 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1314 this adjustment comes from some records associated with compressed
1315 code having the ISA bit cleared, most notably at function prologue
1316 ends. The ISA bit is in this context retrieved from the minimal
1317 symbol covering the address requested, which in turn has been
1318 constructed from the binary's symbol table rather than DWARF-2
1319 information. The correct setting of the ISA bit is required for
1320 breakpoint addresses to correctly match against the stop PC.
1322 As line entries can specify relative address adjustments we need to
1323 keep track of the absolute value of the last line address recorded
1324 in line information, so that we can calculate the actual address to
1325 apply the ISA bit adjustment to. We use PC for this tracking and
1326 keep the original address there.
1328 As such relative address adjustments can be odd within compressed
1329 code we need to keep track of the last line address with the ISA
1330 bit adjustment applied too, as the original address may or may not
1331 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1332 the adjusted address there.
1334 For relative address adjustments we then use these variables to
1335 calculate the address intended by line information, which will be
1336 PC-relative, and return an updated adjustment carrying ISA bit
1337 information, which will be ADJ_PC-relative. For absolute address
1338 adjustments we just return the same address that we store in ADJ_PC
1341 As the first line entry can be relative to an implied address value
1342 of 0 we need to have the initial address set up that we store in PC
1343 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1344 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1347 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1349 static CORE_ADDR adj_pc
;
1350 static CORE_ADDR pc
;
1353 pc
= rel
? pc
+ addr
: addr
;
1354 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1355 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1360 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1362 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1363 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1364 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1365 static const char mips_str_call_stub
[] = "__call_stub_";
1366 static const char mips_str_fn_stub
[] = "__fn_stub_";
1368 /* This is used as a PIC thunk prefix. */
1370 static const char mips_str_pic
[] = ".pic.";
1372 /* Return non-zero if the PC is inside a call thunk (aka stub or
1373 trampoline) that should be treated as a temporary frame. */
1376 mips_in_frame_stub (CORE_ADDR pc
)
1378 CORE_ADDR start_addr
;
1381 /* Find the starting address of the function containing the PC. */
1382 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1385 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1386 if (startswith (name
, mips_str_mips16_call_stub
))
1388 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1389 if (startswith (name
, mips_str_call_stub
))
1391 /* If the PC is in __fn_stub_*, this is a call stub. */
1392 if (startswith (name
, mips_str_fn_stub
))
1395 return 0; /* Not a stub. */
1398 /* MIPS believes that the PC has a sign extended value. Perhaps the
1399 all registers should be sign extended for simplicity? */
1402 mips_read_pc (readable_regcache
*regcache
)
1404 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1407 regcache
->cooked_read (regnum
, &pc
);
1412 mips_unwind_pc (struct gdbarch
*gdbarch
, frame_info_ptr next_frame
)
1416 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1417 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1418 intermediate frames. In this case we can get the caller's address
1419 from $ra, or if $ra contains an address within a thunk as well, then
1420 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1421 and thus the caller's address is in $s2. */
1422 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1424 pc
= frame_unwind_register_signed
1425 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1426 if (mips_in_frame_stub (pc
))
1427 pc
= frame_unwind_register_signed
1428 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1434 mips_unwind_sp (struct gdbarch
*gdbarch
, frame_info_ptr next_frame
)
1436 return frame_unwind_register_signed
1437 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1440 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1441 dummy frame. The frame ID's base needs to match the TOS value
1442 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1445 static struct frame_id
1446 mips_dummy_id (struct gdbarch
*gdbarch
, frame_info_ptr this_frame
)
1448 return frame_id_build
1449 (get_frame_register_signed (this_frame
,
1450 gdbarch_num_regs (gdbarch
)
1452 get_frame_pc (this_frame
));
1455 /* Implement the "write_pc" gdbarch method. */
1458 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1460 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1462 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1465 /* Fetch and return instruction from the specified location. Handle
1466 MIPS16/microMIPS as appropriate. */
1469 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1470 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1472 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1473 gdb_byte buf
[MIPS_INSN32_SIZE
];
1481 instlen
= MIPS_INSN16_SIZE
;
1482 addr
= unmake_compact_addr (addr
);
1485 instlen
= MIPS_INSN32_SIZE
;
1488 internal_error (_("invalid ISA"));
1491 err
= target_read_memory (addr
, buf
, instlen
);
1497 memory_error (TARGET_XFER_E_IO
, addr
);
1500 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1503 /* These are the fields of 32 bit mips instructions. */
1504 #define mips32_op(x) (x >> 26)
1505 #define itype_op(x) (x >> 26)
1506 #define itype_rs(x) ((x >> 21) & 0x1f)
1507 #define itype_rt(x) ((x >> 16) & 0x1f)
1508 #define itype_immediate(x) (x & 0xffff)
1510 #define jtype_op(x) (x >> 26)
1511 #define jtype_target(x) (x & 0x03ffffff)
1513 #define rtype_op(x) (x >> 26)
1514 #define rtype_rs(x) ((x >> 21) & 0x1f)
1515 #define rtype_rt(x) ((x >> 16) & 0x1f)
1516 #define rtype_rd(x) ((x >> 11) & 0x1f)
1517 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1518 #define rtype_funct(x) (x & 0x3f)
1520 /* MicroMIPS instruction fields. */
1521 #define micromips_op(x) ((x) >> 10)
1523 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1524 bit and the size respectively of the field extracted. */
1525 #define b0s4_imm(x) ((x) & 0xf)
1526 #define b0s5_imm(x) ((x) & 0x1f)
1527 #define b0s5_reg(x) ((x) & 0x1f)
1528 #define b0s7_imm(x) ((x) & 0x7f)
1529 #define b0s10_imm(x) ((x) & 0x3ff)
1530 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1531 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1532 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1533 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1534 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1535 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1536 #define b6s4_op(x) (((x) >> 6) & 0xf)
1537 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1539 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1540 respectively of the field extracted. */
1541 #define b0s6_op(x) ((x) & 0x3f)
1542 #define b0s11_op(x) ((x) & 0x7ff)
1543 #define b0s12_imm(x) ((x) & 0xfff)
1544 #define b0s16_imm(x) ((x) & 0xffff)
1545 #define b0s26_imm(x) ((x) & 0x3ffffff)
1546 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1547 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1548 #define b12s4_op(x) (((x) >> 12) & 0xf)
1550 /* Return the size in bytes of the instruction INSN encoded in the ISA
1554 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1559 if ((micromips_op (insn
) & 0x4) == 0x4
1560 || (micromips_op (insn
) & 0x7) == 0x0)
1561 return 2 * MIPS_INSN16_SIZE
;
1563 return MIPS_INSN16_SIZE
;
1565 if ((insn
& 0xf800) == 0xf000)
1566 return 2 * MIPS_INSN16_SIZE
;
1568 return MIPS_INSN16_SIZE
;
1570 return MIPS_INSN32_SIZE
;
1572 internal_error (_("invalid ISA"));
1576 mips32_relative_offset (ULONGEST inst
)
1578 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1581 /* Determine the address of the next instruction executed after the INST
1582 floating condition branch instruction at PC. COUNT specifies the
1583 number of the floating condition bits tested by the branch. */
1586 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1587 ULONGEST inst
, CORE_ADDR pc
, int count
)
1589 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1590 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1591 int tf
= itype_rt (inst
) & 1;
1592 int mask
= (1 << count
) - 1;
1597 /* No way to handle; it'll most likely trap anyway. */
1600 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1601 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1603 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1604 pc
+= mips32_relative_offset (inst
);
1611 /* Return nonzero if the gdbarch is an Octeon series. */
1614 is_octeon (struct gdbarch
*gdbarch
)
1616 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1618 return (info
->mach
== bfd_mach_mips_octeon
1619 || info
->mach
== bfd_mach_mips_octeonp
1620 || info
->mach
== bfd_mach_mips_octeon2
);
1623 /* Return true if the OP represents the Octeon's BBIT instruction. */
1626 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1628 if (!is_octeon (gdbarch
))
1630 /* BBIT0 is encoded as LWC2: 110 010. */
1631 /* BBIT032 is encoded as LDC2: 110 110. */
1632 /* BBIT1 is encoded as SWC2: 111 010. */
1633 /* BBIT132 is encoded as SDC2: 111 110. */
1634 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1640 /* Determine where to set a single step breakpoint while considering
1641 branch prediction. */
1644 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1646 struct gdbarch
*gdbarch
= regcache
->arch ();
1649 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1650 op
= itype_op (inst
);
1651 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1655 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1666 goto greater_branch
;
1671 else if (op
== 17 && itype_rs (inst
) == 8)
1672 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1673 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1674 else if (op
== 17 && itype_rs (inst
) == 9
1675 && (itype_rt (inst
) & 2) == 0)
1676 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1677 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1678 else if (op
== 17 && itype_rs (inst
) == 10
1679 && (itype_rt (inst
) & 2) == 0)
1680 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1681 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1684 /* The new PC will be alternate mode. */
1688 reg
= jtype_target (inst
) << 2;
1689 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1690 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1692 else if (is_octeon_bbit_op (op
, gdbarch
))
1696 branch_if
= op
== 58 || op
== 62;
1697 bit
= itype_rt (inst
);
1699 /* Take into account the *32 instructions. */
1700 if (op
== 54 || op
== 62)
1703 if (((regcache_raw_get_signed (regcache
,
1704 itype_rs (inst
)) >> bit
) & 1)
1706 pc
+= mips32_relative_offset (inst
) + 4;
1708 pc
+= 8; /* After the delay slot. */
1712 pc
+= 4; /* Not a branch, next instruction is easy. */
1715 { /* This gets way messy. */
1717 /* Further subdivide into SPECIAL, REGIMM and other. */
1718 switch (op
& 0x07) /* Extract bits 28,27,26. */
1720 case 0: /* SPECIAL */
1721 op
= rtype_funct (inst
);
1726 /* Set PC to that address. */
1727 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1729 case 12: /* SYSCALL */
1731 mips_gdbarch_tdep
*tdep
1732 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1734 if (tdep
->syscall_next_pc
!= NULL
)
1735 pc
= tdep
->syscall_next_pc (get_current_frame ());
1744 break; /* end SPECIAL */
1745 case 1: /* REGIMM */
1747 op
= itype_rt (inst
); /* branch condition */
1752 case 16: /* BLTZAL */
1753 case 18: /* BLTZALL */
1755 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1756 pc
+= mips32_relative_offset (inst
) + 4;
1758 pc
+= 8; /* after the delay slot */
1762 case 17: /* BGEZAL */
1763 case 19: /* BGEZALL */
1764 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1765 pc
+= mips32_relative_offset (inst
) + 4;
1767 pc
+= 8; /* after the delay slot */
1769 case 0x1c: /* BPOSGE32 */
1770 case 0x1e: /* BPOSGE64 */
1772 if (itype_rs (inst
) == 0)
1774 unsigned int pos
= (op
& 2) ? 64 : 32;
1775 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1778 /* No way to handle; it'll most likely trap anyway. */
1781 if ((regcache_raw_get_unsigned (regcache
,
1782 dspctl
) & 0x7f) >= pos
)
1783 pc
+= mips32_relative_offset (inst
);
1788 /* All of the other instructions in the REGIMM category */
1793 break; /* end REGIMM */
1798 reg
= jtype_target (inst
) << 2;
1799 /* Upper four bits get never changed... */
1800 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1803 case 4: /* BEQ, BEQL */
1805 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1806 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1807 pc
+= mips32_relative_offset (inst
) + 4;
1811 case 5: /* BNE, BNEL */
1813 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1814 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1815 pc
+= mips32_relative_offset (inst
) + 4;
1819 case 6: /* BLEZ, BLEZL */
1820 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1821 pc
+= mips32_relative_offset (inst
) + 4;
1827 greater_branch
: /* BGTZ, BGTZL */
1828 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1829 pc
+= mips32_relative_offset (inst
) + 4;
1836 } /* mips32_next_pc */
1838 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1842 micromips_relative_offset7 (ULONGEST insn
)
1844 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1847 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1851 micromips_relative_offset10 (ULONGEST insn
)
1853 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1856 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1860 micromips_relative_offset16 (ULONGEST insn
)
1862 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1865 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1868 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1872 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1873 return mips_insn_size (ISA_MICROMIPS
, insn
);
1876 /* Calculate the address of the next microMIPS instruction to execute
1877 after the INSN coprocessor 1 conditional branch instruction at the
1878 address PC. COUNT denotes the number of coprocessor condition bits
1879 examined by the branch. */
1882 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1883 ULONGEST insn
, CORE_ADDR pc
, int count
)
1885 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1886 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1887 int tf
= b5s5_op (insn
>> 16) & 1;
1888 int mask
= (1 << count
) - 1;
1893 /* No way to handle; it'll most likely trap anyway. */
1896 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1897 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1899 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1900 pc
+= micromips_relative_offset16 (insn
);
1902 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1907 /* Calculate the address of the next microMIPS instruction to execute
1908 after the instruction at the address PC. */
1911 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1913 struct gdbarch
*gdbarch
= regcache
->arch ();
1916 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1917 pc
+= MIPS_INSN16_SIZE
;
1918 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1920 /* 32-bit instructions. */
1921 case 2 * MIPS_INSN16_SIZE
:
1923 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1924 pc
+= MIPS_INSN16_SIZE
;
1925 switch (micromips_op (insn
>> 16))
1927 case 0x00: /* POOL32A: bits 000000 */
1928 switch (b0s6_op (insn
))
1930 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1931 switch (b6s10_ext (insn
))
1933 case 0x3c: /* JALR: 000000 0000111100 111100 */
1934 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1935 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1936 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1937 pc
= regcache_raw_get_signed (regcache
,
1938 b0s5_reg (insn
>> 16));
1940 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1942 mips_gdbarch_tdep
*tdep
1943 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1945 if (tdep
->syscall_next_pc
!= NULL
)
1946 pc
= tdep
->syscall_next_pc (get_current_frame ());
1954 case 0x10: /* POOL32I: bits 010000 */
1955 switch (b5s5_op (insn
>> 16))
1957 case 0x00: /* BLTZ: bits 010000 00000 */
1958 case 0x01: /* BLTZAL: bits 010000 00001 */
1959 case 0x11: /* BLTZALS: bits 010000 10001 */
1960 if (regcache_raw_get_signed (regcache
,
1961 b0s5_reg (insn
>> 16)) < 0)
1962 pc
+= micromips_relative_offset16 (insn
);
1964 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1967 case 0x02: /* BGEZ: bits 010000 00010 */
1968 case 0x03: /* BGEZAL: bits 010000 00011 */
1969 case 0x13: /* BGEZALS: bits 010000 10011 */
1970 if (regcache_raw_get_signed (regcache
,
1971 b0s5_reg (insn
>> 16)) >= 0)
1972 pc
+= micromips_relative_offset16 (insn
);
1974 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1977 case 0x04: /* BLEZ: bits 010000 00100 */
1978 if (regcache_raw_get_signed (regcache
,
1979 b0s5_reg (insn
>> 16)) <= 0)
1980 pc
+= micromips_relative_offset16 (insn
);
1982 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1985 case 0x05: /* BNEZC: bits 010000 00101 */
1986 if (regcache_raw_get_signed (regcache
,
1987 b0s5_reg (insn
>> 16)) != 0)
1988 pc
+= micromips_relative_offset16 (insn
);
1991 case 0x06: /* BGTZ: bits 010000 00110 */
1992 if (regcache_raw_get_signed (regcache
,
1993 b0s5_reg (insn
>> 16)) > 0)
1994 pc
+= micromips_relative_offset16 (insn
);
1996 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1999 case 0x07: /* BEQZC: bits 010000 00111 */
2000 if (regcache_raw_get_signed (regcache
,
2001 b0s5_reg (insn
>> 16)) == 0)
2002 pc
+= micromips_relative_offset16 (insn
);
2005 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2006 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2007 if (((insn
>> 16) & 0x3) == 0x0)
2008 /* BC2F, BC2T: don't know how to handle these. */
2012 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2013 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2015 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2016 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2019 /* No way to handle; it'll most likely trap anyway. */
2022 if ((regcache_raw_get_unsigned (regcache
,
2023 dspctl
) & 0x7f) >= pos
)
2024 pc
+= micromips_relative_offset16 (insn
);
2026 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2030 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2031 /* BC1ANY2F: bits 010000 11100 xxx01 */
2032 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2033 /* BC1ANY2T: bits 010000 11101 xxx01 */
2034 if (((insn
>> 16) & 0x2) == 0x0)
2035 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2036 ((insn
>> 16) & 0x1) + 1);
2039 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2040 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2041 if (((insn
>> 16) & 0x3) == 0x1)
2042 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2047 case 0x1d: /* JALS: bits 011101 */
2048 case 0x35: /* J: bits 110101 */
2049 case 0x3d: /* JAL: bits 111101 */
2050 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2053 case 0x25: /* BEQ: bits 100101 */
2054 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2055 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2056 pc
+= micromips_relative_offset16 (insn
);
2058 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2061 case 0x2d: /* BNE: bits 101101 */
2062 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2063 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2064 pc
+= micromips_relative_offset16 (insn
);
2066 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2069 case 0x3c: /* JALX: bits 111100 */
2070 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2075 /* 16-bit instructions. */
2076 case MIPS_INSN16_SIZE
:
2077 switch (micromips_op (insn
))
2079 case 0x11: /* POOL16C: bits 010001 */
2080 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2081 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2082 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2083 else if (b5s5_op (insn
) == 0x18)
2084 /* JRADDIUSP: bits 010001 11000 */
2085 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2088 case 0x23: /* BEQZ16: bits 100011 */
2090 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2092 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2093 pc
+= micromips_relative_offset7 (insn
);
2095 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2099 case 0x2b: /* BNEZ16: bits 101011 */
2101 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2103 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2104 pc
+= micromips_relative_offset7 (insn
);
2106 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2110 case 0x33: /* B16: bits 110011 */
2111 pc
+= micromips_relative_offset10 (insn
);
2120 /* Decoding the next place to set a breakpoint is irregular for the
2121 mips 16 variant, but fortunately, there fewer instructions. We have
2122 to cope ith extensions for 16 bit instructions and a pair of actual
2123 32 bit instructions. We dont want to set a single step instruction
2124 on the extend instruction either. */
2126 /* Lots of mips16 instruction formats */
2127 /* Predicting jumps requires itype,ritype,i8type
2128 and their extensions extItype,extritype,extI8type. */
2129 enum mips16_inst_fmts
2131 itype
, /* 0 immediate 5,10 */
2132 ritype
, /* 1 5,3,8 */
2133 rrtype
, /* 2 5,3,3,5 */
2134 rritype
, /* 3 5,3,3,5 */
2135 rrrtype
, /* 4 5,3,3,3,2 */
2136 rriatype
, /* 5 5,3,3,1,4 */
2137 shifttype
, /* 6 5,3,3,3,2 */
2138 i8type
, /* 7 5,3,8 */
2139 i8movtype
, /* 8 5,3,3,5 */
2140 i8mov32rtype
, /* 9 5,3,5,3 */
2141 i64type
, /* 10 5,3,8 */
2142 ri64type
, /* 11 5,3,3,5 */
2143 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2144 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2145 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2146 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2147 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2148 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2149 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2150 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2151 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2152 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2154 /* I am heaping all the fields of the formats into one structure and
2155 then, only the fields which are involved in instruction extension. */
2159 unsigned int regx
; /* Function in i8 type. */
2164 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2165 for the bits which make up the immediate extension. */
2168 extended_offset (unsigned int extension
)
2172 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2174 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2176 value
|= extension
& 0x1f; /* Extract 4:0. */
2181 /* Only call this function if you know that this is an extendable
2182 instruction. It won't malfunction, but why make excess remote memory
2183 references? If the immediate operands get sign extended or something,
2184 do it after the extension is performed. */
2185 /* FIXME: Every one of these cases needs to worry about sign extension
2186 when the offset is to be used in relative addressing. */
2189 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2194 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2195 target_read_memory (pc
, buf
, 2);
2196 return extract_unsigned_integer (buf
, 2, byte_order
);
2200 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2201 unsigned int extension
,
2203 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2208 switch (insn_format
)
2215 value
= extended_offset ((extension
<< 16) | inst
);
2216 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2220 value
= inst
& 0x7ff;
2221 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2230 { /* A register identifier and an offset. */
2231 /* Most of the fields are the same as I type but the
2232 immediate value is of a different length. */
2236 value
= extended_offset ((extension
<< 16) | inst
);
2237 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2241 value
= inst
& 0xff; /* 8 bits */
2242 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2245 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2251 unsigned long value
;
2252 unsigned int nexthalf
;
2253 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2254 value
= value
<< 16;
2255 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2256 /* Low bit still set. */
2264 internal_error (_("bad switch"));
2266 upk
->offset
= offset
;
2272 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2273 and having a signed 16-bit OFFSET. */
2276 add_offset_16 (CORE_ADDR pc
, int offset
)
2278 return pc
+ (offset
<< 1) + 2;
2282 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2283 unsigned int extension
, unsigned int insn
)
2285 struct gdbarch
*gdbarch
= regcache
->arch ();
2286 int op
= (insn
>> 11);
2289 case 2: /* Branch */
2291 struct upk_mips16 upk
;
2292 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2293 pc
= add_offset_16 (pc
, upk
.offset
);
2296 case 3: /* JAL , JALX - Watch out, these are 32 bit
2299 struct upk_mips16 upk
;
2300 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2301 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2302 if ((insn
>> 10) & 0x01) /* Exchange mode */
2303 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2310 struct upk_mips16 upk
;
2312 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2313 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2315 pc
= add_offset_16 (pc
, upk
.offset
);
2322 struct upk_mips16 upk
;
2324 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2325 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2327 pc
= add_offset_16 (pc
, upk
.offset
);
2332 case 12: /* I8 Formats btez btnez */
2334 struct upk_mips16 upk
;
2336 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2337 /* upk.regx contains the opcode */
2338 /* Test register is 24 */
2339 reg
= regcache_raw_get_signed (regcache
, 24);
2340 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2341 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2342 pc
= add_offset_16 (pc
, upk
.offset
);
2347 case 29: /* RR Formats JR, JALR, JALR-RA */
2349 struct upk_mips16 upk
;
2350 /* upk.fmt = rrtype; */
2355 upk
.regx
= (insn
>> 8) & 0x07;
2356 upk
.regy
= (insn
>> 5) & 0x07;
2357 if ((upk
.regy
& 1) == 0)
2358 reg
= mips_reg3_to_reg
[upk
.regx
];
2360 reg
= 31; /* Function return instruction. */
2361 pc
= regcache_raw_get_signed (regcache
, reg
);
2368 /* This is an instruction extension. Fetch the real instruction
2369 (which follows the extension) and decode things based on
2373 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2374 fetch_mips_16 (gdbarch
, pc
));
2387 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2389 struct gdbarch
*gdbarch
= regcache
->arch ();
2390 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2391 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2394 /* The mips_next_pc function supports single_step when the remote
2395 target monitor or stub is not developed enough to do a single_step.
2396 It works by decoding the current instruction and predicting where a
2397 branch will go. This isn't hard because all the data is available.
2398 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2400 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2402 struct gdbarch
*gdbarch
= regcache
->arch ();
2404 if (mips_pc_is_mips16 (gdbarch
, pc
))
2405 return mips16_next_pc (regcache
, pc
);
2406 else if (mips_pc_is_micromips (gdbarch
, pc
))
2407 return micromips_next_pc (regcache
, pc
);
2409 return mips32_next_pc (regcache
, pc
);
2412 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2416 mips16_instruction_is_compact_branch (unsigned short insn
)
2418 switch (insn
& 0xf800)
2421 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2423 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2424 case 0x2800: /* BNEZ */
2425 case 0x2000: /* BEQZ */
2426 case 0x1000: /* B */
2433 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2437 micromips_instruction_is_compact_branch (unsigned short insn
)
2439 switch (micromips_op (insn
))
2441 case 0x11: /* POOL16C: bits 010001 */
2442 return (b5s5_op (insn
) == 0x18
2443 /* JRADDIUSP: bits 010001 11000 */
2444 || b5s5_op (insn
) == 0xd);
2445 /* JRC: bits 010011 01101 */
2446 case 0x10: /* POOL32I: bits 010000 */
2447 return (b5s5_op (insn
) & 0x1d) == 0x5;
2448 /* BEQZC/BNEZC: bits 010000 001x1 */
2454 struct mips_frame_cache
2457 trad_frame_saved_reg
*saved_regs
;
2460 /* Set a register's saved stack address in temp_saved_regs. If an
2461 address has already been set for this register, do nothing; this
2462 way we will only recognize the first save of a given register in a
2465 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2466 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2467 Strictly speaking, only the second range is used as it is only second
2468 range (the ABI instead of ISA registers) that comes into play when finding
2469 saved registers in a frame. */
2472 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2473 int regnum
, CORE_ADDR offset
)
2475 if (this_cache
!= NULL
2476 && this_cache
->saved_regs
[regnum
].is_realreg ()
2477 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2479 this_cache
->saved_regs
[regnum
+ 0
2480 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2481 this_cache
->saved_regs
[regnum
+ 1
2482 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2487 /* Fetch the immediate value from a MIPS16 instruction.
2488 If the previous instruction was an EXTEND, use it to extend
2489 the upper bits of the immediate value. This is a helper function
2490 for mips16_scan_prologue. */
2493 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2494 unsigned short inst
, /* current instruction */
2495 int nbits
, /* number of bits in imm field */
2496 int scale
, /* scale factor to be applied to imm */
2497 int is_signed
) /* is the imm field signed? */
2501 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2503 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2504 if (offset
& 0x8000) /* check for negative extend */
2505 offset
= 0 - (0x10000 - (offset
& 0xffff));
2506 return offset
| (inst
& 0x1f);
2510 int max_imm
= 1 << nbits
;
2511 int mask
= max_imm
- 1;
2512 int sign_bit
= max_imm
>> 1;
2514 offset
= inst
& mask
;
2515 if (is_signed
&& (offset
& sign_bit
))
2516 offset
= 0 - (max_imm
- offset
);
2517 return offset
* scale
;
2522 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2523 the associated FRAME_CACHE if not null.
2524 Return the address of the first instruction past the prologue. */
2527 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2528 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2529 frame_info_ptr this_frame
,
2530 struct mips_frame_cache
*this_cache
)
2532 int prev_non_prologue_insn
= 0;
2533 int this_non_prologue_insn
;
2534 int non_prologue_insns
= 0;
2537 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2539 long frame_offset
= 0; /* Size of stack frame. */
2540 long frame_adjust
= 0; /* Offset of FP from SP. */
2541 int frame_reg
= MIPS_SP_REGNUM
;
2542 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2543 unsigned inst
= 0; /* current instruction */
2544 unsigned entry_inst
= 0; /* the entry instruction */
2545 unsigned save_inst
= 0; /* the save instruction */
2546 int prev_delay_slot
= 0;
2550 int extend_bytes
= 0;
2551 int prev_extend_bytes
= 0;
2552 CORE_ADDR end_prologue_addr
;
2554 /* Can be called when there's no process, and hence when there's no
2556 if (this_frame
!= NULL
)
2557 sp
= get_frame_register_signed (this_frame
,
2558 gdbarch_num_regs (gdbarch
)
2563 if (limit_pc
> start_pc
+ 200)
2564 limit_pc
= start_pc
+ 200;
2567 /* Permit at most one non-prologue non-control-transfer instruction
2568 in the middle which may have been reordered by the compiler for
2570 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2572 this_non_prologue_insn
= 0;
2575 /* Save the previous instruction. If it's an EXTEND, we'll extract
2576 the immediate offset extension from it in mips16_get_imm. */
2579 /* Fetch and decode the instruction. */
2580 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2583 /* Normally we ignore extend instructions. However, if it is
2584 not followed by a valid prologue instruction, then this
2585 instruction is not part of the prologue either. We must
2586 remember in this case to adjust the end_prologue_addr back
2588 if ((inst
& 0xf800) == 0xf000) /* extend */
2590 extend_bytes
= MIPS_INSN16_SIZE
;
2594 prev_extend_bytes
= extend_bytes
;
2597 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2598 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2600 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2601 if (offset
< 0) /* Negative stack adjustment? */
2602 frame_offset
-= offset
;
2604 /* Exit loop if a positive stack adjustment is found, which
2605 usually means that the stack cleanup code in the function
2606 epilogue is reached. */
2609 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2611 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2612 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2613 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2615 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2617 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2618 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2619 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2621 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2623 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2624 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2626 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2628 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2629 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2631 else if (inst
== 0x673d) /* move $s1, $sp */
2636 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2638 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2639 frame_addr
= sp
+ offset
;
2641 frame_adjust
= offset
;
2643 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2645 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2646 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2647 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2649 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2651 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2652 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2653 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2655 else if ((inst
& 0xf81f) == 0xe809
2656 && (inst
& 0x700) != 0x700) /* entry */
2657 entry_inst
= inst
; /* Save for later processing. */
2658 else if ((inst
& 0xff80) == 0x6480) /* save */
2660 save_inst
= inst
; /* Save for later processing. */
2661 if (prev_extend_bytes
) /* extend */
2662 save_inst
|= prev_inst
<< 16;
2664 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2666 /* This instruction is part of the prologue, but we don't
2667 need to do anything special to handle it. */
2669 else if (mips16_instruction_has_delay_slot (inst
, 0))
2670 /* JAL/JALR/JALX/JR */
2672 /* The instruction in the delay slot can be a part
2673 of the prologue, so move forward once more. */
2675 if (mips16_instruction_has_delay_slot (inst
, 1))
2678 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2679 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2684 this_non_prologue_insn
= 1;
2687 non_prologue_insns
+= this_non_prologue_insn
;
2689 /* A jump or branch, or enough non-prologue insns seen? If so,
2690 then we must have reached the end of the prologue by now. */
2691 if (prev_delay_slot
|| non_prologue_insns
> 1
2692 || mips16_instruction_is_compact_branch (inst
))
2695 prev_non_prologue_insn
= this_non_prologue_insn
;
2696 prev_delay_slot
= in_delay_slot
;
2697 prev_pc
= cur_pc
- prev_extend_bytes
;
2700 /* The entry instruction is typically the first instruction in a function,
2701 and it stores registers at offsets relative to the value of the old SP
2702 (before the prologue). But the value of the sp parameter to this
2703 function is the new SP (after the prologue has been executed). So we
2704 can't calculate those offsets until we've seen the entire prologue,
2705 and can calculate what the old SP must have been. */
2706 if (entry_inst
!= 0)
2708 int areg_count
= (entry_inst
>> 8) & 7;
2709 int sreg_count
= (entry_inst
>> 6) & 3;
2711 /* The entry instruction always subtracts 32 from the SP. */
2714 /* Now we can calculate what the SP must have been at the
2715 start of the function prologue. */
2718 /* Check if a0-a3 were saved in the caller's argument save area. */
2719 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2721 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2722 offset
+= mips_abi_regsize (gdbarch
);
2725 /* Check if the ra register was pushed on the stack. */
2727 if (entry_inst
& 0x20)
2729 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2730 offset
-= mips_abi_regsize (gdbarch
);
2733 /* Check if the s0 and s1 registers were pushed on the stack. */
2734 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2736 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2737 offset
-= mips_abi_regsize (gdbarch
);
2741 /* The SAVE instruction is similar to ENTRY, except that defined by the
2742 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2743 size of the frame is specified as an immediate field of instruction
2744 and an extended variation exists which lets additional registers and
2745 frame space to be specified. The instruction always treats registers
2746 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2747 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2749 static int args_table
[16] = {
2750 0, 0, 0, 0, 1, 1, 1, 1,
2751 2, 2, 2, 0, 3, 3, 4, -1,
2753 static int astatic_table
[16] = {
2754 0, 1, 2, 3, 0, 1, 2, 3,
2755 0, 1, 2, 4, 0, 1, 0, -1,
2757 int aregs
= (save_inst
>> 16) & 0xf;
2758 int xsregs
= (save_inst
>> 24) & 0x7;
2759 int args
= args_table
[aregs
];
2760 int astatic
= astatic_table
[aregs
];
2765 warning (_("Invalid number of argument registers encoded in SAVE."));
2770 warning (_("Invalid number of static registers encoded in SAVE."));
2774 /* For standard SAVE the frame size of 0 means 128. */
2775 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2776 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2779 frame_offset
+= frame_size
;
2781 /* Now we can calculate what the SP must have been at the
2782 start of the function prologue. */
2785 /* Check if A0-A3 were saved in the caller's argument save area. */
2786 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2788 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2789 offset
+= mips_abi_regsize (gdbarch
);
2794 /* Check if the RA register was pushed on the stack. */
2795 if (save_inst
& 0x40)
2797 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2798 offset
-= mips_abi_regsize (gdbarch
);
2801 /* Check if the S8 register was pushed on the stack. */
2804 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2805 offset
-= mips_abi_regsize (gdbarch
);
2808 /* Check if S2-S7 were pushed on the stack. */
2809 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2811 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2812 offset
-= mips_abi_regsize (gdbarch
);
2815 /* Check if the S1 register was pushed on the stack. */
2816 if (save_inst
& 0x10)
2818 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2819 offset
-= mips_abi_regsize (gdbarch
);
2821 /* Check if the S0 register was pushed on the stack. */
2822 if (save_inst
& 0x20)
2824 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2825 offset
-= mips_abi_regsize (gdbarch
);
2828 /* Check if A0-A3 were pushed on the stack. */
2829 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2831 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2832 offset
-= mips_abi_regsize (gdbarch
);
2836 if (this_cache
!= NULL
)
2839 (get_frame_register_signed (this_frame
,
2840 gdbarch_num_regs (gdbarch
) + frame_reg
)
2841 + frame_offset
- frame_adjust
);
2842 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2843 be able to get rid of the assignment below, evetually. But it's
2844 still needed for now. */
2845 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2846 + mips_regnum (gdbarch
)->pc
]
2847 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2850 /* Set end_prologue_addr to the address of the instruction immediately
2851 after the last one we scanned. Unless the last one looked like a
2852 non-prologue instruction (and we looked ahead), in which case use
2853 its address instead. */
2854 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2855 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2857 return end_prologue_addr
;
2860 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2861 Procedures that use the 32-bit instruction set are handled by the
2862 mips_insn32 unwinder. */
2864 static struct mips_frame_cache
*
2865 mips_insn16_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2867 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2868 struct mips_frame_cache
*cache
;
2870 if ((*this_cache
) != NULL
)
2871 return (struct mips_frame_cache
*) (*this_cache
);
2872 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2873 (*this_cache
) = cache
;
2874 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2876 /* Analyze the function prologue. */
2878 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2879 CORE_ADDR start_addr
;
2881 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2882 if (start_addr
== 0)
2883 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2884 /* We can't analyze the prologue if we couldn't find the begining
2886 if (start_addr
== 0)
2889 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2890 (struct mips_frame_cache
*) *this_cache
);
2893 /* gdbarch_sp_regnum contains the value and not the address. */
2894 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2895 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2897 return (struct mips_frame_cache
*) (*this_cache
);
2901 mips_insn16_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
2902 struct frame_id
*this_id
)
2904 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2906 /* This marks the outermost frame. */
2907 if (info
->base
== 0)
2909 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2912 static struct value
*
2913 mips_insn16_frame_prev_register (frame_info_ptr this_frame
,
2914 void **this_cache
, int regnum
)
2916 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2918 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2922 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2923 frame_info_ptr this_frame
, void **this_cache
)
2925 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2926 CORE_ADDR pc
= get_frame_pc (this_frame
);
2927 if (mips_pc_is_mips16 (gdbarch
, pc
))
2932 static const struct frame_unwind mips_insn16_frame_unwind
=
2934 "mips insn16 prologue",
2936 default_frame_unwind_stop_reason
,
2937 mips_insn16_frame_this_id
,
2938 mips_insn16_frame_prev_register
,
2940 mips_insn16_frame_sniffer
2944 mips_insn16_frame_base_address (frame_info_ptr this_frame
,
2947 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2952 static const struct frame_base mips_insn16_frame_base
=
2954 &mips_insn16_frame_unwind
,
2955 mips_insn16_frame_base_address
,
2956 mips_insn16_frame_base_address
,
2957 mips_insn16_frame_base_address
2960 static const struct frame_base
*
2961 mips_insn16_frame_base_sniffer (frame_info_ptr this_frame
)
2963 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2964 CORE_ADDR pc
= get_frame_pc (this_frame
);
2965 if (mips_pc_is_mips16 (gdbarch
, pc
))
2966 return &mips_insn16_frame_base
;
2971 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2972 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2973 interpreted directly, and then multiplied by 4. */
2976 micromips_decode_imm9 (int imm
)
2978 imm
= (imm
^ 0x100) - 0x100;
2979 if (imm
> -3 && imm
< 2)
2984 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2985 the address of the first instruction past the prologue. */
2988 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2989 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2990 frame_info_ptr this_frame
,
2991 struct mips_frame_cache
*this_cache
)
2993 CORE_ADDR end_prologue_addr
;
2994 int prev_non_prologue_insn
= 0;
2995 int frame_reg
= MIPS_SP_REGNUM
;
2996 int this_non_prologue_insn
;
2997 int non_prologue_insns
= 0;
2998 long frame_offset
= 0; /* Size of stack frame. */
2999 long frame_adjust
= 0; /* Offset of FP from SP. */
3000 int prev_delay_slot
= 0;
3004 ULONGEST insn
; /* current instruction */
3008 long v1_off
= 0; /* The assumption is LUI will replace it. */
3019 /* Can be called when there's no process, and hence when there's no
3021 if (this_frame
!= NULL
)
3022 sp
= get_frame_register_signed (this_frame
,
3023 gdbarch_num_regs (gdbarch
)
3028 if (limit_pc
> start_pc
+ 200)
3029 limit_pc
= start_pc
+ 200;
3032 /* Permit at most one non-prologue non-control-transfer instruction
3033 in the middle which may have been reordered by the compiler for
3035 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3037 this_non_prologue_insn
= 0;
3041 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3042 loc
+= MIPS_INSN16_SIZE
;
3043 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3045 /* 32-bit instructions. */
3046 case 2 * MIPS_INSN16_SIZE
:
3048 insn
|= mips_fetch_instruction (gdbarch
,
3049 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3050 loc
+= MIPS_INSN16_SIZE
;
3051 switch (micromips_op (insn
>> 16))
3053 /* Record $sp/$fp adjustment. */
3054 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3055 case 0x0: /* POOL32A: bits 000000 */
3056 case 0x16: /* POOL32S: bits 010110 */
3057 op
= b0s11_op (insn
);
3058 sreg
= b0s5_reg (insn
>> 16);
3059 treg
= b5s5_reg (insn
>> 16);
3060 dreg
= b11s5_reg (insn
);
3062 /* SUBU: bits 000000 00111010000 */
3063 /* DSUBU: bits 010110 00111010000 */
3064 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3066 /* (D)SUBU $sp, $v1 */
3068 else if (op
!= 0x150
3069 /* ADDU: bits 000000 00101010000 */
3070 /* DADDU: bits 010110 00101010000 */
3071 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3072 this_non_prologue_insn
= 1;
3075 case 0x8: /* POOL32B: bits 001000 */
3076 op
= b12s4_op (insn
);
3077 breg
= b0s5_reg (insn
>> 16);
3078 reglist
= sreg
= b5s5_reg (insn
>> 16);
3079 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3080 if ((op
== 0x9 || op
== 0xc)
3081 /* SWP: bits 001000 1001 */
3082 /* SDP: bits 001000 1100 */
3083 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3084 /* S[DW]P reg,offset($sp) */
3086 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3087 set_reg_offset (gdbarch
, this_cache
,
3089 set_reg_offset (gdbarch
, this_cache
,
3090 sreg
+ 1, sp
+ offset
+ s
);
3092 else if ((op
== 0xd || op
== 0xf)
3093 /* SWM: bits 001000 1101 */
3094 /* SDM: bits 001000 1111 */
3095 && breg
== MIPS_SP_REGNUM
3096 /* SWM reglist,offset($sp) */
3097 && ((reglist
>= 1 && reglist
<= 9)
3098 || (reglist
>= 16 && reglist
<= 25)))
3100 int sreglist
= std::min(reglist
& 0xf, 8);
3102 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3103 for (i
= 0; i
< sreglist
; i
++)
3104 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3105 if ((reglist
& 0xf) > 8)
3106 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3107 if ((reglist
& 0x10) == 0x10)
3108 set_reg_offset (gdbarch
, this_cache
,
3109 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3112 this_non_prologue_insn
= 1;
3115 /* Record $sp/$fp adjustment. */
3116 /* Discard (D)ADDIU $gp used for PIC code. */
3117 case 0xc: /* ADDIU: bits 001100 */
3118 case 0x17: /* DADDIU: bits 010111 */
3119 sreg
= b0s5_reg (insn
>> 16);
3120 dreg
= b5s5_reg (insn
>> 16);
3121 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3122 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3123 /* (D)ADDIU $sp, imm */
3125 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3126 /* (D)ADDIU $fp, $sp, imm */
3128 frame_adjust
= offset
;
3131 else if (sreg
!= 28 || dreg
!= 28)
3132 /* (D)ADDIU $gp, imm */
3133 this_non_prologue_insn
= 1;
3136 /* LUI $v1 is used for larger $sp adjustments. */
3137 /* Discard LUI $gp used for PIC code. */
3138 case 0x10: /* POOL32I: bits 010000 */
3139 if (b5s5_op (insn
>> 16) == 0xd
3140 /* LUI: bits 010000 001101 */
3141 && b0s5_reg (insn
>> 16) == 3)
3143 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3144 else if (b5s5_op (insn
>> 16) != 0xd
3145 /* LUI: bits 010000 001101 */
3146 || b0s5_reg (insn
>> 16) != 28)
3148 this_non_prologue_insn
= 1;
3151 /* ORI $v1 is used for larger $sp adjustments. */
3152 case 0x14: /* ORI: bits 010100 */
3153 sreg
= b0s5_reg (insn
>> 16);
3154 dreg
= b5s5_reg (insn
>> 16);
3155 if (sreg
== 3 && dreg
== 3)
3157 v1_off
|= b0s16_imm (insn
);
3159 this_non_prologue_insn
= 1;
3162 case 0x26: /* SWC1: bits 100110 */
3163 case 0x2e: /* SDC1: bits 101110 */
3164 breg
= b0s5_reg (insn
>> 16);
3165 if (breg
!= MIPS_SP_REGNUM
)
3166 /* S[DW]C1 reg,offset($sp) */
3167 this_non_prologue_insn
= 1;
3170 case 0x36: /* SD: bits 110110 */
3171 case 0x3e: /* SW: bits 111110 */
3172 breg
= b0s5_reg (insn
>> 16);
3173 sreg
= b5s5_reg (insn
>> 16);
3174 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3175 if (breg
== MIPS_SP_REGNUM
)
3176 /* S[DW] reg,offset($sp) */
3177 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3179 this_non_prologue_insn
= 1;
3183 /* The instruction in the delay slot can be a part
3184 of the prologue, so move forward once more. */
3185 if (micromips_instruction_has_delay_slot (insn
, 0))
3188 this_non_prologue_insn
= 1;
3194 /* 16-bit instructions. */
3195 case MIPS_INSN16_SIZE
:
3196 switch (micromips_op (insn
))
3198 case 0x3: /* MOVE: bits 000011 */
3199 sreg
= b0s5_reg (insn
);
3200 dreg
= b5s5_reg (insn
);
3201 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3204 else if ((sreg
& 0x1c) != 0x4)
3205 /* MOVE reg, $a0-$a3 */
3206 this_non_prologue_insn
= 1;
3209 case 0x11: /* POOL16C: bits 010001 */
3210 if (b6s4_op (insn
) == 0x5)
3211 /* SWM: bits 010001 0101 */
3213 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3214 reglist
= b4s2_regl (insn
);
3215 for (i
= 0; i
<= reglist
; i
++)
3216 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3217 set_reg_offset (gdbarch
, this_cache
,
3218 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3221 this_non_prologue_insn
= 1;
3224 case 0x13: /* POOL16D: bits 010011 */
3225 if ((insn
& 0x1) == 0x1)
3226 /* ADDIUSP: bits 010011 1 */
3227 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3228 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3229 /* ADDIUS5: bits 010011 0 */
3230 /* ADDIUS5 $sp, imm */
3231 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3233 this_non_prologue_insn
= 1;
3236 case 0x32: /* SWSP: bits 110010 */
3237 offset
= b0s5_imm (insn
) << 2;
3238 sreg
= b5s5_reg (insn
);
3239 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3243 /* The instruction in the delay slot can be a part
3244 of the prologue, so move forward once more. */
3245 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3248 this_non_prologue_insn
= 1;
3254 frame_offset
-= sp_adj
;
3256 non_prologue_insns
+= this_non_prologue_insn
;
3258 /* A jump or branch, enough non-prologue insns seen or positive
3259 stack adjustment? If so, then we must have reached the end
3260 of the prologue by now. */
3261 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3262 || micromips_instruction_is_compact_branch (insn
))
3265 prev_non_prologue_insn
= this_non_prologue_insn
;
3266 prev_delay_slot
= in_delay_slot
;
3270 if (this_cache
!= NULL
)
3273 (get_frame_register_signed (this_frame
,
3274 gdbarch_num_regs (gdbarch
) + frame_reg
)
3275 + frame_offset
- frame_adjust
);
3276 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3277 be able to get rid of the assignment below, evetually. But it's
3278 still needed for now. */
3279 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3280 + mips_regnum (gdbarch
)->pc
]
3281 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3284 /* Set end_prologue_addr to the address of the instruction immediately
3285 after the last one we scanned. Unless the last one looked like a
3286 non-prologue instruction (and we looked ahead), in which case use
3287 its address instead. */
3289 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3291 return end_prologue_addr
;
3294 /* Heuristic unwinder for procedures using microMIPS instructions.
3295 Procedures that use the 32-bit instruction set are handled by the
3296 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3298 static struct mips_frame_cache
*
3299 mips_micro_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3301 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3302 struct mips_frame_cache
*cache
;
3304 if ((*this_cache
) != NULL
)
3305 return (struct mips_frame_cache
*) (*this_cache
);
3307 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3308 (*this_cache
) = cache
;
3309 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3311 /* Analyze the function prologue. */
3313 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3314 CORE_ADDR start_addr
;
3316 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3317 if (start_addr
== 0)
3318 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3319 /* We can't analyze the prologue if we couldn't find the begining
3321 if (start_addr
== 0)
3324 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3325 (struct mips_frame_cache
*) *this_cache
);
3328 /* gdbarch_sp_regnum contains the value and not the address. */
3329 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3330 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3332 return (struct mips_frame_cache
*) (*this_cache
);
3336 mips_micro_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3337 struct frame_id
*this_id
)
3339 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3341 /* This marks the outermost frame. */
3342 if (info
->base
== 0)
3344 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3347 static struct value
*
3348 mips_micro_frame_prev_register (frame_info_ptr this_frame
,
3349 void **this_cache
, int regnum
)
3351 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3353 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3357 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3358 frame_info_ptr this_frame
, void **this_cache
)
3360 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3361 CORE_ADDR pc
= get_frame_pc (this_frame
);
3363 if (mips_pc_is_micromips (gdbarch
, pc
))
3368 static const struct frame_unwind mips_micro_frame_unwind
=
3370 "mips micro prologue",
3372 default_frame_unwind_stop_reason
,
3373 mips_micro_frame_this_id
,
3374 mips_micro_frame_prev_register
,
3376 mips_micro_frame_sniffer
3380 mips_micro_frame_base_address (frame_info_ptr this_frame
,
3383 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3388 static const struct frame_base mips_micro_frame_base
=
3390 &mips_micro_frame_unwind
,
3391 mips_micro_frame_base_address
,
3392 mips_micro_frame_base_address
,
3393 mips_micro_frame_base_address
3396 static const struct frame_base
*
3397 mips_micro_frame_base_sniffer (frame_info_ptr this_frame
)
3399 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3400 CORE_ADDR pc
= get_frame_pc (this_frame
);
3402 if (mips_pc_is_micromips (gdbarch
, pc
))
3403 return &mips_micro_frame_base
;
3408 /* Mark all the registers as unset in the saved_regs array
3409 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3412 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3414 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3418 const int num_regs
= gdbarch_num_regs (gdbarch
);
3421 /* Reset the register values to their default state. Register i's value
3422 is in register i. */
3423 for (i
= 0; i
< num_regs
; i
++)
3424 this_cache
->saved_regs
[i
].set_realreg (i
);
3428 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3429 the associated FRAME_CACHE if not null.
3430 Return the address of the first instruction past the prologue. */
3433 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3434 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3435 frame_info_ptr this_frame
,
3436 struct mips_frame_cache
*this_cache
)
3438 int prev_non_prologue_insn
;
3439 int this_non_prologue_insn
;
3440 int non_prologue_insns
;
3441 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3443 int prev_delay_slot
;
3448 int frame_reg
= MIPS_SP_REGNUM
;
3450 CORE_ADDR end_prologue_addr
;
3451 int seen_sp_adjust
= 0;
3452 int load_immediate_bytes
= 0;
3454 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3456 /* Can be called when there's no process, and hence when there's no
3458 if (this_frame
!= NULL
)
3459 sp
= get_frame_register_signed (this_frame
,
3460 gdbarch_num_regs (gdbarch
)
3465 if (limit_pc
> start_pc
+ 200)
3466 limit_pc
= start_pc
+ 200;
3469 prev_non_prologue_insn
= 0;
3470 non_prologue_insns
= 0;
3471 prev_delay_slot
= 0;
3474 /* Permit at most one non-prologue non-control-transfer instruction
3475 in the middle which may have been reordered by the compiler for
3478 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3480 unsigned long inst
, high_word
;
3484 this_non_prologue_insn
= 0;
3487 /* Fetch the instruction. */
3488 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3491 /* Save some code by pre-extracting some useful fields. */
3492 high_word
= (inst
>> 16) & 0xffff;
3493 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3494 reg
= high_word
& 0x1f;
3496 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3497 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3498 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3500 if (offset
< 0) /* Negative stack adjustment? */
3501 frame_offset
-= offset
;
3503 /* Exit loop if a positive stack adjustment is found, which
3504 usually means that the stack cleanup code in the function
3505 epilogue is reached. */
3509 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3510 && !regsize_is_64_bits
)
3512 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3514 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3515 && regsize_is_64_bits
)
3517 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3518 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3520 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3522 /* Old gcc frame, r30 is virtual frame pointer. */
3523 if (offset
!= frame_offset
)
3524 frame_addr
= sp
+ offset
;
3525 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3527 unsigned alloca_adjust
;
3530 frame_addr
= get_frame_register_signed
3531 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3534 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3535 if (alloca_adjust
> 0)
3537 /* FP > SP + frame_size. This may be because of
3538 an alloca or somethings similar. Fix sp to
3539 "pre-alloca" value, and try again. */
3540 sp
+= alloca_adjust
;
3541 /* Need to reset the status of all registers. Otherwise,
3542 we will hit a guard that prevents the new address
3543 for each register to be recomputed during the second
3545 reset_saved_regs (gdbarch
, this_cache
);
3550 /* move $30,$sp. With different versions of gas this will be either
3551 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3552 Accept any one of these. */
3553 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3555 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3556 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3558 unsigned alloca_adjust
;
3561 frame_addr
= get_frame_register_signed
3562 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3564 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3565 if (alloca_adjust
> 0)
3567 /* FP > SP + frame_size. This may be because of
3568 an alloca or somethings similar. Fix sp to
3569 "pre-alloca" value, and try again. */
3571 /* Need to reset the status of all registers. Otherwise,
3572 we will hit a guard that prevents the new address
3573 for each register to be recomputed during the second
3575 reset_saved_regs (gdbarch
, this_cache
);
3580 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3581 && !regsize_is_64_bits
)
3583 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3585 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3586 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3587 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3588 || high_word
== 0x3c1c /* lui $gp,n */
3589 || high_word
== 0x279c /* addiu $gp,$gp,n */
3590 || high_word
== 0x679c /* daddiu $gp,$gp,n */
3591 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3592 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3593 || inst
== 0x0399e02d /* daddu $gp,$gp,$t9 */
3594 || inst
== 0x033ce02d /* daddu $gp,$t9,$gp */
3597 /* These instructions are part of the prologue, but we don't
3598 need to do anything special to handle them. */
3600 /* The instructions below load $at or $t0 with an immediate
3601 value in preparation for a stack adjustment via
3602 subu $sp,$sp,[$at,$t0]. These instructions could also
3603 initialize a local variable, so we accept them only before
3604 a stack adjustment instruction was seen. */
3605 else if (!seen_sp_adjust
3607 && (high_word
== 0x3c01 /* lui $at,n */
3608 || high_word
== 0x3c08 /* lui $t0,n */
3609 || high_word
== 0x3421 /* ori $at,$at,n */
3610 || high_word
== 0x3508 /* ori $t0,$t0,n */
3611 || high_word
== 0x3401 /* ori $at,$zero,n */
3612 || high_word
== 0x3408 /* ori $t0,$zero,n */
3615 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3617 /* Check for branches and jumps. The instruction in the delay
3618 slot can be a part of the prologue, so move forward once more. */
3619 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3623 /* This instruction is not an instruction typically found
3624 in a prologue, so we must have reached the end of the
3628 this_non_prologue_insn
= 1;
3631 non_prologue_insns
+= this_non_prologue_insn
;
3633 /* A jump or branch, or enough non-prologue insns seen? If so,
3634 then we must have reached the end of the prologue by now. */
3635 if (prev_delay_slot
|| non_prologue_insns
> 1)
3638 prev_non_prologue_insn
= this_non_prologue_insn
;
3639 prev_delay_slot
= in_delay_slot
;
3643 if (this_cache
!= NULL
)
3646 (get_frame_register_signed (this_frame
,
3647 gdbarch_num_regs (gdbarch
) + frame_reg
)
3649 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3650 this assignment below, eventually. But it's still needed
3652 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3653 + mips_regnum (gdbarch
)->pc
]
3654 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3658 /* Set end_prologue_addr to the address of the instruction immediately
3659 after the last one we scanned. Unless the last one looked like a
3660 non-prologue instruction (and we looked ahead), in which case use
3661 its address instead. */
3663 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3665 /* In a frameless function, we might have incorrectly
3666 skipped some load immediate instructions. Undo the skipping
3667 if the load immediate was not followed by a stack adjustment. */
3668 if (load_immediate_bytes
&& !seen_sp_adjust
)
3669 end_prologue_addr
-= load_immediate_bytes
;
3671 return end_prologue_addr
;
3674 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3675 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3676 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3677 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3679 static struct mips_frame_cache
*
3680 mips_insn32_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3682 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3683 struct mips_frame_cache
*cache
;
3685 if ((*this_cache
) != NULL
)
3686 return (struct mips_frame_cache
*) (*this_cache
);
3688 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3689 (*this_cache
) = cache
;
3690 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3692 /* Analyze the function prologue. */
3694 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3695 CORE_ADDR start_addr
;
3697 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3698 if (start_addr
== 0)
3699 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3700 /* We can't analyze the prologue if we couldn't find the begining
3702 if (start_addr
== 0)
3705 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3706 (struct mips_frame_cache
*) *this_cache
);
3709 /* gdbarch_sp_regnum contains the value and not the address. */
3710 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3711 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3713 return (struct mips_frame_cache
*) (*this_cache
);
3717 mips_insn32_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3718 struct frame_id
*this_id
)
3720 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3722 /* This marks the outermost frame. */
3723 if (info
->base
== 0)
3725 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3728 static struct value
*
3729 mips_insn32_frame_prev_register (frame_info_ptr this_frame
,
3730 void **this_cache
, int regnum
)
3732 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3734 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3738 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3739 frame_info_ptr this_frame
, void **this_cache
)
3741 CORE_ADDR pc
= get_frame_pc (this_frame
);
3742 if (mips_pc_is_mips (pc
))
3747 static const struct frame_unwind mips_insn32_frame_unwind
=
3749 "mips insn32 prologue",
3751 default_frame_unwind_stop_reason
,
3752 mips_insn32_frame_this_id
,
3753 mips_insn32_frame_prev_register
,
3755 mips_insn32_frame_sniffer
3759 mips_insn32_frame_base_address (frame_info_ptr this_frame
,
3762 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3767 static const struct frame_base mips_insn32_frame_base
=
3769 &mips_insn32_frame_unwind
,
3770 mips_insn32_frame_base_address
,
3771 mips_insn32_frame_base_address
,
3772 mips_insn32_frame_base_address
3775 static const struct frame_base
*
3776 mips_insn32_frame_base_sniffer (frame_info_ptr this_frame
)
3778 CORE_ADDR pc
= get_frame_pc (this_frame
);
3779 if (mips_pc_is_mips (pc
))
3780 return &mips_insn32_frame_base
;
3785 static struct trad_frame_cache
*
3786 mips_stub_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3789 CORE_ADDR start_addr
;
3790 CORE_ADDR stack_addr
;
3791 struct trad_frame_cache
*this_trad_cache
;
3792 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3793 int num_regs
= gdbarch_num_regs (gdbarch
);
3795 if ((*this_cache
) != NULL
)
3796 return (struct trad_frame_cache
*) (*this_cache
);
3797 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3798 (*this_cache
) = this_trad_cache
;
3800 /* The return address is in the link register. */
3801 trad_frame_set_reg_realreg (this_trad_cache
,
3802 gdbarch_pc_regnum (gdbarch
),
3803 num_regs
+ MIPS_RA_REGNUM
);
3805 /* Frame ID, since it's a frameless / stackless function, no stack
3806 space is allocated and SP on entry is the current SP. */
3807 pc
= get_frame_pc (this_frame
);
3808 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3809 stack_addr
= get_frame_register_signed (this_frame
,
3810 num_regs
+ MIPS_SP_REGNUM
);
3811 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3813 /* Assume that the frame's base is the same as the
3815 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3817 return this_trad_cache
;
3821 mips_stub_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3822 struct frame_id
*this_id
)
3824 struct trad_frame_cache
*this_trad_cache
3825 = mips_stub_frame_cache (this_frame
, this_cache
);
3826 trad_frame_get_id (this_trad_cache
, this_id
);
3829 static struct value
*
3830 mips_stub_frame_prev_register (frame_info_ptr this_frame
,
3831 void **this_cache
, int regnum
)
3833 struct trad_frame_cache
*this_trad_cache
3834 = mips_stub_frame_cache (this_frame
, this_cache
);
3835 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3839 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3840 frame_info_ptr this_frame
, void **this_cache
)
3843 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3844 struct bound_minimal_symbol msym
;
3846 /* Use the stub unwinder for unreadable code. */
3847 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3850 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3853 /* Calling a PIC function from a non-PIC function passes through a
3854 stub. The stub for foo is named ".pic.foo". */
3855 msym
= lookup_minimal_symbol_by_pc (pc
);
3856 if (msym
.minsym
!= NULL
3857 && msym
.minsym
->linkage_name () != NULL
3858 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3864 static const struct frame_unwind mips_stub_frame_unwind
=
3868 default_frame_unwind_stop_reason
,
3869 mips_stub_frame_this_id
,
3870 mips_stub_frame_prev_register
,
3872 mips_stub_frame_sniffer
3876 mips_stub_frame_base_address (frame_info_ptr this_frame
,
3879 struct trad_frame_cache
*this_trad_cache
3880 = mips_stub_frame_cache (this_frame
, this_cache
);
3881 return trad_frame_get_this_base (this_trad_cache
);
3884 static const struct frame_base mips_stub_frame_base
=
3886 &mips_stub_frame_unwind
,
3887 mips_stub_frame_base_address
,
3888 mips_stub_frame_base_address
,
3889 mips_stub_frame_base_address
3892 static const struct frame_base
*
3893 mips_stub_frame_base_sniffer (frame_info_ptr this_frame
)
3895 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3896 return &mips_stub_frame_base
;
3901 /* mips_addr_bits_remove - remove useless address bits */
3904 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3906 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
3908 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3909 /* This hack is a work-around for existing boards using PMON, the
3910 simulator, and any other 64-bit targets that doesn't have true
3911 64-bit addressing. On these targets, the upper 32 bits of
3912 addresses are ignored by the hardware. Thus, the PC or SP are
3913 likely to have been sign extended to all 1s by instruction
3914 sequences that load 32-bit addresses. For example, a typical
3915 piece of code that loads an address is this:
3917 lui $r2, <upper 16 bits>
3918 ori $r2, <lower 16 bits>
3920 But the lui sign-extends the value such that the upper 32 bits
3921 may be all 1s. The workaround is simply to mask off these
3922 bits. In the future, gcc may be changed to support true 64-bit
3923 addressing, and this masking will have to be disabled. */
3924 return addr
&= 0xffffffffUL
;
3930 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3931 instruction and ending with a SC/SCD instruction. If such a sequence
3932 is found, attempt to step through it. A breakpoint is placed at the end of
3935 /* Instructions used during single-stepping of atomic sequences, standard
3937 #define LL_OPCODE 0x30
3938 #define LLD_OPCODE 0x34
3939 #define SC_OPCODE 0x38
3940 #define SCD_OPCODE 0x3c
3942 static std::vector
<CORE_ADDR
>
3943 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3945 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3947 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3951 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3952 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3954 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3955 /* Assume all atomic sequences start with a ll/lld instruction. */
3956 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3959 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3961 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3964 loc
+= MIPS_INSN32_SIZE
;
3965 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3967 /* Assume that there is at most one branch in the atomic
3968 sequence. If a branch is found, put a breakpoint in its
3969 destination address. */
3970 switch (itype_op (insn
))
3972 case 0: /* SPECIAL */
3973 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3974 return {}; /* fallback to the standard single-step code. */
3976 case 1: /* REGIMM */
3977 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3978 || ((itype_rt (insn
) & 0x1e) == 0
3979 && itype_rs (insn
) == 0)); /* BPOSGE* */
3983 return {}; /* fallback to the standard single-step code. */
3990 case 22: /* BLEZL */
3991 case 23: /* BGTTL */
3995 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3996 && (itype_rt (insn
) & 0x2) == 0);
3997 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
4002 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4007 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4008 if (last_breakpoint
>= 1)
4009 return {}; /* More than one branch found, fallback to the
4010 standard single-step code. */
4011 breaks
[1] = branch_bp
;
4015 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4019 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4020 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4023 loc
+= MIPS_INSN32_SIZE
;
4025 /* Insert a breakpoint right after the end of the atomic sequence. */
4028 /* Check for duplicated breakpoints. Check also for a breakpoint
4029 placed (branch instruction's destination) in the atomic sequence. */
4030 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4031 last_breakpoint
= 0;
4033 std::vector
<CORE_ADDR
> next_pcs
;
4035 /* Effectively inserts the breakpoints. */
4036 for (index
= 0; index
<= last_breakpoint
; index
++)
4037 next_pcs
.push_back (breaks
[index
]);
4042 static std::vector
<CORE_ADDR
>
4043 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4046 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4047 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4048 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4049 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4057 /* Assume all atomic sequences start with a ll/lld instruction. */
4058 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4059 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4061 loc
+= MIPS_INSN16_SIZE
;
4063 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4064 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4066 loc
+= MIPS_INSN16_SIZE
;
4068 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4069 that no atomic sequence is longer than "atomic_sequence_length"
4071 for (insn_count
= 0;
4072 !sc_found
&& insn_count
< atomic_sequence_length
;
4077 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4078 loc
+= MIPS_INSN16_SIZE
;
4080 /* Assume that there is at most one conditional branch in the
4081 atomic sequence. If a branch is found, put a breakpoint in
4082 its destination address. */
4083 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4085 /* 32-bit instructions. */
4086 case 2 * MIPS_INSN16_SIZE
:
4087 switch (micromips_op (insn
))
4089 case 0x10: /* POOL32I: bits 010000 */
4090 if ((b5s5_op (insn
) & 0x18) != 0x0
4091 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4092 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4093 && (b5s5_op (insn
) & 0x1d) != 0x11
4094 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4095 && ((b5s5_op (insn
) & 0x1e) != 0x14
4096 || (insn
& 0x3) != 0x0)
4097 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4098 && (b5s5_op (insn
) & 0x1e) != 0x1a
4099 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4100 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4101 || (insn
& 0x3) != 0x0)
4102 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4103 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4104 || (insn
& 0x3) != 0x1))
4105 /* BC1ANY*: bits 010000 111xx xxx01 */
4109 case 0x25: /* BEQ: bits 100101 */
4110 case 0x2d: /* BNE: bits 101101 */
4112 insn
|= mips_fetch_instruction (gdbarch
,
4113 ISA_MICROMIPS
, loc
, NULL
);
4114 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4115 + micromips_relative_offset16 (insn
));
4119 case 0x00: /* POOL32A: bits 000000 */
4121 insn
|= mips_fetch_instruction (gdbarch
,
4122 ISA_MICROMIPS
, loc
, NULL
);
4123 if (b0s6_op (insn
) != 0x3c
4124 /* POOL32Axf: bits 000000 ... 111100 */
4125 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4126 /* JALR, JALR.HB: 000000 000x111100 111100 */
4127 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4131 case 0x1d: /* JALS: bits 011101 */
4132 case 0x35: /* J: bits 110101 */
4133 case 0x3d: /* JAL: bits 111101 */
4134 case 0x3c: /* JALX: bits 111100 */
4135 return {}; /* Fall back to the standard single-step code. */
4137 case 0x18: /* POOL32C: bits 011000 */
4138 if ((b12s4_op (insn
) & 0xb) == 0xb)
4139 /* SC, SCD: bits 011000 1x11 */
4143 loc
+= MIPS_INSN16_SIZE
;
4146 /* 16-bit instructions. */
4147 case MIPS_INSN16_SIZE
:
4148 switch (micromips_op (insn
))
4150 case 0x23: /* BEQZ16: bits 100011 */
4151 case 0x2b: /* BNEZ16: bits 101011 */
4152 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4156 case 0x11: /* POOL16C: bits 010001 */
4157 if ((b5s5_op (insn
) & 0x1c) != 0xc
4158 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4159 && b5s5_op (insn
) != 0x18)
4160 /* JRADDIUSP: bits 010001 11000 */
4162 return {}; /* Fall back to the standard single-step code. */
4164 case 0x33: /* B16: bits 110011 */
4165 return {}; /* Fall back to the standard single-step code. */
4171 if (last_breakpoint
>= 1)
4172 return {}; /* More than one branch found, fallback to the
4173 standard single-step code. */
4174 breaks
[1] = branch_bp
;
4181 /* Insert a breakpoint right after the end of the atomic sequence. */
4184 /* Check for duplicated breakpoints. Check also for a breakpoint
4185 placed (branch instruction's destination) in the atomic sequence */
4186 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4187 last_breakpoint
= 0;
4189 std::vector
<CORE_ADDR
> next_pcs
;
4191 /* Effectively inserts the breakpoints. */
4192 for (index
= 0; index
<= last_breakpoint
; index
++)
4193 next_pcs
.push_back (breaks
[index
]);
4198 static std::vector
<CORE_ADDR
>
4199 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4201 if (mips_pc_is_mips (pc
))
4202 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4203 else if (mips_pc_is_micromips (gdbarch
, pc
))
4204 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4209 /* mips_software_single_step() is called just before we want to resume
4210 the inferior, if we want to single-step it but there is no hardware
4211 or kernel single-step support (MIPS on GNU/Linux for example). We find
4212 the target of the coming instruction and breakpoint it. */
4214 std::vector
<CORE_ADDR
>
4215 mips_software_single_step (struct regcache
*regcache
)
4217 struct gdbarch
*gdbarch
= regcache
->arch ();
4218 CORE_ADDR pc
, next_pc
;
4220 pc
= regcache_read_pc (regcache
);
4221 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4223 if (!next_pcs
.empty ())
4226 next_pc
= mips_next_pc (regcache
, pc
);
4231 /* Test whether the PC points to the return instruction at the
4232 end of a function. */
4235 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4240 /* This used to check for MIPS16, but this piece of code is never
4241 called for MIPS16 functions. And likewise microMIPS ones. */
4242 gdb_assert (mips_pc_is_mips (pc
));
4244 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4246 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4250 /* This fencepost looks highly suspicious to me. Removing it also
4251 seems suspicious as it could affect remote debugging across serial
4255 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4261 struct inferior
*inf
;
4263 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4265 fence
= start_pc
- heuristic_fence_post
;
4269 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4270 fence
= VM_MIN_ADDRESS
;
4272 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4274 inf
= current_inferior ();
4276 /* Search back for previous return. */
4277 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4278 if (start_pc
< fence
)
4280 /* It's not clear to me why we reach this point when
4281 stop_soon, but with this test, at least we
4282 don't print out warnings for every child forked (eg, on
4283 decstation). 22apr93 rich@cygnus.com. */
4284 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4286 static int blurb_printed
= 0;
4288 warning (_("GDB can't find the start of the function at %s."),
4289 paddress (gdbarch
, pc
));
4293 /* This actually happens frequently in embedded
4294 development, when you first connect to a board
4295 and your stack pointer and pc are nowhere in
4296 particular. This message needs to give people
4297 in that situation enough information to
4298 determine that it's no big deal. */
4300 GDB is unable to find the start of the function at %s\n\
4301 and thus can't determine the size of that function's stack frame.\n\
4302 This means that GDB may be unable to access that stack frame, or\n\
4303 the frames below it.\n\
4304 This problem is most likely caused by an invalid program counter or\n\
4306 However, if you think GDB should simply search farther back\n\
4307 from %s for code which looks like the beginning of a\n\
4308 function, you can increase the range of the search using the `set\n\
4309 heuristic-fence-post' command.\n",
4310 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4317 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4319 unsigned short inst
;
4321 /* On MIPS16, any one of the following is likely to be the
4322 start of a function:
4328 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4329 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4330 if ((inst
& 0xff80) == 0x6480) /* save */
4332 if (start_pc
- instlen
>= fence
)
4334 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4335 start_pc
- instlen
, NULL
);
4336 if ((inst
& 0xf800) == 0xf000) /* extend */
4337 start_pc
-= instlen
;
4341 else if (((inst
& 0xf81f) == 0xe809
4342 && (inst
& 0x700) != 0x700) /* entry */
4343 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4344 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4345 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4347 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4348 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4353 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4361 /* On microMIPS, any one of the following is likely to be the
4362 start of a function:
4366 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4367 switch (micromips_op (insn
))
4369 case 0xc: /* ADDIU: bits 001100 */
4370 case 0x17: /* DADDIU: bits 010111 */
4371 sreg
= b0s5_reg (insn
);
4372 dreg
= b5s5_reg (insn
);
4374 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4375 pc
+ MIPS_INSN16_SIZE
, NULL
);
4376 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4377 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4378 /* (D)ADDIU $sp, imm */
4383 case 0x10: /* POOL32I: bits 010000 */
4384 if (b5s5_op (insn
) == 0xd
4385 /* LUI: bits 010000 001101 */
4386 && b0s5_reg (insn
>> 16) == 28)
4391 case 0x13: /* POOL16D: bits 010011 */
4392 if ((insn
& 0x1) == 0x1)
4393 /* ADDIUSP: bits 010011 1 */
4395 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4401 /* ADDIUS5: bits 010011 0 */
4403 dreg
= b5s5_reg (insn
);
4404 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4405 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4406 /* ADDIUS5 $sp, -imm */
4414 else if (mips_about_to_return (gdbarch
, start_pc
))
4416 /* Skip return and its delay slot. */
4417 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4424 struct mips_objfile_private
4430 /* According to the current ABI, should the type be passed in a
4431 floating-point register (assuming that there is space)? When there
4432 is no FPU, FP are not even considered as possible candidates for
4433 FP registers and, consequently this returns false - forces FP
4434 arguments into integer registers. */
4437 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4438 struct type
*arg_type
)
4440 return ((typecode
== TYPE_CODE_FLT
4441 || (mips_eabi (gdbarch
)
4442 && (typecode
== TYPE_CODE_STRUCT
4443 || typecode
== TYPE_CODE_UNION
)
4444 && arg_type
->num_fields () == 1
4445 && check_typedef (arg_type
->field (0).type ())->code ()
4447 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4450 /* On o32, argument passing in GPRs depends on the alignment of the type being
4451 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4454 mips_type_needs_double_align (struct type
*type
)
4456 enum type_code typecode
= type
->code ();
4458 if (typecode
== TYPE_CODE_FLT
&& type
->length () == 8)
4460 else if (typecode
== TYPE_CODE_STRUCT
)
4462 if (type
->num_fields () < 1)
4464 return mips_type_needs_double_align (type
->field (0).type ());
4466 else if (typecode
== TYPE_CODE_UNION
)
4470 n
= type
->num_fields ();
4471 for (i
= 0; i
< n
; i
++)
4472 if (mips_type_needs_double_align (type
->field (i
).type ()))
4479 /* Adjust the address downward (direction of stack growth) so that it
4480 is correctly aligned for a new stack frame. */
4482 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4484 return align_down (addr
, 16);
4487 /* Implement the "push_dummy_code" gdbarch method. */
4490 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4491 CORE_ADDR funaddr
, struct value
**args
,
4492 int nargs
, struct type
*value_type
,
4493 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4494 struct regcache
*regcache
)
4496 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4500 /* Reserve enough room on the stack for our breakpoint instruction. */
4501 bp_slot
= sp
- sizeof (nop_insn
);
4503 /* Return to microMIPS mode if calling microMIPS code to avoid
4504 triggering an address error exception on processors that only
4505 support microMIPS execution. */
4506 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4507 ? make_compact_addr (bp_slot
) : bp_slot
);
4509 /* The breakpoint layer automatically adjusts the address of
4510 breakpoints inserted in a branch delay slot. With enough
4511 bad luck, the 4 bytes located just before our breakpoint
4512 instruction could look like a branch instruction, and thus
4513 trigger the adjustement, and break the function call entirely.
4514 So, we reserve those 4 bytes and write a nop instruction
4515 to prevent that from happening. */
4516 nop_addr
= bp_slot
- sizeof (nop_insn
);
4517 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4518 sp
= mips_frame_align (gdbarch
, nop_addr
);
4520 /* Inferior resumes at the function entry point. */
4527 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4528 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4529 int nargs
, struct value
**args
, CORE_ADDR sp
,
4530 function_call_return_method return_method
,
4531 CORE_ADDR struct_addr
)
4537 int stack_offset
= 0;
4538 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4539 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4540 int abi_regsize
= mips_abi_regsize (gdbarch
);
4542 /* For shared libraries, "t9" needs to point at the function
4544 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4546 /* Set the return address register to point to the entry point of
4547 the program, where a breakpoint lies in wait. */
4548 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4550 /* First ensure that the stack and structure return address (if any)
4551 are properly aligned. The stack has to be at least 64-bit
4552 aligned even on 32-bit machines, because doubles must be 64-bit
4553 aligned. For n32 and n64, stack frames need to be 128-bit
4554 aligned, so we round to this widest known alignment. */
4556 sp
= align_down (sp
, 16);
4557 struct_addr
= align_down (struct_addr
, 16);
4559 /* Now make space on the stack for the args. We allocate more
4560 than necessary for EABI, because the first few arguments are
4561 passed in registers, but that's OK. */
4562 for (argnum
= 0; argnum
< nargs
; argnum
++)
4563 arg_space
+= align_up (args
[argnum
]->type ()->length (),
4565 sp
-= align_up (arg_space
, 16);
4568 gdb_printf (gdb_stdlog
,
4569 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4570 paddress (gdbarch
, sp
),
4571 (long) align_up (arg_space
, 16));
4573 /* Initialize the integer and float register pointers. */
4574 argreg
= MIPS_A0_REGNUM
;
4575 float_argreg
= mips_fpa0_regnum (gdbarch
);
4577 /* The struct_return pointer occupies the first parameter-passing reg. */
4578 if (return_method
== return_method_struct
)
4581 gdb_printf (gdb_stdlog
,
4582 "mips_eabi_push_dummy_call: "
4583 "struct_return reg=%d %s\n",
4584 argreg
, paddress (gdbarch
, struct_addr
));
4585 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4588 /* Now load as many as possible of the first arguments into
4589 registers, and push the rest onto the stack. Loop thru args
4590 from first to last. */
4591 for (argnum
= 0; argnum
< nargs
; argnum
++)
4593 const gdb_byte
*val
;
4594 /* This holds the address of structures that are passed by
4596 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4597 struct value
*arg
= args
[argnum
];
4598 struct type
*arg_type
= check_typedef (arg
->type ());
4599 int len
= arg_type
->length ();
4600 enum type_code typecode
= arg_type
->code ();
4603 gdb_printf (gdb_stdlog
,
4604 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4605 argnum
+ 1, len
, (int) typecode
);
4607 /* The EABI passes structures that do not fit in a register by
4609 if (len
> abi_regsize
4610 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4612 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4613 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4615 typecode
= TYPE_CODE_PTR
;
4619 gdb_printf (gdb_stdlog
, " push");
4622 val
= arg
->contents ().data ();
4624 /* 32-bit ABIs always start floating point arguments in an
4625 even-numbered floating point register. Round the FP register
4626 up before the check to see if there are any FP registers
4627 left. Non MIPS_EABI targets also pass the FP in the integer
4628 registers so also round up normal registers. */
4629 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4631 if ((float_argreg
& 1))
4635 /* Floating point arguments passed in registers have to be
4636 treated specially. On 32-bit architectures, doubles
4637 are passed in register pairs; the even register gets
4638 the low word, and the odd register gets the high word.
4639 On non-EABI processors, the first two floating point arguments are
4640 also copied to general registers, because MIPS16 functions
4641 don't use float registers for arguments. This duplication of
4642 arguments in general registers can't hurt non-MIPS16 functions
4643 because those registers are normally skipped. */
4644 /* MIPS_EABI squeezes a struct that contains a single floating
4645 point value into an FP register instead of pushing it onto the
4647 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4648 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4650 /* EABI32 will pass doubles in consecutive registers, even on
4651 64-bit cores. At one time, we used to check the size of
4652 `float_argreg' to determine whether or not to pass doubles
4653 in consecutive registers, but this is not sufficient for
4654 making the ABI determination. */
4655 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4657 int low_offset
= gdbarch_byte_order (gdbarch
)
4658 == BFD_ENDIAN_BIG
? 4 : 0;
4661 /* Write the low word of the double to the even register(s). */
4662 regval
= extract_signed_integer (val
+ low_offset
,
4665 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4666 float_argreg
, phex (regval
, 4));
4667 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4669 /* Write the high word of the double to the odd register(s). */
4670 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4673 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4674 float_argreg
, phex (regval
, 4));
4675 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4679 /* This is a floating point value that fits entirely
4680 in a single register. */
4681 /* On 32 bit ABI's the float_argreg is further adjusted
4682 above to ensure that it is even register aligned. */
4683 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4685 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4686 float_argreg
, phex (regval
, len
));
4687 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4692 /* Copy the argument to general registers or the stack in
4693 register-sized pieces. Large arguments are split between
4694 registers and stack. */
4695 /* Note: structs whose size is not a multiple of abi_regsize
4696 are treated specially: Irix cc passes
4697 them in registers where gcc sometimes puts them on the
4698 stack. For maximum compatibility, we will put them in
4700 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4702 /* Note: Floating-point values that didn't fit into an FP
4703 register are only written to memory. */
4706 /* Remember if the argument was written to the stack. */
4707 int stack_used_p
= 0;
4708 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4711 gdb_printf (gdb_stdlog
, " -- partial=%d",
4714 /* Write this portion of the argument to the stack. */
4715 if (argreg
> mips_last_arg_regnum (gdbarch
)
4717 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4719 /* Should shorter than int integer values be
4720 promoted to int before being stored? */
4721 int longword_offset
= 0;
4724 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4726 if (abi_regsize
== 8
4727 && (typecode
== TYPE_CODE_INT
4728 || typecode
== TYPE_CODE_PTR
4729 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4730 longword_offset
= abi_regsize
- len
;
4731 else if ((typecode
== TYPE_CODE_STRUCT
4732 || typecode
== TYPE_CODE_UNION
)
4733 && arg_type
->length () < abi_regsize
)
4734 longword_offset
= abi_regsize
- len
;
4739 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
4740 paddress (gdbarch
, stack_offset
));
4741 gdb_printf (gdb_stdlog
, " longword_offset=%s",
4742 paddress (gdbarch
, longword_offset
));
4745 addr
= sp
+ stack_offset
+ longword_offset
;
4750 gdb_printf (gdb_stdlog
, " @%s ",
4751 paddress (gdbarch
, addr
));
4752 for (i
= 0; i
< partial_len
; i
++)
4754 gdb_printf (gdb_stdlog
, "%02x",
4758 write_memory (addr
, val
, partial_len
);
4761 /* Note!!! This is NOT an else clause. Odd sized
4762 structs may go thru BOTH paths. Floating point
4763 arguments will not. */
4764 /* Write this portion of the argument to a general
4765 purpose register. */
4766 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4767 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4770 extract_signed_integer (val
, partial_len
, byte_order
);
4773 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
4775 phex (regval
, abi_regsize
));
4776 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4783 /* Compute the offset into the stack at which we will
4784 copy the next parameter.
4786 In the new EABI (and the NABI32), the stack_offset
4787 only needs to be adjusted when it has been used. */
4790 stack_offset
+= align_up (partial_len
, abi_regsize
);
4794 gdb_printf (gdb_stdlog
, "\n");
4797 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4799 /* Return adjusted stack pointer. */
4803 /* Determine the return value convention being used. */
4805 static enum return_value_convention
4806 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4807 struct type
*type
, struct regcache
*regcache
,
4808 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4810 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
4811 int fp_return_type
= 0;
4812 int offset
, regnum
, xfer
;
4814 if (type
->length () > 2 * mips_abi_regsize (gdbarch
))
4815 return RETURN_VALUE_STRUCT_CONVENTION
;
4817 /* Floating point type? */
4818 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4820 if (type
->code () == TYPE_CODE_FLT
)
4822 /* Structs with a single field of float type
4823 are returned in a floating point register. */
4824 if ((type
->code () == TYPE_CODE_STRUCT
4825 || type
->code () == TYPE_CODE_UNION
)
4826 && type
->num_fields () == 1)
4828 struct type
*fieldtype
= type
->field (0).type ();
4830 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4837 /* A floating-point value belongs in the least significant part
4840 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
4841 regnum
= mips_regnum (gdbarch
)->fp0
;
4845 /* An integer value goes in V0/V1. */
4847 gdb_printf (gdb_stderr
, "Return scalar in $v0\n");
4848 regnum
= MIPS_V0_REGNUM
;
4851 offset
< type
->length ();
4852 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4854 xfer
= mips_abi_regsize (gdbarch
);
4855 if (offset
+ xfer
> type
->length ())
4856 xfer
= type
->length () - offset
;
4857 mips_xfer_register (gdbarch
, regcache
,
4858 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4859 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4863 return RETURN_VALUE_REGISTER_CONVENTION
;
4867 /* N32/N64 ABI stuff. */
4869 /* Search for a naturally aligned double at OFFSET inside a struct
4870 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4874 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4879 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4882 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4885 if (arg_type
->length () < offset
+ MIPS64_REGSIZE
)
4888 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4891 struct type
*field_type
;
4893 /* We're only looking at normal fields. */
4894 if (arg_type
->field (i
).is_static ()
4895 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4898 /* If we have gone past the offset, there is no double to pass. */
4899 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4903 field_type
= check_typedef (arg_type
->field (i
).type ());
4905 /* If this field is entirely before the requested offset, go
4906 on to the next one. */
4907 if (pos
+ field_type
->length () <= offset
)
4910 /* If this is our special aligned double, we can stop. */
4911 if (field_type
->code () == TYPE_CODE_FLT
4912 && field_type
->length () == MIPS64_REGSIZE
)
4915 /* This field starts at or before the requested offset, and
4916 overlaps it. If it is a structure, recurse inwards. */
4917 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4924 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4925 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4926 int nargs
, struct value
**args
, CORE_ADDR sp
,
4927 function_call_return_method return_method
,
4928 CORE_ADDR struct_addr
)
4934 int stack_offset
= 0;
4935 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4936 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4938 /* For shared libraries, "t9" needs to point at the function
4940 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4942 /* Set the return address register to point to the entry point of
4943 the program, where a breakpoint lies in wait. */
4944 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4946 /* First ensure that the stack and structure return address (if any)
4947 are properly aligned. The stack has to be at least 64-bit
4948 aligned even on 32-bit machines, because doubles must be 64-bit
4949 aligned. For n32 and n64, stack frames need to be 128-bit
4950 aligned, so we round to this widest known alignment. */
4952 sp
= align_down (sp
, 16);
4953 struct_addr
= align_down (struct_addr
, 16);
4955 /* Now make space on the stack for the args. */
4956 for (argnum
= 0; argnum
< nargs
; argnum
++)
4957 arg_space
+= align_up (args
[argnum
]->type ()->length (),
4959 sp
-= align_up (arg_space
, 16);
4962 gdb_printf (gdb_stdlog
,
4963 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4964 paddress (gdbarch
, sp
),
4965 (long) align_up (arg_space
, 16));
4967 /* Initialize the integer and float register pointers. */
4968 argreg
= MIPS_A0_REGNUM
;
4969 float_argreg
= mips_fpa0_regnum (gdbarch
);
4971 /* The struct_return pointer occupies the first parameter-passing reg. */
4972 if (return_method
== return_method_struct
)
4975 gdb_printf (gdb_stdlog
,
4976 "mips_n32n64_push_dummy_call: "
4977 "struct_return reg=%d %s\n",
4978 argreg
, paddress (gdbarch
, struct_addr
));
4979 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4982 /* Now load as many as possible of the first arguments into
4983 registers, and push the rest onto the stack. Loop thru args
4984 from first to last. */
4985 for (argnum
= 0; argnum
< nargs
; argnum
++)
4987 const gdb_byte
*val
;
4988 struct value
*arg
= args
[argnum
];
4989 struct type
*arg_type
= check_typedef (arg
->type ());
4990 int len
= arg_type
->length ();
4991 enum type_code typecode
= arg_type
->code ();
4994 gdb_printf (gdb_stdlog
,
4995 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4996 argnum
+ 1, len
, (int) typecode
);
4998 val
= arg
->contents ().data ();
5000 /* A 128-bit long double value requires an even-odd pair of
5001 floating-point registers. */
5003 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5004 && (float_argreg
& 1))
5010 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5011 && argreg
<= mips_last_arg_regnum (gdbarch
))
5013 /* This is a floating point value that fits entirely
5014 in a single register or a pair of registers. */
5015 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5016 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5018 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5019 float_argreg
, phex (regval
, reglen
));
5020 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5023 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5024 argreg
, phex (regval
, reglen
));
5025 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5030 regval
= extract_unsigned_integer (val
+ reglen
,
5031 reglen
, byte_order
);
5033 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5034 float_argreg
, phex (regval
, reglen
));
5035 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5038 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5039 argreg
, phex (regval
, reglen
));
5040 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5047 /* Copy the argument to general registers or the stack in
5048 register-sized pieces. Large arguments are split between
5049 registers and stack. */
5050 /* For N32/N64, structs, unions, or other composite types are
5051 treated as a sequence of doublewords, and are passed in integer
5052 or floating point registers as though they were simple scalar
5053 parameters to the extent that they fit, with any excess on the
5054 stack packed according to the normal memory layout of the
5056 The caller does not reserve space for the register arguments;
5057 the callee is responsible for reserving it if required. */
5058 /* Note: Floating-point values that didn't fit into an FP
5059 register are only written to memory. */
5062 /* Remember if the argument was written to the stack. */
5063 int stack_used_p
= 0;
5064 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5067 gdb_printf (gdb_stdlog
, " -- partial=%d",
5070 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5071 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5073 /* Write this portion of the argument to the stack. */
5074 if (argreg
> mips_last_arg_regnum (gdbarch
))
5076 /* Should shorter than int integer values be
5077 promoted to int before being stored? */
5078 int longword_offset
= 0;
5081 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5083 if ((typecode
== TYPE_CODE_INT
5084 || typecode
== TYPE_CODE_PTR
)
5086 longword_offset
= MIPS64_REGSIZE
- len
;
5091 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5092 paddress (gdbarch
, stack_offset
));
5093 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5094 paddress (gdbarch
, longword_offset
));
5097 addr
= sp
+ stack_offset
+ longword_offset
;
5102 gdb_printf (gdb_stdlog
, " @%s ",
5103 paddress (gdbarch
, addr
));
5104 for (i
= 0; i
< partial_len
; i
++)
5106 gdb_printf (gdb_stdlog
, "%02x",
5110 write_memory (addr
, val
, partial_len
);
5113 /* Note!!! This is NOT an else clause. Odd sized
5114 structs may go thru BOTH paths. */
5115 /* Write this portion of the argument to a general
5116 purpose register. */
5117 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5121 /* Sign extend pointers, 32-bit integers and signed
5122 16-bit and 8-bit integers; everything else is taken
5125 if ((partial_len
== 4
5126 && (typecode
== TYPE_CODE_PTR
5127 || typecode
== TYPE_CODE_INT
))
5129 && typecode
== TYPE_CODE_INT
5130 && !arg_type
->is_unsigned ()))
5131 regval
= extract_signed_integer (val
, partial_len
,
5134 regval
= extract_unsigned_integer (val
, partial_len
,
5137 /* A non-floating-point argument being passed in a
5138 general register. If a struct or union, and if
5139 the remaining length is smaller than the register
5140 size, we have to adjust the register value on
5143 It does not seem to be necessary to do the
5144 same for integral types. */
5146 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5147 && partial_len
< MIPS64_REGSIZE
5148 && (typecode
== TYPE_CODE_STRUCT
5149 || typecode
== TYPE_CODE_UNION
))
5150 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5154 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5156 phex (regval
, MIPS64_REGSIZE
));
5157 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5159 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5160 arg_type
->length () - len
))
5163 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5165 phex (regval
, MIPS64_REGSIZE
));
5166 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5177 /* Compute the offset into the stack at which we will
5178 copy the next parameter.
5180 In N32 (N64?), the stack_offset only needs to be
5181 adjusted when it has been used. */
5184 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5188 gdb_printf (gdb_stdlog
, "\n");
5191 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5193 /* Return adjusted stack pointer. */
5197 static enum return_value_convention
5198 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5199 struct type
*type
, struct regcache
*regcache
,
5200 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5202 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5204 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5206 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5207 if needed), as appropriate for the type. Composite results (struct,
5208 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5211 * A struct with only one or two floating point fields is returned in $f0
5212 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5215 * Any other composite results of at most 128 bits are returned in
5216 $2 (first 64 bits) and $3 (remainder, if necessary).
5218 * Larger composite results are handled by converting the function to a
5219 procedure with an implicit first parameter, which is a pointer to an area
5220 reserved by the caller to receive the result. [The o32-bit ABI requires
5221 that all composite results be handled by conversion to implicit first
5222 parameters. The MIPS/SGI Fortran implementation has always made a
5223 specific exception to return COMPLEX results in the floating point
5226 From MIPSpro Assembly Language Programmer's Guide, Document Number:
5231 Name fgregdef.h) Use and Linkage
5232 -----------------------------------------------------------------
5233 $f0, $f2 fv0, fv1 Hold results of floating-point type function
5234 ($f0) and complex type function ($f0 has the
5235 real part, $f2 has the imaginary part.) */
5237 if (type
->length () > 2 * MIPS64_REGSIZE
)
5238 return RETURN_VALUE_STRUCT_CONVENTION
;
5239 else if ((type
->code () == TYPE_CODE_COMPLEX
5240 || (type
->code () == TYPE_CODE_FLT
&& type
->length () == 16))
5241 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5243 /* A complex value of up to 128 bits in width as well as a 128-bit
5244 floating-point value goes in both $f0 and $f2. A single complex
5245 value is held in the lower halves only of the respective registers.
5246 The two registers are used in the same as memory order, so the
5247 bytes with the lower memory address are in $f0. */
5249 gdb_printf (gdb_stderr
, "Return float in $f0 and $f2\n");
5250 mips_xfer_register (gdbarch
, regcache
,
5251 (gdbarch_num_regs (gdbarch
)
5252 + mips_regnum (gdbarch
)->fp0
),
5253 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5254 readbuf
, writebuf
, 0);
5255 mips_xfer_register (gdbarch
, regcache
,
5256 (gdbarch_num_regs (gdbarch
)
5257 + mips_regnum (gdbarch
)->fp0
+ 2),
5258 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5259 readbuf
? readbuf
+ type
->length () / 2 : readbuf
,
5261 ? writebuf
+ type
->length () / 2 : writebuf
), 0);
5262 return RETURN_VALUE_REGISTER_CONVENTION
;
5264 else if (type
->code () == TYPE_CODE_FLT
5265 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5267 /* A single or double floating-point value that fits in FP0. */
5269 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5270 mips_xfer_register (gdbarch
, regcache
,
5271 (gdbarch_num_regs (gdbarch
)
5272 + mips_regnum (gdbarch
)->fp0
),
5274 gdbarch_byte_order (gdbarch
),
5275 readbuf
, writebuf
, 0);
5276 return RETURN_VALUE_REGISTER_CONVENTION
;
5278 else if (type
->code () == TYPE_CODE_STRUCT
5279 && type
->num_fields () <= 2
5280 && type
->num_fields () >= 1
5281 && ((type
->num_fields () == 1
5282 && (check_typedef (type
->field (0).type ())->code ()
5284 || (type
->num_fields () == 2
5285 && (check_typedef (type
->field (0).type ())->code ()
5287 && (check_typedef (type
->field (1).type ())->code ()
5288 == TYPE_CODE_FLT
))))
5290 /* A struct that contains one or two floats. Each value is part
5291 in the least significant part of their floating point
5292 register (or GPR, for soft float). */
5295 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5296 ? mips_regnum (gdbarch
)->fp0
5298 field
< type
->num_fields (); field
++, regnum
+= 2)
5300 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5302 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5304 if (type
->field (field
).type ()->length () == 16)
5306 /* A 16-byte long double field goes in two consecutive
5308 mips_xfer_register (gdbarch
, regcache
,
5309 gdbarch_num_regs (gdbarch
) + regnum
,
5311 gdbarch_byte_order (gdbarch
),
5312 readbuf
, writebuf
, offset
);
5313 mips_xfer_register (gdbarch
, regcache
,
5314 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5316 gdbarch_byte_order (gdbarch
),
5317 readbuf
, writebuf
, offset
+ 8);
5320 mips_xfer_register (gdbarch
, regcache
,
5321 gdbarch_num_regs (gdbarch
) + regnum
,
5322 type
->field (field
).type ()->length (),
5323 gdbarch_byte_order (gdbarch
),
5324 readbuf
, writebuf
, offset
);
5326 return RETURN_VALUE_REGISTER_CONVENTION
;
5328 else if (type
->code () == TYPE_CODE_STRUCT
5329 || type
->code () == TYPE_CODE_UNION
5330 || type
->code () == TYPE_CODE_ARRAY
)
5332 /* A composite type. Extract the left justified value,
5333 regardless of the byte order. I.e. DO NOT USE
5337 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5338 offset
< type
->length ();
5339 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5341 int xfer
= register_size (gdbarch
, regnum
);
5342 if (offset
+ xfer
> type
->length ())
5343 xfer
= type
->length () - offset
;
5345 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5346 offset
, xfer
, regnum
);
5347 mips_xfer_register (gdbarch
, regcache
,
5348 gdbarch_num_regs (gdbarch
) + regnum
,
5349 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5352 return RETURN_VALUE_REGISTER_CONVENTION
;
5356 /* A scalar extract each part but least-significant-byte
5360 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5361 offset
< type
->length ();
5362 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5364 int xfer
= register_size (gdbarch
, regnum
);
5365 if (offset
+ xfer
> type
->length ())
5366 xfer
= type
->length () - offset
;
5368 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5369 offset
, xfer
, regnum
);
5370 mips_xfer_register (gdbarch
, regcache
,
5371 gdbarch_num_regs (gdbarch
) + regnum
,
5372 xfer
, gdbarch_byte_order (gdbarch
),
5373 readbuf
, writebuf
, offset
);
5375 return RETURN_VALUE_REGISTER_CONVENTION
;
5379 /* Which registers to use for passing floating-point values between
5380 function calls, one of floating-point, general and both kinds of
5381 registers. O32 and O64 use different register kinds for standard
5382 MIPS and MIPS16 code; to make the handling of cases where we may
5383 not know what kind of code is being used (e.g. no debug information)
5384 easier we sometimes use both kinds. */
5393 /* O32 ABI stuff. */
5396 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5397 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5398 int nargs
, struct value
**args
, CORE_ADDR sp
,
5399 function_call_return_method return_method
,
5400 CORE_ADDR struct_addr
)
5406 int stack_offset
= 0;
5407 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5408 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5410 /* For shared libraries, "t9" needs to point at the function
5412 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5414 /* Set the return address register to point to the entry point of
5415 the program, where a breakpoint lies in wait. */
5416 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5418 /* First ensure that the stack and structure return address (if any)
5419 are properly aligned. The stack has to be at least 64-bit
5420 aligned even on 32-bit machines, because doubles must be 64-bit
5421 aligned. For n32 and n64, stack frames need to be 128-bit
5422 aligned, so we round to this widest known alignment. */
5424 sp
= align_down (sp
, 16);
5425 struct_addr
= align_down (struct_addr
, 16);
5427 /* Now make space on the stack for the args. */
5428 for (argnum
= 0; argnum
< nargs
; argnum
++)
5430 struct type
*arg_type
= check_typedef (args
[argnum
]->type ());
5432 /* Align to double-word if necessary. */
5433 if (mips_type_needs_double_align (arg_type
))
5434 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5435 /* Allocate space on the stack. */
5436 arg_space
+= align_up (arg_type
->length (), MIPS32_REGSIZE
);
5438 sp
-= align_up (arg_space
, 16);
5441 gdb_printf (gdb_stdlog
,
5442 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5443 paddress (gdbarch
, sp
),
5444 (long) align_up (arg_space
, 16));
5446 /* Initialize the integer and float register pointers. */
5447 argreg
= MIPS_A0_REGNUM
;
5448 float_argreg
= mips_fpa0_regnum (gdbarch
);
5450 /* The struct_return pointer occupies the first parameter-passing reg. */
5451 if (return_method
== return_method_struct
)
5454 gdb_printf (gdb_stdlog
,
5455 "mips_o32_push_dummy_call: "
5456 "struct_return reg=%d %s\n",
5457 argreg
, paddress (gdbarch
, struct_addr
));
5458 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5459 stack_offset
+= MIPS32_REGSIZE
;
5462 /* Now load as many as possible of the first arguments into
5463 registers, and push the rest onto the stack. Loop thru args
5464 from first to last. */
5465 for (argnum
= 0; argnum
< nargs
; argnum
++)
5467 const gdb_byte
*val
;
5468 struct value
*arg
= args
[argnum
];
5469 struct type
*arg_type
= check_typedef (arg
->type ());
5470 int len
= arg_type
->length ();
5471 enum type_code typecode
= arg_type
->code ();
5474 gdb_printf (gdb_stdlog
,
5475 "mips_o32_push_dummy_call: %d len=%d type=%d",
5476 argnum
+ 1, len
, (int) typecode
);
5478 val
= arg
->contents ().data ();
5480 /* 32-bit ABIs always start floating point arguments in an
5481 even-numbered floating point register. Round the FP register
5482 up before the check to see if there are any FP registers
5483 left. O32 targets also pass the FP in the integer registers
5484 so also round up normal registers. */
5485 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5487 if ((float_argreg
& 1))
5491 /* Floating point arguments passed in registers have to be
5492 treated specially. On 32-bit architectures, doubles are
5493 passed in register pairs; the even FP register gets the
5494 low word, and the odd FP register gets the high word.
5495 On O32, the first two floating point arguments are also
5496 copied to general registers, following their memory order,
5497 because MIPS16 functions don't use float registers for
5498 arguments. This duplication of arguments in general
5499 registers can't hurt non-MIPS16 functions, because those
5500 registers are normally skipped. */
5502 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5503 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5505 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5507 int freg_offset
= gdbarch_byte_order (gdbarch
)
5508 == BFD_ENDIAN_BIG
? 1 : 0;
5509 unsigned long regval
;
5512 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5514 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5515 float_argreg
+ freg_offset
,
5517 regcache_cooked_write_unsigned (regcache
,
5518 float_argreg
++ + freg_offset
,
5521 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5522 argreg
, phex (regval
, 4));
5523 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5526 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5528 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5529 float_argreg
- freg_offset
,
5531 regcache_cooked_write_unsigned (regcache
,
5532 float_argreg
++ - freg_offset
,
5535 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5536 argreg
, phex (regval
, 4));
5537 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5541 /* This is a floating point value that fits entirely
5542 in a single register. */
5543 /* On 32 bit ABI's the float_argreg is further adjusted
5544 above to ensure that it is even register aligned. */
5545 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5547 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5548 float_argreg
, phex (regval
, len
));
5549 regcache_cooked_write_unsigned (regcache
,
5550 float_argreg
++, regval
);
5551 /* Although two FP registers are reserved for each
5552 argument, only one corresponding integer register is
5555 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5556 argreg
, phex (regval
, len
));
5557 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5559 /* Reserve space for the FP register. */
5560 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5564 /* Copy the argument to general registers or the stack in
5565 register-sized pieces. Large arguments are split between
5566 registers and stack. */
5567 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5568 are treated specially: Irix cc passes
5569 them in registers where gcc sometimes puts them on the
5570 stack. For maximum compatibility, we will put them in
5572 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5573 && len
% MIPS32_REGSIZE
!= 0);
5574 /* Structures should be aligned to eight bytes (even arg registers)
5575 on MIPS_ABI_O32, if their first member has double precision. */
5576 if (mips_type_needs_double_align (arg_type
))
5581 stack_offset
+= MIPS32_REGSIZE
;
5586 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5589 gdb_printf (gdb_stdlog
, " -- partial=%d",
5592 /* Write this portion of the argument to the stack. */
5593 if (argreg
> mips_last_arg_regnum (gdbarch
)
5594 || odd_sized_struct
)
5596 /* Should shorter than int integer values be
5597 promoted to int before being stored? */
5598 int longword_offset
= 0;
5603 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5604 paddress (gdbarch
, stack_offset
));
5605 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5606 paddress (gdbarch
, longword_offset
));
5609 addr
= sp
+ stack_offset
+ longword_offset
;
5614 gdb_printf (gdb_stdlog
, " @%s ",
5615 paddress (gdbarch
, addr
));
5616 for (i
= 0; i
< partial_len
; i
++)
5618 gdb_printf (gdb_stdlog
, "%02x",
5622 write_memory (addr
, val
, partial_len
);
5625 /* Note!!! This is NOT an else clause. Odd sized
5626 structs may go thru BOTH paths. */
5627 /* Write this portion of the argument to a general
5628 purpose register. */
5629 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5631 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5633 /* Value may need to be sign extended, because
5634 mips_isa_regsize() != mips_abi_regsize(). */
5636 /* A non-floating-point argument being passed in a
5637 general register. If a struct or union, and if
5638 the remaining length is smaller than the register
5639 size, we have to adjust the register value on
5642 It does not seem to be necessary to do the
5643 same for integral types.
5645 Also don't do this adjustment on O64 binaries.
5647 cagney/2001-07-23: gdb/179: Also, GCC, when
5648 outputting LE O32 with sizeof (struct) <
5649 mips_abi_regsize(), generates a left shift
5650 as part of storing the argument in a register
5651 (the left shift isn't generated when
5652 sizeof (struct) >= mips_abi_regsize()). Since
5653 it is quite possible that this is GCC
5654 contradicting the LE/O32 ABI, GDB has not been
5655 adjusted to accommodate this. Either someone
5656 needs to demonstrate that the LE/O32 ABI
5657 specifies such a left shift OR this new ABI gets
5658 identified as such and GDB gets tweaked
5661 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5662 && partial_len
< MIPS32_REGSIZE
5663 && (typecode
== TYPE_CODE_STRUCT
5664 || typecode
== TYPE_CODE_UNION
))
5665 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5669 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5671 phex (regval
, MIPS32_REGSIZE
));
5672 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5675 /* Prevent subsequent floating point arguments from
5676 being passed in floating point registers. */
5677 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5683 /* Compute the offset into the stack at which we will
5684 copy the next parameter.
5686 In older ABIs, the caller reserved space for
5687 registers that contained arguments. This was loosely
5688 referred to as their "home". Consequently, space is
5689 always allocated. */
5691 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5695 gdb_printf (gdb_stdlog
, "\n");
5698 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5700 /* Return adjusted stack pointer. */
5704 static enum return_value_convention
5705 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5706 struct type
*type
, struct regcache
*regcache
,
5707 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5709 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5710 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5711 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5712 enum mips_fval_reg fval_reg
;
5714 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5715 if (type
->code () == TYPE_CODE_STRUCT
5716 || type
->code () == TYPE_CODE_UNION
5717 || type
->code () == TYPE_CODE_ARRAY
)
5718 return RETURN_VALUE_STRUCT_CONVENTION
;
5719 else if (type
->code () == TYPE_CODE_FLT
5720 && type
->length () == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5722 /* A single-precision floating-point value. If reading in or copying,
5723 then we get it from/put it to FP0 for standard MIPS code or GPR2
5724 for MIPS16 code. If writing out only, then we put it to both FP0
5725 and GPR2. We do not support reading in with no function known, if
5726 this safety check ever triggers, then we'll have to try harder. */
5727 gdb_assert (function
|| !readbuf
);
5732 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5735 gdb_printf (gdb_stderr
, "Return float in $2\n");
5737 case mips_fval_both
:
5738 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
5741 if (fval_reg
!= mips_fval_gpr
)
5742 mips_xfer_register (gdbarch
, regcache
,
5743 (gdbarch_num_regs (gdbarch
)
5744 + mips_regnum (gdbarch
)->fp0
),
5746 gdbarch_byte_order (gdbarch
),
5747 readbuf
, writebuf
, 0);
5748 if (fval_reg
!= mips_fval_fpr
)
5749 mips_xfer_register (gdbarch
, regcache
,
5750 gdbarch_num_regs (gdbarch
) + 2,
5752 gdbarch_byte_order (gdbarch
),
5753 readbuf
, writebuf
, 0);
5754 return RETURN_VALUE_REGISTER_CONVENTION
;
5756 else if (type
->code () == TYPE_CODE_FLT
5757 && type
->length () == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5759 /* A double-precision floating-point value. If reading in or copying,
5760 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5761 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5762 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5763 no function known, if this safety check ever triggers, then we'll
5764 have to try harder. */
5765 gdb_assert (function
|| !readbuf
);
5770 gdb_printf (gdb_stderr
, "Return float in $fp1/$fp0\n");
5773 gdb_printf (gdb_stderr
, "Return float in $2/$3\n");
5775 case mips_fval_both
:
5776 gdb_printf (gdb_stderr
,
5777 "Return float in $fp1/$fp0 and $2/$3\n");
5780 if (fval_reg
!= mips_fval_gpr
)
5782 /* The most significant part goes in FP1, and the least significant
5784 switch (gdbarch_byte_order (gdbarch
))
5786 case BFD_ENDIAN_LITTLE
:
5787 mips_xfer_register (gdbarch
, regcache
,
5788 (gdbarch_num_regs (gdbarch
)
5789 + mips_regnum (gdbarch
)->fp0
+ 0),
5790 4, gdbarch_byte_order (gdbarch
),
5791 readbuf
, writebuf
, 0);
5792 mips_xfer_register (gdbarch
, regcache
,
5793 (gdbarch_num_regs (gdbarch
)
5794 + mips_regnum (gdbarch
)->fp0
+ 1),
5795 4, gdbarch_byte_order (gdbarch
),
5796 readbuf
, writebuf
, 4);
5798 case BFD_ENDIAN_BIG
:
5799 mips_xfer_register (gdbarch
, regcache
,
5800 (gdbarch_num_regs (gdbarch
)
5801 + mips_regnum (gdbarch
)->fp0
+ 1),
5802 4, gdbarch_byte_order (gdbarch
),
5803 readbuf
, writebuf
, 0);
5804 mips_xfer_register (gdbarch
, regcache
,
5805 (gdbarch_num_regs (gdbarch
)
5806 + mips_regnum (gdbarch
)->fp0
+ 0),
5807 4, gdbarch_byte_order (gdbarch
),
5808 readbuf
, writebuf
, 4);
5811 internal_error (_("bad switch"));
5814 if (fval_reg
!= mips_fval_fpr
)
5816 /* The two 32-bit parts are always placed in GPR2 and GPR3
5817 following these registers' memory order. */
5818 mips_xfer_register (gdbarch
, regcache
,
5819 gdbarch_num_regs (gdbarch
) + 2,
5820 4, gdbarch_byte_order (gdbarch
),
5821 readbuf
, writebuf
, 0);
5822 mips_xfer_register (gdbarch
, regcache
,
5823 gdbarch_num_regs (gdbarch
) + 3,
5824 4, gdbarch_byte_order (gdbarch
),
5825 readbuf
, writebuf
, 4);
5827 return RETURN_VALUE_REGISTER_CONVENTION
;
5830 else if (type
->code () == TYPE_CODE_STRUCT
5831 && type
->num_fields () <= 2
5832 && type
->num_fields () >= 1
5833 && ((type
->num_fields () == 1
5834 && (TYPE_CODE (type
->field (0).type ())
5836 || (type
->num_fields () == 2
5837 && (TYPE_CODE (type
->field (0).type ())
5839 && (TYPE_CODE (type
->field (1).type ())
5841 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5843 /* A struct that contains one or two floats. Each value is part
5844 in the least significant part of their floating point
5848 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5849 field
< type
->num_fields (); field
++, regnum
+= 2)
5851 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5853 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5855 mips_xfer_register (gdbarch
, regcache
,
5856 gdbarch_num_regs (gdbarch
) + regnum
,
5857 TYPE_LENGTH (type
->field (field
).type ()),
5858 gdbarch_byte_order (gdbarch
),
5859 readbuf
, writebuf
, offset
);
5861 return RETURN_VALUE_REGISTER_CONVENTION
;
5865 else if (type
->code () == TYPE_CODE_STRUCT
5866 || type
->code () == TYPE_CODE_UNION
)
5868 /* A structure or union. Extract the left justified value,
5869 regardless of the byte order. I.e. DO NOT USE
5873 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5874 offset
< type
->length ();
5875 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5877 int xfer
= register_size (gdbarch
, regnum
);
5878 if (offset
+ xfer
> type
->length ())
5879 xfer
= type
->length () - offset
;
5881 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5882 offset
, xfer
, regnum
);
5883 mips_xfer_register (gdbarch
, regcache
,
5884 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5885 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5887 return RETURN_VALUE_REGISTER_CONVENTION
;
5892 /* A scalar extract each part but least-significant-byte
5893 justified. o32 thinks registers are 4 byte, regardless of
5897 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5898 offset
< type
->length ();
5899 offset
+= MIPS32_REGSIZE
, regnum
++)
5901 int xfer
= MIPS32_REGSIZE
;
5902 if (offset
+ xfer
> type
->length ())
5903 xfer
= type
->length () - offset
;
5905 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5906 offset
, xfer
, regnum
);
5907 mips_xfer_register (gdbarch
, regcache
,
5908 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5909 gdbarch_byte_order (gdbarch
),
5910 readbuf
, writebuf
, offset
);
5912 return RETURN_VALUE_REGISTER_CONVENTION
;
5916 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5920 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5921 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5923 struct value
**args
, CORE_ADDR sp
,
5924 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5930 int stack_offset
= 0;
5931 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5932 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5934 /* For shared libraries, "t9" needs to point at the function
5936 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5938 /* Set the return address register to point to the entry point of
5939 the program, where a breakpoint lies in wait. */
5940 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5942 /* First ensure that the stack and structure return address (if any)
5943 are properly aligned. The stack has to be at least 64-bit
5944 aligned even on 32-bit machines, because doubles must be 64-bit
5945 aligned. For n32 and n64, stack frames need to be 128-bit
5946 aligned, so we round to this widest known alignment. */
5948 sp
= align_down (sp
, 16);
5949 struct_addr
= align_down (struct_addr
, 16);
5951 /* Now make space on the stack for the args. */
5952 for (argnum
= 0; argnum
< nargs
; argnum
++)
5954 struct type
*arg_type
= check_typedef (args
[argnum
]->type ());
5956 /* Allocate space on the stack. */
5957 arg_space
+= align_up (arg_type
->length (), MIPS64_REGSIZE
);
5959 sp
-= align_up (arg_space
, 16);
5962 gdb_printf (gdb_stdlog
,
5963 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5964 paddress (gdbarch
, sp
),
5965 (long) align_up (arg_space
, 16));
5967 /* Initialize the integer and float register pointers. */
5968 argreg
= MIPS_A0_REGNUM
;
5969 float_argreg
= mips_fpa0_regnum (gdbarch
);
5971 /* The struct_return pointer occupies the first parameter-passing reg. */
5972 if (return_method
== return_method_struct
)
5975 gdb_printf (gdb_stdlog
,
5976 "mips_o64_push_dummy_call: "
5977 "struct_return reg=%d %s\n",
5978 argreg
, paddress (gdbarch
, struct_addr
));
5979 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5980 stack_offset
+= MIPS64_REGSIZE
;
5983 /* Now load as many as possible of the first arguments into
5984 registers, and push the rest onto the stack. Loop thru args
5985 from first to last. */
5986 for (argnum
= 0; argnum
< nargs
; argnum
++)
5988 const gdb_byte
*val
;
5989 struct value
*arg
= args
[argnum
];
5990 struct type
*arg_type
= check_typedef (arg
->type ());
5991 int len
= arg_type
->length ();
5992 enum type_code typecode
= arg_type
->code ();
5995 gdb_printf (gdb_stdlog
,
5996 "mips_o64_push_dummy_call: %d len=%d type=%d",
5997 argnum
+ 1, len
, (int) typecode
);
5999 val
= arg
->contents ().data ();
6001 /* Floating point arguments passed in registers have to be
6002 treated specially. On 32-bit architectures, doubles are
6003 passed in register pairs; the even FP register gets the
6004 low word, and the odd FP register gets the high word.
6005 On O64, the first two floating point arguments are also
6006 copied to general registers, because MIPS16 functions
6007 don't use float registers for arguments. This duplication
6008 of arguments in general registers can't hurt non-MIPS16
6009 functions because those registers are normally skipped. */
6011 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
6012 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
6014 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
6016 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
6017 float_argreg
, phex (regval
, len
));
6018 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6020 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6021 argreg
, phex (regval
, len
));
6022 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6024 /* Reserve space for the FP register. */
6025 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6029 /* Copy the argument to general registers or the stack in
6030 register-sized pieces. Large arguments are split between
6031 registers and stack. */
6032 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6033 are treated specially: Irix cc passes them in registers
6034 where gcc sometimes puts them on the stack. For maximum
6035 compatibility, we will put them in both places. */
6036 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6037 && len
% MIPS64_REGSIZE
!= 0);
6040 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6043 gdb_printf (gdb_stdlog
, " -- partial=%d",
6046 /* Write this portion of the argument to the stack. */
6047 if (argreg
> mips_last_arg_regnum (gdbarch
)
6048 || odd_sized_struct
)
6050 /* Should shorter than int integer values be
6051 promoted to int before being stored? */
6052 int longword_offset
= 0;
6054 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6056 if ((typecode
== TYPE_CODE_INT
6057 || typecode
== TYPE_CODE_PTR
6058 || typecode
== TYPE_CODE_FLT
)
6060 longword_offset
= MIPS64_REGSIZE
- len
;
6065 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
6066 paddress (gdbarch
, stack_offset
));
6067 gdb_printf (gdb_stdlog
, " longword_offset=%s",
6068 paddress (gdbarch
, longword_offset
));
6071 addr
= sp
+ stack_offset
+ longword_offset
;
6076 gdb_printf (gdb_stdlog
, " @%s ",
6077 paddress (gdbarch
, addr
));
6078 for (i
= 0; i
< partial_len
; i
++)
6080 gdb_printf (gdb_stdlog
, "%02x",
6084 write_memory (addr
, val
, partial_len
);
6087 /* Note!!! This is NOT an else clause. Odd sized
6088 structs may go thru BOTH paths. */
6089 /* Write this portion of the argument to a general
6090 purpose register. */
6091 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6093 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6095 /* Value may need to be sign extended, because
6096 mips_isa_regsize() != mips_abi_regsize(). */
6098 /* A non-floating-point argument being passed in a
6099 general register. If a struct or union, and if
6100 the remaining length is smaller than the register
6101 size, we have to adjust the register value on
6104 It does not seem to be necessary to do the
6105 same for integral types. */
6107 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6108 && partial_len
< MIPS64_REGSIZE
6109 && (typecode
== TYPE_CODE_STRUCT
6110 || typecode
== TYPE_CODE_UNION
))
6111 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6115 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6117 phex (regval
, MIPS64_REGSIZE
));
6118 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6121 /* Prevent subsequent floating point arguments from
6122 being passed in floating point registers. */
6123 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6129 /* Compute the offset into the stack at which we will
6130 copy the next parameter.
6132 In older ABIs, the caller reserved space for
6133 registers that contained arguments. This was loosely
6134 referred to as their "home". Consequently, space is
6135 always allocated. */
6137 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6141 gdb_printf (gdb_stdlog
, "\n");
6144 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6146 /* Return adjusted stack pointer. */
6150 static enum return_value_convention
6151 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6152 struct type
*type
, struct regcache
*regcache
,
6153 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6155 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6156 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6157 enum mips_fval_reg fval_reg
;
6159 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6160 if (type
->code () == TYPE_CODE_STRUCT
6161 || type
->code () == TYPE_CODE_UNION
6162 || type
->code () == TYPE_CODE_ARRAY
)
6163 return RETURN_VALUE_STRUCT_CONVENTION
;
6164 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6166 /* A floating-point value. If reading in or copying, then we get it
6167 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6168 If writing out only, then we put it to both FP0 and GPR2. We do
6169 not support reading in with no function known, if this safety
6170 check ever triggers, then we'll have to try harder. */
6171 gdb_assert (function
|| !readbuf
);
6176 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
6179 gdb_printf (gdb_stderr
, "Return float in $2\n");
6181 case mips_fval_both
:
6182 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
6185 if (fval_reg
!= mips_fval_gpr
)
6186 mips_xfer_register (gdbarch
, regcache
,
6187 (gdbarch_num_regs (gdbarch
)
6188 + mips_regnum (gdbarch
)->fp0
),
6190 gdbarch_byte_order (gdbarch
),
6191 readbuf
, writebuf
, 0);
6192 if (fval_reg
!= mips_fval_fpr
)
6193 mips_xfer_register (gdbarch
, regcache
,
6194 gdbarch_num_regs (gdbarch
) + 2,
6196 gdbarch_byte_order (gdbarch
),
6197 readbuf
, writebuf
, 0);
6198 return RETURN_VALUE_REGISTER_CONVENTION
;
6202 /* A scalar extract each part but least-significant-byte
6206 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6207 offset
< type
->length ();
6208 offset
+= MIPS64_REGSIZE
, regnum
++)
6210 int xfer
= MIPS64_REGSIZE
;
6211 if (offset
+ xfer
> type
->length ())
6212 xfer
= type
->length () - offset
;
6214 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6215 offset
, xfer
, regnum
);
6216 mips_xfer_register (gdbarch
, regcache
,
6217 gdbarch_num_regs (gdbarch
) + regnum
,
6218 xfer
, gdbarch_byte_order (gdbarch
),
6219 readbuf
, writebuf
, offset
);
6221 return RETURN_VALUE_REGISTER_CONVENTION
;
6225 /* Floating point register management.
6227 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6228 64bit operations, these early MIPS cpus treat fp register pairs
6229 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6230 registers and offer a compatibility mode that emulates the MIPS2 fp
6231 model. When operating in MIPS2 fp compat mode, later cpu's split
6232 double precision floats into two 32-bit chunks and store them in
6233 consecutive fp regs. To display 64-bit floats stored in this
6234 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6235 Throw in user-configurable endianness and you have a real mess.
6237 The way this works is:
6238 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6239 double-precision value will be split across two logical registers.
6240 The lower-numbered logical register will hold the low-order bits,
6241 regardless of the processor's endianness.
6242 - If we are on a 64-bit processor, and we are looking for a
6243 single-precision value, it will be in the low ordered bits
6244 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6245 save slot in memory.
6246 - If we are in 64-bit mode, everything is straightforward.
6248 Note that this code only deals with "live" registers at the top of the
6249 stack. We will attempt to deal with saved registers later, when
6250 the raw/cooked register interface is in place. (We need a general
6251 interface that can deal with dynamic saved register sizes -- fp
6252 regs could be 32 bits wide in one frame and 64 on the frame above
6255 /* Copy a 32-bit single-precision value from the current frame
6256 into rare_buffer. */
6259 mips_read_fp_register_single (frame_info_ptr frame
, int regno
,
6260 gdb_byte
*rare_buffer
)
6262 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6263 int raw_size
= register_size (gdbarch
, regno
);
6264 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6266 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6267 error (_("can't read register %d (%s)"),
6268 regno
, gdbarch_register_name (gdbarch
, regno
));
6271 /* We have a 64-bit value for this register. Find the low-order
6275 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6280 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6284 memcpy (rare_buffer
, raw_buffer
, 4);
6288 /* Copy a 64-bit double-precision value from the current frame into
6289 rare_buffer. This may include getting half of it from the next
6293 mips_read_fp_register_double (frame_info_ptr frame
, int regno
,
6294 gdb_byte
*rare_buffer
)
6296 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6297 int raw_size
= register_size (gdbarch
, regno
);
6299 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6301 /* We have a 64-bit value for this register, and we should use
6303 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6304 error (_("can't read register %d (%s)"),
6305 regno
, gdbarch_register_name (gdbarch
, regno
));
6309 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6311 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6312 internal_error (_("mips_read_fp_register_double: bad access to "
6313 "odd-numbered FP register"));
6315 /* mips_read_fp_register_single will find the correct 32 bits from
6317 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6319 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6320 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6324 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6325 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6331 mips_print_fp_register (struct ui_file
*file
, frame_info_ptr frame
,
6333 { /* Do values for FP (float) regs. */
6334 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6335 gdb_byte
*raw_buffer
;
6336 std::string flt_str
, dbl_str
;
6338 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6339 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6343 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6345 gdb_printf (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6346 gdb_printf (file
, "%*s",
6347 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6350 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6352 struct value_print_options opts
;
6354 /* 4-byte registers: Print hex and floating. Also print even
6355 numbered registers as doubles. */
6356 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6357 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6359 get_formatted_print_options (&opts
, 'x');
6360 print_scalar_formatted (raw_buffer
,
6361 builtin_type (gdbarch
)->builtin_uint32
,
6364 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6366 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6368 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6369 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6371 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6376 struct value_print_options opts
;
6378 /* Eight byte registers: print each one as hex, float and double. */
6379 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6380 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6382 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6383 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6385 get_formatted_print_options (&opts
, 'x');
6386 print_scalar_formatted (raw_buffer
,
6387 builtin_type (gdbarch
)->builtin_uint64
,
6390 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6391 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6396 mips_print_register (struct ui_file
*file
, frame_info_ptr frame
,
6399 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6400 struct value_print_options opts
;
6403 if (mips_float_register_p (gdbarch
, regnum
))
6405 mips_print_fp_register (file
, frame
, regnum
);
6409 val
= get_frame_register_value (frame
, regnum
);
6411 gdb_puts (gdbarch_register_name (gdbarch
, regnum
), file
);
6413 /* The problem with printing numeric register names (r26, etc.) is that
6414 the user can't use them on input. Probably the best solution is to
6415 fix it so that either the numeric or the funky (a2, etc.) names
6416 are accepted on input. */
6417 if (regnum
< MIPS_NUMREGS
)
6418 gdb_printf (file
, "(r%d): ", regnum
);
6420 gdb_printf (file
, ": ");
6422 get_formatted_print_options (&opts
, 'x');
6423 value_print_scalar_formatted (val
, &opts
, 0, file
);
6426 /* Print IEEE exception condition bits in FLAGS. */
6429 print_fpu_flags (struct ui_file
*file
, int flags
)
6431 if (flags
& (1 << 0))
6432 gdb_puts (" inexact", file
);
6433 if (flags
& (1 << 1))
6434 gdb_puts (" uflow", file
);
6435 if (flags
& (1 << 2))
6436 gdb_puts (" oflow", file
);
6437 if (flags
& (1 << 3))
6438 gdb_puts (" div0", file
);
6439 if (flags
& (1 << 4))
6440 gdb_puts (" inval", file
);
6441 if (flags
& (1 << 5))
6442 gdb_puts (" unimp", file
);
6443 gdb_putc ('\n', file
);
6446 /* Print interesting information about the floating point processor
6447 (if present) or emulator. */
6450 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6451 frame_info_ptr frame
, const char *args
)
6453 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6454 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6458 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6459 type
= MIPS_FPU_NONE
;
6461 gdb_printf (file
, "fpu type: %s\n",
6462 type
== MIPS_FPU_DOUBLE
? "double-precision"
6463 : type
== MIPS_FPU_SINGLE
? "single-precision"
6466 if (type
== MIPS_FPU_NONE
)
6469 gdb_printf (file
, "reg size: %d bits\n",
6470 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6472 gdb_puts ("cond :", file
);
6473 if (fcs
& (1 << 23))
6474 gdb_puts (" 0", file
);
6475 for (i
= 1; i
<= 7; i
++)
6476 if (fcs
& (1 << (24 + i
)))
6477 gdb_printf (file
, " %d", i
);
6478 gdb_putc ('\n', file
);
6480 gdb_puts ("cause :", file
);
6481 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6482 fputs ("mask :", stdout
);
6483 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6484 fputs ("flags :", stdout
);
6485 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6487 gdb_puts ("rounding: ", file
);
6490 case 0: gdb_puts ("nearest\n", file
); break;
6491 case 1: gdb_puts ("zero\n", file
); break;
6492 case 2: gdb_puts ("+inf\n", file
); break;
6493 case 3: gdb_puts ("-inf\n", file
); break;
6496 gdb_puts ("flush :", file
);
6497 if (fcs
& (1 << 21))
6498 gdb_puts (" nearest", file
);
6499 if (fcs
& (1 << 22))
6500 gdb_puts (" override", file
);
6501 if (fcs
& (1 << 24))
6502 gdb_puts (" zero", file
);
6503 if ((fcs
& (0xb << 21)) == 0)
6504 gdb_puts (" no", file
);
6505 gdb_putc ('\n', file
);
6507 gdb_printf (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6508 gdb_printf (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6509 gdb_putc ('\n', file
);
6511 default_print_float_info (gdbarch
, file
, frame
, args
);
6514 /* Replacement for generic do_registers_info.
6515 Print regs in pretty columns. */
6518 print_fp_register_row (struct ui_file
*file
, frame_info_ptr frame
,
6521 gdb_printf (file
, " ");
6522 mips_print_fp_register (file
, frame
, regnum
);
6523 gdb_printf (file
, "\n");
6528 /* Print a row's worth of GP (int) registers, with name labels above. */
6531 print_gp_register_row (struct ui_file
*file
, frame_info_ptr frame
,
6534 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6535 /* Do values for GP (int) regs. */
6536 const gdb_byte
*raw_buffer
;
6537 struct value
*value
;
6538 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6543 /* For GP registers, we print a separate row of names above the vals. */
6544 for (col
= 0, regnum
= start_regnum
;
6545 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6548 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6549 continue; /* unused register */
6550 if (mips_float_register_p (gdbarch
, regnum
))
6551 break; /* End the row: reached FP register. */
6552 /* Large registers are handled separately. */
6553 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6556 break; /* End the row before this register. */
6558 /* Print this register on a row by itself. */
6559 mips_print_register (file
, frame
, regnum
);
6560 gdb_printf (file
, "\n");
6564 gdb_printf (file
, " ");
6566 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6567 gdbarch_register_name (gdbarch
, regnum
));
6574 /* Print the R0 to R31 names. */
6575 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6576 gdb_printf (file
, "\n R%-4d",
6577 start_regnum
% gdbarch_num_regs (gdbarch
));
6579 gdb_printf (file
, "\n ");
6581 /* Now print the values in hex, 4 or 8 to the row. */
6582 for (col
= 0, regnum
= start_regnum
;
6583 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6586 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6587 continue; /* unused register */
6588 if (mips_float_register_p (gdbarch
, regnum
))
6589 break; /* End row: reached FP register. */
6590 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6591 break; /* End row: large register. */
6593 /* OK: get the data in raw format. */
6594 value
= get_frame_register_value (frame
, regnum
);
6595 if (value
->optimized_out ()
6596 || !value
->entirely_available ())
6598 gdb_printf (file
, "%*s ",
6599 (int) mips_abi_regsize (gdbarch
) * 2,
6600 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6601 : "<unavailable>"));
6605 raw_buffer
= value
->contents_all ().data ();
6606 /* pad small registers */
6608 byte
< (mips_abi_regsize (gdbarch
)
6609 - register_size (gdbarch
, regnum
)); byte
++)
6610 gdb_printf (file
, " ");
6611 /* Now print the register value in hex, endian order. */
6612 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6614 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6615 byte
< register_size (gdbarch
, regnum
); byte
++)
6616 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6618 for (byte
= register_size (gdbarch
, regnum
) - 1;
6620 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6621 gdb_printf (file
, " ");
6624 if (col
> 0) /* ie. if we actually printed anything... */
6625 gdb_printf (file
, "\n");
6630 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6633 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6634 frame_info_ptr frame
, int regnum
, int all
)
6636 if (regnum
!= -1) /* Do one specified register. */
6638 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6639 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6640 error (_("Not a valid register for the current processor type"));
6642 mips_print_register (file
, frame
, regnum
);
6643 gdb_printf (file
, "\n");
6646 /* Do all (or most) registers. */
6648 regnum
= gdbarch_num_regs (gdbarch
);
6649 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6651 if (mips_float_register_p (gdbarch
, regnum
))
6653 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6654 regnum
= print_fp_register_row (file
, frame
, regnum
);
6656 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6659 regnum
= print_gp_register_row (file
, frame
, regnum
);
6665 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6666 frame_info_ptr frame
)
6668 CORE_ADDR pc
= get_frame_pc (frame
);
6673 if ((mips_pc_is_mips (pc
)
6674 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6675 || (mips_pc_is_micromips (gdbarch
, pc
)
6676 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6677 || (mips_pc_is_mips16 (gdbarch
, pc
)
6678 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6681 isa
= mips_pc_isa (gdbarch
, pc
);
6682 /* _has_delay_slot above will have validated the read. */
6683 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6684 size
= mips_insn_size (isa
, insn
);
6686 const address_space
*aspace
= get_frame_address_space (frame
);
6688 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6691 /* To skip prologues, I use this predicate. Returns either PC itself
6692 if the code at PC does not look like a function prologue; otherwise
6693 returns an address that (if we're lucky) follows the prologue. If
6694 LENIENT, then we must skip everything which is involved in setting
6695 up the frame (it's OK to skip more, just so long as we don't skip
6696 anything which might clobber the registers which are being saved.
6697 We must skip more in the case where part of the prologue is in the
6698 delay slot of a non-prologue instruction). */
6701 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6704 CORE_ADDR func_addr
;
6706 /* See if we can determine the end of the prologue via the symbol table.
6707 If so, then return either PC, or the PC after the prologue, whichever
6709 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6711 CORE_ADDR post_prologue_pc
6712 = skip_prologue_using_sal (gdbarch
, func_addr
);
6713 if (post_prologue_pc
!= 0)
6714 return std::max (pc
, post_prologue_pc
);
6717 /* Can't determine prologue from the symbol table, need to examine
6720 /* Find an upper limit on the function prologue using the debug
6721 information. If the debug information could not be used to provide
6722 that bound, then use an arbitrary large number as the upper bound. */
6723 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6725 limit_pc
= pc
+ 100; /* Magic. */
6727 if (mips_pc_is_mips16 (gdbarch
, pc
))
6728 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6729 else if (mips_pc_is_micromips (gdbarch
, pc
))
6730 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6732 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6735 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6736 This is a helper function for mips_stack_frame_destroyed_p. */
6739 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6741 CORE_ADDR func_addr
= 0, func_end
= 0;
6743 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6745 /* The MIPS epilogue is max. 12 bytes long. */
6746 CORE_ADDR addr
= func_end
- 12;
6748 if (addr
< func_addr
+ 4)
6749 addr
= func_addr
+ 4;
6753 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6755 unsigned long high_word
;
6758 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6759 high_word
= (inst
>> 16) & 0xffff;
6761 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6762 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6763 && inst
!= 0x03e00008 /* jr $ra */
6764 && inst
!= 0x00000000) /* nop */
6774 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6775 This is a helper function for mips_stack_frame_destroyed_p. */
6778 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6780 CORE_ADDR func_addr
= 0;
6781 CORE_ADDR func_end
= 0;
6789 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6792 /* The microMIPS epilogue is max. 12 bytes long. */
6793 addr
= func_end
- 12;
6795 if (addr
< func_addr
+ 2)
6796 addr
= func_addr
+ 2;
6800 for (; pc
< func_end
; pc
+= loc
)
6803 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6804 loc
+= MIPS_INSN16_SIZE
;
6805 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6807 /* 32-bit instructions. */
6808 case 2 * MIPS_INSN16_SIZE
:
6810 insn
|= mips_fetch_instruction (gdbarch
,
6811 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6812 loc
+= MIPS_INSN16_SIZE
;
6813 switch (micromips_op (insn
>> 16))
6815 case 0xc: /* ADDIU: bits 001100 */
6816 case 0x17: /* DADDIU: bits 010111 */
6817 sreg
= b0s5_reg (insn
>> 16);
6818 dreg
= b5s5_reg (insn
>> 16);
6819 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6820 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6821 /* (D)ADDIU $sp, imm */
6831 /* 16-bit instructions. */
6832 case MIPS_INSN16_SIZE
:
6833 switch (micromips_op (insn
))
6835 case 0x3: /* MOVE: bits 000011 */
6836 sreg
= b0s5_reg (insn
);
6837 dreg
= b5s5_reg (insn
);
6838 if (sreg
== 0 && dreg
== 0)
6839 /* MOVE $zero, $zero aka NOP */
6843 case 0x11: /* POOL16C: bits 010001 */
6844 if (b5s5_op (insn
) == 0x18
6845 /* JRADDIUSP: bits 010011 11000 */
6846 || (b5s5_op (insn
) == 0xd
6847 /* JRC: bits 010011 01101 */
6848 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6853 case 0x13: /* POOL16D: bits 010011 */
6854 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6855 if ((insn
& 0x1) == 0x1
6856 /* ADDIUSP: bits 010011 1 */
6870 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6871 This is a helper function for mips_stack_frame_destroyed_p. */
6874 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6876 CORE_ADDR func_addr
= 0, func_end
= 0;
6878 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6880 /* The MIPS epilogue is max. 12 bytes long. */
6881 CORE_ADDR addr
= func_end
- 12;
6883 if (addr
< func_addr
+ 4)
6884 addr
= func_addr
+ 4;
6888 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6890 unsigned short inst
;
6892 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6894 if ((inst
& 0xf800) == 0xf000) /* extend */
6897 if (inst
!= 0x6300 /* addiu $sp,offset */
6898 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6899 && inst
!= 0xe820 /* jr $ra */
6900 && inst
!= 0xe8a0 /* jrc $ra */
6901 && inst
!= 0x6500) /* nop */
6911 /* Implement the stack_frame_destroyed_p gdbarch method.
6913 The epilogue is defined here as the area at the end of a function,
6914 after an instruction which destroys the function's stack frame. */
6917 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6919 if (mips_pc_is_mips16 (gdbarch
, pc
))
6920 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6921 else if (mips_pc_is_micromips (gdbarch
, pc
))
6922 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6924 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6927 /* Commands to show/set the MIPS FPU type. */
6930 show_mipsfpu_command (const char *args
, int from_tty
)
6934 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
6938 ("The MIPS floating-point coprocessor is unknown "
6939 "because the current architecture is not MIPS.\n");
6943 switch (mips_get_fpu_type (current_inferior ()->arch ()))
6945 case MIPS_FPU_SINGLE
:
6946 fpu
= "single-precision";
6948 case MIPS_FPU_DOUBLE
:
6949 fpu
= "double-precision";
6952 fpu
= "absent (none)";
6955 internal_error (_("bad switch"));
6957 if (mips_fpu_type_auto
)
6958 gdb_printf ("The MIPS floating-point coprocessor "
6959 "is set automatically (currently %s)\n",
6963 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6968 set_mipsfpu_single_command (const char *args
, int from_tty
)
6970 struct gdbarch_info info
;
6971 mips_fpu_type
= MIPS_FPU_SINGLE
;
6972 mips_fpu_type_auto
= 0;
6973 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6974 instead of relying on globals. Doing that would let generic code
6975 handle the search for this specific architecture. */
6976 if (!gdbarch_update_p (info
))
6977 internal_error (_("set mipsfpu failed"));
6981 set_mipsfpu_double_command (const char *args
, int from_tty
)
6983 struct gdbarch_info info
;
6984 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6985 mips_fpu_type_auto
= 0;
6986 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6987 instead of relying on globals. Doing that would let generic code
6988 handle the search for this specific architecture. */
6989 if (!gdbarch_update_p (info
))
6990 internal_error (_("set mipsfpu failed"));
6994 set_mipsfpu_none_command (const char *args
, int from_tty
)
6996 struct gdbarch_info info
;
6997 mips_fpu_type
= MIPS_FPU_NONE
;
6998 mips_fpu_type_auto
= 0;
6999 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
7000 instead of relying on globals. Doing that would let generic code
7001 handle the search for this specific architecture. */
7002 if (!gdbarch_update_p (info
))
7003 internal_error (_("set mipsfpu failed"));
7007 set_mipsfpu_auto_command (const char *args
, int from_tty
)
7009 mips_fpu_type_auto
= 1;
7012 /* Just like reinit_frame_cache, but with the right arguments to be
7013 callable as an sfunc. */
7016 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
7017 struct cmd_list_element
*c
)
7019 reinit_frame_cache ();
7023 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7025 gdb_disassemble_info
*di
7026 = static_cast<gdb_disassemble_info
*> (info
->application_data
);
7027 struct gdbarch
*gdbarch
= di
->arch ();
7029 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7030 disassembler needs to be able to locally determine the ISA, and
7031 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7033 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7034 info
->mach
= bfd_mach_mips16
;
7035 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7036 info
->mach
= bfd_mach_mips_micromips
;
7038 /* Round down the instruction address to the appropriate boundary. */
7039 memaddr
&= (info
->mach
== bfd_mach_mips16
7040 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7042 return default_print_insn (memaddr
, info
);
7045 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7048 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7050 CORE_ADDR pc
= *pcptr
;
7052 if (mips_pc_is_mips16 (gdbarch
, pc
))
7054 *pcptr
= unmake_compact_addr (pc
);
7055 return MIPS_BP_KIND_MIPS16
;
7057 else if (mips_pc_is_micromips (gdbarch
, pc
))
7062 *pcptr
= unmake_compact_addr (pc
);
7063 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7064 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7065 return MIPS_BP_KIND_MICROMIPS16
;
7067 return MIPS_BP_KIND_MICROMIPS32
;
7070 return MIPS_BP_KIND_MIPS32
;
7073 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7075 static const gdb_byte
*
7076 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7078 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7082 case MIPS_BP_KIND_MIPS16
:
7084 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7085 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7088 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7089 return mips16_big_breakpoint
;
7091 return mips16_little_breakpoint
;
7093 case MIPS_BP_KIND_MICROMIPS16
:
7095 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7096 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7100 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7101 return micromips16_big_breakpoint
;
7103 return micromips16_little_breakpoint
;
7105 case MIPS_BP_KIND_MICROMIPS32
:
7107 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7108 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7111 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7112 return micromips32_big_breakpoint
;
7114 return micromips32_little_breakpoint
;
7116 case MIPS_BP_KIND_MIPS32
:
7118 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7119 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7122 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7123 return big_breakpoint
;
7125 return little_breakpoint
;
7128 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7132 /* Return non-zero if the standard MIPS instruction INST has a branch
7133 delay slot (i.e. it is a jump or branch instruction). This function
7134 is based on mips32_next_pc. */
7137 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7143 op
= itype_op (inst
);
7144 if ((inst
& 0xe0000000) != 0)
7146 rs
= itype_rs (inst
);
7147 rt
= itype_rt (inst
);
7148 return (is_octeon_bbit_op (op
, gdbarch
)
7149 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7150 || op
== 29 /* JALX: bits 011101 */
7153 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7154 || (rs
== 9 && (rt
& 0x2) == 0)
7155 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7156 || (rs
== 10 && (rt
& 0x2) == 0))));
7157 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7160 switch (op
& 0x07) /* extract bits 28,27,26 */
7162 case 0: /* SPECIAL */
7163 op
= rtype_funct (inst
);
7164 return (op
== 8 /* JR */
7165 || op
== 9); /* JALR */
7166 break; /* end SPECIAL */
7167 case 1: /* REGIMM */
7168 rs
= itype_rs (inst
);
7169 rt
= itype_rt (inst
); /* branch condition */
7170 return ((rt
& 0xc) == 0
7171 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7172 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7173 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7174 /* BPOSGE32, BPOSGE64: bits 1110x */
7175 break; /* end REGIMM */
7176 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7182 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7183 delay slot (i.e. it is a jump or branch instruction). */
7186 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7191 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7195 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7198 /* Return non-zero if the microMIPS instruction INSN, comprising the
7199 16-bit major opcode word in the high 16 bits and any second word
7200 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7201 jump or branch instruction). The instruction must be 32-bit if
7202 MUSTBE32 is set or can be any instruction otherwise. */
7205 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7207 ULONGEST major
= insn
>> 16;
7209 switch (micromips_op (major
))
7211 /* 16-bit instructions. */
7212 case 0x33: /* B16: bits 110011 */
7213 case 0x2b: /* BNEZ16: bits 101011 */
7214 case 0x23: /* BEQZ16: bits 100011 */
7216 case 0x11: /* POOL16C: bits 010001 */
7218 && ((b5s5_op (major
) == 0xc
7219 /* JR16: bits 010001 01100 */
7220 || (b5s5_op (major
) & 0x1e) == 0xe)));
7221 /* JALR16, JALRS16: bits 010001 0111x */
7222 /* 32-bit instructions. */
7223 case 0x3d: /* JAL: bits 111101 */
7224 case 0x3c: /* JALX: bits 111100 */
7225 case 0x35: /* J: bits 110101 */
7226 case 0x2d: /* BNE: bits 101101 */
7227 case 0x25: /* BEQ: bits 100101 */
7228 case 0x1d: /* JALS: bits 011101 */
7230 case 0x10: /* POOL32I: bits 010000 */
7231 return ((b5s5_op (major
) & 0x1c) == 0x0
7232 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7233 || (b5s5_op (major
) & 0x1d) == 0x4
7234 /* BLEZ, BGTZ: bits 010000 001x0 */
7235 || (b5s5_op (major
) & 0x1d) == 0x11
7236 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7237 || ((b5s5_op (major
) & 0x1e) == 0x14
7238 && (major
& 0x3) == 0x0)
7239 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7240 || (b5s5_op (major
) & 0x1e) == 0x1a
7241 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7242 || ((b5s5_op (major
) & 0x1e) == 0x1c
7243 && (major
& 0x3) == 0x0)
7244 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7245 || ((b5s5_op (major
) & 0x1c) == 0x1c
7246 && (major
& 0x3) == 0x1));
7247 /* BC1ANY*: bits 010000 111xx xxx01 */
7248 case 0x0: /* POOL32A: bits 000000 */
7249 return (b0s6_op (insn
) == 0x3c
7250 /* POOL32Axf: bits 000000 ... 111100 */
7251 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7252 /* JALR, JALR.HB: 000000 000x111100 111100 */
7253 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7259 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7260 slot (i.e. it is a non-compact jump instruction). The instruction
7261 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7264 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7265 CORE_ADDR addr
, int mustbe32
)
7271 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7274 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7276 if (size
== 2 * MIPS_INSN16_SIZE
)
7278 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7283 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7286 /* Return non-zero if the MIPS16 instruction INST, which must be
7287 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7288 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7289 instruction). This function is based on mips16_next_pc. */
7292 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7294 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7296 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7299 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7300 slot (i.e. it is a non-compact jump instruction). The instruction
7301 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7304 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7305 CORE_ADDR addr
, int mustbe32
)
7307 unsigned short insn
;
7310 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7314 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7317 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7318 This assumes KSSEG exists. */
7321 mips_segment_boundary (CORE_ADDR bpaddr
)
7323 CORE_ADDR mask
= CORE_ADDR_MAX
;
7326 if (sizeof (CORE_ADDR
) == 8)
7327 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7328 a compiler warning produced where CORE_ADDR is a 32-bit type even
7329 though in that case this is dead code). */
7330 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7333 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7334 segsize
= 29; /* 32-bit compatibility segment */
7336 segsize
= 62; /* xkseg */
7338 case 2: /* xkphys */
7341 default: /* xksseg (1), xkuseg/kuseg (0) */
7345 else if (bpaddr
& 0x80000000) /* kernel segment */
7348 segsize
= 31; /* user segment */
7350 return bpaddr
& mask
;
7353 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7354 it backwards if necessary. Return the address of the new location. */
7357 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7359 CORE_ADDR prev_addr
;
7361 CORE_ADDR func_addr
;
7363 /* If a breakpoint is set on the instruction in a branch delay slot,
7364 GDB gets confused. When the breakpoint is hit, the PC isn't on
7365 the instruction in the branch delay slot, the PC will point to
7366 the branch instruction. Since the PC doesn't match any known
7367 breakpoints, GDB reports a trap exception.
7369 There are two possible fixes for this problem.
7371 1) When the breakpoint gets hit, see if the BD bit is set in the
7372 Cause register (which indicates the last exception occurred in a
7373 branch delay slot). If the BD bit is set, fix the PC to point to
7374 the instruction in the branch delay slot.
7376 2) When the user sets the breakpoint, don't allow him to set the
7377 breakpoint on the instruction in the branch delay slot. Instead
7378 move the breakpoint to the branch instruction (which will have
7381 The problem with the first solution is that if the user then
7382 single-steps the processor, the branch instruction will get
7383 skipped (since GDB thinks the PC is on the instruction in the
7386 So, we'll use the second solution. To do this we need to know if
7387 the instruction we're trying to set the breakpoint on is in the
7388 branch delay slot. */
7390 boundary
= mips_segment_boundary (bpaddr
);
7392 /* Make sure we don't scan back before the beginning of the current
7393 function, since we may fetch constant data or insns that look like
7394 a jump. Of course we might do that anyway if the compiler has
7395 moved constants inline. :-( */
7396 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7397 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7398 boundary
= func_addr
;
7400 if (mips_pc_is_mips (bpaddr
))
7402 if (bpaddr
== boundary
)
7405 /* If the previous instruction has a branch delay slot, we have
7406 to move the breakpoint to the branch instruction. */
7407 prev_addr
= bpaddr
- 4;
7408 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7413 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7414 CORE_ADDR addr
, jmpaddr
;
7417 boundary
= unmake_compact_addr (boundary
);
7419 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7420 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7421 so try for that first, then try the 2 byte JALR/JR.
7422 The microMIPS ASE has a whole range of jumps and branches
7423 with delay slots, some of which take 4 bytes and some take
7424 2 bytes, so the idea is the same.
7425 FIXME: We have to assume that bpaddr is not the second half
7426 of an extended instruction. */
7427 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7428 ? micromips_insn_at_pc_has_delay_slot
7429 : mips16_insn_at_pc_has_delay_slot
);
7433 for (i
= 1; i
< 4; i
++)
7435 if (unmake_compact_addr (addr
) == boundary
)
7437 addr
-= MIPS_INSN16_SIZE
;
7438 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7439 /* Looks like a JR/JALR at [target-1], but it could be
7440 the second word of a previous JAL/JALX, so record it
7441 and check back one more. */
7443 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7446 /* Looks like a JAL/JALX at [target-2], but it could also
7447 be the second word of a previous JAL/JALX, record it,
7448 and check back one more. */
7451 /* Looks like a JAL/JALX at [target-3], so any previously
7452 recorded JAL/JALX or JR/JALR must be wrong, because:
7455 -2: JAL-ext (can't be JAL/JALX)
7456 -1: bdslot (can't be JR/JALR)
7459 Of course it could be another JAL-ext which looks
7460 like a JAL, but in that case we'd have broken out
7461 of this loop at [target-2]:
7465 -2: bdslot (can't be jmp)
7472 /* Not a jump instruction: if we're at [target-1] this
7473 could be the second word of a JAL/JALX, so continue;
7474 otherwise we're done. */
7487 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7488 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7491 mips_is_stub_suffix (const char *suffix
, int zero
)
7496 return zero
&& suffix
[1] == '\0';
7498 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7503 return suffix
[1] == '\0';
7509 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7510 call stubs, one of sf, df, sc, or dc. */
7513 mips_is_stub_mode (const char *mode
)
7515 return ((mode
[0] == 's' || mode
[0] == 'd')
7516 && (mode
[1] == 'f' || mode
[1] == 'c'));
7519 /* Code at PC is a compiler-generated stub. Such a stub for a function
7520 bar might have a name like __fn_stub_bar, and might look like this:
7527 followed by (or interspersed with):
7534 addiu $25, $25, %lo(bar)
7537 ($1 may be used in old code; for robustness we accept any register)
7540 lui $28, %hi(_gp_disp)
7541 addiu $28, $28, %lo(_gp_disp)
7544 addiu $25, $25, %lo(bar)
7547 In the case of a __call_stub_bar stub, the sequence to set up
7548 arguments might look like this:
7555 followed by (or interspersed with) one of the jump sequences above.
7557 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7558 of J or JR, respectively, followed by:
7564 We are at the beginning of the stub here, and scan down and extract
7565 the target address from the jump immediate instruction or, if a jump
7566 register instruction is used, from the register referred. Return
7567 the value of PC calculated or 0 if inconclusive.
7569 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7572 mips_get_mips16_fn_stub_pc (frame_info_ptr frame
, CORE_ADDR pc
)
7574 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7575 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7576 int addrreg
= MIPS_ZERO_REGNUM
;
7577 CORE_ADDR start_pc
= pc
;
7578 CORE_ADDR target_pc
= 0;
7585 status
== 0 && target_pc
== 0 && i
< 20;
7586 i
++, pc
+= MIPS_INSN32_SIZE
)
7588 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7594 switch (itype_op (inst
))
7596 case 0: /* SPECIAL */
7597 switch (rtype_funct (inst
))
7601 rs
= rtype_rs (inst
);
7602 if (rs
== MIPS_GP_REGNUM
)
7603 target_pc
= gp
; /* Hmm... */
7604 else if (rs
== addrreg
)
7608 case 0x21: /* ADDU */
7609 rt
= rtype_rt (inst
);
7610 rs
= rtype_rs (inst
);
7611 rd
= rtype_rd (inst
);
7612 if (rd
== MIPS_GP_REGNUM
7613 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7614 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7622 target_pc
= jtype_target (inst
) << 2;
7623 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7627 rt
= itype_rt (inst
);
7628 rs
= itype_rs (inst
);
7631 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7632 if (rt
== MIPS_GP_REGNUM
)
7634 else if (rt
== addrreg
)
7640 rt
= itype_rt (inst
);
7641 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7642 if (rt
== MIPS_GP_REGNUM
)
7644 else if (rt
!= MIPS_ZERO_REGNUM
)
7652 rt
= itype_rt (inst
);
7653 rs
= itype_rs (inst
);
7654 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7655 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7659 memset (buf
, 0, sizeof (buf
));
7660 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7662 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7671 /* If PC is in a MIPS16 call or return stub, return the address of the
7672 target PC, which is either the callee or the caller. There are several
7673 cases which must be handled:
7675 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7676 and the target PC is in $31 ($ra).
7677 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7678 and the target PC is in $2.
7679 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7680 i.e. before the JALR instruction, this is effectively a call stub
7681 and the target PC is in $2. Otherwise this is effectively
7682 a return stub and the target PC is in $18.
7683 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7684 JAL or JALR instruction, this is effectively a call stub and the
7685 target PC is buried in the instruction stream. Otherwise this
7686 is effectively a return stub and the target PC is in $18.
7687 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7688 stub and the target PC is buried in the instruction stream.
7690 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7691 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7695 mips_skip_mips16_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7697 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7698 CORE_ADDR start_addr
;
7702 /* Find the starting address and name of the function containing the PC. */
7703 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7706 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7707 and the target PC is in $31 ($ra). */
7708 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7709 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7710 && mips_is_stub_mode (name
+ prefixlen
)
7711 && name
[prefixlen
+ 2] == '\0')
7712 return get_frame_register_signed
7713 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7715 /* If the PC is in __mips16_call_stub_*, this is one of the call
7716 call/return stubs. */
7717 prefixlen
= strlen (mips_str_mips16_call_stub
);
7718 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7720 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7721 and the target PC is in $2. */
7722 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7723 return get_frame_register_signed
7724 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7726 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7727 i.e. before the JALR instruction, this is effectively a call stub
7728 and the target PC is in $2. Otherwise this is effectively
7729 a return stub and the target PC is in $18. */
7730 else if (mips_is_stub_mode (name
+ prefixlen
)
7731 && name
[prefixlen
+ 2] == '_'
7732 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7734 if (pc
== start_addr
)
7735 /* This is the 'call' part of a call stub. The return
7736 address is in $2. */
7737 return get_frame_register_signed
7738 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7740 /* This is the 'return' part of a call stub. The return
7741 address is in $18. */
7742 return get_frame_register_signed
7743 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7746 return 0; /* Not a stub. */
7749 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7750 compiler-generated call or call/return stubs. */
7751 if (startswith (name
, mips_str_fn_stub
)
7752 || startswith (name
, mips_str_call_stub
))
7754 if (pc
== start_addr
)
7755 /* This is the 'call' part of a call stub. Call this helper
7756 to scan through this code for interesting instructions
7757 and determine the final PC. */
7758 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7760 /* This is the 'return' part of a call stub. The return address
7762 return get_frame_register_signed
7763 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7766 return 0; /* Not a stub. */
7769 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7770 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7773 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7775 CORE_ADDR start_addr
;
7778 /* Find the starting address of the function containing the PC. */
7779 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7782 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7783 the start, i.e. after the JALR instruction, this is effectively
7785 prefixlen
= strlen (mips_str_mips16_call_stub
);
7786 if (pc
!= start_addr
7787 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7788 && mips_is_stub_mode (name
+ prefixlen
)
7789 && name
[prefixlen
+ 2] == '_'
7790 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7793 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7794 the JAL or JALR instruction, this is effectively a return stub. */
7795 prefixlen
= strlen (mips_str_call_fp_stub
);
7796 if (pc
!= start_addr
7797 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7800 /* Consume the .pic. prefix of any PIC stub, this function must return
7801 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7802 or the call stub path will trigger in handle_inferior_event causing
7804 prefixlen
= strlen (mips_str_pic
);
7805 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7808 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7809 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7810 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7811 && mips_is_stub_mode (name
+ prefixlen
)
7812 && name
[prefixlen
+ 2] == '\0')
7815 return 0; /* Not a stub. */
7818 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7819 PC of the stub target. The stub just loads $t9 and jumps to it,
7820 so that $t9 has the correct value at function entry. */
7823 mips_skip_pic_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7825 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7826 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7827 struct bound_minimal_symbol msym
;
7829 gdb_byte stub_code
[16];
7830 int32_t stub_words
[4];
7832 /* The stub for foo is named ".pic.foo", and is either two
7833 instructions inserted before foo or a three instruction sequence
7834 which jumps to foo. */
7835 msym
= lookup_minimal_symbol_by_pc (pc
);
7836 if (msym
.minsym
== NULL
7837 || msym
.value_address () != pc
7838 || msym
.minsym
->linkage_name () == NULL
7839 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7842 /* A two-instruction header. */
7843 if (msym
.minsym
->size () == 8)
7846 /* A three-instruction (plus delay slot) trampoline. */
7847 if (msym
.minsym
->size () == 16)
7849 if (target_read_memory (pc
, stub_code
, 16) != 0)
7851 for (i
= 0; i
< 4; i
++)
7852 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7855 /* A stub contains these instructions:
7858 addiu t9, t9, %lo(target)
7861 This works even for N64, since stubs are only generated with
7863 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7864 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7865 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7866 && stub_words
[3] == 0x00000000)
7867 return ((((stub_words
[0] & 0x0000ffff) << 16)
7868 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7871 /* Not a recognized stub. */
7876 mips_skip_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7878 CORE_ADDR requested_pc
= pc
;
7879 CORE_ADDR target_pc
;
7886 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7890 new_pc
= find_solib_trampoline_target (frame
, pc
);
7894 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7898 while (pc
!= target_pc
);
7900 return pc
!= requested_pc
? pc
: 0;
7903 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7904 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7907 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7910 if (num
>= 0 && num
< 32)
7912 else if (num
>= 38 && num
< 70)
7913 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7915 regnum
= mips_regnum (gdbarch
)->hi
;
7917 regnum
= mips_regnum (gdbarch
)->lo
;
7918 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7919 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7922 return gdbarch_num_regs (gdbarch
) + regnum
;
7926 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7927 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7930 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7933 if (num
>= 0 && num
< 32)
7935 else if (num
>= 32 && num
< 64)
7936 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7938 regnum
= mips_regnum (gdbarch
)->hi
;
7940 regnum
= mips_regnum (gdbarch
)->lo
;
7941 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7942 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7945 return gdbarch_num_regs (gdbarch
) + regnum
;
7949 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7951 /* Only makes sense to supply raw registers. */
7952 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7953 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7954 decide if it is valid. Should instead define a standard sim/gdb
7955 register numbering scheme. */
7956 if (gdbarch_register_name (gdbarch
,
7957 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
7960 return LEGACY_SIM_REGNO_IGNORE
;
7964 /* Convert an integer into an address. Extracting the value signed
7965 guarantees a correctly sign extended address. */
7968 mips_integer_to_address (struct gdbarch
*gdbarch
,
7969 struct type
*type
, const gdb_byte
*buf
)
7971 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7972 return extract_signed_integer (buf
, type
->length (), byte_order
);
7975 /* Dummy virtual frame pointer method. This is no more or less accurate
7976 than most other architectures; we just need to be explicit about it,
7977 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7978 an assertion failure. */
7981 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7982 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7984 *reg
= MIPS_SP_REGNUM
;
7989 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7991 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7992 const char *name
= bfd_section_name (sect
);
7994 if (*abip
!= MIPS_ABI_UNKNOWN
)
7997 if (!startswith (name
, ".mdebug."))
8000 if (strcmp (name
, ".mdebug.abi32") == 0)
8001 *abip
= MIPS_ABI_O32
;
8002 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8003 *abip
= MIPS_ABI_N32
;
8004 else if (strcmp (name
, ".mdebug.abi64") == 0)
8005 *abip
= MIPS_ABI_N64
;
8006 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8007 *abip
= MIPS_ABI_O64
;
8008 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8009 *abip
= MIPS_ABI_EABI32
;
8010 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8011 *abip
= MIPS_ABI_EABI64
;
8013 warning (_("unsupported ABI %s."), name
+ 8);
8017 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8019 int *lbp
= (int *) obj
;
8020 const char *name
= bfd_section_name (sect
);
8022 if (startswith (name
, ".gcc_compiled_long32"))
8024 else if (startswith (name
, ".gcc_compiled_long64"))
8026 else if (startswith (name
, ".gcc_compiled_long"))
8027 warning (_("unrecognized .gcc_compiled_longXX"));
8030 static enum mips_abi
8031 global_mips_abi (void)
8035 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8036 if (mips_abi_strings
[i
] == mips_abi_string
)
8037 return (enum mips_abi
) i
;
8039 internal_error (_("unknown ABI string"));
8042 /* Return the default compressed instruction set, either of MIPS16
8043 or microMIPS, selected when none could have been determined from
8044 the ELF header of the binary being executed (or no binary has been
8047 static enum mips_isa
8048 global_mips_compression (void)
8052 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8053 if (mips_compression_strings
[i
] == mips_compression_string
)
8054 return (enum mips_isa
) i
;
8056 internal_error (_("unknown compressed ISA string"));
8060 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8062 /* If the size matches the set of 32-bit or 64-bit integer registers,
8063 assume that's what we've got. */
8064 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8065 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8067 /* If the size matches the full set of registers GDB traditionally
8068 knows about, including floating point, for either 32-bit or
8069 64-bit, assume that's what we've got. */
8070 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8071 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8073 /* Otherwise we don't have a useful guess. */
8076 static struct value
*
8077 value_of_mips_user_reg (frame_info_ptr frame
, const void *baton
)
8079 const int *reg_p
= (const int *) baton
;
8080 return value_of_register (*reg_p
, get_next_frame_sentinel_okay (frame
));
8083 static struct gdbarch
*
8084 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8087 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8089 enum mips_fpu_type fpu_type
;
8090 tdesc_arch_data_up tdesc_data
;
8091 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8092 const char * const *reg_names
;
8093 struct mips_regnum mips_regnum
, *regnum
;
8094 enum mips_isa mips_isa
;
8098 /* First of all, extract the elf_flags, if available. */
8099 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8100 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8101 else if (arches
!= NULL
)
8103 mips_gdbarch_tdep
*tdep
8104 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8105 elf_flags
= tdep
->elf_flags
;
8110 gdb_printf (gdb_stdlog
,
8111 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8113 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8114 switch ((elf_flags
& EF_MIPS_ABI
))
8116 case EF_MIPS_ABI_O32
:
8117 found_abi
= MIPS_ABI_O32
;
8119 case EF_MIPS_ABI_O64
:
8120 found_abi
= MIPS_ABI_O64
;
8122 case EF_MIPS_ABI_EABI32
:
8123 found_abi
= MIPS_ABI_EABI32
;
8125 case EF_MIPS_ABI_EABI64
:
8126 found_abi
= MIPS_ABI_EABI64
;
8129 if ((elf_flags
& EF_MIPS_ABI2
))
8130 found_abi
= MIPS_ABI_N32
;
8132 found_abi
= MIPS_ABI_UNKNOWN
;
8136 /* GCC creates a pseudo-section whose name describes the ABI. */
8137 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8138 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8140 /* If we have no useful BFD information, use the ABI from the last
8141 MIPS architecture (if there is one). */
8142 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8144 mips_gdbarch_tdep
*tdep
8145 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8146 found_abi
= tdep
->found_abi
;
8149 /* Try the architecture for any hint of the correct ABI. */
8150 if (found_abi
== MIPS_ABI_UNKNOWN
8151 && info
.bfd_arch_info
!= NULL
8152 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8154 switch (info
.bfd_arch_info
->mach
)
8156 case bfd_mach_mips3900
:
8157 found_abi
= MIPS_ABI_EABI32
;
8159 case bfd_mach_mips4100
:
8160 case bfd_mach_mips5000
:
8161 found_abi
= MIPS_ABI_EABI64
;
8163 case bfd_mach_mips8000
:
8164 case bfd_mach_mips10000
:
8165 /* On Irix, ELF64 executables use the N64 ABI. The
8166 pseudo-sections which describe the ABI aren't present
8167 on IRIX. (Even for executables created by gcc.) */
8168 if (info
.abfd
!= NULL
8169 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8170 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8171 found_abi
= MIPS_ABI_N64
;
8173 found_abi
= MIPS_ABI_N32
;
8178 /* Default 64-bit objects to N64 instead of O32. */
8179 if (found_abi
== MIPS_ABI_UNKNOWN
8180 && info
.abfd
!= NULL
8181 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8182 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8183 found_abi
= MIPS_ABI_N64
;
8186 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8189 /* What has the user specified from the command line? */
8190 wanted_abi
= global_mips_abi ();
8192 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8195 /* Now that we have found what the ABI for this binary would be,
8196 check whether the user is overriding it. */
8197 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8198 mips_abi
= wanted_abi
;
8199 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8200 mips_abi
= found_abi
;
8202 mips_abi
= MIPS_ABI_O32
;
8204 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8207 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8208 if (mips_abi
!= MIPS_ABI_EABI32
8209 && mips_abi
!= MIPS_ABI_O32
8210 && info
.bfd_arch_info
!= NULL
8211 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8212 && info
.bfd_arch_info
->bits_per_word
< 64)
8213 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8215 /* Determine the default compressed ISA. */
8216 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8217 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8218 mips_isa
= ISA_MICROMIPS
;
8219 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8220 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8221 mips_isa
= ISA_MIPS16
;
8223 mips_isa
= global_mips_compression ();
8224 mips_compression_string
= mips_compression_strings
[mips_isa
];
8226 /* Also used when doing an architecture lookup. */
8228 gdb_printf (gdb_stdlog
,
8229 "mips_gdbarch_init: "
8230 "mips64_transfers_32bit_regs_p = %d\n",
8231 mips64_transfers_32bit_regs_p
);
8233 /* Determine the MIPS FPU type. */
8236 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8237 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8238 Tag_GNU_MIPS_ABI_FP
);
8239 #endif /* HAVE_ELF */
8241 if (!mips_fpu_type_auto
)
8242 fpu_type
= mips_fpu_type
;
8243 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8245 switch (elf_fpu_type
)
8247 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8248 fpu_type
= MIPS_FPU_DOUBLE
;
8250 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8251 fpu_type
= MIPS_FPU_SINGLE
;
8253 case Val_GNU_MIPS_ABI_FP_SOFT
:
8255 /* Soft float or unknown. */
8256 fpu_type
= MIPS_FPU_NONE
;
8260 else if (info
.bfd_arch_info
!= NULL
8261 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8262 switch (info
.bfd_arch_info
->mach
)
8264 case bfd_mach_mips3900
:
8265 case bfd_mach_mips4100
:
8266 case bfd_mach_mips4111
:
8267 case bfd_mach_mips4120
:
8268 fpu_type
= MIPS_FPU_NONE
;
8270 case bfd_mach_mips4650
:
8271 fpu_type
= MIPS_FPU_SINGLE
;
8274 fpu_type
= MIPS_FPU_DOUBLE
;
8277 else if (arches
!= NULL
)
8278 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8280 fpu_type
= MIPS_FPU_DOUBLE
;
8282 gdb_printf (gdb_stdlog
,
8283 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8285 /* Check for blatant incompatibilities. */
8287 /* If we have only 32-bit registers, then we can't debug a 64-bit
8289 if (info
.target_desc
8290 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8291 && mips_abi
!= MIPS_ABI_EABI32
8292 && mips_abi
!= MIPS_ABI_O32
)
8295 /* Fill in the OS dependent register numbers and names. */
8296 if (info
.osabi
== GDB_OSABI_LINUX
)
8298 mips_regnum
.fp0
= 38;
8299 mips_regnum
.pc
= 37;
8300 mips_regnum
.cause
= 36;
8301 mips_regnum
.badvaddr
= 35;
8302 mips_regnum
.hi
= 34;
8303 mips_regnum
.lo
= 33;
8304 mips_regnum
.fp_control_status
= 70;
8305 mips_regnum
.fp_implementation_revision
= 71;
8306 mips_regnum
.dspacc
= -1;
8307 mips_regnum
.dspctl
= -1;
8311 reg_names
= mips_linux_reg_names
;
8315 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8316 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8317 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8318 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8319 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8320 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8321 mips_regnum
.fp_control_status
= 70;
8322 mips_regnum
.fp_implementation_revision
= 71;
8323 mips_regnum
.dspacc
= dspacc
= -1;
8324 mips_regnum
.dspctl
= dspctl
= -1;
8325 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8326 if (info
.bfd_arch_info
!= NULL
8327 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8328 reg_names
= mips_tx39_reg_names
;
8330 reg_names
= mips_generic_reg_names
;
8333 /* Check any target description for validity. */
8334 if (tdesc_has_registers (info
.target_desc
))
8336 static const char *const mips_gprs
[] = {
8337 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8338 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8339 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8340 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8342 static const char *const mips_fprs
[] = {
8343 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8344 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8345 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8346 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8349 const struct tdesc_feature
*feature
;
8352 feature
= tdesc_find_feature (info
.target_desc
,
8353 "org.gnu.gdb.mips.cpu");
8354 if (feature
== NULL
)
8357 tdesc_data
= tdesc_data_alloc ();
8360 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8361 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8365 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8366 mips_regnum
.lo
, "lo");
8367 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8368 mips_regnum
.hi
, "hi");
8369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8370 mips_regnum
.pc
, "pc");
8375 feature
= tdesc_find_feature (info
.target_desc
,
8376 "org.gnu.gdb.mips.cp0");
8377 if (feature
== NULL
)
8381 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8382 mips_regnum
.badvaddr
, "badvaddr");
8383 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8384 MIPS_PS_REGNUM
, "status");
8385 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8386 mips_regnum
.cause
, "cause");
8391 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8392 backend is not prepared for that, though. */
8393 feature
= tdesc_find_feature (info
.target_desc
,
8394 "org.gnu.gdb.mips.fpu");
8395 if (feature
== NULL
)
8399 for (i
= 0; i
< 32; i
++)
8400 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8401 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8403 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8404 mips_regnum
.fp_control_status
,
8407 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8408 mips_regnum
.fp_implementation_revision
,
8414 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8418 feature
= tdesc_find_feature (info
.target_desc
,
8419 "org.gnu.gdb.mips.dsp");
8420 /* The DSP registers are optional; it's OK if they are absent. */
8421 if (feature
!= NULL
)
8425 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8426 dspacc
+ i
++, "hi1");
8427 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8428 dspacc
+ i
++, "lo1");
8429 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8430 dspacc
+ i
++, "hi2");
8431 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8432 dspacc
+ i
++, "lo2");
8433 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8434 dspacc
+ i
++, "hi3");
8435 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8436 dspacc
+ i
++, "lo3");
8438 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8444 mips_regnum
.dspacc
= dspacc
;
8445 mips_regnum
.dspctl
= dspctl
;
8447 num_regs
= mips_regnum
.dspctl
+ 1;
8451 /* It would be nice to detect an attempt to use a 64-bit ABI
8452 when only 32-bit registers are provided. */
8456 /* Try to find a pre-existing architecture. */
8457 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8459 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8461 mips_gdbarch_tdep
*tdep
8462 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8464 /* MIPS needs to be pedantic about which ABI and the compressed
8465 ISA variation the object is using. */
8466 if (tdep
->elf_flags
!= elf_flags
)
8468 if (tdep
->mips_abi
!= mips_abi
)
8470 if (tdep
->mips_isa
!= mips_isa
)
8472 /* Need to be pedantic about which register virtual size is
8474 if (tdep
->mips64_transfers_32bit_regs_p
8475 != mips64_transfers_32bit_regs_p
)
8477 /* Be pedantic about which FPU is selected. */
8478 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8481 return arches
->gdbarch
;
8484 /* Need a new architecture. Fill in a target specific vector. */
8486 = gdbarch_alloc (&info
, gdbarch_tdep_up (new mips_gdbarch_tdep
));
8487 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8489 tdep
->elf_flags
= elf_flags
;
8490 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8491 tdep
->found_abi
= found_abi
;
8492 tdep
->mips_abi
= mips_abi
;
8493 tdep
->mips_isa
= mips_isa
;
8494 tdep
->mips_fpu_type
= fpu_type
;
8495 tdep
->register_size_valid_p
= 0;
8496 tdep
->register_size
= 0;
8498 if (info
.target_desc
)
8500 /* Some useful properties can be inferred from the target. */
8501 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8503 tdep
->register_size_valid_p
= 1;
8504 tdep
->register_size
= 4;
8506 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8508 tdep
->register_size_valid_p
= 1;
8509 tdep
->register_size
= 8;
8513 /* Initially set everything according to the default ABI/ISA. */
8514 set_gdbarch_short_bit (gdbarch
, 16);
8515 set_gdbarch_int_bit (gdbarch
, 32);
8516 set_gdbarch_float_bit (gdbarch
, 32);
8517 set_gdbarch_double_bit (gdbarch
, 64);
8518 set_gdbarch_long_double_bit (gdbarch
, 64);
8519 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8520 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8521 set_gdbarch_deprecated_pseudo_register_write (gdbarch
,
8522 mips_pseudo_register_write
);
8524 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8525 mips_ax_pseudo_register_collect
);
8526 set_gdbarch_ax_pseudo_register_push_stack
8527 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8529 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8530 mips_elf_make_msymbol_special
);
8531 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8532 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8533 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8535 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8536 *regnum
= mips_regnum
;
8537 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8538 set_gdbarch_num_regs (gdbarch
, num_regs
);
8539 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8540 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8541 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8542 tdep
->mips_processor_reg_names
= reg_names
;
8543 tdep
->regnum
= regnum
;
8548 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8549 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8550 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8551 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8552 tdep
->default_mask_address_p
= 0;
8553 set_gdbarch_long_bit (gdbarch
, 32);
8554 set_gdbarch_ptr_bit (gdbarch
, 32);
8555 set_gdbarch_long_long_bit (gdbarch
, 64);
8558 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8559 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8560 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8561 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8562 tdep
->default_mask_address_p
= 0;
8563 set_gdbarch_long_bit (gdbarch
, 32);
8564 set_gdbarch_ptr_bit (gdbarch
, 32);
8565 set_gdbarch_long_long_bit (gdbarch
, 64);
8567 case MIPS_ABI_EABI32
:
8568 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8569 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8570 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8571 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8572 tdep
->default_mask_address_p
= 0;
8573 set_gdbarch_long_bit (gdbarch
, 32);
8574 set_gdbarch_ptr_bit (gdbarch
, 32);
8575 set_gdbarch_long_long_bit (gdbarch
, 64);
8577 case MIPS_ABI_EABI64
:
8578 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8579 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8580 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8581 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8582 tdep
->default_mask_address_p
= 0;
8583 set_gdbarch_long_bit (gdbarch
, 64);
8584 set_gdbarch_ptr_bit (gdbarch
, 64);
8585 set_gdbarch_long_long_bit (gdbarch
, 64);
8588 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8589 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8590 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8591 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8592 tdep
->default_mask_address_p
= 0;
8593 set_gdbarch_long_bit (gdbarch
, 32);
8594 set_gdbarch_ptr_bit (gdbarch
, 32);
8595 set_gdbarch_long_long_bit (gdbarch
, 64);
8596 set_gdbarch_long_double_bit (gdbarch
, 128);
8597 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8600 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8601 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8602 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8603 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8604 tdep
->default_mask_address_p
= 0;
8605 set_gdbarch_long_bit (gdbarch
, 64);
8606 set_gdbarch_ptr_bit (gdbarch
, 64);
8607 set_gdbarch_long_long_bit (gdbarch
, 64);
8608 set_gdbarch_long_double_bit (gdbarch
, 128);
8609 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8612 internal_error (_("unknown ABI in switch"));
8615 /* GCC creates a pseudo-section whose name specifies the size of
8616 longs, since -mlong32 or -mlong64 may be used independent of
8617 other options. How those options affect pointer sizes is ABI and
8618 architecture dependent, so use them to override the default sizes
8619 set by the ABI. This table shows the relationship between ABI,
8620 -mlongXX, and size of pointers:
8622 ABI -mlongXX ptr bits
8623 --- -------- --------
8637 Note that for o32 and eabi32, pointers are always 32 bits
8638 regardless of any -mlongXX option. For all others, pointers and
8639 longs are the same, as set by -mlongXX or set by defaults. */
8641 if (info
.abfd
!= NULL
)
8645 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8648 set_gdbarch_long_bit (gdbarch
, long_bit
);
8652 case MIPS_ABI_EABI32
:
8657 case MIPS_ABI_EABI64
:
8658 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8661 internal_error (_("unknown ABI in switch"));
8666 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8667 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8670 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8671 flag in object files because to do so would make it impossible to
8672 link with libraries compiled without "-gp32". This is
8673 unnecessarily restrictive.
8675 We could solve this problem by adding "-gp32" multilibs to gcc,
8676 but to set this flag before gcc is built with such multilibs will
8677 break too many systems.''
8679 But even more unhelpfully, the default linker output target for
8680 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8681 for 64-bit programs - you need to change the ABI to change this,
8682 and not all gcc targets support that currently. Therefore using
8683 this flag to detect 32-bit mode would do the wrong thing given
8684 the current gcc - it would make GDB treat these 64-bit programs
8685 as 32-bit programs by default. */
8687 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8688 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8690 /* Add/remove bits from an address. The MIPS needs be careful to
8691 ensure that all 32 bit addresses are sign extended to 64 bits. */
8692 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8694 /* Unwind the frame. */
8695 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8696 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8697 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8699 /* Map debug register numbers onto internal register numbers. */
8700 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8701 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8702 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8703 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8704 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8705 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8707 /* MIPS version of CALL_DUMMY. */
8709 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8710 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8711 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8713 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8715 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8716 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8717 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8719 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8720 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8721 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8722 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8723 mips_adjust_breakpoint_address
);
8725 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8727 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8729 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8730 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8731 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8733 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8735 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8737 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8738 if (mips_abi
== MIPS_ABI_N64
)
8739 set_gdbarch_disassembler_options_implicit
8740 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8741 else if (mips_abi
== MIPS_ABI_N32
)
8742 set_gdbarch_disassembler_options_implicit
8743 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8745 set_gdbarch_disassembler_options_implicit
8746 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8747 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8748 set_gdbarch_valid_disassembler_options (gdbarch
,
8749 disassembler_options_mips ());
8751 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8752 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8753 need to all be folded into the target vector. Since they are
8754 being used as guards for target_stopped_by_watchpoint, why not have
8755 target_stopped_by_watchpoint return the type of watchpoint that the code
8757 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8759 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8761 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8762 to support MIPS16. This is a bad thing. Make sure not to do it
8763 if we have an OS ABI that actually supports shared libraries, since
8764 shared library support is more important. If we have an OS someday
8765 that supports both shared libraries and MIPS16, we'll have to find
8766 a better place for these.
8767 macro/2012-04-25: But that applies to return trampolines only and
8768 currently no MIPS OS ABI uses shared libraries that have them. */
8769 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8771 set_gdbarch_single_step_through_delay (gdbarch
,
8772 mips_single_step_through_delay
);
8774 /* Virtual tables. */
8775 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8777 mips_register_g_packet_guesses (gdbarch
);
8779 /* Hook in OS ABI-specific overrides, if they have been registered. */
8780 info
.tdesc_data
= tdesc_data
.get ();
8781 gdbarch_init_osabi (info
, gdbarch
);
8783 /* The hook may have adjusted num_regs, fetch the final value and
8784 set pc_regnum and sp_regnum now that it has been fixed. */
8785 num_regs
= gdbarch_num_regs (gdbarch
);
8786 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8787 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8789 /* Unwind the frame. */
8790 dwarf2_append_unwinders (gdbarch
);
8791 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8792 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8793 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8794 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8795 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8796 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8797 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8798 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8799 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8801 if (tdesc_data
!= nullptr)
8803 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8804 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8806 /* Override the normal target description methods to handle our
8807 dual real and pseudo registers. */
8808 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8809 set_gdbarch_register_reggroup_p (gdbarch
,
8810 mips_tdesc_register_reggroup_p
);
8812 num_regs
= gdbarch_num_regs (gdbarch
);
8813 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8814 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8815 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8818 /* Add ABI-specific aliases for the registers. */
8819 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8820 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8821 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8822 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8824 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8825 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8826 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8828 /* Add some other standard aliases. */
8829 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8830 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8831 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8833 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8834 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8835 value_of_mips_user_reg
,
8836 &mips_numeric_register_aliases
[i
].regnum
);
8842 mips_abi_update (const char *ignore_args
,
8843 int from_tty
, struct cmd_list_element
*c
)
8845 struct gdbarch_info info
;
8847 /* Force the architecture to update, and (if it's a MIPS architecture)
8848 mips_gdbarch_init will take care of the rest. */
8849 gdbarch_update_p (info
);
8852 /* Print out which MIPS ABI is in use. */
8855 show_mips_abi (struct ui_file
*file
,
8857 struct cmd_list_element
*ignored_cmd
,
8858 const char *ignored_value
)
8860 if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch
8864 "The MIPS ABI is unknown because the current architecture "
8868 enum mips_abi global_abi
= global_mips_abi ();
8869 enum mips_abi actual_abi
= mips_abi (current_inferior ()->arch ());
8870 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8872 if (global_abi
== MIPS_ABI_UNKNOWN
)
8875 "The MIPS ABI is set automatically (currently \"%s\").\n",
8877 else if (global_abi
== actual_abi
)
8880 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8884 /* Probably shouldn't happen... */
8886 "The (auto detected) MIPS ABI \"%s\" is in use "
8887 "even though the user setting was \"%s\".\n",
8888 actual_abi_str
, mips_abi_strings
[global_abi
]);
8893 /* Print out which MIPS compressed ISA encoding is used. */
8896 show_mips_compression (struct ui_file
*file
, int from_tty
,
8897 struct cmd_list_element
*c
, const char *value
)
8899 gdb_printf (file
, _("The compressed ISA encoding used is %s.\n"),
8903 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8906 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8912 case MIPS_FPU_SINGLE
:
8914 case MIPS_FPU_DOUBLE
:
8922 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8924 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8928 int ef_mips_32bitmode
;
8929 /* Determine the ISA. */
8930 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8932 case EF_MIPS_ARCH_1
:
8935 case EF_MIPS_ARCH_2
:
8938 case EF_MIPS_ARCH_3
:
8941 case EF_MIPS_ARCH_4
:
8948 /* Determine the size of a pointer. */
8949 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8951 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8954 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8957 "mips_dump_tdep: ef_mips_arch = %d\n",
8960 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8961 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8964 "mips_mask_address_p() %d (default %d)\n",
8965 mips_mask_address_p (tdep
),
8966 tdep
->default_mask_address_p
);
8969 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8970 MIPS_DEFAULT_FPU_TYPE
,
8971 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8972 gdb_printf (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8973 mips_eabi (gdbarch
));
8975 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8976 mips_get_fpu_type (gdbarch
),
8977 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8980 void _initialize_mips_tdep ();
8982 _initialize_mips_tdep ()
8984 static struct cmd_list_element
*mipsfpulist
= NULL
;
8986 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8987 if (MIPS_ABI_LAST
+ 1
8988 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8989 internal_error (_("mips_abi_strings out of sync"));
8991 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8993 /* Create feature sets with the appropriate properties. The values
8994 are not important. */
8995 mips_tdesc_gp32
= allocate_target_description ().release ();
8996 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8998 mips_tdesc_gp64
= allocate_target_description ().release ();
8999 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9001 /* Add root prefix command for all "set mips"/"show mips" commands. */
9002 add_setshow_prefix_cmd ("mips", no_class
,
9003 _("Various MIPS specific commands."),
9004 _("Various MIPS specific commands."),
9005 &setmipscmdlist
, &showmipscmdlist
,
9006 &setlist
, &showlist
);
9008 /* Allow the user to override the ABI. */
9009 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9010 &mips_abi_string
, _("\
9011 Set the MIPS ABI used by this program."), _("\
9012 Show the MIPS ABI used by this program."), _("\
9013 This option can be set to one of:\n\
9014 auto - the default ABI associated with the current binary\n\
9023 &setmipscmdlist
, &showmipscmdlist
);
9025 /* Allow the user to set the ISA to assume for compressed code if ELF
9026 file flags don't tell or there is no program file selected. This
9027 setting is updated whenever unambiguous ELF file flags are interpreted,
9028 and carried over to subsequent sessions. */
9029 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9030 &mips_compression_string
, _("\
9031 Set the compressed ISA encoding used by MIPS code."), _("\
9032 Show the compressed ISA encoding used by MIPS code."), _("\
9033 Select the compressed ISA encoding used in functions that have no symbol\n\
9034 information available. The encoding can be set to either of:\n\
9037 and is updated automatically from ELF file flags if available."),
9039 show_mips_compression
,
9040 &setmipscmdlist
, &showmipscmdlist
);
9042 /* Let the user turn off floating point and set the fence post for
9043 heuristic_proc_start. */
9045 add_basic_prefix_cmd ("mipsfpu", class_support
,
9046 _("Set use of MIPS floating-point coprocessor."),
9047 &mipsfpulist
, 0, &setlist
);
9048 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9049 _("Select single-precision MIPS floating-point coprocessor."),
9051 cmd_list_element
*set_mipsfpu_double_cmd
9052 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9053 _("Select double-precision MIPS floating-point coprocessor."),
9055 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9056 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9057 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9059 cmd_list_element
*set_mipsfpu_none_cmd
9060 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9061 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9062 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9063 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9064 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9065 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9066 _("Select MIPS floating-point coprocessor automatically."),
9068 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9069 _("Show current use of MIPS floating-point coprocessor target."),
9072 /* We really would like to have both "0" and "unlimited" work, but
9073 command.c doesn't deal with that. So make it a var_zinteger
9074 because the user can always use "999999" or some such for unlimited. */
9075 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9076 &heuristic_fence_post
, _("\
9077 Set the distance searched for the start of a function."), _("\
9078 Show the distance searched for the start of a function."), _("\
9079 If you are debugging a stripped executable, GDB needs to search through the\n\
9080 program for the start of a function. This command sets the distance of the\n\
9081 search. The only need to set it is when debugging a stripped executable."),
9082 reinit_frame_cache_sfunc
,
9083 NULL
, /* FIXME: i18n: The distance searched for
9084 the start of a function is %s. */
9085 &setlist
, &showlist
);
9087 /* Allow the user to control whether the upper bits of 64-bit
9088 addresses should be zeroed. */
9089 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9090 &mask_address_var
, _("\
9091 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9092 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9093 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9094 allow GDB to determine the correct value."),
9095 NULL
, show_mask_address
,
9096 &setmipscmdlist
, &showmipscmdlist
);
9098 /* Allow the user to control the size of 32 bit registers within the
9099 raw remote packet. */
9100 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9101 &mips64_transfers_32bit_regs_p
, _("\
9102 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9104 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9106 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9107 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9108 64 bits for others. Use \"off\" to disable compatibility mode"),
9109 set_mips64_transfers_32bit_regs
,
9110 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9111 MIPS target that transfers 32-bit
9112 quantities is %s. */
9113 &setlist
, &showlist
);
9115 /* Debug this files internals. */
9116 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9118 Set mips debugging."), _("\
9119 Show mips debugging."), _("\
9120 When non-zero, mips specific debugging is enabled."),
9122 NULL
, /* FIXME: i18n: Mips debugging is
9124 &setdebuglist
, &showdebuglist
);