sim/v850/v850-sim.h

   1 #ifndef V850_SIM_H
   2 #define V850_SIM_H
   3
   4 #include <stdint.h>
   5
   6 struct simops
   7 {
   8   unsigned long   opcode;
   9   unsigned long   mask;
  10   int (* func) (void);
  11   int    numops;
  12   int    operands[12];
  13 };
  14
  15 #include "simops.h"
  16
  17 typedef uint32_t reg_t;
  18 typedef uint64_t reg64_t;
  19
  20
  21 /* The current state of the processor; registers, memory, etc.  */
  22
  23 typedef struct _v850_regs {
  24   reg_t regs[32];               /* general-purpose registers */
  25   reg_t sregs[32];              /* system registers, including psw */
  26   reg_t pc;
  27   int dummy_mem;                /* where invalid accesses go */
  28   reg_t mpu0_sregs[28];         /* mpu0 system registers */
  29   reg_t mpu1_sregs[28];         /* mpu1 system registers */
  30   reg_t fpu_sregs[28];          /* fpu system registers */
  31   reg_t selID_sregs[7][32];     /* system registers, selID 1 thru selID 7 */
  32   reg64_t vregs[32];            /* vector registers.  */
  33 } v850_regs;
  34
  35 struct v850_sim_cpu {
  36   v850_regs reg;
  37   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  38   sim_event *pending_nmi;
  39 };
  40
  41 #define V850_SIM_CPU(cpu) ((struct v850_sim_cpu *) CPU_ARCH_DATA (cpu))
  42
  43 /* For compatibility, until all functions converted to passing
  44    SIM_DESC as an argument */
  45 extern SIM_DESC simulator;
  46
  47
  48 #define V850_ROM_SIZE 0x8000
  49 #define V850_LOW_END 0x200000
  50 #define V850_HIGH_START 0xffe000
  51
  52
  53 /* Because we are still using the old semantic table, provide compat
  54    macro's that store the instruction where the old simops expects
  55    it. */
  56
  57 extern uint32_t OP[4];
  58 #if 0
  59 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  60 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  61 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
  62 OP[3] = inst;
  63 #endif
  64
  65 #define SAVE_1 \
  66 PC = cia; \
  67 OP[0] = instruction_0 & 0x1f; \
  68 OP[1] = (instruction_0 >> 11) & 0x1f; \
  69 OP[2] = 0; \
  70 OP[3] = instruction_0
  71
  72 #define COMPAT_1(CALL) \
  73 SAVE_1; \
  74 PC += (CALL); \
  75 nia = PC
  76
  77 #define SAVE_2 \
  78 PC = cia; \
  79 OP[0] = instruction_0 & 0x1f; \
  80 OP[1] = (instruction_0 >> 11) & 0x1f; \
  81 OP[2] = instruction_1; \
  82 OP[3] = (instruction_1 << 16) | instruction_0
  83
  84 #define COMPAT_2(CALL) \
  85 SAVE_2; \
  86 PC += (CALL); \
  87 nia = PC
  88
  89
  90 /* new */
  91 #define GR  (V850_SIM_CPU (CPU)->reg.regs)
  92 #define SR  (V850_SIM_CPU (CPU)->reg.sregs)
  93 #define VR  (V850_SIM_CPU (CPU)->reg.vregs)
  94 #define MPU0_SR  (V850_SIM_CPU (CPU)->reg.mpu0_sregs)
  95 #define MPU1_SR  (V850_SIM_CPU (CPU)->reg.mpu1_sregs)
  96 #define FPU_SR   (V850_SIM_CPU (CPU)->reg.fpu_sregs)
  97
  98 /* old */
  99 #define State    (V850_SIM_CPU (STATE_CPU (simulator, 0))->reg)
 100 #define PC      (State.pc)
 101 #define SP_REGNO        3
 102 #define SP      (State.regs[SP_REGNO])
 103 #define EP      (State.regs[30])
 104
 105 #define EIPC  (State.sregs[0])
 106 #define EIPSW (State.sregs[1])
 107 #define FEPC  (State.sregs[2])
 108 #define FEPSW (State.sregs[3])
 109 #define ECR   (State.sregs[4])
 110 #define PSW   (State.sregs[5])
 111 #define PSW_REGNO   5
 112 #define EIIC  (State.sregs[13])
 113 #define FEIC  (State.sregs[14])
 114 #define DBIC  (SR[15])
 115 #define CTPC  (SR[16])
 116 #define CTPSW (SR[17])
 117 #define DBPC  (State.sregs[18])
 118 #define DBPSW (State.sregs[19])
 119 #define CTBP  (State.sregs[20])
 120 #define DIR   (SR[21])
 121 #define EIWR  (SR[28])
 122 #define FEWR  (SR[29])
 123 #define DBWR  (SR[30])
 124 #define BSEL  (SR[31])
 125
 126 #define PSW_US BIT32 (8)
 127 #define PSW_NP 0x80
 128 #define PSW_EP 0x40
 129 #define PSW_ID 0x20
 130 #define PSW_SAT 0x10
 131 #define PSW_CY 0x8
 132 #define PSW_OV 0x4
 133 #define PSW_S 0x2
 134 #define PSW_Z 0x1
 135
 136 #define PSW_NPV (1<<18)
 137 #define PSW_DMP (1<<17)
 138 #define PSW_IMP (1<<16)
 139
 140 #define ECR_EICC 0x0000ffff
 141 #define ECR_FECC 0xffff0000
 142
 143 /* FPU */
 144
 145 #define FPSR  (FPU_SR[6])
 146 #define FPSR_REGNO 6
 147 #define FPEPC (FPU_SR[7])
 148 #define FPST  (FPU_SR[8])
 149 #define FPST_REGNO 8
 150 #define FPCC  (FPU_SR[9])
 151 #define FPCFG (FPU_SR[10])
 152 #define FPCFG_REGNO 10
 153
 154 #define FPSR_DEM  0x00200000
 155 #define FPSR_SEM  0x00100000
 156 #define FPSR_RM   0x000c0000
 157 #define FPSR_RN   0x00000000
 158 #define FPSR_FS   0x00020000
 159 #define FPSR_PR   0x00010000
 160
 161 #define FPSR_XC   0x0000fc00
 162 #define FPSR_XCE  0x00008000
 163 #define FPSR_XCV  0x00004000
 164 #define FPSR_XCZ  0x00002000
 165 #define FPSR_XCO  0x00001000
 166 #define FPSR_XCU  0x00000800
 167 #define FPSR_XCI  0x00000400
 168
 169 #define FPSR_XE   0x000003e0
 170 #define FPSR_XEV  0x00000200
 171 #define FPSR_XEZ  0x00000100
 172 #define FPSR_XEO  0x00000080
 173 #define FPSR_XEU  0x00000040
 174 #define FPSR_XEI  0x00000020
 175
 176 #define FPSR_XP   0x0000001f
 177 #define FPSR_XPV  0x00000010
 178 #define FPSR_XPZ  0x00000008
 179 #define FPSR_XPO  0x00000004
 180 #define FPSR_XPU  0x00000002
 181 #define FPSR_XPI  0x00000001
 182
 183 #define FPST_PR   0x00008000
 184 #define FPST_XCE  0x00002000
 185 #define FPST_XCV  0x00001000
 186 #define FPST_XCZ  0x00000800
 187 #define FPST_XCO  0x00000400
 188 #define FPST_XCU  0x00000200
 189 #define FPST_XCI  0x00000100
 190
 191 #define FPST_XPV  0x00000010
 192 #define FPST_XPZ  0x00000008
 193 #define FPST_XPO  0x00000004
 194 #define FPST_XPU  0x00000002
 195 #define FPST_XPI  0x00000001
 196
 197 #define FPCFG_RM   0x00000180
 198 #define FPCFG_XEV  0x00000010
 199 #define FPCFG_XEZ  0x00000008
 200 #define FPCFG_XEO  0x00000004
 201 #define FPCFG_XEU  0x00000002
 202 #define FPCFG_XEI  0x00000001
 203
 204 #define GET_FPCC()\
 205  ((FPSR >> 24) &0xf)
 206
 207 #define CLEAR_FPCC(bbb)\
 208   (FPSR &= ~(1 << (bbb+24)))
 209
 210 #define SET_FPCC(bbb)\
 211  (FPSR |= 1 << (bbb+24))
 212
 213 #define TEST_FPCC(bbb)\
 214   ((FPSR & (1 << (bbb+24))) != 0)
 215
 216 #define FPSR_GET_ROUND()                                        \
 217   (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near           \
 218    : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up        \
 219    : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down      \
 220    : sim_fpu_round_zero)
 221
 222
 223 enum FPU_COMPARE {
 224   FPU_CMP_F = 0,
 225   FPU_CMP_UN,
 226   FPU_CMP_EQ,
 227   FPU_CMP_UEQ,
 228   FPU_CMP_OLT,
 229   FPU_CMP_ULT,
 230   FPU_CMP_OLE,
 231   FPU_CMP_ULE,
 232   FPU_CMP_SF,
 233   FPU_CMP_NGLE,
 234   FPU_CMP_SEQ,
 235   FPU_CMP_NGL,
 236   FPU_CMP_LT,
 237   FPU_CMP_NGE,
 238   FPU_CMP_LE,
 239   FPU_CMP_NGT
 240 };
 241
 242
 243 /* MPU */
 244 #define MPM     (MPU1_SR[0])
 245 #define MPC     (MPU1_SR[1])
 246 #define MPC_REGNO 1
 247 #define TID     (MPU1_SR[2])
 248 #define PPA     (MPU1_SR[3])
 249 #define PPM     (MPU1_SR[4])
 250 #define PPC     (MPU1_SR[5])
 251 #define DCC     (MPU1_SR[6])
 252 #define DCV0    (MPU1_SR[7])
 253 #define DCV1    (MPU1_SR[8])
 254 #define SPAL    (MPU1_SR[10])
 255 #define SPAU    (MPU1_SR[11])
 256 #define IPA0L   (MPU1_SR[12])
 257 #define IPA0U   (MPU1_SR[13])
 258 #define IPA1L   (MPU1_SR[14])
 259 #define IPA1U   (MPU1_SR[15])
 260 #define IPA2L   (MPU1_SR[16])
 261 #define IPA2U   (MPU1_SR[17])
 262 #define IPA3L   (MPU1_SR[18])
 263 #define IPA3U   (MPU1_SR[19])
 264 #define DPA0L   (MPU1_SR[20])
 265 #define DPA0U   (MPU1_SR[21])
 266 #define DPA1L   (MPU1_SR[22])
 267 #define DPA1U   (MPU1_SR[23])
 268 #define DPA2L   (MPU1_SR[24])
 269 #define DPA2U   (MPU1_SR[25])
 270 #define DPA3L   (MPU1_SR[26])
 271 #define DPA3U   (MPU1_SR[27])
 272
 273 #define PPC_PPE 0x1
 274 #define SPAL_SPE 0x1
 275 #define SPAL_SPS 0x10
 276
 277 #define VIP     (MPU0_SR[0])
 278 #define VMECR   (MPU0_SR[4])
 279 #define VMTID   (MPU0_SR[5])
 280 #define VMADR   (MPU0_SR[6])
 281 #define VPECR   (MPU0_SR[8])
 282 #define VPTID   (MPU0_SR[9])
 283 #define VPADR   (MPU0_SR[10])
 284 #define VDECR   (MPU0_SR[12])
 285 #define VDTID   (MPU0_SR[13])
 286
 287 #define MPM_AUE 0x2
 288 #define MPM_MPE 0x1
 289
 290 #define VMECR_VMX   0x2
 291 #define VMECR_VMR   0x4
 292 #define VMECR_VMW   0x8
 293 #define VMECR_VMS   0x10
 294 #define VMECR_VMRMW 0x20
 295 #define VMECR_VMMS  0x40
 296
 297 #define IPA2ADDR(IPA)   ((IPA) & 0x1fffff80)
 298 #define IPA_IPE 0x1
 299 #define IPA_IPX 0x2
 300 #define IPA_IPR 0x4
 301 #define IPE0    (IPA0L & IPA_IPE)
 302 #define IPE1    (IPA1L & IPA_IPE)
 303 #define IPE2    (IPA2L & IPA_IPE)
 304 #define IPE3    (IPA3L & IPA_IPE)
 305 #define IPX0    (IPA0L & IPA_IPX)
 306 #define IPX1    (IPA1L & IPA_IPX)
 307 #define IPX2    (IPA2L & IPA_IPX)
 308 #define IPX3    (IPA3L & IPA_IPX)
 309 #define IPR0    (IPA0L & IPA_IPR)
 310 #define IPR1    (IPA1L & IPA_IPR)
 311 #define IPR2    (IPA2L & IPA_IPR)
 312 #define IPR3    (IPA3L & IPA_IPR)
 313
 314 #define DPA2ADDR(DPA)   ((DPA) & 0x1fffff80)
 315 #define DPA_DPE 0x1
 316 #define DPA_DPR 0x4
 317 #define DPA_DPW 0x8
 318 #define DPE0    (DPA0L & DPA_DPE)
 319 #define DPE1    (DPA1L & DPA_DPE)
 320 #define DPE2    (DPA2L & DPA_DPE)
 321 #define DPE3    (DPA3L & DPA_DPE)
 322 #define DPR0    (DPA0L & DPA_DPR)
 323 #define DPR1    (DPA1L & DPA_DPR)
 324 #define DPR2    (DPA2L & DPA_DPR)
 325 #define DPR3    (DPA3L & DPA_DPR)
 326 #define DPW0    (DPA0L & DPA_DPW)
 327 #define DPW1    (DPA1L & DPA_DPW)
 328 #define DPW2    (DPA2L & DPA_DPW)
 329 #define DPW3    (DPA3L & DPA_DPW)
 330
 331 #define DCC_DCE0 0x1
 332 #define DCC_DCE1 0x10000
 333
 334 #define PPA2ADDR(PPA)   ((PPA) & 0x1fffff80)
 335 #define PPC_PPC 0xfffffffe
 336 #define PPC_PPE 0x1
 337 #define PPC_PPM 0x0000fff8
 338
 339
 340 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 341
 342 /* sign-extend a 4-bit number */
 343 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 344
 345 /* sign-extend a 5-bit number */
 346 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 347
 348 /* sign-extend a 9-bit number */
 349 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 350
 351 /* sign-extend a 22-bit number */
 352 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 353
 354 /* sign extend a 40 bit number */
 355 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 356                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 357                          + UNSIGNED64 (0x8000000000))
 358
 359 /* sign extend a 44 bit number */
 360 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 361                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 362                          + UNSIGNED64 (0x80000000000))
 363
 364 /* sign extend a 60 bit number */
 365 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 366                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 367                          + UNSIGNED64 (0x800000000000000))
 368
 369 /* No sign extension */
 370 #define NOP(x)          (x)
 371
 372 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 373
 374 #define RLW(x) load_mem (x, 4)
 375
 376 /* Function declarations.  */
 377
 378 #define IMEM16(EA) \
 379 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 380
 381 #define IMEM16_IMMED(EA,N) \
 382 sim_core_read_aligned_2 (STATE_CPU (SD, 0), \
 383                          PC, exec_map, (EA) + (N) * 2)
 384
 385 #define load_mem(ADDR,LEN) \
 386 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 387                                PC, read_map, (ADDR))
 388
 389 #define store_mem(ADDR,LEN,DATA) \
 390 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 391                                 PC, write_map, (ADDR), (DATA))
 392
 393
 394 /* compare cccc field against PSW */
 395 int condition_met (unsigned code);
 396
 397
 398 /* Debug/tracing calls */
 399
 400 enum op_types
 401 {
 402   OP_UNKNOWN,
 403   OP_NONE,
 404   OP_TRAP,
 405   OP_REG,
 406   OP_REG_REG,
 407   OP_REG_REG_CMP,
 408   OP_REG_REG_MOVE,
 409   OP_IMM_REG,
 410   OP_IMM_REG_CMP,
 411   OP_IMM_REG_MOVE,
 412   OP_COND_BR,
 413   OP_LOAD16,
 414   OP_STORE16,
 415   OP_LOAD32,
 416   OP_STORE32,
 417   OP_JUMP,
 418   OP_IMM_REG_REG,
 419   OP_UIMM_REG_REG,
 420   OP_IMM16_REG_REG,
 421   OP_UIMM16_REG_REG,
 422   OP_BIT,
 423   OP_EX1,
 424   OP_EX2,
 425   OP_LDSR,
 426   OP_STSR,
 427   OP_BIT_CHANGE,
 428   OP_REG_REG_REG,
 429   OP_REG_REG3,
 430   OP_IMM_REG_REG_REG,
 431   OP_PUSHPOP1,
 432   OP_PUSHPOP2,
 433   OP_PUSHPOP3,
 434 };
 435
 436 #if WITH_TRACE_ANY_P
 437 void trace_input (char *name, enum op_types type, int size);
 438 void trace_output (enum op_types result);
 439 void trace_result (int has_result, uint32_t result);
 440
 441 extern int trace_num_values;
 442 extern uint32_t trace_values[];
 443 extern uint32_t trace_pc;
 444 extern const char *trace_name;
 445 extern int trace_module;
 446
 447 #define TRACE_BRANCH0() \
 448 do { \
 449   if (TRACE_BRANCH_P (CPU)) { \
 450     trace_module = TRACE_BRANCH_IDX; \
 451     trace_pc = cia; \
 452     trace_name = itable[MY_INDEX].name; \
 453     trace_num_values = 0; \
 454     trace_result (1, (nia)); \
 455   } \
 456 } while (0)
 457
 458 #define TRACE_BRANCH1(IN1) \
 459 do { \
 460   if (TRACE_BRANCH_P (CPU)) { \
 461     trace_module = TRACE_BRANCH_IDX; \
 462     trace_pc = cia; \
 463     trace_name = itable[MY_INDEX].name; \
 464     trace_values[0] = (IN1); \
 465     trace_num_values = 1; \
 466     trace_result (1, (nia)); \
 467   } \
 468 } while (0)
 469
 470 #define TRACE_BRANCH2(IN1, IN2) \
 471 do { \
 472   if (TRACE_BRANCH_P (CPU)) { \
 473     trace_module = TRACE_BRANCH_IDX; \
 474     trace_pc = cia; \
 475     trace_name = itable[MY_INDEX].name; \
 476     trace_values[0] = (IN1); \
 477     trace_values[1] = (IN2); \
 478     trace_num_values = 2; \
 479     trace_result (1, (nia)); \
 480   } \
 481 } while (0)
 482
 483 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 484 do { \
 485   if (TRACE_BRANCH_P (CPU)) { \
 486     trace_module = TRACE_BRANCH_IDX; \
 487     trace_pc = cia; \
 488     trace_name = itable[MY_INDEX].name; \
 489     trace_values[0] = (IN1); \
 490     trace_values[1] = (IN2); \
 491     trace_values[2] = (IN3); \
 492     trace_num_values = 3; \
 493     trace_result (1, (nia)); \
 494   } \
 495 } while (0)
 496
 497 #define TRACE_LD(ADDR,RESULT) \
 498 do { \
 499   if (TRACE_MEMORY_P (CPU)) { \
 500     trace_module = TRACE_MEMORY_IDX; \
 501     trace_pc = cia; \
 502     trace_name = itable[MY_INDEX].name; \
 503     trace_values[0] = (ADDR); \
 504     trace_num_values = 1; \
 505     trace_result (1, (RESULT)); \
 506   } \
 507 } while (0)
 508
 509 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
 510 do { \
 511   if (TRACE_MEMORY_P (CPU)) { \
 512     trace_module = TRACE_MEMORY_IDX; \
 513     trace_pc = cia; \
 514     trace_name = (NAME); \
 515     trace_values[0] = (ADDR); \
 516     trace_num_values = 1; \
 517     trace_result (1, (RESULT)); \
 518   } \
 519 } while (0)
 520
 521 #define TRACE_ST(ADDR,RESULT) \
 522 do { \
 523   if (TRACE_MEMORY_P (CPU)) { \
 524     trace_module = TRACE_MEMORY_IDX; \
 525     trace_pc = cia; \
 526     trace_name = itable[MY_INDEX].name; \
 527     trace_values[0] = (ADDR); \
 528     trace_num_values = 1; \
 529     trace_result (1, (RESULT)); \
 530   } \
 531 } while (0)
 532
 533 #define TRACE_FP_INPUT_FPU1(V0) \
 534 do { \
 535   if (TRACE_FPU_P (CPU)) \
 536     { \
 537       uint64_t f0; \
 538       sim_fpu_to64 (&f0, (V0)); \
 539       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 540     } \
 541 } while (0)
 542
 543 #define TRACE_FP_INPUT_FPU2(V0, V1) \
 544 do { \
 545   if (TRACE_FPU_P (CPU)) \
 546     { \
 547       uint64_t f0, f1; \
 548       sim_fpu_to64 (&f0, (V0)); \
 549       sim_fpu_to64 (&f1, (V1)); \
 550       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
 551     } \
 552 } while (0)
 553
 554 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
 555 do { \
 556   if (TRACE_FPU_P (CPU)) \
 557     { \
 558       uint64_t f0, f1, f2; \
 559       sim_fpu_to64 (&f0, (V0)); \
 560       sim_fpu_to64 (&f1, (V1)); \
 561       sim_fpu_to64 (&f2, (V2)); \
 562       trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
 563     } \
 564 } while (0)
 565
 566 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
 567 do { \
 568   if (TRACE_FPU_P (CPU)) \
 569     { \
 570       int d0 = (V0); \
 571       uint64_t f1, f2; \
 572       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
 573       TRACE_IDX (data) = TRACE_FPU_IDX; \
 574       sim_fpu_to64 (&f1, (V1)); \
 575       sim_fpu_to64 (&f2, (V2)); \
 576       save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
 577       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
 578       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
 579     } \
 580 } while (0)
 581
 582 #define TRACE_FP_INPUT_WORD2(V0, V1) \
 583 do { \
 584   if (TRACE_FPU_P (CPU)) \
 585     trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
 586 } while (0)
 587
 588 #define TRACE_FP_RESULT_FPU1(R0) \
 589 do { \
 590   if (TRACE_FPU_P (CPU)) \
 591     { \
 592       uint64_t f0; \
 593       sim_fpu_to64 (&f0, (R0)); \
 594       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 595     } \
 596 } while (0)
 597
 598 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
 599
 600 #define TRACE_FP_RESULT_WORD2(R0, R1) \
 601 do { \
 602   if (TRACE_FPU_P (CPU)) \
 603     trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
 604 } while (0)
 605
 606 #else
 607 #define trace_input(NAME, IN1, IN2)
 608 #define trace_output(RESULT)
 609 #define trace_result(HAS_RESULT, RESULT)
 610
 611 #define TRACE_BRANCH0()
 612 #define TRACE_BRANCH1(IN1)
 613 #define TRACE_BRANCH2(IN1, IN2)
 614 #define TRACE_BRANCH3(IN1, IN2, IN3)
 615
 616 #define TRACE_LD(ADDR,RESULT)
 617 #define TRACE_ST(ADDR,RESULT)
 618
 619 #endif
 620
 621 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
 622 #define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 623
 624 extern void divun ( unsigned int       N,
 625                     unsigned long int  als,
 626                     unsigned long int  sfi,
 627                     uint32_t /*unsigned long int*/ *  quotient_ptr,
 628                     uint32_t /*unsigned long int*/ *  remainder_ptr,
 629                     int *overflow_ptr
 630                     );
 631 extern void divn ( unsigned int       N,
 632                    unsigned long int  als,
 633                    unsigned long int  sfi,
 634                    int32_t /*signed long int*/ *  quotient_ptr,
 635                    int32_t /*signed long int*/ *  remainder_ptr,
 636                    int *overflow_ptr
 637                    );
 638 extern int type1_regs[];
 639 extern int type2_regs[];
 640 extern int type3_regs[];
 641
 642 #define SESR_OV   (1 << 0)
 643 #define SESR_SOV  (1 << 1)
 644
 645 #define SESR      (State.sregs[12])
 646
 647 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
 648 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
 649 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
 650 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
 651
 652 #define SAT16(X)                        \
 653   do                                    \
 654     {                                   \
 655       int64_t z = (X);                  \
 656       if (z > 0x7fff)                   \
 657         {                               \
 658           SESR |= SESR_OV | SESR_SOV;   \
 659           z = 0x7fff;                   \
 660         }                               \
 661       else if (z < -0x8000)             \
 662         {                               \
 663           SESR |= SESR_OV | SESR_SOV;   \
 664           z = - 0x8000;                 \
 665         }                               \
 666       (X) = z;                          \
 667     }                                   \
 668   while (0)
 669
 670 #define SAT32(X)                        \
 671   do                                    \
 672     {                                   \
 673       int64_t z = (X);                  \
 674       if (z > 0x7fffffff)               \
 675         {                               \
 676           SESR |= SESR_OV | SESR_SOV;   \
 677           z = 0x7fffffff;               \
 678         }                               \
 679       else if (z < -0x80000000)         \
 680         {                               \
 681           SESR |= SESR_OV | SESR_SOV;   \
 682           z = - 0x80000000;             \
 683         }                               \
 684       (X) = z;                          \
 685     }                                   \
 686   while (0)
 687
 688 #define ABS16(X)                        \
 689   do                                    \
 690     {                                   \
 691       int64_t z = (X) & 0xffff; \
 692       if (z == 0x8000)                  \
 693         {                               \
 694           SESR |= SESR_OV | SESR_SOV;   \
 695           z = 0x7fff;                   \
 696         }                               \
 697       else if (z & 0x8000)              \
 698         {                               \
 699           z = (- z) & 0xffff;           \
 700         }                               \
 701       (X) = z;                          \
 702     }                                   \
 703   while (0)
 704
 705 #define ABS32(X)                        \
 706   do                                    \
 707     {                                   \
 708       int64_t z = (X) & 0xffffffff;     \
 709       if (z == 0x80000000)              \
 710         {                               \
 711           SESR |= SESR_OV | SESR_SOV;   \
 712           z = 0x7fffffff;               \
 713         }                               \
 714       else if (z & 0x80000000)          \
 715         {                               \
 716           z = (- z) & 0xffffffff;       \
 717         }                               \
 718       (X) = z;                          \
 719     }                                   \
 720   while (0)
 721
 722 #endif