| blob | 49dfc5338e45fd1df518cc8781e918444dc1831e |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2015 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
33 /* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35 #define RELOC_SECTION(HTAB, NAME) \
38 /* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40 #define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
45 /* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47 #define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
52 /* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54 #define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
59 #define elf_info_to_howto 0
60 #define elf_info_to_howto_rel elf32_arm_info_to_howto
62 #define ARM_ELF_ABI_VERSION 0
63 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65 /* The Adjusted Place, as defined by AAELF. */
66 #define Pa(X) ((X) & 0xfffffffc)
73 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
78 {
79 /* No relocation. */
108 /* 32 bit absolute */
123 /* standard 32bit pc-relative reloc */
138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
153 /* 16 bit absolute */
168 /* 12 bit absolute */
197 /* 8 bit absolute */
296 /* BLX instruction for the ARM. */
311 /* BLX instruction for the Thumb. */
326 /* Dynamic TLS relocations. */
370 /* Relocs used in ARM Linux */
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
893 /* Group relocations. */
1273 /* End of group relocations. */
1487 /* GNU extension to record C++ vtable member usage */
1502 /* GNU extension to record C++ vtable hierarchy */
1545 /* TLS relocations */
1658 /* 112-127 private relocations. */
1676 /* R_ARM_ME_TOO, obsolete. */
1692 };
1694 /* 160 onwards: */
1696 {
1710 };
1712 /* 249-255 extended, currently unused, relocations: */
1714 {
1770 };
1774 {
1786 }
1788 static void
1791 {
1796 }
1798 struct elf32_arm_reloc_map
1799 {
1800 bfd_reloc_code_real_type bfd_reloc_val;
1802 };
1804 /* All entries in this list must also be present in elf32_arm_howto_table. */
1806 {
1893 };
1897 bfd_reloc_code_real_type code)
1898 {
1906 }
1911 {
1930 }
1932 /* Support for core dump NOTE sections. */
1934 static bfd_boolean
1936 {
1941 {
1946 /* pr_cursig */
1949 /* pr_pid */
1952 /* pr_reg */
1957 }
1959 /* Make a ".reg/999" section. */
1962 }
1964 static bfd_boolean
1966 {
1968 {
1979 }
1981 /* Note that for some reason, a spurious space is tacked
1982 onto the end of the args in some (at least one anyway)
1983 implementations, so strip it off if it exists. */
1984 {
1990 }
1993 }
1998 {
2000 {
2005 {
2017 }
2020 {
2039 }
2040 }
2041 }
2043 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2045 #define TARGET_BIG_SYM arm_elf32_be_vec
2048 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2049 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2050 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2055 /* In lieu of proper flags, assume all EABIv4 or later objects are
2056 interworkable. */
2057 #define INTERWORK_FLAG(abfd) \
2058 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2059 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2060 || ((abfd)->flags & BFD_LINKER_CREATED))
2062 /* The linker script knows the section names for placement.
2063 The entry_names are used to do simple name mangling on the stubs.
2064 Given a function name, and its type, the stub can be found. The
2065 name can be changed. The only requirement is the %s be present. */
2083 /* The name of the dynamic interpreter. This is put in the .interp
2084 section. */
2088 {
2092 };
2095 {
2103 + dl_tlsdesc_lazy_resolver(GOT) */
2105 };
2107 #ifdef FOUR_WORD_PLT
2109 /* The first entry in a procedure linkage table looks like
2110 this. It is set up so that any shared library function that is
2111 called before the relocation has been set up calls the dynamic
2112 linker first. */
2114 {
2119 };
2121 /* Subsequent entries in a procedure linkage table look like
2122 this. */
2124 {
2129 };
2133 /* The first entry in a procedure linkage table looks like
2134 this. It is set up so that any shared library function that is
2135 called before the relocation has been set up calls the dynamic
2136 linker first. */
2138 {
2144 };
2146 /* By default subsequent entries in a procedure linkage table look like
2147 this. Offsets that don't fit into 28 bits will cause link error. */
2149 {
2153 };
2155 /* When explicitly asked, we'll use this "long" entry format
2156 which can cope with arbitrary displacements. */
2158 {
2163 };
2169 /* The first entry in a procedure linkage table looks like this.
2170 It is set up so that any shared library function that is called before the
2171 relocation has been set up calls the dynamic linker first. */
2173 {
2174 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2175 an instruction maybe encoded to one or two array elements. */
2178 /* add lr, pc */
2181 };
2183 /* Subsequent entries in a procedure linkage table for thumb only target
2184 look like this. */
2186 {
2187 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2188 an instruction maybe encoded to one or two array elements. */
2193 /* nop */
2194 };
2196 /* The format of the first entry in the procedure linkage table
2197 for a VxWorks executable. */
2199 {
2204 };
2206 /* The format of subsequent entries in a VxWorks executable. */
2208 {
2215 };
2217 /* The format of entries in a VxWorks shared library. */
2219 {
2226 };
2228 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2229 #define PLT_THUMB_STUB_SIZE 4
2231 {
2234 };
2236 /* The entries in a PLT when using a DLL-based target with multiple
2237 address spaces. */
2239 {
2242 };
2244 /* The first entry in a procedure linkage table looks like
2245 this. It is set up so that any shared library function that is
2246 called before the relocation has been set up calls the dynamic
2247 linker first. */
2249 {
2250 /* First bundle: */
2255 /* Second bundle: */
2260 /* Third bundle: */
2264 /* .Lplt_tail: */
2266 /* Fourth bundle: */
2271 };
2272 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2274 /* Subsequent entries in a procedure linkage table look like this. */
2276 {
2281 };
2283 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2284 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2285 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2286 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2287 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2288 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2289 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2290 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2292 enum stub_insn_type
2293 {
2295 THUMB32_TYPE,
2296 ARM_TYPE,
2297 DATA_TYPE
2298 };
2300 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2301 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2302 is inserted in arm_build_one_stub(). */
2303 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2304 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2305 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2306 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2307 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2308 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2311 {
2312 bfd_vma data;
2318 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2319 to reach the stub if necessary. */
2321 {
2324 };
2326 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2327 available. */
2329 {
2333 };
2335 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2337 {
2345 };
2347 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2348 allowed. */
2350 {
2356 };
2358 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2359 available. */
2361 {
2366 };
2368 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2369 one, when the destination is close enough. */
2371 {
2375 };
2377 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2378 blx to reach the stub if necessary. */
2380 {
2384 };
2386 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2387 blx to reach the stub if necessary. We can not add into pc;
2388 it is not guaranteed to mode switch (different in ARMv6 and
2389 ARMv7). */
2391 {
2396 };
2398 /* V4T ARM -> ARM long branch stub, PIC. */
2400 {
2405 };
2407 /* V4T Thumb -> ARM long branch stub, PIC. */
2409 {
2415 };
2417 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2418 architectures. */
2420 {
2428 };
2430 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2431 allowed. */
2433 {
2440 };
2442 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2443 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2445 {
2449 };
2451 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2452 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2454 {
2460 };
2462 /* NaCl ARM -> ARM long branch stub. */
2464 {
2473 };
2475 /* NaCl ARM -> ARM long branch stub, PIC. */
2477 {
2486 };
2489 /* Cortex-A8 erratum-workaround stubs. */
2491 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2492 can't use a conditional branch to reach this stub). */
2495 {
2499 };
2501 /* Stub used for b.w and bl.w instructions. */
2504 {
2506 };
2509 {
2511 };
2513 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2514 instruction (which switches to ARM mode) to point to this stub. Jump to the
2515 real destination using an ARM-mode branch. */
2518 {
2520 };
2522 /* For each section group there can be a specially created linker section
2523 to hold the stubs for that group. The name of the stub section is based
2524 upon the name of another section within that group with the suffix below
2525 applied.
2527 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2528 create what appeared to be a linker stub section when it actually
2529 contained user code/data. For example, consider this fragment:
2531 const char * stubborn_problems[] = { "np" };
2533 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2534 section called:
2536 .data.rel.local.stubborn_problems
2538 This then causes problems in arm32_arm_build_stubs() as it triggers:
2540 // Ignore non-stub sections.
2541 if (!strstr (stub_sec->name, STUB_SUFFIX))
2542 continue;
2544 And so the section would be ignored instead of being processed. Hence
2545 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2546 C identifier. */
2549 /* One entry per long/short branch stub defined above. */
2550 #define DEF_STUBS \
2551 DEF_STUB(long_branch_any_any) \
2552 DEF_STUB(long_branch_v4t_arm_thumb) \
2553 DEF_STUB(long_branch_thumb_only) \
2554 DEF_STUB(long_branch_v4t_thumb_thumb) \
2555 DEF_STUB(long_branch_v4t_thumb_arm) \
2556 DEF_STUB(short_branch_v4t_thumb_arm) \
2557 DEF_STUB(long_branch_any_arm_pic) \
2558 DEF_STUB(long_branch_any_thumb_pic) \
2559 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2560 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2561 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2562 DEF_STUB(long_branch_thumb_only_pic) \
2563 DEF_STUB(long_branch_any_tls_pic) \
2564 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2565 DEF_STUB(long_branch_arm_nacl) \
2566 DEF_STUB(long_branch_arm_nacl_pic) \
2567 DEF_STUB(a8_veneer_b_cond) \
2568 DEF_STUB(a8_veneer_b) \
2569 DEF_STUB(a8_veneer_bl) \
2570 DEF_STUB(a8_veneer_blx)
2572 #define DEF_STUB(x) arm_stub_##x,
2573 enum elf32_arm_stub_type
2574 {
2575 arm_stub_none,
2576 DEF_STUBS
2577 /* Note the first a8_veneer type. */
2578 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2579 };
2580 #undef DEF_STUB
2583 {
2588 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2590 {
2592 DEF_STUBS
2593 };
2595 struct elf32_arm_stub_hash_entry
2596 {
2597 /* Base hash table entry structure. */
2600 /* The stub section. */
2603 /* Offset within stub_sec of the beginning of this stub. */
2604 bfd_vma stub_offset;
2606 /* Given the symbol's value and its section we can determine its final
2607 value when building the stubs (so the stub knows where to jump). */
2608 bfd_vma target_value;
2611 /* Offset to apply to relocation referencing target_value. */
2612 bfd_vma target_addend;
2614 /* The instruction which caused this stub to be generated (only valid for
2615 Cortex-A8 erratum workaround stubs at present). */
2618 /* The stub type. */
2620 /* Its encoding size in bytes. */
2622 /* Its template. */
2624 /* The size of the template (number of entries). */
2627 /* The symbol table entry, if any, that this was derived from. */
2630 /* Type of branch. */
2633 /* Where this stub is being called from, or, in the case of combined
2634 stub sections, the first input section in the group. */
2637 /* The name for the local symbol at the start of this stub. The
2638 stub name in the hash table has to be unique; this does not, so
2639 it can be friendlier. */
2641 };
2643 /* Used to build a map of a section. This is required for mixed-endian
2644 code/data. */
2647 {
2648 bfd_vma vma;
2650 }
2651 elf32_arm_section_map;
2653 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2656 {
2657 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2658 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2659 VFP11_ERRATUM_ARM_VENEER,
2660 VFP11_ERRATUM_THUMB_VENEER
2661 }
2662 elf32_vfp11_erratum_type;
2665 {
2667 bfd_vma vma;
2668 union
2669 {
2670 struct
2671 {
2675 struct
2676 {
2681 elf32_vfp11_erratum_type type;
2682 }
2683 elf32_vfp11_erratum_list;
2685 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2686 veneer. */
2688 {
2689 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2690 STM32L4XX_ERRATUM_VENEER
2691 }
2692 elf32_stm32l4xx_erratum_type;
2695 {
2697 bfd_vma vma;
2698 union
2699 {
2700 struct
2701 {
2705 struct
2706 {
2711 elf32_stm32l4xx_erratum_type type;
2712 }
2713 elf32_stm32l4xx_erratum_list;
2716 {
2717 DELETE_EXIDX_ENTRY,
2718 INSERT_EXIDX_CANTUNWIND_AT_END
2719 }
2720 arm_unwind_edit_type;
2722 /* A (sorted) list of edits to apply to an unwind table. */
2724 {
2725 arm_unwind_edit_type type;
2726 /* Note: we sometimes want to insert an unwind entry corresponding to a
2727 section different from the one we're currently writing out, so record the
2728 (text) section this edit relates to here. */
2732 }
2733 arm_unwind_table_edit;
2736 {
2737 /* Information about mapping symbols. */
2742 /* Information about CPU errata. */
2747 /* Information about unwind tables. */
2748 union
2749 {
2750 /* Unwind info attached to a text section. */
2751 struct
2752 {
2756 /* Unwind info attached to an .ARM.exidx section. */
2757 struct
2758 {
2763 }
2764 _arm_elf_section_data;
2766 #define elf32_arm_section_data(sec) \
2767 ((_arm_elf_section_data *) elf_section_data (sec))
2769 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2770 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2771 so may be created multiple times: we use an array of these entries whilst
2772 relaxing which we can refresh easily, then create stubs for each potentially
2773 erratum-triggering instruction once we've settled on a solution. */
2775 struct a8_erratum_fix
2776 {
2779 bfd_vma offset;
2780 bfd_vma addend;
2785 };
2787 /* A table of relocs applied to branches which might trigger Cortex-A8
2788 erratum. */
2790 struct a8_erratum_reloc
2791 {
2792 bfd_vma from;
2793 bfd_vma destination;
2798 bfd_boolean non_a8_stub;
2799 };
2801 /* The size of the thread control block. */
2802 #define TCB_SIZE 8
2804 /* ARM-specific information about a PLT entry, over and above the usual
2805 gotplt_union. */
2806 struct arm_plt_info
2807 {
2808 /* We reference count Thumb references to a PLT entry separately,
2809 so that we can emit the Thumb trampoline only if needed. */
2810 bfd_signed_vma thumb_refcount;
2812 /* Some references from Thumb code may be eliminated by BL->BLX
2813 conversion, so record them separately. */
2814 bfd_signed_vma maybe_thumb_refcount;
2816 /* How many of the recorded PLT accesses were from non-call relocations.
2817 This information is useful when deciding whether anything takes the
2818 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2819 non-call references to the function should resolve directly to the
2820 real runtime target. */
2823 /* Since PLT entries have variable size if the Thumb prologue is
2824 used, we need to record the index into .got.plt instead of
2825 recomputing it from the PLT offset. */
2826 bfd_signed_vma got_offset;
2827 };
2829 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
2830 struct arm_local_iplt_info
2831 {
2832 /* The information that is usually found in the generic ELF part of
2833 the hash table entry. */
2836 /* The information that is usually found in the ARM-specific part of
2837 the hash table entry. */
2840 /* A list of all potential dynamic relocations against this symbol. */
2842 };
2844 struct elf_arm_obj_tdata
2845 {
2848 /* tls_type for each local got entry. */
2851 /* GOTPLT entries for TLS descriptors. */
2854 /* Information for local symbols that need entries in .iplt. */
2857 /* Zero to warn when linking objects with incompatible enum sizes. */
2860 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2862 };
2864 #define elf_arm_tdata(bfd) \
2865 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2867 #define elf32_arm_local_got_tls_type(bfd) \
2868 (elf_arm_tdata (bfd)->local_got_tls_type)
2870 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2871 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2873 #define elf32_arm_local_iplt(bfd) \
2874 (elf_arm_tdata (bfd)->local_iplt)
2876 #define is_arm_elf(bfd) \
2877 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2878 && elf_tdata (bfd) != NULL \
2879 && elf_object_id (bfd) == ARM_ELF_DATA)
2881 static bfd_boolean
2883 {
2885 ARM_ELF_DATA);
2886 }
2888 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2890 /* Arm ELF linker hash entry. */
2891 struct elf32_arm_link_hash_entry
2892 {
2895 /* Track dynamic relocs copied for this symbol. */
2898 /* ARM-specific PLT information. */
2901 #define GOT_UNKNOWN 0
2902 #define GOT_NORMAL 1
2903 #define GOT_TLS_GD 2
2904 #define GOT_TLS_IE 4
2905 #define GOT_TLS_GDESC 8
2906 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2909 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2914 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2915 starting at the end of the jump table. */
2916 bfd_vma tlsdesc_got;
2918 /* The symbol marking the real symbol location for exported thumb
2919 symbols with Arm stubs. */
2922 /* A pointer to the most recently used stub hash entry against this
2923 symbol. */
2925 };
2927 /* Traverse an arm ELF linker hash table. */
2928 #define elf32_arm_link_hash_traverse(table, func, info) \
2929 (elf_link_hash_traverse \
2930 (&(table)->root, \
2931 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2932 (info)))
2934 /* Get the ARM elf linker hash table from a link_info structure. */
2935 #define elf32_arm_hash_table(info) \
2936 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2937 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2939 #define arm_stub_hash_lookup(table, string, create, copy) \
2940 ((struct elf32_arm_stub_hash_entry *) \
2941 bfd_hash_lookup ((table), (string), (create), (copy)))
2943 /* Array to keep track of which stub sections have been created, and
2944 information on stub grouping. */
2945 struct map_stub
2946 {
2947 /* This is the section to which stubs in the group will be
2948 attached. */
2950 /* The stub section. */
2952 };
2954 #define elf32_arm_compute_jump_table_size(htab) \
2955 ((htab)->next_tls_desc_index * 4)
2957 /* ARM ELF linker hash table. */
2958 struct elf32_arm_link_hash_table
2959 {
2960 /* The main hash table. */
2963 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2964 bfd_size_type thumb_glue_size;
2966 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2967 bfd_size_type arm_glue_size;
2969 /* The size in bytes of section containing the ARMv4 BX veneers. */
2970 bfd_size_type bx_glue_size;
2972 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2973 veneer has been populated. */
2976 /* The size in bytes of the section containing glue for VFP11 erratum
2977 veneers. */
2978 bfd_size_type vfp11_erratum_glue_size;
2980 /* The size in bytes of the section containing glue for STM32L4XX erratum
2981 veneers. */
2982 bfd_size_type stm32l4xx_erratum_glue_size;
2984 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2985 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2986 elf32_arm_write_section(). */
2990 /* An arbitrary input BFD chosen to hold the glue sections. */
2993 /* Nonzero to output a BE8 image. */
2996 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2997 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3000 /* The relocation to use for R_ARM_TARGET2 relocations. */
3003 /* 0 = Ignore R_ARM_V4BX.
3004 1 = Convert BX to MOV PC.
3005 2 = Generate v4 interworing stubs. */
3008 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3011 /* Whether we should fix the ARM1176 BLX immediate issue. */
3014 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3017 /* What sort of code sequences we should look for which may trigger the
3018 VFP11 denorm erratum. */
3019 bfd_arm_vfp11_fix vfp11_fix;
3021 /* Global counter for the number of fixes we have emitted. */
3024 /* What sort of code sequences we should look for which may trigger the
3025 STM32L4XX erratum. */
3026 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3028 /* Global counter for the number of fixes we have emitted. */
3031 /* Nonzero to force PIC branch veneers. */
3034 /* The number of bytes in the initial entry in the PLT. */
3035 bfd_size_type plt_header_size;
3037 /* The number of bytes in the subsequent PLT etries. */
3038 bfd_size_type plt_entry_size;
3040 /* True if the target system is VxWorks. */
3043 /* True if the target system is Symbian OS. */
3046 /* True if the target system is Native Client. */
3049 /* True if the target uses REL relocations. */
3052 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3053 bfd_vma next_tls_desc_index;
3055 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3056 bfd_vma num_tls_desc;
3058 /* Short-cuts to get to dynamic linker sections. */
3062 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3065 /* The offset into splt of the PLT entry for the TLS descriptor
3066 resolver. Special values are 0, if not necessary (or not found
3067 to be necessary yet), and -1 if needed but not determined
3068 yet. */
3069 bfd_vma dt_tlsdesc_plt;
3071 /* The offset into sgot of the GOT entry used by the PLT entry
3072 above. */
3073 bfd_vma dt_tlsdesc_got;
3075 /* Offset in .plt section of tls_arm_trampoline. */
3076 bfd_vma tls_trampoline;
3078 /* Data for R_ARM_TLS_LDM32 relocations. */
3079 union
3080 {
3081 bfd_signed_vma refcount;
3082 bfd_vma offset;
3085 /* Small local sym cache. */
3088 /* For convenience in allocate_dynrelocs. */
3091 /* The amount of space used by the reserved portion of the sgotplt
3092 section, plus whatever space is used by the jump slots. */
3093 bfd_vma sgotplt_jump_table_size;
3095 /* The stub hash table. */
3098 /* Linker stub bfd. */
3101 /* Linker call-backs. */
3105 /* Array to keep track of which stub sections have been created, and
3106 information on stub grouping. */
3109 /* Number of elements in stub_group. */
3112 /* Assorted information used by elf32_arm_size_stubs. */
3116 };
3120 {
3121 #if GCC_VERSION >= 3004
3123 #else
3127 {
3131 }
3133 #endif
3134 }
3138 {
3139 #if GCC_VERSION >= 3004
3141 #else
3145 {
3147 sum++;
3149 }
3151 #endif
3152 }
3154 /* Create an entry in an ARM ELF linker hash table. */
3160 {
3164 /* Allocate the structure if it has not already been allocated by a
3165 subclass. */
3172 /* Call the allocation method of the superclass. */
3177 {
3189 }
3192 }
3194 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3195 symbols. */
3197 static bfd_boolean
3199 {
3201 {
3202 bfd_size_type num_syms;
3203 bfd_size_type size;
3225 }
3227 }
3229 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3230 to input bfd ABFD. Create the information if it doesn't already exist.
3231 Return null if an allocation fails. */
3235 {
3246 }
3248 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3249 in ABFD's symbol table. If the symbol is global, H points to its
3250 hash table entry, otherwise H is null.
3252 Return true if the symbol does have PLT information. When returning
3253 true, point *ROOT_PLT at the target-independent reference count/offset
3254 union and *ARM_PLT at the ARM-specific information. */
3256 static bfd_boolean
3260 {
3264 {
3268 }
3280 }
3282 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3283 before it. */
3285 static bfd_boolean
3288 {
3294 }
3296 /* Return a pointer to the head of the dynamic reloc list that should
3297 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3298 ABFD's symbol table. Return null if an error occurs. */
3303 {
3305 {
3312 }
3313 else
3314 {
3315 /* Track dynamic relocs needed for local syms too.
3316 We really need local syms available to do this
3317 easily. Oh well. */
3327 }
3328 }
3330 /* Initialize an entry in the stub hash table. */
3336 {
3337 /* Allocate the structure if it has not already been allocated by a
3338 subclass. */
3340 {
3345 }
3347 /* Call the allocation method of the superclass. */
3350 {
3353 /* Initialize the local fields. */
3368 }
3371 }
3373 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3374 shortcuts to them in our hash table. */
3376 static bfd_boolean
3378 {
3385 /* BPABI objects never have a GOT, or associated sections. */
3393 }
3395 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3397 static bfd_boolean
3399 {
3404 flagword flags;
3412 {
3419 }
3422 {
3430 }
3433 {
3439 }
3441 }
3443 /* Determine if we're dealing with a Thumb only architecture. */
3445 static bfd_boolean
3447 {
3449 Tag_CPU_arch);
3459 Tag_CPU_arch_profile);
3462 }
3464 /* Determine if we're dealing with a Thumb-2 object. */
3466 static bfd_boolean
3468 {
3470 Tag_CPU_arch);
3472 }
3474 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3475 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3476 hash table. */
3478 static bfd_boolean
3480 {
3499 {
3504 {
3506 htab->plt_entry_size
3508 }
3509 else
3510 {
3511 htab->plt_header_size
3513 htab->plt_entry_size
3515 }
3516 }
3517 else
3518 {
3519 /* PR ld/16017
3520 Test for thumb only architectures. Note - we cannot just call
3521 using_thumb_only() as the attributes in the output bfd have not been
3522 initialised at this point, so instead we use the input bfd. */
3527 {
3530 }
3532 }
3541 }
3543 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3545 static void
3549 {
3556 {
3558 {
3562 /* Add reloc counts against the indirect sym to the direct sym
3563 list. Merge any entries against the same section. */
3565 {
3570 {
3575 }
3578 }
3580 }
3584 }
3587 {
3588 /* Copy over PLT info. */
3596 /* We should only allocate a function to .iplt once the final
3597 symbol information is known. */
3601 {
3604 }
3605 }
3608 }
3610 /* Destroy an ARM elf linker hash table. */
3612 static void
3614 {
3620 }
3622 /* Create an ARM elf linker hash table. */
3626 {
3635 elf32_arm_link_hash_newfunc,
3637 ARM_ELF_DATA))
3638 {
3641 }
3645 #ifdef FOUR_WORD_PLT
3648 #else
3651 #endif
3657 {
3660 }
3664 }
3666 /* Determine what kind of NOPs are available. */
3668 static bfd_boolean
3670 {
3672 Tag_CPU_arch);
3677 }
3679 static bfd_boolean
3681 {
3683 Tag_CPU_arch);
3686 }
3688 static bfd_boolean
3690 {
3692 {
3706 }
3707 }
3709 /* Determine the type of stub needed, if any, for a call. */
3711 static enum elf32_arm_stub_type
3718 bfd_vma destination,
3722 {
3723 bfd_vma location;
3724 bfd_signed_vma branch_offset;
3746 /* Determine where the call point is. */
3753 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3754 are considering a function call relocation. */
3760 /* For TLS call relocs, it is the caller's responsibility to provide
3761 the address of the appropriate trampoline. */
3767 {
3772 else
3775 {
3778 /* Note when dealing with PLT entries: the main PLT stub is in
3779 ARM mode, so if the branch is in Thumb mode, another
3780 Thumb->ARM stub will be inserted later just before the ARM
3781 PLT stub. We don't take this extra distance into account
3782 here, because if a long branch stub is needed, we'll add a
3783 Thumb->Arm one and branch directly to the ARM PLT entry
3784 because it avoids spreading offset corrections in several
3785 places. */
3792 }
3793 }
3794 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3801 {
3802 /* Handle cases where:
3803 - this call goes too far (different Thumb/Thumb2 max
3804 distance)
3805 - it's a Thumb->Arm call and blx is not available, or it's a
3806 Thumb->Arm branch (not bl). A stub is needed in this case,
3807 but only if this call is not through a PLT entry. Indeed,
3808 PLT stubs handle mode switching already.
3809 */
3813 || (thumb2
3816 || (thumb2
3826 {
3828 {
3829 /* Thumb to thumb. */
3831 {
3833 /* PIC stubs. */
3836 /* V5T and above. Stub starts with ARM code, so
3837 we must be able to switch mode before
3838 reaching it, which is only possible for 'bl'
3839 (ie R_ARM_THM_CALL relocation). */
3840 ? arm_stub_long_branch_any_thumb_pic
3841 /* On V4T, use Thumb code only. */
3844 /* non-PIC stubs. */
3847 /* V5T and above. */
3848 ? arm_stub_long_branch_any_any
3849 /* V4T. */
3851 }
3852 else
3853 {
3855 /* PIC stub. */
3856 ? arm_stub_long_branch_thumb_only_pic
3857 /* non-PIC stub. */
3859 }
3860 }
3861 else
3862 {
3863 /* Thumb to arm. */
3867 {
3872 }
3874 stub_type =
3876 /* PIC stubs. */
3878 /* TLS PIC stubs. */
3882 /* V5T PIC and above. */
3883 ? arm_stub_long_branch_any_arm_pic
3884 /* V4T PIC stub. */
3887 /* non-PIC stubs. */
3889 /* V5T and above. */
3890 ? arm_stub_long_branch_any_any
3891 /* V4T. */
3894 /* Handle v4t short branches. */
3899 }
3900 }
3901 }
3906 {
3908 {
3909 /* Arm to thumb. */
3914 {
3919 }
3921 /* We have an extra 2-bytes reach because of
3922 the mode change (bit 24 (H) of BLX encoding). */
3928 {
3930 /* PIC stubs. */
3932 /* V5T and above. */
3933 ? arm_stub_long_branch_any_thumb_pic
3934 /* V4T stub. */
3937 /* non-PIC stubs. */
3939 /* V5T and above. */
3940 ? arm_stub_long_branch_any_any
3941 /* V4T. */
3943 }
3944 }
3945 else
3946 {
3947 /* Arm to arm. */
3950 {
3951 stub_type =
3953 /* PIC stubs. */
3955 /* TLS PIC Stub. */
3956 ? arm_stub_long_branch_any_tls_pic
3958 ? arm_stub_long_branch_arm_nacl_pic
3960 /* non-PIC stubs. */
3962 ? arm_stub_long_branch_arm_nacl
3964 }
3965 }
3966 }
3968 /* If a stub is needed, record the actual destination type. */
3973 }
3975 /* Build a name for an entry in the stub hash table. */
3983 {
3985 bfd_size_type len;
3988 {
3997 }
3998 else
3999 {
4011 }
4014 }
4016 /* Look up an entry in the stub hash. Stub entries are cached because
4017 creating the stub name takes a bit of time. */
4026 {
4034 /* If this input section is part of a group of sections sharing one
4035 stub section, then use the id of the first section in the group.
4036 Stub names need to include a section id, as there may well be
4037 more than one stub used to reach say, printf, and we need to
4038 distinguish between them. */
4045 {
4047 }
4048 else
4049 {
4062 }
4065 }
4067 /* Find or create a stub section. Returns a pointer to the stub section, and
4068 the section to which the stub section will be attached (in *LINK_SEC_P).
4069 LINK_SEC_P may be NULL. */
4074 {
4083 {
4086 {
4088 bfd_size_type len;
4104 }
4106 }
4112 }
4114 /* Add a new stub entry to the stub hash. Not all fields of the new
4115 stub entry are initialised. */
4121 {
4130 /* Enter this entry into the linker stub hash table. */
4134 {
4137 stub_name);
4139 }
4146 }
4148 /* Store an Arm insn into an output section not processed by
4149 elf32_arm_write_section. */
4151 static void
4154 {
4157 else
4159 }
4161 /* Store a 16-bit Thumb insn into an output section not processed by
4162 elf32_arm_write_section. */
4164 static void
4167 {
4170 else
4172 }
4174 /* Store a Thumb2 insn into an output section not processed by
4175 elf32_arm_write_section. */
4177 static void
4180 {
4181 /* T2 instructions are 16-bit streamed. */
4183 {
4186 }
4187 else
4188 {
4191 }
4192 }
4194 /* If it's possible to change R_TYPE to a more efficient access
4195 model, return the new reloc type. */
4197 static unsigned
4200 {
4207 /* We do not support relaxations for Old TLS models. */
4209 {
4216 }
4219 }
4221 static bfd_reloc_status_type elf32_arm_final_link_relocate
4227 static unsigned int
4229 {
4231 {
4260 }
4261 }
4263 static bfd_boolean
4266 {
4267 #define MAXRELOCS 3
4274 bfd_vma sym_value;
4283 /* Massage our args to the form they really have. */
4295 /* We have to do less-strictly-aligned fixes last. */
4298 /* Make a note of the offset within the stubs for this entry. */
4304 /* This is the address of the stub destination. */
4314 {
4316 {
4318 {
4321 {
4322 /* We've borrowed the reloc_addend field to mean we should
4323 insert a condition code into this (Thumb-1 branch)
4324 instruction. See THUMB16_BCOND_INSN. */
4327 }
4330 }
4340 {
4343 }
4350 /* Handle cases where the target is encoded within the
4351 instruction. */
4353 {
4356 }
4370 }
4371 }
4375 /* Stub size has already been computed in arm_size_one_stub. Check
4376 consistency. */
4379 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
4383 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4384 in each stub. */
4392 {
4393 Elf_Internal_Rela rel;
4394 bfd_boolean unresolved_reloc;
4396 enum arm_st_branch_type branch_type
4407 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4408 template should refer back to the instruction after the original
4409 branch. */
4412 /* There may be unintended consequences if this is not true. */
4415 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4416 properly. We should probably use this function unconditionally,
4417 rather than only for certain relocations listed in the enclosing
4418 conditional, for the sake of consistency. */
4425 }
4426 else
4427 {
4428 Elf_Internal_Rela rel;
4429 bfd_boolean unresolved_reloc;
4446 }
4449 #undef MAXRELOCS
4450 }
4452 /* Calculate the template, template size and instruction size for a stub.
4453 Return value is the instruction size. */
4455 static unsigned int
4459 {
4474 {
4476 {
4490 }
4491 }
4494 }
4496 /* As above, but don't actually build the stub. Just bump offset so
4497 we know stub section sizes. */
4499 static bfd_boolean
4502 {
4507 /* Massage our args to the form they really have. */
4524 }
4526 /* External entry points for sizing and building linker stubs. */
4528 /* Set up various things so that we can make a list of input sections
4529 for each output section included in the link. Returns -1 on error,
4530 0 when no stubs will be needed, and 1 on success. */
4532 int
4535 {
4541 bfd_size_type amt;
4549 /* Count the number of input BFDs and find the top input section id. */
4553 {
4558 {
4561 }
4562 }
4571 /* We can't use output_bfd->section_count here to find the top output
4572 section index as some sections may have been removed, and
4573 _bfd_strip_section_from_output doesn't renumber the indices. */
4577 {
4580 }
4589 /* For sections we aren't interested in, mark their entries with a
4590 value we can check later. */
4592 do
4599 {
4602 }
4605 }
4607 /* The linker repeatedly calls this function for each input section,
4608 in the order that input sections are linked into output sections.
4609 Build lists of input sections to determine groupings between which
4610 we may insert linker stubs. */
4612 void
4615 {
4622 {
4626 {
4627 /* Steal the link_sec pointer for our list. */
4628 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4629 /* This happens to make the list in reverse order,
4630 which we reverse later. */
4633 }
4634 }
4635 }
4637 /* See whether we can group stub sections together. Grouping stub
4638 sections may result in fewer stubs. More importantly, we need to
4639 put all .init* and .fini* stubs at the end of the .init or
4640 .fini output sections respectively, because glibc splits the
4641 _init and _fini functions into multiple parts. Putting a stub in
4642 the middle of a function is not a good idea. */
4644 static void
4646 bfd_size_type stub_group_size,
4647 bfd_boolean stubs_always_after_branch)
4648 {
4651 do
4652 {
4659 /* Reverse the list: we must avoid placing stubs at the
4660 beginning of the section because the beginning of the text
4661 section may be required for an interrupt vector in bare metal
4662 code. */
4663 #define NEXT_SEC PREV_SEC
4666 {
4667 /* Pop from tail. */
4671 /* Push on head. */
4674 }
4677 {
4681 bfd_vma end_of_next;
4685 {
4689 /* End of NEXT is too far from start, so stop. */
4691 /* Add NEXT to the group. */
4693 }
4695 /* OK, the size from the start to the start of CURR is less
4696 than stub_group_size and thus can be handled by one stub
4697 section. (Or the head section is itself larger than
4698 stub_group_size, in which case we may be toast.)
4699 We should really be keeping track of the total size of
4700 stubs added here, as stubs contribute to the final output
4701 section size. */
4702 do
4703 {
4705 /* Set up this stub group. */
4707 }
4710 /* But wait, there's more! Input sections up to stub_group_size
4711 bytes after the stub section can be handled by it too. */
4713 {
4717 {
4720 /* End of NEXT is too far from stubs, so stop. */
4722 /* Add NEXT to the stub group. */
4726 }
4727 }
4729 }
4730 }
4734 #undef PREV_SEC
4735 #undef NEXT_SEC
4736 }
4738 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4739 erratum fix. */
4741 static int
4743 {
4751 else
4753 }
4758 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4759 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4760 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4761 otherwise. */
4763 static bfd_boolean
4773 {
4786 {
4790 bfd_vma base_vma;
4809 {
4820 /* Span is entirely within a single 4KB region: skip scanning. */
4825 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4827 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4828 * The branch target is in the same 4KB region as the
4829 first half of the branch.
4830 * The instruction before the branch is a 32-bit
4831 length non-branch instruction. */
4833 {
4842 {
4843 /* Load the rest of the insn (in manual-friendly order). */
4846 /* Encoding T4: B<c>.W. */
4848 /* Encoding T1: BL<c>.W. */
4850 /* Encoding T2: BLX<c>.W. */
4852 /* Encoding T3: B<c>.W (not permitted in IT block). */
4855 }
4860 && insn_32bit
4861 && is_32bit_branch
4862 && last_was_32bit
4864 {
4868 bfd_vma target;
4880 {
4884 /* We don't care about the error returned from this
4885 function, only if there is glue or not. */
4892 /* Keep a simpler condition, for the sake of clarity. */
4898 {
4902 else
4904 }
4905 }
4907 /* Check if we have an offending branch instruction. */
4910 /* We've already made a stub for this instruction, e.g.
4911 it's a long branch or a Thumb->ARM stub. Assume that
4912 stub will suffice to work around the A8 erratum (see
4913 setting of always_after_branch above). */
4914 ;
4916 {
4925 }
4927 {
4947 }
4950 {
4953 /* The original instruction is a BL, but the target is
4954 an ARM instruction. If we were not making a stub,
4955 the BL would have been converted to a BLX. Use the
4956 BLX stub instead in that case. */
4959 {
4963 }
4964 /* Conversely, if the original instruction was
4965 BLX but the target is Thumb mode, use the BL
4966 stub. */
4969 {
4973 }
4978 /* If we found a relocation, use the proper destination,
4979 not the offset in the (unrelocated) instruction.
4980 Note this is always done if we switched the stub type
4981 above. */
4983 offset =
4986 /* If the stub will use a Thumb-mode branch to a
4987 PLT target, redirect it to the preceding Thumb
4988 entry point. */
4994 /* The BLX stub is ARM-mode code. Adjust the offset to
4995 take the different PC value (+8 instead of +4) into
4996 account. */
5001 {
5005 {
5011 }
5014 {
5015 /* If we're doing a subsequent scan,
5016 check if we've found the same fix as
5017 before, and try and reuse the stub
5018 name. */
5022 {
5026 }
5027 }
5030 {
5034 }
5046 num_a8_fixes++;
5047 }
5048 }
5049 }
5054 }
5055 }
5059 }
5066 }
5068 /* Determine and set the size of the stub section for a final link.
5070 The basic idea here is to examine all the relocations looking for
5071 PC-relative calls to a target that is unreachable with a "bl"
5072 instruction. */
5074 bfd_boolean
5078 bfd_signed_vma group_size,
5082 {
5083 bfd_size_type stub_group_size;
5084 bfd_boolean stubs_always_after_branch;
5095 {
5100 }
5102 /* Propagate mach to stub bfd, because it may not have been
5103 finalized when we created stub_bfd. */
5107 /* Stash our params away. */
5113 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5114 as the first half of a 32-bit branch straddling two 4K pages. This is a
5115 crude way of enforcing that. */
5121 else
5125 {
5126 /* Default values. */
5127 /* Thumb branch range is +-4MB has to be used as the default
5128 maximum size (a given section can contain both ARM and Thumb
5129 code, so the worst case has to be taken into account).
5131 This value is 24K less than that, which allows for 2025
5132 12-byte stubs. If we exceed that, then we will fail to link.
5133 The user will have to relink with an explicit group size
5134 option. */
5136 }
5140 /* If we're applying the cortex A8 fix, we need to determine the
5141 program header size now, because we cannot change it later --
5142 that could alter section placements. Notice the A8 erratum fix
5143 ends up requiring the section addresses to remain unchanged
5144 modulo the page size. That's something we cannot represent
5145 inside BFD, and we don't want to force the section alignment to
5146 be the page size. */
5151 {
5162 {
5172 /* We'll need the symbol table in a second. */
5177 /* Walk over each section attached to the input bfd. */
5181 {
5184 /* If there aren't any relocs, then there's nothing more
5185 to do. */
5191 /* If this section is a link-once section that will be
5192 discarded, then don't create any stubs. */
5197 /* Get the relocs. */
5198 internal_relocs
5204 /* Now examine each relocation. */
5208 {
5213 bfd_vma sym_value;
5214 bfd_vma destination;
5227 {
5229 error_ret_free_internal:
5233 }
5237 hash = elf32_arm_hash_entry
5241 /* Only look for stubs on branch instructions, or
5242 non-relaxed TLSCALL */
5255 : (elf32_arm_local_got_tls_type
5260 /* Now determine the call target, its name, value,
5261 section. */
5269 {
5270 /* A non-relaxed TLS call. The target is the
5271 plt-resident trampoline and nothing to do
5272 with the symbol. */
5279 }
5281 {
5282 /* It's a local symbol. */
5286 {
5287 local_syms
5290 local_syms
5296 }
5305 else
5306 sym_sec =
5310 /* This is an undefined symbol. It can never
5311 be resolved. */
5321 sym_name
5325 }
5326 else
5327 {
5328 /* It's an external symbol. */
5336 {
5343 /* For a destination in a shared library,
5344 use the PLT stub as target address to
5345 decide whether a branch stub is
5346 needed. */
5351 {
5355 destination = (sym_value
5358 }
5363 }
5366 {
5367 /* For a shared library, use the PLT stub as
5368 target address to decide whether a long
5369 branch stub is needed.
5370 For absolute code, they cannot be handled. */
5378 {
5382 destination = (sym_value
5385 }
5386 else
5388 }
5389 else
5390 {
5393 }
5397 }
5399 do
5400 {
5401 /* Determine what (if any) linker stub is needed. */
5409 /* Support for grouping stub sections. */
5412 /* Get the name of this stub. */
5418 /* We've either created a stub for this reloc already,
5419 or we are about to. */
5422 stub_entry = arm_stub_hash_lookup
5426 {
5427 /* The proper stub has already been created. */
5431 }
5434 htab);
5436 {
5439 }
5454 {
5457 }
5459 /* For historical reasons, use the existing names for
5460 ARM-to-Thumb and Thumb-to-ARM stubs. */
5472 else
5474 sym_name);
5477 }
5480 /* Look for relocations which might trigger Cortex-A8
5481 erratum. */
5487 {
5493 {
5494 /* Found a candidate. Note we haven't checked the
5495 destination is within 4K here: if we do so (and
5496 don't create an entry in a8_relocs) we can't tell
5497 that a branch should have been relocated when
5498 scanning later. */
5500 {
5506 }
5516 num_a8_relocs++;
5517 }
5518 }
5519 }
5521 /* We're done with the internal relocs, free them. */
5524 }
5527 {
5528 /* Sort relocs which might apply to Cortex-A8 erratum. */
5533 /* Scan for branches which might trigger Cortex-A8 erratum. */
5540 }
5541 }
5549 /* OK, we've added some stubs. Find out the new size of the
5550 stub sections. */
5554 {
5555 /* Ignore non-stub sections. */
5560 }
5564 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5567 {
5574 stub_sec->size
5576 NULL);
5577 }
5580 /* Ask the linker to do its stuff. */
5582 }
5584 /* Add stubs for Cortex-A8 erratum fixes now. */
5586 {
5588 {
5601 {
5604 stub_name);
5606 }
5625 }
5627 /* Stash the Cortex-A8 erratum fix array for use later in
5628 elf32_arm_write_section(). */
5631 }
5632 else
5633 {
5636 }
5639 error_ret_free_local:
5641 }
5643 /* Build all the stubs associated with the current output file. The
5644 stubs are kept in a hash table attached to the main linker hash
5645 table. We also set up the .plt entries for statically linked PIC
5646 functions here. This function is called via arm_elf_finish in the
5647 linker. */
5649 bfd_boolean
5651 {
5663 {
5664 bfd_size_type size;
5666 /* Ignore non-stub sections. */
5670 /* Allocate memory to hold the linker stubs. */
5676 }
5678 /* Build the stubs as directed by the stub hash table. */
5682 {
5683 /* Place the cortex a8 stubs last. */
5686 }
5689 }
5691 /* Locate the Thumb encoded calling stub for NAME. */
5697 {
5702 /* We need a pointer to the armelf specific hash table. */
5714 hash = elf_link_hash_lookup
5725 }
5727 /* Locate the ARM encoded calling stub for NAME. */
5733 {
5738 /* We need a pointer to the elfarm specific hash table. */
5750 myh = elf_link_hash_lookup
5761 }
5763 /* ARM->Thumb glue (static images):
5765 .arm
5766 __func_from_arm:
5767 ldr r12, __func_addr
5768 bx r12
5769 __func_addr:
5770 .word func @ behave as if you saw a ARM_32 reloc.
5772 (v5t static images)
5773 .arm
5774 __func_from_arm:
5775 ldr pc, __func_addr
5776 __func_addr:
5777 .word func @ behave as if you saw a ARM_32 reloc.
5779 (relocatable images)
5780 .arm
5781 __func_from_arm:
5782 ldr r12, __func_offset
5783 add r12, r12, pc
5784 bx r12
5785 __func_offset:
5786 .word func - . */
5788 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5793 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5797 #define ARM2THUMB_PIC_GLUE_SIZE 16
5802 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5804 .thumb .thumb
5805 .align 2 .align 2
5806 __func_from_thumb: __func_from_thumb:
5807 bx pc push {r6, lr}
5808 nop ldr r6, __func_addr
5809 .arm mov lr, pc
5810 b func bx r6
5811 .arm
5812 ;; back_to_thumb
5813 ldmia r13! {r6, lr}
5814 bx lr
5815 __func_addr:
5816 .word func */
5818 #define THUMB2ARM_GLUE_SIZE 8
5823 #define VFP11_ERRATUM_VENEER_SIZE 8
5824 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5825 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
5827 #define ARM_BX_VENEER_SIZE 12
5832 #ifndef ELFARM_NABI_C_INCLUDED
5833 static void
5835 {
5840 {
5841 /* Do not include empty glue sections in the output. */
5843 {
5847 }
5849 }
5860 }
5862 bfd_boolean
5864 {
5872 ARM2THUMB_GLUE_SECTION_NAME);
5876 THUMB2ARM_GLUE_SECTION_NAME);
5880 VFP11_ERRATUM_VENEER_SECTION_NAME);
5884 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5888 ARM_BX_GLUE_SECTION_NAME);
5891 }
5893 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5894 returns the symbol identifying the stub. */
5899 {
5906 bfd_vma val;
5907 bfd_size_type size;
5913 s = bfd_get_linker_section
5925 myh = elf_link_hash_lookup
5929 {
5930 /* We've already seen this guy. */
5933 }
5935 /* The only trick here is using hash_table->arm_glue_size as the value.
5936 Even though the section isn't allocated yet, this is where we will be
5937 putting it. The +1 on the value marks that the stub has not been
5938 output yet - not that it is a Thumb function. */
5957 else
5964 }
5966 /* Allocate space for ARMv4 BX veneers. */
5968 static void
5970 {
5976 bfd_vma val;
5978 /* BX PC does not need a veneer. */
5986 /* Check if this veneer has already been allocated. */
5990 s = bfd_get_linker_section
5995 /* Add symbol for veneer. */
6003 myh = elf_link_hash_lookup
6021 }
6024 /* Add an entry to the code/data map for section SEC. */
6026 static void
6028 {
6033 {
6038 }
6043 {
6048 }
6051 {
6054 }
6055 }
6058 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6059 veneers are handled for now. */
6061 static bfd_vma
6067 {
6073 bfd_vma val;
6081 s = bfd_get_linker_section
6096 myh = elf_link_hash_lookup
6111 /* Link veneer back to calling location. */
6125 /* A symbol for the return from the veneer. */
6129 myh = elf_link_hash_lookup
6146 /* Generate a mapping symbol for the veneer section, and explicitly add an
6147 entry for that symbol to the code/data map for the section. */
6149 {
6151 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
6152 ever requires this erratum fix. */
6162 /* The elf32_arm_init_maps function only cares about symbols from input
6163 BFDs. We must make a note of this generated mapping symbol
6164 ourselves so that code byteswapping works properly in
6165 elf32_arm_write_section. */
6167 }
6173 /* The offset of the veneer. */
6175 }
6177 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6178 veneers need to be handled because used only in Cortex-M. */
6180 static bfd_vma
6186 bfd_size_type veneer_size)
6187 {
6193 bfd_vma val;
6201 s = bfd_get_linker_section
6216 myh = elf_link_hash_lookup
6231 /* Link veneer back to calling location. */
6245 /* A symbol for the return from the veneer. */
6249 myh = elf_link_hash_lookup
6266 /* Generate a mapping symbol for the veneer section, and explicitly add an
6267 entry for that symbol to the code/data map for the section. */
6269 {
6271 /* Creates a THUMB symbol since there is no other choice. */
6281 /* The elf32_arm_init_maps function only cares about symbols from input
6282 BFDs. We must make a note of this generated mapping symbol
6283 ourselves so that code byteswapping works properly in
6284 elf32_arm_write_section. */
6286 }
6292 /* The offset of the veneer. */
6294 }
6296 #define ARM_GLUE_SECTION_FLAGS \
6297 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6298 | SEC_READONLY | SEC_LINKER_CREATED)
6300 /* Create a fake section for use by the ARM backend of the linker. */
6302 static bfd_boolean
6304 {
6309 /* Already made. */
6318 /* Set the gc mark to prevent the section from being removed by garbage
6319 collection, despite the fact that no relocs refer to this section. */
6323 }
6325 /* Set size of .plt entries. This function is called from the
6326 linker scripts in ld/emultempl/{armelf}.em. */
6328 void
6330 {
6332 }
6334 /* Add the glue sections to ABFD. This function is called from the
6335 linker scripts in ld/emultempl/{armelf}.em. */
6337 bfd_boolean
6340 {
6342 bfd_boolean dostm32l4xx = globals
6344 bfd_boolean addglue;
6346 /* If we are only performing a partial
6347 link do not bother adding the glue. */
6359 return addglue
6361 }
6363 /* Select a BFD to be used to hold the sections used by the glue code.
6364 This function is called from the linker scripts in ld/emultempl/
6365 {armelf/pe}.em. */
6367 bfd_boolean
6369 {
6372 /* If we are only performing a partial link
6373 do not bother getting a bfd to hold the glue. */
6377 /* Make sure we don't attach the glue sections to a dynamic object. */
6386 /* Save the bfd for later use. */
6390 }
6392 static void
6394 {
6398 Tag_CPU_arch);
6401 {
6404 }
6405 else
6406 {
6409 }
6410 }
6412 bfd_boolean
6415 {
6424 /* If we are only performing a partial link do not bother
6425 to construct any glue. */
6429 /* Here we have a bfd that is to be included on the link. We have a
6430 hook to do reloc rummaging, before section sizes are nailed down. */
6437 {
6439 abfd);
6441 }
6443 /* PR 5398: If we have not decided to include any loadable sections in
6444 the output then we will not have a glue owner bfd. This is OK, it
6445 just means that there is nothing else for us to do here. */
6449 /* Rummage around all the relocs and map the glue vectors. */
6456 {
6465 /* Load the relocs. */
6466 internal_relocs
6474 {
6483 /* These are the only relocation types we care about. */
6488 /* Get the section contents if we haven't done so already. */
6490 {
6491 /* Get cached copy if it exists. */
6494 else
6495 {
6496 /* Go get them off disk. */
6499 }
6500 }
6503 {
6509 }
6511 /* If the relocation is not against a symbol it cannot concern us. */
6514 /* We don't care about local symbols. */
6518 /* This is an external symbol. */
6523 /* If the relocation is against a static symbol it must be within
6524 the current section and so cannot be a cross ARM/Thumb relocation. */
6528 /* If the call will go through a PLT entry then we do not need
6529 glue. */
6534 {
6536 /* This one is a call from arm code. We need to look up
6537 the target of the call. If it is a thumb target, we
6538 insert glue. */
6545 }
6546 }
6557 }
6561 error_return:
6570 }
6571 #endif
6574 /* Initialise maps of ARM/Thumb/data for input BFDs. */
6576 void
6578 {
6583 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6593 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6594 should contain the number of local symbols, which should come before any
6595 global symbols. Mapping symbols are always local. */
6597 NULL);
6599 /* No internal symbols read? Skip this BFD. */
6604 {
6611 {
6616 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
6618 }
6619 }
6620 }
6623 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6624 say what they wanted. */
6626 void
6628 {
6636 {
6637 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6642 else
6644 }
6645 }
6648 void
6650 {
6656 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6658 {
6660 {
6667 /* Give a warning, but do as the user requests anyway. */
6670 }
6671 }
6673 /* For earlier architectures, we might need the workaround, but do not
6674 enable it by default. If users is running with broken hardware, they
6675 must enable the erratum fix explicitly. */
6677 }
6679 void
6681 {
6688 /* We assume only Cortex-M4 may require the fix. */
6691 {
6693 /* Give a warning, but do as the user requests anyway. */
6697 }
6698 }
6700 enum bfd_arm_vfp11_pipe
6701 {
6702 VFP11_FMAC,
6703 VFP11_LS,
6704 VFP11_DS,
6705 VFP11_BAD
6706 };
6708 /* Return a VFP register number. This is encoded as RX:X for single-precision
6709 registers, or X:RX for double-precision registers, where RX is the group of
6710 four bits in the instruction encoding and X is the single extension bit.
6711 RX and X fields are specified using their lowest (starting) bit. The return
6712 value is:
6714 0...31: single-precision registers s0...s31
6715 32...63: double-precision registers d0...d31.
6717 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6718 encounter VFP3 instructions, so we allow the full range for DP registers. */
6720 static unsigned int
6723 {
6726 else
6728 }
6730 /* Set bits in *WMASK according to a register number REG as encoded by
6731 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6733 static void
6735 {
6740 }
6742 /* Return TRUE if WMASK overwrites anything in REGS. */
6744 static bfd_boolean
6746 {
6750 {
6763 }
6766 }
6768 /* In this function, we're interested in two things: finding input registers
6769 for VFP data-processing instructions, and finding the set of registers which
6770 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6771 hold the written set, so FLDM etc. are easy to deal with (we're only
6772 interested in 32 SP registers or 16 dp registers, due to the VFP version
6773 implemented by the chip in question). DP registers are marked by setting
6774 both SP registers in the write mask). */
6776 static enum bfd_arm_vfp11_pipe
6779 {
6784 {
6794 {
6816 vfp_binop:
6824 {
6829 {
6843 /* These instructions will not bounce due to underflow. */
6849 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6850 registers to cause the erratum in previous instructions. */
6856 {
6861 /* Only FCVTSD can underflow. */
6868 }
6873 }
6874 }
6879 }
6880 }
6881 /* Two-register transfer. */
6883 {
6887 {
6890 else
6891 {
6894 }
6895 }
6898 }
6900 {
6905 {
6912 {
6920 }
6930 }
6933 }
6934 /* Single-register transfer. Note L==0. */
6936 {
6941 {
6944 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6945 destination register. I don't know if this is exactly right,
6946 but it is the conservative choice. */
6952 }
6955 }
6958 }
6964 /* Look for potentially-troublesome code sequences which might trigger the
6965 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6966 (available from ARM) for details of the erratum. A short version is
6967 described in ld.texinfo. */
6969 bfd_boolean
6971 {
6982 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6983 The states transition as follows:
6985 0 -> 1 (vector) or 0 -> 2 (scalar)
6986 A VFP FMAC-pipeline instruction has been seen. Fill
6987 regs[0]..regs[numregs-1] with its input operands. Remember this
6988 instruction in 'first_fmac'.
6990 1 -> 2
6991 Any instruction, except for a VFP instruction which overwrites
6992 regs[*].
6994 1 -> 3 [ -> 0 ] or
6995 2 -> 3 [ -> 0 ]
6996 A VFP instruction has been seen which overwrites any of regs[*].
6997 We must make a veneer! Reset state to 0 before examining next
6998 instruction.
7000 2 -> 0
7001 If we fail to match anything in state 2, reset to state 0 and reset
7002 the instruction pointer to the instruction after 'first_fmac'.
7004 If the VFP11 vector mode is in use, there must be at least two unrelated
7005 instructions between anti-dependent VFP11 instructions to properly avoid
7006 triggering the erratum, hence the use of the extra state 1. */
7008 /* If we are only performing a partial link do not bother
7009 to construct any glue. */
7013 /* Skip if this bfd does not correspond to an ELF image. */
7017 /* We should have chosen a fix type by the time we get here. */
7023 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7028 {
7032 /* If we don't have executable progbits, we're not interested in this
7033 section. Also skip if section is to be excluded. */
7053 elf32_arm_compare_mapping);
7056 {
7062 /* FIXME: Only ARM mode is supported at present. We may need to
7063 support Thumb-2 mode also at some point. */
7068 {
7083 {
7087 /* I'm assuming the VFP11 erratum can trigger with denorm
7088 operands on either the FMAC or the DS pipeline. This might
7089 lead to slightly overenthusiastic veneer insertion. */
7091 {
7095 }
7099 {
7102 other_regs,
7106 numregs))
7108 else
7110 }
7114 {
7117 other_regs,
7121 numregs))
7123 else
7124 {
7127 }
7128 }
7133 }
7136 {
7145 {
7152 }
7155 first_fmac);
7163 }
7166 }
7167 }
7173 }
7177 error_return:
7183 }
7185 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7186 after sections have been laid out, using specially-named symbols. */
7188 void
7191 {
7199 /* Skip if this bfd does not correspond to an ELF image. */
7211 {
7216 {
7218 bfd_vma vma;
7221 {
7224 /* Find veneer symbol. */
7228 myh = elf_link_hash_lookup
7244 /* Find return location. */
7248 myh = elf_link_hash_lookup
7264 }
7265 }
7266 }
7269 }
7271 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
7272 return locations after sections have been laid out, using
7273 specially-named symbols. */
7275 void
7278 {
7286 /* Skip if this bfd does not correspond to an ELF image. */
7298 {
7303 {
7305 bfd_vma vma;
7308 {
7310 /* Find veneer symbol. */
7314 myh = elf_link_hash_lookup
7329 /* Find return location. */
7333 myh = elf_link_hash_lookup
7349 }
7350 }
7351 }
7354 }
7358 {
7359 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7360 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7362 }
7366 {
7367 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7368 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7370 }
7374 {
7375 /* A6.5 Extension register load or store instruction
7376 A7.7.229
7377 We look only for the 32-bit registers case since the DP (64-bit
7378 registers) are not supported for STM32L4XX
7379 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7380 <list> is consecutive 32-bit registers
7381 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7382 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7383 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7384 return
7388 /* (IA with !), includes VPOP (when reg number is SP). */
7390 /* (DB with !). */
7392 }
7394 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7395 VLDM opcode and:
7396 - computes the number and the mode of memory accesses
7397 - decides if the replacement should be done:
7398 . replaces only if > 8-word accesses
7399 . or (testing purposes only) replaces all accesses. */
7401 static bfd_boolean
7403 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7404 {
7407 /* The field encoding the register list is the same for both LDMIA
7408 and LDMDB encodings. */
7414 /* DEFAULT mode accounts for the real bug condition situation,
7415 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7416 return
7419 }
7421 /* Look for potentially-troublesome code sequences which might trigger
7422 the STM STM32L4XX erratum. */
7424 bfd_boolean
7427 {
7435 /* If we are only performing a partial link do not bother
7436 to construct any glue. */
7440 /* Skip if this bfd does not correspond to an ELF image. */
7447 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7452 {
7456 /* If we don't have executable progbits, we're not interested in this
7457 section. Also skip if section is to be excluded. */
7477 elf32_arm_compare_mapping);
7480 {
7487 /* Only Thumb2 mode need be supported with this CM4 specific
7488 code, we should not encounter any arm mode eg span_type
7489 != 'a'. */
7494 {
7501 /* The first 16-bits of all 32-bit thumb2 instructions start
7502 with opcode[15..13]=0b111 and the encoded op1 can be anything
7503 except opcode[12..11]!=0b00.
7504 See 32-bit Thumb instruction encoding. */
7508 /* Compute the predicate that tells if the instruction
7509 is concerned by the IT block
7510 - Creates an error if there is a ldm that is not
7511 last in the IT block thus cannot be replaced
7512 - Otherwise we can create a branch at the end of the
7513 IT block, it will be controlled naturally by IT
7514 with the proper pseudo-predicate
7515 - So the only interesting predicate is the one that
7516 tells that we are not on the last item of an IT
7517 block. */
7522 {
7523 /* Load the rest of the insn (in manual-friendly order). */
7528 /* Veneers are created for (v)ldm depending on
7529 option flags and memory accesses conditions; but
7530 if the instruction is not the last instruction of
7531 an IT block, we cannot create a jump there, so we
7532 bail out. */
7534 stm32l4xx_need_create_replacing_stub
7536 {
7538 {
7540 /* Note - overlong line used here to allow for translation. */
7542 %B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7545 }
7546 else
7547 {
7550 bfd_zmalloc
7556 /* We create only thumb branches. */
7558 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7559 record_stm32l4xx_erratum_veneer
7561 i,
7562 is_ldm ?
7563 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7564 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7568 }
7569 }
7570 }
7571 else
7572 {
7573 /* A7.7.37 IT p208
7574 IT blocks are only encoded in T1
7575 Encoding T1: IT{x{y{z}}} <firstcond>
7576 1 0 1 1 - 1 1 1 1 - firstcond - mask
7577 if mask = '0000' then see 'related encodings'
7578 We don't deal with UNPREDICTABLE, just ignore these.
7579 There can be no nested IT blocks so an IT block
7580 is naturally a new one for which it is worth
7581 computing its size. */
7584 /* If we have a new IT block we compute its size. */
7586 {
7587 /* Compute the number of instructions controlled
7588 by the IT block, it will be used to decide
7589 whether we are inside an IT block or not. */
7592 }
7593 }
7596 }
7597 }
7603 }
7607 error_return:
7613 }
7615 /* Set target relocation values needed during linking. */
7617 void
7624 bfd_arm_vfp11_fix vfp11_fix,
7625 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
7629 {
7643 else
7644 {
7646 target2_type);
7647 }
7659 }
7661 /* Replace the target offset of a Thumb bl or b.w instruction. */
7663 static void
7665 {
7666 bfd_vma upper;
7667 bfd_vma lower;
7684 }
7686 /* Thumb code calling an ARM function. */
7688 static int
7696 bfd_vma offset,
7697 bfd_signed_vma addend,
7698 bfd_vma val,
7700 {
7702 bfd_vma my_offset;
7718 THUMB2ARM_GLUE_SECTION_NAME);
7725 {
7729 {
7736 }
7747 ret_offset =
7748 /* Address of destination of the stub. */
7751 /* Offset from the start of the current section
7752 to the start of the stubs. */
7754 /* Offset of the start of this stub from the start of the stubs. */
7755 + my_offset
7756 /* Address of the start of the current section. */
7758 /* The branch instruction is 4 bytes into the stub. */
7760 /* ARM branches work from the pc of the instruction + 8. */
7766 }
7770 /* Now go back and fix up the original BL insn to point to here. */
7771 ret_offset =
7772 /* Address of where the stub is located. */
7774 /* Address of where the BL is located. */
7777 /* Addend in the relocation. */
7778 - addend
7779 /* Biassing for PC-relative addressing. */
7785 }
7787 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
7795 bfd_vma val,
7798 {
7799 bfd_vma my_offset;
7815 {
7819 {
7824 }
7832 {
7833 /* For relocatable objects we can't use absolute addresses,
7834 so construct the address from a relative offset. */
7835 /* TODO: If the offset is small it's probably worth
7836 constructing the address with adds. */
7843 /* Adjust the offset by 4 for the position of the add,
7844 and 8 for the pipeline offset. */
7851 }
7853 {
7857 /* It's a thumb address. Add the low order bit. */
7860 }
7861 else
7862 {
7869 /* It's a thumb address. Add the low order bit. */
7874 }
7875 }
7880 }
7882 /* Arm code calling a Thumb function. */
7884 static int
7892 bfd_vma offset,
7893 bfd_signed_vma addend,
7894 bfd_vma val,
7896 {
7898 bfd_vma my_offset;
7909 ARM2THUMB_GLUE_SECTION_NAME);
7923 /* Somehow these are both 4 too far, so subtract 8. */
7925 + my_offset
7937 }
7939 /* Populate Arm stub for an exported Thumb function. */
7941 static bfd_boolean
7943 {
7950 bfd_vma val;
7954 /* Allocate stubs for exported Thumb functions on v4t. */
7963 ARM2THUMB_GLUE_SECTION_NAME);
7981 }
7983 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7985 static bfd_vma
7987 {
7989 bfd_vma glue_addr;
7998 ARM_BX_GLUE_SECTION_NAME);
8008 {
8014 }
8017 }
8019 /* Generate Arm stubs for exported Thumb symbols. */
8020 static void
8023 {
8027 /* Ignore this if we are not called by the ELF backend linker. */
8034 /* If blx is available then exported Thumb symbols are OK and there is
8035 nothing to do. */
8040 link_info);
8041 }
8043 /* Reserve space for COUNT dynamic relocations in relocation selection
8044 SRELOC. */
8046 static void
8048 bfd_size_type count)
8049 {
8057 }
8059 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8060 dynamic, the relocations should go in SRELOC, otherwise they should
8061 go in the special .rel.iplt section. */
8063 static void
8065 bfd_size_type count)
8066 {
8072 else
8073 {
8076 }
8077 }
8079 /* Add relocation REL to the end of relocation section SRELOC. */
8081 static void
8084 {
8099 }
8101 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8102 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8103 to .plt. */
8105 static void
8107 bfd_boolean is_iplt_entry,
8110 {
8118 {
8122 /* NaCl uses a special first entry in .iplt too. */
8126 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8128 }
8129 else
8130 {
8134 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8137 /* If this is the first .plt entry, make room for the special
8138 first entry. */
8143 }
8145 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8152 {
8153 /* We also need to make an entry in the .got.plt section, which
8154 will be placed in the .got section by the linker script. */
8157 else
8160 }
8161 }
8163 static bfd_vma
8165 {
8167 }
8169 static bfd_vma
8171 {
8173 }
8175 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8176 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8177 Otherwise, DYNINDX is the index of the symbol in the dynamic
8178 symbol table and SYM_VALUE is undefined.
8180 ROOT_PLT points to the offset of the PLT entry from the start of its
8181 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
8182 bookkeeping information.
8184 Returns FALSE if there was a problem. */
8186 static bfd_boolean
8191 {
8197 bfd_vma plt_index;
8198 Elf_Internal_Rela rel;
8199 bfd_vma plt_header_size;
8200 bfd_vma got_header_size;
8204 /* Pick the appropriate sections and sizes. */
8206 {
8211 /* There are no reserved entries in .igot.plt, and no special
8212 first entry in .iplt. */
8215 }
8216 else
8217 {
8224 }
8227 /* Fill in the entry in the procedure linkage table. */
8229 {
8238 /* Fill in the entry in the .rel.plt section. */
8244 /* Get the index in the procedure linkage table which
8245 corresponds to this symbol. This is the index of this symbol
8246 in all the symbols for which we are making plt entries. The
8247 first entry in the procedure linkage table is reserved. */
8250 }
8251 else
8252 {
8259 /* Get the offset into the .(i)got.plt table of the entry that
8260 corresponds to this function. */
8263 /* Get the index in the procedure linkage table which
8264 corresponds to this symbol. This is the index of this symbol
8265 in all the symbols for which we are making plt entries.
8266 After the reserved .got.plt entries, all symbols appear in
8267 the same order as in .plt. */
8270 /* Calculate the address of the GOT entry. */
8275 /* ...and the address of the PLT entry. */
8282 {
8284 bfd_vma val;
8287 {
8295 else
8297 }
8298 }
8300 {
8302 bfd_vma val;
8305 {
8315 else
8317 }
8322 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8323 referencing the GOT for this PLT entry. */
8330 /* Create the R_ARM_ABS32 relocation referencing the
8331 beginning of the PLT for this GOT entry. */
8336 }
8338 {
8339 /* Calculate the displacement between the PLT slot and the
8340 common tail that's part of the special initial PLT slot. */
8341 int32_t tail_displacement
8351 /* Calculate the displacement between the PLT slot and the entry
8352 in the GOT. The offset accounts for the value produced by
8353 adding to pc in the penultimate instruction of the PLT stub. */
8354 got_displacement = (got_address
8357 /* NaCl does not support interworking at all. */
8375 }
8377 {
8378 /* PR ld/16017: Generate thumb only PLT entries. */
8380 {
8381 /* FIXME: We ought to be able to generate thumb-1 PLT
8382 instructions... */
8384 output_bfd);
8386 }
8388 /* Calculate the displacement between the PLT slot and the entry in
8389 the GOT. The 12-byte offset accounts for the value produced by
8390 adding to pc in the 3rd instruction of the PLT stub. */
8393 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8394 instead of 'put_thumb_insn'. */
8415 }
8416 else
8417 {
8418 /* Calculate the displacement between the PLT slot and the
8419 entry in the GOT. The eight-byte offset accounts for the
8420 value produced by adding to pc in the first instruction
8421 of the PLT stub. */
8425 {
8430 }
8433 {
8448 #ifdef FOUR_WORD_PLT
8450 #endif
8451 }
8452 else
8453 {
8470 }
8471 }
8473 /* Fill in the entry in the .rel(a).(i)plt section. */
8477 {
8478 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8479 The dynamic linker or static executable then calls SYM_VALUE
8480 to determine the correct run-time value of the .igot.plt entry. */
8483 }
8484 else
8485 {
8489 }
8491 /* Fill in the entry in the global offset table. */
8494 }
8498 else
8499 {
8502 }
8505 }
8507 /* Some relocations map to different relocations depending on the
8508 target. Return the real relocation. */
8510 static int
8513 {
8515 {
8519 else
8527 }
8528 }
8530 /* Return the base VMA address which should be subtracted from real addresses
8531 when resolving @dtpoff relocation.
8532 This is PT_TLS segment p_vaddr. */
8534 static bfd_vma
8536 {
8537 /* If tls_sec is NULL, we should have signalled an error already. */
8541 }
8543 /* Return the relocation value for @tpoff relocation
8544 if STT_TLS virtual address is ADDRESS. */
8546 static bfd_vma
8548 {
8550 bfd_vma base;
8552 /* If tls_sec is NULL, we should have signalled an error already. */
8557 }
8559 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8560 VALUE is the relocation value. */
8562 static bfd_reloc_status_type
8564 {
8571 }
8573 /* Handle TLS relaxations. Relaxing is possible for symbols that use
8574 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8575 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8577 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8578 is to then call final_link_relocate. Return other values in the
8579 case of error.
8581 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8582 the pre-relaxed code. It would be nice if the relocs were updated
8583 to match the optimization. */
8585 static bfd_reloc_status_type
8589 {
8593 {
8600 else
8601 {
8605 else
8607 }
8612 /* Thumb insn. */
8615 {
8617 /* nop */
8619 }
8621 {
8623 /* nop */
8625 else
8626 /* ldr rx,[ry] */
8628 }
8630 {
8632 /* nop */
8634 else
8635 /* mov r0, rx */
8638 }
8639 else
8640 {
8642 /* It's a 32 bit instruction, fetch the rest of it for
8643 error generation. */
8650 }
8654 /* arm insn. */
8657 {
8659 /* mov rx, ry */
8662 }
8664 {
8666 /* nop */
8668 else
8669 /* ldr rx,[ry] */
8672 }
8674 {
8676 /* nop */
8678 else
8679 /* mov r0, rx */
8682 }
8683 else
8684 {
8689 }
8693 /* GD->IE relaxation, turn the instruction into 'nop' or
8694 'ldr r0, [pc,r0]' */
8700 /* GD->IE relaxation. */
8702 /* add r0,pc; ldr r0, [r0] */
8705 /* nop.w */
8707 else
8708 /* nop; nop */
8714 }
8716 }
8718 /* For a given value of n, calculate the value of G_n as required to
8719 deal with group relocations. We return it in the form of an
8720 encoded constant-and-rotation, together with the final residual. If n is
8721 specified as less than zero, then final_residual is filled with the
8722 input value and no further action is performed. */
8724 static bfd_vma
8726 {
8728 bfd_vma g_n;
8733 {
8736 /* Calculate which part of the value to mask. */
8739 else
8740 {
8743 /* Determine the most significant bit in the residual and
8744 align the resulting value to a 2-bit boundary. */
8749 /* The desired shift is now (msb - 6), or zero, whichever
8750 is the greater. */
8754 }
8756 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8761 /* Calculate the residual for the next time around. */
8763 }
8768 }
8770 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
8771 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
8773 static int
8775 {
8785 }
8787 /* Perform a relocation as part of a final link. */
8789 static bfd_reloc_status_type
8796 bfd_vma value,
8805 {
8815 bfd_vma addend;
8816 bfd_signed_vma signed_addend;
8818 bfd_vma dynreloc_value;
8823 bfd_vma plt_offset;
8824 bfd_vma gotplt_offset;
8825 bfd_boolean has_iplt_entry;
8833 /* Some relocation types map to different relocations depending on the
8834 target. We pick the right one here. */
8837 /* It is possible to have linker relaxations on some TLS access
8838 models. Update our information here. */
8851 else
8857 {
8861 {
8865 }
8866 else
8868 }
8869 else
8872 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8873 are resolving a function call relocation. */
8880 /* Record the symbol information that should be used in dynamic
8881 relocations. */
8887 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8888 VALUE appropriately for relocations that we resolve at link time. */
8892 {
8897 {
8901 /* Populate .iplt entries here, because not all of them will
8902 be seen by finish_dynamic_symbol. The lower bit is set if
8903 we have already populated the entry. */
8905 plt_offset--;
8906 else
8907 {
8911 else
8913 }
8915 /* Static relocations always resolve to the .iplt entry. */
8922 /* If there are non-call relocations that resolve to the .iplt
8923 entry, then all dynamic ones must too. */
8925 {
8928 }
8929 }
8930 else
8931 /* We populate the .plt entry in finish_dynamic_symbol. */
8933 }
8934 else
8935 {
8939 }
8942 {
8944 /* We don't need to find a value for this symbol. It's just a
8945 marker. */
8963 /* Handle relocations which should use the PLT entry. ABS32/REL32
8964 will use the symbol's value, which may point to a PLT entry, but we
8965 don't need to handle that here. If we created a PLT entry, all
8966 branches in this object should go to it, except if the PLT is too
8967 far away, in which case a long branch stub should be inserted. */
8974 {
8975 /* If we've created a .plt section, and assigned a PLT entry
8976 to this function, it must either be a STT_GNU_IFUNC reference
8977 or not be known to bind locally. In other cases, we should
8978 have cleared the PLT entry by now. */
8988 }
8990 /* When generating a shared object or relocatable executable, these
8991 relocations are copied into the output file to be resolved at
8992 run time. */
9011 {
9012 Elf_Internal_Rela outrel;
9017 {
9028 }
9033 {
9039 }
9063 else
9064 {
9067 /* This symbol is local, or marked to become local. */
9070 {
9073 /* On Symbian OS, the data segment and text segement
9074 can be relocated independently. Therefore, we
9075 must indicate the segment to which this
9076 relocation is relative. The BPABI allows us to
9077 use any symbol in the right segment; we just use
9078 the section symbol as it is convenient. (We
9079 cannot use the symbol given by "h" directly as it
9080 will not appear in the dynamic symbol table.)
9082 Note that the dynamic linker ignores the section
9083 symbol value, so we don't subtract osec->vma
9084 from the emitted reloc addend. */
9087 else
9091 {
9097 else
9100 }
9102 }
9103 else
9104 /* On SVR4-ish systems, the dynamic loader cannot
9105 relocate the text and data segments independently,
9106 so the symbol does not matter. */
9109 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9110 to the .iplt entry. Instead, every non-call reference
9111 must use an R_ARM_IRELATIVE relocation to obtain the
9112 correct run-time address. */
9114 else
9118 else
9120 }
9124 /* If this reloc is against an external symbol, we do not want to
9125 fiddle with the addend. Otherwise, we need to include the symbol
9126 value so that it becomes an addend for the dynamic reloc. */
9133 }
9135 {
9144 {
9148 {
9149 /* Check for Arm calling Arm function. */
9150 /* FIXME: Should we translate the instruction into a BL
9151 instruction instead ? */
9155 input_bfd,
9157 }
9159 {
9160 /* Check for Arm calling Thumb function. */
9162 {
9167 error_message))
9169 else
9171 }
9172 }
9174 /* Check if a stub has to be inserted because the
9175 destination is too far or we are changing mode. */
9179 {
9190 {
9191 /* The target is out of reach, so redirect the
9192 branch to the local stub for this function. */
9196 stub_type);
9197 {
9205 }
9206 }
9207 else
9208 {
9209 /* If the call goes through a PLT entry, make sure to
9210 check distance to the right destination address. */
9212 {
9217 /* The PLT entry is in ARM mode, regardless of the
9218 target function. */
9220 }
9221 }
9222 }
9224 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9225 where:
9226 S is the address of the symbol in the relocation.
9227 P is address of the instruction being relocated.
9228 A is the addend (extracted from the instruction) in bytes.
9230 S is held in 'value'.
9231 P is the base address of the section containing the
9232 instruction plus the offset of the reloc into that
9233 section, ie:
9234 (input_section->output_section->vma +
9235 input_section->output_offset +
9236 rel->r_offset).
9237 A is the addend, converted into bytes, ie:
9238 (signed_addend * 4)
9240 Note: None of these operations have knowledge of the pipeline
9241 size of the processor, thus it is up to the assembler to
9242 encode this information into the addend. */
9248 else
9249 /* RELA addends do not have to be adjusted by howto->size. */
9255 /* A branch to an undefined weak symbol is turned into a jump to
9256 the next instruction unless a PLT entry will be created.
9257 Do the same for local undefined symbols (but not for STN_UNDEF).
9258 The jump to the next instruction is optimized as a NOP depending
9259 on the architecture. */
9263 {
9268 else
9270 }
9271 else
9272 {
9273 /* Perform a signed range check. */
9284 {
9285 /* Set the H bit in the BLX instruction. */
9287 {
9290 else
9292 }
9294 /* Select the correct instruction (BL or BLX). */
9295 /* Only if we are not handling a BL to a stub. In this
9296 case, mode switching is performed by the stub. */
9300 {
9303 }
9304 }
9305 }
9306 }
9338 {
9339 /* Check for overflow. */
9342 }
9348 }
9354 /* PR 16202: Refectch the addend using the correct size. */
9359 /* There is no way to tell whether the user intended to use a signed or
9360 unsigned addend. When checking for overflow we accept either,
9361 as specified by the AAELF. */
9369 /* PR 16202: Refectch the addend using the correct size. */
9374 /* See comment for R_ARM_ABS8. */
9382 /* Support ldr and str instructions for the thumb. */
9384 {
9385 /* Need to refetch addend. */
9387 /* ??? Need to determine shift amount from operand size. */
9389 }
9392 /* ??? Isn't value unsigned? */
9396 /* ??? Value needs to be properly shifted into place first. */
9402 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9403 {
9404 bfd_vma insn;
9405 bfd_signed_vma relocation;
9411 {
9416 }
9438 }
9441 /* PR 10073: This reloc is not generated by the GNU toolchain,
9442 but it is supported for compatibility with third party libraries
9443 generated by other compilers, specifically the ARM/IAR. */
9444 {
9445 bfd_vma insn;
9446 bfd_signed_vma relocation;
9460 /* We do not check for overflow of this reloc. Although strictly
9461 speaking this is incorrect, it appears to be necessary in order
9462 to work with IAR generated relocs. Since GCC and GAS do not
9463 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9464 a problem for them. */
9472 }
9475 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9476 {
9477 bfd_vma insn;
9478 bfd_signed_vma relocation;
9484 {
9488 }
9508 }
9513 /* Thumb BL (branch long instruction). */
9514 {
9515 bfd_vma relocation;
9516 bfd_vma reloc_sign;
9520 bfd_signed_vma reloc_signed_max;
9521 bfd_signed_vma reloc_signed_min;
9522 bfd_vma check;
9523 bfd_signed_vma signed_check;
9527 /* A branch to an undefined weak symbol is turned into a jump to
9528 the next instruction unless a PLT entry will be created.
9529 The jump to the next instruction is optimized as a NOP.W for
9530 Thumb-2 enabled architectures. */
9533 {
9535 {
9538 }
9539 else
9540 {
9543 }
9545 }
9547 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
9548 with Thumb-1) involving the J1 and J2 bits. */
9550 {
9560 /* Sign extend. */
9564 }
9567 {
9568 /* Check for Thumb to Thumb call. */
9569 /* FIXME: Should we translate the instruction into a BL
9570 instruction instead ? */
9574 input_bfd,
9576 }
9577 else
9578 {
9579 /* If it is not a call to Thumb, assume call to Arm.
9580 If it is a call relative to a section name, then it is not a
9581 function call at all, but rather a long jump. Calls through
9582 the PLT do not require stubs. */
9584 {
9586 {
9587 /* Convert BL to BLX. */
9589 }
9592 {
9596 error_message))
9598 else
9600 }
9601 }
9605 {
9606 /* Make sure this is a BL. */
9608 }
9609 }
9613 {
9614 /* Check if a stub has to be inserted because the destination
9615 is too far. */
9627 {
9628 /* The target is out of reach or we are changing modes, so
9629 redirect the branch to the local stub for this
9630 function. */
9634 stub_type);
9636 {
9643 }
9645 /* If this call becomes a call to Arm, force BLX. */
9647 {
9652 }
9653 }
9654 }
9656 /* Handle calls via the PLT. */
9658 {
9666 {
9667 /* If the Thumb BLX instruction is available, convert
9668 the BL to a BLX instruction to call the ARM-mode
9669 PLT entry. */
9672 }
9673 else
9674 {
9676 /* Target the Thumb stub before the ARM PLT entry. */
9679 }
9681 }
9691 /* If this is a signed value, the rightshift just dropped
9692 leading 1 bits (assuming twos complement). */
9695 else
9698 /* Calculate the permissable maximum and minimum values for
9699 this relocation according to whether we're relocating for
9700 Thumb-2 or not. */
9707 /* Assumes two's complement. */
9712 /* For a BLX instruction, make sure that the relocation is rounded up
9713 to a word boundary. This follows the semantics of the instruction
9714 which specifies that bit 1 of the target address will come from bit
9715 1 of the base address. */
9718 /* Put RELOCATION back into the insn. Assumes two's complement.
9719 We use the Thumb-2 encoding, which is safe even if dealing with
9720 a Thumb-1 instruction by virtue of our overflow check above. */
9730 /* Put the relocated value back in the object file: */
9735 }
9739 /* Thumb32 conditional branch instruction. */
9740 {
9741 bfd_vma relocation;
9747 bfd_signed_vma signed_check;
9752 /* Need to refetch the addend, reconstruct the top three bits,
9753 and squish the two 11 bit pieces together. */
9755 {
9769 }
9771 /* Handle calls via the PLT. */
9773 {
9777 /* Target the Thumb stub before the ARM PLT entry. */
9780 }
9789 {
9793 stub_type);
9795 {
9799 }
9800 }
9811 /* Put RELOCATION back into the insn. */
9812 {
9821 }
9823 /* Put the relocated value back in the object file: */
9828 }
9833 /* Thumb B (branch) instruction). */
9834 {
9835 bfd_signed_vma relocation;
9838 bfd_signed_vma signed_check;
9840 /* CZB cannot jump backward. */
9845 {
9846 /* Need to refetch addend. */
9849 {
9853 }
9854 else
9856 /* The value in the insn has been right shifted. We need to
9857 undo this, so that we can perform the address calculation
9858 in terms of bytes. */
9860 }
9872 else
9878 /* Assumes two's complement. */
9883 }
9888 {
9889 bfd_vma insn;
9890 bfd_vma relocation;
9894 {
9895 /* Extract the addend. */
9898 }
9908 }
9916 /* Relocation is relative to the start of the
9917 global offset table. */
9923 /* If we are addressing a Thumb function, we need to adjust the
9924 address by one, so that attempts to call the function pointer will
9925 correctly interpret it as Thumb code. */
9929 /* Note that sgot->output_offset is not involved in this
9930 calculation. We always want the start of .got. If we
9931 define _GLOBAL_OFFSET_TABLE in a different way, as is
9932 permitted by the ABI, we might have to change this
9933 calculation. */
9940 /* Use global offset table as symbol value. */
9954 /* Relocation is to the entry for this symbol in the
9955 global offset table. */
9962 {
9963 /* We have a relocation against a locally-binding STT_GNU_IFUNC
9964 symbol, and the relocation resolves directly to the runtime
9965 target rather than to the .iplt entry. This means that any
9966 .got entry would be the same value as the .igot.plt entry,
9967 so there's no point creating both. */
9970 }
9972 {
9973 bfd_vma off;
9978 {
9979 /* We have already processsed one GOT relocation against
9980 this symbol. */
9985 }
9986 else
9987 {
9988 Elf_Internal_Rela outrel;
9991 {
9992 /* If the symbol doesn't resolve locally in a static
9993 object, we have an undefined reference. If the
9994 symbol doesn't resolve locally in a dynamic object,
9995 it should be resolved by the dynamic linker. */
9997 {
10000 }
10001 else
10004 }
10005 else
10006 {
10013 else
10016 }
10018 /* The GOT entry is initialized to zero by default.
10019 See if we should install a different value. */
10022 {
10026 }
10029 {
10034 }
10036 }
10038 }
10039 else
10040 {
10041 bfd_vma off;
10048 /* The offset must always be a multiple of 4. We use the
10049 least significant bit to record whether we have already
10050 generated the necessary reloc. */
10053 else
10054 {
10059 {
10060 Elf_Internal_Rela outrel;
10068 else
10071 }
10074 }
10077 }
10093 {
10094 bfd_vma off;
10103 else
10104 {
10105 /* If we don't know the module number, create a relocation
10106 for it. */
10108 {
10109 Elf_Internal_Rela outrel;
10124 }
10125 else
10129 }
10137 }
10146 {
10154 {
10155 bfd_boolean dyn;
10159 h)
10162 {
10165 }
10169 }
10170 else
10171 {
10176 }
10178 /* Linker relaxations happens from one of the
10179 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
10187 else
10188 {
10190 Elf_Internal_Rela outrel;
10193 /* The GOT entries have not been initialized yet. Do it
10194 now, and emit any relocations. If both an IE GOT and a
10195 GD GOT are necessary, we emit the GD first. */
10201 {
10204 }
10207 {
10210 /* We should have relaxed, unless this is an undefined
10211 weak symbol. */
10220 + offplt
10232 /* For globals, the first word in the relocation gets
10233 the relocation index and the top bit set, or zero,
10234 if we're binding now. For locals, it gets the
10235 symbol's offset in the tls section. */
10243 /* Second word in the relocation is always zero. */
10247 }
10249 {
10251 {
10267 else
10268 {
10271 R_ARM_TLS_DTPOFF32);
10280 }
10281 }
10282 else
10283 {
10284 /* If we are not emitting relocations for a
10285 general dynamic reference, then we must be in a
10286 static link or an executable link with the
10287 symbol binding locally. Mark it as belonging
10288 to module 1, the executable. */
10293 }
10296 }
10299 {
10301 {
10304 else
10316 }
10317 else
10321 }
10325 else
10327 }
10336 {
10337 bfd_signed_vma offset;
10338 /* TLS stubs are arm mode. The original symbol is a
10339 data object, so branch_type is bogus. */
10341 enum elf32_arm_stub_type stub_type
10349 {
10351 = elf32_arm_get_stub_entry
10357 }
10358 else
10364 {
10374 }
10375 else
10376 {
10377 /* Thumb blx encodes the offset in a complicated
10378 fashion. */
10388 {
10390 }
10391 else
10392 {
10394 /* Round up the offset to a word boundary. */
10396 }
10408 }
10409 }
10410 /* These relocations needs special care, as besides the fact
10411 they point somewhere in .gotplt, the addend must be
10412 adjusted accordingly depending on the type of instruction
10413 we refer to. */
10415 {
10424 {
10431 /* bl/blx */
10434 /* add */
10436 else
10437 {
10443 }
10444 }
10445 else
10446 {
10450 {
10466 }
10467 }
10475 }
10476 else
10485 }
10489 {
10495 }
10496 else
10505 {
10508 /* Ensure that we have a BX instruction. */
10512 {
10513 /* Branch to veneer. */
10514 bfd_vma glue_addr;
10521 }
10522 else
10523 {
10524 /* Preserve Rm (lowest four bits) and the condition code
10525 (highest four bits). Other bits encode MOV PC,Rm. */
10527 }
10530 }
10537 /* Until we properly support segment-base-relative addressing then
10538 we assume the segment base to be zero, as for the group relocations.
10539 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10540 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10544 {
10548 {
10551 }
10573 }
10580 /* Until we properly support segment-base-relative addressing then
10581 we assume the segment base to be zero, as for the above relocations.
10582 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10583 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10584 as R_ARM_THM_MOVT_ABS. */
10588 {
10589 bfd_vma insn;
10595 {
10601 }
10627 }
10640 {
10644 /* sb is the origin of the *segment* containing the symbol. */
10646 bfd_vma residual;
10647 bfd_vma g_n;
10648 bfd_signed_vma signed_value;
10651 /* Determine which group of bits to select. */
10653 {
10675 }
10677 /* If REL, extract the addend from the insn. If RELA, it will
10678 have already been fetched for us. */
10680 {
10687 else
10688 {
10689 /* Compensate for the fact that in the instruction, the
10690 rotation is stored in multiples of 2 bits. */
10693 /* Rotate "constant" right by "rotation" bits. */
10696 }
10698 /* Determine if the instruction is an ADD or a SUB.
10699 (For REL, this determines the sign of the addend.) */
10702 {
10708 }
10711 }
10713 /* Compute the value (X) to go in the place. */
10719 /* PC relative. */
10721 else
10722 /* Section base relative. */
10725 /* If the target symbol is a Thumb function, then set the
10726 Thumb bit in the address. */
10730 /* Calculate the value of the relevant G_n, in encoded
10731 constant-with-rotation format. */
10735 /* Check for overflow if required. */
10742 {
10749 }
10751 /* Mask out the value and the ADD/SUB part of the opcode; take care
10752 not to destroy the S bit. */
10755 /* Set the opcode according to whether the value to go in the
10756 place is negative. */
10759 else
10762 /* Encode the offset. */
10766 }
10775 {
10779 /* sb is the origin of the *segment* containing the symbol. */
10781 bfd_vma residual;
10782 bfd_signed_vma signed_value;
10785 /* Determine which groups of bits to calculate. */
10787 {
10805 }
10807 /* If REL, extract the addend from the insn. If RELA, it will
10808 have already been fetched for us. */
10810 {
10813 }
10815 /* Compute the value (X) to go in the place. */
10819 /* PC relative. */
10821 else
10822 /* Section base relative. */
10825 /* Calculate the value of the relevant G_{n-1} to obtain
10826 the residual at that stage. */
10830 /* Check for overflow. */
10832 {
10838 }
10840 /* Mask out the value and U bit. */
10843 /* Set the U bit if the value to go in the place is non-negative. */
10847 /* Encode the offset. */
10851 }
10860 {
10864 /* sb is the origin of the *segment* containing the symbol. */
10866 bfd_vma residual;
10867 bfd_signed_vma signed_value;
10870 /* Determine which groups of bits to calculate. */
10872 {
10890 }
10892 /* If REL, extract the addend from the insn. If RELA, it will
10893 have already been fetched for us. */
10895 {
10898 }
10900 /* Compute the value (X) to go in the place. */
10904 /* PC relative. */
10906 else
10907 /* Section base relative. */
10910 /* Calculate the value of the relevant G_{n-1} to obtain
10911 the residual at that stage. */
10915 /* Check for overflow. */
10917 {
10923 }
10925 /* Mask out the value and U bit. */
10928 /* Set the U bit if the value to go in the place is non-negative. */
10932 /* Encode the offset. */
10936 }
10945 {
10949 /* sb is the origin of the *segment* containing the symbol. */
10951 bfd_vma residual;
10952 bfd_signed_vma signed_value;
10955 /* Determine which groups of bits to calculate. */
10957 {
10975 }
10977 /* If REL, extract the addend from the insn. If RELA, it will
10978 have already been fetched for us. */
10980 {
10983 }
10985 /* Compute the value (X) to go in the place. */
10989 /* PC relative. */
10991 else
10992 /* Section base relative. */
10995 /* Calculate the value of the relevant G_{n-1} to obtain
10996 the residual at that stage. */
11000 /* Check for overflow. (The absolute value to go in the place must be
11001 divisible by four and, after having been divided by four, must
11002 fit in eight bits.) */
11004 {
11010 }
11012 /* Mask out the value and U bit. */
11015 /* Set the U bit if the value to go in the place is non-negative. */
11019 /* Encode the offset. */
11023 }
11028 }
11029 }
11031 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11032 static void
11036 bfd_signed_vma increment)
11037 {
11038 bfd_signed_vma addend;
11042 {
11060 }
11061 else
11062 {
11063 bfd_vma contents;
11067 /* Get the (signed) value from the instruction. */
11070 {
11071 bfd_signed_vma mask;
11076 }
11078 /* Add in the increment, (which is a byte value). */
11080 {
11092 /* Should we check for overflow here ? */
11094 /* Drop any undesired bits. */
11097 }
11102 }
11103 }
11105 #define IS_ARM_TLS_RELOC(R_TYPE) \
11106 ((R_TYPE) == R_ARM_TLS_GD32 \
11107 || (R_TYPE) == R_ARM_TLS_LDO32 \
11108 || (R_TYPE) == R_ARM_TLS_LDM32 \
11109 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11110 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11111 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11112 || (R_TYPE) == R_ARM_TLS_LE32 \
11113 || (R_TYPE) == R_ARM_TLS_IE32 \
11114 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11116 /* Specific set of relocations for the gnu tls dialect. */
11117 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11118 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11119 || (R_TYPE) == R_ARM_TLS_CALL \
11120 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11121 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11122 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
11124 /* Relocate an ARM ELF section. */
11126 static bfd_boolean
11135 {
11153 {
11160 bfd_vma relocation;
11161 bfd_reloc_status_type r;
11162 arelent bfd_reloc;
11183 {
11188 /* An object file might have a reference to a local
11189 undefined symbol. This is a daft object file, but we
11190 should at least do something about it. V4BX & NONE
11191 relocations do not use the symbol and are explicitly
11192 allowed to use the undefined symbol, so allow those.
11193 Likewise for relocations against STN_UNDEF. */
11199 {
11206 }
11209 {
11216 {
11221 {
11243 {
11249 }
11253 /* Get the (signed) value from the instruction. */
11256 {
11257 bfd_signed_vma mask;
11262 }
11264 }
11267 addend =
11272 /* Cases here must match those in the preceding
11273 switch statement. */
11275 {
11298 }
11299 }
11300 }
11301 else
11303 }
11304 else
11305 {
11314 }
11321 {
11322 /* This is a relocatable link. We don't have to change
11323 anything, unless the reloc is against a section symbol,
11324 in which case we have to adjust according to where the
11325 section symbol winds up in the output section. */
11327 {
11331 else
11333 }
11335 }
11339 else
11340 {
11341 name = (bfd_elf_string_from_elf_section
11345 }
11353 {
11358 input_bfd,
11359 input_section,
11362 name);
11363 }
11365 /* We call elf32_arm_final_link_relocate unless we're completely
11366 done, i.e., the relaxation produced the final output we want,
11367 and we won't let anybody mess with it. Also, we have to do
11368 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
11369 both in relaxed and non-relaxed cases. */
11375 {
11378 /* This may have been marked unresolved because it came from
11379 a shared library. But we've just dealt with that. */
11381 }
11382 else
11393 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11394 because such sections are not SEC_ALLOC and thus ld.so will
11395 not process them. */
11401 {
11404 input_bfd,
11405 input_section,
11410 }
11413 {
11415 {
11417 /* If the overflowing reloc was to an undefined symbol,
11418 we have already printed one error message and there
11419 is no point complaining again. */
11445 /* error_message should already be set. */
11450 /* Fall through. */
11452 common_error:
11459 }
11460 }
11461 }
11464 }
11466 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
11467 adds the edit to the start of the list. (The list must be built in order of
11468 ascending TINDEX: the function's callers are primarily responsible for
11469 maintaining that condition). */
11471 static void
11474 arm_unwind_edit_type type,
11477 {
11486 {
11496 }
11497 else
11498 {
11505 }
11506 }
11510 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11511 static void
11513 {
11521 /* Adjust size of output section. */
11523 }
11525 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11526 static void
11528 {
11538 }
11540 /* Scan .ARM.exidx tables, and create a list describing edits which should be
11541 made to those tables, such that:
11543 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11544 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
11545 codes which have been inlined into the index).
11547 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11549 The edits are applied when the tables are written
11550 (in elf32_arm_write_section). */
11552 bfd_boolean
11556 bfd_boolean merge_exidx_entries)
11557 {
11564 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11565 text sections. */
11567 {
11571 {
11579 {
11580 Elf_Internal_Shdr *linked_hdr
11588 /* Link this .ARM.exidx section back from the text section it
11589 describes. */
11591 }
11592 }
11593 }
11595 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11596 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
11597 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
11600 {
11607 bfd_vma j;
11618 {
11619 /* Section has no unwind data. */
11623 /* Ignore zero sized sections. */
11630 }
11632 /* Skip /DISCARD/ sections. */
11649 /* An error? */
11653 {
11658 /* An EXIDX_CANTUNWIND entry. */
11660 {
11664 }
11665 /* Inlined unwinding data. Merge if equal to previous. */
11667 {
11673 }
11674 /* Normal table entry. In theory we could merge these too,
11675 but duplicate entries are likely to be much less common. */
11676 else
11680 {
11685 }
11688 }
11690 /* Free contents if we allocated it ourselves. */
11694 /* Record edits to be applied later (in elf32_arm_write_section). */
11703 }
11705 /* Add terminating CANTUNWIND entry. */
11710 }
11712 static bfd_boolean
11715 {
11731 }
11733 static bfd_boolean
11735 {
11742 /* Invoke the regular ELF backend linker to do all the work. */
11746 /* Process stub sections (eg BE8 encoding, ...). */
11750 {
11752 /* Only process it once, in its link_sec slot. */
11754 {
11760 }
11761 }
11763 /* Write out any glue sections now that we have created all the
11764 stubs. */
11766 {
11769 ARM2THUMB_GLUE_SECTION_NAME))
11774 THUMB2ARM_GLUE_SECTION_NAME))
11779 VFP11_ERRATUM_VENEER_SECTION_NAME))
11784 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11789 ARM_BX_GLUE_SECTION_NAME))
11791 }
11794 }
11796 /* Return a best guess for the machine number based on the attributes. */
11798 static unsigned int
11800 {
11804 {
11810 {
11817 {
11825 {
11831 {
11835 }
11836 }
11837 }
11840 }
11844 }
11845 }
11847 /* Set the right machine number. */
11849 static bfd_boolean
11851 {
11857 {
11860 else
11862 }
11866 }
11868 /* Function to keep ARM specific flags in the ELF header. */
11870 static bfd_boolean
11872 {
11875 {
11877 {
11880 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11881 abfd);
11882 else
11883 _bfd_error_handler
11885 abfd);
11886 }
11887 }
11888 else
11889 {
11892 }
11895 }
11897 /* Copy backend specific data from one object module to another. */
11899 static bfd_boolean
11901 {
11902 flagword in_flags;
11903 flagword out_flags;
11914 {
11915 /* Cannot mix APCS26 and APCS32 code. */
11919 /* Cannot mix float APCS and non-float APCS code. */
11923 /* If the src and dest have different interworking flags
11924 then turn off the interworking bit. */
11926 {
11928 _bfd_error_handler
11929 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
11933 }
11935 /* Likewise for PIC, though don't warn for this case. */
11938 }
11944 }
11946 /* Values for Tag_ABI_PCS_R9_use. */
11947 enum
11948 {
11949 AEABI_R9_V6,
11950 AEABI_R9_SB,
11951 AEABI_R9_TLS,
11952 AEABI_R9_unused
11953 };
11955 /* Values for Tag_ABI_PCS_RW_data. */
11956 enum
11957 {
11958 AEABI_PCS_RW_data_absolute,
11959 AEABI_PCS_RW_data_PCrel,
11960 AEABI_PCS_RW_data_SBrel,
11961 AEABI_PCS_RW_data_unused
11962 };
11964 /* Values for Tag_ABI_enum_size. */
11965 enum
11966 {
11967 AEABI_enum_unused,
11968 AEABI_enum_short,
11969 AEABI_enum_wide,
11970 AEABI_enum_forced_wide
11971 };
11973 /* Determine whether an object attribute tag takes an integer, a
11974 string or both. */
11976 static int
11978 {
11987 else
11989 }
11991 /* The ABI defines that Tag_conformance should be emitted first, and that
11992 Tag_nodefaults should be second (if either is defined). This sets those
11993 two positions, and bumps up the position of all the remaining tags to
11994 compensate. */
11995 static int
11997 {
12007 }
12009 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
12010 static bfd_boolean
12012 {
12014 {
12015 _bfd_error_handler
12020 }
12021 else
12022 {
12023 _bfd_error_handler
12027 }
12028 }
12030 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
12031 Returns -1 if no architecture could be read. */
12033 static int
12035 {
12039 /* Note: the tag and its argument below are uleb128 values, though
12040 currently-defined values fit in one byte for each. */
12047 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12049 }
12051 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12052 The tag is removed if ARCH is -1. */
12054 static void
12056 {
12061 {
12064 }
12066 /* Note: the tag and its argument below are uleb128 values, though
12067 currently-defined values fit in one byte for each. */
12073 }
12075 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12076 into account. */
12078 static int
12081 {
12082 #define T(X) TAG_CPU_ARCH_##X
12085 {
12095 };
12097 {
12108 };
12110 {
12122 };
12124 {
12137 };
12139 {
12153 };
12155 {
12170 };
12172 {
12188 };
12190 {
12207 };
12209 {
12210 v6t2,
12211 v6k,
12212 v7,
12213 v6_m,
12214 v6s_m,
12215 v7e_m,
12216 v8,
12217 /* Pseudo-architecture. */
12218 v4t_plus_v6_m
12219 };
12221 /* Check we've not got a higher architecture than we know about. */
12224 {
12227 }
12229 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12235 /* And override the new tag if we have a Tag_also_compatible_with on the
12236 input. */
12245 /* Architectures before V6KZ add features monotonically. */
12251 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12252 as the canonical version. */
12254 {
12257 }
12258 else
12262 {
12266 }
12269 #undef T
12270 }
12272 /* Query attributes object to see if integer divide instructions may be
12273 present in an object. */
12274 static bfd_boolean
12276 {
12281 {
12283 /* Integer divide allowed if instruction contained in archetecture. */
12288 else
12292 /* Integer divide explicitly prohibited. */
12296 /* Unrecognised case - treat as allowing divide everywhere. */
12298 /* Integer divide allowed in ARM state. */
12300 }
12301 }
12303 /* Query attributes object to see if integer divide instructions are
12304 forbidden to be in the object. This is not the inverse of
12305 elf32_arm_attributes_accept_div. */
12306 static bfd_boolean
12308 {
12310 }
12312 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12313 are conflicting attributes. */
12315 static bfd_boolean
12317 {
12320 /* Some tags have 0 = don't care, 1 = strong requirement,
12321 2 = weak requirement. */
12327 /* Skip the linker stubs file. This preserves previous behavior
12328 of accepting unknown attributes in the first input file - but
12329 is that a bug? */
12333 /* Skip any input that hasn't attribute section.
12334 This enables to link object files without attribute section with
12335 any others. */
12340 {
12341 /* This is the first object. Copy the attributes. */
12346 /* Use the Tag_null value to indicate the attributes have been
12347 initialized. */
12350 /* We do not output objects with Tag_MPextension_use_legacy - we move
12351 the attribute's value to Tag_MPextension_use. */
12353 {
12357 {
12358 _bfd_error_handler
12362 }
12368 }
12371 }
12375 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12377 {
12378 /* Ignore mismatches if the object doesn't use floating point or is
12379 floating point ABI independent. */
12386 {
12387 _bfd_error_handler
12392 }
12393 }
12396 {
12397 /* Merge this attribute with existing attributes. */
12399 {
12402 /* These are merged after Tag_CPU_arch. */
12407 /* Use the first value seen. */
12411 {
12416 {
12417 /* These aren't real CPU names, but we can't guess
12418 that from the architecture version alone. */
12432 "ARM v8"
12433 };
12435 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12441 secondary_compat);
12443 /* Return with error if failed to merge. */
12451 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12455 {
12456 /* The output architecture has been changed to match the
12457 input architecture. Use the input names. */
12464 }
12465 else
12466 {
12469 }
12471 /* If we still don't have a value for Tag_CPU_name,
12472 make one up now. Tag_CPU_raw_name remains blank. */
12477 }
12484 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
12493 /* Use the largest value specified. */
12500 /* Use the smallest value specified. */
12509 {
12510 /* This error message should be enabled once all non-conformant
12511 binaries in the toolchain have had the attributes set
12512 properly.
12513 _bfd_error_handler
12514 (_("error: %B: 8-byte data alignment conflicts with %B"),
12515 obfd, ibfd);
12516 result = FALSE; */
12517 }
12518 /* Fall through. */
12521 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12522 value if greater than 2 (for future-proofing). */
12530 /* The virtualization tag effectively stores two bits of
12531 information: the intended use of TrustZone (in bit 0), and the
12532 intended use of Virtualization (in bit 1). */
12537 {
12540 else
12541 {
12542 _bfd_error_handler
12547 }
12548 }
12553 {
12554 /* 0 will merge with anything.
12555 'A' and 'S' merge to 'A'.
12556 'R' and 'S' merge to 'R'.
12557 'M' and 'A|R|S' is an error. */
12566 else
12567 {
12568 _bfd_error_handler
12570 ibfd,
12574 }
12575 }
12578 {
12579 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12580 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12581 when it's 0. It might mean absence of FP hardware if
12582 Tag_FP_arch is zero. */
12584 #define VFP_VERSION_COUNT 9
12585 static const struct
12586 {
12590 {
12600 };
12605 /* If the output has no requirement about FP hardware,
12606 follow the requirement of the input. */
12608 {
12614 }
12615 /* If the input has no requirement about FP hardware, do
12616 nothing. */
12618 {
12621 }
12623 /* Both the input and the output have nonzero Tag_FP_arch.
12624 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
12626 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12627 do nothing. */
12630 ;
12631 /* If the input and the output have different Tag_ABI_HardFP_use,
12632 the combination of them is 0 (implied by Tag_FP_arch). */
12637 /* Now we can handle Tag_FP_arch. */
12639 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12640 pick the biggest. */
12643 {
12646 }
12647 /* The output uses the superset of input features
12648 (ISA version) and registers. */
12655 /* This assumes all possible supersets are also a valid
12656 options. */
12658 {
12662 }
12664 }
12670 {
12671 /* It's sometimes ok to mix different configs, so this is only
12672 a warning. */
12673 _bfd_error_handler
12675 }
12681 {
12682 _bfd_error_handler
12685 }
12693 {
12694 _bfd_error_handler
12696 ibfd);
12698 }
12699 /* Use the smallest value specified. */
12706 {
12707 _bfd_error_handler
12708 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12710 }
12716 {
12719 {
12720 /* The existing object is compatible with anything.
12721 Use whatever requirements the new object has. */
12723 }
12727 {
12738 _bfd_error_handler
12739 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
12741 }
12742 }
12745 /* Aready done. */
12749 {
12750 _bfd_error_handler
12754 }
12757 /* Merged in target-independent code. */
12760 /* This is handled along with Tag_FP_arch. */
12764 {
12766 {
12767 _bfd_error_handler
12771 }
12772 }
12778 /* A value of zero on input means that the divide instruction may
12779 be used if available in the base architecture as specified via
12780 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12781 the user did not want divide instructions. A value of 2
12782 explicitly means that divide instructions were allowed in ARM
12783 and Thumb state. */
12797 /* We don't output objects with Tag_MPextension_use_legacy - we
12798 move the value to Tag_MPextension_use. */
12800 {
12802 {
12803 _bfd_error_handler
12806 ibfd);
12808 }
12809 }
12817 /* This tag is set if it exists, but the value is unused (and is
12818 typically zero). We don't actually need to do anything here -
12819 the merge happens automatically when the type flags are merged
12820 below. */
12823 /* Already done in Tag_CPU_arch. */
12826 /* Keep the attribute if it matches. Throw it away otherwise.
12827 No attribute means no claim to conform. */
12834 result
12836 }
12838 /* If out_attr was copied from in_attr then it won't have a type yet. */
12841 }
12843 /* Merge Tag_compatibility attributes and any common GNU ones. */
12847 /* Check for any attributes not known on ARM. */
12851 }
12854 /* Return TRUE if the two EABI versions are incompatible. */
12856 static bfd_boolean
12858 {
12859 /* v4 and v5 are the same spec before and after it was released,
12860 so allow mixing them. */
12866 }
12868 /* Merge backend specific data from an object file to the output
12869 object file when linking. */
12871 static bfd_boolean
12874 /* Display the flags field. */
12876 static bfd_boolean
12878 {
12884 /* Print normal ELF private data. */
12888 /* Ignore init flag - it may not be set, despite the flags field
12889 containing valid data. */
12891 /* xgettext:c-format */
12895 {
12897 /* The following flag bits are GNU extensions and not part of the
12898 official ARM ELF extended ABI. Hence they are only decoded if
12899 the EABI version is not set. */
12905 else
12912 else
12941 else
12952 else
12984 eabi:
12997 }
13012 }
13014 static int
13016 {
13018 {
13023 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13024 This allows us to distinguish between data used by Thumb instructions
13025 and non-data (which is probably code) inside Thumb regions of an
13026 executable. */
13033 }
13036 }
13044 {
13047 {
13051 }
13054 }
13056 /* Update the got entry reference counts for the section being removed. */
13058 static bfd_boolean
13063 {
13087 {
13092 bfd_boolean call_reloc_p;
13093 bfd_boolean may_become_dynamic_p;
13094 bfd_boolean may_need_local_target_p;
13100 {
13105 }
13115 {
13121 {
13124 }
13126 {
13129 }
13150 {
13153 }
13154 /* Fall through. */
13167 /* Should the interworking branches be here also? */
13170 {
13173 {
13176 }
13177 else
13179 }
13180 else
13186 }
13190 {
13191 /* If PLT refcount book-keeping is wrong and too low, we'll
13192 see a zero value (going to -1) for the root PLT reference
13193 count. */
13195 {
13198 }
13199 else
13200 /* A value of -1 means the symbol has become local, forced
13201 or seeing a hidden definition. Any other negative value
13202 is an error. */
13214 }
13217 {
13223 else
13224 {
13234 }
13237 {
13238 /* Everything must go for SEC. */
13241 }
13242 }
13243 }
13246 }
13248 /* Look through the relocs for a section during the first phase. */
13250 static bfd_boolean
13253 {
13261 bfd_boolean call_reloc_p;
13262 bfd_boolean may_become_dynamic_p;
13263 bfd_boolean may_need_local_target_p;
13277 /* Create dynamic sections for relocatable executables so that we can
13278 copy relocations. */
13281 {
13284 }
13299 {
13311 /* PR 9934: It is possible to have relocations that do not
13312 refer to symbols, thus it is also possible to have an
13313 object file containing relocations but no symbol table. */
13315 {
13317 r_symndx);
13319 }
13324 {
13326 {
13327 /* A local symbol. */
13332 }
13333 else
13334 {
13340 /* PR15323, ref flags aren't set for references in the
13341 same object. */
13343 }
13344 }
13352 /* Could be done earlier, if h were already available. */
13355 {
13365 /* This symbol requires a global offset table entry. */
13366 {
13370 {
13381 }
13387 {
13390 }
13391 else
13392 {
13393 /* This is a global offset table entry for a local symbol. */
13398 }
13400 /* If a variable is accessed with both tls methods, two
13401 slots may be created. */
13406 /* We will already have issued an error message if there
13407 is a TLS/non-TLS mismatch, based on the symbol
13408 type. So just combine any TLS types needed. */
13413 /* If the symbol is accessed in both IE and GDESC
13414 method, we're able to relax. Turn off the GDESC flag,
13415 without messing up with any other kind of tls types
13416 that may be involved. */
13421 {
13424 else
13426 }
13427 }
13428 /* Fall through. */
13433 /* Fall through. */
13455 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13456 ldr __GOTT_INDEX__ offsets. */
13458 {
13461 }
13462 /* Fall through. */
13469 {
13471 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13476 }
13478 /* Fall through. */
13482 {
13484 }
13485 /* Fall through. */
13493 /* Should the interworking branches be listed here? */
13496 {
13499 {
13500 /* In shared libraries and relocatable executables,
13501 we treat local relative references as calls;
13502 see the related SYMBOL_CALLS_LOCAL code in
13503 allocate_dynrelocs. */
13506 }
13507 else
13508 /* We are creating a shared library or relocatable
13509 executable, and this is a reloc against a global symbol,
13510 or a non-PC-relative reloc against a local symbol.
13511 We may need to copy the reloc into the output. */
13513 }
13514 else
13518 /* This relocation describes the C++ object vtable hierarchy.
13519 Reconstruct it for later use during GC. */
13525 /* This relocation describes which C++ vtable entries are actually
13526 used. Record for later use during GC. */
13533 }
13536 {
13538 /* We may need a .plt entry if the function this reloc
13539 refers to is in a different object, regardless of the
13540 symbol's type. We can't tell for sure yet, because
13541 something later might force the symbol local. */
13544 /* If this reloc is in a read-only section, we might
13545 need a copy reloc. We can't check reliably at this
13546 stage whether the section is read-only, as input
13547 sections have not yet been mapped to output sections.
13548 Tentatively set the flag for now, and correct in
13549 adjust_dynamic_symbol. */
13551 }
13555 {
13561 {
13564 }
13565 else
13566 {
13572 }
13574 /* If the symbol is a function that doesn't bind locally,
13575 this relocation will need a PLT entry. */
13582 /* It's too early to use htab->use_blx here, so we have to
13583 record possible blx references separately from
13584 relocs that definitely need a thumb stub. */
13592 }
13595 {
13598 /* Create a reloc section in dynobj. */
13600 {
13601 sreloc = _bfd_elf_make_dynamic_reloc_section
13607 /* BPABI objects never have dynamic relocations mapped. */
13609 {
13610 flagword flags;
13615 }
13616 }
13618 /* If this is a global symbol, count the number of
13619 relocations we need for this symbol. */
13622 else
13623 {
13627 }
13631 {
13642 }
13647 }
13648 }
13651 }
13653 /* Unwinding tables are not referenced directly. This pass marks them as
13654 required if the corresponding code section is marked. */
13656 static bfd_boolean
13658 elf_gc_mark_hook_fn gc_mark_hook)
13659 {
13662 bfd_boolean again;
13666 /* Marking EH data may cause additional code sections to be marked,
13667 requiring multiple passes. */
13670 {
13673 {
13681 {
13690 {
13694 }
13695 }
13696 }
13697 }
13700 }
13702 /* Treat mapping symbols as special target symbols. */
13704 static bfd_boolean
13706 {
13708 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
13709 }
13711 /* This is a copy of elf_find_function() from elf.c except that
13712 ARM mapping symbols are ignored when looking for function names
13713 and STT_ARM_TFUNC is considered to a function type. */
13715 static bfd_boolean
13719 bfd_vma offset,
13722 {
13729 {
13735 {
13744 /* Skip mapping symbols. */
13747 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
13749 /* Fall through. */
13753 {
13756 }
13758 }
13759 }
13770 }
13773 /* Find the nearest line to a particular section and offset, for error
13774 reporting. This code is a duplicate of the code in elf.c, except
13775 that it uses arm_elf_find_function. */
13777 static bfd_boolean
13781 bfd_vma offset,
13786 {
13794 {
13798 functionname_ptr);
13801 }
13803 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
13804 uses DWARF1. */
13824 }
13826 static bfd_boolean
13831 {
13832 bfd_boolean found;
13837 }
13839 /* Adjust a symbol defined by a dynamic object and referenced by a
13840 regular object. The current definition is in some section of the
13841 dynamic object, but we're not including those sections. We have to
13842 change the definition to something the rest of the link can
13843 understand. */
13845 static bfd_boolean
13848 {
13860 /* Make sure we know what is going on here. */
13871 /* If this is a function, put it in the procedure linkage table. We
13872 will fill in the contents of the procedure linkage table later,
13873 when we know the address of the .got section. */
13875 {
13876 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
13877 symbol binds locally. */
13883 {
13884 /* This case can occur if we saw a PLT32 reloc in an input
13885 file, but the symbol was never referred to by a dynamic
13886 object, or if all references were garbage collected. In
13887 such a case, we don't actually need to build a procedure
13888 linkage table, and we can just do a PC24 reloc instead. */
13894 }
13897 }
13898 else
13899 {
13900 /* It's possible that we incorrectly decided a .plt reloc was
13901 needed for an R_ARM_PC24 or similar reloc to a non-function sym
13902 in check_relocs. We can't decide accurately between function
13903 and non-function syms in check-relocs; Objects loaded later in
13904 the link may change h->type. So fix it now. */
13909 }
13911 /* If this is a weak symbol, and there is a real definition, the
13912 processor independent code will have arranged for us to see the
13913 real definition first, and we can just use the same value. */
13915 {
13921 }
13923 /* If there are no non-GOT references, we do not need a copy
13924 relocation. */
13928 /* This is a reference to a symbol defined by a dynamic object which
13929 is not a function. */
13931 /* If we are creating a shared library, we must presume that the
13932 only references to the symbol are via the global offset table.
13933 For such cases we need not do anything here; the relocations will
13934 be handled correctly by relocate_section. Relocatable executables
13935 can reference data in shared objects directly, so we don't need to
13936 do anything here. */
13940 /* We must allocate the symbol in our .dynbss section, which will
13941 become part of the .bss section of the executable. There will be
13942 an entry for this symbol in the .dynsym section. The dynamic
13943 object will contain position independent code, so all references
13944 from the dynamic object to this symbol will go through the global
13945 offset table. The dynamic linker will use the .dynsym entry to
13946 determine the address it must put in the global offset table, so
13947 both the dynamic object and the regular object will refer to the
13948 same memory location for the variable. */
13952 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
13953 copy the initial value out of the dynamic object and into the
13954 runtime process image. We need to remember the offset into the
13955 .rel(a).bss section we are going to use. */
13957 {
13963 }
13966 }
13968 /* Allocate space in .plt, .got and associated reloc sections for
13969 dynamic relocs. */
13971 static bfd_boolean
13973 {
13991 {
13992 /* Make sure this symbol is output as a dynamic symbol.
13993 Undefined weak syms won't yet be marked as dynamic. */
13996 {
13999 }
14001 /* If the call in the PLT entry binds locally, the associated
14002 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14003 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14004 than the .plt section. */
14006 {
14010 /* All non-call references can be resolved directly.
14011 This means that they can (and in some cases, must)
14012 resolve directly to the run-time target, rather than
14013 to the PLT. That in turns means that any .got entry
14014 would be equal to the .igot.plt entry, so there's
14015 no point having both. */
14017 }
14022 {
14025 /* If this symbol is not defined in a regular file, and we are
14026 not generating a shared library, then set the symbol to this
14027 location in the .plt. This is required to make function
14028 pointers compare as equal between the normal executable and
14029 the shared library. */
14032 {
14036 /* Make sure the function is not marked as Thumb, in case
14037 it is the target of an ABS32 relocation, which will
14038 point to the PLT entry. */
14040 }
14042 /* VxWorks executables have a second set of relocations for
14043 each PLT entry. They go in a separate relocation section,
14044 which is processed by the kernel loader. */
14046 {
14047 /* There is a relocation for the initial PLT entry:
14048 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14052 /* There are two extra relocations for each subsequent
14053 PLT entry: an R_ARM_32 relocation for the GOT entry,
14054 and an R_ARM_32 relocation for the PLT entry. */
14056 }
14057 }
14058 else
14059 {
14062 }
14063 }
14064 else
14065 {
14068 }
14074 {
14076 bfd_boolean dyn;
14080 /* Make sure this symbol is output as a dynamic symbol.
14081 Undefined weak syms won't yet be marked as dynamic. */
14084 {
14087 }
14090 {
14098 /* Non-TLS symbols need one GOT slot. */
14100 else
14101 {
14103 {
14104 /* R_ARM_TLS_DESC needs 2 GOT slots. */
14105 eh->tlsdesc_got
14110 /* plt.got_offset needs to know there's a TLS_DESC
14111 reloc in the middle of .got.plt. */
14113 }
14116 {
14117 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14118 the symbol is both GD and GDESC, got.offset may
14119 have been overwritten. */
14122 }
14125 /* R_ARM_TLS_IE32 needs one GOT slot. */
14127 }
14134 h)
14143 {
14151 {
14153 /* GDESC needs a trampoline to jump to. */
14155 }
14157 /* Only GD needs it. GDESC just emits one relocation per
14158 2 entries. */
14161 }
14163 {
14165 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14167 }
14170 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14171 they all resolve dynamically instead. Reserve room for the
14172 GOT entry's R_ARM_IRELATIVE relocation. */
14177 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
14179 }
14180 }
14181 else
14184 /* Allocate stubs for exported Thumb functions on v4t. */
14189 {
14196 /* Create a new symbol to regist the real location of the function. */
14210 /* Point the symbol at the stub. */
14215 }
14220 /* In the shared -Bsymbolic case, discard space allocated for
14221 dynamic pc-relative relocs against symbols which turn out to be
14222 defined in regular objects. For the normal shared case, discard
14223 space for pc-relative relocs that have become local due to symbol
14224 visibility changes. */
14227 {
14228 /* Relocs that use pc_count are PC-relative forms, which will appear
14229 on something like ".long foo - ." or "movw REG, foo - .". We want
14230 calls to protected symbols to resolve directly to the function
14231 rather than going via the plt. If people want function pointer
14232 comparisons to work as expected then they should avoid writing
14233 assembly like ".long foo - .". */
14235 {
14239 {
14244 else
14246 }
14247 }
14250 {
14254 {
14257 else
14259 }
14260 }
14262 /* Also discard relocs on undefined weak syms with non-default
14263 visibility. */
14266 {
14270 /* Make sure undefined weak symbols are output as a dynamic
14271 symbol in PIEs. */
14274 {
14277 }
14278 }
14282 {
14283 /* Output absolute symbols so that we can create relocations
14284 against them. For normal symbols we output a relocation
14285 against the section that contains them. */
14288 }
14290 }
14291 else
14292 {
14293 /* For the non-shared case, discard space for relocs against
14294 symbols which turn out to need copy relocs or are not
14295 dynamic. */
14303 {
14304 /* Make sure this symbol is output as a dynamic symbol.
14305 Undefined weak syms won't yet be marked as dynamic. */
14308 {
14311 }
14313 /* If that succeeded, we know we'll be keeping all the
14314 relocs. */
14317 }
14321 keep: ;
14322 }
14324 /* Finally, allocate space. */
14326 {
14332 else
14334 }
14337 }
14339 /* Find any dynamic relocs that apply to read-only sections. */
14341 static bfd_boolean
14343 {
14349 {
14353 {
14358 /* Not an error, just cut short the traversal. */
14360 }
14361 }
14363 }
14365 void
14368 {
14376 }
14378 /* Set the sizes of the dynamic sections. */
14380 static bfd_boolean
14383 {
14386 bfd_boolean plt;
14387 bfd_boolean relocs;
14400 {
14401 /* Set the contents of the .interp section to the interpreter. */
14403 {
14408 }
14409 }
14411 /* Set up .got offsets for local syms, and space for local dynamic
14412 relocs. */
14414 {
14420 bfd_size_type locsymcount;
14430 {
14435 {
14438 {
14439 /* Input section has been discarded, either because
14440 it is a copy of a linkonce section or due to
14441 linker script /DISCARD/, so we'll be discarding
14442 the relocs too. */
14443 }
14447 {
14448 /* Relocations in vxworks .tls_vars sections are
14449 handled specially by the loader. */
14450 }
14452 {
14457 }
14458 }
14459 }
14477 {
14481 {
14485 {
14490 /* All references to the PLT are calls, so all
14491 non-call references can resolve directly to the
14492 run-time target. This means that the .got entry
14493 would be the same as the .igot.plt entry, so there's
14494 no point creating both. */
14496 }
14497 else
14498 {
14501 }
14504 {
14510 else
14512 }
14513 }
14515 {
14520 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14523 {
14528 /* plt.got_offset needs to know there's a TLS_DESC
14529 reloc in the middle of .got.plt. */
14531 }
14536 {
14537 /* If the symbol is both GD and GDESC, *local_got
14538 may have been overwritten. */
14541 }
14547 /* If all references to an STT_GNU_IFUNC PLT are calls,
14548 then all non-call references, including this GOT entry,
14549 resolve directly to the run-time target. */
14555 {
14561 {
14565 }
14566 }
14567 }
14568 else
14570 }
14571 }
14574 {
14575 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14576 for R_ARM_TLS_LDM32 relocations. */
14581 }
14582 else
14585 /* Allocate global sym .plt and .got entries, and space for global
14586 sym dynamic relocs. */
14589 /* Here we rummage through the found bfds to collect glue information. */
14591 {
14595 /* Initialise mapping tables for code/data. */
14601 /* xgettext:c-format */
14604 }
14606 /* Allocate space for the glue sections now that we've sized them. */
14609 /* For every jump slot reserved in the sgotplt, reloc_count is
14610 incremented. However, when we reserve space for TLS descriptors,
14611 it's not incremented, so in order to compute the space reserved
14612 for them, it suffices to multiply the reloc count by the jump
14613 slot size. */
14618 {
14625 /* If we're not using lazy TLS relocations, don't generate the
14626 PLT and GOT entries they require. */
14628 {
14634 }
14635 }
14637 /* The check_relocs and adjust_dynamic_symbol entry points have
14638 determined the sizes of the various dynamic sections. Allocate
14639 memory for them. */
14643 {
14649 /* It's OK to base decisions on the section name, because none
14650 of the dynobj section names depend upon the input files. */
14654 {
14655 /* Remember whether there is a PLT. */
14657 }
14659 {
14661 {
14662 /* Remember whether there are any reloc sections other
14663 than .rel(a).plt and .rela.plt.unloaded. */
14667 /* We use the reloc_count field as a counter if we need
14668 to copy relocs into the output file. */
14670 }
14671 }
14677 {
14678 /* It's not one of our sections, so don't allocate space. */
14680 }
14683 {
14684 /* If we don't need this section, strip it from the
14685 output file. This is mostly to handle .rel(a).bss and
14686 .rel(a).plt. We must create both sections in
14687 create_dynamic_sections, because they must be created
14688 before the linker maps input sections to output
14689 sections. The linker does that before
14690 adjust_dynamic_symbol is called, and it is that
14691 function which decides whether anything needs to go
14692 into these sections. */
14695 }
14700 /* Allocate memory for the section contents. */
14704 }
14707 {
14708 /* Add some entries to the .dynamic section. We fill in the
14709 values later, in elf32_arm_finish_dynamic_sections, but we
14710 must add the entries now so that we get the correct size for
14711 the .dynamic section. The DT_DEBUG entry is filled in by the
14712 dynamic linker and used by the debugger. */
14713 #define add_dynamic_entry(TAG, VAL) \
14714 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
14717 {
14720 }
14723 {
14735 }
14738 {
14740 {
14745 }
14746 else
14747 {
14752 }
14753 }
14755 /* If any dynamic relocs apply to a read-only section,
14756 then we need a DT_TEXTREL entry. */
14759 info);
14762 {
14765 }
14769 }
14770 #undef add_dynamic_entry
14773 }
14775 /* Size sections even though they're not dynamic. We use it to setup
14776 _TLS_MODULE_BASE_, if needed. */
14778 static bfd_boolean
14781 {
14790 {
14793 tlsbase = elf_link_hash_lookup
14797 {
14813 }
14814 }
14816 }
14818 /* Finish up dynamic symbol handling. We set the contents of various
14819 dynamic sections here. */
14821 static bfd_boolean
14826 {
14837 {
14839 {
14844 }
14847 {
14848 /* Mark the symbol as undefined, rather than as defined in
14849 the .plt section. */
14851 /* If the symbol is weak we need to clear the value.
14852 Otherwise, the PLT entry would provide a definition for
14853 the symbol even if the symbol wasn't defined anywhere,
14854 and so the symbol would never be NULL. Leave the value if
14855 there were any relocations where pointer equality matters
14856 (this is a clue for the dynamic linker, to make function
14857 pointer comparisons work between an application and shared
14858 library). */
14861 }
14863 {
14864 /* At least one non-call relocation references this .iplt entry,
14865 so the .iplt entry is the function's canonical address. */
14873 }
14874 }
14877 {
14879 Elf_Internal_Rela rel;
14881 /* This symbol needs a copy reloc. Set it up. */
14895 }
14897 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
14898 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
14899 to the ".got" section. */
14905 }
14907 static void
14911 {
14915 {
14918 /* Emit mov pc,rx if bx is not permitted. */
14922 }
14923 }
14925 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
14926 other variants, NaCl needs this entry in a static executable's
14927 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
14928 zero. For .iplt really only the last bundle is useful, and .iplt
14929 could have a shorter first entry, with each individual PLT entry's
14930 relative branch calculated differently so it targets the last
14931 bundle instead of the instruction before it (labelled .Lplt_tail
14932 above). But it's simpler to keep the size and layout of PLT0
14933 consistent with the dynamic case, at the cost of some dead code at
14934 the start of .iplt and the one dead store to the stack at the start
14935 of .Lplt_tail. */
14936 static void
14939 {
14955 }
14957 /* Finish up the dynamic sections. */
14959 static bfd_boolean
14961 {
14974 /* A broken linker script might have discarded the dynamic sections.
14975 Catch this here so that we do not seg-fault later on. */
14981 {
14993 {
14994 Elf_Internal_Dyn dyn;
15001 {
15034 get_vma:
15037 {
15038 /* PR ld/14397: Issue an error message if a required section is missing. */
15043 }
15046 else
15047 /* In the BPABI, tags in the PT_DYNAMIC section point
15048 at the file offset, not the memory address, for the
15049 convenience of the post linker. */
15054 get_vma_if_bpabi:
15069 {
15070 /* My reading of the SVR4 ABI indicates that the
15071 procedure linkage table relocs (DT_JMPREL) should be
15072 included in the overall relocs (DT_REL). This is
15073 what Solaris does. However, UnixWare can not handle
15074 that case. Therefore, we override the DT_RELSZ entry
15075 here to make it not include the JMPREL relocs. Since
15076 the linker script arranges for .rel(a).plt to follow all
15077 other relocation sections, we don't have to worry
15078 about changing the DT_REL entry. */
15084 }
15085 /* Fall through. */
15089 /* In the BPABI, the DT_REL tag must point at the file
15090 offset, not the VMA, of the first relocation
15091 section. So, we use code similar to that in
15092 elflink.c, but do not check for SHF_ALLOC on the
15093 relcoation section, since relocations sections are
15094 never allocated under the BPABI. The comments above
15095 about Unixware notwithstanding, we include all of the
15096 relocations here. */
15098 {
15104 {
15105 Elf_Internal_Shdr *hdr
15108 {
15115 }
15116 }
15118 }
15135 /* Set the bottom bit of DT_INIT/FINI if the
15136 corresponding function is Thumb. */
15142 get_sym:
15143 /* If it wasn't set by elf_bfd_final_link
15144 then there is nothing to adjust. */
15146 {
15152 {
15155 }
15156 }
15158 }
15159 }
15161 /* Fill in the first entry in the procedure linkage table. */
15163 {
15167 /* Calculate the addresses of the GOT and PLT. */
15172 {
15173 /* The VxWorks GOT is relocated by the dynamic linker.
15174 Therefore, we must emit relocations rather than simply
15175 computing the values now. */
15176 Elf_Internal_Rela rel;
15187 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
15193 }
15198 {
15210 }
15211 else
15212 {
15225 #ifdef FOUR_WORD_PLT
15226 /* The displacement value goes in the otherwise-unused
15227 last word of the second entry. */
15229 #else
15231 #endif
15232 }
15233 }
15235 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15236 really seem like the right value. */
15241 {
15242 bfd_vma got_address
15246 bfd_vma plt_address
15262 }
15265 {
15269 #ifdef FOUR_WORD_PLT
15272 #endif
15273 }
15278 {
15279 /* Correct the .rel(a).plt.unloaded relocations. They will have
15280 incorrect symbol indexes. */
15289 {
15290 Elf_Internal_Rela rel;
15301 }
15302 }
15303 }
15306 /* NaCl uses a special first entry in .iplt too. */
15309 /* Fill in the first three entries in the global offset table. */
15311 {
15313 {
15316 else
15322 }
15325 }
15328 }
15330 static void
15331 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
15332 {
15340 else
15345 {
15349 }
15353 {
15357 else
15359 }
15360 }
15362 static enum elf_reloc_type_class
15366 {
15368 {
15377 }
15378 }
15380 static void
15382 {
15384 }
15386 /* Return TRUE if this is an unwinding table entry. */
15388 static bfd_boolean
15390 {
15393 }
15396 /* Set the type and flags for an ARM section. We do this by
15397 the section name, which is a hack, but ought to work. */
15399 static bfd_boolean
15401 {
15407 {
15410 }
15412 }
15414 /* Handle an ARM specific section when reading an object file. This is
15415 called when bfd_section_from_shdr finds a section with an unknown
15416 type. */
15418 static bfd_boolean
15423 {
15424 /* There ought to be a place to keep ELF backend specific flags, but
15425 at the moment there isn't one. We just keep track of the
15426 sections by their name, instead. Fortunately, the ABI gives
15427 names for all the ARM specific sections, so we will probably get
15428 away with this. */
15430 {
15438 }
15444 }
15448 {
15451 else
15453 }
15456 {
15465 enum map_symbol_type
15466 {
15467 ARM_MAP_ARM,
15468 ARM_MAP_THUMB,
15469 ARM_MAP_DATA
15470 };
15473 /* Output a single mapping symbol. */
15475 static bfd_boolean
15478 bfd_vma offset)
15479 {
15481 Elf_Internal_Sym sym;
15493 }
15495 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15496 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
15498 static bfd_boolean
15500 bfd_boolean is_iplt_entry_p,
15503 {
15515 {
15518 }
15519 else
15520 {
15523 }
15529 {
15534 }
15536 {
15545 }
15547 {
15550 }
15552 {
15555 }
15556 else
15557 {
15558 bfd_boolean thumb_stub_p;
15562 {
15565 }
15566 #ifdef FOUR_WORD_PLT
15571 #else
15572 /* A three-word PLT with no Thumb thunk contains only Arm code,
15573 so only need to output a mapping symbol for the first PLT entry and
15574 entries with thumb thunks. */
15576 {
15579 }
15580 #endif
15581 }
15584 }
15586 /* Output mapping symbols for PLT entries associated with H. */
15588 static bfd_boolean
15590 {
15598 /* When warning symbols are created, they **replace** the "real"
15599 entry in the hash table, thus we never get to see the real
15600 symbol in a hash traversal. So look at it now. */
15606 }
15608 /* Output a single local symbol for a generated stub. */
15610 static bfd_boolean
15613 {
15614 Elf_Internal_Sym sym;
15625 }
15627 static bfd_boolean
15630 {
15633 bfd_vma addr;
15642 /* Massage our args to the form they really have. */
15648 /* Ensure this stub is attached to the current section being
15649 processed. */
15658 {
15672 }
15677 {
15679 {
15696 }
15699 {
15703 }
15706 {
15723 }
15724 }
15727 }
15729 /* Output mapping symbols for linker generated sections,
15730 and for those data-only sections that do not have a
15731 $d. */
15733 static bfd_boolean
15738 Elf_Internal_Sym *,
15739 asection *,
15741 {
15742 output_arch_syminfo osi;
15744 bfd_vma offset;
15745 bfd_size_type size;
15758 /* Add a $d mapping symbol to data-only sections that
15759 don't have any mapping symbol. This may result in (harmless) redundant
15760 mapping symbols. */
15764 {
15769 {
15774 == SEC_HAS_CONTENTS
15779 {
15784 }
15785 }
15786 }
15788 /* ARM->Thumb glue. */
15790 {
15792 ARM2THUMB_GLUE_SECTION_NAME);
15801 else
15805 {
15808 }
15809 }
15811 /* Thumb->ARM glue. */
15813 {
15815 THUMB2ARM_GLUE_SECTION_NAME);
15822 {
15825 }
15826 }
15828 /* ARMv4 BX veneers. */
15830 {
15832 ARM_BX_GLUE_SECTION_NAME);
15838 }
15840 /* Long calls stubs. */
15842 {
15848 {
15849 /* Ignore non-stub sections. */
15859 }
15860 }
15862 /* Finally, output mapping symbols for the PLT. */
15864 {
15869 /* Output mapping symbols for the plt header. SymbianOS does not have a
15870 plt header. */
15872 {
15873 /* VxWorks shared libraries have no PLT header. */
15875 {
15880 }
15881 }
15883 {
15886 }
15888 {
15895 }
15897 {
15900 #ifndef FOUR_WORD_PLT
15903 #endif
15904 }
15905 }
15907 {
15908 /* NaCl uses a special first entry in .iplt too. */
15914 }
15917 {
15922 {
15928 {
15936 }
15937 }
15938 }
15940 {
15941 /* Mapping symbols for the lazy tls trampoline. */
15948 }
15950 {
15951 /* Mapping symbols for the tls trampoline. */
15954 #ifdef FOUR_WORD_PLT
15958 #endif
15959 }
15962 }
15964 /* Allocate target specific section data. */
15966 static bfd_boolean
15968 {
15970 {
15978 }
15981 }
15984 /* Used to order a list of mapping symbols by address. */
15986 static int
15988 {
15997 /* Ensure results do not depend on the host qsort for objects with
15998 multiple mapping symbols at the same address by sorting on type
15999 after vma. */
16003 else
16005 }
16007 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16009 static unsigned long
16011 {
16013 }
16015 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16016 relocations. */
16018 static void
16020 {
16024 /* High bit of first word is supposed to be zero. */
16028 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16029 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16035 }
16037 /* Data for make_branch_to_a8_stub(). */
16039 struct a8_branch_to_stub_data
16040 {
16043 };
16046 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
16047 places for a particular section. */
16049 static bfd_boolean
16052 {
16058 bfd_signed_vma branch_offset;
16087 /* We attempt to avoid this condition by setting stubs_always_after_branch
16088 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16089 This check is just to be on the safe side... */
16091 {
16095 }
16098 {
16109 {
16114 jump24:
16116 {
16117 /* There's not much we can do apart from complain if this
16118 happens. */
16122 }
16124 /* i1 = not(j1 eor s), so:
16125 not i1 = j1 eor s
16126 j1 = (not i1) eor s. */
16138 }
16144 }
16150 }
16152 /* Beginning of stm32l4xx work-around. */
16154 /* Functions encoding instructions necessary for the emission of the
16155 fix-stm32l4xx-629360.
16156 Encoding is extracted from the
16157 ARM (C) Architecture Reference Manual
16158 ARMv7-A and ARMv7-R edition
16159 ARM DDI 0406C.b (ID072512). */
16163 {
16164 /* A8.8.18 B (A8-334)
16165 B target_address (Encoding T4). */
16166 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16167 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16168 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16185 }
16189 {
16190 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16191 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16198 }
16202 {
16203 /* A8.8.60 LDMDB/LDMEA (A8-402)
16204 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16211 }
16215 {
16216 /* A8.8.103 MOV (register) (A8-486)
16217 MOV Rd, Rm (Encoding T1). */
16224 }
16228 {
16229 /* A8.8.221 SUB (immediate) (A8-708)
16230 SUB Rd, Rn, #value (Encoding T3). */
16240 }
16245 {
16246 /* A8.8.332 VLDM (A8-922)
16247 VLMD{MODE} Rn{!}, {list} (Encoding T2). */
16256 }
16260 {
16261 /* A8.8.332 VLDM (A8-922)
16262 VLMD{MODE} Rn!, {} (Encoding T2). */
16270 }
16274 {
16275 /* A8.8.247 UDF (A8-758)
16276 Undefined (Encoding T2). */
16282 }
16286 {
16287 /* A8.8.247 UDF (A8-758)
16288 Undefined (Encoding T1). */
16293 }
16295 /* Functions writing an instruction in memory, returning the next
16296 memory position to write to. */
16301 {
16304 }
16309 {
16312 }
16314 /* Function filling up a region in memory with T1 and T2 UDFs taking
16315 care of alignment. */
16323 {
16326 /* Fill the remaining of the stub with deterministic contents : UDF
16327 instructions.
16328 Check if realignment is needed on modulo 4 frontier using T1, to
16329 further use T2. */
16333 current_stub_contents =
16338 current_stub_contents =
16343 }
16345 /* Functions writing the stream of instructions equivalent to the
16346 derived sequence for ldmia, ldmdb, vldm respectively. */
16348 static void
16354 {
16367 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16368 smaller than 8 registers load sequences that do not cause the
16369 hardware issue. */
16371 {
16372 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16373 current_stub_contents =
16375 initial_insn);
16377 /* B initial_insn_addr+4. */
16379 current_stub_contents =
16381 create_instruction_branch_absolute
16385 /* Fill the remaining of the stub with deterministic contents. */
16386 current_stub_contents =
16389 base_stub_contents +
16390 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16393 }
16395 /* - reg_list[13] == 0. */
16398 /* - reg_list[14] & reg_list[15] != 1. */
16401 /* - if (wback==1) reg_list[rn] == 0. */
16404 /* - nb_registers > 8. */
16407 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16409 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16410 - One with the 7 lowest registers (register mask 0x007F)
16411 This LDM will finally contain between 2 and 7 registers
16412 - One with the 7 highest registers (register mask 0xDF80)
16413 This ldm will finally contain between 2 and 7 registers. */
16417 /* A spare register may be needed during this veneer to temporarily
16418 handle the base register. This register will be restored with the
16419 last LDM operation.
16420 The usable register may be any general purpose register (that
16421 excludes PC, SP, LR : register mask is 0x1FFF). */
16424 /* Generate the stub function. */
16426 {
16427 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16428 current_stub_contents =
16430 create_instruction_ldmia
16433 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16434 current_stub_contents =
16436 create_instruction_ldmia
16439 {
16440 /* B initial_insn_addr+4. */
16441 current_stub_contents =
16443 create_instruction_branch_absolute
16445 }
16446 }
16448 {
16451 /* If Rn is not part of the high-register-list, move it there. */
16453 {
16454 /* Choose a Ri in the high-register-list that will be restored. */
16457 /* MOV Ri, Rn. */
16458 current_stub_contents =
16461 }
16463 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16464 current_stub_contents =
16466 create_instruction_ldmia
16469 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16470 current_stub_contents =
16472 create_instruction_ldmia
16476 {
16477 /* B initial_insn_addr+4. */
16478 current_stub_contents =
16480 create_instruction_branch_absolute
16482 }
16483 }
16485 /* Fill the remaining of the stub with deterministic contents. */
16486 current_stub_contents =
16489 base_stub_contents +
16490 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16491 }
16493 static void
16499 {
16512 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16513 smaller than 8 registers load sequences that do not cause the
16514 hardware issue. */
16516 {
16517 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16518 current_stub_contents =
16520 initial_insn);
16522 /* B initial_insn_addr+4. */
16523 current_stub_contents =
16525 create_instruction_branch_absolute
16528 /* Fill the remaining of the stub with deterministic contents. */
16529 current_stub_contents =
16532 base_stub_contents +
16533 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16536 }
16538 /* - reg_list[13] == 0. */
16541 /* - reg_list[14] & reg_list[15] != 1. */
16544 /* - if (wback==1) reg_list[rn] == 0. */
16547 /* - nb_registers > 8. */
16550 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16552 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16553 - One with the 7 lowest registers (register mask 0x007F)
16554 This LDM will finally contain between 2 and 7 registers
16555 - One with the 7 highest registers (register mask 0xDF80)
16556 This ldm will finally contain between 2 and 7 registers. */
16560 /* A spare register may be needed during this veneer to temporarily
16561 handle the base register. This register will be restored with
16562 the last LDM operation.
16563 The usable register may be any general purpose register (that excludes
16564 PC, SP, LR : register mask is 0x1FFF). */
16567 /* Generate the stub function. */
16569 {
16570 /* Choose a Ri in the low-register-list that will be restored. */
16573 /* MOV Ri, Rn. */
16574 current_stub_contents =
16578 /* LDMDB Ri!, {R-high-register-list}. */
16579 current_stub_contents =
16581 create_instruction_ldmdb
16584 /* LDMDB Ri, {R-low-register-list}. */
16585 current_stub_contents =
16587 create_instruction_ldmdb
16590 /* B initial_insn_addr+4. */
16591 current_stub_contents =
16593 create_instruction_branch_absolute
16595 }
16597 {
16598 /* LDMDB Rn!, {R-high-register-list}. */
16599 current_stub_contents =
16601 create_instruction_ldmdb
16604 /* LDMDB Rn!, {R-low-register-list}. */
16605 current_stub_contents =
16607 create_instruction_ldmdb
16610 /* B initial_insn_addr+4. */
16611 current_stub_contents =
16613 create_instruction_branch_absolute
16615 }
16617 {
16618 /* Choose a Ri in the high-register-list that will be restored. */
16621 /* SUB Ri, Rn, #(4*nb_registers). */
16622 current_stub_contents =
16626 /* LDMIA Ri!, {R-low-register-list}. */
16627 current_stub_contents =
16629 create_instruction_ldmia
16632 /* LDMIA Ri, {R-high-register-list}. */
16633 current_stub_contents =
16635 create_instruction_ldmia
16637 }
16639 {
16640 /* Choose a Ri in the high-register-list that will be restored. */
16643 /* SUB Rn, Rn, #(4*nb_registers) */
16644 current_stub_contents =
16648 /* MOV Ri, Rn. */
16649 current_stub_contents =
16653 /* LDMIA Ri!, {R-low-register-list}. */
16654 current_stub_contents =
16656 create_instruction_ldmia
16659 /* LDMIA Ri, {R-high-register-list}. */
16660 current_stub_contents =
16662 create_instruction_ldmia
16664 }
16666 {
16669 {
16670 /* Choose a Ri in the low-register-list that will be restored. */
16673 /* MOV Ri, Rn. */
16674 current_stub_contents =
16677 }
16679 /* LDMDB Ri!, {R-high-register-list}. */
16680 current_stub_contents =
16682 create_instruction_ldmdb
16685 /* LDMDB Ri, {R-low-register-list}. */
16686 current_stub_contents =
16688 create_instruction_ldmdb
16691 /* B initial_insn_addr+4. */
16692 current_stub_contents =
16694 create_instruction_branch_absolute
16696 }
16698 {
16701 {
16702 /* Choose a Ri in the high-register-list that will be restored. */
16704 }
16706 /* SUB Ri, Rn, #(4*nb_registers). */
16707 current_stub_contents =
16711 /* LDMIA Ri!, {R-low-register-list}. */
16712 current_stub_contents =
16714 create_instruction_ldmia
16717 /* LDMIA Ri, {R-high-register-list}. */
16718 current_stub_contents =
16720 create_instruction_ldmia
16722 }
16724 {
16725 /* The assembler should not have accepted to encode this. */
16728 }
16730 /* Fill the remaining of the stub with deterministic contents. */
16731 current_stub_contents =
16734 base_stub_contents +
16735 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16737 }
16739 static void
16745 {
16751 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16752 smaller than 8 registers load sequences that do not cause the
16753 hardware issue. */
16755 {
16756 /* Untouched instruction. */
16757 current_stub_contents =
16759 initial_insn);
16761 /* B initial_insn_addr+4. */
16762 current_stub_contents =
16764 create_instruction_branch_absolute
16766 }
16767 else
16768 {
16776 /* d = UInt (Vd:D);. */
16780 /* Compute the number of 8-register chunks needed to split. */
16784 /* The test coverage has been done assuming the following
16785 hypothesis that exactly one of the previous is_ predicates is
16786 true. */
16790 /* We treat the cutting of the register in one pass for all
16791 cases, then we emit the adjustments:
16793 vldm rx, {...}
16794 -> vldm rx!, {8_words_or_less} for each needed 8_word
16795 -> sub rx, rx, #size (list)
16797 vldm rx!, {...}
16798 -> vldm rx!, {8_words_or_less} for each needed 8_word
16799 This also handles vpop instruction (when rx is sp)
16801 vldmd rx!, {...}
16802 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
16804 {
16806 {
16807 current_stub_contents =
16809 create_instruction_vldmia
16815 }
16817 {
16818 current_stub_contents =
16820 create_instruction_vldmdb
16825 }
16826 }
16828 /* Only this case requires the base register compensation
16829 subtract. */
16831 {
16832 current_stub_contents =
16834 create_instruction_sub
16836 }
16838 /* B initial_insn_addr+4. */
16839 current_stub_contents =
16841 create_instruction_branch_absolute
16843 }
16845 /* Fill the remaining of the stub with deterministic contents. */
16846 current_stub_contents =
16849 base_stub_contents +
16850 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
16851 }
16853 static void
16859 {
16863 stub_contents);
16867 stub_contents);
16871 stub_contents);
16872 }
16874 /* End of stm32l4xx work-around. */
16877 /* Do code byteswapping. Return FALSE afterwards so that the section is
16878 written out as normal. */
16880 static bfd_boolean
16885 {
16892 bfd_vma ptr;
16893 bfd_vma end;
16895 bfd_byte tmp;
16901 /* If this section has not been allocated an _arm_elf_section_data
16902 structure then we cannot record anything. */
16912 {
16917 {
16921 {
16923 {
16924 bfd_vma branch_to_veneer;
16925 /* Original condition code of instruction, plus bit mask for
16926 ARM B instruction. */
16930 /* The instruction is before the label. */
16933 /* Above offset included in -4 below. */
16947 }
16951 {
16952 bfd_vma branch_from_veneer;
16955 /* Take size of veneer into account. */
16964 /* Original instruction. */
16971 /* Branch back to insn after original insn. */
16977 }
16982 }
16983 }
16984 }
16987 {
16991 {
16995 {
16997 {
16999 bfd_vma branch_to_veneer =
17004 {
17005 bfd_vma out_of_range =
17013 "Jump out of range by %ld bytes. "
17015 output_bfd,
17017 out_of_range);
17019 }
17021 insn = create_instruction_branch_absolute
17024 /* The instruction is before the label. */
17029 }
17033 {
17039 veneer_r = veneer
17044 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17045 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17046 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17049 {
17053 }
17055 /* Original instruction. */
17058 stm32l4xx_create_replacing_stub
17060 }
17065 }
17066 }
17067 }
17070 {
17071 arm_unwind_table_edit *edit_node
17073 /* Now, sec->size is the size of the section we will write. The original
17074 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
17075 markers) was sec->rawsize. (This isn't the case if we perform no
17076 edits, then rawsize will be zero and we should use size). */
17083 {
17085 {
17089 {
17092 out_index++;
17093 in_index++;
17094 }
17098 {
17100 {
17102 in_index++;
17107 {
17115 /* Note: this is meant to be equivalent to an
17116 R_ARM_PREL31 relocation. These synthetic
17117 EXIDX_CANTUNWIND markers are not relocated by the
17118 usual BFD method. */
17122 /* First address we can't unwind. */
17126 /* Code for EXIDX_CANTUNWIND. */
17130 out_index++;
17132 }
17134 }
17137 }
17138 }
17139 else
17140 {
17141 /* No more edits, copy remaining entries verbatim. */
17144 out_index++;
17145 in_index++;
17146 }
17147 }
17151 edited_contents,
17155 }
17157 /* Fix code to point to Cortex-A8 erratum stubs. */
17159 {
17167 }
17173 {
17178 {
17181 else
17185 {
17187 /* Byte swap code words. */
17189 {
17197 }
17201 /* Byte swap code halfwords. */
17203 {
17208 }
17212 /* Leave data alone. */
17214 }
17216 }
17217 }
17225 }
17227 /* Mangle thumb function symbols as we read them in. */
17229 static bfd_boolean
17234 {
17238 /* New EABI objects mark thumb function symbols by setting the low bit of
17239 the address. */
17242 {
17244 {
17247 }
17248 else
17250 }
17252 {
17255 }
17258 else
17262 }
17265 /* Mangle thumb function symbols as we write them out. */
17267 static void
17272 {
17273 Elf_Internal_Sym newsym;
17275 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17276 of the address set, as per the new EABI. We do this unconditionally
17277 because objcopy does not set the elf header flags until after
17278 it writes out the symbol table. */
17280 {
17285 {
17286 /* Do this only for defined symbols. At link type, the static
17287 linker will simulate the work of dynamic linker of resolving
17288 symbols and will carry over the thumbness of found symbols to
17289 the output symbol table. It's not clear how it happens, but
17290 the thumbness of undefined symbols can well be different at
17291 runtime, and writing '1' for them will be confusing for users
17292 and possibly for dynamic linker itself.
17293 */
17295 }
17298 }
17300 }
17302 /* Add the PT_ARM_EXIDX program header. */
17304 static bfd_boolean
17307 {
17313 {
17314 /* If there is already a PT_ARM_EXIDX header, then we do not
17315 want to add another one. This situation arises when running
17316 "strip"; the input binary already has the header. */
17321 {
17332 }
17333 }
17336 }
17338 /* We may add a PT_ARM_EXIDX program header. */
17340 static int
17343 {
17349 else
17351 }
17353 /* Hook called by the linker routine which adds symbols from an object
17354 file. */
17356 static bfd_boolean
17360 {
17376 }
17378 /* We use this to override swap_symbol_in and swap_symbol_out. */
17380 {
17393 bfd_elf32_write_out_phdrs,
17394 bfd_elf32_write_shdrs_and_ehdr,
17395 bfd_elf32_checksum_contents,
17396 bfd_elf32_write_relocs,
17397 elf32_arm_swap_symbol_in,
17398 elf32_arm_swap_symbol_out,
17399 bfd_elf32_slurp_reloc_table,
17400 bfd_elf32_slurp_symbol_table,
17401 bfd_elf32_swap_dyn_in,
17402 bfd_elf32_swap_dyn_out,
17403 bfd_elf32_swap_reloc_in,
17404 bfd_elf32_swap_reloc_out,
17405 bfd_elf32_swap_reloca_in,
17406 bfd_elf32_swap_reloca_out
17407 };
17409 static bfd_vma
17411 {
17412 /* V7 BE8 code is always little endian. */
17417 }
17419 static bfd_vma
17421 {
17422 /* V7 BE8 code is always little endian. */
17427 }
17429 /* Return size of plt0 entry starting at ADDR
17430 or (bfd_vma) -1 if size can not be determined. */
17432 static bfd_vma
17434 {
17435 bfd_vma first_word;
17436 bfd_vma plt0_size;
17444 else
17445 /* We don't yet handle this PLT format. */
17449 }
17451 /* Return size of plt entry starting at offset OFFSET
17452 of plt section located at address START
17453 or (bfd_vma) -1 if size can not be determined. */
17455 static bfd_vma
17457 {
17458 bfd_vma first_insn;
17462 /* PLT entry size if fixed on Thumb-only platforms. */
17466 /* Respect Thumb stub if necessary. */
17468 {
17470 }
17472 /* Strip immediate from first add. */
17475 #ifdef FOUR_WORD_PLT
17478 #else
17483 #endif
17484 else
17485 /* We don't yet handle this PLT format. */
17489 }
17491 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17493 static long
17500 {
17509 bfd_vma offset;
17538 {
17542 }
17548 {
17552 }
17566 {
17574 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17575 we are defining a symbol, ensure one of them is set. */
17587 {
17594 ;
17598 }
17603 }
17606 }
17608 #define ELF_ARCH bfd_arch_arm
17609 #define ELF_TARGET_ID ARM_ELF_DATA
17610 #define ELF_MACHINE_CODE EM_ARM
17611 #ifdef __QNXTARGET__
17612 #define ELF_MAXPAGESIZE 0x1000
17613 #else
17614 #define ELF_MAXPAGESIZE 0x10000
17615 #endif
17616 #define ELF_MINPAGESIZE 0x1000
17617 #define ELF_COMMONPAGESIZE 0x1000
17619 #define bfd_elf32_mkobject elf32_arm_mkobject
17621 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
17622 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
17623 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
17624 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
17625 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
17626 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
17627 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
17628 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
17629 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
17630 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
17631 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
17632 #define bfd_elf32_bfd_final_link elf32_arm_final_link
17633 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
17635 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
17636 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
17637 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
17638 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
17639 #define elf_backend_check_relocs elf32_arm_check_relocs
17640 #define elf_backend_relocate_section elf32_arm_relocate_section
17641 #define elf_backend_write_section elf32_arm_write_section
17642 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
17643 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
17644 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
17645 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
17646 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
17647 #define elf_backend_always_size_sections elf32_arm_always_size_sections
17648 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
17649 #define elf_backend_post_process_headers elf32_arm_post_process_headers
17650 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
17651 #define elf_backend_object_p elf32_arm_object_p
17652 #define elf_backend_fake_sections elf32_arm_fake_sections
17653 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
17654 #define elf_backend_final_write_processing elf32_arm_final_write_processing
17655 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
17656 #define elf_backend_size_info elf32_arm_size_info
17657 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
17658 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
17659 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
17660 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
17661 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
17663 #define elf_backend_can_refcount 1
17664 #define elf_backend_can_gc_sections 1
17665 #define elf_backend_plt_readonly 1
17666 #define elf_backend_want_got_plt 1
17667 #define elf_backend_want_plt_sym 0
17668 #define elf_backend_may_use_rel_p 1
17669 #define elf_backend_may_use_rela_p 0
17670 #define elf_backend_default_use_rela_p 0
17672 #define elf_backend_got_header_size 12
17673 #define elf_backend_extern_protected_data 1
17675 #undef elf_backend_obj_attrs_vendor
17677 #undef elf_backend_obj_attrs_section
17679 #undef elf_backend_obj_attrs_arg_type
17680 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
17681 #undef elf_backend_obj_attrs_section_type
17682 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
17683 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
17684 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
17688 /* Native Client targets. */
17690 #undef TARGET_LITTLE_SYM
17691 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
17692 #undef TARGET_LITTLE_NAME
17694 #undef TARGET_BIG_SYM
17695 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
17696 #undef TARGET_BIG_NAME
17699 /* Like elf32_arm_link_hash_table_create -- but overrides
17700 appropriately for NaCl. */
17704 {
17709 {
17717 }
17719 }
17721 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
17722 really need to use elf32_arm_modify_segment_map. But we do it
17723 anyway just to reduce gratuitous differences with the stock ARM backend. */
17725 static bfd_boolean
17727 {
17730 }
17732 static void
17734 {
17737 }
17739 static bfd_vma
17742 {
17746 }
17748 #undef elf32_bed
17749 #define elf32_bed elf32_arm_nacl_bed
17750 #undef bfd_elf32_bfd_link_hash_table_create
17751 #define bfd_elf32_bfd_link_hash_table_create \
17752 elf32_arm_nacl_link_hash_table_create
17753 #undef elf_backend_plt_alignment
17754 #define elf_backend_plt_alignment 4
17755 #undef elf_backend_modify_segment_map
17756 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
17757 #undef elf_backend_modify_program_headers
17758 #define elf_backend_modify_program_headers nacl_modify_program_headers
17759 #undef elf_backend_final_write_processing
17760 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
17761 #undef bfd_elf32_get_synthetic_symtab
17762 #undef elf_backend_plt_sym_val
17763 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
17765 #undef ELF_MINPAGESIZE
17766 #undef ELF_COMMONPAGESIZE
17771 /* Reset to defaults. */
17772 #undef elf_backend_plt_alignment
17773 #undef elf_backend_modify_segment_map
17774 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
17775 #undef elf_backend_modify_program_headers
17776 #undef elf_backend_final_write_processing
17777 #define elf_backend_final_write_processing elf32_arm_final_write_processing
17778 #undef ELF_MINPAGESIZE
17779 #define ELF_MINPAGESIZE 0x1000
17780 #undef ELF_COMMONPAGESIZE
17781 #define ELF_COMMONPAGESIZE 0x1000
17784 /* VxWorks Targets. */
17786 #undef TARGET_LITTLE_SYM
17787 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
17788 #undef TARGET_LITTLE_NAME
17790 #undef TARGET_BIG_SYM
17791 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
17792 #undef TARGET_BIG_NAME
17795 /* Like elf32_arm_link_hash_table_create -- but overrides
17796 appropriately for VxWorks. */
17800 {
17805 {
17810 }
17812 }
17814 static void
17816 {
17819 }
17821 #undef elf32_bed
17822 #define elf32_bed elf32_arm_vxworks_bed
17824 #undef bfd_elf32_bfd_link_hash_table_create
17825 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
17826 #undef elf_backend_final_write_processing
17827 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
17828 #undef elf_backend_emit_relocs
17829 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
17831 #undef elf_backend_may_use_rel_p
17832 #define elf_backend_may_use_rel_p 0
17833 #undef elf_backend_may_use_rela_p
17834 #define elf_backend_may_use_rela_p 1
17835 #undef elf_backend_default_use_rela_p
17836 #define elf_backend_default_use_rela_p 1
17837 #undef elf_backend_want_plt_sym
17838 #define elf_backend_want_plt_sym 1
17839 #undef ELF_MAXPAGESIZE
17840 #define ELF_MAXPAGESIZE 0x1000
17845 /* Merge backend specific data from an object file to the output
17846 object file when linking. */
17848 static bfd_boolean
17850 {
17851 flagword out_flags;
17852 flagword in_flags;
17856 /* Check if we have the same endianness. */
17866 /* The input BFD must have had its flags initialised. */
17867 /* The following seems bogus to me -- The flags are initialized in
17868 the assembler but I don't think an elf_flags_init field is
17869 written into the object. */
17870 /* BFD_ASSERT (elf_flags_init (ibfd)); */
17875 /* In theory there is no reason why we couldn't handle this. However
17876 in practice it isn't even close to working and there is no real
17877 reason to want it. */
17881 {
17883 ibfd);
17885 }
17888 {
17889 /* If the input is the default architecture and had the default
17890 flags then do not bother setting the flags for the output
17891 architecture, instead allow future merges to do this. If no
17892 future merges ever set these flags then they will retain their
17893 uninitialised values, which surprise surprise, correspond
17894 to the default values. */
17907 }
17909 /* Determine what should happen if the input ARM architecture
17910 does not match the output ARM architecture. */
17914 /* Identical flags must be compatible. */
17918 /* Check to see if the input BFD actually contains any sections. If
17919 not, its flags may not have been initialised either, but it
17920 cannot actually cause any incompatiblity. Do not short-circuit
17921 dynamic objects; their section list may be emptied by
17922 elf_link_add_object_symbols.
17924 Also check to see if there are no code sections in the input.
17925 In this case there is no need to check for code specific flags.
17926 XXX - do we need to worry about floating-point format compatability
17927 in data sections ? */
17929 {
17934 {
17935 /* Ignore synthetic glue sections. */
17938 {
17946 }
17947 }
17951 }
17953 /* Complain about various flag mismatches. */
17956 {
17957 _bfd_error_handler
17963 }
17965 /* Not sure what needs to be checked for EABI versions >= 1. */
17966 /* VxWorks libraries do not use these flags. */
17970 {
17972 {
17973 _bfd_error_handler
17979 }
17982 {
17984 _bfd_error_handler
17985 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
17987 else
17988 _bfd_error_handler
17989 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
17993 }
17996 {
17998 _bfd_error_handler
18001 else
18002 _bfd_error_handler
18007 }
18010 {
18012 _bfd_error_handler
18015 else
18016 _bfd_error_handler
18021 }
18023 #ifdef EF_ARM_SOFT_FLOAT
18025 {
18026 /* We can allow interworking between code that is VFP format
18027 layout, and uses either soft float or integer regs for
18028 passing floating point arguments and results. We already
18029 know that the APCS_FLOAT flags match; similarly for VFP
18030 flags. */
18033 {
18035 _bfd_error_handler
18038 else
18039 _bfd_error_handler
18044 }
18045 }
18046 #endif
18048 /* Interworking mismatch is only a warning. */
18050 {
18052 {
18053 _bfd_error_handler
18056 }
18057 else
18058 {
18059 _bfd_error_handler
18062 }
18063 }
18064 }
18067 }
18070 /* Symbian OS Targets. */
18072 #undef TARGET_LITTLE_SYM
18073 #define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
18074 #undef TARGET_LITTLE_NAME
18076 #undef TARGET_BIG_SYM
18077 #define TARGET_BIG_SYM arm_elf32_symbian_be_vec
18078 #undef TARGET_BIG_NAME
18081 /* Like elf32_arm_link_hash_table_create -- but overrides
18082 appropriately for Symbian OS. */
18086 {
18091 {
18094 /* There is no PLT header for Symbian OS. */
18096 /* The PLT entries are each one instruction and one word. */
18099 /* Symbian uses armv5t or above, so use_blx is always true. */
18102 }
18104 }
18106 static const struct bfd_elf_special_section
18107 elf32_arm_symbian_special_sections[] =
18108 {
18109 /* In a BPABI executable, the dynamic linking sections do not go in
18110 the loadable read-only segment. The post-linker may wish to
18111 refer to these sections, but they are not part of the final
18112 program image. */
18118 /* These sections do not need to be writable as the SymbianOS
18119 postlinker will arrange things so that no dynamic relocation is
18120 required. */
18125 };
18127 static void
18130 {
18131 /* BPABI objects are never loaded directly by an OS kernel; they are
18132 processed by a postlinker first, into an OS-specific format. If
18133 the D_PAGED bit is set on the file, BFD will align segments on
18134 page boundaries, so that an OS can directly map the file. With
18135 BPABI objects, that just results in wasted space. In addition,
18136 because we clear the D_PAGED bit, map_sections_to_segments will
18137 recognize that the program headers should not be mapped into any
18138 loadable segment. */
18141 }
18143 static bfd_boolean
18146 {
18150 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18151 segment. However, because the .dynamic section is not marked
18152 with SEC_LOAD, the generic ELF code will not create such a
18153 segment. */
18156 {
18162 {
18166 }
18167 }
18169 /* Also call the generic arm routine. */
18171 }
18173 /* Return address for Ith PLT stub in section PLT, for relocation REL
18174 or (bfd_vma) -1 if it should not be included. */
18176 static bfd_vma
18179 {
18181 }
18184 #undef elf32_bed
18185 #define elf32_bed elf32_arm_symbian_bed
18187 /* The dynamic sections are not allocated on SymbianOS; the postlinker
18188 will process them and then discard them. */
18189 #undef ELF_DYNAMIC_SEC_FLAGS
18190 #define ELF_DYNAMIC_SEC_FLAGS \
18191 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18193 #undef elf_backend_emit_relocs
18195 #undef bfd_elf32_bfd_link_hash_table_create
18196 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18197 #undef elf_backend_special_sections
18198 #define elf_backend_special_sections elf32_arm_symbian_special_sections
18199 #undef elf_backend_begin_write_processing
18200 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18201 #undef elf_backend_final_write_processing
18202 #define elf_backend_final_write_processing elf32_arm_final_write_processing
18204 #undef elf_backend_modify_segment_map
18205 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18207 /* There is no .got section for BPABI objects, and hence no header. */
18208 #undef elf_backend_got_header_size
18209 #define elf_backend_got_header_size 0
18211 /* Similarly, there is no .got.plt section. */
18212 #undef elf_backend_want_got_plt
18213 #define elf_backend_want_got_plt 0
18215 #undef elf_backend_plt_sym_val
18216 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18218 #undef elf_backend_may_use_rel_p
18219 #define elf_backend_may_use_rel_p 1
18220 #undef elf_backend_may_use_rela_p
18221 #define elf_backend_may_use_rela_p 0
18222 #undef elf_backend_default_use_rela_p
18223 #define elf_backend_default_use_rela_p 0
18224 #undef elf_backend_want_plt_sym
18225 #define elf_backend_want_plt_sym 0
18226 #undef ELF_MAXPAGESIZE
18227 #define ELF_MAXPAGESIZE 0x8000