| blob | 1280eaf9444ce2ceea17227cb3ad82bc6546e84b |
1 2016-12-23 Tristan Gingold <gingold@adacore.com>
3 * po/opcodes.pot: Regenerate.
5 2016-12-21 Andrew Waterman <andrew@sifive.com>
7 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
9 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
11 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
12 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
13 (print_insn_mips16): Check opcode entries for validity against
14 the ISA level and ASE set selected.
16 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
18 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
19 `insn' together, with `extend' as the high-order 16 bits.
20 (match_kind): New enum.
21 (print_insn_mips16): Rework for 32-bit instruction matching.
22 Do not dump EXTEND prefixes here.
23 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
24 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
25 "jalx" entries.
27 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
29 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
30 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
31 INSN_MACRO entries.
33 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
35 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
36 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
37 opcode).
39 2016-12-20 Andrew Waterman <andrew@sifive.com>
41 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
42 "*.aqrl".
44 2016-12-20 Andrew Waterman <andrew@sifive.com>
46 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
47 INSN_ALIAS.
49 2016-12-20 Andrew Waterman <andrew@sifive.com>
51 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
52 format.
54 2016-12-20 Andrew Waterman <andrew@sifive.com>
56 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
57 XLEN when none is provided.
59 2016-12-20 Andrew Waterman <andrew@sifive.com>
61 * riscv-opc.c: Formatting fixes.
63 2016-12-20 Alan Modra <amodra@gmail.com>
65 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
66 * Makefile.in: Regenerate.
67 * po/POTFILES.in: Regenerate.
69 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
71 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
72 Only examine ELF file structures here.
74 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
76 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
77 `bfd_mips_elf_get_abiflags' here.
79 2016-12-16 Nick Clifton <nickc@redhat.com>
81 * arm-dis.c (print_insn_thumb32): Fix compile time warning
82 computing value_in_comment.
84 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
86 * mips-dis.c (mips_convert_abiflags_ases): New function.
87 (set_default_mips_dis_options): Also infer ASE flags from ELF
88 file structures.
90 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
92 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
93 header flag interpretation code.
95 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
97 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
98 `pinfo2' with SP-relative "sd" entries.
100 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
102 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
103 compact jumps.
105 2016-12-13 Renlin Li <renlin.li@arm.com>
107 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
108 qualifier.
109 (operand_general_constraint_met_p): Remove case for CP_REG.
110 (aarch64_print_operand): Print CRn, CRm operand using imm field.
111 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
112 (QL_SYSL): Likewise.
113 (aarch64_opcode_table): Change CRn, CRm operand class and type.
114 * aarch64-opc-2.c : Regenerate.
115 * aarch64-asm-2.c : Likewise.
116 * aarch64-dis-2.c : Likewise.
118 2016-12-12 Yao Qi <yao.qi@linaro.org>
120 * rx-dis.c: Include <setjmp.h>
121 (struct private): New.
122 (rx_get_byte): Check return value of read_memory_func, and
123 call memory_error_func and OPCODES_SIGLONGJMP on error.
124 (print_insn_rx): Call OPCODES_SIGSETJMP.
126 2016-12-12 Yao Qi <yao.qi@linaro.org>
128 * rl78-dis.c: Include <setjmp.h>.
129 (struct private): New.
130 (rl78_get_byte): Check return value of read_memory_func, and
131 call memory_error_func and OPCODES_SIGLONGJMP on error.
132 (print_insn_rl78_common): Call OPCODES_SIGJMP.
134 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
136 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
138 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
140 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
141 than UINT.
143 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
145 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
146 to separate `extend' and its uninterpreted argument output.
147 Separate hexadecimal halves of undecoded extended instructions
148 output.
150 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
152 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
153 indentation space across.
155 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
157 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
158 adjustment for PC-relative operations following MIPS16e compact
159 jumps or undefined RR/J(AL)R(C) encodings.
161 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
163 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
164 variable to `reglane_index'.
166 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
168 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
170 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
172 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
174 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
176 * mips16-opc.c (mips16_opcodes): Update comment naming structure
177 members.
179 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
181 * mips-dis.c (print_mips_disassembler_options): Reformat output.
183 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
185 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
186 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
188 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
190 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
192 2016-12-01 Nick Clifton <nickc@redhat.com>
194 PR binutils/20893
195 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
196 opcode designator.
198 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
200 * arc-opc.c (insert_ra_chk): New function.
201 (insert_rb_chk): Likewise.
202 (insert_rad): Update text error message.
203 (insert_rcd): Likewise.
204 (insert_rhv2): Likewise.
205 (insert_r0): Likewise.
206 (insert_r1): Likewise.
207 (insert_r2): Likewise.
208 (insert_r3): Likewise.
209 (insert_sp): Likewise.
210 (insert_gp): Likewise.
211 (insert_pcl): Likewise.
212 (insert_blink): Likewise.
213 (insert_ilink1): Likewise.
214 (insert_ilink2): Likewise.
215 (insert_ras): Likewise.
216 (insert_rbs): Likewise.
217 (insert_rcs): Likewise.
218 (insert_simm3s): Likewise.
219 (insert_rrange): Likewise.
220 (insert_fpel): Likewise.
221 (insert_blinkel): Likewise.
222 (insert_pcel): Likewise.
223 (insert_nps_3bit_dst): Likewise.
224 (insert_nps_3bit_dst_short): Likewise.
225 (insert_nps_3bit_src2_short): Likewise.
226 (insert_nps_bitop_size_2b): Likewise.
227 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
228 (RA_CHK): Define.
229 (RB): Adjust.
230 (RB_CHK): Define.
231 (RC): Adjust.
232 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
233 * arc-tbl.h (div, divu): All instructions are DIVREM class.
234 Change first insn argument to check for LP_COUNT usage.
235 (rem): Likewise.
236 (ld, ldd): All instructions are LOAD class. Change first insn
237 argument to check for LP_COUNT usage.
238 (st, std): All instructions are STORE class.
239 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
240 Change first insn argument to check for LP_COUNT usage.
241 (mov): All instructions are MOVE class. Change first insn
242 argument to check for LP_COUNT usage.
244 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
246 * arc-dis.c (is_compatible_p): Remove function.
247 (skip_this_opcode): Don't add any decoding class to decode list.
248 Remove warning.
249 (find_format_from_table): Go through all opcodes, and warn if we
250 use a guessed mnemonic.
252 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
253 Amit Pawar <amit.pawar@amd.com>
255 PR binutils/20637
256 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
257 instructions.
259 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
261 * configure: Regenerate.
263 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
265 * sparc-opc.c (HWS_V8): Definition moved from
266 gas/config/tc-sparc.c.
267 (HWS_V9): Likewise.
268 (HWS_VA): Likewise.
269 (HWS_VB): Likewise.
270 (HWS_VC): Likewise.
271 (HWS_VD): Likewise.
272 (HWS_VE): Likewise.
273 (HWS_VV): Likewise.
274 (HWS_VM): Likewise.
275 (HWS2_VM): Likewise.
276 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
277 existing entries.
279 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
281 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
282 instructions.
284 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
286 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
287 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
288 (aarch64_opcode_table): Add fcmla and fcadd.
289 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
290 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
291 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
292 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
293 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
294 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
295 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
296 (operand_general_constraint_met_p): Rotate and index range check.
297 (aarch64_print_operand): Handle rotate operand.
298 * aarch64-asm-2.c: Regenerate.
299 * aarch64-dis-2.c: Likewise.
300 * aarch64-opc-2.c: Likewise.
302 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
304 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
305 * aarch64-asm-2.c: Regenerate.
306 * aarch64-dis-2.c: Regenerate.
307 * aarch64-opc-2.c: Regenerate.
309 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
311 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
312 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
313 * aarch64-asm-2.c: Regenerate.
314 * aarch64-dis-2.c: Regenerate.
315 * aarch64-opc-2.c: Regenerate.
317 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
319 * aarch64-tbl.h (QL_X1NIL): New.
320 (arch64_opcode_table): Add ldraa, ldrab.
321 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
322 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
323 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
324 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
325 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
326 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
327 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
328 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
329 (aarch64_print_operand): Likewise.
330 * aarch64-asm-2.c: Regenerate.
331 * aarch64-dis-2.c: Regenerate.
332 * aarch64-opc-2.c: Regenerate.
334 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
336 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
337 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
338 * aarch64-asm-2.c: Regenerate.
339 * aarch64-dis-2.c: Regenerate.
340 * aarch64-opc-2.c: Regenerate.
342 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
344 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
345 (AARCH64_OPERANDS): Add Rm_SP.
346 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
347 * aarch64-asm-2.c: Regenerate.
348 * aarch64-dis-2.c: Regenerate.
349 * aarch64-opc-2.c: Regenerate.
351 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
353 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
354 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
355 autdzb, xpaci, xpacd.
356 * aarch64-asm-2.c: Regenerate.
357 * aarch64-dis-2.c: Regenerate.
358 * aarch64-opc-2.c: Regenerate.
360 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
362 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
363 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
364 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
365 (aarch64_sys_reg_supported_p): Add feature test for new registers.
367 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
369 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
370 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
371 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
372 autibsp.
373 * aarch64-asm-2.c: Regenerate.
374 * aarch64-dis-2.c: Regenerate.
376 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
378 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
380 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
382 PR binutils/20799
383 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
384 * i386-dis.c (EdqwS): Removed.
385 (dqw_swap_mode): Likewise.
386 (intel_operand_size): Don't check dqw_swap_mode.
387 (OP_E_register): Likewise.
388 (OP_E_memory): Likewise.
389 (OP_G): Likewise.
390 (OP_EX): Likewise.
391 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
392 * i386-tbl.h: Regerated.
394 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
396 * i386-opc.tbl: Merge AVX512F vmovq.
397 * i386-tbl.h: Regerated.
399 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
401 PR binutils/20701
402 * i386-dis.c (THREE_BYTE_0F7A): Removed.
403 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
404 (three_byte_table): Remove THREE_BYTE_0F7A.
406 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
408 PR binutils/20775
409 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
410 (FGRPd9_4): Replace 1 with 2.
411 (FGRPd9_5): Replace 2 with 3.
412 (FGRPd9_6): Replace 3 with 4.
413 (FGRPd9_7): Replace 4 with 5.
414 (FGRPda_5): Replace 5 with 6.
415 (FGRPdb_4): Replace 6 with 7.
416 (FGRPde_3): Replace 7 with 8.
417 (FGRPdf_4): Replace 8 with 9.
418 (fgrps): Add an entry for Bad_Opcode.
420 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
422 * arc-opc.c (arc_flag_operands): Add F_DI14.
423 (arc_flag_classes): Add C_DI14.
424 * arc-nps400-tbl.h: Add new exc instructions.
426 2016-11-03 Graham Markall <graham.markall@embecosm.com>
428 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
429 major opcode 0xa.
430 * arc-nps-400-tbl.h: Add dcmac instruction.
431 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
432 (insert_nps_rbdouble_64): Added.
433 (extract_nps_rbdouble_64): Added.
434 (insert_nps_proto_size): Added.
435 (extract_nps_proto_size): Added.
437 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
439 * arc-dis.c (struct arc_operand_iterator): Remove all fields
440 relating to long instruction processing, add new limm field.
441 (OPCODE): Rename to...
442 (OPCODE_32BIT_INSN): ...this.
443 (OPCODE_AC): Delete.
444 (skip_this_opcode): Handle different instruction lengths, update
445 macro name.
446 (special_flag_p): Update parameter type.
447 (find_format_from_table): Update for more instruction lengths.
448 (find_format_long_instructions): Delete.
449 (find_format): Update for more instruction lengths.
450 (arc_insn_length): Likewise.
451 (extract_operand_value): Update for more instruction lengths.
452 (operand_iterator_next): Remove code relating to long
453 instructions.
454 (arc_opcode_to_insn_type): New function.
455 (print_insn_arc):Update for more instructions lengths.
456 * arc-ext.c (extInstruction_t): Change argument type.
457 * arc-ext.h (extInstruction_t): Change argument type.
458 * arc-fxi.h: Change type unsigned to unsigned long long
459 extensively throughout.
460 * arc-nps400-tbl.h: Add long instructions taken from
461 arc_long_opcodes table in arc-opc.c.
462 * arc-opc.c: Update parameter types on insert/extract handlers.
463 (arc_long_opcodes): Delete.
464 (arc_num_long_opcodes): Delete.
465 (arc_opcode_len): Update for more instruction lengths.
467 2016-11-03 Graham Markall <graham.markall@embecosm.com>
469 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
471 2016-11-03 Graham Markall <graham.markall@embecosm.com>
473 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
474 with arc_opcode_len.
475 (find_format_long_instructions): Likewise.
476 * arc-opc.c (arc_opcode_len): New function.
478 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
480 * arc-nps400-tbl.h: Fix some instruction masks.
482 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
484 * i386-dis.c (REG_82): Removed.
485 (X86_64_82_REG_0): Likewise.
486 (X86_64_82_REG_1): Likewise.
487 (X86_64_82_REG_2): Likewise.
488 (X86_64_82_REG_3): Likewise.
489 (X86_64_82_REG_4): Likewise.
490 (X86_64_82_REG_5): Likewise.
491 (X86_64_82_REG_6): Likewise.
492 (X86_64_82_REG_7): Likewise.
493 (X86_64_82): New.
494 (dis386): Use X86_64_82 instead of REG_82.
495 (reg_table): Remove REG_82.
496 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
497 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
498 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
499 X86_64_82_REG_7.
501 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
503 PR binutils/20754
504 * i386-dis.c (REG_82): New.
505 (X86_64_82_REG_0): Likewise.
506 (X86_64_82_REG_1): Likewise.
507 (X86_64_82_REG_2): Likewise.
508 (X86_64_82_REG_3): Likewise.
509 (X86_64_82_REG_4): Likewise.
510 (X86_64_82_REG_5): Likewise.
511 (X86_64_82_REG_6): Likewise.
512 (X86_64_82_REG_7): Likewise.
513 (dis386): Use REG_82.
514 (reg_table): Add REG_82.
515 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
516 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
517 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
519 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
521 * i386-dis.c (REG_82): Renamed to ...
522 (REG_83): This.
523 (dis386): Updated.
524 (reg_table): Likewise.
526 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
528 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
529 * i386-dis-evex.h (evex_table): Updated.
530 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
531 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
532 (cpu_flags): Add CpuAVX512_4VNNIW.
533 * i386-opc.h (enum): (AVX512_4VNNIW): New.
534 (i386_cpu_flags): Add cpuavx512_4vnniw.
535 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
536 * i386-init.h: Regenerate.
537 * i386-tbl.h: Ditto.
539 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
541 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
542 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
543 * i386-dis-evex.h (evex_table): Updated.
544 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
545 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
546 (cpu_flags): Add CpuAVX512_4FMAPS.
547 (opcode_modifiers): Add ImplicitQuadGroup modifier.
548 * i386-opc.h (AVX512_4FMAP): New.
549 (i386_cpu_flags): Add cpuavx512_4fmaps.
550 (ImplicitQuadGroup): New.
551 (i386_opcode_modifier): Add implicitquadgroup.
552 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
553 * i386-init.h: Regenerate.
554 * i386-tbl.h: Ditto.
556 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
557 Andrew Waterman <andrew@sifive.com>
559 Add support for RISC-V architecture.
560 * configure.ac: Add entry for bfd_riscv_arch.
561 * configure: Regenerate.
562 * disassemble.c (disassembler): Add support for riscv.
563 (disassembler_usage): Likewise.
564 * riscv-dis.c: New file.
565 * riscv-opc.c: New file.
567 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
569 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
570 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
571 (rm_table): Update the RM_0FAE_REG_7 entry.
572 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
573 (cpu_flags): Remove CpuPCOMMIT.
574 * i386-opc.h (CpuPCOMMIT): Removed.
575 (i386_cpu_flags): Remove cpupcommit.
576 * i386-opc.tbl: Remove pcommit.
577 * i386-init.h: Regenerated.
578 * i386-tbl.h: Likewise.
580 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
582 PR binutis/20705
583 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
584 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
585 32-bit mode. Don't check vex.register_specifier in 32-bit
586 mode.
587 (OP_VEX): Check for invalid mask registers.
589 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
591 PR binutis/20699
592 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
593 sizeflag.
595 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
597 PR binutis/20704
598 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
600 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
602 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
603 local variable to `index_regno'.
605 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
607 * arc-tbl.h: Removed any "inv.+" instructions from the table.
609 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
611 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
612 usage on ISA basis.
614 2016-10-11 Jiong Wang <jiong.wang@arm.com>
616 PR target/20666
617 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
619 2016-10-07 Jiong Wang <jiong.wang@arm.com>
621 PR target/20667
622 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
623 available.
625 2016-10-07 Alan Modra <amodra@gmail.com>
627 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
629 2016-10-06 Alan Modra <amodra@gmail.com>
631 * aarch64-opc.c: Spell fall through comments consistently.
632 * i386-dis.c: Likewise.
633 * aarch64-dis.c: Add missing fall through comments.
634 * aarch64-opc.c: Likewise.
635 * arc-dis.c: Likewise.
636 * arm-dis.c: Likewise.
637 * i386-dis.c: Likewise.
638 * m68k-dis.c: Likewise.
639 * mep-asm.c: Likewise.
640 * ns32k-dis.c: Likewise.
641 * sh-dis.c: Likewise.
642 * tic4x-dis.c: Likewise.
643 * tic6x-dis.c: Likewise.
644 * vax-dis.c: Likewise.
646 2016-10-06 Alan Modra <amodra@gmail.com>
648 * arc-ext.c (create_map): Add missing break.
649 * msp430-decode.opc (encode_as): Likewise.
650 * msp430-decode.c: Regenerate.
652 2016-10-06 Alan Modra <amodra@gmail.com>
654 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
655 * crx-dis.c (print_insn_crx): Likewise.
657 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
659 PR binutils/20657
660 * i386-dis.c (putop): Don't assign alt twice.
662 2016-09-29 Jiong Wang <jiong.wang@arm.com>
664 PR target/20553
665 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
667 2016-09-29 Alan Modra <amodra@gmail.com>
669 * ppc-opc.c (L): Make compulsory.
670 (LOPT): New, optional form of L.
671 (HTM_R): Define as LOPT.
672 (L0, L1): Delete.
673 (L32OPT): New, optional for 32-bit L.
674 (L2OPT): New, 2-bit L for dcbf.
675 (SVC_LEC): Update.
676 (L2): Define.
677 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
678 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
679 <dcbf>: Use L2OPT.
680 <tlbiel, tlbie>: Use LOPT.
681 <wclr, wclrall>: Use L2.
683 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
685 * Makefile.in: Regenerate.
686 * configure: Likewise.
688 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
690 * arc-ext-tbl.h (EXTINSN2OPF): Define.
691 (EXTINSN2OP): Use EXTINSN2OPF.
692 (bspeekm, bspop, modapp): New extension instructions.
693 * arc-opc.c (F_DNZ_ND): Define.
694 (F_DNZ_D): Likewise.
695 (F_SIZEB1): Changed.
696 (C_DNZ_D): Define.
697 (C_HARD): Changed.
698 * arc-tbl.h (dbnz): New instruction.
699 (prealloc): Allow it for ARC EM.
700 (xbfu): Likewise.
702 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
704 * aarch64-opc.c (print_immediate_offset_address): Print spaces
705 after commas in addresses.
706 (aarch64_print_operand): Likewise.
708 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
710 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
711 rather than "should be" or "expected to be" in error messages.
713 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
715 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
716 (print_mnemonic_name): ...here.
717 (print_comment): New function.
718 (print_aarch64_insn): Call it.
719 * aarch64-opc.c (aarch64_conds): Add SVE names.
720 (aarch64_print_operand): Print alternative condition names in
721 a comment.
723 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
725 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
726 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
727 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
728 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
729 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
730 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
731 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
732 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
733 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
734 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
735 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
736 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
737 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
738 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
739 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
740 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
741 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
742 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
743 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
744 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
745 (OP_SVE_XWU, OP_SVE_XXU): New macros.
746 (aarch64_feature_sve): New variable.
747 (SVE): New macro.
748 (_SVE_INSN): Likewise.
749 (aarch64_opcode_table): Add SVE instructions.
750 * aarch64-opc.h (extract_fields): Declare.
751 * aarch64-opc-2.c: Regenerate.
752 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
753 * aarch64-asm-2.c: Regenerate.
754 * aarch64-dis.c (extract_fields): Make global.
755 (do_misc_decoding): Handle the new SVE aarch64_ops.
756 * aarch64-dis-2.c: Regenerate.
758 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
760 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
761 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
762 aarch64_field_kinds.
763 * aarch64-opc.c (fields): Add corresponding entries.
764 * aarch64-asm.c (aarch64_get_variant): New function.
765 (aarch64_encode_variant_using_iclass): Likewise.
766 (aarch64_opcode_encode): Call it.
767 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
768 (aarch64_opcode_decode): Call it.
770 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
772 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
773 and FP register operands.
774 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
775 (FLD_SVE_Vn): New aarch64_field_kinds.
776 * aarch64-opc.c (fields): Add corresponding entries.
777 (aarch64_print_operand): Handle the new SVE core and FP register
778 operands.
779 * aarch64-opc-2.c: Regenerate.
780 * aarch64-asm-2.c: Likewise.
781 * aarch64-dis-2.c: Likewise.
783 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
785 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
786 immediate operands.
787 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
788 * aarch64-opc.c (fields): Add corresponding entry.
789 (operand_general_constraint_met_p): Handle the new SVE FP immediate
790 operands.
791 (aarch64_print_operand): Likewise.
792 * aarch64-opc-2.c: Regenerate.
793 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
794 (ins_sve_float_zero_one): New inserters.
795 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
796 (aarch64_ins_sve_float_half_two): Likewise.
797 (aarch64_ins_sve_float_zero_one): Likewise.
798 * aarch64-asm-2.c: Regenerate.
799 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
800 (ext_sve_float_zero_one): New extractors.
801 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
802 (aarch64_ext_sve_float_half_two): Likewise.
803 (aarch64_ext_sve_float_zero_one): Likewise.
804 * aarch64-dis-2.c: Regenerate.
806 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
808 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
809 integer immediate operands.
810 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
811 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
812 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
813 * aarch64-opc.c (fields): Add corresponding entries.
814 (operand_general_constraint_met_p): Handle the new SVE integer
815 immediate operands.
816 (aarch64_print_operand): Likewise.
817 (aarch64_sve_dupm_mov_immediate_p): New function.
818 * aarch64-opc-2.c: Regenerate.
819 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
820 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
821 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
822 (aarch64_ins_limm): ...here.
823 (aarch64_ins_inv_limm): New function.
824 (aarch64_ins_sve_aimm): Likewise.
825 (aarch64_ins_sve_asimm): Likewise.
826 (aarch64_ins_sve_limm_mov): Likewise.
827 (aarch64_ins_sve_shlimm): Likewise.
828 (aarch64_ins_sve_shrimm): Likewise.
829 * aarch64-asm-2.c: Regenerate.
830 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
831 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
832 * aarch64-dis.c (decode_limm): New function, split out from...
833 (aarch64_ext_limm): ...here.
834 (aarch64_ext_inv_limm): New function.
835 (decode_sve_aimm): Likewise.
836 (aarch64_ext_sve_aimm): Likewise.
837 (aarch64_ext_sve_asimm): Likewise.
838 (aarch64_ext_sve_limm_mov): Likewise.
839 (aarch64_top_bit): Likewise.
840 (aarch64_ext_sve_shlimm): Likewise.
841 (aarch64_ext_sve_shrimm): Likewise.
842 * aarch64-dis-2.c: Regenerate.
844 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
846 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
847 operands.
848 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
849 the AARCH64_MOD_MUL_VL entry.
850 (value_aligned_p): Cope with non-power-of-two alignments.
851 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
852 (print_immediate_offset_address): Likewise.
853 (aarch64_print_operand): Likewise.
854 * aarch64-opc-2.c: Regenerate.
855 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
856 (ins_sve_addr_ri_s9xvl): New inserters.
857 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
858 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
859 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
860 * aarch64-asm-2.c: Regenerate.
861 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
862 (ext_sve_addr_ri_s9xvl): New extractors.
863 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
864 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
865 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
866 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
867 * aarch64-dis-2.c: Regenerate.
869 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
871 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
872 address operands.
873 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
874 (FLD_SVE_xs_22): New aarch64_field_kinds.
875 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
876 (get_operand_specific_data): New function.
877 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
878 FLD_SVE_xs_14 and FLD_SVE_xs_22.
879 (operand_general_constraint_met_p): Handle the new SVE address
880 operands.
881 (sve_reg): New array.
882 (get_addr_sve_reg_name): New function.
883 (aarch64_print_operand): Handle the new SVE address operands.
884 * aarch64-opc-2.c: Regenerate.
885 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
886 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
887 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
888 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
889 (aarch64_ins_sve_addr_rr_lsl): Likewise.
890 (aarch64_ins_sve_addr_rz_xtw): Likewise.
891 (aarch64_ins_sve_addr_zi_u5): Likewise.
892 (aarch64_ins_sve_addr_zz): Likewise.
893 (aarch64_ins_sve_addr_zz_lsl): Likewise.
894 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
895 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
896 * aarch64-asm-2.c: Regenerate.
897 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
898 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
899 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
900 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
901 (aarch64_ext_sve_addr_ri_u6): Likewise.
902 (aarch64_ext_sve_addr_rr_lsl): Likewise.
903 (aarch64_ext_sve_addr_rz_xtw): Likewise.
904 (aarch64_ext_sve_addr_zi_u5): Likewise.
905 (aarch64_ext_sve_addr_zz): Likewise.
906 (aarch64_ext_sve_addr_zz_lsl): Likewise.
907 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
908 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
909 * aarch64-dis-2.c: Regenerate.
911 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
913 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
914 AARCH64_OPND_SVE_PATTERN_SCALED.
915 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
916 * aarch64-opc.c (fields): Add a corresponding entry.
917 (set_multiplier_out_of_range_error): New function.
918 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
919 (operand_general_constraint_met_p): Handle
920 AARCH64_OPND_SVE_PATTERN_SCALED.
921 (print_register_offset_address): Use PRIi64 to print the
922 shift amount.
923 (aarch64_print_operand): Likewise. Handle
924 AARCH64_OPND_SVE_PATTERN_SCALED.
925 * aarch64-opc-2.c: Regenerate.
926 * aarch64-asm.h (ins_sve_scale): New inserter.
927 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
928 * aarch64-asm-2.c: Regenerate.
929 * aarch64-dis.h (ext_sve_scale): New inserter.
930 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
931 * aarch64-dis-2.c: Regenerate.
933 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
935 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
936 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
937 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
938 (FLD_SVE_prfop): Likewise.
939 * aarch64-opc.c: Include libiberty.h.
940 (aarch64_sve_pattern_array): New variable.
941 (aarch64_sve_prfop_array): Likewise.
942 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
943 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
944 AARCH64_OPND_SVE_PRFOP.
945 * aarch64-asm-2.c: Regenerate.
946 * aarch64-dis-2.c: Likewise.
947 * aarch64-opc-2.c: Likewise.
949 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
951 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
952 AARCH64_OPND_QLF_P_[ZM].
953 (aarch64_print_operand): Print /z and /m where appropriate.
955 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
957 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
958 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
959 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
960 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
961 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
962 * aarch64-opc.c (fields): Add corresponding entries here.
963 (operand_general_constraint_met_p): Check that SVE register lists
964 have the correct length. Check the ranges of SVE index registers.
965 Check for cases where p8-p15 are used in 3-bit predicate fields.
966 (aarch64_print_operand): Handle the new SVE operands.
967 * aarch64-opc-2.c: Regenerate.
968 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
969 * aarch64-asm.c (aarch64_ins_sve_index): New function.
970 (aarch64_ins_sve_reglist): Likewise.
971 * aarch64-asm-2.c: Regenerate.
972 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
973 * aarch64-dis.c (aarch64_ext_sve_index): New function.
974 (aarch64_ext_sve_reglist): Likewise.
975 * aarch64-dis-2.c: Regenerate.
977 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
979 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
980 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
981 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
982 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
983 tied operands.
985 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
987 * aarch64-opc.c (get_offset_int_reg_name): New function.
988 (print_immediate_offset_address): Likewise.
989 (print_register_offset_address): Take the base and offset
990 registers as parameters.
991 (aarch64_print_operand): Update caller accordingly. Use
992 print_immediate_offset_address.
994 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
996 * aarch64-opc.c (BANK): New macro.
997 (R32, R64): Take a register number as argument
998 (int_reg): Use BANK.
1000 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1002 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1003 (aarch64_print_operand): Update accordingly.
1005 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1007 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1008 for FPIMM.
1009 * aarch64-asm.h (ins_fpimm): New inserter.
1010 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1011 * aarch64-asm-2.c: Regenerate.
1012 * aarch64-dis.h (ext_fpimm): New extractor.
1013 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1014 (aarch64_ext_fpimm): New function.
1015 * aarch64-dis-2.c: Regenerate.
1017 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1019 * aarch64-asm.c: Include libiberty.h.
1020 (insert_fields): New function.
1021 (aarch64_ins_imm): Use it.
1022 * aarch64-dis.c (extract_fields): New function.
1023 (aarch64_ext_imm): Use it.
1025 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1027 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1028 with an esize parameter.
1029 (operand_general_constraint_met_p): Update accordingly.
1030 Fix misindented code.
1031 * aarch64-asm.c (aarch64_ins_limm): Update call to
1032 aarch64_logical_immediate_p.
1034 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1036 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1038 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1040 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1042 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1044 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1046 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1048 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1049 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1050 xor3>: Delete mnemonics.
1051 <cp_abort>: Rename mnemonic from ...
1052 <cpabort>: ...to this.
1053 <setb>: Change to a X form instruction.
1054 <sync>: Change to 1 operand form.
1055 <copy>: Delete mnemonic.
1056 <copy_first>: Rename mnemonic from ...
1057 <copy>: ...to this.
1058 <paste, paste.>: Delete mnemonics.
1059 <paste_last>: Rename mnemonic from ...
1060 <paste.>: ...to this.
1062 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1064 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1066 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1068 * s390-mkopc.c (main): Support alternate arch strings.
1070 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1072 * s390-opc.txt: Fix kmctr instruction type.
1074 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1076 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1077 * i386-init.h: Regenerated.
1079 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1081 * opcodes/arc-dis.c (print_insn_arc): Changed.
1083 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1085 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1086 camellia_fl.
1088 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1090 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1091 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1092 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1094 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1096 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1097 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1098 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1099 PREFIX_MOD_3_0FAE_REG_4.
1100 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1101 PREFIX_MOD_3_0FAE_REG_4.
1102 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1103 (cpu_flags): Add CpuPTWRITE.
1104 * i386-opc.h (CpuPTWRITE): New.
1105 (i386_cpu_flags): Add cpuptwrite.
1106 * i386-opc.tbl: Add ptwrite instruction.
1107 * i386-init.h: Regenerated.
1108 * i386-tbl.h: Likewise.
1110 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1112 * arc-dis.h: Wrap around in extern "C".
1114 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1116 * aarch64-tbl.h (V8_2_INSN): New macro.
1117 (aarch64_opcode_table): Use it.
1119 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1121 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1122 CORE_INSN, __FP_INSN and SIMD_INSN.
1124 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1126 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1127 (aarch64_opcode_table): Update uses accordingly.
1129 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1130 Kwok Cheung Yeung <kcy@codesourcery.com>
1132 opcodes/
1133 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1134 'e_cmplwi' to 'e_cmpli' instead.
1135 (OPVUPRT, OPVUPRT_MASK): Define.
1136 (powerpc_opcodes): Add E200Z4 insns.
1137 (vle_opcodes): Add context save/restore insns.
1139 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1141 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1142 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1143 "j".
1145 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1147 * arc-nps400-tbl.h: Change block comments to GNU format.
1148 * arc-dis.c: Add new globals addrtypenames,
1149 addrtypenames_max, and addtypeunknown.
1150 (get_addrtype): New function.
1151 (print_insn_arc): Print colons and address types when
1152 required.
1153 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1154 define insert and extract functions for all address types.
1155 (arc_operands): Add operands for colon and all address
1156 types.
1157 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1158 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1159 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1160 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1161 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1162 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1164 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1166 * configure: Regenerated.
1168 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1170 * arc-dis.c (skipclass): New structure.
1171 (decodelist): New variable.
1172 (is_compatible_p): New function.
1173 (new_element): Likewise.
1174 (skip_class_p): Likewise.
1175 (find_format_from_table): Use skip_class_p function.
1176 (find_format): Decode first the extension instructions.
1177 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1178 e_flags.
1179 (parse_option): New function.
1180 (parse_disassembler_options): Likewise.
1181 (print_arc_disassembler_options): Likewise.
1182 (print_insn_arc): Use parse_disassembler_options function. Proper
1183 select ARCv2 cpu variant.
1184 * disassemble.c (disassembler_usage): Add ARC disassembler
1185 options.
1187 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1189 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1190 annotation from the "nal" entry and reorder it beyond "bltzal".
1192 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1194 * sparc-opc.c (ldtxa): New macro.
1195 (sparc_opcodes): Use the macro defined above to add entries for
1196 the LDTXA instructions.
1197 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1198 instruction.
1200 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1202 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1203 and "jmpc".
1205 2016-07-01 Jan Beulich <jbeulich@suse.com>
1207 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1208 (movzb): Adjust to cover all permitted suffixes.
1209 (movzw): New.
1210 * i386-tbl.h: Re-generate.
1212 2016-07-01 Jan Beulich <jbeulich@suse.com>
1214 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1215 (lgdt): Remove Tbyte from non-64-bit variant.
1216 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1217 xsaves64, xsavec64): Remove Disp16.
1218 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1219 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1220 64-bit variants.
1221 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1222 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1223 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1224 64-bit variants.
1225 * i386-tbl.h: Re-generate.
1227 2016-07-01 Jan Beulich <jbeulich@suse.com>
1229 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1230 * i386-tbl.h: Re-generate.
1232 2016-06-30 Yao Qi <yao.qi@linaro.org>
1234 * arm-dis.c (print_insn): Fix typo in comment.
1236 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1238 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1239 range of ldst_elemlist operands.
1240 (print_register_list): Use PRIi64 to print the index.
1241 (aarch64_print_operand): Likewise.
1243 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1245 * mcore-opc.h: Remove sentinal.
1246 * mcore-dis.c (print_insn_mcore): Adjust.
1248 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1250 * arc-opc.c: Correct description of availability of NPS400
1251 features.
1253 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1255 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1256 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1257 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1258 xor3>: New mnemonics.
1259 <setb>: Change to a VX form instruction.
1260 (insert_sh6): Add support for rldixor.
1261 (extract_sh6): Likewise.
1263 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1265 * arc-ext.h: Wrap in extern C.
1267 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1269 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1270 Use same method for determining instruction length on ARC700 and
1271 NPS-400.
1272 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1273 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1274 with the NPS400 subclass.
1275 * arc-opc.c: Likewise.
1277 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1279 * sparc-opc.c (rdasr): New macro.
1280 (wrasr): Likewise.
1281 (rdpr): Likewise.
1282 (wrpr): Likewise.
1283 (rdhpr): Likewise.
1284 (wrhpr): Likewise.
1285 (sparc_opcodes): Use the macros above to fix and expand the
1286 definition of read/write instructions from/to
1287 asr/privileged/hyperprivileged instructions.
1288 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1289 %hva_mask_nz. Prefer softint_set and softint_clear over
1290 set_softint and clear_softint.
1291 (print_insn_sparc): Support %ver in Rd.
1293 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1295 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1296 architecture according to the hardware capabilities they require.
1298 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1300 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1301 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1302 bfd_mach_sparc_v9{c,d,e,v,m}.
1303 * sparc-opc.c (MASK_V9C): Define.
1304 (MASK_V9D): Likewise.
1305 (MASK_V9E): Likewise.
1306 (MASK_V9V): Likewise.
1307 (MASK_V9M): Likewise.
1308 (v6): Add MASK_V9{C,D,E,V,M}.
1309 (v6notlet): Likewise.
1310 (v7): Likewise.
1311 (v8): Likewise.
1312 (v9): Likewise.
1313 (v9andleon): Likewise.
1314 (v9a): Likewise.
1315 (v9b): Likewise.
1316 (v9c): Define.
1317 (v9d): Likewise.
1318 (v9e): Likewise.
1319 (v9v): Likewise.
1320 (v9m): Likewise.
1321 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1323 2016-06-15 Nick Clifton <nickc@redhat.com>
1325 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1326 constants to match expected behaviour.
1327 (nds32_parse_opcode): Likewise. Also for whitespace.
1329 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1331 * arc-opc.c (extract_rhv1): Extract value from insn.
1333 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1335 * arc-nps400-tbl.h: Add ldbit instruction.
1336 * arc-opc.c: Add flag classes required for ldbit.
1338 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1340 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1341 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1342 support the above instructions.
1344 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1346 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1347 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1348 csma, cbba, zncv, and hofs.
1349 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1350 support the above instructions.
1352 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1354 * arc-nps400-tbl.h: Add andab and orab instructions.
1356 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1358 * arc-nps400-tbl.h: Add addl-like instructions.
1360 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1362 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1364 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1366 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1367 instructions.
1369 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1371 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1372 variable.
1373 (init_disasm): Handle new command line option "insnlength".
1374 (print_s390_disassembler_options): Mention new option in help
1375 output.
1376 (print_insn_s390): Use the encoded insn length when dumping
1377 unknown instructions.
1379 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1381 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1382 to the address and set as symbol address for LDS/ STS immediate operands.
1384 2016-06-07 Alan Modra <amodra@gmail.com>
1386 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1387 cpu for "vle" to e500.
1388 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1389 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1390 (PPCNONE): Delete, substitute throughout.
1391 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1392 except for major opcode 4 and 31.
1393 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1395 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1397 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1398 ARM_EXT_RAS in relevant entries.
1400 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1402 PR binutils/20196
1403 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1404 opcodes for E6500.
1406 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1408 PR binutis/18386
1409 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1410 (indir_v_mode): New.
1411 Add comments for '&'.
1412 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1413 (putop): Handle '&'.
1414 (intel_operand_size): Handle indir_v_mode.
1415 (OP_E_register): Likewise.
1416 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1417 64-bit indirect call/jmp for AMD64.
1418 * i386-tbl.h: Regenerated
1420 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1422 * arc-dis.c (struct arc_operand_iterator): New structure.
1423 (find_format_from_table): All the old content from find_format,
1424 with some minor adjustments, and parameter renaming.
1425 (find_format_long_instructions): New function.
1426 (find_format): Rewritten.
1427 (arc_insn_length): Add LSB parameter.
1428 (extract_operand_value): New function.
1429 (operand_iterator_next): New function.
1430 (print_insn_arc): Use new functions to find opcode, and iterator
1431 over operands.
1432 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1433 (extract_nps_3bit_dst_short): New function.
1434 (insert_nps_3bit_src2_short): New function.
1435 (extract_nps_3bit_src2_short): New function.
1436 (insert_nps_bitop1_size): New function.
1437 (extract_nps_bitop1_size): New function.
1438 (insert_nps_bitop2_size): New function.
1439 (extract_nps_bitop2_size): New function.
1440 (insert_nps_bitop_mod4_msb): New function.
1441 (extract_nps_bitop_mod4_msb): New function.
1442 (insert_nps_bitop_mod4_lsb): New function.
1443 (extract_nps_bitop_mod4_lsb): New function.
1444 (insert_nps_bitop_dst_pos3_pos4): New function.
1445 (extract_nps_bitop_dst_pos3_pos4): New function.
1446 (insert_nps_bitop_ins_ext): New function.
1447 (extract_nps_bitop_ins_ext): New function.
1448 (arc_operands): Add new operands.
1449 (arc_long_opcodes): New global array.
1450 (arc_num_long_opcodes): New global.
1451 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1453 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1455 * nds32-asm.h: Add extern "C".
1456 * sh-opc.h: Likewise.
1458 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1460 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1461 0,b,limm to the rflt instruction.
1463 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1465 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1466 constant.
1468 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1470 PR gas/20145
1471 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1472 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1473 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1474 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1475 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1476 * i386-init.h: Regenerated.
1478 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1480 PR gas/20145
1481 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1482 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1483 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1484 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1485 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1486 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1487 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1488 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1489 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1490 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1491 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1492 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1493 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1494 CpuRegMask for AVX512.
1495 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1496 and CpuRegMask.
1497 (set_bitfield_from_cpu_flag_init): New function.
1498 (set_bitfield): Remove const on f. Call
1499 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1500 * i386-opc.h (CpuRegMMX): New.
1501 (CpuRegXMM): Likewise.
1502 (CpuRegYMM): Likewise.
1503 (CpuRegZMM): Likewise.
1504 (CpuRegMask): Likewise.
1505 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1506 and cpuregmask.
1507 * i386-init.h: Regenerated.
1508 * i386-tbl.h: Likewise.
1510 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1512 PR gas/20154
1513 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1514 (opcode_modifiers): Add AMD64 and Intel64.
1515 (main): Properly verify CpuMax.
1516 * i386-opc.h (CpuAMD64): Removed.
1517 (CpuIntel64): Likewise.
1518 (CpuMax): Set to CpuNo64.
1519 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1520 (AMD64): New.
1521 (Intel64): Likewise.
1522 (i386_opcode_modifier): Add amd64 and intel64.
1523 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1524 on call and jmp.
1525 * i386-init.h: Regenerated.
1526 * i386-tbl.h: Likewise.
1528 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1530 PR gas/20154
1531 * i386-gen.c (main): Fail if CpuMax is incorrect.
1532 * i386-opc.h (CpuMax): Set to CpuIntel64.
1533 * i386-tbl.h: Regenerated.
1535 2016-05-27 Nick Clifton <nickc@redhat.com>
1537 PR target/20150
1538 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1539 (msp430dis_opcode_unsigned): New function.
1540 (msp430dis_opcode_signed): New function.
1541 (msp430_singleoperand): Use the new opcode reading functions.
1542 Only disassenmble bytes if they were successfully read.
1543 (msp430_doubleoperand): Likewise.
1544 (msp430_branchinstr): Likewise.
1545 (msp430x_callx_instr): Likewise.
1546 (print_insn_msp430): Check that it is safe to read bytes before
1547 attempting disassembly. Use the new opcode reading functions.
1549 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1551 * ppc-opc.c (CY): New define. Document it.
1552 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1554 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1556 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1557 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1558 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1559 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1560 CPU_ANY_AVX_FLAGS.
1561 * i386-init.h: Regenerated.
1563 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1565 PR gas/20141
1566 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1567 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1568 * i386-init.h: Regenerated.
1570 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1572 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1573 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1574 * i386-init.h: Regenerated.
1576 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1578 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1579 information.
1580 (print_insn_arc): Set insn_type information.
1581 * arc-opc.c (C_CC): Add F_CLASS_COND.
1582 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1583 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1584 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1585 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1586 (brne, brne_s, jeq_s, jne_s): Likewise.
1588 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1590 * arc-tbl.h (neg): New instruction variant.
1592 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1594 * arc-dis.c (find_format, find_format, get_auxreg)
1595 (print_insn_arc): Changed.
1596 * arc-ext.h (INSERT_XOP): Likewise.
1598 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1600 * tic54x-dis.c (sprint_mmr): Adjust.
1601 * tic54x-opc.c: Likewise.
1603 2016-05-19 Alan Modra <amodra@gmail.com>
1605 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1607 2016-05-19 Alan Modra <amodra@gmail.com>
1609 * ppc-opc.c: Formatting.
1610 (NSISIGNOPT): Define.
1611 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1613 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1615 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1616 replacing references to `micromips_ase' throughout.
1617 (_print_insn_mips): Don't use file-level microMIPS annotation to
1618 determine the disassembly mode with the symbol table.
1620 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1622 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1624 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1626 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1627 mips64r6.
1628 * mips-opc.c (D34): New macro.
1629 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1631 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1633 * i386-dis.c (prefix_table): Add RDPID instruction.
1634 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1635 (cpu_flags): Add RDPID bitfield.
1636 * i386-opc.h (enum): Add RDPID element.
1637 (i386_cpu_flags): Add RDPID field.
1638 * i386-opc.tbl: Add RDPID instruction.
1639 * i386-init.h: Regenerate.
1640 * i386-tbl.h: Regenerate.
1642 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1644 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1645 branch type of a symbol.
1646 (print_insn): Likewise.
1648 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1650 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1651 Mainline Security Extensions instructions.
1652 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1653 Extensions instructions.
1654 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1655 instructions.
1656 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1657 special registers.
1659 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1661 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1663 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1665 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1666 (arcExtMap_genOpcode): Likewise.
1667 * arc-opc.c (arg_32bit_rc): Define new variable.
1668 (arg_32bit_u6): Likewise.
1669 (arg_32bit_limm): Likewise.
1671 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1673 * aarch64-gen.c (VERIFIER): Define.
1674 * aarch64-opc.c (VERIFIER): Define.
1675 (verify_ldpsw): Use static linkage.
1676 * aarch64-opc.h (verify_ldpsw): Remove.
1677 * aarch64-tbl.h: Use VERIFIER for verifiers.
1679 2016-04-28 Nick Clifton <nickc@redhat.com>
1681 PR target/19722
1682 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1683 * aarch64-opc.c (verify_ldpsw): New function.
1684 * aarch64-opc.h (verify_ldpsw): New prototype.
1685 * aarch64-tbl.h: Add initialiser for verifier field.
1686 (LDPSW): Set verifier to verify_ldpsw.
1688 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1690 PR binutils/19983
1691 PR binutils/19984
1692 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1693 smaller than address size.
1695 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1697 * alpha-dis.c: Regenerate.
1698 * crx-dis.c: Likewise.
1699 * disassemble.c: Likewise.
1700 * epiphany-opc.c: Likewise.
1701 * fr30-opc.c: Likewise.
1702 * frv-opc.c: Likewise.
1703 * ip2k-opc.c: Likewise.
1704 * iq2000-opc.c: Likewise.
1705 * lm32-opc.c: Likewise.
1706 * lm32-opinst.c: Likewise.
1707 * m32c-opc.c: Likewise.
1708 * m32r-opc.c: Likewise.
1709 * m32r-opinst.c: Likewise.
1710 * mep-opc.c: Likewise.
1711 * mt-opc.c: Likewise.
1712 * or1k-opc.c: Likewise.
1713 * or1k-opinst.c: Likewise.
1714 * tic80-opc.c: Likewise.
1715 * xc16x-opc.c: Likewise.
1716 * xstormy16-opc.c: Likewise.
1718 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1720 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1721 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1722 calcsd, and calcxd instructions.
1723 * arc-opc.c (insert_nps_bitop_size): Delete.
1724 (extract_nps_bitop_size): Delete.
1725 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1726 (extract_nps_qcmp_m3): Define.
1727 (extract_nps_qcmp_m2): Define.
1728 (extract_nps_qcmp_m1): Define.
1729 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1730 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1731 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1732 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1733 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1734 NPS_QCMP_M3.
1736 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1738 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1740 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1742 * Makefile.in: Regenerated with automake 1.11.6.
1743 * aclocal.m4: Likewise.
1745 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1747 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1748 instructions.
1749 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1750 (extract_nps_cmem_uimm16): New function.
1751 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1753 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1755 * arc-dis.c (arc_insn_length): New function.
1756 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1757 (find_format): Change insnLen parameter to unsigned.
1759 2016-04-13 Nick Clifton <nickc@redhat.com>
1761 PR target/19937
1762 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1763 the LD.B and LD.BU instructions.
1765 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1767 * arc-dis.c (find_format): Check for extension flags.
1768 (print_flags): New function.
1769 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1770 .extAuxRegister.
1771 * arc-ext.c (arcExtMap_coreRegName): Use
1772 LAST_EXTENSION_CORE_REGISTER.
1773 (arcExtMap_coreReadWrite): Likewise.
1774 (dump_ARC_extmap): Update printing.
1775 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1776 (arc_aux_regs): Add cpu field.
1777 * arc-regs.h: Add cpu field, lower case name aux registers.
1779 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1781 * arc-tbl.h: Add rtsc, sleep with no arguments.
1783 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1785 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1786 Initialize.
1787 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1788 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1789 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1790 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1791 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1792 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1793 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1794 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1795 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1796 (arc_opcode arc_opcodes): Null terminate the array.
1797 (arc_num_opcodes): Remove.
1798 * arc-ext.h (INSERT_XOP): Define.
1799 (extInstruction_t): Likewise.
1800 (arcExtMap_instName): Delete.
1801 (arcExtMap_insn): New function.
1802 (arcExtMap_genOpcode): Likewise.
1803 * arc-ext.c (ExtInstruction): Remove.
1804 (create_map): Zero initialize instruction fields.
1805 (arcExtMap_instName): Remove.
1806 (arcExtMap_insn): New function.
1807 (dump_ARC_extmap): More info while debuging.
1808 (arcExtMap_genOpcode): New function.
1809 * arc-dis.c (find_format): New function.
1810 (print_insn_arc): Use find_format.
1811 (arc_get_disassembler): Enable dump_ARC_extmap only when
1812 debugging.
1814 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1816 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1817 instruction bits out.
1819 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1821 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1822 * arc-opc.c (arc_flag_operands): Add new flags.
1823 (arc_flag_classes): Add new classes.
1825 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1827 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1829 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1831 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1832 encode1, rflt, crc16, and crc32 instructions.
1833 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1834 (arc_flag_classes): Add C_NPS_R.
1835 (insert_nps_bitop_size_2b): New function.
1836 (extract_nps_bitop_size_2b): Likewise.
1837 (insert_nps_bitop_uimm8): Likewise.
1838 (extract_nps_bitop_uimm8): Likewise.
1839 (arc_operands): Add new operand entries.
1841 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1843 * arc-regs.h: Add a new subclass field. Add double assist
1844 accumulator register values.
1845 * arc-tbl.h: Use DPA subclass to mark the double assist
1846 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1847 * arc-opc.c (RSP): Define instead of SP.
1848 (arc_aux_regs): Add the subclass field.
1850 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1852 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1854 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1856 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1857 NPS_R_SRC1.
1859 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1861 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1862 issues. No functional changes.
1864 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1866 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1867 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1868 (RTT): Remove duplicate.
1869 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1870 (PCT_CONFIG*): Remove.
1871 (D1L, D1H, D2H, D2L): Define.
1873 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1875 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1877 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1879 * arc-tbl.h (invld07): Remove.
1880 * arc-ext-tbl.h: New file.
1881 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1882 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1884 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1886 Fix -Wstack-usage warnings.
1887 * aarch64-dis.c (print_operands): Substitute size.
1888 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1890 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1892 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1893 to get a proper diagnostic when an invalid ASR register is used.
1895 2016-03-22 Nick Clifton <nickc@redhat.com>
1897 * configure: Regenerate.
1899 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1901 * arc-nps400-tbl.h: New file.
1902 * arc-opc.c: Add top level comment.
1903 (insert_nps_3bit_dst): New function.
1904 (extract_nps_3bit_dst): New function.
1905 (insert_nps_3bit_src2): New function.
1906 (extract_nps_3bit_src2): New function.
1907 (insert_nps_bitop_size): New function.
1908 (extract_nps_bitop_size): New function.
1909 (arc_flag_operands): Add nps400 entries.
1910 (arc_flag_classes): Add nps400 entries.
1911 (arc_operands): Add nps400 entries.
1912 (arc_opcodes): Add nps400 include.
1914 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1916 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1917 the new class enum values.
1919 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1921 * arc-dis.c (print_insn_arc): Handle nps400.
1923 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1925 * arc-opc.c (BASE): Delete.
1927 2016-03-18 Nick Clifton <nickc@redhat.com>
1929 PR target/19721
1930 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1931 of MOV insn that aliases an ORR insn.
1933 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1935 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1937 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1939 * mcore-opc.h: Add const qualifiers.
1940 * microblaze-opc.h (struct op_code_struct): Likewise.
1941 * sh-opc.h: Likewise.
1942 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1943 (tic4x_print_op): Likewise.
1945 2016-03-02 Alan Modra <amodra@gmail.com>
1947 * or1k-desc.h: Regenerate.
1948 * fr30-ibld.c: Regenerate.
1949 * rl78-decode.c: Regenerate.
1951 2016-03-01 Nick Clifton <nickc@redhat.com>
1953 PR target/19747
1954 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1956 2016-02-24 Renlin Li <renlin.li@arm.com>
1958 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1959 (print_insn_coprocessor): Support fp16 instructions.
1961 2016-02-24 Renlin Li <renlin.li@arm.com>
1963 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1964 vminnm, vrint(mpna).
1966 2016-02-24 Renlin Li <renlin.li@arm.com>
1968 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1969 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1971 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1973 * i386-dis.c (print_insn): Parenthesize expression to prevent
1974 truncated addresses.
1975 (OP_J): Likewise.
1977 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1978 Janek van Oirschot <jvanoirs@synopsys.com>
1980 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1981 variable.
1983 2016-02-04 Nick Clifton <nickc@redhat.com>
1985 PR target/19561
1986 * msp430-dis.c (print_insn_msp430): Add a special case for
1987 decoding an RRC instruction with the ZC bit set in the extension
1988 word.
1990 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1992 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1993 * epiphany-ibld.c: Regenerate.
1994 * fr30-ibld.c: Regenerate.
1995 * frv-ibld.c: Regenerate.
1996 * ip2k-ibld.c: Regenerate.
1997 * iq2000-ibld.c: Regenerate.
1998 * lm32-ibld.c: Regenerate.
1999 * m32c-ibld.c: Regenerate.
2000 * m32r-ibld.c: Regenerate.
2001 * mep-ibld.c: Regenerate.
2002 * mt-ibld.c: Regenerate.
2003 * or1k-ibld.c: Regenerate.
2004 * xc16x-ibld.c: Regenerate.
2005 * xstormy16-ibld.c: Regenerate.
2007 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2009 * epiphany-dis.c: Regenerated from latest cpu files.
2011 2016-02-01 Michael McConville <mmcco@mykolab.com>
2013 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2014 test bit.
2016 2016-01-25 Renlin Li <renlin.li@arm.com>
2018 * arm-dis.c (mapping_symbol_for_insn): New function.
2019 (find_ifthen_state): Call mapping_symbol_for_insn().
2021 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2023 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2024 of MSR UAO immediate operand.
2026 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2028 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2029 instruction support.
2031 2016-01-17 Alan Modra <amodra@gmail.com>
2033 * configure: Regenerate.
2035 2016-01-14 Nick Clifton <nickc@redhat.com>
2037 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2038 instructions that can support stack pointer operations.
2039 * rl78-decode.c: Regenerate.
2040 * rl78-dis.c: Fix display of stack pointer in MOVW based
2041 instructions.
2043 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2045 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2046 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2047 erxtatus_el1 and erxaddr_el1.
2049 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2051 * arm-dis.c (arm_opcodes): Add "esb".
2052 (thumb_opcodes): Likewise.
2054 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2056 * ppc-opc.c <xscmpnedp>: Delete.
2057 <xvcmpnedp>: Likewise.
2058 <xvcmpnedp.>: Likewise.
2059 <xvcmpnesp>: Likewise.
2060 <xvcmpnesp.>: Likewise.
2062 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2064 PR gas/13050
2065 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2066 addition to ISA_A.
2068 2016-01-01 Alan Modra <amodra@gmail.com>
2070 Update year range in copyright notice of all files.
2072 For older changes see ChangeLog-2015
2073 \f
2074 Copyright (C) 2016 Free Software Foundation, Inc.
2076 Copying and distribution of this file, with or without modification,
2077 are permitted in any medium without royalty provided the copyright
2078 notice and this notice are preserved.
2080 Local Variables:
2081 mode: change-log
2082 left-margin: 8
2083 fill-column: 74
2084 version-control: never
2085 End: