1 /* This must come before any other includes. */
14 #include "sim-signal.h"
16 #include "target-newlib-syscall.h"
20 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
53 PSW_MASK
= (PSW_SM_BIT
64 /* The following bits in the PSW _can't_ be set by instructions such
66 PSW_HW_MASK
= (PSW_MASK
| PSW_DM_BIT
)
70 move_to_cr (SIM_DESC sd
, SIM_CPU
*cpu
, int cr
, reg_t mask
, reg_t val
, int psw_hw_p
)
72 /* A MASK bit is set when the corresponding bit in the CR should
74 /* This assumes that (VAL & MASK) == 0 */
82 if ((mask
& PSW_SM_BIT
) == 0)
84 int new_psw_sm
= (val
& PSW_SM_BIT
) != 0;
86 SET_HELD_SP (PSW_SM
, GPR (SP_IDX
));
87 if (PSW_SM
!= new_psw_sm
)
89 SET_GPR (SP_IDX
, HELD_SP (new_psw_sm
));
91 if ((mask
& (PSW_ST_BIT
| PSW_FX_BIT
)) == 0)
93 if (val
& PSW_ST_BIT
&& !(val
& PSW_FX_BIT
))
97 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
99 EXCEPTION (SIM_SIGILL
);
102 /* keep an up-to-date psw around for tracing */
103 State
.trace
.psw
= (State
.trace
.psw
& mask
) | val
;
107 /* Just like PSW, mask things like DM out. */
120 /* only issue an update if the register is being changed */
121 if ((State
.cregs
[cr
] & ~mask
) != val
)
122 SLOT_PEND_MASK (State
.cregs
[cr
], mask
, val
);
127 static void trace_input_func (SIM_DESC sd
,
133 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
135 #ifndef SIZE_INSTRUCTION
136 #define SIZE_INSTRUCTION 8
139 #ifndef SIZE_OPERANDS
140 #define SIZE_OPERANDS 18
144 #define SIZE_VALUES 13
147 #ifndef SIZE_LOCATION
148 #define SIZE_LOCATION 20
155 #ifndef SIZE_LINE_NUMBER
156 #define SIZE_LINE_NUMBER 4
160 trace_input_func (SIM_DESC sd
, const char *name
, enum op_types in1
, enum op_types in2
, enum op_types in3
)
169 const char *filename
;
170 const char *functionname
;
171 unsigned int linenumber
;
174 if ((d10v_debug
& DEBUG_TRACE
) == 0)
177 switch (State
.ins_type
)
180 case INS_UNKNOWN
: type
= " ?"; break;
181 case INS_LEFT
: type
= " L"; break;
182 case INS_RIGHT
: type
= " R"; break;
183 case INS_LEFT_PARALLEL
: type
= "*L"; break;
184 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
185 case INS_LEFT_COND_TEST
: type
= "?L"; break;
186 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
187 case INS_LEFT_COND_EXE
: type
= "&L"; break;
188 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
189 case INS_LONG
: type
= " B"; break;
192 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
195 SIZE_PC
, (unsigned)PC
,
197 SIZE_INSTRUCTION
, name
);
203 if (STATE_TEXT_SECTION (sd
)
204 && byte_pc
>= STATE_TEXT_START (sd
)
205 && byte_pc
< STATE_TEXT_END (sd
))
207 filename
= (const char *)0;
208 functionname
= (const char *)0;
210 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
211 STATE_TEXT_SECTION (sd
),
212 (struct bfd_symbol
**)0,
213 byte_pc
- STATE_TEXT_START (sd
),
214 &filename
, &functionname
, &linenumber
))
219 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
224 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
225 p
+= SIZE_LINE_NUMBER
+2;
230 sprintf (p
, "%s ", functionname
);
235 char *q
= strrchr (filename
, '/');
236 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
246 "0x%.*x %s: %-*.*s %-*s ",
247 SIZE_PC
, (unsigned)PC
,
249 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
250 SIZE_INSTRUCTION
, name
);
258 for (i
= 0; i
< 3; i
++)
272 sprintf (p
, "%sr%d", comma
, OP
[i
]);
280 sprintf (p
, "%scr%d", comma
, OP
[i
]);
286 case OP_ACCUM_OUTPUT
:
287 case OP_ACCUM_REVERSE
:
288 sprintf (p
, "%sa%d", comma
, OP
[i
]);
294 sprintf (p
, "%s%d", comma
, OP
[i
]);
300 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
306 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
312 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
318 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
324 sprintf (p
, "%s@(%d,r%d)", comma
, (int16_t)OP
[i
], OP
[i
+1]);
330 sprintf (p
, "%s@%d", comma
, OP
[i
]);
336 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
342 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
348 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
356 sprintf (p
, "%sf0", comma
);
359 sprintf (p
, "%sf1", comma
);
362 sprintf (p
, "%sc", comma
);
370 if ((d10v_debug
& DEBUG_VALUES
) == 0)
374 sim_io_printf (sd
, "%s", buf
);
379 sim_io_printf (sd
, "%-*s", SIZE_OPERANDS
, buf
);
382 for (i
= 0; i
< 3; i
++)
388 sim_io_printf (sd
, "%*s", SIZE_VALUES
, "");
394 case OP_ACCUM_OUTPUT
:
396 sim_io_printf (sd
, "%*s", SIZE_VALUES
, "---");
404 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
405 (uint16_t) GPR (OP
[i
]));
409 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "", (uint16_t) OP
[i
]);
413 tmp
= (long)((((uint32_t) GPR (OP
[i
])) << 16) | ((uint32_t) GPR (OP
[i
] + 1)));
414 sim_io_printf (sd
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
419 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
420 (uint16_t) CREG (OP
[i
]));
424 case OP_ACCUM_REVERSE
:
425 sim_io_printf (sd
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
426 ((int)(ACC (OP
[i
]) >> 32) & 0xff),
427 ((unsigned long) ACC (OP
[i
])) & 0xffffffff);
431 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
436 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
437 (uint16_t)SEXT4(OP
[i
]));
441 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
442 (uint16_t)SEXT8(OP
[i
]));
446 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
447 (uint16_t)SEXT3(OP
[i
]));
452 sim_io_printf (sd
, "%*sF0 = %d", SIZE_VALUES
-6, "",
456 sim_io_printf (sd
, "%*sF1 = %d", SIZE_VALUES
-6, "",
460 sim_io_printf (sd
, "%*sC = %d", SIZE_VALUES
-5, "",
466 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
468 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
469 (uint16_t)GPR (OP
[i
+ 1]));
474 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
479 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
484 sim_io_printf (sd
, "%*s0x%.4x", SIZE_VALUES
-6, "",
492 sim_io_flush_stdout (sd
);
496 do_trace_output_flush (SIM_DESC sd
)
498 sim_io_flush_stdout (sd
);
502 do_trace_output_finish (SIM_DESC sd
)
505 " F0=%d F1=%d C=%d\n",
506 (State
.trace
.psw
& PSW_F0_BIT
) != 0,
507 (State
.trace
.psw
& PSW_F1_BIT
) != 0,
508 (State
.trace
.psw
& PSW_C_BIT
) != 0);
509 sim_io_flush_stdout (sd
);
513 trace_output_40 (SIM_DESC sd
, uint64_t val
)
515 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
518 " :: %*s0x%.2x%.8lx",
521 ((int)(val
>> 32) & 0xff),
522 ((unsigned long) val
) & 0xffffffff);
523 do_trace_output_finish (sd
);
528 trace_output_32 (SIM_DESC sd
, uint32_t val
)
530 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
537 do_trace_output_finish (sd
);
542 trace_output_16 (SIM_DESC sd
, uint16_t val
)
544 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
551 do_trace_output_finish (sd
);
556 trace_output_void (SIM_DESC sd
)
558 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
560 sim_io_printf (sd
, "\n");
561 do_trace_output_flush (sd
);
566 trace_output_flag (SIM_DESC sd
)
568 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
574 do_trace_output_finish (sd
);
582 #define trace_input(NAME, IN1, IN2, IN3)
583 #define trace_output(RESULT)
588 OP_4607 (SIM_DESC sd
, SIM_CPU
*cpu
)
591 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
601 SET_GPR (OP
[0], tmp
);
602 trace_output_16 (sd
, tmp
);
607 OP_5607 (SIM_DESC sd
, SIM_CPU
*cpu
)
610 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
613 tmp
= SEXT40 (ACC (OP
[0]));
619 if (tmp
> SEXT40(MAX32
))
621 else if (tmp
< SEXT40(MIN32
))
624 tmp
= (tmp
& MASK40
);
627 tmp
= (tmp
& MASK40
);
632 tmp
= (tmp
& MASK40
);
635 SET_ACC (OP
[0], tmp
);
636 trace_output_40 (sd
, tmp
);
641 OP_200 (SIM_DESC sd
, SIM_CPU
*cpu
)
643 uint16_t a
= GPR (OP
[0]);
644 uint16_t b
= GPR (OP
[1]);
645 uint16_t tmp
= (a
+ b
);
646 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
648 SET_GPR (OP
[0], tmp
);
649 trace_output_16 (sd
, tmp
);
654 OP_1201 (SIM_DESC sd
, SIM_CPU
*cpu
)
657 tmp
= SEXT40(ACC (OP
[0])) + (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
659 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
662 if (tmp
> SEXT40(MAX32
))
664 else if (tmp
< SEXT40(MIN32
))
667 tmp
= (tmp
& MASK40
);
670 tmp
= (tmp
& MASK40
);
671 SET_ACC (OP
[0], tmp
);
672 trace_output_40 (sd
, tmp
);
677 OP_1203 (SIM_DESC sd
, SIM_CPU
*cpu
)
680 tmp
= SEXT40(ACC (OP
[0])) + SEXT40(ACC (OP
[1]));
682 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
685 if (tmp
> SEXT40(MAX32
))
687 else if (tmp
< SEXT40(MIN32
))
690 tmp
= (tmp
& MASK40
);
693 tmp
= (tmp
& MASK40
);
694 SET_ACC (OP
[0], tmp
);
695 trace_output_40 (sd
, tmp
);
700 OP_1200 (SIM_DESC sd
, SIM_CPU
*cpu
)
703 uint32_t a
= (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1);
704 uint32_t b
= (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
705 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
708 SET_GPR (OP
[0] + 0, (tmp
>> 16));
709 SET_GPR (OP
[0] + 1, (tmp
& 0xFFFF));
710 trace_output_32 (sd
, tmp
);
715 OP_1000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
717 uint16_t a
= GPR (OP
[1]);
719 uint16_t tmp
= (a
+ b
);
720 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
722 SET_GPR (OP
[0], tmp
);
723 trace_output_16 (sd
, tmp
);
728 OP_17000200 (SIM_DESC sd
, SIM_CPU
*cpu
)
731 tmp
= SEXT40(ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
733 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
734 SET_GPR (OP
[0] + 0, ((tmp
>> 16) & 0xffff));
735 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
736 trace_output_32 (sd
, tmp
);
741 OP_17000202 (SIM_DESC sd
, SIM_CPU
*cpu
)
744 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
746 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
747 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
748 SET_GPR (OP
[0] + 1, tmp
& 0xffff);
749 trace_output_32 (sd
, tmp
);
754 OP_17001200 (SIM_DESC sd
, SIM_CPU
*cpu
)
759 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
760 tmp
= SEXT40 (ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
761 if (tmp
> SEXT40(MAX32
))
766 else if (tmp
< SEXT40(MIN32
))
775 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
776 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
777 trace_output_32 (sd
, tmp
);
782 OP_17001202 (SIM_DESC sd
, SIM_CPU
*cpu
)
787 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
788 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
789 if (tmp
> SEXT40(MAX32
))
794 else if (tmp
< SEXT40(MIN32
))
803 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
804 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
805 trace_output_32 (sd
, tmp
);
810 OP_201 (SIM_DESC sd
, SIM_CPU
*cpu
)
812 uint16_t a
= GPR (OP
[0]);
819 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
821 SET_GPR (OP
[0], tmp
);
822 trace_output_16 (sd
, tmp
);
827 OP_C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
829 uint16_t tmp
= GPR (OP
[0]) & GPR (OP
[1]);
830 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
831 SET_GPR (OP
[0], tmp
);
832 trace_output_16 (sd
, tmp
);
837 OP_6000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
839 uint16_t tmp
= GPR (OP
[1]) & OP
[2];
840 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
841 SET_GPR (OP
[0], tmp
);
842 trace_output_16 (sd
, tmp
);
847 OP_C01 (SIM_DESC sd
, SIM_CPU
*cpu
)
850 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
851 tmp
= (GPR (OP
[0]) &~(0x8000 >> OP
[1]));
852 SET_GPR (OP
[0], tmp
);
853 trace_output_16 (sd
, tmp
);
858 OP_4900 (SIM_DESC sd
, SIM_CPU
*cpu
)
860 trace_input ("bl.s", OP_CONSTANT8
, OP_R0
, OP_R1
);
861 SET_GPR (13, PC
+ 1);
862 JMP( PC
+ SEXT8 (OP
[0]));
863 trace_output_void (sd
);
868 OP_24800000 (SIM_DESC sd
, SIM_CPU
*cpu
)
870 trace_input ("bl.l", OP_CONSTANT16
, OP_R0
, OP_R1
);
871 SET_GPR (13, (PC
+ 1));
873 trace_output_void (sd
);
878 OP_A01 (SIM_DESC sd
, SIM_CPU
*cpu
)
881 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
882 tmp
= (GPR (OP
[0]) ^ (0x8000 >> OP
[1]));
883 SET_GPR (OP
[0], tmp
);
884 trace_output_16 (sd
, tmp
);
889 OP_4800 (SIM_DESC sd
, SIM_CPU
*cpu
)
891 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
892 JMP (PC
+ SEXT8 (OP
[0]));
893 trace_output_void (sd
);
898 OP_24000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
900 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
902 trace_output_void (sd
);
907 OP_4A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
909 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
911 JMP (PC
+ SEXT8 (OP
[0]));
912 trace_output_flag (sd
);
917 OP_25000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
919 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
922 trace_output_flag (sd
);
927 OP_4B00 (SIM_DESC sd
, SIM_CPU
*cpu
)
929 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
931 JMP (PC
+ SEXT8 (OP
[0]));
932 trace_output_flag (sd
);
937 OP_25800000 (SIM_DESC sd
, SIM_CPU
*cpu
)
939 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
942 trace_output_flag (sd
);
947 OP_801 (SIM_DESC sd
, SIM_CPU
*cpu
)
950 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
951 tmp
= (GPR (OP
[0]) | (0x8000 >> OP
[1]));
952 SET_GPR (OP
[0], tmp
);
953 trace_output_16 (sd
, tmp
);
958 OP_E01 (SIM_DESC sd
, SIM_CPU
*cpu
)
960 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
962 SET_PSW_F0 ((GPR (OP
[0]) & (0x8000 >> OP
[1])) ? 1 : 0);
963 trace_output_flag (sd
);
968 OP_5601 (SIM_DESC sd
, SIM_CPU
*cpu
)
970 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
972 trace_output_40 (sd
, 0);
977 OP_600 (SIM_DESC sd
, SIM_CPU
*cpu
)
979 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
981 SET_PSW_F0 (((int16_t)(GPR (OP
[0])) < (int16_t)(GPR (OP
[1]))) ? 1 : 0);
982 trace_output_flag (sd
);
987 OP_1603 (SIM_DESC sd
, SIM_CPU
*cpu
)
989 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
991 SET_PSW_F0 ((SEXT40(ACC (OP
[0])) < SEXT40(ACC (OP
[1]))) ? 1 : 0);
992 trace_output_flag (sd
);
997 OP_400 (SIM_DESC sd
, SIM_CPU
*cpu
)
999 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
1000 SET_PSW_F1 (PSW_F0
);
1001 SET_PSW_F0 ((GPR (OP
[0]) == GPR (OP
[1])) ? 1 : 0);
1002 trace_output_flag (sd
);
1007 OP_1403 (SIM_DESC sd
, SIM_CPU
*cpu
)
1009 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1010 SET_PSW_F1 (PSW_F0
);
1011 SET_PSW_F0 (((ACC (OP
[0]) & MASK40
) == (ACC (OP
[1]) & MASK40
)) ? 1 : 0);
1012 trace_output_flag (sd
);
1017 OP_401 (SIM_DESC sd
, SIM_CPU
*cpu
)
1019 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1020 SET_PSW_F1 (PSW_F0
);
1021 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
) SEXT4 (OP
[1])) ? 1 : 0);
1022 trace_output_flag (sd
);
1027 OP_2000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1029 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1030 SET_PSW_F1 (PSW_F0
);
1031 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
)OP
[1]) ? 1 : 0);
1032 trace_output_flag (sd
);
1037 OP_601 (SIM_DESC sd
, SIM_CPU
*cpu
)
1039 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1040 SET_PSW_F1 (PSW_F0
);
1041 SET_PSW_F0 (((int16_t)(GPR (OP
[0])) < (int16_t)SEXT4(OP
[1])) ? 1 : 0);
1042 trace_output_flag (sd
);
1047 OP_3000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1049 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1050 SET_PSW_F1 (PSW_F0
);
1051 SET_PSW_F0 (((int16_t)(GPR (OP
[0])) < (int16_t)(OP
[1])) ? 1 : 0);
1052 trace_output_flag (sd
);
1057 OP_4600 (SIM_DESC sd
, SIM_CPU
*cpu
)
1059 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
1060 SET_PSW_F1 (PSW_F0
);
1061 SET_PSW_F0 ((GPR (OP
[0]) < GPR (OP
[1])) ? 1 : 0);
1062 trace_output_flag (sd
);
1067 OP_23000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1069 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1070 SET_PSW_F1 (PSW_F0
);
1071 SET_PSW_F0 ((GPR (OP
[0]) < (reg_t
)OP
[1]) ? 1 : 0);
1072 trace_output_flag (sd
);
1077 OP_4E09 (SIM_DESC sd
, SIM_CPU
*cpu
)
1081 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1085 else if (OP
[1] == 1)
1094 trace_output_flag (sd
);
1099 OP_4E0F (SIM_DESC sd
, SIM_CPU
*cpu
)
1103 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1107 else if (OP
[1] == 1)
1116 trace_output_flag (sd
);
1121 OP_5F20 (SIM_DESC sd
, SIM_CPU
*cpu
)
1123 /* sim_io_printf (sd, "***** DBT ***** PC=%x\n",PC); */
1125 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1126 The conditional below is for either of the instruction pairs
1127 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1128 where the dbt instruction should be interpreted.
1130 The module `sim-break' provides a more effective mechanism for
1131 detecting GDB planted breakpoints. The code below may,
1132 eventually, be changed to use that mechanism. */
1134 if (State
.ins_type
== INS_LEFT
1135 || State
.ins_type
== INS_RIGHT
)
1137 trace_input ("dbt", OP_VOID
, OP_VOID
, OP_VOID
);
1140 SET_HW_PSW (PSW_DM_BIT
| (PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1141 JMP (DBT_VECTOR_START
);
1142 trace_output_void (sd
);
1145 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGTRAP
);
1150 OP_14002800 (SIM_DESC sd
, SIM_CPU
*cpu
)
1152 uint16_t foo
, tmp
, tmpf
;
1156 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1157 foo
= (GPR (OP
[0]) << 1) | (GPR (OP
[0] + 1) >> 15);
1158 tmp
= (int16_t)foo
- (int16_t)(GPR (OP
[1]));
1159 tmpf
= (foo
>= GPR (OP
[1])) ? 1 : 0;
1160 hi
= ((tmpf
== 1) ? tmp
: foo
);
1161 lo
= ((GPR (OP
[0] + 1) << 1) | tmpf
);
1162 SET_GPR (OP
[0] + 0, hi
);
1163 SET_GPR (OP
[0] + 1, lo
);
1164 trace_output_32 (sd
, ((uint32_t) hi
<< 16) | lo
);
1169 OP_4E04 (SIM_DESC sd
, SIM_CPU
*cpu
)
1171 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1172 State
.exe
= (PSW_F0
== 0);
1173 trace_output_flag (sd
);
1178 OP_4E24 (SIM_DESC sd
, SIM_CPU
*cpu
)
1180 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1181 State
.exe
= (PSW_F0
!= 0);
1182 trace_output_flag (sd
);
1187 OP_4E40 (SIM_DESC sd
, SIM_CPU
*cpu
)
1189 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1190 State
.exe
= (PSW_F1
== 0);
1191 trace_output_flag (sd
);
1196 OP_4E42 (SIM_DESC sd
, SIM_CPU
*cpu
)
1198 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1199 State
.exe
= (PSW_F1
!= 0);
1200 trace_output_flag (sd
);
1205 OP_4E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1207 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1208 State
.exe
= (PSW_F0
== 0) & (PSW_F1
== 0);
1209 trace_output_flag (sd
);
1214 OP_4E02 (SIM_DESC sd
, SIM_CPU
*cpu
)
1216 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1217 State
.exe
= (PSW_F0
== 0) & (PSW_F1
!= 0);
1218 trace_output_flag (sd
);
1223 OP_4E20 (SIM_DESC sd
, SIM_CPU
*cpu
)
1225 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1226 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
== 0);
1227 trace_output_flag (sd
);
1232 OP_4E22 (SIM_DESC sd
, SIM_CPU
*cpu
)
1234 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1235 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
!= 0);
1236 trace_output_flag (sd
);
1241 OP_15002A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1246 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1247 if (((int16_t)GPR (OP
[1])) >= 0)
1248 tmp
= (GPR (OP
[1]) << 16) | GPR (OP
[1] + 1);
1250 tmp
= ~((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
1257 SET_GPR (OP
[0], (i
- 1));
1258 trace_output_16 (sd
, i
- 1);
1263 SET_GPR (OP
[0], 16);
1264 trace_output_16 (sd
, 16);
1269 OP_15002A02 (SIM_DESC sd
, SIM_CPU
*cpu
)
1274 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1275 tmp
= SEXT40(ACC (OP
[1]));
1277 tmp
= ~tmp
& MASK40
;
1279 foo
= 0x4000000000LL
;
1284 SET_GPR (OP
[0], i
- 9);
1285 trace_output_16 (sd
, i
- 9);
1290 SET_GPR (OP
[0], 16);
1291 trace_output_16 (sd
, 16);
1296 OP_4D00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1298 trace_input ("jl", OP_REG
, OP_R0
, OP_R1
);
1299 SET_GPR (13, PC
+ 1);
1301 trace_output_void (sd
);
1306 OP_4C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1308 trace_input ("jmp", OP_REG
,
1309 (OP
[0] == 13) ? OP_R0
: OP_VOID
,
1310 (OP
[0] == 13) ? OP_R1
: OP_VOID
);
1313 trace_output_void (sd
);
1318 OP_30000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1321 uint16_t addr
= OP
[1] + GPR (OP
[2]);
1322 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1325 trace_output_void (sd
);
1326 EXCEPTION (SIM_SIGBUS
);
1329 SET_GPR (OP
[0], tmp
);
1330 trace_output_16 (sd
, tmp
);
1335 OP_6401 (SIM_DESC sd
, SIM_CPU
*cpu
)
1338 uint16_t addr
= GPR (OP
[1]);
1339 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1342 trace_output_void (sd
);
1343 EXCEPTION (SIM_SIGBUS
);
1346 SET_GPR (OP
[0], tmp
);
1348 INC_ADDR (OP
[1], -2);
1349 trace_output_16 (sd
, tmp
);
1354 OP_6001 (SIM_DESC sd
, SIM_CPU
*cpu
)
1357 uint16_t addr
= GPR (OP
[1]);
1358 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1361 trace_output_void (sd
);
1362 EXCEPTION (SIM_SIGBUS
);
1365 SET_GPR (OP
[0], tmp
);
1367 INC_ADDR (OP
[1], 2);
1368 trace_output_16 (sd
, tmp
);
1373 OP_6000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1376 uint16_t addr
= GPR (OP
[1]);
1377 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1380 trace_output_void (sd
);
1381 EXCEPTION (SIM_SIGBUS
);
1384 SET_GPR (OP
[0], tmp
);
1385 trace_output_16 (sd
, tmp
);
1390 OP_32010000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1393 uint16_t addr
= OP
[1];
1394 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1397 trace_output_void (sd
);
1398 EXCEPTION (SIM_SIGBUS
);
1401 SET_GPR (OP
[0], tmp
);
1402 trace_output_16 (sd
, tmp
);
1407 OP_31000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1410 uint16_t addr
= OP
[1] + GPR (OP
[2]);
1411 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1414 trace_output_void (sd
);
1415 EXCEPTION (SIM_SIGBUS
);
1418 SET_GPR32 (OP
[0], tmp
);
1419 trace_output_32 (sd
, tmp
);
1424 OP_6601 (SIM_DESC sd
, SIM_CPU
*cpu
)
1426 uint16_t addr
= GPR (OP
[1]);
1428 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1431 trace_output_void (sd
);
1432 EXCEPTION (SIM_SIGBUS
);
1435 SET_GPR32 (OP
[0], tmp
);
1436 if (OP
[0] != OP
[1] && ((OP
[0] + 1) != OP
[1]))
1437 INC_ADDR (OP
[1], -4);
1438 trace_output_32 (sd
, tmp
);
1443 OP_6201 (SIM_DESC sd
, SIM_CPU
*cpu
)
1446 uint16_t addr
= GPR (OP
[1]);
1447 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1450 trace_output_void (sd
);
1451 EXCEPTION (SIM_SIGBUS
);
1454 SET_GPR32 (OP
[0], tmp
);
1455 if (OP
[0] != OP
[1] && ((OP
[0] + 1) != OP
[1]))
1456 INC_ADDR (OP
[1], 4);
1457 trace_output_32 (sd
, tmp
);
1462 OP_6200 (SIM_DESC sd
, SIM_CPU
*cpu
)
1464 uint16_t addr
= GPR (OP
[1]);
1466 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1469 trace_output_void (sd
);
1470 EXCEPTION (SIM_SIGBUS
);
1473 SET_GPR32 (OP
[0], tmp
);
1474 trace_output_32 (sd
, tmp
);
1479 OP_33010000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1482 uint16_t addr
= OP
[1];
1483 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1486 trace_output_void (sd
);
1487 EXCEPTION (SIM_SIGBUS
);
1490 SET_GPR32 (OP
[0], tmp
);
1491 trace_output_32 (sd
, tmp
);
1496 OP_38000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1499 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1500 tmp
= SEXT8 (RB (OP
[1] + GPR (OP
[2])));
1501 SET_GPR (OP
[0], tmp
);
1502 trace_output_16 (sd
, tmp
);
1507 OP_7000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1510 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1511 tmp
= SEXT8 (RB (GPR (OP
[1])));
1512 SET_GPR (OP
[0], tmp
);
1513 trace_output_16 (sd
, tmp
);
1518 OP_4001 (SIM_DESC sd
, SIM_CPU
*cpu
)
1521 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1522 tmp
= SEXT4 (OP
[1]);
1523 SET_GPR (OP
[0], tmp
);
1524 trace_output_16 (sd
, tmp
);
1529 OP_20000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1532 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1534 SET_GPR (OP
[0], tmp
);
1535 trace_output_16 (sd
, tmp
);
1540 OP_39000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1543 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1544 tmp
= RB (OP
[1] + GPR (OP
[2]));
1545 SET_GPR (OP
[0], tmp
);
1546 trace_output_16 (sd
, tmp
);
1551 OP_7200 (SIM_DESC sd
, SIM_CPU
*cpu
)
1554 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1555 tmp
= RB (GPR (OP
[1]));
1556 SET_GPR (OP
[0], tmp
);
1557 trace_output_16 (sd
, tmp
);
1562 OP_2A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1566 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1567 tmp
= SEXT40 ((int16_t)(GPR (OP
[1])) * (int16_t)(GPR (OP
[2])));
1570 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1572 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1575 tmp
+= SEXT40 (ACC (OP
[0]));
1578 if (tmp
> SEXT40(MAX32
))
1580 else if (tmp
< SEXT40(MIN32
))
1583 tmp
= (tmp
& MASK40
);
1586 tmp
= (tmp
& MASK40
);
1587 SET_ACC (OP
[0], tmp
);
1588 trace_output_40 (sd
, tmp
);
1593 OP_1A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1597 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1598 tmp
= SEXT40 ((int16_t) GPR (OP
[1]) * GPR (OP
[2]));
1600 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1601 tmp
= ((SEXT40 (ACC (OP
[0])) + tmp
) & MASK40
);
1602 SET_ACC (OP
[0], tmp
);
1603 trace_output_40 (sd
, tmp
);
1608 OP_3A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1614 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1615 src1
= (uint16_t) GPR (OP
[1]);
1616 src2
= (uint16_t) GPR (OP
[2]);
1620 tmp
= ((ACC (OP
[0]) + tmp
) & MASK40
);
1621 SET_ACC (OP
[0], tmp
);
1622 trace_output_40 (sd
, tmp
);
1627 OP_2600 (SIM_DESC sd
, SIM_CPU
*cpu
)
1630 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1631 SET_PSW_F1 (PSW_F0
);
1632 if ((int16_t) GPR (OP
[1]) > (int16_t)GPR (OP
[0]))
1642 SET_GPR (OP
[0], tmp
);
1643 trace_output_16 (sd
, tmp
);
1648 OP_3600 (SIM_DESC sd
, SIM_CPU
*cpu
)
1652 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1653 SET_PSW_F1 (PSW_F0
);
1654 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1655 if (tmp
> SEXT40 (ACC (OP
[0])))
1657 tmp
= (tmp
& MASK40
);
1665 SET_ACC (OP
[0], tmp
);
1666 trace_output_40 (sd
, tmp
);
1671 OP_3602 (SIM_DESC sd
, SIM_CPU
*cpu
)
1674 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1675 SET_PSW_F1 (PSW_F0
);
1676 if (SEXT40 (ACC (OP
[1])) > SEXT40 (ACC (OP
[0])))
1686 SET_ACC (OP
[0], tmp
);
1687 trace_output_40 (sd
, tmp
);
1693 OP_2601 (SIM_DESC sd
, SIM_CPU
*cpu
)
1696 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1697 SET_PSW_F1 (PSW_F0
);
1698 if ((int16_t)GPR (OP
[1]) < (int16_t)GPR (OP
[0]))
1708 SET_GPR (OP
[0], tmp
);
1709 trace_output_16 (sd
, tmp
);
1714 OP_3601 (SIM_DESC sd
, SIM_CPU
*cpu
)
1718 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1719 SET_PSW_F1 (PSW_F0
);
1720 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1721 if (tmp
< SEXT40(ACC (OP
[0])))
1723 tmp
= (tmp
& MASK40
);
1731 SET_ACC (OP
[0], tmp
);
1732 trace_output_40 (sd
, tmp
);
1737 OP_3603 (SIM_DESC sd
, SIM_CPU
*cpu
)
1740 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1741 SET_PSW_F1 (PSW_F0
);
1742 if (SEXT40(ACC (OP
[1])) < SEXT40(ACC (OP
[0])))
1752 SET_ACC (OP
[0], tmp
);
1753 trace_output_40 (sd
, tmp
);
1758 OP_2800 (SIM_DESC sd
, SIM_CPU
*cpu
)
1762 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1763 tmp
= SEXT40 ((int16_t)(GPR (OP
[1])) * (int16_t)(GPR (OP
[2])));
1766 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1768 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1771 tmp
= SEXT40(ACC (OP
[0])) - tmp
;
1774 if (tmp
> SEXT40(MAX32
))
1776 else if (tmp
< SEXT40(MIN32
))
1779 tmp
= (tmp
& MASK40
);
1783 tmp
= (tmp
& MASK40
);
1785 SET_ACC (OP
[0], tmp
);
1786 trace_output_40 (sd
, tmp
);
1791 OP_1800 (SIM_DESC sd
, SIM_CPU
*cpu
)
1795 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1796 tmp
= SEXT40 ((int16_t)GPR (OP
[1]) * GPR (OP
[2]));
1798 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1799 tmp
= ((SEXT40 (ACC (OP
[0])) - tmp
) & MASK40
);
1800 SET_ACC (OP
[0], tmp
);
1801 trace_output_40 (sd
, tmp
);
1806 OP_3800 (SIM_DESC sd
, SIM_CPU
*cpu
)
1812 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1813 src1
= (uint16_t) GPR (OP
[1]);
1814 src2
= (uint16_t) GPR (OP
[2]);
1818 tmp
= ((ACC (OP
[0]) - tmp
) & MASK40
);
1819 SET_ACC (OP
[0], tmp
);
1820 trace_output_40 (sd
, tmp
);
1825 OP_2E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1828 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1829 tmp
= GPR (OP
[0]) * GPR (OP
[1]);
1830 SET_GPR (OP
[0], tmp
);
1831 trace_output_16 (sd
, tmp
);
1836 OP_2C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1840 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1841 tmp
= SEXT40 ((int16_t)(GPR (OP
[1])) * (int16_t)(GPR (OP
[2])));
1844 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1846 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1849 tmp
= (tmp
& MASK40
);
1850 SET_ACC (OP
[0], tmp
);
1851 trace_output_40 (sd
, tmp
);
1856 OP_1C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1860 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1861 tmp
= SEXT40 ((int16_t)(GPR (OP
[1])) * GPR (OP
[2]));
1865 tmp
= (tmp
& MASK40
);
1866 SET_ACC (OP
[0], tmp
);
1867 trace_output_40 (sd
, tmp
);
1872 OP_3C00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1878 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1879 src1
= (uint16_t) GPR (OP
[1]);
1880 src2
= (uint16_t) GPR (OP
[2]);
1884 tmp
= (tmp
& MASK40
);
1885 SET_ACC (OP
[0], tmp
);
1886 trace_output_40 (sd
, tmp
);
1891 OP_4000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1894 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1896 SET_GPR (OP
[0], tmp
);
1897 trace_output_16 (sd
, tmp
);
1902 OP_5000 (SIM_DESC sd
, SIM_CPU
*cpu
)
1905 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1906 tmp
= GPR32 (OP
[1]);
1907 SET_GPR32 (OP
[0], tmp
);
1908 trace_output_32 (sd
, tmp
);
1913 OP_3E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
1916 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1918 SET_GPR32 (OP
[0], tmp
);
1919 trace_output_32 (sd
, tmp
);
1924 OP_3E01 (SIM_DESC sd
, SIM_CPU
*cpu
)
1927 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1928 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1)) & MASK40
);
1929 SET_ACC (OP
[1], tmp
);
1930 trace_output_40 (sd
, tmp
);
1935 OP_3E03 (SIM_DESC sd
, SIM_CPU
*cpu
)
1938 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1940 SET_ACC (OP
[0], tmp
);
1941 trace_output_40 (sd
, tmp
);
1946 OP_5400 (SIM_DESC sd
, SIM_CPU
*cpu
)
1949 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1950 tmp
= SEXT8 (GPR (OP
[1]) & 0xff);
1951 SET_GPR (OP
[0], tmp
);
1952 trace_output_16 (sd
, tmp
);
1957 OP_4400 (SIM_DESC sd
, SIM_CPU
*cpu
)
1960 trace_input ("mvf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1964 SET_GPR (OP
[0], tmp
);
1968 trace_output_16 (sd
, tmp
);
1973 OP_4401 (SIM_DESC sd
, SIM_CPU
*cpu
)
1976 trace_input ("mvf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1980 SET_GPR (OP
[0], tmp
);
1984 trace_output_16 (sd
, tmp
);
1989 OP_1E04 (SIM_DESC sd
, SIM_CPU
*cpu
)
1992 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1993 tmp
= ((ACC (OP
[1]) >> 32) & 0xff);
1994 SET_GPR (OP
[0], tmp
);
1995 trace_output_16 (sd
, tmp
);
2000 OP_1E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
2003 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2004 tmp
= (ACC (OP
[1]) >> 16);
2005 SET_GPR (OP
[0], tmp
);
2006 trace_output_16 (sd
, tmp
);
2011 OP_1E02 (SIM_DESC sd
, SIM_CPU
*cpu
)
2014 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2016 SET_GPR (OP
[0], tmp
);
2017 trace_output_16 (sd
, tmp
);
2022 OP_5200 (SIM_DESC sd
, SIM_CPU
*cpu
)
2025 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
2027 SET_GPR (OP
[0], tmp
);
2028 trace_output_16 (sd
, tmp
);
2033 OP_1E41 (SIM_DESC sd
, SIM_CPU
*cpu
)
2036 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
2037 tmp
= ((ACC (OP
[1]) & MASK32
)
2038 | ((int64_t)(GPR (OP
[0]) & 0xff) << 32));
2039 SET_ACC (OP
[1], tmp
);
2040 trace_output_40 (sd
, tmp
);
2045 OP_1E01 (SIM_DESC sd
, SIM_CPU
*cpu
)
2048 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
2049 tmp
= ACC (OP
[1]) & 0xffff;
2050 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | tmp
) & MASK40
);
2051 SET_ACC (OP
[1], tmp
);
2052 trace_output_40 (sd
, tmp
);
2057 OP_1E21 (SIM_DESC sd
, SIM_CPU
*cpu
)
2060 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
2061 tmp
= ((SEXT16 (GPR (OP
[0]))) & MASK40
);
2062 SET_ACC (OP
[1], tmp
);
2063 trace_output_40 (sd
, tmp
);
2068 OP_5600 (SIM_DESC sd
, SIM_CPU
*cpu
)
2071 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
2073 tmp
= SET_CREG (OP
[1], tmp
);
2074 trace_output_16 (sd
, tmp
);
2079 OP_5401 (SIM_DESC sd
, SIM_CPU
*cpu
)
2082 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
2083 tmp
= (GPR (OP
[1]) & 0xff);
2084 SET_GPR (OP
[0], tmp
);
2085 trace_output_16 (sd
, tmp
);
2090 OP_4605 (SIM_DESC sd
, SIM_CPU
*cpu
)
2093 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
2094 tmp
= - GPR (OP
[0]);
2095 SET_GPR (OP
[0], tmp
);
2096 trace_output_16 (sd
, tmp
);
2101 OP_5605 (SIM_DESC sd
, SIM_CPU
*cpu
)
2105 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
2106 tmp
= -SEXT40(ACC (OP
[0]));
2109 if (tmp
> SEXT40(MAX32
))
2111 else if (tmp
< SEXT40(MIN32
))
2114 tmp
= (tmp
& MASK40
);
2117 tmp
= (tmp
& MASK40
);
2118 SET_ACC (OP
[0], tmp
);
2119 trace_output_40 (sd
, tmp
);
2125 OP_5E00 (SIM_DESC sd
, SIM_CPU
*cpu
)
2127 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
2129 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
2130 switch (State
.ins_type
)
2133 ins_type_counters
[ (int)INS_UNKNOWN
]++;
2136 case INS_LEFT_PARALLEL
:
2137 /* Don't count a parallel op that includes a NOP as a true parallel op */
2138 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
2139 ins_type_counters
[ (int)INS_RIGHT
]++;
2140 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2144 case INS_LEFT_COND_EXE
:
2145 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2148 case INS_RIGHT_PARALLEL
:
2149 /* Don't count a parallel op that includes a NOP as a true parallel op */
2150 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
2151 ins_type_counters
[ (int)INS_LEFT
]++;
2152 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2156 case INS_RIGHT_COND_EXE
:
2157 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2161 trace_output_void (sd
);
2166 OP_4603 (SIM_DESC sd
, SIM_CPU
*cpu
)
2169 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
2171 SET_GPR (OP
[0], tmp
);
2172 trace_output_16 (sd
, tmp
);
2177 OP_800 (SIM_DESC sd
, SIM_CPU
*cpu
)
2180 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
2181 tmp
= (GPR (OP
[0]) | GPR (OP
[1]));
2182 SET_GPR (OP
[0], tmp
);
2183 trace_output_16 (sd
, tmp
);
2188 OP_4000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2191 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2192 tmp
= (GPR (OP
[1]) | OP
[2]);
2193 SET_GPR (OP
[0], tmp
);
2194 trace_output_16 (sd
, tmp
);
2199 OP_5201 (SIM_DESC sd
, SIM_CPU
*cpu
)
2202 int shift
= SEXT3 (OP
[2]);
2204 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2208 "ERROR at PC 0x%x: instruction only valid for A0\n",
2210 EXCEPTION (SIM_SIGILL
);
2213 SET_PSW_F1 (PSW_F0
);
2214 tmp
= SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2220 tmp
>>= 16; /* look at bits 0:43 */
2221 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2226 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2235 SET_GPR32 (OP
[0], tmp
);
2236 trace_output_32 (sd
, tmp
);
2241 OP_4201 (SIM_DESC sd
, SIM_CPU
*cpu
)
2244 int shift
= SEXT3 (OP
[2]);
2246 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2247 SET_PSW_F1 (PSW_F0
);
2249 tmp
= SEXT40 (ACC (OP
[1])) << shift
;
2251 tmp
= SEXT40 (ACC (OP
[1])) >> -shift
;
2254 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2259 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2269 SET_GPR (OP
[0], tmp
);
2270 trace_output_16 (sd
, tmp
);
2275 OP_27000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2277 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2279 SET_RPT_E (PC
+ OP
[1]);
2280 SET_RPT_C (GPR (OP
[0]));
2282 if (GPR (OP
[0]) == 0)
2284 sim_io_printf (sd
, "ERROR: rep with count=0 is illegal.\n");
2285 EXCEPTION (SIM_SIGILL
);
2289 sim_io_printf (sd
, "ERROR: rep must include at least 4 instructions.\n");
2290 EXCEPTION (SIM_SIGILL
);
2292 trace_output_void (sd
);
2297 OP_2F000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2299 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2301 SET_RPT_E (PC
+ OP
[1]);
2306 sim_io_printf (sd
, "ERROR: repi with count=0 is illegal.\n");
2307 EXCEPTION (SIM_SIGILL
);
2311 sim_io_printf (sd
, "ERROR: repi must include at least 4 instructions.\n");
2312 EXCEPTION (SIM_SIGILL
);
2314 trace_output_void (sd
);
2319 OP_5F60 (SIM_DESC sd
, SIM_CPU
*cpu
)
2321 trace_input ("rtd", OP_VOID
, OP_VOID
, OP_VOID
);
2322 SET_CREG (PSW_CR
, DPSW
);
2324 trace_output_void (sd
);
2329 OP_5F40 (SIM_DESC sd
, SIM_CPU
*cpu
)
2331 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2332 SET_CREG (PSW_CR
, BPSW
);
2334 trace_output_void (sd
);
2338 void OP_5209 (SIM_DESC sd
, SIM_CPU
*cpu
)
2342 trace_input ("sac", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2344 tmp
= SEXT40(ACC (OP
[1]));
2346 SET_PSW_F1 (PSW_F0
);
2348 if (tmp
> SEXT40(MAX32
))
2353 else if (tmp
< SEXT40(MIN32
))
2360 tmp
= (tmp
& MASK32
);
2364 SET_GPR32 (OP
[0], tmp
);
2366 trace_output_40 (sd
, tmp
);
2371 OP_4209 (SIM_DESC sd
, SIM_CPU
*cpu
)
2375 trace_input ("sachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2377 tmp
= SEXT40(ACC (OP
[1]));
2379 SET_PSW_F1 (PSW_F0
);
2381 if (tmp
> SEXT40(MAX32
))
2386 else if (tmp
< SEXT40(MIN32
))
2397 SET_GPR (OP
[0], tmp
);
2399 trace_output_16 (sd
, OP
[0]);
2404 OP_1223 (SIM_DESC sd
, SIM_CPU
*cpu
)
2408 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2409 tmp
= SEXT40(ACC (OP
[0])) + (SEXT40(ACC (OP
[1])) >> 16);
2412 if (tmp
> SEXT40(MAX32
))
2414 else if (tmp
< SEXT40(MIN32
))
2417 tmp
= (tmp
& MASK40
);
2420 tmp
= (tmp
& MASK40
);
2421 SET_ACC (OP
[0], tmp
);
2422 trace_output_40 (sd
, tmp
);
2427 OP_4611 (SIM_DESC sd
, SIM_CPU
*cpu
)
2430 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2431 tmp
= ((PSW_F0
== 0) ? 1 : 0);
2432 SET_GPR (OP
[0], tmp
);
2433 trace_output_16 (sd
, tmp
);
2438 OP_4613 (SIM_DESC sd
, SIM_CPU
*cpu
)
2441 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2442 tmp
= ((PSW_F0
== 1) ? 1 : 0);
2443 SET_GPR (OP
[0], tmp
);
2444 trace_output_16 (sd
, tmp
);
2449 OP_3220 (SIM_DESC sd
, SIM_CPU
*cpu
)
2454 trace_input ("slae", OP_ACCUM
, OP_REG
, OP_VOID
);
2456 reg
= SEXT16 (GPR (OP
[1]));
2458 if (reg
>= 17 || reg
<= -17)
2460 sim_io_printf (sd
, "ERROR: shift value %d too large.\n", reg
);
2461 EXCEPTION (SIM_SIGILL
);
2464 tmp
= SEXT40 (ACC (OP
[0]));
2466 if (PSW_ST
&& (tmp
< SEXT40 (MIN32
) || tmp
> SEXT40 (MAX32
)))
2468 sim_io_printf (sd
, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp
>> 32) & 0xff), ((unsigned long) tmp
) & 0xffffffff);
2469 EXCEPTION (SIM_SIGILL
);
2472 if (reg
>= 0 && reg
<= 16)
2474 tmp
= SEXT56 ((SEXT56 (tmp
)) << (GPR (OP
[1])));
2477 if (tmp
> SEXT40(MAX32
))
2479 else if (tmp
< SEXT40(MIN32
))
2482 tmp
= (tmp
& MASK40
);
2485 tmp
= (tmp
& MASK40
);
2489 tmp
= (SEXT40 (ACC (OP
[0]))) >> (-GPR (OP
[1]));
2492 SET_ACC(OP
[0], tmp
);
2494 trace_output_40 (sd
, tmp
);
2499 OP_5FC0 (SIM_DESC sd
, SIM_CPU
*cpu
)
2501 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2503 trace_output_void (sd
);
2508 OP_2200 (SIM_DESC sd
, SIM_CPU
*cpu
)
2511 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2512 tmp
= (GPR (OP
[0]) << (GPR (OP
[1]) & 0xf));
2513 SET_GPR (OP
[0], tmp
);
2514 trace_output_16 (sd
, tmp
);
2519 OP_3200 (SIM_DESC sd
, SIM_CPU
*cpu
)
2522 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2523 if ((GPR (OP
[1]) & 31) <= 16)
2524 tmp
= SEXT40 (ACC (OP
[0])) << (GPR (OP
[1]) & 31);
2527 sim_io_printf (sd
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2528 EXCEPTION (SIM_SIGILL
);
2533 if (tmp
> SEXT40(MAX32
))
2535 else if (tmp
< SEXT40(MIN32
))
2538 tmp
= (tmp
& MASK40
);
2541 tmp
= (tmp
& MASK40
);
2542 SET_ACC (OP
[0], tmp
);
2543 trace_output_40 (sd
, tmp
);
2548 OP_2201 (SIM_DESC sd
, SIM_CPU
*cpu
)
2551 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2552 tmp
= (GPR (OP
[0]) << OP
[1]);
2553 SET_GPR (OP
[0], tmp
);
2554 trace_output_16 (sd
, tmp
);
2559 OP_3201 (SIM_DESC sd
, SIM_CPU
*cpu
)
2566 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2567 tmp
= SEXT40(ACC (OP
[0])) << OP
[1];
2571 if (tmp
> SEXT40(MAX32
))
2573 else if (tmp
< SEXT40(MIN32
))
2576 tmp
= (tmp
& MASK40
);
2579 tmp
= (tmp
& MASK40
);
2580 SET_ACC (OP
[0], tmp
);
2581 trace_output_40 (sd
, tmp
);
2586 OP_460B (SIM_DESC sd
, SIM_CPU
*cpu
)
2589 trace_input ("slx", OP_REG
, OP_VOID
, OP_VOID
);
2590 tmp
= ((GPR (OP
[0]) << 1) | PSW_F0
);
2591 SET_GPR (OP
[0], tmp
);
2592 trace_output_16 (sd
, tmp
);
2597 OP_2400 (SIM_DESC sd
, SIM_CPU
*cpu
)
2600 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2601 tmp
= (((int16_t)(GPR (OP
[0]))) >> (GPR (OP
[1]) & 0xf));
2602 SET_GPR (OP
[0], tmp
);
2603 trace_output_16 (sd
, tmp
);
2608 OP_3400 (SIM_DESC sd
, SIM_CPU
*cpu
)
2610 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2611 if ((GPR (OP
[1]) & 31) <= 16)
2613 int64_t tmp
= ((SEXT40(ACC (OP
[0])) >> (GPR (OP
[1]) & 31)) & MASK40
);
2614 SET_ACC (OP
[0], tmp
);
2615 trace_output_40 (sd
, tmp
);
2619 sim_io_printf (sd
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2620 EXCEPTION (SIM_SIGILL
);
2626 OP_2401 (SIM_DESC sd
, SIM_CPU
*cpu
)
2629 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2630 tmp
= (((int16_t)(GPR (OP
[0]))) >> OP
[1]);
2631 SET_GPR (OP
[0], tmp
);
2632 trace_output_16 (sd
, tmp
);
2637 OP_3401 (SIM_DESC sd
, SIM_CPU
*cpu
)
2643 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2644 tmp
= ((SEXT40(ACC (OP
[0])) >> OP
[1]) & MASK40
);
2645 SET_ACC (OP
[0], tmp
);
2646 trace_output_40 (sd
, tmp
);
2651 OP_2000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2654 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2655 tmp
= (GPR (OP
[0]) >> (GPR (OP
[1]) & 0xf));
2656 SET_GPR (OP
[0], tmp
);
2657 trace_output_16 (sd
, tmp
);
2662 OP_3000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2664 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2665 if ((GPR (OP
[1]) & 31) <= 16)
2667 int64_t tmp
= ((uint64_t)((ACC (OP
[0]) & MASK40
) >> (GPR (OP
[1]) & 31)));
2668 SET_ACC (OP
[0], tmp
);
2669 trace_output_40 (sd
, tmp
);
2673 sim_io_printf (sd
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2674 EXCEPTION (SIM_SIGILL
);
2681 OP_2001 (SIM_DESC sd
, SIM_CPU
*cpu
)
2684 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2685 tmp
= (GPR (OP
[0]) >> OP
[1]);
2686 SET_GPR (OP
[0], tmp
);
2687 trace_output_16 (sd
, tmp
);
2692 OP_3001 (SIM_DESC sd
, SIM_CPU
*cpu
)
2698 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2699 tmp
= ((uint64_t)(ACC (OP
[0]) & MASK40
) >> OP
[1]);
2700 SET_ACC (OP
[0], tmp
);
2701 trace_output_40 (sd
, tmp
);
2706 OP_4609 (SIM_DESC sd
, SIM_CPU
*cpu
)
2709 trace_input ("srx", OP_REG
, OP_VOID
, OP_VOID
);
2711 tmp
= ((GPR (OP
[0]) >> 1) | tmp
);
2712 SET_GPR (OP
[0], tmp
);
2713 trace_output_16 (sd
, tmp
);
2718 OP_34000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2720 uint16_t addr
= OP
[1] + GPR (OP
[2]);
2721 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2724 trace_output_void (sd
);
2725 EXCEPTION (SIM_SIGBUS
);
2727 SW (addr
, GPR (OP
[0]));
2728 trace_output_void (sd
);
2733 OP_6800 (SIM_DESC sd
, SIM_CPU
*cpu
)
2735 uint16_t addr
= GPR (OP
[1]);
2736 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2739 trace_output_void (sd
);
2740 EXCEPTION (SIM_SIGBUS
);
2742 SW (addr
, GPR (OP
[0]));
2743 trace_output_void (sd
);
2749 OP_6C1F (SIM_DESC sd
, SIM_CPU
*cpu
)
2751 uint16_t addr
= GPR (OP
[1]) - 2;
2752 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2755 sim_io_printf (sd
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2756 EXCEPTION (SIM_SIGILL
);
2760 trace_output_void (sd
);
2761 EXCEPTION (SIM_SIGBUS
);
2763 SW (addr
, GPR (OP
[0]));
2764 SET_GPR (OP
[1], addr
);
2765 trace_output_void (sd
);
2770 OP_6801 (SIM_DESC sd
, SIM_CPU
*cpu
)
2772 uint16_t addr
= GPR (OP
[1]);
2773 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2776 trace_output_void (sd
);
2777 EXCEPTION (SIM_SIGBUS
);
2779 SW (addr
, GPR (OP
[0]));
2780 INC_ADDR (OP
[1], 2);
2781 trace_output_void (sd
);
2786 OP_6C01 (SIM_DESC sd
, SIM_CPU
*cpu
)
2788 uint16_t addr
= GPR (OP
[1]);
2789 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2792 sim_io_printf (sd
, "ERROR: cannot post-decrement register r15 (SP).\n");
2793 EXCEPTION (SIM_SIGILL
);
2797 trace_output_void (sd
);
2798 EXCEPTION (SIM_SIGBUS
);
2800 SW (addr
, GPR (OP
[0]));
2801 INC_ADDR (OP
[1], -2);
2802 trace_output_void (sd
);
2807 OP_36010000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2809 uint16_t addr
= OP
[1];
2810 trace_input ("st", OP_REG
, OP_MEMREF3
, OP_VOID
);
2813 trace_output_void (sd
);
2814 EXCEPTION (SIM_SIGBUS
);
2816 SW (addr
, GPR (OP
[0]));
2817 trace_output_void (sd
);
2822 OP_35000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2824 uint16_t addr
= GPR (OP
[2])+ OP
[1];
2825 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2828 trace_output_void (sd
);
2829 EXCEPTION (SIM_SIGBUS
);
2831 SW (addr
+ 0, GPR (OP
[0] + 0));
2832 SW (addr
+ 2, GPR (OP
[0] + 1));
2833 trace_output_void (sd
);
2838 OP_6A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
2840 uint16_t addr
= GPR (OP
[1]);
2841 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2844 trace_output_void (sd
);
2845 EXCEPTION (SIM_SIGBUS
);
2847 SW (addr
+ 0, GPR (OP
[0] + 0));
2848 SW (addr
+ 2, GPR (OP
[0] + 1));
2849 trace_output_void (sd
);
2854 OP_6E1F (SIM_DESC sd
, SIM_CPU
*cpu
)
2856 uint16_t addr
= GPR (OP
[1]) - 4;
2857 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2860 sim_io_printf (sd
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2861 EXCEPTION (SIM_SIGILL
);
2865 trace_output_void (sd
);
2866 EXCEPTION (SIM_SIGBUS
);
2868 SW (addr
+ 0, GPR (OP
[0] + 0));
2869 SW (addr
+ 2, GPR (OP
[0] + 1));
2870 SET_GPR (OP
[1], addr
);
2871 trace_output_void (sd
);
2876 OP_6A01 (SIM_DESC sd
, SIM_CPU
*cpu
)
2878 uint16_t addr
= GPR (OP
[1]);
2879 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2882 trace_output_void (sd
);
2883 EXCEPTION (SIM_SIGBUS
);
2885 SW (addr
+ 0, GPR (OP
[0] + 0));
2886 SW (addr
+ 2, GPR (OP
[0] + 1));
2887 INC_ADDR (OP
[1], 4);
2888 trace_output_void (sd
);
2893 OP_6E01 (SIM_DESC sd
, SIM_CPU
*cpu
)
2895 uint16_t addr
= GPR (OP
[1]);
2896 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2899 sim_io_printf (sd
, "ERROR: cannot post-decrement register r15 (SP).\n");
2900 EXCEPTION (SIM_SIGILL
);
2904 trace_output_void (sd
);
2905 EXCEPTION (SIM_SIGBUS
);
2907 SW (addr
+ 0, GPR (OP
[0] + 0));
2908 SW (addr
+ 2, GPR (OP
[0] + 1));
2909 INC_ADDR (OP
[1], -4);
2910 trace_output_void (sd
);
2915 OP_37010000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2917 uint16_t addr
= OP
[1];
2918 trace_input ("st2w", OP_DREG
, OP_MEMREF3
, OP_VOID
);
2921 trace_output_void (sd
);
2922 EXCEPTION (SIM_SIGBUS
);
2924 SW (addr
+ 0, GPR (OP
[0] + 0));
2925 SW (addr
+ 2, GPR (OP
[0] + 1));
2926 trace_output_void (sd
);
2931 OP_3C000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
2933 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2934 SB (GPR (OP
[2]) + OP
[1], GPR (OP
[0]));
2935 trace_output_void (sd
);
2940 OP_7800 (SIM_DESC sd
, SIM_CPU
*cpu
)
2942 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2943 SB (GPR (OP
[1]), GPR (OP
[0]));
2944 trace_output_void (sd
);
2949 OP_5FE0 (SIM_DESC sd
, SIM_CPU
*cpu
)
2951 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2952 trace_output_void (sd
);
2953 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_exited
, 0);
2958 OP_0 (SIM_DESC sd
, SIM_CPU
*cpu
)
2960 uint16_t a
= GPR (OP
[0]);
2961 uint16_t b
= GPR (OP
[1]);
2962 uint16_t tmp
= (a
- b
);
2963 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2964 /* see ../common/sim-alu.h for a more extensive discussion on how to
2965 compute the carry/overflow bits. */
2967 SET_GPR (OP
[0], tmp
);
2968 trace_output_16 (sd
, tmp
);
2973 OP_1001 (SIM_DESC sd
, SIM_CPU
*cpu
)
2977 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2978 tmp
= SEXT40(ACC (OP
[0])) - (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
2981 if (tmp
> SEXT40(MAX32
))
2983 else if (tmp
< SEXT40(MIN32
))
2986 tmp
= (tmp
& MASK40
);
2989 tmp
= (tmp
& MASK40
);
2990 SET_ACC (OP
[0], tmp
);
2992 trace_output_40 (sd
, tmp
);
2998 OP_1003 (SIM_DESC sd
, SIM_CPU
*cpu
)
3002 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
3003 tmp
= SEXT40(ACC (OP
[0])) - SEXT40(ACC (OP
[1]));
3006 if (tmp
> SEXT40(MAX32
))
3008 else if (tmp
< SEXT40(MIN32
))
3011 tmp
= (tmp
& MASK40
);
3014 tmp
= (tmp
& MASK40
);
3015 SET_ACC (OP
[0], tmp
);
3017 trace_output_40 (sd
, tmp
);
3022 OP_1000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3026 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
3027 a
= (uint32_t)((GPR (OP
[0]) << 16) | GPR (OP
[0] + 1));
3028 b
= (uint32_t)((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
3029 /* see ../common/sim-alu.h for a more extensive discussion on how to
3030 compute the carry/overflow bits */
3033 SET_GPR32 (OP
[0], tmp
);
3034 trace_output_32 (sd
, tmp
);
3039 OP_17000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3043 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3044 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40 (ACC (OP
[2]));
3045 SET_GPR32 (OP
[0], tmp
);
3046 trace_output_32 (sd
, tmp
);
3051 OP_17000002 (SIM_DESC sd
, SIM_CPU
*cpu
)
3055 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3056 tmp
= SEXT40 (ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
3057 SET_GPR32 (OP
[0], tmp
);
3058 trace_output_32 (sd
, tmp
);
3063 OP_17001000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3067 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3068 SET_PSW_F1 (PSW_F0
);
3069 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40(ACC (OP
[2]));
3070 if (tmp
> SEXT40(MAX32
))
3075 else if (tmp
< SEXT40(MIN32
))
3084 SET_GPR32 (OP
[0], tmp
);
3085 trace_output_32 (sd
, tmp
);
3090 OP_17001002 (SIM_DESC sd
, SIM_CPU
*cpu
)
3094 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3095 SET_PSW_F1 (PSW_F0
);
3096 tmp
= SEXT40(ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
3097 if (tmp
> SEXT40(MAX32
))
3102 else if (tmp
< SEXT40(MIN32
))
3111 SET_GPR32 (OP
[0], tmp
);
3112 trace_output_32 (sd
, tmp
);
3117 OP_1 (SIM_DESC sd
, SIM_CPU
*cpu
)
3123 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3124 /* see ../common/sim-alu.h for a more extensive discussion on how to
3125 compute the carry/overflow bits. */
3126 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3127 tmp
= ((unsigned)(uint16_t) GPR (OP
[0])
3128 + (unsigned)(uint16_t) ( - OP
[1]));
3129 SET_PSW_C (tmp
>= (1 << 16));
3130 SET_GPR (OP
[0], tmp
);
3131 trace_output_16 (sd
, tmp
);
3136 OP_5F00 (SIM_DESC sd
, SIM_CPU
*cpu
)
3138 host_callback
*cb
= STATE_CALLBACK (sd
);
3140 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
3141 trace_output_void (sd
);
3146 #if (DEBUG & DEBUG_TRAP) == 0
3148 uint16_t vec
= OP
[0] + TRAP_VECTOR_START
;
3151 SET_PSW (PSW
& PSW_SM_BIT
);
3155 #else /* if debugging use trap to print registers */
3158 static int first_time
= 1;
3163 sim_io_printf (sd
, "Trap # PC ");
3164 for (i
= 0; i
< 16; i
++)
3165 sim_io_printf (sd
, " %sr%d", (i
> 9) ? "" : " ", i
);
3166 sim_io_printf (sd
, " a0 a1 f0 f1 c\n");
3169 sim_io_printf (sd
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
3171 for (i
= 0; i
< 16; i
++)
3172 sim_io_printf (sd
, " %.4x", (int) GPR (i
));
3174 for (i
= 0; i
< 2; i
++)
3175 sim_io_printf (sd
, " %.2x%.8lx",
3176 ((int)(ACC (i
) >> 32) & 0xff),
3177 ((unsigned long) ACC (i
)) & 0xffffffff);
3179 sim_io_printf (sd
, " %d %d %d\n",
3180 PSW_F0
!= 0, PSW_F1
!= 0, PSW_C
!= 0);
3181 sim_io_flush_stdout (sd
);
3185 case 15: /* new system call trap */
3186 /* Trap 15 is used for simulating low-level I/O */
3188 uint32_t result
= 0;
3191 /* Registers passed to trap 0 */
3193 #define FUNC GPR (4) /* function number */
3194 #define PARM1 GPR (0) /* optional parm 1 */
3195 #define PARM2 GPR (1) /* optional parm 2 */
3196 #define PARM3 GPR (2) /* optional parm 3 */
3197 #define PARM4 GPR (3) /* optional parm 3 */
3199 /* Registers set by trap 0 */
3201 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3202 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3203 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3205 /* Turn a pointer in a register into a pointer into real memory. */
3207 #define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x)))
3211 #if !defined(__GO32__) && !defined(_WIN32)
3212 case TARGET_NEWLIB_D10V_SYS_fork
:
3213 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
3215 trace_output_16 (sd
, result
);
3219 case TARGET_NEWLIB_D10V_SYS_getpid
:
3220 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3222 trace_output_16 (sd
, result
);
3225 case TARGET_NEWLIB_D10V_SYS_kill
:
3226 trace_input ("<kill>", OP_R0
, OP_R1
, OP_VOID
);
3227 if (PARM1
== getpid ())
3229 trace_output_void (sd
);
3230 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, PARM2
);
3238 case 1: os_sig
= SIGHUP
; break;
3241 case 2: os_sig
= SIGINT
; break;
3244 case 3: os_sig
= SIGQUIT
; break;
3247 case 4: os_sig
= SIGILL
; break;
3250 case 5: os_sig
= SIGTRAP
; break;
3253 case 6: os_sig
= SIGABRT
; break;
3254 #elif defined(SIGIOT)
3255 case 6: os_sig
= SIGIOT
; break;
3258 case 7: os_sig
= SIGEMT
; break;
3261 case 8: os_sig
= SIGFPE
; break;
3264 case 9: os_sig
= SIGKILL
; break;
3267 case 10: os_sig
= SIGBUS
; break;
3270 case 11: os_sig
= SIGSEGV
; break;
3273 case 12: os_sig
= SIGSYS
; break;
3276 case 13: os_sig
= SIGPIPE
; break;
3279 case 14: os_sig
= SIGALRM
; break;
3282 case 15: os_sig
= SIGTERM
; break;
3285 case 16: os_sig
= SIGURG
; break;
3288 case 17: os_sig
= SIGSTOP
; break;
3291 case 18: os_sig
= SIGTSTP
; break;
3294 case 19: os_sig
= SIGCONT
; break;
3297 case 20: os_sig
= SIGCHLD
; break;
3298 #elif defined(SIGCLD)
3299 case 20: os_sig
= SIGCLD
; break;
3302 case 21: os_sig
= SIGTTIN
; break;
3305 case 22: os_sig
= SIGTTOU
; break;
3308 case 23: os_sig
= SIGIO
; break;
3309 #elif defined (SIGPOLL)
3310 case 23: os_sig
= SIGPOLL
; break;
3313 case 24: os_sig
= SIGXCPU
; break;
3316 case 25: os_sig
= SIGXFSZ
; break;
3319 case 26: os_sig
= SIGVTALRM
; break;
3322 case 27: os_sig
= SIGPROF
; break;
3325 case 28: os_sig
= SIGWINCH
; break;
3328 case 29: os_sig
= SIGLOST
; break;
3331 case 30: os_sig
= SIGUSR1
; break;
3334 case 31: os_sig
= SIGUSR2
; break;
3340 trace_output_void (sd
);
3341 sim_io_printf (sd
, "Unknown signal %d\n", PARM2
);
3342 sim_io_flush_stdout (sd
);
3343 EXCEPTION (SIM_SIGILL
);
3347 RETVAL (kill (PARM1
, PARM2
));
3348 trace_output_16 (sd
, result
);
3353 case TARGET_NEWLIB_D10V_SYS_execve
:
3354 trace_input ("<execve>", OP_R0
, OP_R1
, OP_R2
);
3355 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
3356 (char **)MEMPTR (PARM3
)));
3357 trace_output_16 (sd
, result
);
3360 case TARGET_NEWLIB_D10V_SYS_execv
:
3361 trace_input ("<execv>", OP_R0
, OP_R1
, OP_VOID
);
3362 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
));
3363 trace_output_16 (sd
, result
);
3366 case TARGET_NEWLIB_D10V_SYS_pipe
:
3371 trace_input ("<pipe>", OP_R0
, OP_VOID
, OP_VOID
);
3373 RETVAL (pipe (host_fd
));
3374 SW (buf
, host_fd
[0]);
3375 buf
+= sizeof(uint16_t);
3376 SW (buf
, host_fd
[1]);
3377 trace_output_16 (sd
, result
);
3382 case TARGET_NEWLIB_D10V_SYS_wait
:
3385 trace_input ("<wait>", OP_R0
, OP_VOID
, OP_VOID
);
3386 RETVAL (wait (&status
));
3389 trace_output_16 (sd
, result
);
3394 case TARGET_NEWLIB_D10V_SYS_getpid
:
3395 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3397 trace_output_16 (sd
, result
);
3400 case TARGET_NEWLIB_D10V_SYS_kill
:
3401 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
3402 trace_output_void (sd
);
3403 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, PARM2
);
3407 case TARGET_NEWLIB_D10V_SYS_read
:
3408 trace_input ("<read>", OP_R0
, OP_R1
, OP_R2
);
3409 RETVAL (cb
->read (cb
, PARM1
, MEMPTR (PARM2
), PARM3
));
3410 trace_output_16 (sd
, result
);
3413 case TARGET_NEWLIB_D10V_SYS_write
:
3414 trace_input ("<write>", OP_R0
, OP_R1
, OP_R2
);
3416 RETVAL ((int)cb
->write_stdout (cb
, MEMPTR (PARM2
), PARM3
));
3418 RETVAL ((int)cb
->write (cb
, PARM1
, MEMPTR (PARM2
), PARM3
));
3419 trace_output_16 (sd
, result
);
3422 case TARGET_NEWLIB_D10V_SYS_lseek
:
3423 trace_input ("<lseek>", OP_R0
, OP_R1
, OP_R2
);
3424 RETVAL32 (cb
->lseek (cb
, PARM1
,
3425 ((((unsigned long) PARM2
) << 16)
3426 || (unsigned long) PARM3
),
3428 trace_output_32 (sd
, result
);
3431 case TARGET_NEWLIB_D10V_SYS_close
:
3432 trace_input ("<close>", OP_R0
, OP_VOID
, OP_VOID
);
3433 RETVAL (cb
->close (cb
, PARM1
));
3434 trace_output_16 (sd
, result
);
3437 case TARGET_NEWLIB_D10V_SYS_open
:
3438 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
3439 RETVAL (cb
->open (cb
, MEMPTR (PARM1
), PARM2
));
3440 trace_output_16 (sd
, result
);
3443 case TARGET_NEWLIB_D10V_SYS_exit
:
3444 trace_input ("<exit>", OP_R0
, OP_VOID
, OP_VOID
);
3445 trace_output_void (sd
);
3446 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_exited
, GPR (0));
3449 case TARGET_NEWLIB_D10V_SYS_stat
:
3450 trace_input ("<stat>", OP_R0
, OP_R1
, OP_VOID
);
3451 /* stat system call */
3453 struct stat host_stat
;
3456 RETVAL (stat (MEMPTR (PARM1
), &host_stat
));
3460 /* The hard-coded offsets and sizes were determined by using
3461 * the D10V compiler on a test program that used struct stat.
3463 SW (buf
, host_stat
.st_dev
);
3464 SW (buf
+2, host_stat
.st_ino
);
3465 SW (buf
+4, host_stat
.st_mode
);
3466 SW (buf
+6, host_stat
.st_nlink
);
3467 SW (buf
+8, host_stat
.st_uid
);
3468 SW (buf
+10, host_stat
.st_gid
);
3469 SW (buf
+12, host_stat
.st_rdev
);
3470 SLW (buf
+16, host_stat
.st_size
);
3471 SLW (buf
+20, host_stat
.st_atime
);
3472 SLW (buf
+28, host_stat
.st_mtime
);
3473 SLW (buf
+36, host_stat
.st_ctime
);
3475 trace_output_16 (sd
, result
);
3478 case TARGET_NEWLIB_D10V_SYS_chown
:
3479 trace_input ("<chown>", OP_R0
, OP_R1
, OP_R2
);
3480 RETVAL (chown (MEMPTR (PARM1
), PARM2
, PARM3
));
3481 trace_output_16 (sd
, result
);
3484 case TARGET_NEWLIB_D10V_SYS_chmod
:
3485 trace_input ("<chmod>", OP_R0
, OP_R1
, OP_R2
);
3486 RETVAL (chmod (MEMPTR (PARM1
), PARM2
));
3487 trace_output_16 (sd
, result
);
3491 case TARGET_NEWLIB_D10V_SYS_utime
:
3492 trace_input ("<utime>", OP_R0
, OP_R1
, OP_R2
);
3493 /* Cast the second argument to void *, to avoid type mismatch
3494 if a prototype is present. */
3495 RETVAL (utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
)));
3496 trace_output_16 (sd
, result
);
3501 case TARGET_NEWLIB_D10V_SYS_time
:
3502 trace_input ("<time>", OP_R0
, OP_R1
, OP_R2
);
3503 RETVAL32 (time (PARM1
? MEMPTR (PARM1
) : NULL
));
3504 trace_output_32 (sd
, result
);
3509 cb
->error (cb
, "Unknown syscall %d", FUNC
);
3511 if ((uint16_t) result
== (uint16_t) -1)
3512 RETERR (cb
->get_errno (cb
));
3522 OP_7000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3524 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3525 SET_PSW_F1 (PSW_F0
);;
3526 SET_PSW_F0 ((GPR (OP
[0]) & OP
[1]) ? 1 : 0);
3527 trace_output_flag (sd
);
3532 OP_F000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3534 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3535 SET_PSW_F1 (PSW_F0
);
3536 SET_PSW_F0 ((~(GPR (OP
[0])) & OP
[1]) ? 1 : 0);
3537 trace_output_flag (sd
);
3542 OP_5F80 (SIM_DESC sd
, SIM_CPU
*cpu
)
3544 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3546 trace_output_void (sd
);
3551 OP_A00 (SIM_DESC sd
, SIM_CPU
*cpu
)
3554 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3555 tmp
= (GPR (OP
[0]) ^ GPR (OP
[1]));
3556 SET_GPR (OP
[0], tmp
);
3557 trace_output_16 (sd
, tmp
);
3562 OP_5000000 (SIM_DESC sd
, SIM_CPU
*cpu
)
3565 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3566 tmp
= (GPR (OP
[1]) ^ OP
[2]);
3567 SET_GPR (OP
[0], tmp
);
3568 trace_output_16 (sd
, tmp
);