sim/bfin/dv-bfin_pll.c

   1 /* Blackfin Phase Lock Loop (PLL) model.
   2
   3    Copyright (C) 2010-2024 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25 #include "devices.h"
  26 #include "dv-bfin_pll.h"
  27
  28 struct bfin_pll
  29 {
  30   bu32 base;
  31
  32   /* Order after here is important -- matches hardware MMR layout.  */
  33   bu16 BFIN_MMR_16(pll_ctl);
  34   bu16 BFIN_MMR_16(pll_div);
  35   bu16 BFIN_MMR_16(vr_ctl);
  36   bu16 BFIN_MMR_16(pll_stat);
  37   bu16 BFIN_MMR_16(pll_lockcnt);
  38
  39   /* XXX: Not really the best place for this ...  */
  40   bu32 chipid;
  41 };
  42 #define mmr_base()      offsetof(struct bfin_pll, pll_ctl)
  43 #define mmr_offset(mmr) (offsetof(struct bfin_pll, mmr) - mmr_base())
  44
  45 static const char * const mmr_names[] =
  46 {
  47   "PLL_CTL", "PLL_DIV", "VR_CTL", "PLL_STAT", "PLL_LOCKCNT", "CHIPID",
  48 };
  49 #define mmr_name(off) mmr_names[(off) / 4]
  50
  51 static unsigned
  52 bfin_pll_io_write_buffer (struct hw *me, const void *source,
  53                           int space, address_word addr, unsigned nr_bytes)
  54 {
  55   struct bfin_pll *pll = hw_data (me);
  56   bu32 mmr_off;
  57   bu32 value;
  58   bu16 *value16p;
  59   void *valuep;
  60
  61   /* Invalid access mode is higher priority than missing register.  */
  62   if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
  63     return 0;
  64
  65   if (nr_bytes == 4)
  66     value = dv_load_4 (source);
  67   else
  68     value = dv_load_2 (source);
  69
  70   mmr_off = addr - pll->base;
  71   valuep = (void *)((uintptr_t)pll + mmr_base() + mmr_off);
  72   value16p = valuep;
  73
  74   HW_TRACE_WRITE ();
  75
  76   switch (mmr_off)
  77     {
  78     case mmr_offset(pll_stat):
  79       if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
  80         return 0;
  81     case mmr_offset(chipid):
  82       /* Discard writes.  */
  83       break;
  84     default:
  85       if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
  86         return 0;
  87       *value16p = value;
  88       break;
  89     }
  90
  91   return nr_bytes;
  92 }
  93
  94 static unsigned
  95 bfin_pll_io_read_buffer (struct hw *me, void *dest,
  96                          int space, address_word addr, unsigned nr_bytes)
  97 {
  98   struct bfin_pll *pll = hw_data (me);
  99   bu32 mmr_off;
 100   bu32 *value32p;
 101   bu16 *value16p;
 102   void *valuep;
 103
 104   /* Invalid access mode is higher priority than missing register.  */
 105   if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
 106     return 0;
 107
 108   mmr_off = addr - pll->base;
 109   valuep = (void *)((uintptr_t)pll + mmr_base() + mmr_off);
 110   value16p = valuep;
 111   value32p = valuep;
 112
 113   HW_TRACE_READ ();
 114
 115   switch (mmr_off)
 116     {
 117     case mmr_offset(chipid):
 118       dv_store_4 (dest, *value32p);
 119       break;
 120     default:
 121       if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
 122         return 0;
 123       dv_store_2 (dest, *value16p);
 124       break;
 125     }
 126
 127   return nr_bytes;
 128 }
 129
 130 static const struct hw_port_descriptor bfin_pll_ports[] =
 131 {
 132   { "pll", 0, 0, output_port, },
 133   { NULL, 0, 0, 0, },
 134 };
 135
 136 static void
 137 attach_bfin_pll_regs (struct hw *me, struct bfin_pll *pll)
 138 {
 139   address_word attach_address;
 140   int attach_space;
 141   unsigned attach_size;
 142   reg_property_spec reg;
 143
 144   if (hw_find_property (me, "reg") == NULL)
 145     hw_abort (me, "Missing \"reg\" property");
 146
 147   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 148     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 149
 150   hw_unit_address_to_attach_address (hw_parent (me),
 151                                      &reg.address,
 152                                      &attach_space, &attach_address, me);
 153   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 154
 155   if (attach_size != BFIN_MMR_PLL_SIZE)
 156     hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PLL_SIZE);
 157
 158   hw_attach_address (hw_parent (me),
 159                      0, attach_space, attach_address, attach_size, me);
 160
 161   pll->base = attach_address;
 162 }
 163
 164 static void
 165 bfin_pll_finish (struct hw *me)
 166 {
 167   struct bfin_pll *pll;
 168
 169   pll = HW_ZALLOC (me, struct bfin_pll);
 170
 171   set_hw_data (me, pll);
 172   set_hw_io_read_buffer (me, bfin_pll_io_read_buffer);
 173   set_hw_io_write_buffer (me, bfin_pll_io_write_buffer);
 174   set_hw_ports (me, bfin_pll_ports);
 175
 176   attach_bfin_pll_regs (me, pll);
 177
 178   /* Initialize the PLL.  */
 179   /* XXX: Depends on part ?  */
 180   pll->pll_ctl = 0x1400;
 181   pll->pll_div = 0x0005;
 182   pll->vr_ctl = 0x40DB;
 183   pll->pll_stat = 0x00A2;
 184   pll->pll_lockcnt = 0x0200;
 185   pll->chipid = bfin_model_get_chipid (hw_system (me));
 186
 187   /* XXX: slow it down!  */
 188   pll->pll_ctl = 0xa800;
 189   pll->pll_div = 0x4;
 190   pll->vr_ctl = 0x40fb;
 191   pll->pll_stat = 0xa2;
 192   pll->pll_lockcnt = 0x300;
 193 }
 194
 195 const struct hw_descriptor dv_bfin_pll_descriptor[] =
 196 {
 197   {"bfin_pll", bfin_pll_finish,},
 198   {NULL, NULL},
 199 };