1 @c Copyright (C) 2014-2024 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter Visium Dependent Features
13 @node Machine Dependencies
14 @chapter Visium Dependent Features
17 @cindex Visium support
19 * Visium Options:: Options
20 * Visium Syntax:: Syntax
21 * Visium Opcodes:: Opcodes
26 @cindex Visium options
27 @cindex options for Visium
29 The Visium assembler implements one machine-specific option:
33 @cindex @code{-mtune=@var{arch}} command-line option, Visium
34 @item -mtune=@var{arch}
35 This option specifies the target architecture. If an attempt is made to
36 assemble an instruction that will not execute on the target architecture,
37 the assembler will issue an error message.
39 The following names are recognized:
51 * Visium Characters:: Special Characters
52 * Visium Registers:: Register Names
55 @node Visium Characters
56 @subsection Special Characters
58 @cindex line comment character, Visium
59 @cindex Visium line comment character
60 Line comments are introduced either by the @samp{!} character or by the
61 @samp{;} character appearing anywhere on a line.
63 A hash character (@samp{#}) as the first character on a line also
64 marks the start of a line comment, but in this case it could also be a
65 logical line number directive (@pxref{Comments}) or a preprocessor
66 control command (@pxref{Preprocessing}).
68 @cindex line separator, Visium
69 @cindex statement separator, Visium
70 @cindex Visium line separator
71 The Visium assembler does not currently support a line separator character.
73 @node Visium Registers
74 @subsection Register Names
75 @cindex Visium registers
76 @cindex register names, Visium
77 Registers can be specified either by using their canonical mnemonic names
78 or by using their alias if they have one, for example @samp{sp}.
82 All the standard opcodes of the architecture are implemented, along with the
83 following three pseudo-instructions: @code{cmp}, @code{cmpc}, @code{move}.
85 In addition, the following two illegal opcodes are implemented and used by the simulation:
88 stop 5-bit immediate, SourceA
89 trace 5-bit immediate, SourceA