gdb/rl78-tdep.c

   1 /* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
   2
   3    Copyright (C) 2011-2022 Free Software Foundation, Inc.
   4
   5    Contributed by Red Hat, Inc.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "defs.h"
  23 #include "arch-utils.h"
  24 #include "prologue-value.h"
  25 #include "target.h"
  26 #include "regcache.h"
  27 #include "opcode/rl78.h"
  28 #include "dis-asm.h"
  29 #include "gdbtypes.h"
  30 #include "frame.h"
  31 #include "frame-unwind.h"
  32 #include "frame-base.h"
  33 #include "value.h"
  34 #include "gdbcore.h"
  35 #include "dwarf2/frame.h"
  36 #include "reggroups.h"
  37 #include "gdbarch.h"
  38
  39 #include "elf/rl78.h"
  40 #include "elf-bfd.h"
  41
  42 /* Register Banks.  */
  43
  44 enum
  45 {
  46   RL78_BANK0 = 0,
  47   RL78_BANK1 = 1,
  48   RL78_BANK2 = 2,
  49   RL78_BANK3 = 3,
  50   RL78_NUMBANKS = 4,
  51   RL78_REGS_PER_BANK = 8
  52 };
  53
  54 /* Register Numbers.  */
  55
  56 enum
  57 {
  58   /* All general purpose registers are 8 bits wide.  */
  59   RL78_RAW_BANK0_R0_REGNUM = 0,
  60   RL78_RAW_BANK0_R1_REGNUM,
  61   RL78_RAW_BANK0_R2_REGNUM,
  62   RL78_RAW_BANK0_R3_REGNUM,
  63   RL78_RAW_BANK0_R4_REGNUM,
  64   RL78_RAW_BANK0_R5_REGNUM,
  65   RL78_RAW_BANK0_R6_REGNUM,
  66   RL78_RAW_BANK0_R7_REGNUM,
  67
  68   RL78_RAW_BANK1_R0_REGNUM,
  69   RL78_RAW_BANK1_R1_REGNUM,
  70   RL78_RAW_BANK1_R2_REGNUM,
  71   RL78_RAW_BANK1_R3_REGNUM,
  72   RL78_RAW_BANK1_R4_REGNUM,
  73   RL78_RAW_BANK1_R5_REGNUM,
  74   RL78_RAW_BANK1_R6_REGNUM,
  75   RL78_RAW_BANK1_R7_REGNUM,
  76
  77   RL78_RAW_BANK2_R0_REGNUM,
  78   RL78_RAW_BANK2_R1_REGNUM,
  79   RL78_RAW_BANK2_R2_REGNUM,
  80   RL78_RAW_BANK2_R3_REGNUM,
  81   RL78_RAW_BANK2_R4_REGNUM,
  82   RL78_RAW_BANK2_R5_REGNUM,
  83   RL78_RAW_BANK2_R6_REGNUM,
  84   RL78_RAW_BANK2_R7_REGNUM,
  85
  86   RL78_RAW_BANK3_R0_REGNUM,
  87   RL78_RAW_BANK3_R1_REGNUM,
  88   RL78_RAW_BANK3_R2_REGNUM,
  89   RL78_RAW_BANK3_R3_REGNUM,
  90   RL78_RAW_BANK3_R4_REGNUM,
  91   RL78_RAW_BANK3_R5_REGNUM,
  92   RL78_RAW_BANK3_R6_REGNUM,
  93   RL78_RAW_BANK3_R7_REGNUM,
  94
  95   RL78_PSW_REGNUM,      /* 8 bits */
  96   RL78_ES_REGNUM,       /* 8 bits */
  97   RL78_CS_REGNUM,       /* 8 bits */
  98   RL78_RAW_PC_REGNUM,   /* 20 bits; we'll use 32 bits for it.  */
  99
 100   /* Fixed address SFRs (some of those above are SFRs too.) */
 101   RL78_SPL_REGNUM,      /* 8 bits; lower half of SP */
 102   RL78_SPH_REGNUM,      /* 8 bits; upper half of SP */
 103   RL78_PMC_REGNUM,      /* 8 bits */
 104   RL78_MEM_REGNUM,      /* 8 bits ?? */
 105
 106   RL78_NUM_REGS,
 107
 108   /* Pseudo registers.  */
 109   RL78_PC_REGNUM = RL78_NUM_REGS,
 110   RL78_SP_REGNUM,
 111
 112   RL78_X_REGNUM,
 113   RL78_A_REGNUM,
 114   RL78_C_REGNUM,
 115   RL78_B_REGNUM,
 116   RL78_E_REGNUM,
 117   RL78_D_REGNUM,
 118   RL78_L_REGNUM,
 119   RL78_H_REGNUM,
 120
 121   RL78_AX_REGNUM,
 122   RL78_BC_REGNUM,
 123   RL78_DE_REGNUM,
 124   RL78_HL_REGNUM,
 125
 126   RL78_BANK0_R0_REGNUM,
 127   RL78_BANK0_R1_REGNUM,
 128   RL78_BANK0_R2_REGNUM,
 129   RL78_BANK0_R3_REGNUM,
 130   RL78_BANK0_R4_REGNUM,
 131   RL78_BANK0_R5_REGNUM,
 132   RL78_BANK0_R6_REGNUM,
 133   RL78_BANK0_R7_REGNUM,
 134
 135   RL78_BANK1_R0_REGNUM,
 136   RL78_BANK1_R1_REGNUM,
 137   RL78_BANK1_R2_REGNUM,
 138   RL78_BANK1_R3_REGNUM,
 139   RL78_BANK1_R4_REGNUM,
 140   RL78_BANK1_R5_REGNUM,
 141   RL78_BANK1_R6_REGNUM,
 142   RL78_BANK1_R7_REGNUM,
 143
 144   RL78_BANK2_R0_REGNUM,
 145   RL78_BANK2_R1_REGNUM,
 146   RL78_BANK2_R2_REGNUM,
 147   RL78_BANK2_R3_REGNUM,
 148   RL78_BANK2_R4_REGNUM,
 149   RL78_BANK2_R5_REGNUM,
 150   RL78_BANK2_R6_REGNUM,
 151   RL78_BANK2_R7_REGNUM,
 152
 153   RL78_BANK3_R0_REGNUM,
 154   RL78_BANK3_R1_REGNUM,
 155   RL78_BANK3_R2_REGNUM,
 156   RL78_BANK3_R3_REGNUM,
 157   RL78_BANK3_R4_REGNUM,
 158   RL78_BANK3_R5_REGNUM,
 159   RL78_BANK3_R6_REGNUM,
 160   RL78_BANK3_R7_REGNUM,
 161
 162   RL78_BANK0_RP0_REGNUM,
 163   RL78_BANK0_RP1_REGNUM,
 164   RL78_BANK0_RP2_REGNUM,
 165   RL78_BANK0_RP3_REGNUM,
 166
 167   RL78_BANK1_RP0_REGNUM,
 168   RL78_BANK1_RP1_REGNUM,
 169   RL78_BANK1_RP2_REGNUM,
 170   RL78_BANK1_RP3_REGNUM,
 171
 172   RL78_BANK2_RP0_REGNUM,
 173   RL78_BANK2_RP1_REGNUM,
 174   RL78_BANK2_RP2_REGNUM,
 175   RL78_BANK2_RP3_REGNUM,
 176
 177   RL78_BANK3_RP0_REGNUM,
 178   RL78_BANK3_RP1_REGNUM,
 179   RL78_BANK3_RP2_REGNUM,
 180   RL78_BANK3_RP3_REGNUM,
 181
 182   /* These are the same as the above 16 registers, but have
 183      a pointer type for use as base registers in expression
 184      evaluation.  These are not user visible registers.  */
 185   RL78_BANK0_RP0_PTR_REGNUM,
 186   RL78_BANK0_RP1_PTR_REGNUM,
 187   RL78_BANK0_RP2_PTR_REGNUM,
 188   RL78_BANK0_RP3_PTR_REGNUM,
 189
 190   RL78_BANK1_RP0_PTR_REGNUM,
 191   RL78_BANK1_RP1_PTR_REGNUM,
 192   RL78_BANK1_RP2_PTR_REGNUM,
 193   RL78_BANK1_RP3_PTR_REGNUM,
 194
 195   RL78_BANK2_RP0_PTR_REGNUM,
 196   RL78_BANK2_RP1_PTR_REGNUM,
 197   RL78_BANK2_RP2_PTR_REGNUM,
 198   RL78_BANK2_RP3_PTR_REGNUM,
 199
 200   RL78_BANK3_RP0_PTR_REGNUM,
 201   RL78_BANK3_RP1_PTR_REGNUM,
 202   RL78_BANK3_RP2_PTR_REGNUM,
 203   RL78_BANK3_RP3_PTR_REGNUM,
 204
 205   RL78_NUM_TOTAL_REGS,
 206   RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
 207 };
 208
 209 #define RL78_SP_ADDR 0xffff8
 210
 211 /* Architecture specific data.  */
 212
 213 struct rl78_gdbarch_tdep : gdbarch_tdep_base
 214 {
 215   /* The ELF header flags specify the multilib used.  */
 216   int elf_flags = 0;
 217
 218   struct type *rl78_void = nullptr,
 219               *rl78_uint8 = nullptr,
 220               *rl78_int8 = nullptr,
 221               *rl78_uint16 = nullptr,
 222               *rl78_int16 = nullptr,
 223               *rl78_uint32 = nullptr,
 224               *rl78_int32 = nullptr,
 225               *rl78_data_pointer = nullptr,
 226               *rl78_code_pointer = nullptr,
 227               *rl78_psw_type = nullptr;
 228 };
 229
 230 /* This structure holds the results of a prologue analysis.  */
 231
 232 struct rl78_prologue
 233 {
 234   /* The offset from the frame base to the stack pointer --- always
 235      zero or negative.
 236
 237      Calling this a "size" is a bit misleading, but given that the
 238      stack grows downwards, using offsets for everything keeps one
 239      from going completely sign-crazy: you never change anything's
 240      sign for an ADD instruction; always change the second operand's
 241      sign for a SUB instruction; and everything takes care of
 242      itself.  */
 243   int frame_size;
 244
 245   /* Non-zero if this function has initialized the frame pointer from
 246      the stack pointer, zero otherwise.  */
 247   int has_frame_ptr;
 248
 249   /* If has_frame_ptr is non-zero, this is the offset from the frame
 250      base to where the frame pointer points.  This is always zero or
 251      negative.  */
 252   int frame_ptr_offset;
 253
 254   /* The address of the first instruction at which the frame has been
 255      set up and the arguments are where the debug info says they are
 256      --- as best as we can tell.  */
 257   CORE_ADDR prologue_end;
 258
 259   /* reg_offset[R] is the offset from the CFA at which register R is
 260      saved, or 1 if register R has not been saved.  (Real values are
 261      always zero or negative.)  */
 262   int reg_offset[RL78_NUM_TOTAL_REGS];
 263 };
 264
 265 /* Construct type for PSW register.  */
 266
 267 static struct type *
 268 rl78_psw_type (struct gdbarch *gdbarch)
 269 {
 270   rl78_gdbarch_tdep *tdep = gdbarch_tdep<rl78_gdbarch_tdep> (gdbarch);
 271
 272   if (tdep->rl78_psw_type == NULL)
 273     {
 274       tdep->rl78_psw_type = arch_flags_type (gdbarch,
 275                                              "builtin_type_rl78_psw", 8);
 276       append_flags_type_flag (tdep->rl78_psw_type, 0, "CY");
 277       append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0");
 278       append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1");
 279       append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0");
 280       append_flags_type_flag (tdep->rl78_psw_type, 4, "AC");
 281       append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1");
 282       append_flags_type_flag (tdep->rl78_psw_type, 6, "Z");
 283       append_flags_type_flag (tdep->rl78_psw_type, 7, "IE");
 284     }
 285
 286   return tdep->rl78_psw_type;
 287 }
 288
 289 /* Implement the "register_type" gdbarch method.  */
 290
 291 static struct type *
 292 rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
 293 {
 294   rl78_gdbarch_tdep *tdep = gdbarch_tdep<rl78_gdbarch_tdep> (gdbarch);
 295
 296   if (reg_nr == RL78_PC_REGNUM)
 297     return tdep->rl78_code_pointer;
 298   else if (reg_nr == RL78_RAW_PC_REGNUM)
 299     return tdep->rl78_uint32;
 300   else if (reg_nr == RL78_PSW_REGNUM)
 301     return rl78_psw_type (gdbarch);
 302   else if (reg_nr <= RL78_MEM_REGNUM
 303            || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
 304            || (RL78_BANK0_R0_REGNUM <= reg_nr
 305                && reg_nr <= RL78_BANK3_R7_REGNUM))
 306     return tdep->rl78_int8;
 307   else if (reg_nr == RL78_SP_REGNUM
 308            || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
 309                && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
 310     return tdep->rl78_data_pointer;
 311   else
 312     return tdep->rl78_int16;
 313 }
 314
 315 /* Implement the "register_name" gdbarch method.  */
 316
 317 static const char *
 318 rl78_register_name (struct gdbarch *gdbarch, int regnr)
 319 {
 320   static const char *const reg_names[] =
 321   {
 322     "",         /* bank0_r0 */
 323     "",         /* bank0_r1 */
 324     "",         /* bank0_r2 */
 325     "",         /* bank0_r3 */
 326     "",         /* bank0_r4 */
 327     "",         /* bank0_r5 */
 328     "",         /* bank0_r6 */
 329     "",         /* bank0_r7 */
 330
 331     "",         /* bank1_r0 */
 332     "",         /* bank1_r1 */
 333     "",         /* bank1_r2 */
 334     "",         /* bank1_r3 */
 335     "",         /* bank1_r4 */
 336     "",         /* bank1_r5 */
 337     "",         /* bank1_r6 */
 338     "",         /* bank1_r7 */
 339
 340     "",         /* bank2_r0 */
 341     "",         /* bank2_r1 */
 342     "",         /* bank2_r2 */
 343     "",         /* bank2_r3 */
 344     "",         /* bank2_r4 */
 345     "",         /* bank2_r5 */
 346     "",         /* bank2_r6 */
 347     "",         /* bank2_r7 */
 348
 349     "",         /* bank3_r0 */
 350     "",         /* bank3_r1 */
 351     "",         /* bank3_r2 */
 352     "",         /* bank3_r3 */
 353     "",         /* bank3_r4 */
 354     "",         /* bank3_r5 */
 355     "",         /* bank3_r6 */
 356     "",         /* bank3_r7 */
 357
 358     "psw",
 359     "es",
 360     "cs",
 361     "",
 362
 363     "",         /* spl */
 364     "",         /* sph */
 365     "pmc",
 366     "mem",
 367
 368     "pc",
 369     "sp",
 370
 371     "x",
 372     "a",
 373     "c",
 374     "b",
 375     "e",
 376     "d",
 377     "l",
 378     "h",
 379
 380     "ax",
 381     "bc",
 382     "de",
 383     "hl",
 384
 385     "bank0_r0",
 386     "bank0_r1",
 387     "bank0_r2",
 388     "bank0_r3",
 389     "bank0_r4",
 390     "bank0_r5",
 391     "bank0_r6",
 392     "bank0_r7",
 393
 394     "bank1_r0",
 395     "bank1_r1",
 396     "bank1_r2",
 397     "bank1_r3",
 398     "bank1_r4",
 399     "bank1_r5",
 400     "bank1_r6",
 401     "bank1_r7",
 402
 403     "bank2_r0",
 404     "bank2_r1",
 405     "bank2_r2",
 406     "bank2_r3",
 407     "bank2_r4",
 408     "bank2_r5",
 409     "bank2_r6",
 410     "bank2_r7",
 411
 412     "bank3_r0",
 413     "bank3_r1",
 414     "bank3_r2",
 415     "bank3_r3",
 416     "bank3_r4",
 417     "bank3_r5",
 418     "bank3_r6",
 419     "bank3_r7",
 420
 421     "bank0_rp0",
 422     "bank0_rp1",
 423     "bank0_rp2",
 424     "bank0_rp3",
 425
 426     "bank1_rp0",
 427     "bank1_rp1",
 428     "bank1_rp2",
 429     "bank1_rp3",
 430
 431     "bank2_rp0",
 432     "bank2_rp1",
 433     "bank2_rp2",
 434     "bank2_rp3",
 435
 436     "bank3_rp0",
 437     "bank3_rp1",
 438     "bank3_rp2",
 439     "bank3_rp3",
 440
 441     /* The 16 register slots would be named
 442        bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
 443        want these to be user visible registers.  */
 444     "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
 445   };
 446
 447   return reg_names[regnr];
 448 }
 449
 450 /* Implement the "register_name" gdbarch method for the g10 variant.  */
 451
 452 static const char *
 453 rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
 454 {
 455   static const char *const reg_names[] =
 456   {
 457     "",         /* bank0_r0 */
 458     "",         /* bank0_r1 */
 459     "",         /* bank0_r2 */
 460     "",         /* bank0_r3 */
 461     "",         /* bank0_r4 */
 462     "",         /* bank0_r5 */
 463     "",         /* bank0_r6 */
 464     "",         /* bank0_r7 */
 465
 466     "",         /* bank1_r0 */
 467     "",         /* bank1_r1 */
 468     "",         /* bank1_r2 */
 469     "",         /* bank1_r3 */
 470     "",         /* bank1_r4 */
 471     "",         /* bank1_r5 */
 472     "",         /* bank1_r6 */
 473     "",         /* bank1_r7 */
 474
 475     "",         /* bank2_r0 */
 476     "",         /* bank2_r1 */
 477     "",         /* bank2_r2 */
 478     "",         /* bank2_r3 */
 479     "",         /* bank2_r4 */
 480     "",         /* bank2_r5 */
 481     "",         /* bank2_r6 */
 482     "",         /* bank2_r7 */
 483
 484     "",         /* bank3_r0 */
 485     "",         /* bank3_r1 */
 486     "",         /* bank3_r2 */
 487     "",         /* bank3_r3 */
 488     "",         /* bank3_r4 */
 489     "",         /* bank3_r5 */
 490     "",         /* bank3_r6 */
 491     "",         /* bank3_r7 */
 492
 493     "psw",
 494     "es",
 495     "cs",
 496     "",
 497
 498     "",         /* spl */
 499     "",         /* sph */
 500     "pmc",
 501     "mem",
 502
 503     "pc",
 504     "sp",
 505
 506     "x",
 507     "a",
 508     "c",
 509     "b",
 510     "e",
 511     "d",
 512     "l",
 513     "h",
 514
 515     "ax",
 516     "bc",
 517     "de",
 518     "hl",
 519
 520     "bank0_r0",
 521     "bank0_r1",
 522     "bank0_r2",
 523     "bank0_r3",
 524     "bank0_r4",
 525     "bank0_r5",
 526     "bank0_r6",
 527     "bank0_r7",
 528
 529     "",
 530     "",
 531     "",
 532     "",
 533     "",
 534     "",
 535     "",
 536     "",
 537
 538     "",
 539     "",
 540     "",
 541     "",
 542     "",
 543     "",
 544     "",
 545     "",
 546
 547     "",
 548     "",
 549     "",
 550     "",
 551     "",
 552     "",
 553     "",
 554     "",
 555
 556     "bank0_rp0",
 557     "bank0_rp1",
 558     "bank0_rp2",
 559     "bank0_rp3",
 560
 561     "",
 562     "",
 563     "",
 564     "",
 565
 566     "",
 567     "",
 568     "",
 569     "",
 570
 571     "",
 572     "",
 573     "",
 574     "",
 575
 576     /* The 16 register slots would be named
 577        bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
 578        want these to be user visible registers.  */
 579     "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
 580   };
 581
 582   return reg_names[regnr];
 583 }
 584
 585 /* Implement the "register_reggroup_p" gdbarch method.  */
 586
 587 static int
 588 rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
 589                           const struct reggroup *group)
 590 {
 591   if (group == all_reggroup)
 592     return 1;
 593
 594   /* All other registers are saved and restored.  */
 595   if (group == save_reggroup || group == restore_reggroup)
 596     {
 597       if ((regnum < RL78_NUM_REGS
 598            && regnum != RL78_SPL_REGNUM
 599            && regnum != RL78_SPH_REGNUM
 600            && regnum != RL78_RAW_PC_REGNUM)
 601           || regnum == RL78_SP_REGNUM
 602           || regnum == RL78_PC_REGNUM)
 603         return 1;
 604       else
 605         return 0;
 606     }
 607
 608   if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
 609       || regnum == RL78_ES_REGNUM
 610       || regnum == RL78_CS_REGNUM
 611       || regnum == RL78_SPL_REGNUM
 612       || regnum == RL78_SPH_REGNUM
 613       || regnum == RL78_PMC_REGNUM
 614       || regnum == RL78_MEM_REGNUM
 615       || regnum == RL78_RAW_PC_REGNUM
 616       || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
 617     return group == system_reggroup;
 618
 619   return group == general_reggroup;
 620 }
 621
 622 /* Strip bits to form an instruction address.  (When fetching a
 623    32-bit address from the stack, the high eight bits are garbage.
 624    This function strips off those unused bits.)  */
 625
 626 static CORE_ADDR
 627 rl78_make_instruction_address (CORE_ADDR addr)
 628 {
 629   return addr & 0xffffff;
 630 }
 631
 632 /* Set / clear bits necessary to make a data address.  */
 633
 634 static CORE_ADDR
 635 rl78_make_data_address (CORE_ADDR addr)
 636 {
 637   return (addr & 0xffff) | 0xf0000;
 638 }
 639
 640 /* Implement the "pseudo_register_read" gdbarch method.  */
 641
 642 static enum register_status
 643 rl78_pseudo_register_read (struct gdbarch *gdbarch,
 644                            readable_regcache *regcache,
 645                            int reg, gdb_byte *buffer)
 646 {
 647   enum register_status status;
 648
 649   if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
 650     {
 651       int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
 652                        + (reg - RL78_BANK0_R0_REGNUM);
 653
 654       status = regcache->raw_read (raw_regnum, buffer);
 655     }
 656   else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
 657     {
 658       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
 659                        + RL78_RAW_BANK0_R0_REGNUM;
 660
 661       status = regcache->raw_read (raw_regnum, buffer);
 662       if (status == REG_VALID)
 663         status = regcache->raw_read (raw_regnum + 1, buffer + 1);
 664     }
 665   else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
 666     {
 667       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
 668                        + RL78_RAW_BANK0_R0_REGNUM;
 669
 670       status = regcache->raw_read (raw_regnum, buffer);
 671       if (status == REG_VALID)
 672         status = regcache->raw_read (raw_regnum + 1, buffer + 1);
 673     }
 674   else if (reg == RL78_SP_REGNUM)
 675     {
 676       status = regcache->raw_read (RL78_SPL_REGNUM, buffer);
 677       if (status == REG_VALID)
 678         status = regcache->raw_read (RL78_SPH_REGNUM, buffer + 1);
 679     }
 680   else if (reg == RL78_PC_REGNUM)
 681     {
 682       gdb_byte rawbuf[4];
 683
 684       status = regcache->raw_read (RL78_RAW_PC_REGNUM, rawbuf);
 685       memcpy (buffer, rawbuf, 3);
 686     }
 687   else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
 688     {
 689       ULONGEST psw;
 690
 691       status = regcache->raw_read (RL78_PSW_REGNUM, &psw);
 692       if (status == REG_VALID)
 693         {
 694           /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
 695           int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
 696           int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
 697                            + (reg - RL78_X_REGNUM);
 698           status = regcache->raw_read (raw_regnum, buffer);
 699         }
 700     }
 701   else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
 702     {
 703       ULONGEST psw;
 704
 705       status = regcache->raw_read (RL78_PSW_REGNUM, &psw);
 706       if (status == REG_VALID)
 707         {
 708           /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
 709           int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
 710           int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
 711                            + 2 * (reg - RL78_AX_REGNUM);
 712           status = regcache->raw_read (raw_regnum, buffer);
 713           if (status == REG_VALID)
 714             status = regcache->raw_read (raw_regnum + 1, buffer + 1);
 715         }
 716     }
 717   else
 718     gdb_assert_not_reached ("invalid pseudo register number");
 719   return status;
 720 }
 721
 722 /* Implement the "pseudo_register_write" gdbarch method.  */
 723
 724 static void
 725 rl78_pseudo_register_write (struct gdbarch *gdbarch,
 726                             struct regcache *regcache,
 727                             int reg, const gdb_byte *buffer)
 728 {
 729   if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
 730     {
 731       int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
 732                        + (reg - RL78_BANK0_R0_REGNUM);
 733
 734       regcache->raw_write (raw_regnum, buffer);
 735     }
 736   else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
 737     {
 738       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
 739                        + RL78_RAW_BANK0_R0_REGNUM;
 740
 741       regcache->raw_write (raw_regnum, buffer);
 742       regcache->raw_write (raw_regnum + 1, buffer + 1);
 743     }
 744   else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
 745     {
 746       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
 747                        + RL78_RAW_BANK0_R0_REGNUM;
 748
 749       regcache->raw_write (raw_regnum, buffer);
 750       regcache->raw_write (raw_regnum + 1, buffer + 1);
 751     }
 752   else if (reg == RL78_SP_REGNUM)
 753     {
 754       regcache->raw_write (RL78_SPL_REGNUM, buffer);
 755       regcache->raw_write (RL78_SPH_REGNUM, buffer + 1);
 756     }
 757   else if (reg == RL78_PC_REGNUM)
 758     {
 759       gdb_byte rawbuf[4];
 760
 761       memcpy (rawbuf, buffer, 3);
 762       rawbuf[3] = 0;
 763       regcache->raw_write (RL78_RAW_PC_REGNUM, rawbuf);
 764     }
 765   else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
 766     {
 767       ULONGEST psw;
 768       int bank;
 769       int raw_regnum;
 770
 771       regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
 772       bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
 773       /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
 774       raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
 775                    + (reg - RL78_X_REGNUM);
 776       regcache->raw_write (raw_regnum, buffer);
 777     }
 778   else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
 779     {
 780       ULONGEST psw;
 781       int bank, raw_regnum;
 782
 783       regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
 784       bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
 785       /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
 786       raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
 787                    + 2 * (reg - RL78_AX_REGNUM);
 788       regcache->raw_write (raw_regnum, buffer);
 789       regcache->raw_write (raw_regnum + 1, buffer + 1);
 790     }
 791   else
 792     gdb_assert_not_reached ("invalid pseudo register number");
 793 }
 794
 795 /* The documented BRK instruction is actually a two byte sequence,
 796    {0x61, 0xcc}, but instructions may be as short as one byte.
 797    Correspondence with Renesas revealed that the one byte sequence
 798    0xff is used when a one byte breakpoint instruction is required.  */
 799 constexpr gdb_byte rl78_break_insn[] = { 0xff };
 800
 801 typedef BP_MANIPULATION (rl78_break_insn) rl78_breakpoint;
 802
 803 /* Define a "handle" struct for fetching the next opcode.  */
 804
 805 struct rl78_get_opcode_byte_handle
 806 {
 807   CORE_ADDR pc;
 808 };
 809
 810 static int
 811 opc_reg_to_gdb_regnum (int opcreg)
 812 {
 813   switch (opcreg)
 814     {
 815       case RL78_Reg_X:
 816         return RL78_X_REGNUM;
 817       case RL78_Reg_A:
 818         return RL78_A_REGNUM;
 819       case RL78_Reg_C:
 820         return RL78_C_REGNUM;
 821       case RL78_Reg_B:
 822         return RL78_B_REGNUM;
 823       case RL78_Reg_E:
 824         return RL78_E_REGNUM;
 825       case RL78_Reg_D:
 826         return RL78_D_REGNUM;
 827       case RL78_Reg_L:
 828         return RL78_L_REGNUM;
 829       case RL78_Reg_H:
 830         return RL78_H_REGNUM;
 831       case RL78_Reg_AX:
 832         return RL78_AX_REGNUM;
 833       case RL78_Reg_BC:
 834         return RL78_BC_REGNUM;
 835       case RL78_Reg_DE:
 836         return RL78_DE_REGNUM;
 837       case RL78_Reg_HL:
 838         return RL78_HL_REGNUM;
 839       case RL78_Reg_SP:
 840         return RL78_SP_REGNUM;
 841       case RL78_Reg_PSW:
 842         return RL78_PSW_REGNUM;
 843       case RL78_Reg_CS:
 844         return RL78_CS_REGNUM;
 845       case RL78_Reg_ES:
 846         return RL78_ES_REGNUM;
 847       case RL78_Reg_PMC:
 848         return RL78_PMC_REGNUM;
 849       case RL78_Reg_MEM:
 850         return RL78_MEM_REGNUM;
 851       default:
 852         internal_error (_("Undefined mapping for opc reg %d"),
 853                         opcreg);
 854     }
 855
 856   /* Not reached.  */
 857   return 0;
 858 }
 859
 860 /* Fetch a byte on behalf of the opcode decoder.  HANDLE contains
 861    the memory address of the next byte to fetch.  If successful,
 862    the address in the handle is updated and the byte fetched is
 863    returned as the value of the function.  If not successful, -1
 864    is returned.  */
 865
 866 static int
 867 rl78_get_opcode_byte (void *handle)
 868 {
 869   struct rl78_get_opcode_byte_handle *opcdata
 870     = (struct rl78_get_opcode_byte_handle *) handle;
 871   int status;
 872   gdb_byte byte;
 873
 874   status = target_read_memory (opcdata->pc, &byte, 1);
 875   if (status == 0)
 876     {
 877       opcdata->pc += 1;
 878       return byte;
 879     }
 880   else
 881     return -1;
 882 }
 883
 884 /* Function for finding saved registers in a 'struct pv_area'; this
 885    function is passed to pv_area::scan.
 886
 887    If VALUE is a saved register, ADDR says it was saved at a constant
 888    offset from the frame base, and SIZE indicates that the whole
 889    register was saved, record its offset.  */
 890
 891 static void
 892 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
 893                  pv_t value)
 894 {
 895   struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
 896
 897   if (value.kind == pvk_register
 898       && value.k == 0
 899       && pv_is_register (addr, RL78_SP_REGNUM)
 900       && size == register_size (target_gdbarch (), value.reg))
 901     result->reg_offset[value.reg] = addr.k;
 902 }
 903
 904 /* Analyze a prologue starting at START_PC, going no further than
 905    LIMIT_PC.  Fill in RESULT as appropriate.  */
 906
 907 static void
 908 rl78_analyze_prologue (CORE_ADDR start_pc,
 909                        CORE_ADDR limit_pc, struct rl78_prologue *result)
 910 {
 911   CORE_ADDR pc, next_pc;
 912   int rn;
 913   pv_t reg[RL78_NUM_TOTAL_REGS];
 914   CORE_ADDR after_last_frame_setup_insn = start_pc;
 915   int bank = 0;
 916
 917   memset (result, 0, sizeof (*result));
 918
 919   for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
 920     {
 921       reg[rn] = pv_register (rn, 0);
 922       result->reg_offset[rn] = 1;
 923     }
 924
 925   pv_area stack (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
 926
 927   /* The call instruction has saved the return address on the stack.  */
 928   reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
 929   stack.store (reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
 930
 931   pc = start_pc;
 932   while (pc < limit_pc)
 933     {
 934       int bytes_read;
 935       struct rl78_get_opcode_byte_handle opcode_handle;
 936       RL78_Opcode_Decoded opc;
 937
 938       opcode_handle.pc = pc;
 939       bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
 940                                        &opcode_handle, RL78_ISA_DEFAULT);
 941       next_pc = pc + bytes_read;
 942
 943       if (opc.id == RLO_sel)
 944         {
 945           bank = opc.op[1].addend;
 946         }
 947       else if (opc.id == RLO_mov
 948                && opc.op[0].type == RL78_Operand_PreDec
 949                && opc.op[0].reg == RL78_Reg_SP
 950                && opc.op[1].type == RL78_Operand_Register)
 951         {
 952           int rsrc = (bank * RL78_REGS_PER_BANK)
 953             + 2 * (opc.op[1].reg - RL78_Reg_AX);
 954
 955           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
 956           stack.store (reg[RL78_SP_REGNUM], 1, reg[rsrc]);
 957           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
 958           stack.store (reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
 959           after_last_frame_setup_insn = next_pc;
 960         }
 961       else if (opc.id == RLO_sub
 962                && opc.op[0].type == RL78_Operand_Register
 963                && opc.op[0].reg == RL78_Reg_SP
 964                && opc.op[1].type == RL78_Operand_Immediate)
 965         {
 966           int addend = opc.op[1].addend;
 967
 968           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
 969                                                  -addend);
 970           after_last_frame_setup_insn = next_pc;
 971         }
 972       else if (opc.id == RLO_mov
 973                && opc.size == RL78_Word
 974                && opc.op[0].type == RL78_Operand_Register
 975                && opc.op[1].type == RL78_Operand_Indirect
 976                && opc.op[1].addend == RL78_SP_ADDR)
 977         {
 978           reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
 979             = reg[RL78_SP_REGNUM];
 980         }
 981       else if (opc.id == RLO_sub
 982                && opc.size == RL78_Word
 983                && opc.op[0].type == RL78_Operand_Register
 984                && opc.op[1].type == RL78_Operand_Immediate)
 985         {
 986           int addend = opc.op[1].addend;
 987           int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
 988
 989           reg[regnum] = pv_add_constant (reg[regnum], -addend);
 990         }
 991       else if (opc.id == RLO_mov
 992                && opc.size == RL78_Word
 993                && opc.op[0].type == RL78_Operand_Indirect
 994                && opc.op[0].addend == RL78_SP_ADDR
 995                && opc.op[1].type == RL78_Operand_Register)
 996         {
 997           reg[RL78_SP_REGNUM]
 998             = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
 999           after_last_frame_setup_insn = next_pc;
1000         }
1001       else
1002         {
1003           /* Terminate the prologue scan.  */
1004           break;
1005         }
1006
1007       pc = next_pc;
1008     }
1009
1010   /* Is the frame size (offset, really) a known constant?  */
1011   if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
1012     result->frame_size = reg[RL78_SP_REGNUM].k;
1013
1014   /* Record where all the registers were saved.  */
1015   stack.scan (check_for_saved, (void *) result);
1016
1017   result->prologue_end = after_last_frame_setup_insn;
1018 }
1019
1020 /* Implement the "addr_bits_remove" gdbarch method.  */
1021
1022 static CORE_ADDR
1023 rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
1024 {
1025   return addr & 0xffffff;
1026 }
1027
1028 /* Implement the "address_to_pointer" gdbarch method.  */
1029
1030 static void
1031 rl78_address_to_pointer (struct gdbarch *gdbarch,
1032                          struct type *type, gdb_byte *buf, CORE_ADDR addr)
1033 {
1034   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1035
1036   store_unsigned_integer (buf, type->length (), byte_order,
1037                           addr & 0xffffff);
1038 }
1039
1040 /* Implement the "pointer_to_address" gdbarch method.  */
1041
1042 static CORE_ADDR
1043 rl78_pointer_to_address (struct gdbarch *gdbarch,
1044                          struct type *type, const gdb_byte *buf)
1045 {
1046   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1047   CORE_ADDR addr
1048     = extract_unsigned_integer (buf, type->length (), byte_order);
1049
1050   /* Is it a code address?  */
1051   if (type->target_type ()->code () == TYPE_CODE_FUNC
1052       || type->target_type ()->code () == TYPE_CODE_METHOD
1053       || TYPE_CODE_SPACE (type->target_type ())
1054       || type->length () == 4)
1055     return rl78_make_instruction_address (addr);
1056   else
1057     return rl78_make_data_address (addr);
1058 }
1059
1060 /* Implement the "skip_prologue" gdbarch method.  */
1061
1062 static CORE_ADDR
1063 rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1064 {
1065   const char *name;
1066   CORE_ADDR func_addr, func_end;
1067   struct rl78_prologue p;
1068
1069   /* Try to find the extent of the function that contains PC.  */
1070   if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1071     return pc;
1072
1073   rl78_analyze_prologue (pc, func_end, &p);
1074   return p.prologue_end;
1075 }
1076
1077 /* Implement the "unwind_pc" gdbarch method.  */
1078
1079 static CORE_ADDR
1080 rl78_unwind_pc (struct gdbarch *arch, frame_info_ptr next_frame)
1081 {
1082   return rl78_addr_bits_remove
1083            (arch, frame_unwind_register_unsigned (next_frame,
1084                                                   RL78_PC_REGNUM));
1085 }
1086
1087 /* Given a frame described by THIS_FRAME, decode the prologue of its
1088    associated function if there is not cache entry as specified by
1089    THIS_PROLOGUE_CACHE.  Save the decoded prologue in the cache and
1090    return that struct as the value of this function.  */
1091
1092 static struct rl78_prologue *
1093 rl78_analyze_frame_prologue (frame_info_ptr this_frame,
1094                            void **this_prologue_cache)
1095 {
1096   if (!*this_prologue_cache)
1097     {
1098       CORE_ADDR func_start, stop_addr;
1099
1100       *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
1101
1102       func_start = get_frame_func (this_frame);
1103       stop_addr = get_frame_pc (this_frame);
1104
1105       /* If we couldn't find any function containing the PC, then
1106          just initialize the prologue cache, but don't do anything.  */
1107       if (!func_start)
1108         stop_addr = func_start;
1109
1110       rl78_analyze_prologue (func_start, stop_addr,
1111                              (struct rl78_prologue *) *this_prologue_cache);
1112     }
1113
1114   return (struct rl78_prologue *) *this_prologue_cache;
1115 }
1116
1117 /* Given a frame and a prologue cache, return this frame's base.  */
1118
1119 static CORE_ADDR
1120 rl78_frame_base (frame_info_ptr this_frame, void **this_prologue_cache)
1121 {
1122   struct rl78_prologue *p
1123     = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1124   CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
1125
1126   return rl78_make_data_address (sp - p->frame_size);
1127 }
1128
1129 /* Implement the "frame_this_id" method for unwinding frames.  */
1130
1131 static void
1132 rl78_this_id (frame_info_ptr this_frame,
1133               void **this_prologue_cache, struct frame_id *this_id)
1134 {
1135   *this_id = frame_id_build (rl78_frame_base (this_frame,
1136                                               this_prologue_cache),
1137                              get_frame_func (this_frame));
1138 }
1139
1140 /* Implement the "frame_prev_register" method for unwinding frames.  */
1141
1142 static struct value *
1143 rl78_prev_register (frame_info_ptr this_frame,
1144                     void **this_prologue_cache, int regnum)
1145 {
1146   struct rl78_prologue *p
1147     = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1148   CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
1149
1150   if (regnum == RL78_SP_REGNUM)
1151     return frame_unwind_got_constant (this_frame, regnum, frame_base);
1152
1153   else if (regnum == RL78_SPL_REGNUM)
1154     return frame_unwind_got_constant (this_frame, regnum,
1155                                       (frame_base & 0xff));
1156
1157   else if (regnum == RL78_SPH_REGNUM)
1158     return frame_unwind_got_constant (this_frame, regnum,
1159                                       ((frame_base >> 8) & 0xff));
1160
1161   /* If prologue analysis says we saved this register somewhere,
1162      return a description of the stack slot holding it.  */
1163   else if (p->reg_offset[regnum] != 1)
1164     {
1165       struct value *rv =
1166         frame_unwind_got_memory (this_frame, regnum,
1167                                  frame_base + p->reg_offset[regnum]);
1168
1169       if (regnum == RL78_PC_REGNUM)
1170         {
1171           ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
1172
1173           return frame_unwind_got_constant (this_frame, regnum, pc);
1174         }
1175       return rv;
1176     }
1177
1178   /* Otherwise, presume we haven't changed the value of this
1179      register, and get it from the next frame.  */
1180   else
1181     return frame_unwind_got_register (this_frame, regnum, regnum);
1182 }
1183
1184 static const struct frame_unwind rl78_unwind =
1185 {
1186   "rl78 prologue",
1187   NORMAL_FRAME,
1188   default_frame_unwind_stop_reason,
1189   rl78_this_id,
1190   rl78_prev_register,
1191   NULL,
1192   default_frame_sniffer
1193 };
1194
1195 /* Implement the "dwarf_reg_to_regnum" gdbarch method.  */
1196
1197 static int
1198 rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1199 {
1200   if (0 <= reg && reg <= 31)
1201     {
1202       if ((reg & 1) == 0)
1203         /* Map even registers to their 16-bit counterparts which have a
1204            pointer type.  This is usually what is required from the DWARF
1205            info.  */
1206         return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
1207       else
1208         return reg;
1209     }
1210   else if (reg == 32)
1211     return RL78_SP_REGNUM;
1212   else if (reg == 33)
1213     return -1;                  /* ap */
1214   else if (reg == 34)
1215     return RL78_PSW_REGNUM;
1216   else if (reg == 35)
1217     return RL78_ES_REGNUM;
1218   else if (reg == 36)
1219     return RL78_CS_REGNUM;
1220   else if (reg == 37)
1221     return RL78_PC_REGNUM;
1222   else
1223     return -1;
1224 }
1225
1226 /* Implement the `register_sim_regno' gdbarch method.  */
1227
1228 static int
1229 rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1230 {
1231   gdb_assert (regnum < RL78_NUM_REGS);
1232
1233   /* So long as regnum is in [0, RL78_NUM_REGS), it's valid.  We
1234      just want to override the default here which disallows register
1235      numbers which have no names.  */
1236   return regnum;
1237 }
1238
1239 /* Implement the "return_value" gdbarch method.  */
1240
1241 static enum return_value_convention
1242 rl78_return_value (struct gdbarch *gdbarch,
1243                    struct value *function,
1244                    struct type *valtype,
1245                    struct regcache *regcache,
1246                    gdb_byte *readbuf, const gdb_byte *writebuf)
1247 {
1248   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1249   ULONGEST valtype_len = valtype->length ();
1250   rl78_gdbarch_tdep *tdep = gdbarch_tdep<rl78_gdbarch_tdep> (gdbarch);
1251   int is_g10 = tdep->elf_flags & E_FLAG_RL78_G10;
1252
1253   if (valtype_len > 8)
1254     return RETURN_VALUE_STRUCT_CONVENTION;
1255
1256   if (readbuf)
1257     {
1258       ULONGEST u;
1259       int argreg = RL78_RAW_BANK1_R0_REGNUM;
1260       CORE_ADDR g10_raddr = 0xffec8;
1261       int offset = 0;
1262
1263       while (valtype_len > 0)
1264         {
1265           if (is_g10)
1266             u = read_memory_integer (g10_raddr, 1,
1267                                      gdbarch_byte_order (gdbarch));
1268           else
1269             regcache_cooked_read_unsigned (regcache, argreg, &u);
1270           store_unsigned_integer (readbuf + offset, 1, byte_order, u);
1271           valtype_len -= 1;
1272           offset += 1;
1273           argreg++;
1274           g10_raddr++;
1275         }
1276     }
1277
1278   if (writebuf)
1279     {
1280       ULONGEST u;
1281       int argreg = RL78_RAW_BANK1_R0_REGNUM;
1282       CORE_ADDR g10_raddr = 0xffec8;
1283       int offset = 0;
1284
1285       while (valtype_len > 0)
1286         {
1287           u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
1288           if (is_g10) {
1289             gdb_byte b = u & 0xff;
1290             write_memory (g10_raddr, &b, 1);
1291           }
1292           else
1293             regcache_cooked_write_unsigned (regcache, argreg, u);
1294           valtype_len -= 1;
1295           offset += 1;
1296           argreg++;
1297           g10_raddr++;
1298         }
1299     }
1300
1301   return RETURN_VALUE_REGISTER_CONVENTION;
1302 }
1303
1304
1305 /* Implement the "frame_align" gdbarch method.  */
1306
1307 static CORE_ADDR
1308 rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1309 {
1310   return rl78_make_data_address (align_down (sp, 2));
1311 }
1312
1313
1314 /* Implement the "dummy_id" gdbarch method.  */
1315
1316 static struct frame_id
1317 rl78_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame)
1318 {
1319   return
1320     frame_id_build (rl78_make_data_address
1321                       (get_frame_register_unsigned
1322                         (this_frame, RL78_SP_REGNUM)),
1323                     get_frame_pc (this_frame));
1324 }
1325
1326
1327 /* Implement the "push_dummy_call" gdbarch method.  */
1328
1329 static CORE_ADDR
1330 rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1331                       struct regcache *regcache, CORE_ADDR bp_addr,
1332                       int nargs, struct value **args, CORE_ADDR sp,
1333                       function_call_return_method return_method,
1334                       CORE_ADDR struct_addr)
1335 {
1336   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1337   gdb_byte buf[4];
1338   int i;
1339
1340   /* Push arguments in reverse order.  */
1341   for (i = nargs - 1; i >= 0; i--)
1342     {
1343       struct type *value_type = value_enclosing_type (args[i]);
1344       int len = value_type->length ();
1345       int container_len = (len + 1) & ~1;
1346
1347       sp -= container_len;
1348       write_memory (rl78_make_data_address (sp),
1349                     value_contents_all (args[i]).data (), len);
1350     }
1351
1352   /* Store struct value address.  */
1353   if (return_method == return_method_struct)
1354     {
1355       store_unsigned_integer (buf, 2, byte_order, struct_addr);
1356       sp -= 2;
1357       write_memory (rl78_make_data_address (sp), buf, 2);
1358     }
1359
1360   /* Store return address.  */
1361   sp -= 4;
1362   store_unsigned_integer (buf, 4, byte_order, bp_addr);
1363   write_memory (rl78_make_data_address (sp), buf, 4);
1364
1365   /* Finally, update the stack pointer...  */
1366   regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1367
1368   /* DWARF2/GCC uses the stack address *before* the function call as a
1369      frame's CFA.  */
1370   return rl78_make_data_address (sp + 4);
1371 }
1372
1373 /* Allocate and initialize a gdbarch object.  */
1374
1375 static struct gdbarch *
1376 rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1377 {
1378   struct gdbarch *gdbarch;
1379   int elf_flags;
1380
1381   /* Extract the elf_flags if available.  */
1382   if (info.abfd != NULL
1383       && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1384     elf_flags = elf_elfheader (info.abfd)->e_flags;
1385   else
1386     elf_flags = 0;
1387
1388
1389   /* Try to find the architecture in the list of already defined
1390      architectures.  */
1391   for (arches = gdbarch_list_lookup_by_info (arches, &info);
1392        arches != NULL;
1393        arches = gdbarch_list_lookup_by_info (arches->next, &info))
1394     {
1395       rl78_gdbarch_tdep *tdep
1396         = gdbarch_tdep<rl78_gdbarch_tdep> (arches->gdbarch);
1397
1398       if (tdep->elf_flags != elf_flags)
1399         continue;
1400
1401       return arches->gdbarch;
1402     }
1403
1404   /* None found, create a new architecture from the information
1405      provided.  */
1406   rl78_gdbarch_tdep * tdep = new rl78_gdbarch_tdep;
1407   gdbarch = gdbarch_alloc (&info, tdep);
1408   tdep->elf_flags = elf_flags;
1409
1410   /* Initialize types.  */
1411   tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, TARGET_CHAR_BIT,
1412                                "void");
1413   tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1414   tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1415   tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1416   tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1417   tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1418   tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1419
1420   tdep->rl78_data_pointer
1421     = arch_pointer_type (gdbarch, 16, "rl78_data_addr_t", tdep->rl78_void);
1422   tdep->rl78_code_pointer
1423     = arch_pointer_type (gdbarch, 32, "rl78_code_addr_t", tdep->rl78_void);
1424
1425   /* Registers.  */
1426   set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1427   set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
1428   if (tdep->elf_flags & E_FLAG_RL78_G10)
1429     set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
1430   else
1431     set_gdbarch_register_name (gdbarch, rl78_register_name);
1432   set_gdbarch_register_type (gdbarch, rl78_register_type);
1433   set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1434   set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1435   set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1436   set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1437   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
1438   set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1439   set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
1440
1441   /* Data types.  */
1442   set_gdbarch_char_signed (gdbarch, 0);
1443   set_gdbarch_short_bit (gdbarch, 16);
1444   set_gdbarch_int_bit (gdbarch, 16);
1445   set_gdbarch_long_bit (gdbarch, 32);
1446   set_gdbarch_long_long_bit (gdbarch, 64);
1447   set_gdbarch_ptr_bit (gdbarch, 16);
1448   set_gdbarch_addr_bit (gdbarch, 32);
1449   set_gdbarch_dwarf2_addr_size (gdbarch, 4);
1450   set_gdbarch_float_bit (gdbarch, 32);
1451   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1452   set_gdbarch_double_bit (gdbarch, 32);
1453   set_gdbarch_long_double_bit (gdbarch, 64);
1454   set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1455   set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1456   set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1457   set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1458   set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1459
1460   /* Breakpoints.  */
1461   set_gdbarch_breakpoint_kind_from_pc (gdbarch, rl78_breakpoint::kind_from_pc);
1462   set_gdbarch_sw_breakpoint_from_kind (gdbarch, rl78_breakpoint::bp_from_kind);
1463   set_gdbarch_decr_pc_after_break (gdbarch, 1);
1464
1465   /* Frames, prologues, etc.  */
1466   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1467   set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1468   set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1469   set_gdbarch_frame_align (gdbarch, rl78_frame_align);
1470
1471   dwarf2_append_unwinders (gdbarch);
1472   frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1473
1474   /* Dummy frames, return values.  */
1475   set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1476   set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1477   set_gdbarch_return_value (gdbarch, rl78_return_value);
1478
1479   /* Virtual tables.  */
1480   set_gdbarch_vbit_in_delta (gdbarch, 1);
1481
1482   return gdbarch;
1483 }
1484
1485 /* Register the above initialization routine.  */
1486
1487 void _initialize_rl78_tdep ();
1488 void
1489 _initialize_rl78_tdep ()
1490 {
1491   gdbarch_register (bfd_arch_rl78, rl78_gdbarch_init);
1492 }