sim/riscv/machs.c

   1 /* RISC-V simulator.
   2
   3    Copyright (C) 2005-2023 Free Software Foundation, Inc.
   4    Contributed by Mike Frysinger.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25 #include "machs.h"
  26
  27 static void
  28 riscv_model_init (SIM_CPU *cpu)
  29 {
  30 }
  31
  32 static void
  33 riscv_init_cpu (SIM_CPU *cpu)
  34 {
  35 }
  36
  37 static void
  38 riscv_prepare_run (SIM_CPU *cpu)
  39 {
  40 }
  41
  42 static const SIM_MACH_IMP_PROPERTIES riscv_imp_properties =
  43 {
  44   sizeof (SIM_CPU),
  45   0,
  46 };
  47
  48 #if WITH_TARGET_WORD_BITSIZE >= 32
  49
  50 static const SIM_MACH rv32i_mach;
  51
  52 static const SIM_MODEL rv32_models[] =
  53 {
  54 #define M(ext) { "RV32"#ext, &rv32i_mach, MODEL_RV32##ext, NULL, riscv_model_init },
  55 #include "model_list.def"
  56 #undef M
  57   { 0, NULL, 0, NULL, NULL, }
  58 };
  59
  60 static const SIM_MACH rv32i_mach =
  61 {
  62   "rv32i", "riscv:rv32", MACH_RV32I,
  63   32, 32, &rv32_models[0], &riscv_imp_properties,
  64   riscv_init_cpu,
  65   riscv_prepare_run
  66 };
  67
  68 #endif
  69
  70 #if WITH_TARGET_WORD_BITSIZE >= 64
  71
  72 static const SIM_MACH rv64i_mach;
  73
  74 static const SIM_MODEL rv64_models[] =
  75 {
  76 #define M(ext) { "RV64"#ext, &rv64i_mach, MODEL_RV64##ext, NULL, riscv_model_init },
  77 #include "model_list.def"
  78 #undef M
  79   { 0, NULL, 0, NULL, NULL, }
  80 };
  81
  82 static const SIM_MACH rv64i_mach =
  83 {
  84   "rv64i", "riscv:rv64", MACH_RV64I,
  85   64, 64, &rv64_models[0], &riscv_imp_properties,
  86   riscv_init_cpu,
  87   riscv_prepare_run
  88 };
  89
  90 #endif
  91
  92 #if WITH_TARGET_WORD_BITSIZE >= 128
  93
  94 static const SIM_MACH rv128i_mach;
  95
  96 static const SIM_MODEL rv128_models[] =
  97 {
  98 #define M(ext) { "RV128"#ext, &rv128i_mach, MODEL_RV128##ext, NULL, riscv_model_init },
  99 #include "model_list.def"
 100 #undef M
 101   { 0, NULL, 0, NULL, NULL, }
 102 };
 103
 104 static const SIM_MACH rv128i_mach =
 105 {
 106   "rv128i", "riscv:rv128", MACH_RV128I,
 107   128, 128, &rv128_models[0], &riscv_imp_properties,
 108   riscv_init_cpu,
 109   riscv_prepare_run
 110 };
 111
 112 #endif
 113
 114 /* Order matters here.  */
 115 const SIM_MACH * const riscv_sim_machs[] =
 116 {
 117 #if WITH_TARGET_WORD_BITSIZE >= 128
 118   &rv128i_mach,
 119 #endif
 120 #if WITH_TARGET_WORD_BITSIZE >= 64
 121   &rv64i_mach,
 122 #endif
 123 #if WITH_TARGET_WORD_BITSIZE >= 32
 124   &rv32i_mach,
 125 #endif
 126   NULL
 127 };