sim/m32c/cpu.h

   1 /* cpu.h --- declarations for the M32C core.
   2
   3 Copyright (C) 2005-2023 Free Software Foundation, Inc.
   4 Contributed by Red Hat, Inc.
   5
   6 This file is part of the GNU simulators.
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3 of the License, or
  11 (at your option) any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21
  22 extern int verbose;
  23 extern int trace;
  24 extern int enable_counting;
  25
  26 extern int in_gdb;
  27
  28 typedef unsigned char QI;
  29 typedef unsigned short HI;
  30 typedef unsigned long SI;
  31 typedef unsigned long long DI;
  32
  33 #define CPU_R8C         0x11
  34 #define CPU_M16C        0x12
  35 #define CPU_M32CM       0x23
  36 #define CPU_M32C        0x24
  37 extern int m32c_cpu;
  38 void m32c_set_cpu (int cpu);
  39
  40 #define A16 (m32c_cpu & 0x10)
  41 #define A24 (m32c_cpu & 0x20)
  42
  43 typedef struct
  44 {
  45   HI r_r0;
  46   HI r_r2;
  47   HI r_r1;
  48   HI r_r3;
  49   SI r_a0;
  50   SI r_a1;
  51   SI r_sb;
  52   SI r_fb;
  53 } reg_bank_type;
  54
  55 typedef struct
  56 {
  57   reg_bank_type r[2];
  58   QI r_intbh;
  59   HI r_intbl;
  60   SI r_usp;
  61   SI r_isp;
  62   SI r_pc;
  63   HI r_flags;
  64 } regs_type;
  65
  66 extern regs_type regs;
  67 extern int addr_mask;
  68 extern int membus_mask;
  69
  70 #define FLAGBIT_C       0x0001
  71 #define FLAGBIT_D       0x0002
  72 #define FLAGBIT_Z       0x0004
  73 #define FLAGBIT_S       0x0008
  74 #define FLAGBIT_B       0x0010
  75 #define FLAGBIT_O       0x0020
  76 #define FLAGBIT_I       0x0040
  77 #define FLAGBIT_U       0x0080
  78
  79 #define REG_BANK (regs.r_flags & FLAG_B ? 1 : 0)
  80
  81 typedef enum
  82 {
  83   mem,
  84   r0, r0h, r0l,
  85   r1, r1h, r1l,
  86   r2, r2r0,
  87   r3, r3r1,
  88   r3r1r2r0,
  89   r3r2r1r0,
  90   a0,
  91   a1, a1a0,
  92   sb, fb,
  93   intb, intbl, intbh,
  94   sp, usp, isp, pc, flags,
  95   num_regs
  96 } reg_id;
  97
  98 extern char *reg_names[];
  99 extern int reg_bytes[];
 100
 101 extern unsigned int b2mask[];
 102 extern unsigned int b2signbit[];
 103 extern int b2maxsigned[];
 104 extern int b2minsigned[];
 105
 106 /* address of the opcode that just decoded, and thus caused the
 107    exception.  */
 108 extern int m32c_opcode_pc;
 109
 110 void init_regs (void);
 111 void stack_heap_stats (void);
 112 void set_pointer_width (int bytes);
 113 unsigned int get_reg (reg_id id);
 114 DI get_reg_ll (reg_id id);
 115 void put_reg (reg_id id, unsigned int value);
 116 void put_reg_ll (reg_id id, DI value);
 117
 118 void set_flags (int mask, int newbits);
 119 void set_oszc (int value, int bytes, int c);
 120 void set_szc (int value, int bytes, int c);
 121 void set_osz (int value, int bytes);
 122 void set_sz (int value, int bytes);
 123 void set_zc (int z, int c);
 124 void set_c (int c);
 125
 126 const char *bits (int v, int b);
 127
 128 typedef struct
 129 {
 130   QI bytes;
 131   QI mem;
 132   HI mask;
 133   union
 134   {
 135     unsigned int addr;
 136     reg_id reg;
 137   } u;
 138 } srcdest;
 139
 140 void decode_indirect (int src_indirect, int dest_indirect);
 141 void decode_index (int src_addend, int dest_addend);
 142
 143 /* r8c */
 144 srcdest decode_srcdest4 (int destcode, int bw);
 145 srcdest decode_dest3 (int destcode, int bw);
 146 srcdest decode_src2 (int srccode, int bw, int d);
 147 srcdest decode_dest1 (int destcode, int bw);
 148 srcdest decode_jumpdest (int destcode, int w);
 149 srcdest decode_cr (int crcode);
 150 srcdest decode_cr_b (int crcode, int bank);
 151 #define CR_B_DCT0       0
 152 #define CR_B_INTB       1
 153 #define CR_B_DMA0       2
 154
 155 /* m32c */
 156 srcdest decode_dest23 (int ddd, int dd, int bytes);
 157 srcdest decode_src23 (int sss, int ss, int bytes);
 158 srcdest decode_src3 (int sss, int bytes);
 159 srcdest decode_dest2 (int dd, int bytes);
 160
 161 srcdest widen_sd (srcdest sd);
 162 srcdest reg_sd (reg_id reg);
 163
 164 /* Mask has the one appropriate bit set.  */
 165 srcdest decode_bit (int destcode);
 166 srcdest decode_bit11 (int op0);
 167 int get_bit (srcdest sd);
 168 void put_bit (srcdest sd, int val);
 169 int get_bit2 (srcdest sd, int bit);
 170 void put_bit2 (srcdest sd, int bit, int val);
 171
 172 int get_src (srcdest sd);
 173 void put_dest (srcdest sd, int value);
 174
 175 int condition_true (int cond_id);
 176
 177 #define FLAG(f) (regs.r_flags & f ? 1 : 0)
 178 #define FLAG_C  FLAG(FLAGBIT_C)
 179 #define FLAG_D  FLAG(FLAGBIT_D)
 180 #define FLAG_Z  FLAG(FLAGBIT_Z)
 181 #define FLAG_S  FLAG(FLAGBIT_S)
 182 #define FLAG_B  FLAG(FLAGBIT_B)
 183 #define FLAG_O  FLAG(FLAGBIT_O)
 184 #define FLAG_I  FLAG(FLAGBIT_I)
 185 #define FLAG_U  FLAG(FLAGBIT_U)
 186
 187 /* Instruction step return codes.
 188    Suppose one of the decode_* functions below returns a value R:
 189    - If M32C_STEPPED (R), then the single-step completed normally.
 190    - If M32C_HIT_BREAK (R), then the program hit a breakpoint.
 191    - If M32C_EXITED (R), then the program has done an 'exit' system
 192      call, and the exit code is M32C_EXIT_STATUS (R).
 193    - If M32C_STOPPED (R), then a signal (number M32C_STOP_SIG (R)) was
 194      generated.
 195
 196    For building step return codes:
 197    - M32C_MAKE_STEPPED is the return code for finishing a normal step.
 198    - M32C_MAKE_HIT_BREAK is the return code for hitting a breakpoint.
 199    - M32C_MAKE_EXITED (C) is the return code for exiting with status C.
 200    - M32C_MAKE_STOPPED (S) is the return code for stopping on signal S.  */
 201 #define M32C_MAKE_STEPPED()   (0)
 202 #define M32C_MAKE_HIT_BREAK() (1)
 203 #define M32C_MAKE_EXITED(c)   (((int) (c) << 8) + 2)
 204 #define M32C_MAKE_STOPPED(s)  (((int) (s) << 8) + 3)
 205
 206 #define M32C_STEPPED(r)       ((r) == M32C_MAKE_STEPPED ())
 207 #define M32C_HIT_BREAK(r)     ((r) == M32C_MAKE_HIT_BREAK ())
 208 #define M32C_EXITED(r)        (((r) & 0xff) == 2)
 209 #define M32C_EXIT_STATUS(r)   ((r) >> 8)
 210 #define M32C_STOPPED(r)       (((r) & 0xff) == 3)
 211 #define M32C_STOP_SIG(r)      ((r) >> 8)
 212
 213 /* The step result for the current step.  Global to allow
 214    communication between the stepping function and the system
 215    calls.  */
 216 extern int step_result;
 217
 218 /* Used to detect heap/stack collisions */
 219 extern unsigned int heaptop;
 220 extern unsigned int heapbottom;
 221
 222 /* Points to one of the below functions, set by m32c_load().  */
 223 extern int (*decode_opcode) (void);
 224
 225 extern int decode_r8c (void);
 226 extern int decode_m32c (void);
 227
 228 extern void trace_register_changes (void);
 229
 230 extern void m32c_dump_all_registers (void);