1 # Hitachi H8 testcase 'cmp.w'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
15 .if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
17 set_grs_a5a5 ; Fill all general regs with
a fixed pattern
20 ;; cmp.w
#xx:3,Rd ; Immediate 3-bit operand
35 ;; fixme test ccr ; H
=0 N
=1 Z
=0 V
=0 C
=0
36 test_h_gr32
0xa5a50005 er0 ; er0 unchanged
37 test_gr_a5a5
1 ; Make sure other general regs
not disturbed
46 .if (sim_cpu) ; non-zero means h8300h, s, or sx
47 cmp_w_imm16
: ; cmp.w immediate
not available in h8300 mode.
48 set_grs_a5a5 ; Fill all general regs with
a fixed pattern
52 cmp.w
#0xa5a5, r0 ; Immediate 16-bit operand
55 eqi
: cmp.w
#0xa5a6, r0
58 lti
: cmp.w
#0xa5a4, r0
62 ;; fixme test ccr ; H
=0 N
=1 Z
=0 V
=0 C
=0
63 test_h_gr16
0xa5a5 r0 ;
r0 unchanged
64 .if (sim_cpu) ; non-zero means h8300h, s, or sx
65 test_h_gr32
0xa5a5a5a5 er0 ; er0 unchanged
67 test_gr_a5a5
1 ; Make sure other general regs
not disturbed
75 cmp_w_imm16_less_than_zero
: ; Test for less-than-zero immediate
77 ;; cmp.w
#xx:16, Rd, where #xx < 0 (ie. #xx > 0x7fff).
93 set_grs_a5a5 ; Fill all general regs with
a fixed pattern
98 cmp.w
r1, r0 ; Register operand
101 eqr
: mov.w
#0xa5a6, r1
105 ltr
: mov.w
#0xa5a4, r1
110 ;; fixme test ccr ; H
=0 N
=1 Z
=0 V
=0 C
=0
111 test_h_gr16
0xa5a5 r0 ;
r0 unchanged.
112 test_h_gr16
0xa5a4 r1 ;
r1 unchanged.
113 .if (sim_cpu) ; non-zero means h8300h, s, or sx
114 test_h_gr32
0xa5a5a5a5 er0 ;
r0 unchanged
115 test_h_gr32
0xa5a5a5a4 er1 ;
r1 unchanged
117 test_gr_a5a5
2 ; Make sure other general regs
not disturbed