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[binutils-gdb.git] / sim / or1k / sem-switch.c
blob404c6d982ba19ecc5bf411685abea6699812b772
1 /* Simulator instruction semantics for or1k32bf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright (C) 1996-2024 Free Software Foundation, Inc.
6
7 This file is part of the GNU simulators.
8
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23 */
24
25 #ifdef DEFINE_LABELS
26
27 /* The labels have the case they have because the enum of insn types
28 is all uppercase and in the non-stdc case the insn symbol is built
29 into the enum name. */
30
31 static struct {
32 int index;
33 void *label;
34 } labels[] = {
35 { OR1K32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
36 { OR1K32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
37 { OR1K32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
38 { OR1K32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
39 { OR1K32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
40 { OR1K32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
41 { OR1K32BF_INSN_L_J, && case_sem_INSN_L_J },
42 { OR1K32BF_INSN_L_ADRP, && case_sem_INSN_L_ADRP },
43 { OR1K32BF_INSN_L_JAL, && case_sem_INSN_L_JAL },
44 { OR1K32BF_INSN_L_JR, && case_sem_INSN_L_JR },
45 { OR1K32BF_INSN_L_JALR, && case_sem_INSN_L_JALR },
46 { OR1K32BF_INSN_L_BNF, && case_sem_INSN_L_BNF },
47 { OR1K32BF_INSN_L_BF, && case_sem_INSN_L_BF },
48 { OR1K32BF_INSN_L_TRAP, && case_sem_INSN_L_TRAP },
49 { OR1K32BF_INSN_L_SYS, && case_sem_INSN_L_SYS },
50 { OR1K32BF_INSN_L_MSYNC, && case_sem_INSN_L_MSYNC },
51 { OR1K32BF_INSN_L_PSYNC, && case_sem_INSN_L_PSYNC },
52 { OR1K32BF_INSN_L_CSYNC, && case_sem_INSN_L_CSYNC },
53 { OR1K32BF_INSN_L_RFE, && case_sem_INSN_L_RFE },
54 { OR1K32BF_INSN_L_NOP_IMM, && case_sem_INSN_L_NOP_IMM },
55 { OR1K32BF_INSN_L_MOVHI, && case_sem_INSN_L_MOVHI },
56 { OR1K32BF_INSN_L_MACRC, && case_sem_INSN_L_MACRC },
57 { OR1K32BF_INSN_L_MFSPR, && case_sem_INSN_L_MFSPR },
58 { OR1K32BF_INSN_L_MTSPR, && case_sem_INSN_L_MTSPR },
59 { OR1K32BF_INSN_L_LWZ, && case_sem_INSN_L_LWZ },
60 { OR1K32BF_INSN_L_LWS, && case_sem_INSN_L_LWS },
61 { OR1K32BF_INSN_L_LWA, && case_sem_INSN_L_LWA },
62 { OR1K32BF_INSN_L_LBZ, && case_sem_INSN_L_LBZ },
63 { OR1K32BF_INSN_L_LBS, && case_sem_INSN_L_LBS },
64 { OR1K32BF_INSN_L_LHZ, && case_sem_INSN_L_LHZ },
65 { OR1K32BF_INSN_L_LHS, && case_sem_INSN_L_LHS },
66 { OR1K32BF_INSN_L_SW, && case_sem_INSN_L_SW },
67 { OR1K32BF_INSN_L_SB, && case_sem_INSN_L_SB },
68 { OR1K32BF_INSN_L_SH, && case_sem_INSN_L_SH },
69 { OR1K32BF_INSN_L_SWA, && case_sem_INSN_L_SWA },
70 { OR1K32BF_INSN_L_SLL, && case_sem_INSN_L_SLL },
71 { OR1K32BF_INSN_L_SLLI, && case_sem_INSN_L_SLLI },
72 { OR1K32BF_INSN_L_SRL, && case_sem_INSN_L_SRL },
73 { OR1K32BF_INSN_L_SRLI, && case_sem_INSN_L_SRLI },
74 { OR1K32BF_INSN_L_SRA, && case_sem_INSN_L_SRA },
75 { OR1K32BF_INSN_L_SRAI, && case_sem_INSN_L_SRAI },
76 { OR1K32BF_INSN_L_ROR, && case_sem_INSN_L_ROR },
77 { OR1K32BF_INSN_L_RORI, && case_sem_INSN_L_RORI },
78 { OR1K32BF_INSN_L_AND, && case_sem_INSN_L_AND },
79 { OR1K32BF_INSN_L_OR, && case_sem_INSN_L_OR },
80 { OR1K32BF_INSN_L_XOR, && case_sem_INSN_L_XOR },
81 { OR1K32BF_INSN_L_ADD, && case_sem_INSN_L_ADD },
82 { OR1K32BF_INSN_L_SUB, && case_sem_INSN_L_SUB },
83 { OR1K32BF_INSN_L_ADDC, && case_sem_INSN_L_ADDC },
84 { OR1K32BF_INSN_L_MUL, && case_sem_INSN_L_MUL },
85 { OR1K32BF_INSN_L_MULD, && case_sem_INSN_L_MULD },
86 { OR1K32BF_INSN_L_MULU, && case_sem_INSN_L_MULU },
87 { OR1K32BF_INSN_L_MULDU, && case_sem_INSN_L_MULDU },
88 { OR1K32BF_INSN_L_DIV, && case_sem_INSN_L_DIV },
89 { OR1K32BF_INSN_L_DIVU, && case_sem_INSN_L_DIVU },
90 { OR1K32BF_INSN_L_FF1, && case_sem_INSN_L_FF1 },
91 { OR1K32BF_INSN_L_FL1, && case_sem_INSN_L_FL1 },
92 { OR1K32BF_INSN_L_ANDI, && case_sem_INSN_L_ANDI },
93 { OR1K32BF_INSN_L_ORI, && case_sem_INSN_L_ORI },
94 { OR1K32BF_INSN_L_XORI, && case_sem_INSN_L_XORI },
95 { OR1K32BF_INSN_L_ADDI, && case_sem_INSN_L_ADDI },
96 { OR1K32BF_INSN_L_ADDIC, && case_sem_INSN_L_ADDIC },
97 { OR1K32BF_INSN_L_MULI, && case_sem_INSN_L_MULI },
98 { OR1K32BF_INSN_L_EXTHS, && case_sem_INSN_L_EXTHS },
99 { OR1K32BF_INSN_L_EXTBS, && case_sem_INSN_L_EXTBS },
100 { OR1K32BF_INSN_L_EXTHZ, && case_sem_INSN_L_EXTHZ },
101 { OR1K32BF_INSN_L_EXTBZ, && case_sem_INSN_L_EXTBZ },
102 { OR1K32BF_INSN_L_EXTWS, && case_sem_INSN_L_EXTWS },
103 { OR1K32BF_INSN_L_EXTWZ, && case_sem_INSN_L_EXTWZ },
104 { OR1K32BF_INSN_L_CMOV, && case_sem_INSN_L_CMOV },
105 { OR1K32BF_INSN_L_SFGTS, && case_sem_INSN_L_SFGTS },
106 { OR1K32BF_INSN_L_SFGTSI, && case_sem_INSN_L_SFGTSI },
107 { OR1K32BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU },
108 { OR1K32BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI },
109 { OR1K32BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES },
110 { OR1K32BF_INSN_L_SFGESI, && case_sem_INSN_L_SFGESI },
111 { OR1K32BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU },
112 { OR1K32BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI },
113 { OR1K32BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS },
114 { OR1K32BF_INSN_L_SFLTSI, && case_sem_INSN_L_SFLTSI },
115 { OR1K32BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU },
116 { OR1K32BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI },
117 { OR1K32BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES },
118 { OR1K32BF_INSN_L_SFLESI, && case_sem_INSN_L_SFLESI },
119 { OR1K32BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU },
120 { OR1K32BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI },
121 { OR1K32BF_INSN_L_SFEQ, && case_sem_INSN_L_SFEQ },
122 { OR1K32BF_INSN_L_SFEQI, && case_sem_INSN_L_SFEQI },
123 { OR1K32BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE },
124 { OR1K32BF_INSN_L_SFNEI, && case_sem_INSN_L_SFNEI },
125 { OR1K32BF_INSN_L_MAC, && case_sem_INSN_L_MAC },
126 { OR1K32BF_INSN_L_MACI, && case_sem_INSN_L_MACI },
127 { OR1K32BF_INSN_L_MACU, && case_sem_INSN_L_MACU },
128 { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB },
129 { OR1K32BF_INSN_L_MSBU, && case_sem_INSN_L_MSBU },
130 { OR1K32BF_INSN_L_CUST1, && case_sem_INSN_L_CUST1 },
131 { OR1K32BF_INSN_L_CUST2, && case_sem_INSN_L_CUST2 },
132 { OR1K32BF_INSN_L_CUST3, && case_sem_INSN_L_CUST3 },
133 { OR1K32BF_INSN_L_CUST4, && case_sem_INSN_L_CUST4 },
134 { OR1K32BF_INSN_L_CUST5, && case_sem_INSN_L_CUST5 },
135 { OR1K32BF_INSN_L_CUST6, && case_sem_INSN_L_CUST6 },
136 { OR1K32BF_INSN_L_CUST7, && case_sem_INSN_L_CUST7 },
137 { OR1K32BF_INSN_L_CUST8, && case_sem_INSN_L_CUST8 },
138 { OR1K32BF_INSN_LF_ADD_S, && case_sem_INSN_LF_ADD_S },
139 { OR1K32BF_INSN_LF_ADD_D32, && case_sem_INSN_LF_ADD_D32 },
140 { OR1K32BF_INSN_LF_SUB_S, && case_sem_INSN_LF_SUB_S },
141 { OR1K32BF_INSN_LF_SUB_D32, && case_sem_INSN_LF_SUB_D32 },
142 { OR1K32BF_INSN_LF_MUL_S, && case_sem_INSN_LF_MUL_S },
143 { OR1K32BF_INSN_LF_MUL_D32, && case_sem_INSN_LF_MUL_D32 },
144 { OR1K32BF_INSN_LF_DIV_S, && case_sem_INSN_LF_DIV_S },
145 { OR1K32BF_INSN_LF_DIV_D32, && case_sem_INSN_LF_DIV_D32 },
146 { OR1K32BF_INSN_LF_REM_S, && case_sem_INSN_LF_REM_S },
147 { OR1K32BF_INSN_LF_REM_D32, && case_sem_INSN_LF_REM_D32 },
148 { OR1K32BF_INSN_LF_ITOF_S, && case_sem_INSN_LF_ITOF_S },
149 { OR1K32BF_INSN_LF_ITOF_D32, && case_sem_INSN_LF_ITOF_D32 },
150 { OR1K32BF_INSN_LF_FTOI_S, && case_sem_INSN_LF_FTOI_S },
151 { OR1K32BF_INSN_LF_FTOI_D32, && case_sem_INSN_LF_FTOI_D32 },
152 { OR1K32BF_INSN_LF_SFEQ_S, && case_sem_INSN_LF_SFEQ_S },
153 { OR1K32BF_INSN_LF_SFEQ_D32, && case_sem_INSN_LF_SFEQ_D32 },
154 { OR1K32BF_INSN_LF_SFNE_S, && case_sem_INSN_LF_SFNE_S },
155 { OR1K32BF_INSN_LF_SFNE_D32, && case_sem_INSN_LF_SFNE_D32 },
156 { OR1K32BF_INSN_LF_SFGE_S, && case_sem_INSN_LF_SFGE_S },
157 { OR1K32BF_INSN_LF_SFGE_D32, && case_sem_INSN_LF_SFGE_D32 },
158 { OR1K32BF_INSN_LF_SFGT_S, && case_sem_INSN_LF_SFGT_S },
159 { OR1K32BF_INSN_LF_SFGT_D32, && case_sem_INSN_LF_SFGT_D32 },
160 { OR1K32BF_INSN_LF_SFLT_S, && case_sem_INSN_LF_SFLT_S },
161 { OR1K32BF_INSN_LF_SFLT_D32, && case_sem_INSN_LF_SFLT_D32 },
162 { OR1K32BF_INSN_LF_SFLE_S, && case_sem_INSN_LF_SFLE_S },
163 { OR1K32BF_INSN_LF_SFLE_D32, && case_sem_INSN_LF_SFLE_D32 },
164 { OR1K32BF_INSN_LF_SFUEQ_S, && case_sem_INSN_LF_SFUEQ_S },
165 { OR1K32BF_INSN_LF_SFUEQ_D32, && case_sem_INSN_LF_SFUEQ_D32 },
166 { OR1K32BF_INSN_LF_SFUNE_S, && case_sem_INSN_LF_SFUNE_S },
167 { OR1K32BF_INSN_LF_SFUNE_D32, && case_sem_INSN_LF_SFUNE_D32 },
168 { OR1K32BF_INSN_LF_SFUGT_S, && case_sem_INSN_LF_SFUGT_S },
169 { OR1K32BF_INSN_LF_SFUGT_D32, && case_sem_INSN_LF_SFUGT_D32 },
170 { OR1K32BF_INSN_LF_SFUGE_S, && case_sem_INSN_LF_SFUGE_S },
171 { OR1K32BF_INSN_LF_SFUGE_D32, && case_sem_INSN_LF_SFUGE_D32 },
172 { OR1K32BF_INSN_LF_SFULT_S, && case_sem_INSN_LF_SFULT_S },
173 { OR1K32BF_INSN_LF_SFULT_D32, && case_sem_INSN_LF_SFULT_D32 },
174 { OR1K32BF_INSN_LF_SFULE_S, && case_sem_INSN_LF_SFULE_S },
175 { OR1K32BF_INSN_LF_SFULE_D32, && case_sem_INSN_LF_SFULE_D32 },
176 { OR1K32BF_INSN_LF_SFUN_S, && case_sem_INSN_LF_SFUN_S },
177 { OR1K32BF_INSN_LF_SFUN_D32, && case_sem_INSN_LF_SFUN_D32 },
178 { OR1K32BF_INSN_LF_MADD_S, && case_sem_INSN_LF_MADD_S },
179 { OR1K32BF_INSN_LF_MADD_D32, && case_sem_INSN_LF_MADD_D32 },
180 { OR1K32BF_INSN_LF_CUST1_S, && case_sem_INSN_LF_CUST1_S },
181 { OR1K32BF_INSN_LF_CUST1_D32, && case_sem_INSN_LF_CUST1_D32 },
182 { 0, 0 }
183 };
184 int i;
185
186 for (i = 0; labels[i].label != 0; ++i)
187 {
188 #if FAST_P
189 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
190 #else
191 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
192 #endif
193 }
194
195 #undef DEFINE_LABELS
196 #endif /* DEFINE_LABELS */
197
198 #ifdef DEFINE_SWITCH
199
200 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
201 off frills like tracing and profiling. */
202 /* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something
203 that can cause it to be optimized out. Another way would be to emit
204 special handlers into the instruction "stream". */
205
206 #if FAST_P
207 #undef CGEN_TRACE_RESULT
208 #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
209 #endif
210
211 #undef GET_ATTR
212 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
213
214 {
215
216 #if WITH_SCACHE_PBB
217
218 /* Branch to next handler without going around main loop. */
219 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
220 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
221
222 #else /* ! WITH_SCACHE_PBB */
223
224 #define NEXT(vpc) BREAK (sem)
225 #ifdef __GNUC__
226 #if FAST_P
227 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
228 #else
229 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
230 #endif
231 #else
232 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
233 #endif
234
235 #endif /* ! WITH_SCACHE_PBB */
236
237 {
238
239 CASE (sem, INSN_X_INVALID) : /* --invalid-- */
240 {
241 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
242 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
243 #define FLD(f) abuf->fields.sfmt_empty.f
244 int UNUSED written = 0;
245 IADDR UNUSED pc = abuf->addr;
246 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
247
248 {
249 /* Update the recorded pc in the cpu state struct.
250 Only necessary for WITH_SCACHE case, but to avoid the
251 conditional compilation .... */
252 SET_H_PC (pc);
253 /* Virtual insns have zero size. Overwrite vpc with address of next insn
254 using the default-insn-bitsize spec. When executing insns in parallel
255 we may want to queue the fault and continue execution. */
256 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
257 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
258 }
259
260 #undef FLD
261 }
262 NEXT (vpc);
263
264 CASE (sem, INSN_X_AFTER) : /* --after-- */
265 {
266 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
267 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
268 #define FLD(f) abuf->fields.sfmt_empty.f
269 int UNUSED written = 0;
270 IADDR UNUSED pc = abuf->addr;
271 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
272
273 {
274 #if WITH_SCACHE_PBB_OR1K32BF
275 or1k32bf_pbb_after (current_cpu, sem_arg);
276 #endif
277 }
278
279 #undef FLD
280 }
281 NEXT (vpc);
282
283 CASE (sem, INSN_X_BEFORE) : /* --before-- */
284 {
285 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
286 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
287 #define FLD(f) abuf->fields.sfmt_empty.f
288 int UNUSED written = 0;
289 IADDR UNUSED pc = abuf->addr;
290 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
291
292 {
293 #if WITH_SCACHE_PBB_OR1K32BF
294 or1k32bf_pbb_before (current_cpu, sem_arg);
295 #endif
296 }
297
298 #undef FLD
299 }
300 NEXT (vpc);
301
302 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
303 {
304 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
305 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
306 #define FLD(f) abuf->fields.sfmt_empty.f
307 int UNUSED written = 0;
308 IADDR UNUSED pc = abuf->addr;
309 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
310
311 {
312 #if WITH_SCACHE_PBB_OR1K32BF
313 #ifdef DEFINE_SWITCH
314 vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
315 pbb_br_type, pbb_br_npc);
316 BREAK (sem);
317 #else
318 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
319 vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
320 CPU_PBB_BR_TYPE (current_cpu),
321 CPU_PBB_BR_NPC (current_cpu));
322 #endif
323 #endif
324 }
325
326 #undef FLD
327 }
328 NEXT (vpc);
329
330 CASE (sem, INSN_X_CHAIN) : /* --chain-- */
331 {
332 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
333 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
334 #define FLD(f) abuf->fields.sfmt_empty.f
335 int UNUSED written = 0;
336 IADDR UNUSED pc = abuf->addr;
337 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
338
339 {
340 #if WITH_SCACHE_PBB_OR1K32BF
341 vpc = or1k32bf_pbb_chain (current_cpu, sem_arg);
342 #ifdef DEFINE_SWITCH
343 BREAK (sem);
344 #endif
345 #endif
346 }
347
348 #undef FLD
349 }
350 NEXT (vpc);
351
352 CASE (sem, INSN_X_BEGIN) : /* --begin-- */
353 {
354 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
355 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
356 #define FLD(f) abuf->fields.sfmt_empty.f
357 int UNUSED written = 0;
358 IADDR UNUSED pc = abuf->addr;
359 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
360
361 {
362 #if WITH_SCACHE_PBB_OR1K32BF
363 #if defined DEFINE_SWITCH || defined FAST_P
364 /* In the switch case FAST_P is a constant, allowing several optimizations
365 in any called inline functions. */
366 vpc = or1k32bf_pbb_begin (current_cpu, FAST_P);
367 #else
368 #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
369 vpc = or1k32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
370 #else
371 vpc = or1k32bf_pbb_begin (current_cpu, 0);
372 #endif
373 #endif
374 #endif
375 }
376
377 #undef FLD
378 }
379 NEXT (vpc);
380
381 CASE (sem, INSN_L_J) : /* l.j ${disp26} */
382 {
383 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
384 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
385 #define FLD(f) abuf->fields.sfmt_l_j.f
386 int UNUSED written = 0;
387 IADDR UNUSED pc = abuf->addr;
388 SEM_BRANCH_INIT
389 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
390
391 {
392 {
393 {
394 USI opval = FLD (i_disp26);
395 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
396 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
397 }
398 }
399 if (GET_H_SYS_CPUCFGR_ND ()) {
400 if (1)
401 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
402 }
403 }
404
405 SEM_BRANCH_FINI (vpc);
406 #undef FLD
407 }
408 NEXT (vpc);
409
410 CASE (sem, INSN_L_ADRP) : /* l.adrp $rD,${disp21} */
411 {
412 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
413 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
414 #define FLD(f) abuf->fields.sfmt_l_adrp.f
415 int UNUSED written = 0;
416 IADDR UNUSED pc = abuf->addr;
417 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
418
419 {
420 USI opval = FLD (i_disp21);
421 SET_H_GPR (FLD (f_r1), opval);
422 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
423 }
424
425 #undef FLD
426 }
427 NEXT (vpc);
428
429 CASE (sem, INSN_L_JAL) : /* l.jal ${disp26} */
430 {
431 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
432 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
433 #define FLD(f) abuf->fields.sfmt_l_j.f
434 int UNUSED written = 0;
435 IADDR UNUSED pc = abuf->addr;
436 SEM_BRANCH_INIT
437 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
438
439 {
440 {
441 USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
442 SET_H_GPR (((UINT) 9), opval);
443 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
444 }
445 {
446 {
447 {
448 USI opval = FLD (i_disp26);
449 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
450 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
451 }
452 }
453 if (GET_H_SYS_CPUCFGR_ND ()) {
454 if (1)
455 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
456 }
457 }
458 }
459
460 SEM_BRANCH_FINI (vpc);
461 #undef FLD
462 }
463 NEXT (vpc);
464
465 CASE (sem, INSN_L_JR) : /* l.jr $rB */
466 {
467 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
468 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
469 #define FLD(f) abuf->fields.sfmt_l_sll.f
470 int UNUSED written = 0;
471 IADDR UNUSED pc = abuf->addr;
472 SEM_BRANCH_INIT
473 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
474
475 {
476 {
477 {
478 USI opval = GET_H_GPR (FLD (f_r3));
479 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
480 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
481 }
482 }
483 if (GET_H_SYS_CPUCFGR_ND ()) {
484 if (1)
485 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
486 }
487 }
488
489 SEM_BRANCH_FINI (vpc);
490 #undef FLD
491 }
492 NEXT (vpc);
493
494 CASE (sem, INSN_L_JALR) : /* l.jalr $rB */
495 {
496 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
497 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
498 #define FLD(f) abuf->fields.sfmt_l_sll.f
499 int UNUSED written = 0;
500 IADDR UNUSED pc = abuf->addr;
501 SEM_BRANCH_INIT
502 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
503
504 {
505 {
506 USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
507 SET_H_GPR (((UINT) 9), opval);
508 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
509 }
510 {
511 {
512 {
513 USI opval = GET_H_GPR (FLD (f_r3));
514 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
515 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
516 }
517 }
518 if (GET_H_SYS_CPUCFGR_ND ()) {
519 if (1)
520 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
521 }
522 }
523 }
524
525 SEM_BRANCH_FINI (vpc);
526 #undef FLD
527 }
528 NEXT (vpc);
529
530 CASE (sem, INSN_L_BNF) : /* l.bnf ${disp26} */
531 {
532 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
533 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
534 #define FLD(f) abuf->fields.sfmt_l_j.f
535 int UNUSED written = 0;
536 IADDR UNUSED pc = abuf->addr;
537 SEM_BRANCH_INIT
538 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
539
540 {
541 if (NOTSI (GET_H_SYS_SR_F ())) {
542 {
543 {
544 USI opval = FLD (i_disp26);
545 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
546 written |= (1 << 4);
547 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
548 }
549 }
550 } else {
551 if (GET_H_SYS_CPUCFGR_ND ()) {
552 {
553 {
554 USI opval = ADDSI (pc, 4);
555 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
556 written |= (1 << 4);
557 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
558 }
559 }
560 }
561 }
562 if (GET_H_SYS_CPUCFGR_ND ()) {
563 if (1)
564 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
565 }
566 }
567
568 abuf->written = written;
569 SEM_BRANCH_FINI (vpc);
570 #undef FLD
571 }
572 NEXT (vpc);
573
574 CASE (sem, INSN_L_BF) : /* l.bf ${disp26} */
575 {
576 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
577 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
578 #define FLD(f) abuf->fields.sfmt_l_j.f
579 int UNUSED written = 0;
580 IADDR UNUSED pc = abuf->addr;
581 SEM_BRANCH_INIT
582 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
583
584 {
585 if (GET_H_SYS_SR_F ()) {
586 {
587 {
588 USI opval = FLD (i_disp26);
589 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
590 written |= (1 << 4);
591 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
592 }
593 }
594 } else {
595 if (GET_H_SYS_CPUCFGR_ND ()) {
596 {
597 {
598 USI opval = ADDSI (pc, 4);
599 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
600 written |= (1 << 4);
601 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
602 }
603 }
604 }
605 }
606 if (GET_H_SYS_CPUCFGR_ND ()) {
607 if (1)
608 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
609 }
610 }
611
612 abuf->written = written;
613 SEM_BRANCH_FINI (vpc);
614 #undef FLD
615 }
616 NEXT (vpc);
617
618 CASE (sem, INSN_L_TRAP) : /* l.trap ${uimm16} */
619 {
620 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
621 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
622 #define FLD(f) abuf->fields.sfmt_empty.f
623 int UNUSED written = 0;
624 IADDR UNUSED pc = abuf->addr;
625 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
626
627 or1k32bf_exception (current_cpu, pc, EXCEPT_TRAP);
628
629 #undef FLD
630 }
631 NEXT (vpc);
632
633 CASE (sem, INSN_L_SYS) : /* l.sys ${uimm16} */
634 {
635 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
636 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
637 #define FLD(f) abuf->fields.sfmt_empty.f
638 int UNUSED written = 0;
639 IADDR UNUSED pc = abuf->addr;
640 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
641
642 or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
643
644 #undef FLD
645 }
646 NEXT (vpc);
647
648 CASE (sem, INSN_L_MSYNC) : /* l.msync */
649 {
650 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
651 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
652 #define FLD(f) abuf->fields.sfmt_empty.f
653 int UNUSED written = 0;
654 IADDR UNUSED pc = abuf->addr;
655 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
656
657 ((void) 0); /*nop*/
658
659 #undef FLD
660 }
661 NEXT (vpc);
662
663 CASE (sem, INSN_L_PSYNC) : /* l.psync */
664 {
665 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
666 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
667 #define FLD(f) abuf->fields.sfmt_empty.f
668 int UNUSED written = 0;
669 IADDR UNUSED pc = abuf->addr;
670 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
671
672 ((void) 0); /*nop*/
673
674 #undef FLD
675 }
676 NEXT (vpc);
677
678 CASE (sem, INSN_L_CSYNC) : /* l.csync */
679 {
680 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
681 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
682 #define FLD(f) abuf->fields.sfmt_empty.f
683 int UNUSED written = 0;
684 IADDR UNUSED pc = abuf->addr;
685 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
686
687 ((void) 0); /*nop*/
688
689 #undef FLD
690 }
691 NEXT (vpc);
692
693 CASE (sem, INSN_L_RFE) : /* l.rfe */
694 {
695 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
696 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
697 #define FLD(f) abuf->fields.sfmt_empty.f
698 int UNUSED written = 0;
699 IADDR UNUSED pc = abuf->addr;
700 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
701
702 or1k32bf_rfe (current_cpu);
703
704 #undef FLD
705 }
706 NEXT (vpc);
707
708 CASE (sem, INSN_L_NOP_IMM) : /* l.nop ${uimm16} */
709 {
710 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
711 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
712 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
713 int UNUSED written = 0;
714 IADDR UNUSED pc = abuf->addr;
715 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
716
717 or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
718
719 #undef FLD
720 }
721 NEXT (vpc);
722
723 CASE (sem, INSN_L_MOVHI) : /* l.movhi $rD,$uimm16 */
724 {
725 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
726 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
727 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
728 int UNUSED written = 0;
729 IADDR UNUSED pc = abuf->addr;
730 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
731
732 {
733 USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16);
734 SET_H_GPR (FLD (f_r1), opval);
735 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
736 }
737
738 #undef FLD
739 }
740 NEXT (vpc);
741
742 CASE (sem, INSN_L_MACRC) : /* l.macrc $rD */
743 {
744 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
745 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
746 #define FLD(f) abuf->fields.sfmt_l_adrp.f
747 int UNUSED written = 0;
748 IADDR UNUSED pc = abuf->addr;
749 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
750
751 {
752 {
753 USI opval = GET_H_MAC_MACLO ();
754 SET_H_GPR (FLD (f_r1), opval);
755 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
756 }
757 {
758 USI opval = 0;
759 SET_H_MAC_MACLO (opval);
760 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
761 }
762 {
763 USI opval = 0;
764 SET_H_MAC_MACHI (opval);
765 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
766 }
767 }
768
769 #undef FLD
770 }
771 NEXT (vpc);
772
773 CASE (sem, INSN_L_MFSPR) : /* l.mfspr $rD,$rA,${uimm16} */
774 {
775 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
776 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
777 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
778 int UNUSED written = 0;
779 IADDR UNUSED pc = abuf->addr;
780 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
781
782 {
783 USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
784 SET_H_GPR (FLD (f_r1), opval);
785 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
786 }
787
788 #undef FLD
789 }
790 NEXT (vpc);
791
792 CASE (sem, INSN_L_MTSPR) : /* l.mtspr $rA,$rB,${uimm16-split} */
793 {
794 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
795 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
796 #define FLD(f) abuf->fields.sfmt_l_mtspr.f
797 int UNUSED written = 0;
798 IADDR UNUSED pc = abuf->addr;
799 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
800
801 or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
802
803 #undef FLD
804 }
805 NEXT (vpc);
806
807 CASE (sem, INSN_L_LWZ) : /* l.lwz $rD,${simm16}($rA) */
808 {
809 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
810 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
811 #define FLD(f) abuf->fields.sfmt_l_lwz.f
812 int UNUSED written = 0;
813 IADDR UNUSED pc = abuf->addr;
814 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
815
816 {
817 USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
818 SET_H_GPR (FLD (f_r1), opval);
819 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
820 }
821
822 #undef FLD
823 }
824 NEXT (vpc);
825
826 CASE (sem, INSN_L_LWS) : /* l.lws $rD,${simm16}($rA) */
827 {
828 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
829 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
830 #define FLD(f) abuf->fields.sfmt_l_lwz.f
831 int UNUSED written = 0;
832 IADDR UNUSED pc = abuf->addr;
833 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
834
835 {
836 SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
837 SET_H_GPR (FLD (f_r1), opval);
838 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
839 }
840
841 #undef FLD
842 }
843 NEXT (vpc);
844
845 CASE (sem, INSN_L_LWA) : /* l.lwa $rD,${simm16}($rA) */
846 {
847 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
848 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
849 #define FLD(f) abuf->fields.sfmt_l_lwz.f
850 int UNUSED written = 0;
851 IADDR UNUSED pc = abuf->addr;
852 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
853
854 {
855 {
856 USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
857 SET_H_GPR (FLD (f_r1), opval);
858 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
859 }
860 {
861 BI opval = 1;
862 CPU (h_atomic_reserve) = opval;
863 CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
864 }
865 {
866 SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
867 CPU (h_atomic_address) = opval;
868 CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
869 }
870 }
871
872 #undef FLD
873 }
874 NEXT (vpc);
875
876 CASE (sem, INSN_L_LBZ) : /* l.lbz $rD,${simm16}($rA) */
877 {
878 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
879 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
880 #define FLD(f) abuf->fields.sfmt_l_lwz.f
881 int UNUSED written = 0;
882 IADDR UNUSED pc = abuf->addr;
883 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
884
885 {
886 USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
887 SET_H_GPR (FLD (f_r1), opval);
888 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
889 }
890
891 #undef FLD
892 }
893 NEXT (vpc);
894
895 CASE (sem, INSN_L_LBS) : /* l.lbs $rD,${simm16}($rA) */
896 {
897 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
898 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
899 #define FLD(f) abuf->fields.sfmt_l_lwz.f
900 int UNUSED written = 0;
901 IADDR UNUSED pc = abuf->addr;
902 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
903
904 {
905 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
906 SET_H_GPR (FLD (f_r1), opval);
907 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
908 }
909
910 #undef FLD
911 }
912 NEXT (vpc);
913
914 CASE (sem, INSN_L_LHZ) : /* l.lhz $rD,${simm16}($rA) */
915 {
916 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
917 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
918 #define FLD(f) abuf->fields.sfmt_l_lwz.f
919 int UNUSED written = 0;
920 IADDR UNUSED pc = abuf->addr;
921 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
922
923 {
924 USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
925 SET_H_GPR (FLD (f_r1), opval);
926 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
927 }
928
929 #undef FLD
930 }
931 NEXT (vpc);
932
933 CASE (sem, INSN_L_LHS) : /* l.lhs $rD,${simm16}($rA) */
934 {
935 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
936 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
937 #define FLD(f) abuf->fields.sfmt_l_lwz.f
938 int UNUSED written = 0;
939 IADDR UNUSED pc = abuf->addr;
940 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
941
942 {
943 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
944 SET_H_GPR (FLD (f_r1), opval);
945 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
946 }
947
948 #undef FLD
949 }
950 NEXT (vpc);
951
952 CASE (sem, INSN_L_SW) : /* l.sw ${simm16-split}($rA),$rB */
953 {
954 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
955 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
956 #define FLD(f) abuf->fields.sfmt_l_sw.f
957 int UNUSED written = 0;
958 IADDR UNUSED pc = abuf->addr;
959 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
960
961 {
962 SI tmp_addr;
963 tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
964 {
965 USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
966 SETMEMUSI (current_cpu, pc, tmp_addr, opval);
967 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
968 }
969 if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
970 {
971 BI opval = 0;
972 CPU (h_atomic_reserve) = opval;
973 written |= (1 << 4);
974 CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
975 }
976 }
977 }
978
979 abuf->written = written;
980 #undef FLD
981 }
982 NEXT (vpc);
983
984 CASE (sem, INSN_L_SB) : /* l.sb ${simm16-split}($rA),$rB */
985 {
986 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
987 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
988 #define FLD(f) abuf->fields.sfmt_l_sw.f
989 int UNUSED written = 0;
990 IADDR UNUSED pc = abuf->addr;
991 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
992
993 {
994 SI tmp_addr;
995 tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
996 {
997 UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3)));
998 SETMEMUQI (current_cpu, pc, tmp_addr, opval);
999 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1000 }
1001 if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
1002 {
1003 BI opval = 0;
1004 CPU (h_atomic_reserve) = opval;
1005 written |= (1 << 4);
1006 CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
1007 }
1008 }
1009 }
1010
1011 abuf->written = written;
1012 #undef FLD
1013 }
1014 NEXT (vpc);
1015
1016 CASE (sem, INSN_L_SH) : /* l.sh ${simm16-split}($rA),$rB */
1017 {
1018 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1019 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1020 #define FLD(f) abuf->fields.sfmt_l_sw.f
1021 int UNUSED written = 0;
1022 IADDR UNUSED pc = abuf->addr;
1023 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1024
1025 {
1026 SI tmp_addr;
1027 tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
1028 {
1029 UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3)));
1030 SETMEMUHI (current_cpu, pc, tmp_addr, opval);
1031 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1032 }
1033 if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
1034 {
1035 BI opval = 0;
1036 CPU (h_atomic_reserve) = opval;
1037 written |= (1 << 4);
1038 CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
1039 }
1040 }
1041 }
1042
1043 abuf->written = written;
1044 #undef FLD
1045 }
1046 NEXT (vpc);
1047
1048 CASE (sem, INSN_L_SWA) : /* l.swa ${simm16-split}($rA),$rB */
1049 {
1050 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1051 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1052 #define FLD(f) abuf->fields.sfmt_l_sw.f
1053 int UNUSED written = 0;
1054 IADDR UNUSED pc = abuf->addr;
1055 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1056
1057 {
1058 SI tmp_addr;
1059 tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
1060 {
1061 USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
1062 SET_H_SYS_SR_F (opval);
1063 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1064 }
1065 if (GET_H_SYS_SR_F ()) {
1066 {
1067 USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
1068 SETMEMUSI (current_cpu, pc, tmp_addr, opval);
1069 written |= (1 << 7);
1070 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1071 }
1072 }
1073 {
1074 BI opval = 0;
1075 CPU (h_atomic_reserve) = opval;
1076 CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
1077 }
1078 }
1079
1080 abuf->written = written;
1081 #undef FLD
1082 }
1083 NEXT (vpc);
1084
1085 CASE (sem, INSN_L_SLL) : /* l.sll $rD,$rA,$rB */
1086 {
1087 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1088 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1089 #define FLD(f) abuf->fields.sfmt_l_sll.f
1090 int UNUSED written = 0;
1091 IADDR UNUSED pc = abuf->addr;
1092 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1093
1094 {
1095 USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1096 SET_H_GPR (FLD (f_r1), opval);
1097 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1098 }
1099
1100 #undef FLD
1101 }
1102 NEXT (vpc);
1103
1104 CASE (sem, INSN_L_SLLI) : /* l.slli $rD,$rA,${uimm6} */
1105 {
1106 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1107 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1108 #define FLD(f) abuf->fields.sfmt_l_slli.f
1109 int UNUSED written = 0;
1110 IADDR UNUSED pc = abuf->addr;
1111 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1112
1113 {
1114 USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
1115 SET_H_GPR (FLD (f_r1), opval);
1116 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1117 }
1118
1119 #undef FLD
1120 }
1121 NEXT (vpc);
1122
1123 CASE (sem, INSN_L_SRL) : /* l.srl $rD,$rA,$rB */
1124 {
1125 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1126 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1127 #define FLD(f) abuf->fields.sfmt_l_sll.f
1128 int UNUSED written = 0;
1129 IADDR UNUSED pc = abuf->addr;
1130 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1131
1132 {
1133 USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1134 SET_H_GPR (FLD (f_r1), opval);
1135 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1136 }
1137
1138 #undef FLD
1139 }
1140 NEXT (vpc);
1141
1142 CASE (sem, INSN_L_SRLI) : /* l.srli $rD,$rA,${uimm6} */
1143 {
1144 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1145 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1146 #define FLD(f) abuf->fields.sfmt_l_slli.f
1147 int UNUSED written = 0;
1148 IADDR UNUSED pc = abuf->addr;
1149 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1150
1151 {
1152 USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
1153 SET_H_GPR (FLD (f_r1), opval);
1154 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1155 }
1156
1157 #undef FLD
1158 }
1159 NEXT (vpc);
1160
1161 CASE (sem, INSN_L_SRA) : /* l.sra $rD,$rA,$rB */
1162 {
1163 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1164 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1165 #define FLD(f) abuf->fields.sfmt_l_sll.f
1166 int UNUSED written = 0;
1167 IADDR UNUSED pc = abuf->addr;
1168 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1169
1170 {
1171 USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1172 SET_H_GPR (FLD (f_r1), opval);
1173 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1174 }
1175
1176 #undef FLD
1177 }
1178 NEXT (vpc);
1179
1180 CASE (sem, INSN_L_SRAI) : /* l.srai $rD,$rA,${uimm6} */
1181 {
1182 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1183 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1184 #define FLD(f) abuf->fields.sfmt_l_slli.f
1185 int UNUSED written = 0;
1186 IADDR UNUSED pc = abuf->addr;
1187 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1188
1189 {
1190 USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
1191 SET_H_GPR (FLD (f_r1), opval);
1192 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1193 }
1194
1195 #undef FLD
1196 }
1197 NEXT (vpc);
1198
1199 CASE (sem, INSN_L_ROR) : /* l.ror $rD,$rA,$rB */
1200 {
1201 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1202 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1203 #define FLD(f) abuf->fields.sfmt_l_sll.f
1204 int UNUSED written = 0;
1205 IADDR UNUSED pc = abuf->addr;
1206 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1207
1208 {
1209 USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1210 SET_H_GPR (FLD (f_r1), opval);
1211 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1212 }
1213
1214 #undef FLD
1215 }
1216 NEXT (vpc);
1217
1218 CASE (sem, INSN_L_RORI) : /* l.rori $rD,$rA,${uimm6} */
1219 {
1220 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1221 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1222 #define FLD(f) abuf->fields.sfmt_l_slli.f
1223 int UNUSED written = 0;
1224 IADDR UNUSED pc = abuf->addr;
1225 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1226
1227 {
1228 USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
1229 SET_H_GPR (FLD (f_r1), opval);
1230 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1231 }
1232
1233 #undef FLD
1234 }
1235 NEXT (vpc);
1236
1237 CASE (sem, INSN_L_AND) : /* l.and $rD,$rA,$rB */
1238 {
1239 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1240 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1241 #define FLD(f) abuf->fields.sfmt_l_sll.f
1242 int UNUSED written = 0;
1243 IADDR UNUSED pc = abuf->addr;
1244 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1245
1246 {
1247 USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1248 SET_H_GPR (FLD (f_r1), opval);
1249 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1250 }
1251
1252 #undef FLD
1253 }
1254 NEXT (vpc);
1255
1256 CASE (sem, INSN_L_OR) : /* l.or $rD,$rA,$rB */
1257 {
1258 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1259 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1260 #define FLD(f) abuf->fields.sfmt_l_sll.f
1261 int UNUSED written = 0;
1262 IADDR UNUSED pc = abuf->addr;
1263 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1264
1265 {
1266 USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1267 SET_H_GPR (FLD (f_r1), opval);
1268 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1269 }
1270
1271 #undef FLD
1272 }
1273 NEXT (vpc);
1274
1275 CASE (sem, INSN_L_XOR) : /* l.xor $rD,$rA,$rB */
1276 {
1277 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1278 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1279 #define FLD(f) abuf->fields.sfmt_l_sll.f
1280 int UNUSED written = 0;
1281 IADDR UNUSED pc = abuf->addr;
1282 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1283
1284 {
1285 USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1286 SET_H_GPR (FLD (f_r1), opval);
1287 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1288 }
1289
1290 #undef FLD
1291 }
1292 NEXT (vpc);
1293
1294 CASE (sem, INSN_L_ADD) : /* l.add $rD,$rA,$rB */
1295 {
1296 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1297 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1298 #define FLD(f) abuf->fields.sfmt_l_sll.f
1299 int UNUSED written = 0;
1300 IADDR UNUSED pc = abuf->addr;
1301 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1302
1303 {
1304 {
1305 {
1306 BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
1307 SET_H_SYS_SR_CY (opval);
1308 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1309 }
1310 {
1311 BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
1312 SET_H_SYS_SR_OV (opval);
1313 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1314 }
1315 {
1316 USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1317 SET_H_GPR (FLD (f_r1), opval);
1318 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1319 }
1320 }
1321 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1322 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1323 }
1324 }
1325
1326 #undef FLD
1327 }
1328 NEXT (vpc);
1329
1330 CASE (sem, INSN_L_SUB) : /* l.sub $rD,$rA,$rB */
1331 {
1332 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1333 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1334 #define FLD(f) abuf->fields.sfmt_l_sll.f
1335 int UNUSED written = 0;
1336 IADDR UNUSED pc = abuf->addr;
1337 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1338
1339 {
1340 {
1341 {
1342 BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
1343 SET_H_SYS_SR_CY (opval);
1344 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1345 }
1346 {
1347 BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
1348 SET_H_SYS_SR_OV (opval);
1349 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1350 }
1351 {
1352 USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1353 SET_H_GPR (FLD (f_r1), opval);
1354 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1355 }
1356 }
1357 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1358 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1359 }
1360 }
1361
1362 #undef FLD
1363 }
1364 NEXT (vpc);
1365
1366 CASE (sem, INSN_L_ADDC) : /* l.addc $rD,$rA,$rB */
1367 {
1368 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1369 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1370 #define FLD(f) abuf->fields.sfmt_l_sll.f
1371 int UNUSED written = 0;
1372 IADDR UNUSED pc = abuf->addr;
1373 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1374
1375 {
1376 {
1377 BI tmp_tmp_sys_sr_cy;
1378 tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
1379 {
1380 BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
1381 SET_H_SYS_SR_CY (opval);
1382 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1383 }
1384 {
1385 BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
1386 SET_H_SYS_SR_OV (opval);
1387 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1388 }
1389 {
1390 USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
1391 SET_H_GPR (FLD (f_r1), opval);
1392 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1393 }
1394 }
1395 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1396 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1397 }
1398 }
1399
1400 #undef FLD
1401 }
1402 NEXT (vpc);
1403
1404 CASE (sem, INSN_L_MUL) : /* l.mul $rD,$rA,$rB */
1405 {
1406 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1407 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1408 #define FLD(f) abuf->fields.sfmt_l_sll.f
1409 int UNUSED written = 0;
1410 IADDR UNUSED pc = abuf->addr;
1411 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1412
1413 {
1414 {
1415 {
1416 BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1417 SET_H_SYS_SR_OV (opval);
1418 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1419 }
1420 {
1421 USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1422 SET_H_GPR (FLD (f_r1), opval);
1423 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1424 }
1425 }
1426 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1427 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1428 }
1429 }
1430
1431 #undef FLD
1432 }
1433 NEXT (vpc);
1434
1435 CASE (sem, INSN_L_MULD) : /* l.muld $rA,$rB */
1436 {
1437 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1438 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1439 #define FLD(f) abuf->fields.sfmt_l_sll.f
1440 int UNUSED written = 0;
1441 IADDR UNUSED pc = abuf->addr;
1442 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1443
1444 {
1445 DI tmp_result;
1446 tmp_result = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3))));
1447 {
1448 SI opval = SUBWORDDISI (tmp_result, 0);
1449 SET_H_MAC_MACHI (opval);
1450 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
1451 }
1452 {
1453 SI opval = SUBWORDDISI (tmp_result, 1);
1454 SET_H_MAC_MACLO (opval);
1455 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
1456 }
1457 }
1458
1459 #undef FLD
1460 }
1461 NEXT (vpc);
1462
1463 CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */
1464 {
1465 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1466 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1467 #define FLD(f) abuf->fields.sfmt_l_sll.f
1468 int UNUSED written = 0;
1469 IADDR UNUSED pc = abuf->addr;
1470 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1471
1472 {
1473 {
1474 {
1475 BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1476 SET_H_SYS_SR_CY (opval);
1477 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1478 }
1479 {
1480 USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1481 SET_H_GPR (FLD (f_r1), opval);
1482 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1483 }
1484 }
1485 if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
1486 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1487 }
1488 }
1489
1490 #undef FLD
1491 }
1492 NEXT (vpc);
1493
1494 CASE (sem, INSN_L_MULDU) : /* l.muldu $rA,$rB */
1495 {
1496 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1497 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1498 #define FLD(f) abuf->fields.sfmt_l_sll.f
1499 int UNUSED written = 0;
1500 IADDR UNUSED pc = abuf->addr;
1501 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1502
1503 {
1504 DI tmp_result;
1505 tmp_result = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3))));
1506 {
1507 SI opval = SUBWORDDISI (tmp_result, 0);
1508 SET_H_MAC_MACHI (opval);
1509 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
1510 }
1511 {
1512 SI opval = SUBWORDDISI (tmp_result, 1);
1513 SET_H_MAC_MACLO (opval);
1514 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
1515 }
1516 }
1517
1518 #undef FLD
1519 }
1520 NEXT (vpc);
1521
1522 CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */
1523 {
1524 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1525 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1526 #define FLD(f) abuf->fields.sfmt_l_sll.f
1527 int UNUSED written = 0;
1528 IADDR UNUSED pc = abuf->addr;
1529 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1530
1531 if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
1532 {
1533 {
1534 BI opval = 0;
1535 SET_H_SYS_SR_OV (opval);
1536 written |= (1 << 5);
1537 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1538 }
1539 {
1540 SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1541 SET_H_GPR (FLD (f_r1), opval);
1542 written |= (1 << 4);
1543 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1544 }
1545 }
1546 } else {
1547 {
1548 {
1549 BI opval = 1;
1550 SET_H_SYS_SR_OV (opval);
1551 written |= (1 << 5);
1552 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1553 }
1554 if (GET_H_SYS_SR_OVE ()) {
1555 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1556 }
1557 }
1558 }
1559
1560 abuf->written = written;
1561 #undef FLD
1562 }
1563 NEXT (vpc);
1564
1565 CASE (sem, INSN_L_DIVU) : /* l.divu $rD,$rA,$rB */
1566 {
1567 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1568 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1569 #define FLD(f) abuf->fields.sfmt_l_sll.f
1570 int UNUSED written = 0;
1571 IADDR UNUSED pc = abuf->addr;
1572 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1573
1574 if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
1575 {
1576 {
1577 BI opval = 0;
1578 SET_H_SYS_SR_CY (opval);
1579 written |= (1 << 5);
1580 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1581 }
1582 {
1583 USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1584 SET_H_GPR (FLD (f_r1), opval);
1585 written |= (1 << 4);
1586 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1587 }
1588 }
1589 } else {
1590 {
1591 {
1592 BI opval = 1;
1593 SET_H_SYS_SR_CY (opval);
1594 written |= (1 << 5);
1595 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1596 }
1597 if (GET_H_SYS_SR_OVE ()) {
1598 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1599 }
1600 }
1601 }
1602
1603 abuf->written = written;
1604 #undef FLD
1605 }
1606 NEXT (vpc);
1607
1608 CASE (sem, INSN_L_FF1) : /* l.ff1 $rD,$rA */
1609 {
1610 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1611 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1612 #define FLD(f) abuf->fields.sfmt_l_slli.f
1613 int UNUSED written = 0;
1614 IADDR UNUSED pc = abuf->addr;
1615 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1616
1617 {
1618 USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2)));
1619 SET_H_GPR (FLD (f_r1), opval);
1620 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1621 }
1622
1623 #undef FLD
1624 }
1625 NEXT (vpc);
1626
1627 CASE (sem, INSN_L_FL1) : /* l.fl1 $rD,$rA */
1628 {
1629 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1630 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1631 #define FLD(f) abuf->fields.sfmt_l_slli.f
1632 int UNUSED written = 0;
1633 IADDR UNUSED pc = abuf->addr;
1634 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1635
1636 {
1637 USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2)));
1638 SET_H_GPR (FLD (f_r1), opval);
1639 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1640 }
1641
1642 #undef FLD
1643 }
1644 NEXT (vpc);
1645
1646 CASE (sem, INSN_L_ANDI) : /* l.andi $rD,$rA,$uimm16 */
1647 {
1648 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1649 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1650 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
1651 int UNUSED written = 0;
1652 IADDR UNUSED pc = abuf->addr;
1653 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1654
1655 {
1656 USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
1657 SET_H_GPR (FLD (f_r1), opval);
1658 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1659 }
1660
1661 #undef FLD
1662 }
1663 NEXT (vpc);
1664
1665 CASE (sem, INSN_L_ORI) : /* l.ori $rD,$rA,$uimm16 */
1666 {
1667 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1668 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1669 #define FLD(f) abuf->fields.sfmt_l_mfspr.f
1670 int UNUSED written = 0;
1671 IADDR UNUSED pc = abuf->addr;
1672 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1673
1674 {
1675 USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
1676 SET_H_GPR (FLD (f_r1), opval);
1677 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1678 }
1679
1680 #undef FLD
1681 }
1682 NEXT (vpc);
1683
1684 CASE (sem, INSN_L_XORI) : /* l.xori $rD,$rA,$simm16 */
1685 {
1686 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1687 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1688 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1689 int UNUSED written = 0;
1690 IADDR UNUSED pc = abuf->addr;
1691 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1692
1693 {
1694 USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1695 SET_H_GPR (FLD (f_r1), opval);
1696 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1697 }
1698
1699 #undef FLD
1700 }
1701 NEXT (vpc);
1702
1703 CASE (sem, INSN_L_ADDI) : /* l.addi $rD,$rA,$simm16 */
1704 {
1705 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1706 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1707 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1708 int UNUSED written = 0;
1709 IADDR UNUSED pc = abuf->addr;
1710 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1711
1712 {
1713 {
1714 {
1715 BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
1716 SET_H_SYS_SR_CY (opval);
1717 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1718 }
1719 {
1720 BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
1721 SET_H_SYS_SR_OV (opval);
1722 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1723 }
1724 {
1725 USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1726 SET_H_GPR (FLD (f_r1), opval);
1727 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1728 }
1729 }
1730 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1731 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1732 }
1733 }
1734
1735 #undef FLD
1736 }
1737 NEXT (vpc);
1738
1739 CASE (sem, INSN_L_ADDIC) : /* l.addic $rD,$rA,$simm16 */
1740 {
1741 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1742 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1743 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1744 int UNUSED written = 0;
1745 IADDR UNUSED pc = abuf->addr;
1746 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1747
1748 {
1749 {
1750 BI tmp_tmp_sys_sr_cy;
1751 tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
1752 {
1753 BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
1754 SET_H_SYS_SR_CY (opval);
1755 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
1756 }
1757 {
1758 BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
1759 SET_H_SYS_SR_OV (opval);
1760 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1761 }
1762 {
1763 SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
1764 SET_H_GPR (FLD (f_r1), opval);
1765 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1766 }
1767 }
1768 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1769 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1770 }
1771 }
1772
1773 #undef FLD
1774 }
1775 NEXT (vpc);
1776
1777 CASE (sem, INSN_L_MULI) : /* l.muli $rD,$rA,$simm16 */
1778 {
1779 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1780 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1781 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1782 int UNUSED written = 0;
1783 IADDR UNUSED pc = abuf->addr;
1784 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1785
1786 {
1787 {
1788 {
1789 USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1790 SET_H_SYS_SR_OV (opval);
1791 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
1792 }
1793 {
1794 USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1795 SET_H_GPR (FLD (f_r1), opval);
1796 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1797 }
1798 }
1799 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
1800 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
1801 }
1802 }
1803
1804 #undef FLD
1805 }
1806 NEXT (vpc);
1807
1808 CASE (sem, INSN_L_EXTHS) : /* l.exths $rD,$rA */
1809 {
1810 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1811 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1812 #define FLD(f) abuf->fields.sfmt_l_slli.f
1813 int UNUSED written = 0;
1814 IADDR UNUSED pc = abuf->addr;
1815 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1816
1817 {
1818 USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
1819 SET_H_GPR (FLD (f_r1), opval);
1820 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1821 }
1822
1823 #undef FLD
1824 }
1825 NEXT (vpc);
1826
1827 CASE (sem, INSN_L_EXTBS) : /* l.extbs $rD,$rA */
1828 {
1829 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1830 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1831 #define FLD(f) abuf->fields.sfmt_l_slli.f
1832 int UNUSED written = 0;
1833 IADDR UNUSED pc = abuf->addr;
1834 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1835
1836 {
1837 USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
1838 SET_H_GPR (FLD (f_r1), opval);
1839 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1840 }
1841
1842 #undef FLD
1843 }
1844 NEXT (vpc);
1845
1846 CASE (sem, INSN_L_EXTHZ) : /* l.exthz $rD,$rA */
1847 {
1848 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1849 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1850 #define FLD(f) abuf->fields.sfmt_l_slli.f
1851 int UNUSED written = 0;
1852 IADDR UNUSED pc = abuf->addr;
1853 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1854
1855 {
1856 USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
1857 SET_H_GPR (FLD (f_r1), opval);
1858 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1859 }
1860
1861 #undef FLD
1862 }
1863 NEXT (vpc);
1864
1865 CASE (sem, INSN_L_EXTBZ) : /* l.extbz $rD,$rA */
1866 {
1867 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1868 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1869 #define FLD(f) abuf->fields.sfmt_l_slli.f
1870 int UNUSED written = 0;
1871 IADDR UNUSED pc = abuf->addr;
1872 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1873
1874 {
1875 USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
1876 SET_H_GPR (FLD (f_r1), opval);
1877 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1878 }
1879
1880 #undef FLD
1881 }
1882 NEXT (vpc);
1883
1884 CASE (sem, INSN_L_EXTWS) : /* l.extws $rD,$rA */
1885 {
1886 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1887 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1888 #define FLD(f) abuf->fields.sfmt_l_slli.f
1889 int UNUSED written = 0;
1890 IADDR UNUSED pc = abuf->addr;
1891 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1892
1893 {
1894 USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
1895 SET_H_GPR (FLD (f_r1), opval);
1896 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1897 }
1898
1899 #undef FLD
1900 }
1901 NEXT (vpc);
1902
1903 CASE (sem, INSN_L_EXTWZ) : /* l.extwz $rD,$rA */
1904 {
1905 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1906 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1907 #define FLD(f) abuf->fields.sfmt_l_slli.f
1908 int UNUSED written = 0;
1909 IADDR UNUSED pc = abuf->addr;
1910 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1911
1912 {
1913 USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
1914 SET_H_GPR (FLD (f_r1), opval);
1915 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1916 }
1917
1918 #undef FLD
1919 }
1920 NEXT (vpc);
1921
1922 CASE (sem, INSN_L_CMOV) : /* l.cmov $rD,$rA,$rB */
1923 {
1924 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1925 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1926 #define FLD(f) abuf->fields.sfmt_l_sll.f
1927 int UNUSED written = 0;
1928 IADDR UNUSED pc = abuf->addr;
1929 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1930
1931 if (GET_H_SYS_SR_F ()) {
1932 {
1933 USI opval = GET_H_GPR (FLD (f_r2));
1934 SET_H_GPR (FLD (f_r1), opval);
1935 written |= (1 << 3);
1936 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1937 }
1938 } else {
1939 {
1940 USI opval = GET_H_GPR (FLD (f_r3));
1941 SET_H_GPR (FLD (f_r1), opval);
1942 written |= (1 << 3);
1943 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
1944 }
1945 }
1946
1947 abuf->written = written;
1948 #undef FLD
1949 }
1950 NEXT (vpc);
1951
1952 CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */
1953 {
1954 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1955 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1956 #define FLD(f) abuf->fields.sfmt_l_sll.f
1957 int UNUSED written = 0;
1958 IADDR UNUSED pc = abuf->addr;
1959 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1960
1961 {
1962 USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
1963 SET_H_SYS_SR_F (opval);
1964 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1965 }
1966
1967 #undef FLD
1968 }
1969 NEXT (vpc);
1970
1971 CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,$simm16 */
1972 {
1973 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1974 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1975 #define FLD(f) abuf->fields.sfmt_l_lwz.f
1976 int UNUSED written = 0;
1977 IADDR UNUSED pc = abuf->addr;
1978 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1979
1980 {
1981 USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
1982 SET_H_SYS_SR_F (opval);
1983 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
1984 }
1985
1986 #undef FLD
1987 }
1988 NEXT (vpc);
1989
1990 CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */
1991 {
1992 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1993 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1994 #define FLD(f) abuf->fields.sfmt_l_sll.f
1995 int UNUSED written = 0;
1996 IADDR UNUSED pc = abuf->addr;
1997 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1998
1999 {
2000 USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2001 SET_H_SYS_SR_F (opval);
2002 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2003 }
2004
2005 #undef FLD
2006 }
2007 NEXT (vpc);
2008
2009 CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$simm16 */
2010 {
2011 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2012 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2013 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2014 int UNUSED written = 0;
2015 IADDR UNUSED pc = abuf->addr;
2016 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2017
2018 {
2019 USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2020 SET_H_SYS_SR_F (opval);
2021 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2022 }
2023
2024 #undef FLD
2025 }
2026 NEXT (vpc);
2027
2028 CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */
2029 {
2030 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2031 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2032 #define FLD(f) abuf->fields.sfmt_l_sll.f
2033 int UNUSED written = 0;
2034 IADDR UNUSED pc = abuf->addr;
2035 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2036
2037 {
2038 USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2039 SET_H_SYS_SR_F (opval);
2040 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2041 }
2042
2043 #undef FLD
2044 }
2045 NEXT (vpc);
2046
2047 CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,$simm16 */
2048 {
2049 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2050 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2051 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2052 int UNUSED written = 0;
2053 IADDR UNUSED pc = abuf->addr;
2054 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2055
2056 {
2057 USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2058 SET_H_SYS_SR_F (opval);
2059 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2060 }
2061
2062 #undef FLD
2063 }
2064 NEXT (vpc);
2065
2066 CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */
2067 {
2068 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2069 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2070 #define FLD(f) abuf->fields.sfmt_l_sll.f
2071 int UNUSED written = 0;
2072 IADDR UNUSED pc = abuf->addr;
2073 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2074
2075 {
2076 USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2077 SET_H_SYS_SR_F (opval);
2078 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2079 }
2080
2081 #undef FLD
2082 }
2083 NEXT (vpc);
2084
2085 CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$simm16 */
2086 {
2087 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2088 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2089 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2090 int UNUSED written = 0;
2091 IADDR UNUSED pc = abuf->addr;
2092 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2093
2094 {
2095 USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2096 SET_H_SYS_SR_F (opval);
2097 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2098 }
2099
2100 #undef FLD
2101 }
2102 NEXT (vpc);
2103
2104 CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */
2105 {
2106 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2107 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2108 #define FLD(f) abuf->fields.sfmt_l_sll.f
2109 int UNUSED written = 0;
2110 IADDR UNUSED pc = abuf->addr;
2111 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2112
2113 {
2114 USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2115 SET_H_SYS_SR_F (opval);
2116 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2117 }
2118
2119 #undef FLD
2120 }
2121 NEXT (vpc);
2122
2123 CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,$simm16 */
2124 {
2125 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2126 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2127 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2128 int UNUSED written = 0;
2129 IADDR UNUSED pc = abuf->addr;
2130 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2131
2132 {
2133 USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2134 SET_H_SYS_SR_F (opval);
2135 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2136 }
2137
2138 #undef FLD
2139 }
2140 NEXT (vpc);
2141
2142 CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */
2143 {
2144 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2145 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2146 #define FLD(f) abuf->fields.sfmt_l_sll.f
2147 int UNUSED written = 0;
2148 IADDR UNUSED pc = abuf->addr;
2149 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2150
2151 {
2152 USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2153 SET_H_SYS_SR_F (opval);
2154 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2155 }
2156
2157 #undef FLD
2158 }
2159 NEXT (vpc);
2160
2161 CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$simm16 */
2162 {
2163 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2164 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2165 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2166 int UNUSED written = 0;
2167 IADDR UNUSED pc = abuf->addr;
2168 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2169
2170 {
2171 USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2172 SET_H_SYS_SR_F (opval);
2173 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2174 }
2175
2176 #undef FLD
2177 }
2178 NEXT (vpc);
2179
2180 CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */
2181 {
2182 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2183 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2184 #define FLD(f) abuf->fields.sfmt_l_sll.f
2185 int UNUSED written = 0;
2186 IADDR UNUSED pc = abuf->addr;
2187 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2188
2189 {
2190 USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2191 SET_H_SYS_SR_F (opval);
2192 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2193 }
2194
2195 #undef FLD
2196 }
2197 NEXT (vpc);
2198
2199 CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,$simm16 */
2200 {
2201 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2202 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2203 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2204 int UNUSED written = 0;
2205 IADDR UNUSED pc = abuf->addr;
2206 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2207
2208 {
2209 USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2210 SET_H_SYS_SR_F (opval);
2211 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2212 }
2213
2214 #undef FLD
2215 }
2216 NEXT (vpc);
2217
2218 CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */
2219 {
2220 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2221 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2222 #define FLD(f) abuf->fields.sfmt_l_sll.f
2223 int UNUSED written = 0;
2224 IADDR UNUSED pc = abuf->addr;
2225 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2226
2227 {
2228 USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2229 SET_H_SYS_SR_F (opval);
2230 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2231 }
2232
2233 #undef FLD
2234 }
2235 NEXT (vpc);
2236
2237 CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$simm16 */
2238 {
2239 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2240 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2241 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2242 int UNUSED written = 0;
2243 IADDR UNUSED pc = abuf->addr;
2244 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2245
2246 {
2247 USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2248 SET_H_SYS_SR_F (opval);
2249 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2250 }
2251
2252 #undef FLD
2253 }
2254 NEXT (vpc);
2255
2256 CASE (sem, INSN_L_SFEQ) : /* l.sfeq $rA,$rB */
2257 {
2258 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2259 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2260 #define FLD(f) abuf->fields.sfmt_l_sll.f
2261 int UNUSED written = 0;
2262 IADDR UNUSED pc = abuf->addr;
2263 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2264
2265 {
2266 USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2267 SET_H_SYS_SR_F (opval);
2268 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2269 }
2270
2271 #undef FLD
2272 }
2273 NEXT (vpc);
2274
2275 CASE (sem, INSN_L_SFEQI) : /* l.sfeqi $rA,$simm16 */
2276 {
2277 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2278 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2279 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2280 int UNUSED written = 0;
2281 IADDR UNUSED pc = abuf->addr;
2282 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2283
2284 {
2285 USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2286 SET_H_SYS_SR_F (opval);
2287 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2288 }
2289
2290 #undef FLD
2291 }
2292 NEXT (vpc);
2293
2294 CASE (sem, INSN_L_SFNE) : /* l.sfne $rA,$rB */
2295 {
2296 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2297 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2298 #define FLD(f) abuf->fields.sfmt_l_sll.f
2299 int UNUSED written = 0;
2300 IADDR UNUSED pc = abuf->addr;
2301 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2302
2303 {
2304 USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
2305 SET_H_SYS_SR_F (opval);
2306 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2307 }
2308
2309 #undef FLD
2310 }
2311 NEXT (vpc);
2312
2313 CASE (sem, INSN_L_SFNEI) : /* l.sfnei $rA,$simm16 */
2314 {
2315 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2316 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2317 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2318 int UNUSED written = 0;
2319 IADDR UNUSED pc = abuf->addr;
2320 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2321
2322 {
2323 USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
2324 SET_H_SYS_SR_F (opval);
2325 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2326 }
2327
2328 #undef FLD
2329 }
2330 NEXT (vpc);
2331
2332 CASE (sem, INSN_L_MAC) : /* l.mac $rA,$rB */
2333 {
2334 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2335 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2336 #define FLD(f) abuf->fields.sfmt_l_sll.f
2337 int UNUSED written = 0;
2338 IADDR UNUSED pc = abuf->addr;
2339 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2340
2341 {
2342 {
2343 DI tmp_prod;
2344 DI tmp_mac;
2345 DI tmp_result;
2346 tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3))));
2347 tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
2348 tmp_result = ADDDI (tmp_prod, tmp_mac);
2349 {
2350 SI opval = SUBWORDDISI (tmp_result, 0);
2351 SET_H_MAC_MACHI (opval);
2352 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
2353 }
2354 {
2355 SI opval = SUBWORDDISI (tmp_result, 1);
2356 SET_H_MAC_MACLO (opval);
2357 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
2358 }
2359 {
2360 BI opval = ADDOFDI (tmp_prod, tmp_mac, 0);
2361 SET_H_SYS_SR_OV (opval);
2362 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
2363 }
2364 }
2365 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
2366 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
2367 }
2368 }
2369
2370 #undef FLD
2371 }
2372 NEXT (vpc);
2373
2374 CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */
2375 {
2376 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2377 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2378 #define FLD(f) abuf->fields.sfmt_l_lwz.f
2379 int UNUSED written = 0;
2380 IADDR UNUSED pc = abuf->addr;
2381 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2382
2383 {
2384 {
2385 DI tmp_prod;
2386 DI tmp_mac;
2387 DI tmp_result;
2388 tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (FLD (f_simm16)));
2389 tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
2390 tmp_result = ADDDI (tmp_mac, tmp_prod);
2391 {
2392 SI opval = SUBWORDDISI (tmp_result, 0);
2393 SET_H_MAC_MACHI (opval);
2394 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
2395 }
2396 {
2397 SI opval = SUBWORDDISI (tmp_result, 1);
2398 SET_H_MAC_MACLO (opval);
2399 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
2400 }
2401 {
2402 BI opval = ADDOFDI (tmp_prod, tmp_mac, 0);
2403 SET_H_SYS_SR_OV (opval);
2404 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
2405 }
2406 }
2407 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
2408 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
2409 }
2410 }
2411
2412 #undef FLD
2413 }
2414 NEXT (vpc);
2415
2416 CASE (sem, INSN_L_MACU) : /* l.macu $rA,$rB */
2417 {
2418 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2419 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2420 #define FLD(f) abuf->fields.sfmt_l_sll.f
2421 int UNUSED written = 0;
2422 IADDR UNUSED pc = abuf->addr;
2423 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2424
2425 {
2426 {
2427 DI tmp_prod;
2428 DI tmp_mac;
2429 DI tmp_result;
2430 tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3))));
2431 tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
2432 tmp_result = ADDDI (tmp_prod, tmp_mac);
2433 {
2434 SI opval = SUBWORDDISI (tmp_result, 0);
2435 SET_H_MAC_MACHI (opval);
2436 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
2437 }
2438 {
2439 SI opval = SUBWORDDISI (tmp_result, 1);
2440 SET_H_MAC_MACLO (opval);
2441 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
2442 }
2443 {
2444 BI opval = ADDCFDI (tmp_prod, tmp_mac, 0);
2445 SET_H_SYS_SR_CY (opval);
2446 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
2447 }
2448 }
2449 if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
2450 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
2451 }
2452 }
2453
2454 #undef FLD
2455 }
2456 NEXT (vpc);
2457
2458 CASE (sem, INSN_L_MSB) : /* l.msb $rA,$rB */
2459 {
2460 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2461 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2462 #define FLD(f) abuf->fields.sfmt_l_sll.f
2463 int UNUSED written = 0;
2464 IADDR UNUSED pc = abuf->addr;
2465 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2466
2467 {
2468 {
2469 DI tmp_prod;
2470 DI tmp_mac;
2471 DI tmp_result;
2472 tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3))));
2473 tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
2474 tmp_result = SUBDI (tmp_mac, tmp_prod);
2475 {
2476 SI opval = SUBWORDDISI (tmp_result, 0);
2477 SET_H_MAC_MACHI (opval);
2478 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
2479 }
2480 {
2481 SI opval = SUBWORDDISI (tmp_result, 1);
2482 SET_H_MAC_MACLO (opval);
2483 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
2484 }
2485 {
2486 BI opval = SUBOFDI (tmp_mac, tmp_result, 0);
2487 SET_H_SYS_SR_OV (opval);
2488 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
2489 }
2490 }
2491 if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
2492 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
2493 }
2494 }
2495
2496 #undef FLD
2497 }
2498 NEXT (vpc);
2499
2500 CASE (sem, INSN_L_MSBU) : /* l.msbu $rA,$rB */
2501 {
2502 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2503 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2504 #define FLD(f) abuf->fields.sfmt_l_sll.f
2505 int UNUSED written = 0;
2506 IADDR UNUSED pc = abuf->addr;
2507 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2508
2509 {
2510 {
2511 DI tmp_prod;
2512 DI tmp_mac;
2513 DI tmp_result;
2514 tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3))));
2515 tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ());
2516 tmp_result = SUBDI (tmp_mac, tmp_prod);
2517 {
2518 SI opval = SUBWORDDISI (tmp_result, 0);
2519 SET_H_MAC_MACHI (opval);
2520 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
2521 }
2522 {
2523 SI opval = SUBWORDDISI (tmp_result, 1);
2524 SET_H_MAC_MACLO (opval);
2525 CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
2526 }
2527 {
2528 BI opval = SUBCFDI (tmp_mac, tmp_result, 0);
2529 SET_H_SYS_SR_CY (opval);
2530 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
2531 }
2532 }
2533 if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
2534 or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
2535 }
2536 }
2537
2538 #undef FLD
2539 }
2540 NEXT (vpc);
2541
2542 CASE (sem, INSN_L_CUST1) : /* l.cust1 */
2543 {
2544 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2545 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2546 #define FLD(f) abuf->fields.sfmt_empty.f
2547 int UNUSED written = 0;
2548 IADDR UNUSED pc = abuf->addr;
2549 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2550
2551 ((void) 0); /*nop*/
2552
2553 #undef FLD
2554 }
2555 NEXT (vpc);
2556
2557 CASE (sem, INSN_L_CUST2) : /* l.cust2 */
2558 {
2559 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2560 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2561 #define FLD(f) abuf->fields.sfmt_empty.f
2562 int UNUSED written = 0;
2563 IADDR UNUSED pc = abuf->addr;
2564 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2565
2566 ((void) 0); /*nop*/
2567
2568 #undef FLD
2569 }
2570 NEXT (vpc);
2571
2572 CASE (sem, INSN_L_CUST3) : /* l.cust3 */
2573 {
2574 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2575 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2576 #define FLD(f) abuf->fields.sfmt_empty.f
2577 int UNUSED written = 0;
2578 IADDR UNUSED pc = abuf->addr;
2579 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2580
2581 ((void) 0); /*nop*/
2582
2583 #undef FLD
2584 }
2585 NEXT (vpc);
2586
2587 CASE (sem, INSN_L_CUST4) : /* l.cust4 */
2588 {
2589 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2590 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2591 #define FLD(f) abuf->fields.sfmt_empty.f
2592 int UNUSED written = 0;
2593 IADDR UNUSED pc = abuf->addr;
2594 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2595
2596 ((void) 0); /*nop*/
2597
2598 #undef FLD
2599 }
2600 NEXT (vpc);
2601
2602 CASE (sem, INSN_L_CUST5) : /* l.cust5 */
2603 {
2604 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2605 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2606 #define FLD(f) abuf->fields.sfmt_empty.f
2607 int UNUSED written = 0;
2608 IADDR UNUSED pc = abuf->addr;
2609 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2610
2611 ((void) 0); /*nop*/
2612
2613 #undef FLD
2614 }
2615 NEXT (vpc);
2616
2617 CASE (sem, INSN_L_CUST6) : /* l.cust6 */
2618 {
2619 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2620 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2621 #define FLD(f) abuf->fields.sfmt_empty.f
2622 int UNUSED written = 0;
2623 IADDR UNUSED pc = abuf->addr;
2624 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2625
2626 ((void) 0); /*nop*/
2627
2628 #undef FLD
2629 }
2630 NEXT (vpc);
2631
2632 CASE (sem, INSN_L_CUST7) : /* l.cust7 */
2633 {
2634 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2635 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2636 #define FLD(f) abuf->fields.sfmt_empty.f
2637 int UNUSED written = 0;
2638 IADDR UNUSED pc = abuf->addr;
2639 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2640
2641 ((void) 0); /*nop*/
2642
2643 #undef FLD
2644 }
2645 NEXT (vpc);
2646
2647 CASE (sem, INSN_L_CUST8) : /* l.cust8 */
2648 {
2649 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2650 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2651 #define FLD(f) abuf->fields.sfmt_empty.f
2652 int UNUSED written = 0;
2653 IADDR UNUSED pc = abuf->addr;
2654 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2655
2656 ((void) 0); /*nop*/
2657
2658 #undef FLD
2659 }
2660 NEXT (vpc);
2661
2662 CASE (sem, INSN_LF_ADD_S) : /* lf.add.s $rDSF,$rASF,$rBSF */
2663 {
2664 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2665 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2666 #define FLD(f) abuf->fields.sfmt_l_sll.f
2667 int UNUSED written = 0;
2668 IADDR UNUSED pc = abuf->addr;
2669 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2670
2671 {
2672 SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2673 SET_H_FSR (FLD (f_r1), opval);
2674 CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2675 }
2676
2677 #undef FLD
2678 }
2679 NEXT (vpc);
2680
2681 CASE (sem, INSN_LF_ADD_D32) : /* lf.add.d $rDD32F,$rAD32F,$rBD32F */
2682 {
2683 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2684 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2685 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2686 int UNUSED written = 0;
2687 IADDR UNUSED pc = abuf->addr;
2688 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2689
2690 {
2691 DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
2692 SET_H_FD32R (FLD (f_rdd32), opval);
2693 CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
2694 }
2695
2696 #undef FLD
2697 }
2698 NEXT (vpc);
2699
2700 CASE (sem, INSN_LF_SUB_S) : /* lf.sub.s $rDSF,$rASF,$rBSF */
2701 {
2702 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2703 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2704 #define FLD(f) abuf->fields.sfmt_l_sll.f
2705 int UNUSED written = 0;
2706 IADDR UNUSED pc = abuf->addr;
2707 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2708
2709 {
2710 SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2711 SET_H_FSR (FLD (f_r1), opval);
2712 CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2713 }
2714
2715 #undef FLD
2716 }
2717 NEXT (vpc);
2718
2719 CASE (sem, INSN_LF_SUB_D32) : /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
2720 {
2721 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2722 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2723 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2724 int UNUSED written = 0;
2725 IADDR UNUSED pc = abuf->addr;
2726 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2727
2728 {
2729 DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
2730 SET_H_FD32R (FLD (f_rdd32), opval);
2731 CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
2732 }
2733
2734 #undef FLD
2735 }
2736 NEXT (vpc);
2737
2738 CASE (sem, INSN_LF_MUL_S) : /* lf.mul.s $rDSF,$rASF,$rBSF */
2739 {
2740 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2741 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2742 #define FLD(f) abuf->fields.sfmt_l_sll.f
2743 int UNUSED written = 0;
2744 IADDR UNUSED pc = abuf->addr;
2745 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2746
2747 {
2748 SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2749 SET_H_FSR (FLD (f_r1), opval);
2750 CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2751 }
2752
2753 #undef FLD
2754 }
2755 NEXT (vpc);
2756
2757 CASE (sem, INSN_LF_MUL_D32) : /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
2758 {
2759 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2760 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2761 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2762 int UNUSED written = 0;
2763 IADDR UNUSED pc = abuf->addr;
2764 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2765
2766 {
2767 DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
2768 SET_H_FD32R (FLD (f_rdd32), opval);
2769 CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
2770 }
2771
2772 #undef FLD
2773 }
2774 NEXT (vpc);
2775
2776 CASE (sem, INSN_LF_DIV_S) : /* lf.div.s $rDSF,$rASF,$rBSF */
2777 {
2778 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2779 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2780 #define FLD(f) abuf->fields.sfmt_l_sll.f
2781 int UNUSED written = 0;
2782 IADDR UNUSED pc = abuf->addr;
2783 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2784
2785 {
2786 SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2787 SET_H_FSR (FLD (f_r1), opval);
2788 CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2789 }
2790
2791 #undef FLD
2792 }
2793 NEXT (vpc);
2794
2795 CASE (sem, INSN_LF_DIV_D32) : /* lf.div.d $rDD32F,$rAD32F,$rBD32F */
2796 {
2797 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2798 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2799 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2800 int UNUSED written = 0;
2801 IADDR UNUSED pc = abuf->addr;
2802 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2803
2804 {
2805 DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
2806 SET_H_FD32R (FLD (f_rdd32), opval);
2807 CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
2808 }
2809
2810 #undef FLD
2811 }
2812 NEXT (vpc);
2813
2814 CASE (sem, INSN_LF_REM_S) : /* lf.rem.s $rDSF,$rASF,$rBSF */
2815 {
2816 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2817 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2818 #define FLD(f) abuf->fields.sfmt_l_sll.f
2819 int UNUSED written = 0;
2820 IADDR UNUSED pc = abuf->addr;
2821 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2822
2823 {
2824 SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2825 SET_H_FSR (FLD (f_r1), opval);
2826 CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2827 }
2828
2829 #undef FLD
2830 }
2831 NEXT (vpc);
2832
2833 CASE (sem, INSN_LF_REM_D32) : /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
2834 {
2835 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2836 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2837 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2838 int UNUSED written = 0;
2839 IADDR UNUSED pc = abuf->addr;
2840 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2841
2842 {
2843 DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
2844 SET_H_FD32R (FLD (f_rdd32), opval);
2845 CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
2846 }
2847
2848 #undef FLD
2849 }
2850 NEXT (vpc);
2851
2852 CASE (sem, INSN_LF_ITOF_S) : /* lf.itof.s $rDSF,$rA */
2853 {
2854 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2855 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2856 #define FLD(f) abuf->fields.sfmt_l_slli.f
2857 int UNUSED written = 0;
2858 IADDR UNUSED pc = abuf->addr;
2859 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2860
2861 {
2862 SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2))));
2863 SET_H_FSR (FLD (f_r1), opval);
2864 CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
2865 }
2866
2867 #undef FLD
2868 }
2869 NEXT (vpc);
2870
2871 CASE (sem, INSN_LF_ITOF_D32) : /* lf.itof.d $rDD32F,$rADI */
2872 {
2873 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2874 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2875 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2876 int UNUSED written = 0;
2877 IADDR UNUSED pc = abuf->addr;
2878 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2879
2880 {
2881 DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_rad32)));
2882 SET_H_FD32R (FLD (f_rdd32), opval);
2883 CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
2884 }
2885
2886 #undef FLD
2887 }
2888 NEXT (vpc);
2889
2890 CASE (sem, INSN_LF_FTOI_S) : /* lf.ftoi.s $rD,$rASF */
2891 {
2892 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2893 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2894 #define FLD(f) abuf->fields.sfmt_l_slli.f
2895 int UNUSED written = 0;
2896 IADDR UNUSED pc = abuf->addr;
2897 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2898
2899 {
2900 SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2))));
2901 SET_H_GPR (FLD (f_r1), opval);
2902 CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
2903 }
2904
2905 #undef FLD
2906 }
2907 NEXT (vpc);
2908
2909 CASE (sem, INSN_LF_FTOI_D32) : /* lf.ftoi.d $rDDI,$rAD32F */
2910 {
2911 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2912 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2913 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2914 int UNUSED written = 0;
2915 IADDR UNUSED pc = abuf->addr;
2916 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2917
2918 {
2919 DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_rad32)));
2920 SET_H_I64R (FLD (f_rdd32), opval);
2921 CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval);
2922 }
2923
2924 #undef FLD
2925 }
2926 NEXT (vpc);
2927
2928 CASE (sem, INSN_LF_SFEQ_S) : /* lf.sfeq.s $rASF,$rBSF */
2929 {
2930 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2931 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2932 #define FLD(f) abuf->fields.sfmt_l_sll.f
2933 int UNUSED written = 0;
2934 IADDR UNUSED pc = abuf->addr;
2935 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2936
2937 {
2938 BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2939 SET_H_SYS_SR_F (opval);
2940 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2941 }
2942
2943 #undef FLD
2944 }
2945 NEXT (vpc);
2946
2947 CASE (sem, INSN_LF_SFEQ_D32) : /* lf.sfeq.d $rAD32F,$rBD32F */
2948 {
2949 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2950 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2951 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2952 int UNUSED written = 0;
2953 IADDR UNUSED pc = abuf->addr;
2954 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2955
2956 {
2957 BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
2958 SET_H_SYS_SR_F (opval);
2959 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2960 }
2961
2962 #undef FLD
2963 }
2964 NEXT (vpc);
2965
2966 CASE (sem, INSN_LF_SFNE_S) : /* lf.sfne.s $rASF,$rBSF */
2967 {
2968 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2969 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2970 #define FLD(f) abuf->fields.sfmt_l_sll.f
2971 int UNUSED written = 0;
2972 IADDR UNUSED pc = abuf->addr;
2973 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2974
2975 {
2976 BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
2977 SET_H_SYS_SR_F (opval);
2978 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2979 }
2980
2981 #undef FLD
2982 }
2983 NEXT (vpc);
2984
2985 CASE (sem, INSN_LF_SFNE_D32) : /* lf.sfne.d $rAD32F,$rBD32F */
2986 {
2987 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2988 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2989 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
2990 int UNUSED written = 0;
2991 IADDR UNUSED pc = abuf->addr;
2992 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2993
2994 {
2995 BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
2996 SET_H_SYS_SR_F (opval);
2997 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
2998 }
2999
3000 #undef FLD
3001 }
3002 NEXT (vpc);
3003
3004 CASE (sem, INSN_LF_SFGE_S) : /* lf.sfge.s $rASF,$rBSF */
3005 {
3006 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3007 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3008 #define FLD(f) abuf->fields.sfmt_l_sll.f
3009 int UNUSED written = 0;
3010 IADDR UNUSED pc = abuf->addr;
3011 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3012
3013 {
3014 BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
3015 SET_H_SYS_SR_F (opval);
3016 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3017 }
3018
3019 #undef FLD
3020 }
3021 NEXT (vpc);
3022
3023 CASE (sem, INSN_LF_SFGE_D32) : /* lf.sfge.d $rAD32F,$rBD32F */
3024 {
3025 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3026 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3027 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3028 int UNUSED written = 0;
3029 IADDR UNUSED pc = abuf->addr;
3030 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3031
3032 {
3033 BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
3034 SET_H_SYS_SR_F (opval);
3035 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3036 }
3037
3038 #undef FLD
3039 }
3040 NEXT (vpc);
3041
3042 CASE (sem, INSN_LF_SFGT_S) : /* lf.sfgt.s $rASF,$rBSF */
3043 {
3044 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3045 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3046 #define FLD(f) abuf->fields.sfmt_l_sll.f
3047 int UNUSED written = 0;
3048 IADDR UNUSED pc = abuf->addr;
3049 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3050
3051 {
3052 BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
3053 SET_H_SYS_SR_F (opval);
3054 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3055 }
3056
3057 #undef FLD
3058 }
3059 NEXT (vpc);
3060
3061 CASE (sem, INSN_LF_SFGT_D32) : /* lf.sfgt.d $rAD32F,$rBD32F */
3062 {
3063 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3064 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3065 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3066 int UNUSED written = 0;
3067 IADDR UNUSED pc = abuf->addr;
3068 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3069
3070 {
3071 BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
3072 SET_H_SYS_SR_F (opval);
3073 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3074 }
3075
3076 #undef FLD
3077 }
3078 NEXT (vpc);
3079
3080 CASE (sem, INSN_LF_SFLT_S) : /* lf.sflt.s $rASF,$rBSF */
3081 {
3082 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3083 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3084 #define FLD(f) abuf->fields.sfmt_l_sll.f
3085 int UNUSED written = 0;
3086 IADDR UNUSED pc = abuf->addr;
3087 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3088
3089 {
3090 BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
3091 SET_H_SYS_SR_F (opval);
3092 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3093 }
3094
3095 #undef FLD
3096 }
3097 NEXT (vpc);
3098
3099 CASE (sem, INSN_LF_SFLT_D32) : /* lf.sflt.d $rAD32F,$rBD32F */
3100 {
3101 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3102 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3103 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3104 int UNUSED written = 0;
3105 IADDR UNUSED pc = abuf->addr;
3106 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3107
3108 {
3109 BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
3110 SET_H_SYS_SR_F (opval);
3111 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3112 }
3113
3114 #undef FLD
3115 }
3116 NEXT (vpc);
3117
3118 CASE (sem, INSN_LF_SFLE_S) : /* lf.sfle.s $rASF,$rBSF */
3119 {
3120 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3121 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3122 #define FLD(f) abuf->fields.sfmt_l_sll.f
3123 int UNUSED written = 0;
3124 IADDR UNUSED pc = abuf->addr;
3125 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3126
3127 {
3128 BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
3129 SET_H_SYS_SR_F (opval);
3130 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3131 }
3132
3133 #undef FLD
3134 }
3135 NEXT (vpc);
3136
3137 CASE (sem, INSN_LF_SFLE_D32) : /* lf.sfle.d $rAD32F,$rBD32F */
3138 {
3139 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3140 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3141 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3142 int UNUSED written = 0;
3143 IADDR UNUSED pc = abuf->addr;
3144 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3145
3146 {
3147 BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
3148 SET_H_SYS_SR_F (opval);
3149 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3150 }
3151
3152 #undef FLD
3153 }
3154 NEXT (vpc);
3155
3156 CASE (sem, INSN_LF_SFUEQ_S) : /* lf.sfueq.s $rASF,$rBSF */
3157 {
3158 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3159 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3160 #define FLD(f) abuf->fields.sfmt_l_sll.f
3161 int UNUSED written = 0;
3162 IADDR UNUSED pc = abuf->addr;
3163 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3164
3165 {
3166 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
3167 SET_H_SYS_SR_F (opval);
3168 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3169 }
3170
3171 #undef FLD
3172 }
3173 NEXT (vpc);
3174
3175 CASE (sem, INSN_LF_SFUEQ_D32) : /* lf.sfueq.d $rAD32F,$rBD32F */
3176 {
3177 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3178 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3179 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3180 int UNUSED written = 0;
3181 IADDR UNUSED pc = abuf->addr;
3182 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3183
3184 {
3185 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
3186 SET_H_SYS_SR_F (opval);
3187 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3188 }
3189
3190 #undef FLD
3191 }
3192 NEXT (vpc);
3193
3194 CASE (sem, INSN_LF_SFUNE_S) : /* lf.sfune.s $rASF,$rBSF */
3195 {
3196 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3197 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3198 #define FLD(f) abuf->fields.sfmt_l_sll.f
3199 int UNUSED written = 0;
3200 IADDR UNUSED pc = abuf->addr;
3201 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3202
3203 {
3204 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
3205 SET_H_SYS_SR_F (opval);
3206 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3207 }
3208
3209 #undef FLD
3210 }
3211 NEXT (vpc);
3212
3213 CASE (sem, INSN_LF_SFUNE_D32) : /* lf.sfune.d $rAD32F,$rBD32F */
3214 {
3215 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3216 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3217 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3218 int UNUSED written = 0;
3219 IADDR UNUSED pc = abuf->addr;
3220 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3221
3222 {
3223 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
3224 SET_H_SYS_SR_F (opval);
3225 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3226 }
3227
3228 #undef FLD
3229 }
3230 NEXT (vpc);
3231
3232 CASE (sem, INSN_LF_SFUGT_S) : /* lf.sfugt.s $rASF,$rBSF */
3233 {
3234 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3235 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3236 #define FLD(f) abuf->fields.sfmt_l_sll.f
3237 int UNUSED written = 0;
3238 IADDR UNUSED pc = abuf->addr;
3239 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3240
3241 {
3242 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
3243 SET_H_SYS_SR_F (opval);
3244 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3245 }
3246
3247 #undef FLD
3248 }
3249 NEXT (vpc);
3250
3251 CASE (sem, INSN_LF_SFUGT_D32) : /* lf.sfugt.d $rAD32F,$rBD32F */
3252 {
3253 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3254 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3255 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3256 int UNUSED written = 0;
3257 IADDR UNUSED pc = abuf->addr;
3258 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3259
3260 {
3261 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
3262 SET_H_SYS_SR_F (opval);
3263 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3264 }
3265
3266 #undef FLD
3267 }
3268 NEXT (vpc);
3269
3270 CASE (sem, INSN_LF_SFUGE_S) : /* lf.sfuge.s $rASF,$rBSF */
3271 {
3272 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3273 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3274 #define FLD(f) abuf->fields.sfmt_l_sll.f
3275 int UNUSED written = 0;
3276 IADDR UNUSED pc = abuf->addr;
3277 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3278
3279 {
3280 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
3281 SET_H_SYS_SR_F (opval);
3282 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3283 }
3284
3285 #undef FLD
3286 }
3287 NEXT (vpc);
3288
3289 CASE (sem, INSN_LF_SFUGE_D32) : /* lf.sfuge.d $rAD32F,$rBD32F */
3290 {
3291 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3292 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3293 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3294 int UNUSED written = 0;
3295 IADDR UNUSED pc = abuf->addr;
3296 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3297
3298 {
3299 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
3300 SET_H_SYS_SR_F (opval);
3301 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3302 }
3303
3304 #undef FLD
3305 }
3306 NEXT (vpc);
3307
3308 CASE (sem, INSN_LF_SFULT_S) : /* lf.sfult.s $rASF,$rBSF */
3309 {
3310 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3311 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3312 #define FLD(f) abuf->fields.sfmt_l_sll.f
3313 int UNUSED written = 0;
3314 IADDR UNUSED pc = abuf->addr;
3315 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3316
3317 {
3318 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
3319 SET_H_SYS_SR_F (opval);
3320 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3321 }
3322
3323 #undef FLD
3324 }
3325 NEXT (vpc);
3326
3327 CASE (sem, INSN_LF_SFULT_D32) : /* lf.sfult.d $rAD32F,$rBD32F */
3328 {
3329 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3330 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3331 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3332 int UNUSED written = 0;
3333 IADDR UNUSED pc = abuf->addr;
3334 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3335
3336 {
3337 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
3338 SET_H_SYS_SR_F (opval);
3339 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3340 }
3341
3342 #undef FLD
3343 }
3344 NEXT (vpc);
3345
3346 CASE (sem, INSN_LF_SFULE_S) : /* lf.sfule.s $rASF,$rBSF */
3347 {
3348 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3349 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3350 #define FLD(f) abuf->fields.sfmt_l_sll.f
3351 int UNUSED written = 0;
3352 IADDR UNUSED pc = abuf->addr;
3353 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3354
3355 {
3356 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))));
3357 SET_H_SYS_SR_F (opval);
3358 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3359 }
3360
3361 #undef FLD
3362 }
3363 NEXT (vpc);
3364
3365 CASE (sem, INSN_LF_SFULE_D32) : /* lf.sfule.d $rAD32F,$rBD32F */
3366 {
3367 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3368 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3369 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3370 int UNUSED written = 0;
3371 IADDR UNUSED pc = abuf->addr;
3372 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3373
3374 {
3375 BI opval = ORBI (CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))));
3376 SET_H_SYS_SR_F (opval);
3377 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3378 }
3379
3380 #undef FLD
3381 }
3382 NEXT (vpc);
3383
3384 CASE (sem, INSN_LF_SFUN_S) : /* lf.sfun.s $rASF,$rBSF */
3385 {
3386 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3387 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3388 #define FLD(f) abuf->fields.sfmt_l_sll.f
3389 int UNUSED written = 0;
3390 IADDR UNUSED pc = abuf->addr;
3391 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3392
3393 {
3394 BI opval = CGEN_CPU_FPU (current_cpu)->ops->unorderedsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
3395 SET_H_SYS_SR_F (opval);
3396 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3397 }
3398
3399 #undef FLD
3400 }
3401 NEXT (vpc);
3402
3403 CASE (sem, INSN_LF_SFUN_D32) : /* lf.sfun.d $rAD32F,$rBD32F */
3404 {
3405 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3406 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3407 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3408 int UNUSED written = 0;
3409 IADDR UNUSED pc = abuf->addr;
3410 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3411
3412 {
3413 BI opval = CGEN_CPU_FPU (current_cpu)->ops->unordereddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32)));
3414 SET_H_SYS_SR_F (opval);
3415 CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
3416 }
3417
3418 #undef FLD
3419 }
3420 NEXT (vpc);
3421
3422 CASE (sem, INSN_LF_MADD_S) : /* lf.madd.s $rDSF,$rASF,$rBSF */
3423 {
3424 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3425 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3426 #define FLD(f) abuf->fields.sfmt_l_sll.f
3427 int UNUSED written = 0;
3428 IADDR UNUSED pc = abuf->addr;
3429 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3430
3431 {
3432 SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1)));
3433 SET_H_FSR (FLD (f_r1), opval);
3434 CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
3435 }
3436
3437 #undef FLD
3438 }
3439 NEXT (vpc);
3440
3441 CASE (sem, INSN_LF_MADD_D32) : /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
3442 {
3443 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3444 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3445 #define FLD(f) abuf->fields.sfmt_lf_add_d32.f
3446 int UNUSED written = 0;
3447 IADDR UNUSED pc = abuf->addr;
3448 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3449
3450 {
3451 DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_rad32)), GET_H_FD32R (FLD (f_rbd32))), GET_H_FD32R (FLD (f_rdd32)));
3452 SET_H_FD32R (FLD (f_rdd32), opval);
3453 CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
3454 }
3455
3456 #undef FLD
3457 }
3458 NEXT (vpc);
3459
3460 CASE (sem, INSN_LF_CUST1_S) : /* lf.cust1.s $rASF,$rBSF */
3461 {
3462 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3463 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3464 #define FLD(f) abuf->fields.sfmt_empty.f
3465 int UNUSED written = 0;
3466 IADDR UNUSED pc = abuf->addr;
3467 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3468
3469 ((void) 0); /*nop*/
3470
3471 #undef FLD
3472 }
3473 NEXT (vpc);
3474
3475 CASE (sem, INSN_LF_CUST1_D32) : /* lf.cust1.d */
3476 {
3477 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3478 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3479 #define FLD(f) abuf->fields.sfmt_empty.f
3480 int UNUSED written = 0;
3481 IADDR UNUSED pc = abuf->addr;
3482 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3483
3484 ((void) 0); /*nop*/
3485
3486 #undef FLD
3487 }
3488 NEXT (vpc);
3489
3490
3491 }
3492 ENDSWITCH (sem) /* End of semantic switch. */
3493
3494 /* At this point `vpc' contains the next insn to execute. */
3495 }
3496
3497 #undef DEFINE_SWITCH
3498 #endif /* DEFINE_SWITCH */
The GNU Binutils are a collection of binary tools.