sim/mcore/mcore-sim.h

   1 /* Simulator for Motorola's MCore processor
   2    Copyright (C) 2009-2024 Free Software Foundation, Inc.
   3
   4 This file is part of the GNU simulators.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef MCORE_SIM_H
  20 #define MCORE_SIM_H
  21
  22 #include <stdint.h>
  23
  24 /* The machine state.
  25    This state is maintained in host byte order.  The
  26    fetch/store register functions must translate between host
  27    byte order and the target processor byte order.
  28    Keeping this data in target byte order simplifies the register
  29    read/write functions.  Keeping this data in native order improves
  30    the performance of the simulator.  Simulation speed is deemed more
  31    important.  */
  32
  33 /* The ordering of the mcore_regset structure is matched in the
  34    gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro.  */
  35 struct mcore_regset
  36 {
  37   int32_t gregs[16];            /* primary registers */
  38   int32_t alt_gregs[16];        /* alt register file */
  39   int32_t cregs[32];            /* control registers */
  40   int32_t pc;
  41 };
  42 #define LAST_VALID_CREG 32              /* only 0..12 implemented */
  43 #define NUM_MCORE_REGS  (16 + 16 + LAST_VALID_CREG + 1)
  44
  45 struct mcore_sim_cpu {
  46   union
  47   {
  48     struct mcore_regset regs;
  49     /* Used by the fetch/store reg helpers to access registers linearly.  */
  50     int32_t asints[NUM_MCORE_REGS];
  51   };
  52
  53   /* Used to switch between gregs/alt_gregs based on the control state.  */
  54   int32_t *active_gregs;
  55
  56   int ticks;
  57   int stalls;
  58   int cycles;
  59   int insts;
  60 };
  61
  62 #define MCORE_SIM_CPU(cpu) ((struct mcore_sim_cpu *) CPU_ARCH_DATA (cpu))
  63
  64 #endif