1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2024 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
42 typedef struct instr_info instr_info
;
44 static bool dofloat (instr_info
*, int);
45 static int putop (instr_info
*, const char *, int);
46 static void oappend_with_style (instr_info
*, const char *,
47 enum disassembler_style
);
49 static bool OP_E (instr_info
*, int, int);
50 static bool OP_E_memory (instr_info
*, int, int);
51 static bool OP_indirE (instr_info
*, int, int);
52 static bool OP_G (instr_info
*, int, int);
53 static bool OP_ST (instr_info
*, int, int);
54 static bool OP_STi (instr_info
*, int, int);
55 static bool OP_Skip_MODRM (instr_info
*, int, int);
56 static bool OP_REG (instr_info
*, int, int);
57 static bool OP_IMREG (instr_info
*, int, int);
58 static bool OP_I (instr_info
*, int, int);
59 static bool OP_I64 (instr_info
*, int, int);
60 static bool OP_sI (instr_info
*, int, int);
61 static bool OP_J (instr_info
*, int, int);
62 static bool OP_SEG (instr_info
*, int, int);
63 static bool OP_DIR (instr_info
*, int, int);
64 static bool OP_OFF (instr_info
*, int, int);
65 static bool OP_OFF64 (instr_info
*, int, int);
66 static bool OP_ESreg (instr_info
*, int, int);
67 static bool OP_DSreg (instr_info
*, int, int);
68 static bool OP_C (instr_info
*, int, int);
69 static bool OP_D (instr_info
*, int, int);
70 static bool OP_T (instr_info
*, int, int);
71 static bool OP_MMX (instr_info
*, int, int);
72 static bool OP_XMM (instr_info
*, int, int);
73 static bool OP_EM (instr_info
*, int, int);
74 static bool OP_EX (instr_info
*, int, int);
75 static bool OP_EMC (instr_info
*, int,int);
76 static bool OP_MXC (instr_info
*, int,int);
77 static bool OP_R (instr_info
*, int, int);
78 static bool OP_M (instr_info
*, int, int);
79 static bool OP_VEX (instr_info
*, int, int);
80 static bool OP_VexR (instr_info
*, int, int);
81 static bool OP_VexW (instr_info
*, int, int);
82 static bool OP_Rounding (instr_info
*, int, int);
83 static bool OP_REG_VexI4 (instr_info
*, int, int);
84 static bool OP_VexI4 (instr_info
*, int, int);
85 static bool OP_0f07 (instr_info
*, int, int);
86 static bool OP_Monitor (instr_info
*, int, int);
87 static bool OP_Mwait (instr_info
*, int, int);
89 static bool PCLMUL_Fixup (instr_info
*, int, int);
90 static bool VPCMP_Fixup (instr_info
*, int, int);
91 static bool VPCOM_Fixup (instr_info
*, int, int);
92 static bool NOP_Fixup (instr_info
*, int, int);
93 static bool OP_3DNowSuffix (instr_info
*, int, int);
94 static bool CMP_Fixup (instr_info
*, int, int);
95 static bool REP_Fixup (instr_info
*, int, int);
96 static bool SEP_Fixup (instr_info
*, int, int);
97 static bool BND_Fixup (instr_info
*, int, int);
98 static bool NOTRACK_Fixup (instr_info
*, int, int);
99 static bool HLE_Fixup1 (instr_info
*, int, int);
100 static bool HLE_Fixup2 (instr_info
*, int, int);
101 static bool HLE_Fixup3 (instr_info
*, int, int);
102 static bool CMPXCHG8B_Fixup (instr_info
*, int, int);
103 static bool XMM_Fixup (instr_info
*, int, int);
104 static bool FXSAVE_Fixup (instr_info
*, int, int);
105 static bool MOVSXD_Fixup (instr_info
*, int, int);
106 static bool DistinctDest_Fixup (instr_info
*, int, int);
107 static bool PREFETCHI_Fixup (instr_info
*, int, int);
108 static bool PUSH2_POP2_Fixup (instr_info
*, int, int);
109 static bool JMPABS_Fixup (instr_info
*, int, int);
111 static void ATTRIBUTE_PRINTF_3
i386_dis_printf (const disassemble_info
*,
112 enum disassembler_style
,
115 /* This character is used to encode style information within the output
116 buffers. See oappend_insert_style for more details. */
117 #define STYLE_MARKER_CHAR '\002'
119 /* The maximum operand buffer size. */
120 #define MAX_OPERAND_BUFFER_SIZE 128
129 static const char *prefix_name (enum address_mode
, uint8_t, int);
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
156 /* Record W R4 X4 B4 bits for rex2. */
158 /* Bits of rex2 we've already used. */
159 unsigned char rex2_used
;
160 unsigned char rex2_payload
;
163 unsigned char need_vex
;
166 /* Flags for ins->prefixes which we somehow handled when printing the
167 current instruction. */
170 /* Flags for EVEX bits which we somehow handled when printing the
171 current instruction. */
174 char obuf
[MAX_OPERAND_BUFFER_SIZE
];
177 const uint8_t *start_codep
;
179 const uint8_t *end_codep
;
180 unsigned char nr_prefixes
;
181 signed char last_lock_prefix
;
182 signed char last_repz_prefix
;
183 signed char last_repnz_prefix
;
184 signed char last_data_prefix
;
185 signed char last_addr_prefix
;
186 signed char last_rex_prefix
;
187 signed char last_rex2_prefix
;
188 signed char last_seg_prefix
;
189 signed char fwait_prefix
;
190 /* The active segment register prefix. */
191 unsigned char active_seg_prefix
;
193 #define MAX_CODE_LENGTH 15
194 /* We can up to 14 ins->prefixes since the maximum instruction length is
196 uint8_t all_prefixes
[MAX_CODE_LENGTH
- 1];
197 disassemble_info
*info
;
217 int register_specifier
;
220 int mask_register_specifier
;
231 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */
234 enum evex_type evex_type
;
236 /* Remember if the current op is a jump instruction. */
241 /* Record whether EVEX masking is used incorrectly. */
242 bool illegal_masking
;
244 /* Record whether the modrm byte has been skipped. */
245 bool has_skipped_modrm
;
248 signed char op_index
[MAX_OPERANDS
];
249 bool op_riprel
[MAX_OPERANDS
];
250 char *op_out
[MAX_OPERANDS
];
251 bfd_vma op_address
[MAX_OPERANDS
];
254 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
255 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
256 * section of the "Virtual 8086 Mode" chapter.)
257 * 'pc' should be the address of this instruction, it will
258 * be used to print the target address if this is a relative jump or call
259 * The function returns the length of this instruction in bytes.
268 enum x86_64_isa isa64
;
275 /* Indexes first byte not fetched. */
276 unsigned int fetched
;
277 uint8_t the_buffer
[2 * MAX_CODE_LENGTH
- 1];
280 /* Mark parts used in the REX prefix. When we are testing for
281 empty prefix (for 8bit register REX extension), just mask it
282 out. Otherwise test for REX bit is excuse for existence of REX
283 only in case value is nonzero. */
284 #define USED_REX(value) \
288 if (ins->rex & value) \
289 ins->rex_used |= (value) | REX_OPCODE; \
290 if (ins->rex2 & value) \
292 ins->rex2_used |= (value); \
293 ins->rex_used |= REX_OPCODE; \
297 ins->rex_used |= REX_OPCODE; \
301 #define EVEX_b_used 1
302 #define EVEX_len_used 2
305 /* {rex2} is not printed when the REX2_SPECIAL is set. */
306 #define REX2_SPECIAL 16
308 /* Flags stored in PREFIXES. */
309 #define PREFIX_REPZ 1
310 #define PREFIX_REPNZ 2
313 #define PREFIX_DS 0x10
314 #define PREFIX_ES 0x20
315 #define PREFIX_FS 0x40
316 #define PREFIX_GS 0x80
317 #define PREFIX_LOCK 0x100
318 #define PREFIX_DATA 0x200
319 #define PREFIX_ADDR 0x400
320 #define PREFIX_FWAIT 0x800
321 #define PREFIX_REX2 0x1000
322 #define PREFIX_NP_OR_DATA 0x2000
323 #define NO_PREFIX 0x4000
325 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
326 to ADDR (exclusive) are valid. Returns true for success, false
329 fetch_code (struct disassemble_info
*info
, const uint8_t *until
)
332 struct dis_private
*priv
= info
->private_data
;
333 bfd_vma start
= priv
->insn_start
+ priv
->fetched
;
334 uint8_t *fetch_end
= priv
->the_buffer
+ priv
->fetched
;
335 ptrdiff_t needed
= until
- fetch_end
;
340 if (priv
->fetched
+ (size_t) needed
<= ARRAY_SIZE (priv
->the_buffer
))
341 status
= (*info
->read_memory_func
) (start
, fetch_end
, needed
, info
);
344 /* If we did manage to read at least one byte, then
345 print_insn_i386 will do something sensible. Otherwise, print
346 an error. We do that here because this is where we know
349 (*info
->memory_error_func
) (status
, start
, info
);
353 priv
->fetched
+= needed
;
358 fetch_modrm (instr_info
*ins
)
360 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
363 ins
->modrm
.mod
= (*ins
->codep
>> 6) & 3;
364 ins
->modrm
.reg
= (*ins
->codep
>> 3) & 7;
365 ins
->modrm
.rm
= *ins
->codep
& 7;
371 fetch_error (const instr_info
*ins
)
373 /* Getting here means we tried for data but didn't get it. That
374 means we have an incomplete instruction of some sort. Just
375 print the first byte as a prefix or a .byte pseudo-op. */
376 const struct dis_private
*priv
= ins
->info
->private_data
;
377 const char *name
= NULL
;
379 if (ins
->codep
<= priv
->the_buffer
)
382 if (ins
->prefixes
|| ins
->fwait_prefix
>= 0 || (ins
->rex
& REX_OPCODE
))
383 name
= prefix_name (ins
->address_mode
, priv
->the_buffer
[0],
384 priv
->orig_sizeflag
);
386 i386_dis_printf (ins
->info
, dis_style_mnemonic
, "%s", name
);
389 /* Just print the first byte as a .byte instruction. */
390 i386_dis_printf (ins
->info
, dis_style_assembler_directive
, ".byte ");
391 i386_dis_printf (ins
->info
, dis_style_immediate
, "%#x",
392 (unsigned int) priv
->the_buffer
[0]);
398 /* Possible values for prefix requirement. */
399 #define PREFIX_IGNORED_SHIFT 16
400 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
401 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
402 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
403 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
404 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
405 #define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
407 /* Opcode prefixes. */
408 #define PREFIX_OPCODE (PREFIX_REPZ \
412 /* Prefixes ignored. */
413 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
414 | PREFIX_IGNORED_REPNZ \
415 | PREFIX_IGNORED_DATA)
417 #define XX { NULL, 0 }
418 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
420 #define Eb { OP_E, b_mode }
421 #define Ebnd { OP_E, bnd_mode }
422 #define EbS { OP_E, b_swap_mode }
423 #define EbndS { OP_E, bnd_swap_mode }
424 #define Ev { OP_E, v_mode }
425 #define Eva { OP_E, va_mode }
426 #define Ev_bnd { OP_E, v_bnd_mode }
427 #define EvS { OP_E, v_swap_mode }
428 #define Ed { OP_E, d_mode }
429 #define Edq { OP_E, dq_mode }
430 #define Edb { OP_E, db_mode }
431 #define Edw { OP_E, dw_mode }
432 #define Eq { OP_E, q_mode }
433 #define indirEv { OP_indirE, indir_v_mode }
434 #define indirEp { OP_indirE, f_mode }
435 #define stackEv { OP_E, stack_v_mode }
436 #define Em { OP_E, m_mode }
437 #define Ew { OP_E, w_mode }
438 #define M { OP_M, 0 } /* lea, lgdt, etc. */
439 #define Ma { OP_M, a_mode }
440 #define Mb { OP_M, b_mode }
441 #define Md { OP_M, d_mode }
442 #define Mdq { OP_M, dq_mode }
443 #define Mo { OP_M, o_mode }
444 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
445 #define Mq { OP_M, q_mode }
446 #define Mv { OP_M, v_mode }
447 #define Mv_bnd { OP_M, v_bndmk_mode }
448 #define Mw { OP_M, w_mode }
449 #define Mx { OP_M, x_mode }
450 #define Mxmm { OP_M, xmm_mode }
451 #define Mymm { OP_M, ymm_mode }
452 #define Gb { OP_G, b_mode }
453 #define Gbnd { OP_G, bnd_mode }
454 #define Gv { OP_G, v_mode }
455 #define Gd { OP_G, d_mode }
456 #define Gdq { OP_G, dq_mode }
457 #define Gq { OP_G, q_mode }
458 #define Gm { OP_G, m_mode }
459 #define Gva { OP_G, va_mode }
460 #define Gw { OP_G, w_mode }
461 #define Ib { OP_I, b_mode }
462 #define sIb { OP_sI, b_mode } /* sign extened byte */
463 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
464 #define Iv { OP_I, v_mode }
465 #define sIv { OP_sI, v_mode }
466 #define Iv64 { OP_I64, v_mode }
467 #define Id { OP_I, d_mode }
468 #define Iw { OP_I, w_mode }
469 #define I1 { OP_I, const_1_mode }
470 #define Jb { OP_J, b_mode }
471 #define Jv { OP_J, v_mode }
472 #define Jdqw { OP_J, dqw_mode }
473 #define Cm { OP_C, m_mode }
474 #define Dm { OP_D, m_mode }
475 #define Td { OP_T, d_mode }
476 #define Skip_MODRM { OP_Skip_MODRM, 0 }
478 #define RMeAX { OP_REG, eAX_reg }
479 #define RMeBX { OP_REG, eBX_reg }
480 #define RMeCX { OP_REG, eCX_reg }
481 #define RMeDX { OP_REG, eDX_reg }
482 #define RMeSP { OP_REG, eSP_reg }
483 #define RMeBP { OP_REG, eBP_reg }
484 #define RMeSI { OP_REG, eSI_reg }
485 #define RMeDI { OP_REG, eDI_reg }
486 #define RMrAX { OP_REG, rAX_reg }
487 #define RMrBX { OP_REG, rBX_reg }
488 #define RMrCX { OP_REG, rCX_reg }
489 #define RMrDX { OP_REG, rDX_reg }
490 #define RMrSP { OP_REG, rSP_reg }
491 #define RMrBP { OP_REG, rBP_reg }
492 #define RMrSI { OP_REG, rSI_reg }
493 #define RMrDI { OP_REG, rDI_reg }
494 #define RMAL { OP_REG, al_reg }
495 #define RMCL { OP_REG, cl_reg }
496 #define RMDL { OP_REG, dl_reg }
497 #define RMBL { OP_REG, bl_reg }
498 #define RMAH { OP_REG, ah_reg }
499 #define RMCH { OP_REG, ch_reg }
500 #define RMDH { OP_REG, dh_reg }
501 #define RMBH { OP_REG, bh_reg }
502 #define RMAX { OP_REG, ax_reg }
503 #define RMDX { OP_REG, dx_reg }
505 #define eAX { OP_IMREG, eAX_reg }
506 #define AL { OP_IMREG, al_reg }
507 #define CL { OP_IMREG, cl_reg }
508 #define zAX { OP_IMREG, z_mode_ax_reg }
509 #define indirDX { OP_IMREG, indir_dx_reg }
511 #define Sw { OP_SEG, w_mode }
512 #define Sv { OP_SEG, v_mode }
513 #define Ap { OP_DIR, 0 }
514 #define Ob { OP_OFF64, b_mode }
515 #define Ov { OP_OFF64, v_mode }
516 #define Xb { OP_DSreg, eSI_reg }
517 #define Xv { OP_DSreg, eSI_reg }
518 #define Xz { OP_DSreg, eSI_reg }
519 #define Yb { OP_ESreg, eDI_reg }
520 #define Yv { OP_ESreg, eDI_reg }
521 #define DSBX { OP_DSreg, eBX_reg }
523 #define es { OP_REG, es_reg }
524 #define ss { OP_REG, ss_reg }
525 #define cs { OP_REG, cs_reg }
526 #define ds { OP_REG, ds_reg }
527 #define fs { OP_REG, fs_reg }
528 #define gs { OP_REG, gs_reg }
530 #define MX { OP_MMX, 0 }
531 #define XM { OP_XMM, 0 }
532 #define XMScalar { OP_XMM, scalar_mode }
533 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
534 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
535 #define XMM { OP_XMM, xmm_mode }
536 #define TMM { OP_XMM, tmm_mode }
537 #define XMxmmq { OP_XMM, xmmq_mode }
538 #define EM { OP_EM, v_mode }
539 #define EMS { OP_EM, v_swap_mode }
540 #define EMd { OP_EM, d_mode }
541 #define EMx { OP_EM, x_mode }
542 #define EXbwUnit { OP_EX, bw_unit_mode }
543 #define EXb { OP_EX, b_mode }
544 #define EXw { OP_EX, w_mode }
545 #define EXd { OP_EX, d_mode }
546 #define EXdS { OP_EX, d_swap_mode }
547 #define EXwS { OP_EX, w_swap_mode }
548 #define EXq { OP_EX, q_mode }
549 #define EXqS { OP_EX, q_swap_mode }
550 #define EXdq { OP_EX, dq_mode }
551 #define EXx { OP_EX, x_mode }
552 #define EXxh { OP_EX, xh_mode }
553 #define EXxS { OP_EX, x_swap_mode }
554 #define EXxmm { OP_EX, xmm_mode }
555 #define EXymm { OP_EX, ymm_mode }
556 #define EXxmmq { OP_EX, xmmq_mode }
557 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
558 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
559 #define EXxmmdw { OP_EX, xmmdw_mode }
560 #define EXxmmqd { OP_EX, xmmqd_mode }
561 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
562 #define EXymmq { OP_EX, ymmq_mode }
563 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
564 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
565 #define Rd { OP_R, d_mode }
566 #define Rdq { OP_R, dq_mode }
567 #define Rq { OP_R, q_mode }
568 #define Nq { OP_R, q_mm_mode }
569 #define Ux { OP_R, x_mode }
570 #define Uxmm { OP_R, xmm_mode }
571 #define Rxmmq { OP_R, xmmq_mode }
572 #define Rymm { OP_R, ymm_mode }
573 #define Rtmm { OP_R, tmm_mode }
574 #define EMCq { OP_EMC, q_mode }
575 #define MXC { OP_MXC, 0 }
576 #define OPSUF { OP_3DNowSuffix, 0 }
577 #define SEP { SEP_Fixup, 0 }
578 #define CMP { CMP_Fixup, 0 }
579 #define XMM0 { XMM_Fixup, 0 }
580 #define FXSAVE { FXSAVE_Fixup, 0 }
582 #define Vex { OP_VEX, x_mode }
583 #define VexW { OP_VexW, x_mode }
584 #define VexScalar { OP_VEX, scalar_mode }
585 #define VexScalarR { OP_VexR, scalar_mode }
586 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
587 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
588 #define VexGdq { OP_VEX, dq_mode }
589 #define VexGb { OP_VEX, b_mode }
590 #define VexGv { OP_VEX, v_mode }
591 #define VexTmm { OP_VEX, tmm_mode }
592 #define XMVexI4 { OP_REG_VexI4, x_mode }
593 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
594 #define VexI4 { OP_VexI4, 0 }
595 #define PCLMUL { PCLMUL_Fixup, 0 }
596 #define VPCMP { VPCMP_Fixup, 0 }
597 #define VPCOM { VPCOM_Fixup, 0 }
599 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
600 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
601 #define EXxEVexS { OP_Rounding, evex_sae_mode }
603 #define MaskG { OP_G, mask_mode }
604 #define MaskE { OP_E, mask_mode }
605 #define MaskR { OP_R, mask_mode }
606 #define MaskBDE { OP_E, mask_bd_mode }
607 #define MaskVex { OP_VEX, mask_mode }
609 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
610 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
612 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
614 /* Used handle "rep" prefix for string instructions. */
615 #define Xbr { REP_Fixup, eSI_reg }
616 #define Xvr { REP_Fixup, eSI_reg }
617 #define Ybr { REP_Fixup, eDI_reg }
618 #define Yvr { REP_Fixup, eDI_reg }
619 #define Yzr { REP_Fixup, eDI_reg }
620 #define indirDXr { REP_Fixup, indir_dx_reg }
621 #define ALr { REP_Fixup, al_reg }
622 #define eAXr { REP_Fixup, eAX_reg }
624 /* Used handle HLE prefix for lockable instructions. */
625 #define Ebh1 { HLE_Fixup1, b_mode }
626 #define Evh1 { HLE_Fixup1, v_mode }
627 #define Ebh2 { HLE_Fixup2, b_mode }
628 #define Evh2 { HLE_Fixup2, v_mode }
629 #define Ebh3 { HLE_Fixup3, b_mode }
630 #define Evh3 { HLE_Fixup3, v_mode }
632 #define BND { BND_Fixup, 0 }
633 #define NOTRACK { NOTRACK_Fixup, 0 }
635 #define cond_jump_flag { NULL, cond_jump_mode }
636 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
638 /* bits in sizeflag */
639 #define SUFFIX_ALWAYS 4
647 /* byte operand with operand swapped */
649 /* byte operand, sign extend like 'T' suffix */
651 /* operand size depends on prefixes */
653 /* operand size depends on prefixes with operand swapped */
655 /* operand size depends on address prefix */
659 /* double word operand */
661 /* word operand with operand swapped */
663 /* double word operand with operand swapped */
665 /* quad word operand */
667 /* 8-byte MM operand */
669 /* quad word operand with operand swapped */
671 /* ten-byte operand */
673 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
674 broadcast enabled. */
676 /* Similar to x_mode, but with different EVEX mem shifts. */
678 /* Similar to x_mode, but with yet different EVEX mem shifts. */
680 /* Similar to x_mode, but with disabled broadcast. */
682 /* Similar to x_mode, but with operands swapped and disabled broadcast
685 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
686 broadcast of 16bit enabled. */
688 /* 16-byte XMM operand */
690 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
691 memory operand (depending on vector length). Broadcast isn't
694 /* Same as xmmq_mode, but broadcast is allowed. */
695 evex_half_bcst_xmmq_mode
,
696 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
697 memory operand (depending on vector length). 16bit broadcast. */
698 evex_half_bcst_xmmqh_mode
,
699 /* 16-byte XMM, word, double word or quad word operand. */
701 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
703 /* 16-byte XMM, double word, quad word operand or xmm word operand.
705 evex_half_bcst_xmmqdh_mode
,
706 /* 32-byte YMM operand */
708 /* quad word, ymmword or zmmword memory operand. */
712 /* d_mode in 32bit, q_mode in 64bit mode. */
714 /* pair of v_mode operands */
720 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
722 /* operand size depends on REX.W / VEX.W. */
724 /* Displacements like v_mode without considering Intel64 ISA. */
728 /* bounds operand with operand swapped */
730 /* 4- or 6-byte pointer operand */
733 /* v_mode for indirect branch opcodes. */
735 /* v_mode for stack-related opcodes. */
737 /* non-quad operand size depends on prefixes */
739 /* 16-byte operand */
741 /* registers like d_mode, memory like b_mode. */
743 /* registers like d_mode, memory like w_mode. */
746 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
747 vex_vsib_d_w_dq_mode
,
748 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
749 vex_vsib_q_w_dq_mode
,
750 /* mandatory non-vector SIB. */
753 /* scalar, ignore vector length. */
756 /* Static rounding. */
758 /* Static rounding, 64-bit mode only. */
759 evex_rounding_64_mode
,
760 /* Supress all exceptions. */
763 /* Mask register operand. */
765 /* Mask register operand. */
823 USE_X86_64_EVEX_FROM_VEX_TABLE
,
824 USE_X86_64_EVEX_PFX_TABLE
,
825 USE_X86_64_EVEX_W_TABLE
,
826 USE_X86_64_EVEX_MEM_W_TABLE
,
837 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
839 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
840 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
841 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
842 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
843 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
844 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
845 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
846 DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
847 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
848 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
849 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
850 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
851 #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0)
852 #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0)
853 #define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0)
854 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
855 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
856 #define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0)
857 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
897 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0
,
898 REG_VEX_0F38F3_L_0_P_0
,
899 REG_VEX_MAP7_F8_L_0_W_0
,
958 MOD_VEX_0F3849_X86_64_L_0_W_0
,
960 MOD_EVEX_MAP4_F8_P_1
,
961 MOD_EVEX_MAP4_F8_P_3
,
974 RM_0F1E_P_1_MOD_3_REG_7
,
975 RM_0FAE_REG_6_MOD_3_P_0
,
979 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0
,
980 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3
,
986 PREFIX_0F00_REG_6_X86_64
,
987 PREFIX_0F01_REG_0_MOD_3_RM_6
,
988 PREFIX_0F01_REG_0_MOD_3_RM_7
,
989 PREFIX_0F01_REG_1_RM_2
,
990 PREFIX_0F01_REG_1_RM_4
,
991 PREFIX_0F01_REG_1_RM_5
,
992 PREFIX_0F01_REG_1_RM_6
,
993 PREFIX_0F01_REG_1_RM_7
,
994 PREFIX_0F01_REG_3_RM_1
,
995 PREFIX_0F01_REG_5_MOD_0
,
996 PREFIX_0F01_REG_5_MOD_3_RM_0
,
997 PREFIX_0F01_REG_5_MOD_3_RM_1
,
998 PREFIX_0F01_REG_5_MOD_3_RM_2
,
999 PREFIX_0F01_REG_5_MOD_3_RM_4
,
1000 PREFIX_0F01_REG_5_MOD_3_RM_5
,
1001 PREFIX_0F01_REG_5_MOD_3_RM_6
,
1002 PREFIX_0F01_REG_5_MOD_3_RM_7
,
1003 PREFIX_0F01_REG_7_MOD_3_RM_2
,
1004 PREFIX_0F01_REG_7_MOD_3_RM_5
,
1005 PREFIX_0F01_REG_7_MOD_3_RM_6
,
1006 PREFIX_0F01_REG_7_MOD_3_RM_7
,
1012 PREFIX_0F18_REG_6_MOD_0_X86_64
,
1013 PREFIX_0F18_REG_7_MOD_0_X86_64
,
1046 PREFIX_0FAE_REG_0_MOD_3
,
1047 PREFIX_0FAE_REG_1_MOD_3
,
1048 PREFIX_0FAE_REG_2_MOD_3
,
1049 PREFIX_0FAE_REG_3_MOD_3
,
1050 PREFIX_0FAE_REG_4_MOD_0
,
1051 PREFIX_0FAE_REG_4_MOD_3
,
1052 PREFIX_0FAE_REG_5_MOD_3
,
1053 PREFIX_0FAE_REG_6_MOD_0
,
1054 PREFIX_0FAE_REG_6_MOD_3
,
1055 PREFIX_0FAE_REG_7_MOD_0
,
1060 PREFIX_0FC7_REG_6_MOD_0
,
1061 PREFIX_0FC7_REG_6_MOD_3
,
1062 PREFIX_0FC7_REG_7_MOD_3
,
1078 PREFIX_0F38F8_M_1_X86_64
,
1088 PREFIX_VEX_0F41_L_1_W_0
,
1089 PREFIX_VEX_0F41_L_1_W_1
,
1090 PREFIX_VEX_0F42_L_1_W_0
,
1091 PREFIX_VEX_0F42_L_1_W_1
,
1092 PREFIX_VEX_0F44_L_0_W_0
,
1093 PREFIX_VEX_0F44_L_0_W_1
,
1094 PREFIX_VEX_0F45_L_1_W_0
,
1095 PREFIX_VEX_0F45_L_1_W_1
,
1096 PREFIX_VEX_0F46_L_1_W_0
,
1097 PREFIX_VEX_0F46_L_1_W_1
,
1098 PREFIX_VEX_0F47_L_1_W_0
,
1099 PREFIX_VEX_0F47_L_1_W_1
,
1100 PREFIX_VEX_0F4A_L_1_W_0
,
1101 PREFIX_VEX_0F4A_L_1_W_1
,
1102 PREFIX_VEX_0F4B_L_1_W_0
,
1103 PREFIX_VEX_0F4B_L_1_W_1
,
1108 PREFIX_VEX_0F90_L_0_W_0
,
1109 PREFIX_VEX_0F90_L_0_W_1
,
1110 PREFIX_VEX_0F91_L_0_W_0
,
1111 PREFIX_VEX_0F91_L_0_W_1
,
1112 PREFIX_VEX_0F92_L_0_W_0
,
1113 PREFIX_VEX_0F92_L_0_W_1
,
1114 PREFIX_VEX_0F93_L_0_W_0
,
1115 PREFIX_VEX_0F93_L_0_W_1
,
1116 PREFIX_VEX_0F98_L_0_W_0
,
1117 PREFIX_VEX_0F98_L_0_W_1
,
1118 PREFIX_VEX_0F99_L_0_W_0
,
1119 PREFIX_VEX_0F99_L_0_W_1
,
1120 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0
,
1121 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1
,
1122 PREFIX_VEX_0F384B_X86_64_L_0_W_0
,
1123 PREFIX_VEX_0F3850_W_0
,
1124 PREFIX_VEX_0F3851_W_0
,
1125 PREFIX_VEX_0F385C_X86_64_L_0_W_0
,
1126 PREFIX_VEX_0F385E_X86_64_L_0_W_0
,
1127 PREFIX_VEX_0F386C_X86_64_L_0_W_0
,
1129 PREFIX_VEX_0F38B0_W_0
,
1130 PREFIX_VEX_0F38B1_W_0
,
1131 PREFIX_VEX_0F38D2_W_0
,
1132 PREFIX_VEX_0F38D3_W_0
,
1136 PREFIX_VEX_0F38DA_W_0
,
1137 PREFIX_VEX_0F38F2_L_0
,
1138 PREFIX_VEX_0F38F3_L_0
,
1139 PREFIX_VEX_0F38F5_L_0
,
1140 PREFIX_VEX_0F38F6_L_0
,
1141 PREFIX_VEX_0F38F7_L_0
,
1142 PREFIX_VEX_0F3AF0_L_0
,
1143 PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64
,
1201 PREFIX_EVEX_MAP4_D8
,
1202 PREFIX_EVEX_MAP4_DA
,
1203 PREFIX_EVEX_MAP4_DB
,
1204 PREFIX_EVEX_MAP4_DC
,
1205 PREFIX_EVEX_MAP4_DD
,
1206 PREFIX_EVEX_MAP4_DE
,
1207 PREFIX_EVEX_MAP4_DF
,
1208 PREFIX_EVEX_MAP4_F0
,
1209 PREFIX_EVEX_MAP4_F1
,
1210 PREFIX_EVEX_MAP4_F2
,
1211 PREFIX_EVEX_MAP4_F8
,
1213 PREFIX_EVEX_MAP5_10
,
1214 PREFIX_EVEX_MAP5_11
,
1215 PREFIX_EVEX_MAP5_1D
,
1216 PREFIX_EVEX_MAP5_2A
,
1217 PREFIX_EVEX_MAP5_2C
,
1218 PREFIX_EVEX_MAP5_2D
,
1219 PREFIX_EVEX_MAP5_2E
,
1220 PREFIX_EVEX_MAP5_2F
,
1221 PREFIX_EVEX_MAP5_51
,
1222 PREFIX_EVEX_MAP5_58
,
1223 PREFIX_EVEX_MAP5_59
,
1224 PREFIX_EVEX_MAP5_5A
,
1225 PREFIX_EVEX_MAP5_5B
,
1226 PREFIX_EVEX_MAP5_5C
,
1227 PREFIX_EVEX_MAP5_5D
,
1228 PREFIX_EVEX_MAP5_5E
,
1229 PREFIX_EVEX_MAP5_5F
,
1230 PREFIX_EVEX_MAP5_78
,
1231 PREFIX_EVEX_MAP5_79
,
1232 PREFIX_EVEX_MAP5_7A
,
1233 PREFIX_EVEX_MAP5_7B
,
1234 PREFIX_EVEX_MAP5_7C
,
1235 PREFIX_EVEX_MAP5_7D
,
1237 PREFIX_EVEX_MAP6_13
,
1238 PREFIX_EVEX_MAP6_56
,
1239 PREFIX_EVEX_MAP6_57
,
1240 PREFIX_EVEX_MAP6_D6
,
1241 PREFIX_EVEX_MAP6_D7
,
1277 X86_64_0F01_REG_0_MOD_3_RM_6_P_1
,
1278 X86_64_0F01_REG_0_MOD_3_RM_6_P_3
,
1279 X86_64_0F01_REG_0_MOD_3_RM_7_P_0
,
1281 X86_64_0F01_REG_1_RM_2_PREFIX_1
,
1282 X86_64_0F01_REG_1_RM_2_PREFIX_3
,
1283 X86_64_0F01_REG_1_RM_5_PREFIX_2
,
1284 X86_64_0F01_REG_1_RM_6_PREFIX_2
,
1285 X86_64_0F01_REG_1_RM_7_PREFIX_2
,
1288 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
,
1289 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
,
1290 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
,
1291 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
,
1292 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1
,
1293 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
,
1294 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
,
1295 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
,
1296 X86_64_0F18_REG_6_MOD_0
,
1297 X86_64_0F18_REG_7_MOD_0
,
1301 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
,
1325 X86_64_VEX_MAP7_F8_L_0_W_0_R_0
,
1330 THREE_BYTE_0F38
= 0,
1362 VEX_LEN_0F12_P_0
= 0,
1395 VEX_LEN_0F3849_X86_64
,
1396 VEX_LEN_0F384B_X86_64
,
1398 VEX_LEN_0F385C_X86_64
,
1399 VEX_LEN_0F385E_X86_64
,
1400 VEX_LEN_0F386C_X86_64
,
1401 VEX_LEN_0F38CB_P_3_W_0
,
1402 VEX_LEN_0F38CC_P_3_W_0
,
1403 VEX_LEN_0F38CD_P_3_W_0
,
1404 VEX_LEN_0F38DA_W_0_P_0
,
1405 VEX_LEN_0F38DA_W_0_P_2
,
1468 VEX_LEN_XOP_09_82_W_0
,
1469 VEX_LEN_XOP_09_83_W_0
,
1502 EVEX_LEN_0F3816
= 0,
1556 VEX_W_0F3849_X86_64_L_0
,
1557 VEX_W_0F384B_X86_64_L_0
,
1565 VEX_W_0F385C_X86_64_L_0
,
1566 VEX_W_0F385E_X86_64_L_0
,
1567 VEX_W_0F386C_X86_64_L_0
,
1602 VEX_W_XOP_08_85_L_0
,
1603 VEX_W_XOP_08_86_L_0
,
1604 VEX_W_XOP_08_87_L_0
,
1605 VEX_W_XOP_08_8E_L_0
,
1606 VEX_W_XOP_08_8F_L_0
,
1607 VEX_W_XOP_08_95_L_0
,
1608 VEX_W_XOP_08_96_L_0
,
1609 VEX_W_XOP_08_97_L_0
,
1610 VEX_W_XOP_08_9E_L_0
,
1611 VEX_W_XOP_08_9F_L_0
,
1612 VEX_W_XOP_08_A6_L_0
,
1613 VEX_W_XOP_08_B6_L_0
,
1614 VEX_W_XOP_08_C0_L_0
,
1615 VEX_W_XOP_08_C1_L_0
,
1616 VEX_W_XOP_08_C2_L_0
,
1617 VEX_W_XOP_08_C3_L_0
,
1618 VEX_W_XOP_08_CC_L_0
,
1619 VEX_W_XOP_08_CD_L_0
,
1620 VEX_W_XOP_08_CE_L_0
,
1621 VEX_W_XOP_08_CF_L_0
,
1622 VEX_W_XOP_08_EC_L_0
,
1623 VEX_W_XOP_08_ED_L_0
,
1624 VEX_W_XOP_08_EE_L_0
,
1625 VEX_W_XOP_08_EF_L_0
,
1631 VEX_W_XOP_09_C1_L_0
,
1632 VEX_W_XOP_09_C2_L_0
,
1633 VEX_W_XOP_09_C3_L_0
,
1634 VEX_W_XOP_09_C6_L_0
,
1635 VEX_W_XOP_09_C7_L_0
,
1636 VEX_W_XOP_09_CB_L_0
,
1637 VEX_W_XOP_09_D1_L_0
,
1638 VEX_W_XOP_09_D2_L_0
,
1639 VEX_W_XOP_09_D3_L_0
,
1640 VEX_W_XOP_09_D6_L_0
,
1641 VEX_W_XOP_09_D7_L_0
,
1642 VEX_W_XOP_09_DB_L_0
,
1643 VEX_W_XOP_09_E1_L_0
,
1644 VEX_W_XOP_09_E2_L_0
,
1645 VEX_W_XOP_09_E3_L_0
,
1754 typedef bool (*op_rtn
) (instr_info
*ins
, int bytemode
, int sizeflag
);
1763 unsigned int prefix_requirement
;
1766 /* Upper case letters in the instruction names here are macros.
1767 'A' => print 'b' if no (suitable) register operand or suffix_always is true
1768 'B' => print 'b' if suffix_always is true
1769 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1771 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1772 suffix_always is true
1773 'E' => print 'e' if 32-bit form of jcxz
1774 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1775 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1776 'H' => print ",pt" or ",pn" branch hint
1779 'K' => print 'd' or 'q' if rex prefix is present.
1780 'L' => print 'l' or 'q' if suffix_always is true
1781 'M' => print 'r' if intel_mnemonic is false.
1782 'N' => print 'n' if instruction has no wait "prefix"
1783 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1784 'P' => behave as 'T' except with register operand outside of suffix_always
1786 'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1787 suffix_always is true
1788 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1789 'S' => print 'w', 'l' or 'q' if suffix_always is true
1790 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1791 prefix or if suffix_always is true.
1793 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1794 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1795 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1796 'Y' => no output, mark EVEX.aaa != 0 as bad.
1797 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1798 '!' => change condition from true to false or from false to true.
1799 '%' => add 1 upper case letter to the macro.
1800 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1801 prefix or suffix_always is true (lcall/ljmp).
1802 '@' => in 64bit mode for Intel64 ISA or if instruction
1803 has no operand sizing prefix, print 'q' if suffix_always is true or
1804 nothing otherwise; behave as 'P' in all other cases
1806 2 upper case letter macros:
1807 "XY" => print 'x' or 'y' if suffix_always is true or no register
1808 operands and no broadcast.
1809 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1810 register operands and no broadcast.
1811 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1812 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1813 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1814 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1815 "XV" => print "{vex} " pseudo prefix
1816 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1817 is used by an EVEX-encoded (AVX512VL) instruction.
1818 "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1819 "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1820 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1821 being false, or no operand at all in 64bit mode, or if suffix_always
1823 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1824 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1825 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1826 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1827 "BW" => print 'b' or 'w' depending on the VEX.W bit
1828 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1829 an operand size prefix, or suffix_always is true. print
1830 'q' if rex prefix is present.
1832 Many of the above letters print nothing in Intel mode. See "putop"
1835 Braces '{' and '}', and vertical bars '|', indicate alternative
1836 mnemonic strings for AT&T and Intel. */
1838 static const struct dis386 dis386
[] = {
1840 { "addB", { Ebh1
, Gb
}, 0 },
1841 { "addS", { Evh1
, Gv
}, 0 },
1842 { "addB", { Gb
, EbS
}, 0 },
1843 { "addS", { Gv
, EvS
}, 0 },
1844 { "addB", { AL
, Ib
}, 0 },
1845 { "addS", { eAX
, Iv
}, 0 },
1846 { X86_64_TABLE (X86_64_06
) },
1847 { X86_64_TABLE (X86_64_07
) },
1849 { "orB", { Ebh1
, Gb
}, 0 },
1850 { "orS", { Evh1
, Gv
}, 0 },
1851 { "orB", { Gb
, EbS
}, 0 },
1852 { "orS", { Gv
, EvS
}, 0 },
1853 { "orB", { AL
, Ib
}, 0 },
1854 { "orS", { eAX
, Iv
}, 0 },
1855 { X86_64_TABLE (X86_64_0E
) },
1856 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1858 { "adcB", { Ebh1
, Gb
}, 0 },
1859 { "adcS", { Evh1
, Gv
}, 0 },
1860 { "adcB", { Gb
, EbS
}, 0 },
1861 { "adcS", { Gv
, EvS
}, 0 },
1862 { "adcB", { AL
, Ib
}, 0 },
1863 { "adcS", { eAX
, Iv
}, 0 },
1864 { X86_64_TABLE (X86_64_16
) },
1865 { X86_64_TABLE (X86_64_17
) },
1867 { "sbbB", { Ebh1
, Gb
}, 0 },
1868 { "sbbS", { Evh1
, Gv
}, 0 },
1869 { "sbbB", { Gb
, EbS
}, 0 },
1870 { "sbbS", { Gv
, EvS
}, 0 },
1871 { "sbbB", { AL
, Ib
}, 0 },
1872 { "sbbS", { eAX
, Iv
}, 0 },
1873 { X86_64_TABLE (X86_64_1E
) },
1874 { X86_64_TABLE (X86_64_1F
) },
1876 { "andB", { Ebh1
, Gb
}, 0 },
1877 { "andS", { Evh1
, Gv
}, 0 },
1878 { "andB", { Gb
, EbS
}, 0 },
1879 { "andS", { Gv
, EvS
}, 0 },
1880 { "andB", { AL
, Ib
}, 0 },
1881 { "andS", { eAX
, Iv
}, 0 },
1882 { Bad_Opcode
}, /* SEG ES prefix */
1883 { X86_64_TABLE (X86_64_27
) },
1885 { "subB", { Ebh1
, Gb
}, 0 },
1886 { "subS", { Evh1
, Gv
}, 0 },
1887 { "subB", { Gb
, EbS
}, 0 },
1888 { "subS", { Gv
, EvS
}, 0 },
1889 { "subB", { AL
, Ib
}, 0 },
1890 { "subS", { eAX
, Iv
}, 0 },
1891 { Bad_Opcode
}, /* SEG CS prefix */
1892 { X86_64_TABLE (X86_64_2F
) },
1894 { "xorB", { Ebh1
, Gb
}, 0 },
1895 { "xorS", { Evh1
, Gv
}, 0 },
1896 { "xorB", { Gb
, EbS
}, 0 },
1897 { "xorS", { Gv
, EvS
}, 0 },
1898 { "xorB", { AL
, Ib
}, 0 },
1899 { "xorS", { eAX
, Iv
}, 0 },
1900 { Bad_Opcode
}, /* SEG SS prefix */
1901 { X86_64_TABLE (X86_64_37
) },
1903 { "cmpB", { Eb
, Gb
}, 0 },
1904 { "cmpS", { Ev
, Gv
}, 0 },
1905 { "cmpB", { Gb
, EbS
}, 0 },
1906 { "cmpS", { Gv
, EvS
}, 0 },
1907 { "cmpB", { AL
, Ib
}, 0 },
1908 { "cmpS", { eAX
, Iv
}, 0 },
1909 { Bad_Opcode
}, /* SEG DS prefix */
1910 { X86_64_TABLE (X86_64_3F
) },
1912 { "inc{S|}", { RMeAX
}, 0 },
1913 { "inc{S|}", { RMeCX
}, 0 },
1914 { "inc{S|}", { RMeDX
}, 0 },
1915 { "inc{S|}", { RMeBX
}, 0 },
1916 { "inc{S|}", { RMeSP
}, 0 },
1917 { "inc{S|}", { RMeBP
}, 0 },
1918 { "inc{S|}", { RMeSI
}, 0 },
1919 { "inc{S|}", { RMeDI
}, 0 },
1921 { "dec{S|}", { RMeAX
}, 0 },
1922 { "dec{S|}", { RMeCX
}, 0 },
1923 { "dec{S|}", { RMeDX
}, 0 },
1924 { "dec{S|}", { RMeBX
}, 0 },
1925 { "dec{S|}", { RMeSP
}, 0 },
1926 { "dec{S|}", { RMeBP
}, 0 },
1927 { "dec{S|}", { RMeSI
}, 0 },
1928 { "dec{S|}", { RMeDI
}, 0 },
1930 { "push!P", { RMrAX
}, 0 },
1931 { "push!P", { RMrCX
}, 0 },
1932 { "push!P", { RMrDX
}, 0 },
1933 { "push!P", { RMrBX
}, 0 },
1934 { "push!P", { RMrSP
}, 0 },
1935 { "push!P", { RMrBP
}, 0 },
1936 { "push!P", { RMrSI
}, 0 },
1937 { "push!P", { RMrDI
}, 0 },
1939 { "pop!P", { RMrAX
}, 0 },
1940 { "pop!P", { RMrCX
}, 0 },
1941 { "pop!P", { RMrDX
}, 0 },
1942 { "pop!P", { RMrBX
}, 0 },
1943 { "pop!P", { RMrSP
}, 0 },
1944 { "pop!P", { RMrBP
}, 0 },
1945 { "pop!P", { RMrSI
}, 0 },
1946 { "pop!P", { RMrDI
}, 0 },
1948 { X86_64_TABLE (X86_64_60
) },
1949 { X86_64_TABLE (X86_64_61
) },
1950 { X86_64_TABLE (X86_64_62
) },
1951 { X86_64_TABLE (X86_64_63
) },
1952 { Bad_Opcode
}, /* seg fs */
1953 { Bad_Opcode
}, /* seg gs */
1954 { Bad_Opcode
}, /* op size prefix */
1955 { Bad_Opcode
}, /* adr size prefix */
1957 { "pushP", { sIv
}, 0 },
1958 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1959 { "pushP", { sIbT
}, 0 },
1960 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1961 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1962 { X86_64_TABLE (X86_64_6D
) },
1963 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1964 { X86_64_TABLE (X86_64_6F
) },
1966 { "joH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1967 { "jnoH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1968 { "jbH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1969 { "jaeH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1970 { "jeH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1971 { "jneH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1972 { "jbeH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1973 { "jaH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1975 { "jsH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1976 { "jnsH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1977 { "jpH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1978 { "jnpH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1979 { "jlH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1980 { "jgeH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1981 { "jleH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1982 { "jgH", { Jb
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
1984 { REG_TABLE (REG_80
) },
1985 { REG_TABLE (REG_81
) },
1986 { X86_64_TABLE (X86_64_82
) },
1987 { REG_TABLE (REG_83
) },
1988 { "testB", { Eb
, Gb
}, 0 },
1989 { "testS", { Ev
, Gv
}, 0 },
1990 { "xchgB", { Ebh2
, Gb
}, 0 },
1991 { "xchgS", { Evh2
, Gv
}, 0 },
1993 { "movB", { Ebh3
, Gb
}, 0 },
1994 { "movS", { Evh3
, Gv
}, 0 },
1995 { "movB", { Gb
, EbS
}, 0 },
1996 { "movS", { Gv
, EvS
}, 0 },
1997 { "movD", { Sv
, Sw
}, 0 },
1998 { "leaS", { Gv
, M
}, 0 },
1999 { "movD", { Sw
, Sv
}, 0 },
2000 { REG_TABLE (REG_8F
) },
2002 { PREFIX_TABLE (PREFIX_90
) },
2003 { "xchgS", { RMeCX
, eAX
}, 0 },
2004 { "xchgS", { RMeDX
, eAX
}, 0 },
2005 { "xchgS", { RMeBX
, eAX
}, 0 },
2006 { "xchgS", { RMeSP
, eAX
}, 0 },
2007 { "xchgS", { RMeBP
, eAX
}, 0 },
2008 { "xchgS", { RMeSI
, eAX
}, 0 },
2009 { "xchgS", { RMeDI
, eAX
}, 0 },
2011 { "cW{t|}R", { XX
}, 0 },
2012 { "cR{t|}O", { XX
}, 0 },
2013 { X86_64_TABLE (X86_64_9A
) },
2014 { Bad_Opcode
}, /* fwait */
2015 { "pushfP", { XX
}, 0 },
2016 { "popfP", { XX
}, 0 },
2017 { "sahf", { XX
}, 0 },
2018 { "lahf", { XX
}, 0 },
2020 { "mov%LB", { AL
, Ob
}, PREFIX_REX2_ILLEGAL
},
2021 { "mov%LS", { { JMPABS_Fixup
, eAX_reg
}, { JMPABS_Fixup
, v_mode
} }, PREFIX_REX2_ILLEGAL
},
2022 { "mov%LB", { Ob
, AL
}, PREFIX_REX2_ILLEGAL
},
2023 { "mov%LS", { Ov
, eAX
}, PREFIX_REX2_ILLEGAL
},
2024 { "movs{b|}", { Ybr
, Xb
}, PREFIX_REX2_ILLEGAL
},
2025 { "movs{R|}", { Yvr
, Xv
}, PREFIX_REX2_ILLEGAL
},
2026 { "cmps{b|}", { Xb
, Yb
}, PREFIX_REX2_ILLEGAL
},
2027 { "cmps{R|}", { Xv
, Yv
}, PREFIX_REX2_ILLEGAL
},
2029 { "testB", { AL
, Ib
}, PREFIX_REX2_ILLEGAL
},
2030 { "testS", { eAX
, Iv
}, PREFIX_REX2_ILLEGAL
},
2031 { "stosB", { Ybr
, AL
}, PREFIX_REX2_ILLEGAL
},
2032 { "stosS", { Yvr
, eAX
}, PREFIX_REX2_ILLEGAL
},
2033 { "lodsB", { ALr
, Xb
}, PREFIX_REX2_ILLEGAL
},
2034 { "lodsS", { eAXr
, Xv
}, PREFIX_REX2_ILLEGAL
},
2035 { "scasB", { AL
, Yb
}, PREFIX_REX2_ILLEGAL
},
2036 { "scasS", { eAX
, Yv
}, PREFIX_REX2_ILLEGAL
},
2038 { "movB", { RMAL
, Ib
}, 0 },
2039 { "movB", { RMCL
, Ib
}, 0 },
2040 { "movB", { RMDL
, Ib
}, 0 },
2041 { "movB", { RMBL
, Ib
}, 0 },
2042 { "movB", { RMAH
, Ib
}, 0 },
2043 { "movB", { RMCH
, Ib
}, 0 },
2044 { "movB", { RMDH
, Ib
}, 0 },
2045 { "movB", { RMBH
, Ib
}, 0 },
2047 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2048 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2049 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2050 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2051 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2052 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2053 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2054 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2056 { REG_TABLE (REG_C0
) },
2057 { REG_TABLE (REG_C1
) },
2058 { X86_64_TABLE (X86_64_C2
) },
2059 { X86_64_TABLE (X86_64_C3
) },
2060 { X86_64_TABLE (X86_64_C4
) },
2061 { X86_64_TABLE (X86_64_C5
) },
2062 { REG_TABLE (REG_C6
) },
2063 { REG_TABLE (REG_C7
) },
2065 { "enterP", { Iw
, Ib
}, 0 },
2066 { "leaveP", { XX
}, 0 },
2067 { "{l|}ret{|f}%LP", { Iw
}, 0 },
2068 { "{l|}ret{|f}%LP", { XX
}, 0 },
2069 { "int3", { XX
}, 0 },
2070 { "int", { Ib
}, 0 },
2071 { X86_64_TABLE (X86_64_CE
) },
2072 { "iret%LP", { XX
}, 0 },
2074 { REG_TABLE (REG_D0
) },
2075 { REG_TABLE (REG_D1
) },
2076 { REG_TABLE (REG_D2
) },
2077 { REG_TABLE (REG_D3
) },
2078 { X86_64_TABLE (X86_64_D4
) },
2079 { X86_64_TABLE (X86_64_D5
) },
2081 { "xlat", { DSBX
}, 0 },
2092 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, PREFIX_REX2_ILLEGAL
},
2093 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, PREFIX_REX2_ILLEGAL
},
2094 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, PREFIX_REX2_ILLEGAL
},
2095 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, PREFIX_REX2_ILLEGAL
},
2096 { "inB", { AL
, Ib
}, PREFIX_REX2_ILLEGAL
},
2097 { "inG", { zAX
, Ib
}, PREFIX_REX2_ILLEGAL
},
2098 { "outB", { Ib
, AL
}, PREFIX_REX2_ILLEGAL
},
2099 { "outG", { Ib
, zAX
}, PREFIX_REX2_ILLEGAL
},
2101 { X86_64_TABLE (X86_64_E8
) },
2102 { X86_64_TABLE (X86_64_E9
) },
2103 { X86_64_TABLE (X86_64_EA
) },
2104 { "jmp", { Jb
, BND
}, PREFIX_REX2_ILLEGAL
},
2105 { "inB", { AL
, indirDX
}, PREFIX_REX2_ILLEGAL
},
2106 { "inG", { zAX
, indirDX
}, PREFIX_REX2_ILLEGAL
},
2107 { "outB", { indirDX
, AL
}, PREFIX_REX2_ILLEGAL
},
2108 { "outG", { indirDX
, zAX
}, PREFIX_REX2_ILLEGAL
},
2110 { Bad_Opcode
}, /* lock prefix */
2111 { "int1", { XX
}, 0 },
2112 { Bad_Opcode
}, /* repne */
2113 { Bad_Opcode
}, /* repz */
2114 { "hlt", { XX
}, 0 },
2115 { "cmc", { XX
}, 0 },
2116 { REG_TABLE (REG_F6
) },
2117 { REG_TABLE (REG_F7
) },
2119 { "clc", { XX
}, 0 },
2120 { "stc", { XX
}, 0 },
2121 { "cli", { XX
}, 0 },
2122 { "sti", { XX
}, 0 },
2123 { "cld", { XX
}, 0 },
2124 { "std", { XX
}, 0 },
2125 { REG_TABLE (REG_FE
) },
2126 { REG_TABLE (REG_FF
) },
2129 static const struct dis386 dis386_twobyte
[] = {
2131 { REG_TABLE (REG_0F00
) },
2132 { REG_TABLE (REG_0F01
) },
2133 { "larS", { Gv
, Sv
}, 0 },
2134 { "lslS", { Gv
, Sv
}, 0 },
2136 { "syscall", { XX
}, 0 },
2137 { "clts", { XX
}, 0 },
2138 { "sysret%LQ", { XX
}, 0 },
2140 { "invd", { XX
}, 0 },
2141 { PREFIX_TABLE (PREFIX_0F09
) },
2143 { "ud2", { XX
}, 0 },
2145 { REG_TABLE (REG_0F0D
) },
2146 { "femms", { XX
}, 0 },
2147 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2149 { PREFIX_TABLE (PREFIX_0F10
) },
2150 { PREFIX_TABLE (PREFIX_0F11
) },
2151 { PREFIX_TABLE (PREFIX_0F12
) },
2152 { "movlpX", { Mq
, XM
}, PREFIX_OPCODE
},
2153 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2154 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2155 { PREFIX_TABLE (PREFIX_0F16
) },
2156 { "movhpX", { Mq
, XM
}, PREFIX_OPCODE
},
2158 { REG_TABLE (REG_0F18
) },
2159 { "nopQ", { Ev
}, 0 },
2160 { PREFIX_TABLE (PREFIX_0F1A
) },
2161 { PREFIX_TABLE (PREFIX_0F1B
) },
2162 { PREFIX_TABLE (PREFIX_0F1C
) },
2163 { "nopQ", { Ev
}, 0 },
2164 { PREFIX_TABLE (PREFIX_0F1E
) },
2165 { "nopQ", { Ev
}, 0 },
2167 { "movZ", { Em
, Cm
}, 0 },
2168 { "movZ", { Em
, Dm
}, 0 },
2169 { "movZ", { Cm
, Em
}, 0 },
2170 { "movZ", { Dm
, Em
}, 0 },
2171 { X86_64_TABLE (X86_64_0F24
) },
2173 { X86_64_TABLE (X86_64_0F26
) },
2176 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2177 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2178 { PREFIX_TABLE (PREFIX_0F2A
) },
2179 { PREFIX_TABLE (PREFIX_0F2B
) },
2180 { PREFIX_TABLE (PREFIX_0F2C
) },
2181 { PREFIX_TABLE (PREFIX_0F2D
) },
2182 { PREFIX_TABLE (PREFIX_0F2E
) },
2183 { PREFIX_TABLE (PREFIX_0F2F
) },
2185 { "wrmsr", { XX
}, PREFIX_REX2_ILLEGAL
},
2186 { "rdtsc", { XX
}, PREFIX_REX2_ILLEGAL
},
2187 { "rdmsr", { XX
}, PREFIX_REX2_ILLEGAL
},
2188 { "rdpmc", { XX
}, PREFIX_REX2_ILLEGAL
},
2189 { "sysenter", { SEP
}, PREFIX_REX2_ILLEGAL
},
2190 { "sysexit%LQ", { SEP
}, PREFIX_REX2_ILLEGAL
},
2192 { "getsec", { XX
}, 0 },
2194 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2196 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2203 { "cmovoS", { Gv
, Ev
}, 0 },
2204 { "cmovnoS", { Gv
, Ev
}, 0 },
2205 { "cmovbS", { Gv
, Ev
}, 0 },
2206 { "cmovaeS", { Gv
, Ev
}, 0 },
2207 { "cmoveS", { Gv
, Ev
}, 0 },
2208 { "cmovneS", { Gv
, Ev
}, 0 },
2209 { "cmovbeS", { Gv
, Ev
}, 0 },
2210 { "cmovaS", { Gv
, Ev
}, 0 },
2212 { "cmovsS", { Gv
, Ev
}, 0 },
2213 { "cmovnsS", { Gv
, Ev
}, 0 },
2214 { "cmovpS", { Gv
, Ev
}, 0 },
2215 { "cmovnpS", { Gv
, Ev
}, 0 },
2216 { "cmovlS", { Gv
, Ev
}, 0 },
2217 { "cmovgeS", { Gv
, Ev
}, 0 },
2218 { "cmovleS", { Gv
, Ev
}, 0 },
2219 { "cmovgS", { Gv
, Ev
}, 0 },
2221 { "movmskpX", { Gdq
, Ux
}, PREFIX_OPCODE
},
2222 { PREFIX_TABLE (PREFIX_0F51
) },
2223 { PREFIX_TABLE (PREFIX_0F52
) },
2224 { PREFIX_TABLE (PREFIX_0F53
) },
2225 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2226 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2227 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2228 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2230 { PREFIX_TABLE (PREFIX_0F58
) },
2231 { PREFIX_TABLE (PREFIX_0F59
) },
2232 { PREFIX_TABLE (PREFIX_0F5A
) },
2233 { PREFIX_TABLE (PREFIX_0F5B
) },
2234 { PREFIX_TABLE (PREFIX_0F5C
) },
2235 { PREFIX_TABLE (PREFIX_0F5D
) },
2236 { PREFIX_TABLE (PREFIX_0F5E
) },
2237 { PREFIX_TABLE (PREFIX_0F5F
) },
2239 { PREFIX_TABLE (PREFIX_0F60
) },
2240 { PREFIX_TABLE (PREFIX_0F61
) },
2241 { PREFIX_TABLE (PREFIX_0F62
) },
2242 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2243 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2244 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2245 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2246 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2248 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2249 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2250 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2251 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2252 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2253 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2254 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2255 { PREFIX_TABLE (PREFIX_0F6F
) },
2257 { PREFIX_TABLE (PREFIX_0F70
) },
2258 { REG_TABLE (REG_0F71
) },
2259 { REG_TABLE (REG_0F72
) },
2260 { REG_TABLE (REG_0F73
) },
2261 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2262 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2263 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2264 { "emms", { XX
}, PREFIX_OPCODE
},
2266 { PREFIX_TABLE (PREFIX_0F78
) },
2267 { PREFIX_TABLE (PREFIX_0F79
) },
2270 { PREFIX_TABLE (PREFIX_0F7C
) },
2271 { PREFIX_TABLE (PREFIX_0F7D
) },
2272 { PREFIX_TABLE (PREFIX_0F7E
) },
2273 { PREFIX_TABLE (PREFIX_0F7F
) },
2275 { "joH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2276 { "jnoH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2277 { "jbH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2278 { "jaeH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2279 { "jeH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2280 { "jneH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2281 { "jbeH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2282 { "jaH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2284 { "jsH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2285 { "jnsH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2286 { "jpH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2287 { "jnpH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2288 { "jlH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2289 { "jgeH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2290 { "jleH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2291 { "jgH", { Jv
, BND
, cond_jump_flag
}, PREFIX_REX2_ILLEGAL
},
2293 { "seto", { Eb
}, 0 },
2294 { "setno", { Eb
}, 0 },
2295 { "setb", { Eb
}, 0 },
2296 { "setae", { Eb
}, 0 },
2297 { "sete", { Eb
}, 0 },
2298 { "setne", { Eb
}, 0 },
2299 { "setbe", { Eb
}, 0 },
2300 { "seta", { Eb
}, 0 },
2302 { "sets", { Eb
}, 0 },
2303 { "setns", { Eb
}, 0 },
2304 { "setp", { Eb
}, 0 },
2305 { "setnp", { Eb
}, 0 },
2306 { "setl", { Eb
}, 0 },
2307 { "setge", { Eb
}, 0 },
2308 { "setle", { Eb
}, 0 },
2309 { "setg", { Eb
}, 0 },
2311 { "pushP", { fs
}, 0 },
2312 { "popP", { fs
}, 0 },
2313 { "cpuid", { XX
}, 0 },
2314 { "btS", { Ev
, Gv
}, 0 },
2315 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2316 { "shldS", { Ev
, Gv
, CL
}, 0 },
2317 { REG_TABLE (REG_0FA6
) },
2318 { REG_TABLE (REG_0FA7
) },
2320 { "pushP", { gs
}, 0 },
2321 { "popP", { gs
}, 0 },
2322 { "rsm", { XX
}, 0 },
2323 { "btsS", { Evh1
, Gv
}, 0 },
2324 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2325 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2326 { REG_TABLE (REG_0FAE
) },
2327 { "imulS", { Gv
, Ev
}, 0 },
2329 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2330 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2331 { "lssS", { Gv
, Mp
}, 0 },
2332 { "btrS", { Evh1
, Gv
}, 0 },
2333 { "lfsS", { Gv
, Mp
}, 0 },
2334 { "lgsS", { Gv
, Mp
}, 0 },
2335 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2336 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2338 { PREFIX_TABLE (PREFIX_0FB8
) },
2339 { "ud1S", { Gv
, Ev
}, 0 },
2340 { REG_TABLE (REG_0FBA
) },
2341 { "btcS", { Evh1
, Gv
}, 0 },
2342 { PREFIX_TABLE (PREFIX_0FBC
) },
2343 { PREFIX_TABLE (PREFIX_0FBD
) },
2344 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2345 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2347 { "xaddB", { Ebh1
, Gb
}, 0 },
2348 { "xaddS", { Evh1
, Gv
}, 0 },
2349 { PREFIX_TABLE (PREFIX_0FC2
) },
2350 { "movntiS", { Mdq
, Gdq
}, PREFIX_OPCODE
},
2351 { "pinsrw", { MX
, Edw
, Ib
}, PREFIX_OPCODE
},
2352 { "pextrw", { Gd
, Nq
, Ib
}, PREFIX_OPCODE
},
2353 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2354 { REG_TABLE (REG_0FC7
) },
2356 { "bswap", { RMeAX
}, 0 },
2357 { "bswap", { RMeCX
}, 0 },
2358 { "bswap", { RMeDX
}, 0 },
2359 { "bswap", { RMeBX
}, 0 },
2360 { "bswap", { RMeSP
}, 0 },
2361 { "bswap", { RMeBP
}, 0 },
2362 { "bswap", { RMeSI
}, 0 },
2363 { "bswap", { RMeDI
}, 0 },
2365 { PREFIX_TABLE (PREFIX_0FD0
) },
2366 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2367 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2368 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2369 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2370 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2371 { PREFIX_TABLE (PREFIX_0FD6
) },
2372 { "pmovmskb", { Gdq
, Nq
}, PREFIX_OPCODE
},
2374 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2375 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2376 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2377 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2378 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2379 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2380 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2381 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2383 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2384 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2385 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2386 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2387 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2388 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2389 { PREFIX_TABLE (PREFIX_0FE6
) },
2390 { PREFIX_TABLE (PREFIX_0FE7
) },
2392 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2393 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2394 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2395 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2396 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2397 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2398 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2399 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2401 { PREFIX_TABLE (PREFIX_0FF0
) },
2402 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2403 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2404 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2405 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2406 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2407 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2408 { PREFIX_TABLE (PREFIX_0FF7
) },
2410 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2411 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2412 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2413 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2414 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2415 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2416 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2417 { "ud0S", { Gv
, Ev
}, 0 },
2420 static const bool onebyte_has_modrm
[256] = {
2421 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2422 /* ------------------------------- */
2423 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2424 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2425 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2426 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2427 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2428 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2429 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2430 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2431 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2432 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2433 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2434 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2435 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2436 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2437 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2438 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2439 /* ------------------------------- */
2440 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2443 static const bool twobyte_has_modrm
[256] = {
2444 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2445 /* ------------------------------- */
2446 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2447 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2448 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2449 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2450 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2451 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2452 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2453 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2454 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2455 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2456 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2457 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2458 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2459 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2460 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2461 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2462 /* ------------------------------- */
2463 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2473 /* If we are accessing mod/rm/reg without need_modrm set, then the
2474 values are stale. Hitting this abort likely indicates that you
2475 need to update onebyte_has_modrm or twobyte_has_modrm. */
2476 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2478 static const char intel_index16
[][6] = {
2479 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2482 static const char att_names64
[][8] = {
2483 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2484 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2485 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2486 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2488 static const char att_names32
[][8] = {
2489 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2490 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2491 "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2492 "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2494 static const char att_names16
[][8] = {
2495 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2496 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2497 "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2498 "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2500 static const char att_names8
[][8] = {
2501 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2503 static const char att_names8rex
[][8] = {
2504 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2505 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2506 "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2507 "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2509 static const char att_names_seg
[][4] = {
2510 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2512 static const char att_index64
[] = "%riz";
2513 static const char att_index32
[] = "%eiz";
2514 static const char att_index16
[][8] = {
2515 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2518 static const char att_names_mm
[][8] = {
2519 "%mm0", "%mm1", "%mm2", "%mm3",
2520 "%mm4", "%mm5", "%mm6", "%mm7"
2523 static const char att_names_bnd
[][8] = {
2524 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2527 static const char att_names_xmm
[][8] = {
2528 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2529 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2530 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2531 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2532 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2533 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2534 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2535 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2538 static const char att_names_ymm
[][8] = {
2539 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2540 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2541 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2542 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2543 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2544 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2545 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2546 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2549 static const char att_names_zmm
[][8] = {
2550 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2551 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2552 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2553 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2554 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2555 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2556 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2557 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2560 static const char att_names_tmm
[][8] = {
2561 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2562 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2565 static const char att_names_mask
[][8] = {
2566 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2569 static const char *const names_rounding
[] =
2577 static const struct dis386 reg_table
[][8] = {
2580 { "addA", { Ebh1
, Ib
}, 0 },
2581 { "orA", { Ebh1
, Ib
}, 0 },
2582 { "adcA", { Ebh1
, Ib
}, 0 },
2583 { "sbbA", { Ebh1
, Ib
}, 0 },
2584 { "andA", { Ebh1
, Ib
}, 0 },
2585 { "subA", { Ebh1
, Ib
}, 0 },
2586 { "xorA", { Ebh1
, Ib
}, 0 },
2587 { "cmpA", { Eb
, Ib
}, 0 },
2591 { "addQ", { Evh1
, Iv
}, 0 },
2592 { "orQ", { Evh1
, Iv
}, 0 },
2593 { "adcQ", { Evh1
, Iv
}, 0 },
2594 { "sbbQ", { Evh1
, Iv
}, 0 },
2595 { "andQ", { Evh1
, Iv
}, 0 },
2596 { "subQ", { Evh1
, Iv
}, 0 },
2597 { "xorQ", { Evh1
, Iv
}, 0 },
2598 { "cmpQ", { Ev
, Iv
}, 0 },
2602 { "addQ", { Evh1
, sIb
}, 0 },
2603 { "orQ", { Evh1
, sIb
}, 0 },
2604 { "adcQ", { Evh1
, sIb
}, 0 },
2605 { "sbbQ", { Evh1
, sIb
}, 0 },
2606 { "andQ", { Evh1
, sIb
}, 0 },
2607 { "subQ", { Evh1
, sIb
}, 0 },
2608 { "xorQ", { Evh1
, sIb
}, 0 },
2609 { "cmpQ", { Ev
, sIb
}, 0 },
2613 { "pop{P|}", { stackEv
}, 0 },
2614 { XOP_8F_TABLE () },
2618 { XOP_8F_TABLE () },
2622 { "rolA", { VexGb
, Eb
, Ib
}, NO_PREFIX
},
2623 { "rorA", { VexGb
, Eb
, Ib
}, NO_PREFIX
},
2624 { "rclA", { VexGb
, Eb
, Ib
}, NO_PREFIX
},
2625 { "rcrA", { VexGb
, Eb
, Ib
}, NO_PREFIX
},
2626 { "shlA", { VexGb
, Eb
, Ib
}, NO_PREFIX
},
2627 { "shrA", { VexGb
, Eb
, Ib
}, NO_PREFIX
},
2628 { "shlA", { VexGb
, Eb
, Ib
}, NO_PREFIX
},
2629 { "sarA", { VexGb
, Eb
, Ib
}, NO_PREFIX
},
2633 { "rolQ", { VexGv
, Ev
, Ib
}, PREFIX_NP_OR_DATA
},
2634 { "rorQ", { VexGv
, Ev
, Ib
}, PREFIX_NP_OR_DATA
},
2635 { "rclQ", { VexGv
, Ev
, Ib
}, PREFIX_NP_OR_DATA
},
2636 { "rcrQ", { VexGv
, Ev
, Ib
}, PREFIX_NP_OR_DATA
},
2637 { "shlQ", { VexGv
, Ev
, Ib
}, PREFIX_NP_OR_DATA
},
2638 { "shrQ", { VexGv
, Ev
, Ib
}, PREFIX_NP_OR_DATA
},
2639 { "shlQ", { VexGv
, Ev
, Ib
}, PREFIX_NP_OR_DATA
},
2640 { "sarQ", { VexGv
, Ev
, Ib
}, PREFIX_NP_OR_DATA
},
2644 { "movA", { Ebh3
, Ib
}, 0 },
2651 { RM_TABLE (RM_C6_REG_7
) },
2655 { "movQ", { Evh3
, Iv
}, 0 },
2662 { RM_TABLE (RM_C7_REG_7
) },
2666 { "rolA", { VexGb
, Eb
, I1
}, NO_PREFIX
},
2667 { "rorA", { VexGb
, Eb
, I1
}, NO_PREFIX
},
2668 { "rclA", { VexGb
, Eb
, I1
}, NO_PREFIX
},
2669 { "rcrA", { VexGb
, Eb
, I1
}, NO_PREFIX
},
2670 { "shlA", { VexGb
, Eb
, I1
}, NO_PREFIX
},
2671 { "shrA", { VexGb
, Eb
, I1
}, NO_PREFIX
},
2672 { "shlA", { VexGb
, Eb
, I1
}, NO_PREFIX
},
2673 { "sarA", { VexGb
, Eb
, I1
}, NO_PREFIX
},
2677 { "rolQ", { VexGv
, Ev
, I1
}, PREFIX_NP_OR_DATA
},
2678 { "rorQ", { VexGv
, Ev
, I1
}, PREFIX_NP_OR_DATA
},
2679 { "rclQ", { VexGv
, Ev
, I1
}, PREFIX_NP_OR_DATA
},
2680 { "rcrQ", { VexGv
, Ev
, I1
}, PREFIX_NP_OR_DATA
},
2681 { "shlQ", { VexGv
, Ev
, I1
}, PREFIX_NP_OR_DATA
},
2682 { "shrQ", { VexGv
, Ev
, I1
}, PREFIX_NP_OR_DATA
},
2683 { "shlQ", { VexGv
, Ev
, I1
}, PREFIX_NP_OR_DATA
},
2684 { "sarQ", { VexGv
, Ev
, I1
}, PREFIX_NP_OR_DATA
},
2688 { "rolA", { VexGb
, Eb
, CL
}, NO_PREFIX
},
2689 { "rorA", { VexGb
, Eb
, CL
}, NO_PREFIX
},
2690 { "rclA", { VexGb
, Eb
, CL
}, NO_PREFIX
},
2691 { "rcrA", { VexGb
, Eb
, CL
}, NO_PREFIX
},
2692 { "shlA", { VexGb
, Eb
, CL
}, NO_PREFIX
},
2693 { "shrA", { VexGb
, Eb
, CL
}, NO_PREFIX
},
2694 { "shlA", { VexGb
, Eb
, CL
}, NO_PREFIX
},
2695 { "sarA", { VexGb
, Eb
, CL
}, NO_PREFIX
},
2699 { "rolQ", { VexGv
, Ev
, CL
}, PREFIX_NP_OR_DATA
},
2700 { "rorQ", { VexGv
, Ev
, CL
}, PREFIX_NP_OR_DATA
},
2701 { "rclQ", { VexGv
, Ev
, CL
}, PREFIX_NP_OR_DATA
},
2702 { "rcrQ", { VexGv
, Ev
, CL
}, PREFIX_NP_OR_DATA
},
2703 { "shlQ", { VexGv
, Ev
, CL
}, PREFIX_NP_OR_DATA
},
2704 { "shrQ", { VexGv
, Ev
, CL
}, PREFIX_NP_OR_DATA
},
2705 { "shlQ", { VexGv
, Ev
, CL
}, PREFIX_NP_OR_DATA
},
2706 { "sarQ", { VexGv
, Ev
, CL
}, PREFIX_NP_OR_DATA
},
2710 { "testA", { Eb
, Ib
}, 0 },
2711 { "testA", { Eb
, Ib
}, 0 },
2712 { "notA", { Ebh1
}, 0 },
2713 { "negA", { Ebh1
}, 0 },
2714 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2715 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2716 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2717 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2721 { "testQ", { Ev
, Iv
}, 0 },
2722 { "testQ", { Ev
, Iv
}, 0 },
2723 { "notQ", { Evh1
}, 0 },
2724 { "negQ", { Evh1
}, 0 },
2725 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2726 { "imulQ", { Ev
}, 0 },
2727 { "divQ", { Ev
}, 0 },
2728 { "idivQ", { Ev
}, 0 },
2732 { "incA", { Ebh1
}, 0 },
2733 { "decA", { Ebh1
}, 0 },
2737 { "incQ", { Evh1
}, 0 },
2738 { "decQ", { Evh1
}, 0 },
2739 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2740 { "{l|}call^", { indirEp
}, 0 },
2741 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2742 { "{l|}jmp^", { indirEp
}, 0 },
2743 { "push{P|}", { stackEv
}, 0 },
2748 { "sldtD", { Sv
}, 0 },
2749 { "strD", { Sv
}, 0 },
2750 { "lldtD", { Sv
}, 0 },
2751 { "ltrD", { Sv
}, 0 },
2752 { "verrD", { Sv
}, 0 },
2753 { "verwD", { Sv
}, 0 },
2754 { X86_64_TABLE (X86_64_0F00_REG_6
) },
2759 { MOD_TABLE (MOD_0F01_REG_0
) },
2760 { MOD_TABLE (MOD_0F01_REG_1
) },
2761 { MOD_TABLE (MOD_0F01_REG_2
) },
2762 { MOD_TABLE (MOD_0F01_REG_3
) },
2763 { "smswD", { Sv
}, 0 },
2764 { MOD_TABLE (MOD_0F01_REG_5
) },
2765 { "lmsw", { Ew
}, 0 },
2766 { MOD_TABLE (MOD_0F01_REG_7
) },
2770 { "prefetch", { Mb
}, 0 },
2771 { "prefetchw", { Mb
}, 0 },
2772 { "prefetchwt1", { Mb
}, 0 },
2773 { "prefetch", { Mb
}, 0 },
2774 { "prefetch", { Mb
}, 0 },
2775 { "prefetch", { Mb
}, 0 },
2776 { "prefetch", { Mb
}, 0 },
2777 { "prefetch", { Mb
}, 0 },
2781 { MOD_TABLE (MOD_0F18_REG_0
) },
2782 { MOD_TABLE (MOD_0F18_REG_1
) },
2783 { MOD_TABLE (MOD_0F18_REG_2
) },
2784 { MOD_TABLE (MOD_0F18_REG_3
) },
2785 { "nopQ", { Ev
}, 0 },
2786 { "nopQ", { Ev
}, 0 },
2787 { MOD_TABLE (MOD_0F18_REG_6
) },
2788 { MOD_TABLE (MOD_0F18_REG_7
) },
2790 /* REG_0F1C_P_0_MOD_0 */
2792 { "cldemote", { Mb
}, 0 },
2793 { "nopQ", { Ev
}, 0 },
2794 { "nopQ", { Ev
}, 0 },
2795 { "nopQ", { Ev
}, 0 },
2796 { "nopQ", { Ev
}, 0 },
2797 { "nopQ", { Ev
}, 0 },
2798 { "nopQ", { Ev
}, 0 },
2799 { "nopQ", { Ev
}, 0 },
2801 /* REG_0F1E_P_1_MOD_3 */
2803 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2804 { "rdsspK", { Edq
}, 0 },
2805 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2806 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2807 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2808 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2809 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2810 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2812 /* REG_0F38D8_PREFIX_1 */
2814 { "aesencwide128kl", { M
}, 0 },
2815 { "aesdecwide128kl", { M
}, 0 },
2816 { "aesencwide256kl", { M
}, 0 },
2817 { "aesdecwide256kl", { M
}, 0 },
2819 /* REG_0F3A0F_P_1 */
2821 { RM_TABLE (RM_0F3A0F_P_1_R_0
) },
2827 { "psrlw", { Nq
, Ib
}, PREFIX_OPCODE
},
2829 { "psraw", { Nq
, Ib
}, PREFIX_OPCODE
},
2831 { "psllw", { Nq
, Ib
}, PREFIX_OPCODE
},
2837 { "psrld", { Nq
, Ib
}, PREFIX_OPCODE
},
2839 { "psrad", { Nq
, Ib
}, PREFIX_OPCODE
},
2841 { "pslld", { Nq
, Ib
}, PREFIX_OPCODE
},
2847 { "psrlq", { Nq
, Ib
}, PREFIX_OPCODE
},
2848 { "psrldq", { Ux
, Ib
}, PREFIX_DATA
},
2851 { "psllq", { Nq
, Ib
}, PREFIX_OPCODE
},
2852 { "pslldq", { Ux
, Ib
}, PREFIX_DATA
},
2856 { "montmul", { { OP_0f07
, 0 } }, 0 },
2857 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2858 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2862 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2863 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2864 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2865 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2866 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2867 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2871 { MOD_TABLE (MOD_0FAE_REG_0
) },
2872 { MOD_TABLE (MOD_0FAE_REG_1
) },
2873 { MOD_TABLE (MOD_0FAE_REG_2
) },
2874 { MOD_TABLE (MOD_0FAE_REG_3
) },
2875 { MOD_TABLE (MOD_0FAE_REG_4
) },
2876 { MOD_TABLE (MOD_0FAE_REG_5
) },
2877 { MOD_TABLE (MOD_0FAE_REG_6
) },
2878 { MOD_TABLE (MOD_0FAE_REG_7
) },
2886 { "btQ", { Ev
, Ib
}, 0 },
2887 { "btsQ", { Evh1
, Ib
}, 0 },
2888 { "btrQ", { Evh1
, Ib
}, 0 },
2889 { "btcQ", { Evh1
, Ib
}, 0 },
2894 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
2896 { "xrstors", { FXSAVE
}, PREFIX_REX2_ILLEGAL
},
2897 { "xsavec", { FXSAVE
}, PREFIX_REX2_ILLEGAL
},
2898 { "xsaves", { FXSAVE
}, PREFIX_REX2_ILLEGAL
},
2899 { MOD_TABLE (MOD_0FC7_REG_6
) },
2900 { MOD_TABLE (MOD_0FC7_REG_7
) },
2906 { "vpsrlw", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2908 { "vpsraw", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2910 { "vpsllw", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2916 { "vpsrld", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2918 { "vpsrad", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2920 { "vpslld", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2926 { "vpsrlq", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2927 { "vpsrldq", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2930 { "vpsllq", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2931 { "vpslldq", { Vex
, Ux
, Ib
}, PREFIX_DATA
},
2937 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2
) },
2938 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3
) },
2940 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2942 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0
) },
2944 /* REG_VEX_0F38F3_L_0_P_0 */
2947 { "blsrS", { VexGdq
, Edq
}, 0 },
2948 { "blsmskS", { VexGdq
, Edq
}, 0 },
2949 { "blsiS", { VexGdq
, Edq
}, 0 },
2951 /* REG_VEX_MAP7_F8_L_0_W_0 */
2953 { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0
) },
2955 /* REG_XOP_09_01_L_0 */
2958 { "blcfill", { VexGdq
, Edq
}, 0 },
2959 { "blsfill", { VexGdq
, Edq
}, 0 },
2960 { "blcs", { VexGdq
, Edq
}, 0 },
2961 { "tzmsk", { VexGdq
, Edq
}, 0 },
2962 { "blcic", { VexGdq
, Edq
}, 0 },
2963 { "blsic", { VexGdq
, Edq
}, 0 },
2964 { "t1mskc", { VexGdq
, Edq
}, 0 },
2966 /* REG_XOP_09_02_L_0 */
2969 { "blcmsk", { VexGdq
, Edq
}, 0 },
2974 { "blci", { VexGdq
, Edq
}, 0 },
2976 /* REG_XOP_09_12_L_0 */
2978 { "llwpcb", { Rdq
}, 0 },
2979 { "slwpcb", { Rdq
}, 0 },
2981 /* REG_XOP_0A_12_L_0 */
2983 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
2984 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
2987 #include "i386-dis-evex-reg.h"
2990 static const struct dis386 prefix_table
[][4] = {
2993 { "xchgS", { { NOP_Fixup
, 0 }, { NOP_Fixup
, 1 } }, 0 },
2994 { "pause", { XX
}, 0 },
2995 { "xchgS", { { NOP_Fixup
, 0 }, { NOP_Fixup
, 1 } }, 0 },
2996 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
2999 /* PREFIX_0F00_REG_6_X86_64 */
3004 { "lkgsD", { Sv
}, 0 },
3007 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3009 { "wrmsrns", { Skip_MODRM
}, 0 },
3010 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1
) },
3012 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3
) },
3015 /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3017 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0
) },
3020 /* PREFIX_0F01_REG_1_RM_2 */
3022 { "clac", { Skip_MODRM
}, 0 },
3023 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1
) },
3025 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3
)},
3028 /* PREFIX_0F01_REG_1_RM_4 */
3032 { "tdcall", { Skip_MODRM
}, 0 },
3036 /* PREFIX_0F01_REG_1_RM_5 */
3040 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2
) },
3044 /* PREFIX_0F01_REG_1_RM_6 */
3048 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2
) },
3052 /* PREFIX_0F01_REG_1_RM_7 */
3054 { "encls", { Skip_MODRM
}, 0 },
3056 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2
) },
3060 /* PREFIX_0F01_REG_3_RM_1 */
3062 { "vmmcall", { Skip_MODRM
}, 0 },
3063 { "vmgexit", { Skip_MODRM
}, 0 },
3065 { "vmgexit", { Skip_MODRM
}, 0 },
3068 /* PREFIX_0F01_REG_5_MOD_0 */
3071 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3074 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3076 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3077 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3079 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3082 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3087 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3090 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3093 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3096 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3099 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
) },
3102 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3105 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
) },
3108 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3110 { "rdpkru", { Skip_MODRM
}, 0 },
3111 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
) },
3114 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3116 { "wrpkru", { Skip_MODRM
}, 0 },
3117 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
) },
3120 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3122 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3123 { "mcommit", { Skip_MODRM
}, 0 },
3126 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3128 { "rdpru", { Skip_MODRM
}, 0 },
3129 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1
) },
3132 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3134 { "invlpgb", { Skip_MODRM
}, 0 },
3135 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
) },
3137 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
) },
3140 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3142 { "tlbsync", { Skip_MODRM
}, 0 },
3143 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
) },
3145 { "pvalidate", { Skip_MODRM
}, 0 },
3150 { "wbinvd", { XX
}, 0 },
3151 { "wbnoinvd", { XX
}, 0 },
3156 { "%XEVmovupX", { XM
, EXEvexXNoBcst
}, 0 },
3157 { "%XEVmovs%XS", { XMScalar
, VexScalarR
, EXd
}, 0 },
3158 { "%XEVmovupX", { XM
, EXEvexXNoBcst
}, 0 },
3159 { "%XEVmovs%XD", { XMScalar
, VexScalarR
, EXq
}, 0 },
3164 { "%XEVmovupX", { EXxS
, XM
}, 0 },
3165 { "%XEVmovs%XS", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3166 { "%XEVmovupX", { EXxS
, XM
}, 0 },
3167 { "%XEVmovs%XD", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3172 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3173 { "movsldup", { XM
, EXx
}, 0 },
3174 { "%XEVmovlpYX", { XM
, Vex
, Mq
}, 0 },
3175 { "movddup", { XM
, EXq
}, 0 },
3180 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3181 { "movshdup", { XM
, EXx
}, 0 },
3182 { "%XEVmovhpYX", { XM
, Vex
, Mq
}, 0 },
3185 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3187 { "prefetchit1", { { PREFETCHI_Fixup
, b_mode
} }, 0 },
3188 { "nopQ", { Ev
}, 0 },
3189 { "nopQ", { Ev
}, 0 },
3190 { "nopQ", { Ev
}, 0 },
3193 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3195 { "prefetchit0", { { PREFETCHI_Fixup
, b_mode
} }, 0 },
3196 { "nopQ", { Ev
}, 0 },
3197 { "nopQ", { Ev
}, 0 },
3198 { "nopQ", { Ev
}, 0 },
3203 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3204 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3205 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3206 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3211 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3212 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3213 { "bndmov", { EbndS
, Gbnd
}, 0 },
3214 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3219 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3220 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3221 { "nopQ", { Ev
}, 0 },
3222 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3227 { "nopQ", { Ev
}, 0 },
3228 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3229 { "nopQ", { Ev
}, 0 },
3230 { NULL
, { XX
}, PREFIX_IGNORED
},
3235 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3236 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3237 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3238 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3243 { "movntps", { Mx
, XM
}, 0 },
3244 { "movntss", { Md
, XM
}, 0 },
3245 { "movntpd", { Mx
, XM
}, 0 },
3246 { "movntsd", { Mq
, XM
}, 0 },
3251 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3252 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3253 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3254 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3259 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3260 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3261 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3262 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3267 { "%XEVucomisYX", { XMScalar
, EXd
, EXxEVexS
}, 0 },
3269 { "%XEVucomisYX", { XMScalar
, EXq
, EXxEVexS
}, 0 },
3274 { "%XEVcomisYX", { XMScalar
, EXd
, EXxEVexS
}, 0 },
3276 { "%XEVcomisYX", { XMScalar
, EXq
, EXxEVexS
}, 0 },
3281 { "%XEVsqrtpX", { XM
, EXx
, EXxEVexR
}, 0 },
3282 { "%XEVsqrts%XS", { XMScalar
, VexScalar
, EXd
, EXxEVexR
}, 0 },
3283 { "%XEVsqrtpX", { XM
, EXx
, EXxEVexR
}, 0 },
3284 { "%XEVsqrts%XD", { XMScalar
, VexScalar
, EXq
, EXxEVexR
}, 0 },
3289 { "Vrsqrtps", { XM
, EXx
}, 0 },
3290 { "Vrsqrtss", { XMScalar
, VexScalar
, EXd
}, 0 },
3295 { "Vrcpps", { XM
, EXx
}, 0 },
3296 { "Vrcpss", { XMScalar
, VexScalar
, EXd
}, 0 },
3301 { "%XEVaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
3302 { "%XEVadds%XS", { XMScalar
, VexScalar
, EXd
, EXxEVexR
}, 0 },
3303 { "%XEVaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
3304 { "%XEVadds%XD", { XMScalar
, VexScalar
, EXq
, EXxEVexR
}, 0 },
3309 { "%XEVmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
3310 { "%XEVmuls%XS", { XMScalar
, VexScalar
, EXd
, EXxEVexR
}, 0 },
3311 { "%XEVmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
3312 { "%XEVmuls%XD", { XMScalar
, VexScalar
, EXq
, EXxEVexR
}, 0 },
3317 { "%XEVcvtp%XS2pd", { XM
, EXEvexHalfBcstXmmq
, EXxEVexS
}, 0 },
3318 { "%XEVcvts%XS2sd", { XMScalar
, VexScalar
, EXd
, EXxEVexS
}, 0 },
3319 { "%XEVcvtp%XD2ps%XY", { XMxmmq
, EXx
, EXxEVexR
}, 0 },
3320 { "%XEVcvts%XD2ss", { XMScalar
, VexScalar
, EXq
, EXxEVexR
}, 0 },
3325 { "Vcvtdq2ps", { XM
, EXx
}, 0 },
3326 { "Vcvttps2dq", { XM
, EXx
}, 0 },
3327 { "Vcvtps2dq", { XM
, EXx
}, 0 },
3332 { "%XEVsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
3333 { "%XEVsubs%XS", { XMScalar
, VexScalar
, EXd
, EXxEVexR
}, 0 },
3334 { "%XEVsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
3335 { "%XEVsubs%XD", { XMScalar
, VexScalar
, EXq
, EXxEVexR
}, 0 },
3340 { "%XEVminpX", { XM
, Vex
, EXx
, EXxEVexS
}, 0 },
3341 { "%XEVmins%XS", { XMScalar
, VexScalar
, EXd
, EXxEVexS
}, 0 },
3342 { "%XEVminpX", { XM
, Vex
, EXx
, EXxEVexS
}, 0 },
3343 { "%XEVmins%XD", { XMScalar
, VexScalar
, EXq
, EXxEVexS
}, 0 },
3348 { "%XEVdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
3349 { "%XEVdivs%XS", { XMScalar
, VexScalar
, EXd
, EXxEVexR
}, 0 },
3350 { "%XEVdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
3351 { "%XEVdivs%XD", { XMScalar
, VexScalar
, EXq
, EXxEVexR
}, 0 },
3356 { "%XEVmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, 0 },
3357 { "%XEVmaxs%XS", { XMScalar
, VexScalar
, EXd
, EXxEVexS
}, 0 },
3358 { "%XEVmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, 0 },
3359 { "%XEVmaxs%XD", { XMScalar
, VexScalar
, EXq
, EXxEVexS
}, 0 },
3364 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3366 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3371 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3373 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3378 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3380 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3385 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3386 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3387 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3392 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3393 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3394 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3395 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3400 {"vmread", { Em
, Gm
}, 0 },
3402 {"extrq", { Uxmm
, Ib
, Ib
}, 0 },
3403 {"insertq", { XM
, Uxmm
, Ib
, Ib
}, 0 },
3408 {"vmwrite", { Gm
, Em
}, 0 },
3410 {"extrq", { XM
, Uxmm
}, 0 },
3411 {"insertq", { XM
, Uxmm
}, 0 },
3418 { "Vhaddpd", { XM
, Vex
, EXx
}, 0 },
3419 { "Vhaddps", { XM
, Vex
, EXx
}, 0 },
3426 { "Vhsubpd", { XM
, Vex
, EXx
}, 0 },
3427 { "Vhsubps", { XM
, Vex
, EXx
}, 0 },
3432 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3433 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3434 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3439 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3440 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3441 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3444 /* PREFIX_0FAE_REG_0_MOD_3 */
3447 { "rdfsbase", { Ev
}, 0 },
3450 /* PREFIX_0FAE_REG_1_MOD_3 */
3453 { "rdgsbase", { Ev
}, 0 },
3456 /* PREFIX_0FAE_REG_2_MOD_3 */
3459 { "wrfsbase", { Ev
}, 0 },
3462 /* PREFIX_0FAE_REG_3_MOD_3 */
3465 { "wrgsbase", { Ev
}, 0 },
3468 /* PREFIX_0FAE_REG_4_MOD_0 */
3470 { "xsave", { FXSAVE
}, PREFIX_REX2_ILLEGAL
},
3471 { "ptwrite{%LQ|}", { Edq
}, 0 },
3474 /* PREFIX_0FAE_REG_4_MOD_3 */
3477 { "ptwrite{%LQ|}", { Edq
}, 0 },
3480 /* PREFIX_0FAE_REG_5_MOD_3 */
3482 { "lfence", { Skip_MODRM
}, 0 },
3483 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3486 /* PREFIX_0FAE_REG_6_MOD_0 */
3488 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
| PREFIX_REX2_ILLEGAL
},
3489 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3490 { "clwb", { Mb
}, PREFIX_OPCODE
},
3493 /* PREFIX_0FAE_REG_6_MOD_3 */
3495 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3496 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3497 { "tpause", { Edq
}, PREFIX_OPCODE
},
3498 { "umwait", { Edq
}, PREFIX_OPCODE
},
3501 /* PREFIX_0FAE_REG_7_MOD_0 */
3503 { "clflush", { Mb
}, 0 },
3505 { "clflushopt", { Mb
}, 0 },
3511 { "popcntS", { Gv
, Ev
}, 0 },
3516 { "bsfS", { Gv
, Ev
}, 0 },
3517 { "tzcntS", { Gv
, Ev
}, 0 },
3518 { "bsfS", { Gv
, Ev
}, 0 },
3523 { "bsrS", { Gv
, Ev
}, 0 },
3524 { "lzcntS", { Gv
, Ev
}, 0 },
3525 { "bsrS", { Gv
, Ev
}, 0 },
3530 { "VcmppX", { XM
, Vex
, EXx
, CMP
}, 0 },
3531 { "Vcmpss", { XMScalar
, VexScalar
, EXd
, CMP
}, 0 },
3532 { "VcmppX", { XM
, Vex
, EXx
, CMP
}, 0 },
3533 { "Vcmpsd", { XMScalar
, VexScalar
, EXq
, CMP
}, 0 },
3536 /* PREFIX_0FC7_REG_6_MOD_0 */
3538 { "vmptrld",{ Mq
}, 0 },
3539 { "vmxon", { Mq
}, 0 },
3540 { "vmclear",{ Mq
}, 0 },
3543 /* PREFIX_0FC7_REG_6_MOD_3 */
3545 { "rdrand", { Ev
}, 0 },
3546 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1
) },
3547 { "rdrand", { Ev
}, 0 }
3550 /* PREFIX_0FC7_REG_7_MOD_3 */
3552 { "rdseed", { Ev
}, 0 },
3553 { "rdpid", { Em
}, 0 },
3554 { "rdseed", { Ev
}, 0 },
3561 { "VaddsubpX", { XM
, Vex
, EXx
}, 0 },
3562 { "VaddsubpX", { XM
, Vex
, EXx
}, 0 },
3568 { "movq2dq",{ XM
, Nq
}, 0 },
3569 { "movq", { EXqS
, XM
}, 0 },
3570 { "movdq2q",{ MX
, Ux
}, 0 },
3576 { "Vcvtdq2pd", { XM
, EXxmmq
}, 0 },
3577 { "Vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
3578 { "Vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
3583 { "movntq", { Mq
, MX
}, 0 },
3585 { "movntdq", { Mx
, XM
}, 0 },
3593 { "Vlddqu", { XM
, M
}, 0 },
3598 { "maskmovq", { MX
, Nq
}, PREFIX_OPCODE
},
3600 { "maskmovdqu", { XM
, Ux
}, PREFIX_OPCODE
},
3606 { REG_TABLE (REG_0F38D8_PREFIX_1
) },
3612 { MOD_TABLE (MOD_0F38DC_PREFIX_1
) },
3613 { "aesenc", { XM
, EXx
}, 0 },
3619 { "aesdec128kl", { XM
, M
}, 0 },
3620 { "aesenclast", { XM
, EXx
}, 0 },
3626 { "aesenc256kl", { XM
, M
}, 0 },
3627 { "aesdec", { XM
, EXx
}, 0 },
3633 { "aesdec256kl", { XM
, M
}, 0 },
3634 { "aesdeclast", { XM
, EXx
}, 0 },
3639 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3641 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3642 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3647 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3649 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3650 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3655 { "wrssK", { M
, Gdq
}, 0 },
3656 { "adoxL", { VexGdq
, Gdq
, Edq
}, 0 },
3657 { "adcxL", { VexGdq
, Gdq
, Edq
}, 0 },
3661 /* PREFIX_0F38F8_M_0 */
3664 { "enqcmds", { Gva
, M
}, 0 },
3665 { "movdir64b", { Gva
, M
}, 0 },
3666 { "enqcmd", { Gva
, M
}, 0 },
3669 /* PREFIX_0F38F8_M_1_X86_64 */
3672 { "uwrmsr", { Gq
, Rq
}, 0 },
3674 { "urdmsr", { Rq
, Gq
}, 0 },
3680 { "encodekey128", { Gd
, Rd
}, 0 },
3686 { "encodekey256", { Gd
, Rd
}, 0 },
3691 { "aadd", { Mdq
, Gdq
}, 0 },
3692 { "axor", { Mdq
, Gdq
}, 0 },
3693 { "aand", { Mdq
, Gdq
}, 0 },
3694 { "aor", { Mdq
, Gdq
}, 0 },
3700 { REG_TABLE (REG_0F3A0F_P_1
) },
3703 /* PREFIX_VEX_0F12 */
3705 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0
) },
3706 { "%XEvmov%XSldup", { XM
, EXEvexXNoBcst
}, 0 },
3707 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
3708 { "%XEvmov%XDdup", { XM
, EXymmq
}, 0 },
3711 /* PREFIX_VEX_0F16 */
3713 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0
) },
3714 { "%XEvmov%XShdup", { XM
, EXEvexXNoBcst
}, 0 },
3715 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
3718 /* PREFIX_VEX_0F2A */
3721 { "%XEvcvtsi2ssY{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
3723 { "%XEvcvtsi2sdY{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR64
, Edq
}, 0 },
3726 /* PREFIX_VEX_0F2C */
3729 { "%XEvcvttss2si", { Gdq
, EXd
, EXxEVexS
}, 0 },
3731 { "%XEvcvttsd2si", { Gdq
, EXq
, EXxEVexS
}, 0 },
3734 /* PREFIX_VEX_0F2D */
3737 { "%XEvcvtss2si", { Gdq
, EXd
, EXxEVexR
}, 0 },
3739 { "%XEvcvtsd2si", { Gdq
, EXq
, EXxEVexR
}, 0 },
3742 /* PREFIX_VEX_0F41_L_1_W_0 */
3744 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
3746 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
3749 /* PREFIX_VEX_0F41_L_1_W_1 */
3751 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
3753 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
3756 /* PREFIX_VEX_0F42_L_1_W_0 */
3758 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
3760 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
3763 /* PREFIX_VEX_0F42_L_1_W_1 */
3765 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
3767 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
3770 /* PREFIX_VEX_0F44_L_0_W_0 */
3772 { "knotw", { MaskG
, MaskR
}, 0 },
3774 { "knotb", { MaskG
, MaskR
}, 0 },
3777 /* PREFIX_VEX_0F44_L_0_W_1 */
3779 { "knotq", { MaskG
, MaskR
}, 0 },
3781 { "knotd", { MaskG
, MaskR
}, 0 },
3784 /* PREFIX_VEX_0F45_L_1_W_0 */
3786 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
3788 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
3791 /* PREFIX_VEX_0F45_L_1_W_1 */
3793 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
3795 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
3798 /* PREFIX_VEX_0F46_L_1_W_0 */
3800 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
3802 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
3805 /* PREFIX_VEX_0F46_L_1_W_1 */
3807 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
3809 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
3812 /* PREFIX_VEX_0F47_L_1_W_0 */
3814 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
3816 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
3819 /* PREFIX_VEX_0F47_L_1_W_1 */
3821 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
3823 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
3826 /* PREFIX_VEX_0F4A_L_1_W_0 */
3828 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
3830 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
3833 /* PREFIX_VEX_0F4A_L_1_W_1 */
3835 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
3837 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
3840 /* PREFIX_VEX_0F4B_L_1_W_0 */
3842 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
3844 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
3847 /* PREFIX_VEX_0F4B_L_1_W_1 */
3849 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
3852 /* PREFIX_VEX_0F6F */
3855 { "vmovdqu", { XM
, EXx
}, 0 },
3856 { "vmovdqa", { XM
, EXx
}, 0 },
3859 /* PREFIX_VEX_0F70 */
3862 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3863 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3864 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3867 /* PREFIX_VEX_0F7E */
3870 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3871 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3874 /* PREFIX_VEX_0F7F */
3877 { "vmovdqu", { EXxS
, XM
}, 0 },
3878 { "vmovdqa", { EXxS
, XM
}, 0 },
3881 /* PREFIX_VEX_0F90_L_0_W_0 */
3883 { "kmovw", { MaskG
, MaskE
}, 0 },
3885 { "kmovb", { MaskG
, MaskBDE
}, 0 },
3888 /* PREFIX_VEX_0F90_L_0_W_1 */
3890 { "kmovq", { MaskG
, MaskE
}, 0 },
3892 { "kmovd", { MaskG
, MaskBDE
}, 0 },
3895 /* PREFIX_VEX_0F91_L_0_W_0 */
3897 { "kmovw", { Mw
, MaskG
}, 0 },
3899 { "kmovb", { Mb
, MaskG
}, 0 },
3902 /* PREFIX_VEX_0F91_L_0_W_1 */
3904 { "kmovq", { Mq
, MaskG
}, 0 },
3906 { "kmovd", { Md
, MaskG
}, 0 },
3909 /* PREFIX_VEX_0F92_L_0_W_0 */
3911 { "kmovw", { MaskG
, Rdq
}, 0 },
3913 { "kmovb", { MaskG
, Rdq
}, 0 },
3914 { "kmovd", { MaskG
, Rdq
}, 0 },
3917 /* PREFIX_VEX_0F92_L_0_W_1 */
3922 { "kmovK", { MaskG
, Rdq
}, 0 },
3925 /* PREFIX_VEX_0F93_L_0_W_0 */
3927 { "kmovw", { Gdq
, MaskR
}, 0 },
3929 { "kmovb", { Gdq
, MaskR
}, 0 },
3930 { "kmovd", { Gdq
, MaskR
}, 0 },
3933 /* PREFIX_VEX_0F93_L_0_W_1 */
3938 { "kmovK", { Gdq
, MaskR
}, 0 },
3941 /* PREFIX_VEX_0F98_L_0_W_0 */
3943 { "kortestw", { MaskG
, MaskR
}, 0 },
3945 { "kortestb", { MaskG
, MaskR
}, 0 },
3948 /* PREFIX_VEX_0F98_L_0_W_1 */
3950 { "kortestq", { MaskG
, MaskR
}, 0 },
3952 { "kortestd", { MaskG
, MaskR
}, 0 },
3955 /* PREFIX_VEX_0F99_L_0_W_0 */
3957 { "ktestw", { MaskG
, MaskR
}, 0 },
3959 { "ktestb", { MaskG
, MaskR
}, 0 },
3962 /* PREFIX_VEX_0F99_L_0_W_1 */
3964 { "ktestq", { MaskG
, MaskR
}, 0 },
3966 { "ktestd", { MaskG
, MaskR
}, 0 },
3969 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
3971 { "ldtilecfg", { M
}, 0 },
3973 { "sttilecfg", { M
}, 0 },
3976 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
3978 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0
) },
3981 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3
) },
3984 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
3987 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
3988 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
3989 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
3992 /* PREFIX_VEX_0F3850_W_0 */
3994 { "vpdpbuud", { XM
, Vex
, EXx
}, 0 },
3995 { "vpdpbsud", { XM
, Vex
, EXx
}, 0 },
3996 { "%XVvpdpbusd", { XM
, Vex
, EXx
}, 0 },
3997 { "vpdpbssd", { XM
, Vex
, EXx
}, 0 },
4000 /* PREFIX_VEX_0F3851_W_0 */
4002 { "vpdpbuuds", { XM
, Vex
, EXx
}, 0 },
4003 { "vpdpbsuds", { XM
, Vex
, EXx
}, 0 },
4004 { "%XVvpdpbusds", { XM
, Vex
, EXx
}, 0 },
4005 { "vpdpbssds", { XM
, Vex
, EXx
}, 0 },
4007 /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4010 { "tdpbf16ps", { TMM
, Rtmm
, VexTmm
}, 0 },
4012 { "tdpfp16ps", { TMM
, Rtmm
, VexTmm
}, 0 },
4015 /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4017 { "tdpbuud", {TMM
, Rtmm
, VexTmm
}, 0 },
4018 { "tdpbsud", {TMM
, Rtmm
, VexTmm
}, 0 },
4019 { "tdpbusd", {TMM
, Rtmm
, VexTmm
}, 0 },
4020 { "tdpbssd", {TMM
, Rtmm
, VexTmm
}, 0 },
4023 /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4025 { "tcmmrlfp16ps", { TMM
, Rtmm
, VexTmm
}, 0 },
4027 { "tcmmimfp16ps", { TMM
, Rtmm
, VexTmm
}, 0 },
4030 /* PREFIX_VEX_0F3872 */
4033 { VEX_W_TABLE (VEX_W_0F3872_P_1
) },
4036 /* PREFIX_VEX_0F38B0_W_0 */
4038 { "vcvtneoph2ps", { XM
, Mx
}, 0 },
4039 { "vcvtneebf162ps", { XM
, Mx
}, 0 },
4040 { "vcvtneeph2ps", { XM
, Mx
}, 0 },
4041 { "vcvtneobf162ps", { XM
, Mx
}, 0 },
4044 /* PREFIX_VEX_0F38B1_W_0 */
4047 { "vbcstnebf162ps", { XM
, Mw
}, 0 },
4048 { "vbcstnesh2ps", { XM
, Mw
}, 0 },
4051 /* PREFIX_VEX_0F38D2_W_0 */
4053 { "vpdpwuud", { XM
, Vex
, EXx
}, 0 },
4054 { "vpdpwsud", { XM
, Vex
, EXx
}, 0 },
4055 { "vpdpwusd", { XM
, Vex
, EXx
}, 0 },
4058 /* PREFIX_VEX_0F38D3_W_0 */
4060 { "vpdpwuuds", { XM
, Vex
, EXx
}, 0 },
4061 { "vpdpwsuds", { XM
, Vex
, EXx
}, 0 },
4062 { "vpdpwusds", { XM
, Vex
, EXx
}, 0 },
4065 /* PREFIX_VEX_0F38CB */
4070 { VEX_W_TABLE (VEX_W_0F38CB_P_3
) },
4073 /* PREFIX_VEX_0F38CC */
4078 { VEX_W_TABLE (VEX_W_0F38CC_P_3
) },
4081 /* PREFIX_VEX_0F38CD */
4086 { VEX_W_TABLE (VEX_W_0F38CD_P_3
) },
4089 /* PREFIX_VEX_0F38DA_W_0 */
4091 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0
) },
4092 { "vsm4key4", { XM
, Vex
, EXx
}, 0 },
4093 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2
) },
4094 { "vsm4rnds4", { XM
, Vex
, EXx
}, 0 },
4097 /* PREFIX_VEX_0F38F2_L_0 */
4099 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
4102 /* PREFIX_VEX_0F38F3_L_0 */
4104 { REG_TABLE (REG_VEX_0F38F3_L_0_P_0
) },
4107 /* PREFIX_VEX_0F38F5_L_0 */
4109 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
4110 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
4112 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
4115 /* PREFIX_VEX_0F38F6_L_0 */
4120 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
4123 /* PREFIX_VEX_0F38F7_L_0 */
4125 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
4126 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
4127 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
4128 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
4131 /* PREFIX_VEX_0F3AF0_L_0 */
4136 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
4139 /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4142 { "uwrmsr", { Skip_MODRM
, Id
, Rq
}, 0 },
4144 { "urdmsr", { Rq
, Id
}, 0 },
4147 #include "i386-dis-evex-prefix.h"
4150 static const struct dis386 x86_64_table
[][2] = {
4153 { "pushP", { es
}, 0 },
4158 { "popP", { es
}, 0 },
4163 { "pushP", { cs
}, 0 },
4168 { "pushP", { ss
}, 0 },
4173 { "popP", { ss
}, 0 },
4178 { "pushP", { ds
}, 0 },
4183 { "popP", { ds
}, 0 },
4188 { "daa", { XX
}, 0 },
4193 { "das", { XX
}, 0 },
4198 { "aaa", { XX
}, 0 },
4203 { "aas", { XX
}, 0 },
4208 { "pushaP", { XX
}, 0 },
4213 { "popaP", { XX
}, 0 },
4218 { MOD_TABLE (MOD_62_32BIT
) },
4224 { "arplS", { Sv
, Gv
}, 0 },
4225 { "movs", { Gv
, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4230 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4231 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4236 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4237 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4242 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4243 { REG_TABLE (REG_80
) },
4248 { "{l|}call{P|}", { Ap
}, 0 },
4253 { "retP", { Iw
, BND
}, 0 },
4254 { "ret@", { Iw
, BND
}, 0 },
4259 { "retP", { BND
}, 0 },
4260 { "ret@", { BND
}, 0 },
4265 { MOD_TABLE (MOD_C4_32BIT
) },
4266 { VEX_C4_TABLE () },
4271 { MOD_TABLE (MOD_C5_32BIT
) },
4272 { VEX_C5_TABLE () },
4277 { "into", { XX
}, 0 },
4282 { "aam", { Ib
}, 0 },
4287 { "aad", { Ib
}, 0 },
4292 { "callP", { Jv
, BND
}, 0 },
4293 { "call@", { Jv
, BND
}, PREFIX_REX2_ILLEGAL
}
4298 { "jmpP", { Jv
, BND
}, 0 },
4299 { "jmp@", { Jv
, BND
}, PREFIX_REX2_ILLEGAL
}
4304 { "{l|}jmp{P|}", { Ap
}, 0 },
4307 /* X86_64_0F00_REG_6 */
4310 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64
) },
4313 /* X86_64_0F01_REG_0 */
4315 { "sgdt{Q|Q}", { M
}, 0 },
4316 { "sgdt", { M
}, 0 },
4319 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4322 { "wrmsrlist", { Skip_MODRM
}, 0 },
4325 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4328 { "rdmsrlist", { Skip_MODRM
}, 0 },
4331 /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4334 { "pbndkb", { Skip_MODRM
}, 0 },
4337 /* X86_64_0F01_REG_1 */
4339 { "sidt{Q|Q}", { M
}, 0 },
4340 { "sidt", { M
}, 0 },
4343 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4346 { "eretu", { Skip_MODRM
}, 0 },
4349 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4352 { "erets", { Skip_MODRM
}, 0 },
4355 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4358 { "seamret", { Skip_MODRM
}, 0 },
4361 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4364 { "seamops", { Skip_MODRM
}, 0 },
4367 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4370 { "seamcall", { Skip_MODRM
}, 0 },
4373 /* X86_64_0F01_REG_2 */
4375 { "lgdt{Q|Q}", { M
}, 0 },
4376 { "lgdt", { M
}, 0 },
4379 /* X86_64_0F01_REG_3 */
4381 { "lidt{Q|Q}", { M
}, 0 },
4382 { "lidt", { M
}, 0 },
4385 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4388 { "uiret", { Skip_MODRM
}, 0 },
4391 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4394 { "testui", { Skip_MODRM
}, 0 },
4397 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4400 { "clui", { Skip_MODRM
}, 0 },
4403 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4406 { "stui", { Skip_MODRM
}, 0 },
4409 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4412 { "rmpquery", { Skip_MODRM
}, 0 },
4415 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4418 { "rmpadjust", { Skip_MODRM
}, 0 },
4421 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4424 { "rmpupdate", { Skip_MODRM
}, 0 },
4427 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4430 { "psmash", { Skip_MODRM
}, 0 },
4433 /* X86_64_0F18_REG_6_MOD_0 */
4435 { "nopQ", { Ev
}, 0 },
4436 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64
) },
4439 /* X86_64_0F18_REG_7_MOD_0 */
4441 { "nopQ", { Ev
}, 0 },
4442 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64
) },
4447 { "movZ", { Em
, Td
}, 0 },
4452 { "movZ", { Td
, Em
}, 0 },
4456 /* X86_64_0F38F8_M_1 */
4458 { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64
) },
4461 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4464 { "senduipi", { Eq
}, 0 },
4467 /* X86_64_VEX_0F3849 */
4470 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64
) },
4473 /* X86_64_VEX_0F384B */
4476 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64
) },
4479 /* X86_64_VEX_0F385C */
4482 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64
) },
4485 /* X86_64_VEX_0F385E */
4488 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64
) },
4491 /* X86_64_VEX_0F386C */
4494 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64
) },
4497 /* X86_64_VEX_0F38E0 */
4500 { "cmpoxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4503 /* X86_64_VEX_0F38E1 */
4506 { "cmpnoxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4509 /* X86_64_VEX_0F38E2 */
4512 { "cmpbxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4515 /* X86_64_VEX_0F38E3 */
4518 { "cmpnbxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4521 /* X86_64_VEX_0F38E4 */
4524 { "cmpzxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4527 /* X86_64_VEX_0F38E5 */
4530 { "cmpnzxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4533 /* X86_64_VEX_0F38E6 */
4536 { "cmpbexadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4539 /* X86_64_VEX_0F38E7 */
4542 { "cmpnbexadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4545 /* X86_64_VEX_0F38E8 */
4548 { "cmpsxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4551 /* X86_64_VEX_0F38E9 */
4554 { "cmpnsxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4557 /* X86_64_VEX_0F38EA */
4560 { "cmppxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4563 /* X86_64_VEX_0F38EB */
4566 { "cmpnpxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4569 /* X86_64_VEX_0F38EC */
4572 { "cmplxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4575 /* X86_64_VEX_0F38ED */
4578 { "cmpnlxadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4581 /* X86_64_VEX_0F38EE */
4584 { "cmplexadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4587 /* X86_64_VEX_0F38EF */
4590 { "cmpnlexadd", { Mdq
, Gdq
, VexGdq
}, PREFIX_DATA
},
4593 /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4596 { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64
) },
4600 static const struct dis386 three_byte_table
[][256] = {
4602 /* THREE_BYTE_0F38 */
4605 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4606 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4607 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4608 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4609 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4610 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4611 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4612 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4614 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4615 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4616 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4617 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4623 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4627 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4628 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4630 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4636 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4637 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4638 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4641 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4642 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4643 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4644 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4645 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4646 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4650 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4651 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4652 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
4653 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4659 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4660 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4661 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4662 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4663 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4664 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4666 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4668 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4669 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4670 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4671 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4672 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4673 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4674 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4675 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4677 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4678 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4749 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4750 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4751 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4830 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4831 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4832 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4833 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4834 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4835 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4837 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4848 { PREFIX_TABLE (PREFIX_0F38D8
) },
4851 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4852 { PREFIX_TABLE (PREFIX_0F38DC
) },
4853 { PREFIX_TABLE (PREFIX_0F38DD
) },
4854 { PREFIX_TABLE (PREFIX_0F38DE
) },
4855 { PREFIX_TABLE (PREFIX_0F38DF
) },
4875 { PREFIX_TABLE (PREFIX_0F38F0
) },
4876 { PREFIX_TABLE (PREFIX_0F38F1
) },
4880 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
4881 { PREFIX_TABLE (PREFIX_0F38F6
) },
4884 { MOD_TABLE (MOD_0F38F8
) },
4885 { "movdiri", { Mdq
, Gdq
}, PREFIX_OPCODE
},
4886 { PREFIX_TABLE (PREFIX_0F38FA
) },
4887 { PREFIX_TABLE (PREFIX_0F38FB
) },
4888 { PREFIX_TABLE (PREFIX_0F38FC
) },
4893 /* THREE_BYTE_0F3A */
4905 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4906 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4907 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4908 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4909 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4910 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4911 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4912 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4918 { "pextrb", { Edb
, XM
, Ib
}, PREFIX_DATA
},
4919 { "pextrw", { Edw
, XM
, Ib
}, PREFIX_DATA
},
4920 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4921 { "extractps", { Ed
, XM
, Ib
}, PREFIX_DATA
},
4932 { "pinsrb", { XM
, Edb
, Ib
}, PREFIX_DATA
},
4933 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4934 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4968 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4969 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4970 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4972 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
5004 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
5005 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
5006 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
5007 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
5125 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
5127 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
5128 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
5146 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
5166 { PREFIX_TABLE (PREFIX_0F3A0F
) },
5186 static const struct dis386 xop_table
[][256] = {
5339 { VEX_LEN_TABLE (VEX_LEN_XOP_08_85
) },
5340 { VEX_LEN_TABLE (VEX_LEN_XOP_08_86
) },
5341 { VEX_LEN_TABLE (VEX_LEN_XOP_08_87
) },
5349 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E
) },
5350 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F
) },
5357 { VEX_LEN_TABLE (VEX_LEN_XOP_08_95
) },
5358 { VEX_LEN_TABLE (VEX_LEN_XOP_08_96
) },
5359 { VEX_LEN_TABLE (VEX_LEN_XOP_08_97
) },
5367 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E
) },
5368 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F
) },
5372 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
5373 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3
) },
5376 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6
) },
5394 { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6
) },
5406 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0
) },
5407 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1
) },
5408 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2
) },
5409 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3
) },
5419 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC
) },
5420 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD
) },
5421 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE
) },
5422 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF
) },
5455 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC
) },
5456 { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED
) },
5457 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE
) },
5458 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF
) },
5482 { VEX_LEN_TABLE (VEX_LEN_XOP_09_01
) },
5483 { VEX_LEN_TABLE (VEX_LEN_XOP_09_02
) },
5501 { VEX_LEN_TABLE (VEX_LEN_XOP_09_12
) },
5625 { VEX_W_TABLE (VEX_W_XOP_09_80
) },
5626 { VEX_W_TABLE (VEX_W_XOP_09_81
) },
5627 { VEX_W_TABLE (VEX_W_XOP_09_82
) },
5628 { VEX_W_TABLE (VEX_W_XOP_09_83
) },
5643 { VEX_LEN_TABLE (VEX_LEN_XOP_09_90
) },
5644 { VEX_LEN_TABLE (VEX_LEN_XOP_09_91
) },
5645 { VEX_LEN_TABLE (VEX_LEN_XOP_09_92
) },
5646 { VEX_LEN_TABLE (VEX_LEN_XOP_09_93
) },
5647 { VEX_LEN_TABLE (VEX_LEN_XOP_09_94
) },
5648 { VEX_LEN_TABLE (VEX_LEN_XOP_09_95
) },
5649 { VEX_LEN_TABLE (VEX_LEN_XOP_09_96
) },
5650 { VEX_LEN_TABLE (VEX_LEN_XOP_09_97
) },
5652 { VEX_LEN_TABLE (VEX_LEN_XOP_09_98
) },
5653 { VEX_LEN_TABLE (VEX_LEN_XOP_09_99
) },
5654 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A
) },
5655 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B
) },
5698 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1
) },
5699 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2
) },
5700 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3
) },
5703 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6
) },
5704 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7
) },
5709 { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB
) },
5716 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1
) },
5717 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2
) },
5718 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3
) },
5721 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6
) },
5722 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7
) },
5727 { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB
) },
5734 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1
) },
5735 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2
) },
5736 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3
) },
5790 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5792 { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12
) },
6062 static const struct dis386 vex_table
[][256] = {
6084 { PREFIX_TABLE (PREFIX_0F10
) },
6085 { PREFIX_TABLE (PREFIX_0F11
) },
6086 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
6087 { VEX_LEN_TABLE (VEX_LEN_0F13
) },
6088 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6089 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6090 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
6091 { VEX_LEN_TABLE (VEX_LEN_0F17
) },
6111 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
6112 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
6113 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
6114 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
6115 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
6116 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
6117 { PREFIX_TABLE (PREFIX_0F2E
) },
6118 { PREFIX_TABLE (PREFIX_0F2F
) },
6139 { VEX_LEN_TABLE (VEX_LEN_0F41
) },
6140 { VEX_LEN_TABLE (VEX_LEN_0F42
) },
6142 { VEX_LEN_TABLE (VEX_LEN_0F44
) },
6143 { VEX_LEN_TABLE (VEX_LEN_0F45
) },
6144 { VEX_LEN_TABLE (VEX_LEN_0F46
) },
6145 { VEX_LEN_TABLE (VEX_LEN_0F47
) },
6149 { VEX_LEN_TABLE (VEX_LEN_0F4A
) },
6150 { VEX_LEN_TABLE (VEX_LEN_0F4B
) },
6156 { "vmovmskpX", { Gdq
, Ux
}, PREFIX_OPCODE
},
6157 { PREFIX_TABLE (PREFIX_0F51
) },
6158 { PREFIX_TABLE (PREFIX_0F52
) },
6159 { PREFIX_TABLE (PREFIX_0F53
) },
6160 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6161 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6162 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6163 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
6165 { PREFIX_TABLE (PREFIX_0F58
) },
6166 { PREFIX_TABLE (PREFIX_0F59
) },
6167 { PREFIX_TABLE (PREFIX_0F5A
) },
6168 { PREFIX_TABLE (PREFIX_0F5B
) },
6169 { PREFIX_TABLE (PREFIX_0F5C
) },
6170 { PREFIX_TABLE (PREFIX_0F5D
) },
6171 { PREFIX_TABLE (PREFIX_0F5E
) },
6172 { PREFIX_TABLE (PREFIX_0F5F
) },
6174 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6175 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6176 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6177 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6178 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6179 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6180 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6181 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6183 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6184 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6185 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6186 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6187 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6188 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6189 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
6190 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
6192 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
6193 { REG_TABLE (REG_VEX_0F71
) },
6194 { REG_TABLE (REG_VEX_0F72
) },
6195 { REG_TABLE (REG_VEX_0F73
) },
6196 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6197 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6198 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6199 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
6205 { PREFIX_TABLE (PREFIX_0F7C
) },
6206 { PREFIX_TABLE (PREFIX_0F7D
) },
6207 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
6208 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
6228 { VEX_LEN_TABLE (VEX_LEN_0F90
) },
6229 { VEX_LEN_TABLE (VEX_LEN_0F91
) },
6230 { VEX_LEN_TABLE (VEX_LEN_0F92
) },
6231 { VEX_LEN_TABLE (VEX_LEN_0F93
) },
6237 { VEX_LEN_TABLE (VEX_LEN_0F98
) },
6238 { VEX_LEN_TABLE (VEX_LEN_0F99
) },
6261 { REG_TABLE (REG_VEX_0FAE
) },
6284 { PREFIX_TABLE (PREFIX_0FC2
) },
6286 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
6287 { "vpextrw", { Gd
, Uxmm
, Ib
}, PREFIX_DATA
},
6288 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
6300 { PREFIX_TABLE (PREFIX_0FD0
) },
6301 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6302 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6303 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6304 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6305 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6306 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
6307 { "vpmovmskb", { Gdq
, Ux
}, PREFIX_DATA
},
6309 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6310 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6311 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6312 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6313 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6314 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6315 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6316 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6318 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6319 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6320 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6321 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6322 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6323 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6324 { PREFIX_TABLE (PREFIX_0FE6
) },
6325 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
6327 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6328 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6329 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6330 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6331 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6332 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6333 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6334 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6336 { PREFIX_TABLE (PREFIX_0FF0
) },
6337 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6338 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6339 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6340 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6341 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6342 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6343 { "vmaskmovdqu", { XM
, Uxmm
}, PREFIX_DATA
},
6345 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6346 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6347 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6348 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6349 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6350 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6351 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6357 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6358 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6359 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6360 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6361 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6362 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6363 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6364 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6366 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6367 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6368 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6369 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6370 { VEX_W_TABLE (VEX_W_0F380C
) },
6371 { VEX_W_TABLE (VEX_W_0F380D
) },
6372 { VEX_W_TABLE (VEX_W_0F380E
) },
6373 { VEX_W_TABLE (VEX_W_0F380F
) },
6378 { VEX_W_TABLE (VEX_W_0F3813
) },
6381 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
6382 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
6384 { VEX_W_TABLE (VEX_W_0F3818
) },
6385 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
6386 { VEX_LEN_TABLE (VEX_LEN_0F381A
) },
6388 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
6389 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
6390 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
6393 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6394 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6395 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6396 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6397 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6398 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6402 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6403 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6404 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
6405 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6406 { VEX_W_TABLE (VEX_W_0F382C
) },
6407 { VEX_W_TABLE (VEX_W_0F382D
) },
6408 { VEX_W_TABLE (VEX_W_0F382E
) },
6409 { VEX_W_TABLE (VEX_W_0F382F
) },
6411 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6412 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6413 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6414 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6415 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6416 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6417 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6418 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6420 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6421 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6422 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6423 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6424 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6425 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6426 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6427 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6429 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6430 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6434 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6435 { VEX_W_TABLE (VEX_W_0F3846
) },
6436 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6439 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6441 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6447 { VEX_W_TABLE (VEX_W_0F3850
) },
6448 { VEX_W_TABLE (VEX_W_0F3851
) },
6449 { VEX_W_TABLE (VEX_W_0F3852
) },
6450 { VEX_W_TABLE (VEX_W_0F3853
) },
6456 { VEX_W_TABLE (VEX_W_0F3858
) },
6457 { VEX_W_TABLE (VEX_W_0F3859
) },
6458 { VEX_LEN_TABLE (VEX_LEN_0F385A
) },
6460 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6462 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6478 { X86_64_TABLE (X86_64_VEX_0F386C
) },
6485 { PREFIX_TABLE (PREFIX_VEX_0F3872
) },
6492 { VEX_W_TABLE (VEX_W_0F3878
) },
6493 { VEX_W_TABLE (VEX_W_0F3879
) },
6514 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
6516 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
6519 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, VexGatherD
}, PREFIX_DATA
},
6520 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6521 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, VexGatherD
}, PREFIX_DATA
},
6522 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6525 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6526 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6528 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6529 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6530 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6531 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6532 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6533 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6534 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6535 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6543 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6544 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6546 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6547 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6548 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6549 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6550 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6551 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6552 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6553 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6555 { VEX_W_TABLE (VEX_W_0F38B0
) },
6556 { VEX_W_TABLE (VEX_W_0F38B1
) },
6559 { VEX_W_TABLE (VEX_W_0F38B4
) },
6560 { VEX_W_TABLE (VEX_W_0F38B5
) },
6561 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6562 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6564 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6565 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6566 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6567 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6568 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6569 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6570 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6571 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXdq
}, PREFIX_DATA
},
6585 { PREFIX_TABLE (PREFIX_VEX_0F38CB
) },
6586 { PREFIX_TABLE (PREFIX_VEX_0F38CC
) },
6587 { PREFIX_TABLE (PREFIX_VEX_0F38CD
) },
6589 { VEX_W_TABLE (VEX_W_0F38CF
) },
6593 { VEX_W_TABLE (VEX_W_0F38D2
) },
6594 { VEX_W_TABLE (VEX_W_0F38D3
) },
6602 { VEX_W_TABLE (VEX_W_0F38DA
) },
6603 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6604 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6605 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6606 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6607 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6609 { X86_64_TABLE (X86_64_VEX_0F38E0
) },
6610 { X86_64_TABLE (X86_64_VEX_0F38E1
) },
6611 { X86_64_TABLE (X86_64_VEX_0F38E2
) },
6612 { X86_64_TABLE (X86_64_VEX_0F38E3
) },
6613 { X86_64_TABLE (X86_64_VEX_0F38E4
) },
6614 { X86_64_TABLE (X86_64_VEX_0F38E5
) },
6615 { X86_64_TABLE (X86_64_VEX_0F38E6
) },
6616 { X86_64_TABLE (X86_64_VEX_0F38E7
) },
6618 { X86_64_TABLE (X86_64_VEX_0F38E8
) },
6619 { X86_64_TABLE (X86_64_VEX_0F38E9
) },
6620 { X86_64_TABLE (X86_64_VEX_0F38EA
) },
6621 { X86_64_TABLE (X86_64_VEX_0F38EB
) },
6622 { X86_64_TABLE (X86_64_VEX_0F38EC
) },
6623 { X86_64_TABLE (X86_64_VEX_0F38ED
) },
6624 { X86_64_TABLE (X86_64_VEX_0F38EE
) },
6625 { X86_64_TABLE (X86_64_VEX_0F38EF
) },
6629 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6630 { VEX_LEN_TABLE (VEX_LEN_0F38F3
) },
6632 { VEX_LEN_TABLE (VEX_LEN_0F38F5
) },
6633 { VEX_LEN_TABLE (VEX_LEN_0F38F6
) },
6634 { VEX_LEN_TABLE (VEX_LEN_0F38F7
) },
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6649 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6650 { VEX_W_TABLE (VEX_W_0F3A02
) },
6652 { VEX_W_TABLE (VEX_W_0F3A04
) },
6653 { VEX_W_TABLE (VEX_W_0F3A05
) },
6654 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6657 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6658 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6659 { "vroundss", { XMScalar
, VexScalar
, EXd
, Ib
}, PREFIX_DATA
},
6660 { "vroundsd", { XMScalar
, VexScalar
, EXq
, Ib
}, PREFIX_DATA
},
6661 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6662 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6663 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6664 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6670 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6671 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6673 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6675 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6676 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6680 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6684 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6685 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6686 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6702 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6703 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6704 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6705 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6711 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6712 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6720 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6721 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6722 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6724 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6726 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6729 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6730 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6731 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6732 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6733 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6751 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6752 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6753 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6754 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6756 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6757 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6758 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6759 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6765 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6766 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6767 { "vfmaddss", { XMScalar
, VexScalar
, EXd
, XMVexScalarI4
}, PREFIX_DATA
},
6768 { "vfmaddsd", { XMScalar
, VexScalar
, EXq
, XMVexScalarI4
}, PREFIX_DATA
},
6769 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6770 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6771 { "vfmsubss", { XMScalar
, VexScalar
, EXd
, XMVexScalarI4
}, PREFIX_DATA
},
6772 { "vfmsubsd", { XMScalar
, VexScalar
, EXq
, XMVexScalarI4
}, PREFIX_DATA
},
6783 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6784 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6785 { "vfnmaddss", { XMScalar
, VexScalar
, EXd
, XMVexScalarI4
}, PREFIX_DATA
},
6786 { "vfnmaddsd", { XMScalar
, VexScalar
, EXq
, XMVexScalarI4
}, PREFIX_DATA
},
6787 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6788 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6789 { "vfnmsubss", { XMScalar
, VexScalar
, EXd
, XMVexScalarI4
}, PREFIX_DATA
},
6790 { "vfnmsubsd", { XMScalar
, VexScalar
, EXq
, XMVexScalarI4
}, PREFIX_DATA
},
6879 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6880 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6897 { VEX_W_TABLE (VEX_W_0F3ADE
) },
6898 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6918 { VEX_LEN_TABLE (VEX_LEN_0F3AF0
) },
6938 #include "i386-dis-evex.h"
6940 static const struct dis386 vex_len_table
[][2] = {
6941 /* VEX_LEN_0F12_P_0 */
6943 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
6946 /* VEX_LEN_0F12_P_2 */
6948 { "%XEVmovlpYX", { XM
, Vex
, Mq
}, 0 },
6953 { "%XEVmovlpYX", { Mq
, XM
}, PREFIX_OPCODE
},
6956 /* VEX_LEN_0F16_P_0 */
6958 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
6961 /* VEX_LEN_0F16_P_2 */
6963 { "%XEVmovhpYX", { XM
, Vex
, Mq
}, 0 },
6968 { "%XEVmovhpYX", { Mq
, XM
}, PREFIX_OPCODE
},
6974 { VEX_W_TABLE (VEX_W_0F41_L_1
) },
6980 { VEX_W_TABLE (VEX_W_0F42_L_1
) },
6985 { VEX_W_TABLE (VEX_W_0F44_L_0
) },
6991 { VEX_W_TABLE (VEX_W_0F45_L_1
) },
6997 { VEX_W_TABLE (VEX_W_0F46_L_1
) },
7003 { VEX_W_TABLE (VEX_W_0F47_L_1
) },
7009 { VEX_W_TABLE (VEX_W_0F4A_L_1
) },
7015 { VEX_W_TABLE (VEX_W_0F4B_L_1
) },
7020 { "%XEvmovYK", { XMScalar
, Edq
}, PREFIX_DATA
},
7025 { "vzeroupper", { XX
}, 0 },
7026 { "vzeroall", { XX
}, 0 },
7029 /* VEX_LEN_0F7E_P_1 */
7031 { "%XEvmovqY", { XMScalar
, EXq
}, 0 },
7034 /* VEX_LEN_0F7E_P_2 */
7036 { "%XEvmovK", { Edq
, XMScalar
}, 0 },
7041 { VEX_W_TABLE (VEX_W_0F90_L_0
) },
7046 { VEX_W_TABLE (VEX_W_0F91_L_0
) },
7051 { VEX_W_TABLE (VEX_W_0F92_L_0
) },
7056 { VEX_W_TABLE (VEX_W_0F93_L_0
) },
7061 { VEX_W_TABLE (VEX_W_0F98_L_0
) },
7066 { VEX_W_TABLE (VEX_W_0F99_L_0
) },
7069 /* VEX_LEN_0FAE_R_2 */
7071 { "vldmxcsr", { Md
}, 0 },
7074 /* VEX_LEN_0FAE_R_3 */
7076 { "vstmxcsr", { Md
}, 0 },
7081 { "%XEvpinsrwY", { XM
, Vex
, Edw
, Ib
}, PREFIX_DATA
},
7086 { "%XEvmovqY", { EXqS
, XMScalar
}, PREFIX_DATA
},
7089 /* VEX_LEN_0F3816 */
7092 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
7095 /* VEX_LEN_0F3819 */
7098 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
7101 /* VEX_LEN_0F381A */
7104 { VEX_W_TABLE (VEX_W_0F381A_L_1
) },
7107 /* VEX_LEN_0F3836 */
7110 { VEX_W_TABLE (VEX_W_0F3836
) },
7113 /* VEX_LEN_0F3841 */
7115 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
7118 /* VEX_LEN_0F3849_X86_64 */
7120 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0
) },
7123 /* VEX_LEN_0F384B_X86_64 */
7125 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0
) },
7128 /* VEX_LEN_0F385A */
7131 { VEX_W_TABLE (VEX_W_0F385A_L_0
) },
7134 /* VEX_LEN_0F385C_X86_64 */
7136 { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0
) },
7139 /* VEX_LEN_0F385E_X86_64 */
7141 { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0
) },
7144 /* VEX_LEN_0F386C_X86_64 */
7146 { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0
) },
7149 /* VEX_LEN_0F38CB_P_3_W_0 */
7152 { "vsha512rnds2", { XM
, Vex
, Rxmmq
}, 0 },
7155 /* VEX_LEN_0F38CC_P_3_W_0 */
7158 { "vsha512msg1", { XM
, Rxmmq
}, 0 },
7161 /* VEX_LEN_0F38CD_P_3_W_0 */
7164 { "vsha512msg2", { XM
, Rymm
}, 0 },
7167 /* VEX_LEN_0F38DA_W_0_P_0 */
7169 { "vsm3msg1", { XM
, Vex
, EXxmm
}, 0 },
7172 /* VEX_LEN_0F38DA_W_0_P_2 */
7174 { "vsm3msg2", { XM
, Vex
, EXxmm
}, 0 },
7177 /* VEX_LEN_0F38DB */
7179 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
7182 /* VEX_LEN_0F38F2 */
7184 { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0
) },
7187 /* VEX_LEN_0F38F3 */
7189 { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0
) },
7192 /* VEX_LEN_0F38F5 */
7194 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0
) },
7197 /* VEX_LEN_0F38F6 */
7199 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0
) },
7202 /* VEX_LEN_0F38F7 */
7204 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0
) },
7207 /* VEX_LEN_0F3A00 */
7210 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
7213 /* VEX_LEN_0F3A01 */
7216 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
7219 /* VEX_LEN_0F3A06 */
7222 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
7225 /* VEX_LEN_0F3A14 */
7227 { "%XEvpextrb", { Edb
, XM
, Ib
}, PREFIX_DATA
},
7230 /* VEX_LEN_0F3A15 */
7232 { "%XEvpextrw", { Edw
, XM
, Ib
}, PREFIX_DATA
},
7235 /* VEX_LEN_0F3A16 */
7237 { "%XEvpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
7240 /* VEX_LEN_0F3A17 */
7242 { "%XEvextractps", { Ed
, XM
, Ib
}, PREFIX_DATA
},
7245 /* VEX_LEN_0F3A18 */
7248 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
7251 /* VEX_LEN_0F3A19 */
7254 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
7257 /* VEX_LEN_0F3A20 */
7259 { "%XEvpinsrbY", { XM
, Vex
, Edb
, Ib
}, PREFIX_DATA
},
7262 /* VEX_LEN_0F3A21 */
7264 { "%XEvinsertpsY", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
7267 /* VEX_LEN_0F3A22 */
7269 { "%XEvpinsrYK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
7272 /* VEX_LEN_0F3A30 */
7274 { "kshiftr%BW", { MaskG
, MaskR
, Ib
}, PREFIX_DATA
},
7277 /* VEX_LEN_0F3A31 */
7279 { "kshiftr%DQ", { MaskG
, MaskR
, Ib
}, PREFIX_DATA
},
7282 /* VEX_LEN_0F3A32 */
7284 { "kshiftl%BW", { MaskG
, MaskR
, Ib
}, PREFIX_DATA
},
7287 /* VEX_LEN_0F3A33 */
7289 { "kshiftl%DQ", { MaskG
, MaskR
, Ib
}, PREFIX_DATA
},
7292 /* VEX_LEN_0F3A38 */
7295 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7298 /* VEX_LEN_0F3A39 */
7301 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7304 /* VEX_LEN_0F3A41 */
7306 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7309 /* VEX_LEN_0F3A46 */
7312 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7315 /* VEX_LEN_0F3A60 */
7317 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7320 /* VEX_LEN_0F3A61 */
7322 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7325 /* VEX_LEN_0F3A62 */
7327 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7330 /* VEX_LEN_0F3A63 */
7332 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7335 /* VEX_LEN_0F3ADE_W_0 */
7337 { "vsm3rnds2", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7340 /* VEX_LEN_0F3ADF */
7342 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7345 /* VEX_LEN_0F3AF0 */
7347 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0
) },
7350 /* VEX_LEN_MAP7_F8 */
7352 { VEX_W_TABLE (VEX_W_MAP7_F8_L_0
) },
7355 /* VEX_LEN_XOP_08_85 */
7357 { VEX_W_TABLE (VEX_W_XOP_08_85_L_0
) },
7360 /* VEX_LEN_XOP_08_86 */
7362 { VEX_W_TABLE (VEX_W_XOP_08_86_L_0
) },
7365 /* VEX_LEN_XOP_08_87 */
7367 { VEX_W_TABLE (VEX_W_XOP_08_87_L_0
) },
7370 /* VEX_LEN_XOP_08_8E */
7372 { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0
) },
7375 /* VEX_LEN_XOP_08_8F */
7377 { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0
) },
7380 /* VEX_LEN_XOP_08_95 */
7382 { VEX_W_TABLE (VEX_W_XOP_08_95_L_0
) },
7385 /* VEX_LEN_XOP_08_96 */
7387 { VEX_W_TABLE (VEX_W_XOP_08_96_L_0
) },
7390 /* VEX_LEN_XOP_08_97 */
7392 { VEX_W_TABLE (VEX_W_XOP_08_97_L_0
) },
7395 /* VEX_LEN_XOP_08_9E */
7397 { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0
) },
7400 /* VEX_LEN_XOP_08_9F */
7402 { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0
) },
7405 /* VEX_LEN_XOP_08_A3 */
7407 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7410 /* VEX_LEN_XOP_08_A6 */
7412 { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0
) },
7415 /* VEX_LEN_XOP_08_B6 */
7417 { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0
) },
7420 /* VEX_LEN_XOP_08_C0 */
7422 { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0
) },
7425 /* VEX_LEN_XOP_08_C1 */
7427 { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0
) },
7430 /* VEX_LEN_XOP_08_C2 */
7432 { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0
) },
7435 /* VEX_LEN_XOP_08_C3 */
7437 { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0
) },
7440 /* VEX_LEN_XOP_08_CC */
7442 { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0
) },
7445 /* VEX_LEN_XOP_08_CD */
7447 { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0
) },
7450 /* VEX_LEN_XOP_08_CE */
7452 { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0
) },
7455 /* VEX_LEN_XOP_08_CF */
7457 { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0
) },
7460 /* VEX_LEN_XOP_08_EC */
7462 { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0
) },
7465 /* VEX_LEN_XOP_08_ED */
7467 { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0
) },
7470 /* VEX_LEN_XOP_08_EE */
7472 { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0
) },
7475 /* VEX_LEN_XOP_08_EF */
7477 { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0
) },
7480 /* VEX_LEN_XOP_09_01 */
7482 { REG_TABLE (REG_XOP_09_01_L_0
) },
7485 /* VEX_LEN_XOP_09_02 */
7487 { REG_TABLE (REG_XOP_09_02_L_0
) },
7490 /* VEX_LEN_XOP_09_12 */
7492 { REG_TABLE (REG_XOP_09_12_L_0
) },
7495 /* VEX_LEN_XOP_09_82_W_0 */
7497 { "vfrczss", { XM
, EXd
}, 0 },
7500 /* VEX_LEN_XOP_09_83_W_0 */
7502 { "vfrczsd", { XM
, EXq
}, 0 },
7505 /* VEX_LEN_XOP_09_90 */
7507 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7510 /* VEX_LEN_XOP_09_91 */
7512 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7515 /* VEX_LEN_XOP_09_92 */
7517 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7520 /* VEX_LEN_XOP_09_93 */
7522 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7525 /* VEX_LEN_XOP_09_94 */
7527 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7530 /* VEX_LEN_XOP_09_95 */
7532 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7535 /* VEX_LEN_XOP_09_96 */
7537 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7540 /* VEX_LEN_XOP_09_97 */
7542 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7545 /* VEX_LEN_XOP_09_98 */
7547 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7550 /* VEX_LEN_XOP_09_99 */
7552 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7555 /* VEX_LEN_XOP_09_9A */
7557 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7560 /* VEX_LEN_XOP_09_9B */
7562 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7565 /* VEX_LEN_XOP_09_C1 */
7567 { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0
) },
7570 /* VEX_LEN_XOP_09_C2 */
7572 { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0
) },
7575 /* VEX_LEN_XOP_09_C3 */
7577 { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0
) },
7580 /* VEX_LEN_XOP_09_C6 */
7582 { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0
) },
7585 /* VEX_LEN_XOP_09_C7 */
7587 { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0
) },
7590 /* VEX_LEN_XOP_09_CB */
7592 { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0
) },
7595 /* VEX_LEN_XOP_09_D1 */
7597 { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0
) },
7600 /* VEX_LEN_XOP_09_D2 */
7602 { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0
) },
7605 /* VEX_LEN_XOP_09_D3 */
7607 { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0
) },
7610 /* VEX_LEN_XOP_09_D6 */
7612 { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0
) },
7615 /* VEX_LEN_XOP_09_D7 */
7617 { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0
) },
7620 /* VEX_LEN_XOP_09_DB */
7622 { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0
) },
7625 /* VEX_LEN_XOP_09_E1 */
7627 { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0
) },
7630 /* VEX_LEN_XOP_09_E2 */
7632 { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0
) },
7635 /* VEX_LEN_XOP_09_E3 */
7637 { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0
) },
7640 /* VEX_LEN_XOP_0A_12 */
7642 { REG_TABLE (REG_XOP_0A_12_L_0
) },
7646 #include "i386-dis-evex-len.h"
7648 static const struct dis386 vex_w_table
[][2] = {
7650 /* VEX_W_0F41_L_1_M_1 */
7651 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0
) },
7652 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1
) },
7655 /* VEX_W_0F42_L_1_M_1 */
7656 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0
) },
7657 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1
) },
7660 /* VEX_W_0F44_L_0_M_1 */
7661 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0
) },
7662 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1
) },
7665 /* VEX_W_0F45_L_1_M_1 */
7666 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0
) },
7667 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1
) },
7670 /* VEX_W_0F46_L_1_M_1 */
7671 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0
) },
7672 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1
) },
7675 /* VEX_W_0F47_L_1_M_1 */
7676 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0
) },
7677 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1
) },
7680 /* VEX_W_0F4A_L_1_M_1 */
7681 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0
) },
7682 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1
) },
7685 /* VEX_W_0F4B_L_1_M_1 */
7686 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0
) },
7687 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1
) },
7690 /* VEX_W_0F90_L_0 */
7691 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0
) },
7692 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1
) },
7695 /* VEX_W_0F91_L_0_M_0 */
7696 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0
) },
7697 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1
) },
7700 /* VEX_W_0F92_L_0_M_1 */
7701 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0
) },
7702 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1
) },
7705 /* VEX_W_0F93_L_0_M_1 */
7706 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0
) },
7707 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1
) },
7710 /* VEX_W_0F98_L_0_M_1 */
7711 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0
) },
7712 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1
) },
7715 /* VEX_W_0F99_L_0_M_1 */
7716 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0
) },
7717 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1
) },
7721 { "%XEvpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7725 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7729 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7733 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7737 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7740 /* VEX_W_0F3816_L_1 */
7741 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7745 { "%XEvbroadcastss", { XM
, EXd
}, PREFIX_DATA
},
7748 /* VEX_W_0F3819_L_1 */
7749 { "vbroadcastsd", { XM
, EXq
}, PREFIX_DATA
},
7752 /* VEX_W_0F381A_L_1 */
7753 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7757 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7761 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7765 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7769 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7773 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7777 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7780 /* VEX_W_0F3849_X86_64_L_0 */
7781 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0
) },
7784 /* VEX_W_0F384B_X86_64_L_0 */
7785 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0
) },
7789 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0
) },
7793 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0
) },
7797 { "%XVvpdpwssd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7801 { "%XVvpdpwssds", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7805 { "%XEvpbroadcastd", { XM
, EXd
}, PREFIX_DATA
},
7809 { "vpbroadcastq", { XM
, EXq
}, PREFIX_DATA
},
7812 /* VEX_W_0F385A_L_0 */
7813 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7816 /* VEX_W_0F385C_X86_64_L_0 */
7817 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0
) },
7820 /* VEX_W_0F385E_X86_64_L_0 */
7821 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0
) },
7824 /* VEX_W_0F386C_X86_64_L_0 */
7825 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0
) },
7828 /* VEX_W_0F3872_P_1 */
7829 { "%XVvcvtneps2bf16%XY", { XMM
, EXx
}, 0 },
7833 { "%XEvpbroadcastb", { XM
, EXb
}, PREFIX_DATA
},
7837 { "%XEvpbroadcastw", { XM
, EXw
}, PREFIX_DATA
},
7841 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0
) },
7845 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0
) },
7850 { "%XVvpmadd52luq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7855 { "%XVvpmadd52huq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7858 /* VEX_W_0F38CB_P_3 */
7859 { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0
) },
7862 /* VEX_W_0F38CC_P_3 */
7863 { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0
) },
7866 /* VEX_W_0F38CD_P_3 */
7867 { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0
) },
7871 { "%XEvgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7875 { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0
) },
7879 { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0
) },
7883 { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0
) },
7886 /* VEX_W_0F3A00_L_1 */
7888 { "%XEvpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7891 /* VEX_W_0F3A01_L_1 */
7893 { "%XEvpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7897 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7901 { "%XEvpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7905 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7908 /* VEX_W_0F3A06_L_1 */
7909 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7912 /* VEX_W_0F3A18_L_1 */
7913 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7916 /* VEX_W_0F3A19_L_1 */
7917 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7921 { "%XEvcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7924 /* VEX_W_0F3A38_L_1 */
7925 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7928 /* VEX_W_0F3A39_L_1 */
7929 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7932 /* VEX_W_0F3A46_L_1 */
7933 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7937 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7941 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7945 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7950 { "%XEvgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7955 { "%XEvgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7959 { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0
) },
7962 /* VEX_W_MAP7_F8_L_0 */
7963 { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0
) },
7965 /* VEX_W_XOP_08_85_L_0 */
7967 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7969 /* VEX_W_XOP_08_86_L_0 */
7971 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7973 /* VEX_W_XOP_08_87_L_0 */
7975 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7977 /* VEX_W_XOP_08_8E_L_0 */
7979 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7981 /* VEX_W_XOP_08_8F_L_0 */
7983 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7985 /* VEX_W_XOP_08_95_L_0 */
7987 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7989 /* VEX_W_XOP_08_96_L_0 */
7991 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7993 /* VEX_W_XOP_08_97_L_0 */
7995 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7997 /* VEX_W_XOP_08_9E_L_0 */
7999 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
8001 /* VEX_W_XOP_08_9F_L_0 */
8003 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
8005 /* VEX_W_XOP_08_A6_L_0 */
8007 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
8009 /* VEX_W_XOP_08_B6_L_0 */
8011 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
8013 /* VEX_W_XOP_08_C0_L_0 */
8015 { "vprotb", { XM
, EXx
, Ib
}, 0 },
8017 /* VEX_W_XOP_08_C1_L_0 */
8019 { "vprotw", { XM
, EXx
, Ib
}, 0 },
8021 /* VEX_W_XOP_08_C2_L_0 */
8023 { "vprotd", { XM
, EXx
, Ib
}, 0 },
8025 /* VEX_W_XOP_08_C3_L_0 */
8027 { "vprotq", { XM
, EXx
, Ib
}, 0 },
8029 /* VEX_W_XOP_08_CC_L_0 */
8031 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8033 /* VEX_W_XOP_08_CD_L_0 */
8035 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8037 /* VEX_W_XOP_08_CE_L_0 */
8039 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8041 /* VEX_W_XOP_08_CF_L_0 */
8043 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8045 /* VEX_W_XOP_08_EC_L_0 */
8047 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8049 /* VEX_W_XOP_08_ED_L_0 */
8051 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8053 /* VEX_W_XOP_08_EE_L_0 */
8055 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8057 /* VEX_W_XOP_08_EF_L_0 */
8059 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8061 /* VEX_W_XOP_09_80 */
8063 { "vfrczps", { XM
, EXx
}, 0 },
8065 /* VEX_W_XOP_09_81 */
8067 { "vfrczpd", { XM
, EXx
}, 0 },
8069 /* VEX_W_XOP_09_82 */
8071 { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0
) },
8073 /* VEX_W_XOP_09_83 */
8075 { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0
) },
8077 /* VEX_W_XOP_09_C1_L_0 */
8079 { "vphaddbw", { XM
, EXxmm
}, 0 },
8081 /* VEX_W_XOP_09_C2_L_0 */
8083 { "vphaddbd", { XM
, EXxmm
}, 0 },
8085 /* VEX_W_XOP_09_C3_L_0 */
8087 { "vphaddbq", { XM
, EXxmm
}, 0 },
8089 /* VEX_W_XOP_09_C6_L_0 */
8091 { "vphaddwd", { XM
, EXxmm
}, 0 },
8093 /* VEX_W_XOP_09_C7_L_0 */
8095 { "vphaddwq", { XM
, EXxmm
}, 0 },
8097 /* VEX_W_XOP_09_CB_L_0 */
8099 { "vphadddq", { XM
, EXxmm
}, 0 },
8101 /* VEX_W_XOP_09_D1_L_0 */
8103 { "vphaddubw", { XM
, EXxmm
}, 0 },
8105 /* VEX_W_XOP_09_D2_L_0 */
8107 { "vphaddubd", { XM
, EXxmm
}, 0 },
8109 /* VEX_W_XOP_09_D3_L_0 */
8111 { "vphaddubq", { XM
, EXxmm
}, 0 },
8113 /* VEX_W_XOP_09_D6_L_0 */
8115 { "vphadduwd", { XM
, EXxmm
}, 0 },
8117 /* VEX_W_XOP_09_D7_L_0 */
8119 { "vphadduwq", { XM
, EXxmm
}, 0 },
8121 /* VEX_W_XOP_09_DB_L_0 */
8123 { "vphaddudq", { XM
, EXxmm
}, 0 },
8125 /* VEX_W_XOP_09_E1_L_0 */
8127 { "vphsubbw", { XM
, EXxmm
}, 0 },
8129 /* VEX_W_XOP_09_E2_L_0 */
8131 { "vphsubwd", { XM
, EXxmm
}, 0 },
8133 /* VEX_W_XOP_09_E3_L_0 */
8135 { "vphsubdq", { XM
, EXxmm
}, 0 },
8138 #include "i386-dis-evex-w.h"
8141 static const struct dis386 mod_table
[][2] = {
8144 { "bound{S|}", { Gv
, Ma
}, 0 },
8149 { "lesS", { Gv
, Mp
}, 0 },
8150 { VEX_C4_TABLE () },
8154 { "ldsS", { Gv
, Mp
}, 0 },
8155 { VEX_C5_TABLE () },
8158 /* MOD_0F01_REG_0 */
8159 { X86_64_TABLE (X86_64_0F01_REG_0
) },
8160 { RM_TABLE (RM_0F01_REG_0
) },
8163 /* MOD_0F01_REG_1 */
8164 { X86_64_TABLE (X86_64_0F01_REG_1
) },
8165 { RM_TABLE (RM_0F01_REG_1
) },
8168 /* MOD_0F01_REG_2 */
8169 { X86_64_TABLE (X86_64_0F01_REG_2
) },
8170 { RM_TABLE (RM_0F01_REG_2
) },
8173 /* MOD_0F01_REG_3 */
8174 { X86_64_TABLE (X86_64_0F01_REG_3
) },
8175 { RM_TABLE (RM_0F01_REG_3
) },
8178 /* MOD_0F01_REG_5 */
8179 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
8180 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
8183 /* MOD_0F01_REG_7 */
8184 { "invlpg", { Mb
}, 0 },
8185 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
8188 /* MOD_0F12_PREFIX_0 */
8189 { "%XEVmovlpYX", { XM
, Vex
, EXq
}, 0 },
8190 { "%XEVmovhlpY%XS", { XM
, Vex
, EXq
}, 0 },
8193 /* MOD_0F16_PREFIX_0 */
8194 { "%XEVmovhpYX", { XM
, Vex
, EXq
}, 0 },
8195 { "%XEVmovlhpY%XS", { XM
, Vex
, EXq
}, 0 },
8198 /* MOD_0F18_REG_0 */
8199 { "prefetchnta", { Mb
}, 0 },
8200 { "nopQ", { Ev
}, 0 },
8203 /* MOD_0F18_REG_1 */
8204 { "prefetcht0", { Mb
}, 0 },
8205 { "nopQ", { Ev
}, 0 },
8208 /* MOD_0F18_REG_2 */
8209 { "prefetcht1", { Mb
}, 0 },
8210 { "nopQ", { Ev
}, 0 },
8213 /* MOD_0F18_REG_3 */
8214 { "prefetcht2", { Mb
}, 0 },
8215 { "nopQ", { Ev
}, 0 },
8218 /* MOD_0F18_REG_6 */
8219 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0
) },
8220 { "nopQ", { Ev
}, 0 },
8223 /* MOD_0F18_REG_7 */
8224 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0
) },
8225 { "nopQ", { Ev
}, 0 },
8228 /* MOD_0F1A_PREFIX_0 */
8229 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
8230 { "nopQ", { Ev
}, 0 },
8233 /* MOD_0F1B_PREFIX_0 */
8234 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
8235 { "nopQ", { Ev
}, 0 },
8238 /* MOD_0F1B_PREFIX_1 */
8239 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
8240 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8243 /* MOD_0F1C_PREFIX_0 */
8244 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
8245 { "nopQ", { Ev
}, 0 },
8248 /* MOD_0F1E_PREFIX_1 */
8249 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8250 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
8253 /* MOD_0FAE_REG_0 */
8254 { "fxsave", { FXSAVE
}, 0 },
8255 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8258 /* MOD_0FAE_REG_1 */
8259 { "fxrstor", { FXSAVE
}, 0 },
8260 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8263 /* MOD_0FAE_REG_2 */
8264 { "ldmxcsr", { Md
}, 0 },
8265 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8268 /* MOD_0FAE_REG_3 */
8269 { "stmxcsr", { Md
}, 0 },
8270 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8273 /* MOD_0FAE_REG_4 */
8274 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8275 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8278 /* MOD_0FAE_REG_5 */
8279 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
| PREFIX_REX2_ILLEGAL
},
8280 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8283 /* MOD_0FAE_REG_6 */
8284 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8285 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8288 /* MOD_0FAE_REG_7 */
8289 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8290 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8293 /* MOD_0FC7_REG_6 */
8294 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8295 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8298 /* MOD_0FC7_REG_7 */
8299 { "vmptrst", { Mq
}, 0 },
8300 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8303 /* MOD_0F38DC_PREFIX_1 */
8304 { "aesenc128kl", { XM
, M
}, 0 },
8305 { "loadiwkey", { XM
, EXx
}, 0 },
8309 { PREFIX_TABLE (PREFIX_0F38F8_M_0
) },
8310 { X86_64_TABLE (X86_64_0F38F8_M_1
) },
8313 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8314 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0
) },
8315 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1
) },
8318 #include "i386-dis-evex-mod.h"
8321 static const struct dis386 rm_table
[][8] = {
8324 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8328 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8332 { "enclv", { Skip_MODRM
}, 0 },
8333 { "vmcall", { Skip_MODRM
}, 0 },
8334 { "vmlaunch", { Skip_MODRM
}, 0 },
8335 { "vmresume", { Skip_MODRM
}, 0 },
8336 { "vmxoff", { Skip_MODRM
}, 0 },
8337 { "pconfig", { Skip_MODRM
}, 0 },
8338 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6
) },
8339 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7
) },
8343 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8344 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8345 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2
) },
8346 { "stac", { Skip_MODRM
}, 0 },
8347 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4
) },
8348 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5
) },
8349 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6
) },
8350 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7
) },
8354 { "xgetbv", { Skip_MODRM
}, 0 },
8355 { "xsetbv", { Skip_MODRM
}, 0 },
8358 { "vmfunc", { Skip_MODRM
}, 0 },
8359 { "xend", { Skip_MODRM
}, 0 },
8360 { "xtest", { Skip_MODRM
}, 0 },
8361 { "enclu", { Skip_MODRM
}, 0 },
8365 { "vmrun", { Skip_MODRM
}, 0 },
8366 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
8367 { "vmload", { Skip_MODRM
}, 0 },
8368 { "vmsave", { Skip_MODRM
}, 0 },
8369 { "stgi", { Skip_MODRM
}, 0 },
8370 { "clgi", { Skip_MODRM
}, 0 },
8371 { "skinit", { Skip_MODRM
}, 0 },
8372 { "invlpga", { Skip_MODRM
}, 0 },
8375 /* RM_0F01_REG_5_MOD_3 */
8376 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
8377 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
8378 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
8380 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4
) },
8381 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5
) },
8382 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6
) },
8383 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7
) },
8386 /* RM_0F01_REG_7_MOD_3 */
8387 { "swapgs", { Skip_MODRM
}, 0 },
8388 { "rdtscp", { Skip_MODRM
}, 0 },
8389 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
8390 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
8391 { "clzero", { Skip_MODRM
}, 0 },
8392 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5
) },
8393 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6
) },
8394 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7
) },
8397 /* RM_0F1E_P_1_MOD_3_REG_7 */
8398 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8399 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8400 { "endbr64", { Skip_MODRM
}, 0 },
8401 { "endbr32", { Skip_MODRM
}, 0 },
8402 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8403 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8404 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8405 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8408 /* RM_0FAE_REG_6_MOD_3 */
8409 { "mfence", { Skip_MODRM
}, 0 },
8412 /* RM_0FAE_REG_7_MOD_3 */
8413 { "sfence", { Skip_MODRM
}, 0 },
8416 /* RM_0F3A0F_P_1_R_0 */
8417 { "hreset", { Skip_MODRM
, Ib
}, 0 },
8420 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8421 { "tilerelease", { Skip_MODRM
}, 0 },
8424 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8425 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
8429 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8431 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8432 in conflict with actual prefix opcodes. */
8433 #define REP_PREFIX 0x01
8434 #define XACQUIRE_PREFIX 0x02
8435 #define XRELEASE_PREFIX 0x03
8436 #define BND_PREFIX 0x04
8437 #define NOTRACK_PREFIX 0x05
8444 ckprefix (instr_info
*ins
)
8451 /* The maximum instruction length is 15bytes. */
8452 while (length
< MAX_CODE_LENGTH
- 1)
8454 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
8455 return ckp_fetch_error
;
8457 switch (*ins
->codep
)
8459 /* REX prefixes family. */
8476 if (ins
->address_mode
== mode_64bit
)
8477 newrex
= *ins
->codep
;
8480 ins
->last_rex_prefix
= i
;
8482 /* REX2 must be the last prefix. */
8484 if (ins
->address_mode
== mode_64bit
)
8486 if (ins
->last_rex_prefix
>= 0)
8490 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
8491 return ckp_fetch_error
;
8492 ins
->rex2_payload
= *ins
->codep
;
8493 ins
->rex2
= ins
->rex2_payload
>> 4;
8494 ins
->rex
= (ins
->rex2_payload
& 0xf) | REX_OPCODE
;
8496 ins
->last_rex2_prefix
= i
;
8497 ins
->all_prefixes
[i
] = REX2_OPCODE
;
8501 ins
->prefixes
|= PREFIX_REPZ
;
8502 ins
->last_repz_prefix
= i
;
8505 ins
->prefixes
|= PREFIX_REPNZ
;
8506 ins
->last_repnz_prefix
= i
;
8509 ins
->prefixes
|= PREFIX_LOCK
;
8510 ins
->last_lock_prefix
= i
;
8513 ins
->prefixes
|= PREFIX_CS
;
8514 ins
->last_seg_prefix
= i
;
8515 if (ins
->address_mode
!= mode_64bit
)
8516 ins
->active_seg_prefix
= PREFIX_CS
;
8519 ins
->prefixes
|= PREFIX_SS
;
8520 ins
->last_seg_prefix
= i
;
8521 if (ins
->address_mode
!= mode_64bit
)
8522 ins
->active_seg_prefix
= PREFIX_SS
;
8525 ins
->prefixes
|= PREFIX_DS
;
8526 ins
->last_seg_prefix
= i
;
8527 if (ins
->address_mode
!= mode_64bit
)
8528 ins
->active_seg_prefix
= PREFIX_DS
;
8531 ins
->prefixes
|= PREFIX_ES
;
8532 ins
->last_seg_prefix
= i
;
8533 if (ins
->address_mode
!= mode_64bit
)
8534 ins
->active_seg_prefix
= PREFIX_ES
;
8537 ins
->prefixes
|= PREFIX_FS
;
8538 ins
->last_seg_prefix
= i
;
8539 ins
->active_seg_prefix
= PREFIX_FS
;
8542 ins
->prefixes
|= PREFIX_GS
;
8543 ins
->last_seg_prefix
= i
;
8544 ins
->active_seg_prefix
= PREFIX_GS
;
8547 ins
->prefixes
|= PREFIX_DATA
;
8548 ins
->last_data_prefix
= i
;
8551 ins
->prefixes
|= PREFIX_ADDR
;
8552 ins
->last_addr_prefix
= i
;
8555 /* fwait is really an instruction. If there are prefixes
8556 before the fwait, they belong to the fwait, *not* to the
8557 following instruction. */
8558 ins
->fwait_prefix
= i
;
8559 if (ins
->prefixes
|| ins
->rex
)
8561 ins
->prefixes
|= PREFIX_FWAIT
;
8563 /* This ensures that the previous REX prefixes are noticed
8564 as unused prefixes, as in the return case below. */
8565 return ins
->rex
? ckp_bogus
: ckp_okay
;
8567 ins
->prefixes
= PREFIX_FWAIT
;
8572 /* Rex is ignored when followed by another prefix. */
8575 if (*ins
->codep
!= FWAIT_OPCODE
)
8576 ins
->all_prefixes
[i
++] = *ins
->codep
;
8584 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8588 prefix_name (enum address_mode mode
, uint8_t pref
, int sizeflag
)
8590 static const char *rexes
[16] =
8595 "rex.XB", /* 0x43 */
8597 "rex.RB", /* 0x45 */
8598 "rex.RX", /* 0x46 */
8599 "rex.RXB", /* 0x47 */
8601 "rex.WB", /* 0x49 */
8602 "rex.WX", /* 0x4a */
8603 "rex.WXB", /* 0x4b */
8604 "rex.WR", /* 0x4c */
8605 "rex.WRB", /* 0x4d */
8606 "rex.WRX", /* 0x4e */
8607 "rex.WRXB", /* 0x4f */
8612 /* REX prefixes family. */
8629 return rexes
[pref
- 0x40];
8649 return (sizeflag
& DFLAG
) ? "data16" : "data32";
8651 if (mode
== mode_64bit
)
8652 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
8654 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
8659 case XACQUIRE_PREFIX
:
8661 case XRELEASE_PREFIX
:
8665 case NOTRACK_PREFIX
:
8675 print_i386_disassembler_options (FILE *stream
)
8677 fprintf (stream
, _("\n\
8678 The following i386/x86-64 specific disassembler options are supported for use\n\
8679 with the -M switch (multiple options should be separated by commas):\n"));
8681 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
8682 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
8683 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
8684 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
8685 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
8686 fprintf (stream
, _(" att-mnemonic (AT&T syntax only)\n"
8687 " Display instruction with AT&T mnemonic\n"));
8688 fprintf (stream
, _(" intel-mnemonic (AT&T syntax only)\n"
8689 " Display instruction with Intel mnemonic\n"));
8690 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
8691 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
8692 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
8693 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
8694 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
8695 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8696 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
8697 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
8701 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
8703 /* Fetch error indicator. */
8704 static const struct dis386 err_opcode
= { NULL
, { XX
}, 0 };
8706 static const struct dis386 map7_f8_opcode
= { VEX_LEN_TABLE (VEX_LEN_MAP7_F8
) };
8708 /* Get a pointer to struct dis386 with a valid name. */
8710 static const struct dis386
*
8711 get_valid_dis386 (const struct dis386
*dp
, instr_info
*ins
)
8713 int vindex
, vex_table_index
;
8715 if (dp
->name
!= NULL
)
8718 switch (dp
->op
[0].bytemode
)
8721 dp
= ®_table
[dp
->op
[1].bytemode
][ins
->modrm
.reg
];
8725 vindex
= ins
->modrm
.mod
== 0x3 ? 1 : 0;
8726 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
8730 dp
= &rm_table
[dp
->op
[1].bytemode
][ins
->modrm
.rm
];
8733 case USE_PREFIX_TABLE
:
8737 /* The prefix in VEX is implicit. */
8738 switch (ins
->vex
.prefix
)
8743 case REPE_PREFIX_OPCODE
:
8746 case DATA_PREFIX_OPCODE
:
8749 case REPNE_PREFIX_OPCODE
:
8759 int last_prefix
= -1;
8762 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8763 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8765 if ((ins
->prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
8767 if (ins
->last_repz_prefix
> ins
->last_repnz_prefix
)
8770 prefix
= PREFIX_REPZ
;
8771 last_prefix
= ins
->last_repz_prefix
;
8776 prefix
= PREFIX_REPNZ
;
8777 last_prefix
= ins
->last_repnz_prefix
;
8780 /* Check if prefix should be ignored. */
8781 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
8782 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
8784 && !prefix_table
[dp
->op
[1].bytemode
][vindex
].name
)
8788 if (vindex
== 0 && (ins
->prefixes
& PREFIX_DATA
) != 0)
8791 prefix
= PREFIX_DATA
;
8792 last_prefix
= ins
->last_data_prefix
;
8797 ins
->used_prefixes
|= prefix
;
8798 ins
->all_prefixes
[last_prefix
] = 0;
8801 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
8804 case USE_X86_64_EVEX_FROM_VEX_TABLE
:
8805 case USE_X86_64_EVEX_PFX_TABLE
:
8806 case USE_X86_64_EVEX_W_TABLE
:
8807 case USE_X86_64_EVEX_MEM_W_TABLE
:
8808 ins
->evex_type
= evex_from_vex
;
8809 /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
8810 EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0. */
8811 if (ins
->address_mode
!= mode_64bit
8812 || (ins
->vex
.mask_register_specifier
& 0x3) != 0
8814 || ins
->vex
.zeroing
!= 0
8818 if (dp
->op
[0].bytemode
== USE_X86_64_EVEX_PFX_TABLE
)
8819 goto use_prefix_table
;
8820 if (dp
->op
[0].bytemode
== USE_X86_64_EVEX_W_TABLE
)
8821 goto use_vex_w_table
;
8822 if (dp
->op
[0].bytemode
== USE_X86_64_EVEX_MEM_W_TABLE
)
8824 if (ins
->modrm
.mod
== 3)
8826 goto use_vex_w_table
;
8830 case USE_X86_64_TABLE
:
8831 vindex
= ins
->address_mode
== mode_64bit
? 1 : 0;
8832 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
8835 case USE_3BYTE_TABLE
:
8836 if (ins
->last_rex2_prefix
>= 0)
8838 if (!fetch_code (ins
->info
, ins
->codep
+ 2))
8840 vindex
= *ins
->codep
++;
8841 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
8842 ins
->end_codep
= ins
->codep
;
8843 if (!fetch_modrm (ins
))
8847 case USE_VEX_LEN_TABLE
:
8851 switch (ins
->vex
.length
)
8857 /* This allows re-using in particular table entries where only
8858 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
8871 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
8874 case USE_EVEX_LEN_TABLE
:
8878 switch (ins
->vex
.length
)
8894 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
8897 case USE_XOP_8F_TABLE
:
8898 if (!fetch_code (ins
->info
, ins
->codep
+ 3))
8900 ins
->rex
= ~(*ins
->codep
>> 5) & 0x7;
8902 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
8903 switch ((*ins
->codep
& 0x1f))
8909 vex_table_index
= XOP_08
;
8912 vex_table_index
= XOP_09
;
8915 vex_table_index
= XOP_0A
;
8919 ins
->vex
.w
= *ins
->codep
& 0x80;
8920 if (ins
->vex
.w
&& ins
->address_mode
== mode_64bit
)
8923 ins
->vex
.register_specifier
= (~(*ins
->codep
>> 3)) & 0xf;
8924 if (ins
->address_mode
!= mode_64bit
)
8926 /* In 16/32-bit mode REX_B is silently ignored. */
8930 ins
->vex
.length
= (*ins
->codep
& 0x4) ? 256 : 128;
8931 switch ((*ins
->codep
& 0x3))
8936 ins
->vex
.prefix
= DATA_PREFIX_OPCODE
;
8939 ins
->vex
.prefix
= REPE_PREFIX_OPCODE
;
8942 ins
->vex
.prefix
= REPNE_PREFIX_OPCODE
;
8947 vindex
= *ins
->codep
++;
8948 dp
= &xop_table
[vex_table_index
][vindex
];
8950 ins
->end_codep
= ins
->codep
;
8951 if (!fetch_modrm (ins
))
8954 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8955 having to decode the bits for every otherwise valid encoding. */
8956 if (ins
->vex
.prefix
)
8960 case USE_VEX_C4_TABLE
:
8962 if (!fetch_code (ins
->info
, ins
->codep
+ 3))
8964 ins
->rex
= ~(*ins
->codep
>> 5) & 0x7;
8965 switch ((*ins
->codep
& 0x1f))
8971 vex_table_index
= VEX_0F
;
8974 vex_table_index
= VEX_0F38
;
8977 vex_table_index
= VEX_0F3A
;
8980 vex_table_index
= VEX_MAP7
;
8984 ins
->vex
.w
= *ins
->codep
& 0x80;
8985 if (ins
->address_mode
== mode_64bit
)
8992 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
8993 is ignored, other REX bits are 0 and the highest bit in
8994 VEX.vvvv is also ignored (but we mustn't clear it here). */
8997 ins
->vex
.register_specifier
= (~(*ins
->codep
>> 3)) & 0xf;
8998 ins
->vex
.length
= (*ins
->codep
& 0x4) ? 256 : 128;
8999 switch ((*ins
->codep
& 0x3))
9004 ins
->vex
.prefix
= DATA_PREFIX_OPCODE
;
9007 ins
->vex
.prefix
= REPE_PREFIX_OPCODE
;
9010 ins
->vex
.prefix
= REPNE_PREFIX_OPCODE
;
9015 vindex
= *ins
->codep
++;
9016 if (vex_table_index
!= VEX_MAP7
)
9017 dp
= &vex_table
[vex_table_index
][vindex
];
9018 else if (vindex
== 0xf8)
9019 dp
= &map7_f8_opcode
;
9022 ins
->end_codep
= ins
->codep
;
9023 /* There is no MODRM byte for VEX0F 77. */
9024 if ((vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9025 && !fetch_modrm (ins
))
9029 case USE_VEX_C5_TABLE
:
9031 if (!fetch_code (ins
->info
, ins
->codep
+ 2))
9033 ins
->rex
= (*ins
->codep
& 0x80) ? 0 : REX_R
;
9035 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9037 ins
->vex
.register_specifier
= (~(*ins
->codep
>> 3)) & 0xf;
9038 ins
->vex
.length
= (*ins
->codep
& 0x4) ? 256 : 128;
9039 switch ((*ins
->codep
& 0x3))
9044 ins
->vex
.prefix
= DATA_PREFIX_OPCODE
;
9047 ins
->vex
.prefix
= REPE_PREFIX_OPCODE
;
9050 ins
->vex
.prefix
= REPNE_PREFIX_OPCODE
;
9055 vindex
= *ins
->codep
++;
9056 dp
= &vex_table
[VEX_0F
][vindex
];
9057 ins
->end_codep
= ins
->codep
;
9058 /* There is no MODRM byte for VEX 77. */
9059 if (vindex
!= 0x77 && !fetch_modrm (ins
))
9063 case USE_VEX_W_TABLE
:
9068 dp
= &vex_w_table
[dp
->op
[1].bytemode
][ins
->vex
.w
];
9071 case USE_EVEX_TABLE
:
9072 ins
->two_source_ops
= false;
9074 ins
->vex
.evex
= true;
9075 if (!fetch_code (ins
->info
, ins
->codep
+ 4))
9077 /* The first byte after 0x62. */
9078 if (*ins
->codep
& 0x8)
9080 if (!(*ins
->codep
& 0x10))
9083 ins
->rex
= ~(*ins
->codep
>> 5) & 0x7;
9084 switch (*ins
->codep
& 0x7)
9089 vex_table_index
= EVEX_0F
;
9092 vex_table_index
= EVEX_0F38
;
9095 vex_table_index
= EVEX_0F3A
;
9098 vex_table_index
= EVEX_MAP4
;
9099 ins
->evex_type
= evex_from_legacy
;
9100 if (ins
->address_mode
!= mode_64bit
)
9104 vex_table_index
= EVEX_MAP5
;
9107 vex_table_index
= EVEX_MAP6
;
9110 vex_table_index
= EVEX_MAP7
;
9114 /* The second byte after 0x62. */
9116 ins
->vex
.w
= *ins
->codep
& 0x80;
9117 if (ins
->vex
.w
&& ins
->address_mode
== mode_64bit
)
9120 ins
->vex
.register_specifier
= (~(*ins
->codep
>> 3)) & 0xf;
9122 if (!(*ins
->codep
& 0x4))
9125 switch ((*ins
->codep
& 0x3))
9130 ins
->vex
.prefix
= DATA_PREFIX_OPCODE
;
9133 ins
->vex
.prefix
= REPE_PREFIX_OPCODE
;
9136 ins
->vex
.prefix
= REPNE_PREFIX_OPCODE
;
9140 /* The third byte after 0x62. */
9143 /* Remember the static rounding bits. */
9144 ins
->vex
.ll
= (*ins
->codep
>> 5) & 3;
9145 ins
->vex
.b
= *ins
->codep
& 0x10;
9147 ins
->vex
.v
= *ins
->codep
& 0x8;
9148 ins
->vex
.mask_register_specifier
= *ins
->codep
& 0x7;
9149 ins
->vex
.zeroing
= *ins
->codep
& 0x80;
9151 if (ins
->address_mode
!= mode_64bit
)
9153 /* Report bad for !evex_default and when two fixed values of evex
9155 if (ins
->evex_type
!= evex_default
9156 || (ins
->rex2
& (REX_B
| REX_X
)))
9158 /* In 16/32-bit mode silently ignore following bits. */
9160 ins
->rex2
&= ~REX_R
;
9163 /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9164 all bits of EVEX.vvvv and EVEX.V' must be 1. */
9165 if (ins
->evex_type
== evex_from_legacy
&& !ins
->vex
.nd
9166 && (ins
->vex
.register_specifier
|| !ins
->vex
.v
))
9171 /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9172 lower 2 bits of EVEX.aaa must be 0. */
9173 if (ins
->evex_type
== evex_from_legacy
9174 && ((ins
->vex
.mask_register_specifier
& 0x3) != 0
9176 || ins
->vex
.zeroing
!= 0))
9180 vindex
= *ins
->codep
++;
9181 if (vex_table_index
!= EVEX_MAP7
)
9182 dp
= &evex_table
[vex_table_index
][vindex
];
9183 else if (vindex
== 0xf8)
9184 dp
= &map7_f8_opcode
;
9187 ins
->end_codep
= ins
->codep
;
9188 if (!fetch_modrm (ins
))
9191 /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9192 which has the same encoding as vex.length == 128 and they can share
9193 the same processing with vex.length in OP_VEX. */
9194 if (ins
->modrm
.mod
== 3 && ins
->vex
.b
&& ins
->evex_type
!= evex_from_legacy
)
9195 ins
->vex
.length
= 512;
9198 switch (ins
->vex
.ll
)
9201 ins
->vex
.length
= 128;
9204 ins
->vex
.length
= 256;
9207 ins
->vex
.length
= 512;
9223 if (dp
->name
!= NULL
)
9226 return get_valid_dis386 (dp
, ins
);
9230 get_sib (instr_info
*ins
, int sizeflag
)
9232 /* If modrm.mod == 3, operand must be register. */
9234 && ((sizeflag
& AFLAG
) || ins
->address_mode
== mode_64bit
)
9235 && ins
->modrm
.mod
!= 3
9236 && ins
->modrm
.rm
== 4)
9238 if (!fetch_code (ins
->info
, ins
->codep
+ 2))
9240 ins
->sib
.index
= (ins
->codep
[1] >> 3) & 7;
9241 ins
->sib
.scale
= (ins
->codep
[1] >> 6) & 3;
9242 ins
->sib
.base
= ins
->codep
[1] & 7;
9243 ins
->has_sib
= true;
9246 ins
->has_sib
= false;
9251 /* Like oappend_with_style (below) but always with text style. */
9254 oappend (instr_info
*ins
, const char *s
)
9256 oappend_with_style (ins
, s
, dis_style_text
);
9259 /* Like oappend (above), but S is a string starting with '%'. In
9260 Intel syntax, the '%' is elided. */
9263 oappend_register (instr_info
*ins
, const char *s
)
9265 oappend_with_style (ins
, s
+ ins
->intel_syntax
, dis_style_register
);
9268 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9269 STYLE is the default style to use in the fprintf_styled_func calls,
9270 however, FMT might include embedded style markers (see oappend_style),
9271 these embedded markers are not printed, but instead change the style
9272 used in the next fprintf_styled_func call. */
9274 static void ATTRIBUTE_PRINTF_3
9275 i386_dis_printf (const disassemble_info
*info
, enum disassembler_style style
,
9276 const char *fmt
, ...)
9279 enum disassembler_style curr_style
= style
;
9280 const char *start
, *curr
;
9281 char staging_area
[40];
9284 /* In particular print_insn()'s processing of op_txt[] can hand rather long
9285 strings here. Bypass vsnprintf() in such cases to avoid capacity issues
9286 with the staging area. */
9287 if (strcmp (fmt
, "%s"))
9289 int res
= vsnprintf (staging_area
, sizeof (staging_area
), fmt
, ap
);
9296 if ((size_t) res
>= sizeof (staging_area
))
9299 start
= curr
= staging_area
;
9303 start
= curr
= va_arg (ap
, const char *);
9310 || (*curr
== STYLE_MARKER_CHAR
9311 && ISXDIGIT (*(curr
+ 1))
9312 && *(curr
+ 2) == STYLE_MARKER_CHAR
))
9314 /* Output content between our START position and CURR. */
9315 int len
= curr
- start
;
9316 int n
= (*info
->fprintf_styled_func
) (info
->stream
, curr_style
,
9317 "%.*s", len
, start
);
9324 /* Skip over the initial STYLE_MARKER_CHAR. */
9327 /* Update the CURR_STYLE. As there are less than 16 styles, it
9328 is possible, that if the input is corrupted in some way, that
9329 we might set CURR_STYLE to an invalid value. Don't worry
9330 though, we check for this situation. */
9331 if (*curr
>= '0' && *curr
<= '9')
9332 curr_style
= (enum disassembler_style
) (*curr
- '0');
9333 else if (*curr
>= 'a' && *curr
<= 'f')
9334 curr_style
= (enum disassembler_style
) (*curr
- 'a' + 10);
9336 curr_style
= dis_style_text
;
9338 /* Check for an invalid style having been selected. This should
9339 never happen, but it doesn't hurt to be a little paranoid. */
9340 if (curr_style
> dis_style_comment_start
)
9341 curr_style
= dis_style_text
;
9343 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9346 /* Reset the START to after the style marker. */
9356 print_insn (bfd_vma pc
, disassemble_info
*info
, int intel_syntax
)
9358 const struct dis386
*dp
;
9361 char *op_txt
[MAX_OPERANDS
];
9363 bool intel_swap_2_3
;
9364 int sizeflag
, orig_sizeflag
;
9366 struct dis_private priv
;
9371 .intel_syntax
= intel_syntax
>= 0
9373 : (info
->mach
& bfd_mach_i386_intel_syntax
) != 0,
9374 .intel_mnemonic
= !SYSV386_COMPAT
,
9375 .op_index
[0 ... MAX_OPERANDS
- 1] = -1,
9377 .start_codep
= priv
.the_buffer
,
9378 .codep
= priv
.the_buffer
,
9380 .last_lock_prefix
= -1,
9381 .last_repz_prefix
= -1,
9382 .last_repnz_prefix
= -1,
9383 .last_data_prefix
= -1,
9384 .last_addr_prefix
= -1,
9385 .last_rex_prefix
= -1,
9386 .last_rex2_prefix
= -1,
9387 .last_seg_prefix
= -1,
9390 char op_out
[MAX_OPERANDS
][MAX_OPERAND_BUFFER_SIZE
];
9392 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9393 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9394 ins
.address_mode
= mode_32bit
;
9395 else if (info
->mach
== bfd_mach_i386_i8086
)
9397 ins
.address_mode
= mode_16bit
;
9398 priv
.orig_sizeflag
= 0;
9401 ins
.address_mode
= mode_64bit
;
9403 for (p
= info
->disassembler_options
; p
!= NULL
;)
9405 if (startswith (p
, "amd64"))
9407 else if (startswith (p
, "intel64"))
9408 ins
.isa64
= intel64
;
9409 else if (startswith (p
, "x86-64"))
9411 ins
.address_mode
= mode_64bit
;
9412 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9414 else if (startswith (p
, "i386"))
9416 ins
.address_mode
= mode_32bit
;
9417 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9419 else if (startswith (p
, "i8086"))
9421 ins
.address_mode
= mode_16bit
;
9422 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9424 else if (startswith (p
, "intel"))
9426 if (startswith (p
+ 5, "-mnemonic"))
9427 ins
.intel_mnemonic
= true;
9429 ins
.intel_syntax
= 1;
9431 else if (startswith (p
, "att"))
9433 ins
.intel_syntax
= 0;
9434 if (startswith (p
+ 3, "-mnemonic"))
9435 ins
.intel_mnemonic
= false;
9437 else if (startswith (p
, "addr"))
9439 if (ins
.address_mode
== mode_64bit
)
9441 if (p
[4] == '3' && p
[5] == '2')
9442 priv
.orig_sizeflag
&= ~AFLAG
;
9443 else if (p
[4] == '6' && p
[5] == '4')
9444 priv
.orig_sizeflag
|= AFLAG
;
9448 if (p
[4] == '1' && p
[5] == '6')
9449 priv
.orig_sizeflag
&= ~AFLAG
;
9450 else if (p
[4] == '3' && p
[5] == '2')
9451 priv
.orig_sizeflag
|= AFLAG
;
9454 else if (startswith (p
, "data"))
9456 if (p
[4] == '1' && p
[5] == '6')
9457 priv
.orig_sizeflag
&= ~DFLAG
;
9458 else if (p
[4] == '3' && p
[5] == '2')
9459 priv
.orig_sizeflag
|= DFLAG
;
9461 else if (startswith (p
, "suffix"))
9462 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9464 p
= strchr (p
, ',');
9469 if (ins
.address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9471 i386_dis_printf (info
, dis_style_text
, _("64-bit address is disabled"));
9475 if (ins
.intel_syntax
)
9477 ins
.open_char
= '[';
9478 ins
.close_char
= ']';
9479 ins
.separator_char
= '+';
9480 ins
.scale_char
= '*';
9484 ins
.open_char
= '(';
9485 ins
.close_char
= ')';
9486 ins
.separator_char
= ',';
9487 ins
.scale_char
= ',';
9490 /* The output looks better if we put 7 bytes on a line, since that
9491 puts most long word instructions on a single line. */
9492 info
->bytes_per_line
= 7;
9494 info
->private_data
= &priv
;
9496 priv
.insn_start
= pc
;
9498 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9501 ins
.op_out
[i
] = op_out
[i
];
9504 sizeflag
= priv
.orig_sizeflag
;
9506 switch (ckprefix (&ins
))
9512 /* Too many prefixes or unused REX prefixes. */
9514 i
< (int) ARRAY_SIZE (ins
.all_prefixes
) && ins
.all_prefixes
[i
];
9516 i386_dis_printf (info
, dis_style_mnemonic
, "%s%s",
9517 (i
== 0 ? "" : " "),
9518 prefix_name (ins
.address_mode
, ins
.all_prefixes
[i
],
9523 case ckp_fetch_error
:
9524 goto fetch_error_out
;
9527 ins
.nr_prefixes
= ins
.codep
- ins
.start_codep
;
9529 if (!fetch_code (info
, ins
.codep
+ 1))
9532 ret
= fetch_error (&ins
);
9536 ins
.two_source_ops
= (*ins
.codep
== 0x62 || *ins
.codep
== 0xc8);
9538 if ((ins
.prefixes
& PREFIX_FWAIT
)
9539 && (*ins
.codep
< 0xd8 || *ins
.codep
> 0xdf))
9541 /* Handle ins.prefixes before fwait. */
9542 for (i
= 0; i
< ins
.fwait_prefix
&& ins
.all_prefixes
[i
];
9544 i386_dis_printf (info
, dis_style_mnemonic
, "%s ",
9545 prefix_name (ins
.address_mode
, ins
.all_prefixes
[i
],
9547 i386_dis_printf (info
, dis_style_mnemonic
, "fwait");
9552 /* REX2.M in rex2 prefix represents map0 or map1. */
9553 if (ins
.last_rex2_prefix
< 0 ? *ins
.codep
== 0x0f : (ins
.rex2
& REX2_M
))
9558 if (!fetch_code (info
, ins
.codep
+ 1))
9559 goto fetch_error_out
;
9562 dp
= &dis386_twobyte
[*ins
.codep
];
9563 ins
.need_modrm
= twobyte_has_modrm
[*ins
.codep
];
9567 dp
= &dis386
[*ins
.codep
];
9568 ins
.need_modrm
= onebyte_has_modrm
[*ins
.codep
];
9572 /* Save sizeflag for printing the extra ins.prefixes later before updating
9573 it for mnemonic and operand processing. The prefix names depend
9574 only on the address mode. */
9575 orig_sizeflag
= sizeflag
;
9576 if (ins
.prefixes
& PREFIX_ADDR
)
9578 if ((ins
.prefixes
& PREFIX_DATA
))
9581 ins
.end_codep
= ins
.codep
;
9582 if (ins
.need_modrm
&& !fetch_modrm (&ins
))
9583 goto fetch_error_out
;
9585 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
9587 if (!get_sib (&ins
, sizeflag
)
9588 || !dofloat (&ins
, sizeflag
))
9589 goto fetch_error_out
;
9593 dp
= get_valid_dis386 (dp
, &ins
);
9594 if (dp
== &err_opcode
)
9595 goto fetch_error_out
;
9597 /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9598 is interpreted as the operand size override. */
9599 if (ins
.evex_type
== evex_from_legacy
9600 && ins
.vex
.prefix
== DATA_PREFIX_OPCODE
)
9603 if (dp
!= NULL
&& putop (&ins
, dp
->name
, sizeflag
) == 0)
9605 if (!get_sib (&ins
, sizeflag
))
9606 goto fetch_error_out
;
9607 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9609 ins
.obufp
= ins
.op_out
[i
];
9610 ins
.op_ad
= MAX_OPERANDS
- 1 - i
;
9612 && !dp
->op
[i
].rtn (&ins
, dp
->op
[i
].bytemode
, sizeflag
))
9613 goto fetch_error_out
;
9614 /* For EVEX instruction after the last operand masking
9615 should be printed. */
9616 if (i
== 0 && ins
.vex
.evex
)
9618 /* Don't print {%k0}. */
9619 if (ins
.vex
.mask_register_specifier
)
9621 const char *reg_name
9622 = att_names_mask
[ins
.vex
.mask_register_specifier
];
9624 oappend (&ins
, "{");
9625 oappend_register (&ins
, reg_name
);
9626 oappend (&ins
, "}");
9628 if (ins
.vex
.zeroing
)
9629 oappend (&ins
, "{z}");
9631 else if (ins
.vex
.zeroing
)
9633 oappend (&ins
, "{bad}");
9637 /* Instructions with a mask register destination allow for
9638 zeroing-masking only (if any masking at all), which is
9639 _not_ expressed by EVEX.z. */
9640 if (ins
.vex
.zeroing
&& dp
->op
[0].bytemode
== mask_mode
)
9641 ins
.illegal_masking
= true;
9643 /* S/G insns require a mask and don't allow
9645 if ((dp
->op
[0].bytemode
== vex_vsib_d_w_dq_mode
9646 || dp
->op
[0].bytemode
== vex_vsib_q_w_dq_mode
)
9647 && (ins
.vex
.mask_register_specifier
== 0
9648 || ins
.vex
.zeroing
))
9649 ins
.illegal_masking
= true;
9651 if (ins
.illegal_masking
)
9652 oappend (&ins
, "/(bad)");
9656 /* Check whether rounding control was enabled for an insn not
9657 supporting it, when evex.b is not treated as evex.nd. */
9658 if (ins
.modrm
.mod
== 3 && ins
.vex
.b
&& ins
.evex_type
== evex_default
9659 && !(ins
.evex_used
& EVEX_b_used
))
9661 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9663 ins
.obufp
= ins
.op_out
[i
];
9666 oappend (&ins
, names_rounding
[ins
.vex
.ll
]);
9667 oappend (&ins
, "bad}");
9674 /* Clear instruction information. */
9675 info
->insn_info_valid
= 0;
9676 info
->branch_delay_insns
= 0;
9677 info
->data_size
= 0;
9678 info
->insn_type
= dis_noninsn
;
9682 /* Reset jump operation indicator. */
9683 ins
.op_is_jump
= false;
9685 int jump_detection
= 0;
9687 /* Extract flags. */
9688 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9690 if ((dp
->op
[i
].rtn
== OP_J
)
9691 || (dp
->op
[i
].rtn
== OP_indirE
))
9692 jump_detection
|= 1;
9693 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
9694 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
9695 jump_detection
|= 2;
9696 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
9697 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
9698 jump_detection
|= 4;
9701 /* Determine if this is a jump or branch. */
9702 if ((jump_detection
& 0x3) == 0x3)
9704 ins
.op_is_jump
= true;
9705 if (jump_detection
& 0x4)
9706 info
->insn_type
= dis_condbranch
;
9708 info
->insn_type
= (dp
->name
&& !strncmp (dp
->name
, "call", 4))
9709 ? dis_jsr
: dis_branch
;
9713 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9714 are all 0s in inverted form. */
9715 if (ins
.need_vex
&& ins
.vex
.register_specifier
!= 0)
9717 i386_dis_printf (info
, dis_style_text
, "(bad)");
9718 ret
= ins
.end_codep
- priv
.the_buffer
;
9722 if ((dp
->prefix_requirement
& PREFIX_REX2_ILLEGAL
)
9723 && ins
.last_rex2_prefix
>= 0 && (ins
.rex2
& REX2_SPECIAL
) == 0)
9725 i386_dis_printf (info
, dis_style_text
, "(bad)");
9726 ret
= ins
.end_codep
- priv
.the_buffer
;
9730 switch (dp
->prefix_requirement
& ~PREFIX_REX2_ILLEGAL
)
9733 /* If only the data prefix is marked as mandatory, its absence renders
9734 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9735 if (ins
.need_vex
? !ins
.vex
.prefix
: !(ins
.prefixes
& PREFIX_DATA
))
9737 i386_dis_printf (info
, dis_style_text
, "(bad)");
9738 ret
= ins
.end_codep
- priv
.the_buffer
;
9741 ins
.used_prefixes
|= PREFIX_DATA
;
9744 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9745 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9746 used by putop and MMX/SSE operand and may be overridden by the
9747 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9750 ? ins
.vex
.prefix
== REPE_PREFIX_OPCODE
9751 || ins
.vex
.prefix
== REPNE_PREFIX_OPCODE
9753 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9754 && (ins
.used_prefixes
9755 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
9757 ? ins
.vex
.prefix
== DATA_PREFIX_OPCODE
9759 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
9761 && (ins
.used_prefixes
& PREFIX_DATA
) == 0))
9762 || (ins
.vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
9763 && !ins
.vex
.w
!= !(ins
.used_prefixes
& PREFIX_DATA
)))
9765 i386_dis_printf (info
, dis_style_text
, "(bad)");
9766 ret
= ins
.end_codep
- priv
.the_buffer
;
9771 case PREFIX_IGNORED
:
9772 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9773 origins in all_prefixes. */
9774 ins
.used_prefixes
&= ~PREFIX_OPCODE
;
9775 if (ins
.last_data_prefix
>= 0)
9776 ins
.all_prefixes
[ins
.last_data_prefix
] = 0x66;
9777 if (ins
.last_repz_prefix
>= 0)
9778 ins
.all_prefixes
[ins
.last_repz_prefix
] = 0xf3;
9779 if (ins
.last_repnz_prefix
>= 0)
9780 ins
.all_prefixes
[ins
.last_repnz_prefix
] = 0xf2;
9783 case PREFIX_NP_OR_DATA
:
9784 if (ins
.vex
.prefix
== REPE_PREFIX_OPCODE
9785 || ins
.vex
.prefix
== REPNE_PREFIX_OPCODE
)
9787 i386_dis_printf (info
, dis_style_text
, "(bad)");
9788 ret
= ins
.end_codep
- priv
.the_buffer
;
9796 i386_dis_printf (info
, dis_style_text
, "(bad)");
9797 ret
= ins
.end_codep
- priv
.the_buffer
;
9803 /* Check if the REX prefix is used. */
9804 if ((ins
.rex
^ ins
.rex_used
) == 0
9805 && !ins
.need_vex
&& ins
.last_rex_prefix
>= 0)
9806 ins
.all_prefixes
[ins
.last_rex_prefix
] = 0;
9808 /* Check if the REX2 prefix is used. */
9809 if (ins
.last_rex2_prefix
>= 0
9810 && ((ins
.rex2
& REX2_SPECIAL
)
9811 || (((ins
.rex2
& 7) ^ (ins
.rex2_used
& 7)) == 0
9812 && (ins
.rex
^ ins
.rex_used
) == 0
9813 && (ins
.rex2
& 7))))
9814 ins
.all_prefixes
[ins
.last_rex2_prefix
] = 0;
9816 /* Check if the SEG prefix is used. */
9817 if ((ins
.prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
9818 | PREFIX_FS
| PREFIX_GS
)) != 0
9819 && (ins
.used_prefixes
& ins
.active_seg_prefix
) != 0)
9820 ins
.all_prefixes
[ins
.last_seg_prefix
] = 0;
9822 /* Check if the ADDR prefix is used. */
9823 if ((ins
.prefixes
& PREFIX_ADDR
) != 0
9824 && (ins
.used_prefixes
& PREFIX_ADDR
) != 0)
9825 ins
.all_prefixes
[ins
.last_addr_prefix
] = 0;
9827 /* Check if the DATA prefix is used. */
9828 if ((ins
.prefixes
& PREFIX_DATA
) != 0
9829 && (ins
.used_prefixes
& PREFIX_DATA
) != 0
9831 ins
.all_prefixes
[ins
.last_data_prefix
] = 0;
9833 /* Print the extra ins.prefixes. */
9835 for (i
= 0; i
< (int) ARRAY_SIZE (ins
.all_prefixes
); i
++)
9836 if (ins
.all_prefixes
[i
])
9838 const char *name
= prefix_name (ins
.address_mode
, ins
.all_prefixes
[i
],
9843 prefix_length
+= strlen (name
) + 1;
9844 if (ins
.all_prefixes
[i
] == REX2_OPCODE
)
9845 i386_dis_printf (info
, dis_style_mnemonic
, "{%s 0x%x} ", name
,
9846 (unsigned int) ins
.rex2_payload
);
9848 i386_dis_printf (info
, dis_style_mnemonic
, "%s ", name
);
9851 /* Check maximum code length. */
9852 if ((ins
.codep
- ins
.start_codep
) > MAX_CODE_LENGTH
)
9854 i386_dis_printf (info
, dis_style_text
, "(bad)");
9855 ret
= MAX_CODE_LENGTH
;
9859 /* Calculate the number of operands this instruction has. */
9861 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9862 if (*ins
.op_out
[i
] != '\0')
9865 /* Calculate the number of spaces to print after the mnemonic. */
9866 ins
.obufp
= ins
.mnemonicendp
;
9869 i
= strlen (ins
.obuf
) + prefix_length
;
9878 /* Print the instruction mnemonic along with any trailing whitespace. */
9879 i386_dis_printf (info
, dis_style_mnemonic
, "%s%*s", ins
.obuf
, i
, "");
9881 /* The enter and bound instructions are printed with operands in the same
9882 order as the intel book; everything else is printed in reverse order. */
9883 intel_swap_2_3
= false;
9884 if (ins
.intel_syntax
|| ins
.two_source_ops
)
9886 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9887 op_txt
[i
] = ins
.op_out
[i
];
9889 if (ins
.intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
9890 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
9892 op_txt
[2] = ins
.op_out
[3];
9893 op_txt
[3] = ins
.op_out
[2];
9894 intel_swap_2_3
= true;
9897 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
9901 ins
.op_ad
= ins
.op_index
[i
];
9902 ins
.op_index
[i
] = ins
.op_index
[MAX_OPERANDS
- 1 - i
];
9903 ins
.op_index
[MAX_OPERANDS
- 1 - i
] = ins
.op_ad
;
9904 riprel
= ins
.op_riprel
[i
];
9905 ins
.op_riprel
[i
] = ins
.op_riprel
[MAX_OPERANDS
- 1 - i
];
9906 ins
.op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
9911 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9912 op_txt
[MAX_OPERANDS
- 1 - i
] = ins
.op_out
[i
];
9916 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9919 /* In Intel syntax embedded rounding / SAE are not separate operands.
9920 Instead they're attached to the prior register operand. Simply
9921 suppress emission of the comma to achieve that effect. */
9922 switch (i
& -(ins
.intel_syntax
&& dp
))
9925 if (dp
->op
[2].rtn
== OP_Rounding
&& !intel_swap_2_3
)
9929 if (dp
->op
[3].rtn
== OP_Rounding
|| intel_swap_2_3
)
9934 i386_dis_printf (info
, dis_style_text
, ",");
9935 if (ins
.op_index
[i
] != -1 && !ins
.op_riprel
[i
])
9937 bfd_vma target
= (bfd_vma
) ins
.op_address
[ins
.op_index
[i
]];
9941 info
->insn_info_valid
= 1;
9942 info
->branch_delay_insns
= 0;
9943 info
->data_size
= 0;
9944 info
->target
= target
;
9947 (*info
->print_address_func
) (target
, info
);
9950 i386_dis_printf (info
, dis_style_text
, "%s", op_txt
[i
]);
9954 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9955 if (ins
.op_index
[i
] != -1 && ins
.op_riprel
[i
])
9957 i386_dis_printf (info
, dis_style_comment_start
, " # ");
9958 (*info
->print_address_func
)
9959 ((bfd_vma
)(ins
.start_pc
+ (ins
.codep
- ins
.start_codep
)
9960 + ins
.op_address
[ins
.op_index
[i
]]),
9964 ret
= ins
.codep
- priv
.the_buffer
;
9966 info
->private_data
= NULL
;
9970 /* Here for backwards compatibility. When gdb stops using
9971 print_insn_i386_att and print_insn_i386_intel these functions can
9972 disappear, and print_insn_i386 be merged into print_insn. */
9974 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
9976 return print_insn (pc
, info
, 0);
9980 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
9982 return print_insn (pc
, info
, 1);
9986 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
9988 return print_insn (pc
, info
, -1);
9991 static const char *float_mem
[] = {
10066 static const unsigned char float_mem_mode
[] = {
10141 #define ST { OP_ST, 0 }
10142 #define STi { OP_STi, 0 }
10144 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10145 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10146 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10147 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10148 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10149 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10150 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10151 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10152 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10154 static const struct dis386 float_reg
[][8] = {
10157 { "fadd", { ST
, STi
}, 0 },
10158 { "fmul", { ST
, STi
}, 0 },
10159 { "fcom", { STi
}, 0 },
10160 { "fcomp", { STi
}, 0 },
10161 { "fsub", { ST
, STi
}, 0 },
10162 { "fsubr", { ST
, STi
}, 0 },
10163 { "fdiv", { ST
, STi
}, 0 },
10164 { "fdivr", { ST
, STi
}, 0 },
10168 { "fld", { STi
}, 0 },
10169 { "fxch", { STi
}, 0 },
10179 { "fcmovb", { ST
, STi
}, 0 },
10180 { "fcmove", { ST
, STi
}, 0 },
10181 { "fcmovbe",{ ST
, STi
}, 0 },
10182 { "fcmovu", { ST
, STi
}, 0 },
10190 { "fcmovnb",{ ST
, STi
}, 0 },
10191 { "fcmovne",{ ST
, STi
}, 0 },
10192 { "fcmovnbe",{ ST
, STi
}, 0 },
10193 { "fcmovnu",{ ST
, STi
}, 0 },
10195 { "fucomi", { ST
, STi
}, 0 },
10196 { "fcomi", { ST
, STi
}, 0 },
10201 { "fadd", { STi
, ST
}, 0 },
10202 { "fmul", { STi
, ST
}, 0 },
10205 { "fsub{!M|r}", { STi
, ST
}, 0 },
10206 { "fsub{M|}", { STi
, ST
}, 0 },
10207 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10208 { "fdiv{M|}", { STi
, ST
}, 0 },
10212 { "ffree", { STi
}, 0 },
10214 { "fst", { STi
}, 0 },
10215 { "fstp", { STi
}, 0 },
10216 { "fucom", { STi
}, 0 },
10217 { "fucomp", { STi
}, 0 },
10223 { "faddp", { STi
, ST
}, 0 },
10224 { "fmulp", { STi
, ST
}, 0 },
10227 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10228 { "fsub{M|}p", { STi
, ST
}, 0 },
10229 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10230 { "fdiv{M|}p", { STi
, ST
}, 0 },
10234 { "ffreep", { STi
}, 0 },
10239 { "fucomip", { ST
, STi
}, 0 },
10240 { "fcomip", { ST
, STi
}, 0 },
10245 static const char *const fgrps
[][8] = {
10248 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10253 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10258 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10263 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10268 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10273 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10278 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10283 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10284 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10289 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10294 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10299 swap_operand (instr_info
*ins
)
10301 ins
->mnemonicendp
[0] = '.';
10302 ins
->mnemonicendp
[1] = 's';
10303 ins
->mnemonicendp
[2] = '\0';
10304 ins
->mnemonicendp
+= 2;
10308 dofloat (instr_info
*ins
, int sizeflag
)
10310 const struct dis386
*dp
;
10311 unsigned char floatop
= ins
->codep
[-1];
10313 if (ins
->modrm
.mod
!= 3)
10315 int fp_indx
= (floatop
- 0xd8) * 8 + ins
->modrm
.reg
;
10317 putop (ins
, float_mem
[fp_indx
], sizeflag
);
10318 ins
->obufp
= ins
->op_out
[0];
10320 return OP_E (ins
, float_mem_mode
[fp_indx
], sizeflag
);
10322 /* Skip mod/rm byte. */
10326 dp
= &float_reg
[floatop
- 0xd8][ins
->modrm
.reg
];
10327 if (dp
->name
== NULL
)
10329 putop (ins
, fgrps
[dp
->op
[0].bytemode
][ins
->modrm
.rm
], sizeflag
);
10331 /* Instruction fnstsw is only one with strange arg. */
10332 if (floatop
== 0xdf && ins
->codep
[-1] == 0xe0)
10333 strcpy (ins
->op_out
[0], att_names16
[0] + ins
->intel_syntax
);
10337 putop (ins
, dp
->name
, sizeflag
);
10339 ins
->obufp
= ins
->op_out
[0];
10342 && !dp
->op
[0].rtn (ins
, dp
->op
[0].bytemode
, sizeflag
))
10345 ins
->obufp
= ins
->op_out
[1];
10348 && !dp
->op
[1].rtn (ins
, dp
->op
[1].bytemode
, sizeflag
))
10355 OP_ST (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
10356 int sizeflag ATTRIBUTE_UNUSED
)
10358 oappend_register (ins
, "%st");
10363 OP_STi (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
10364 int sizeflag ATTRIBUTE_UNUSED
)
10367 int res
= snprintf (scratch
, ARRAY_SIZE (scratch
), "%%st(%d)", ins
->modrm
.rm
);
10369 if (res
< 0 || (size_t) res
>= ARRAY_SIZE (scratch
))
10371 oappend_register (ins
, scratch
);
10375 /* Capital letters in template are macros. */
10377 putop (instr_info
*ins
, const char *in_template
, int sizeflag
)
10382 unsigned int l
= 0, len
= 0;
10385 for (p
= in_template
; *p
; p
++)
10389 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10397 *ins
->obufp
++ = *p
;
10406 if (ins
->intel_syntax
)
10408 while (*++p
!= '|')
10409 if (*p
== '}' || *p
== '\0')
10415 while (*++p
!= '}')
10425 if (ins
->intel_syntax
)
10427 if ((ins
->need_modrm
&& ins
->modrm
.mod
!= 3 && !ins
->vex
.nd
)
10428 || (sizeflag
& SUFFIX_ALWAYS
))
10429 *ins
->obufp
++ = 'b';
10435 if (ins
->intel_syntax
)
10437 if (sizeflag
& SUFFIX_ALWAYS
)
10438 *ins
->obufp
++ = 'b';
10440 else if (l
== 1 && last
[0] == 'L')
10442 if (ins
->address_mode
== mode_64bit
10443 && !(ins
->prefixes
& PREFIX_ADDR
))
10445 *ins
->obufp
++ = 'a';
10446 *ins
->obufp
++ = 'b';
10447 *ins
->obufp
++ = 's';
10456 if (ins
->intel_syntax
&& !alt
)
10458 if ((ins
->prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10460 if (sizeflag
& DFLAG
)
10461 *ins
->obufp
++ = ins
->intel_syntax
? 'd' : 'l';
10463 *ins
->obufp
++ = ins
->intel_syntax
? 'w' : 's';
10464 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10473 if (!ins
->vex
.evex
|| ins
->vex
.w
)
10474 *ins
->obufp
++ = 'd';
10476 oappend (ins
, "{bad}");
10485 if (ins
->intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10488 if (ins
->modrm
.mod
== 3)
10490 if (ins
->rex
& REX_W
)
10491 *ins
->obufp
++ = 'q';
10494 if (sizeflag
& DFLAG
)
10495 *ins
->obufp
++ = ins
->intel_syntax
? 'd' : 'l';
10497 *ins
->obufp
++ = 'w';
10498 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10502 *ins
->obufp
++ = 'w';
10510 if (!ins
->vex
.evex
|| ins
->vex
.b
|| ins
->vex
.ll
>= 2
10512 || (ins
->modrm
.mod
== 3 && (ins
->rex
& REX_X
))
10513 || !ins
->vex
.v
|| ins
->vex
.mask_register_specifier
)
10515 /* AVX512 extends a number of V*D insns to also have V*Q variants,
10516 merely distinguished by EVEX.W. Look for a use of the
10517 respective macro. */
10520 const char *pct
= strchr (p
+ 1, '%');
10522 if (pct
!= NULL
&& pct
[1] == 'D' && pct
[2] == 'Q')
10525 *ins
->obufp
++ = '{';
10526 *ins
->obufp
++ = 'e';
10527 *ins
->obufp
++ = 'v';
10528 *ins
->obufp
++ = 'e';
10529 *ins
->obufp
++ = 'x';
10530 *ins
->obufp
++ = '}';
10531 *ins
->obufp
++ = ' ';
10538 /* For jcxz/jecxz */
10539 if (ins
->address_mode
== mode_64bit
)
10541 if (sizeflag
& AFLAG
)
10542 *ins
->obufp
++ = 'r';
10544 *ins
->obufp
++ = 'e';
10547 if (sizeflag
& AFLAG
)
10548 *ins
->obufp
++ = 'e';
10549 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_ADDR
);
10554 if (ins
->intel_syntax
)
10556 if ((ins
->prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10558 if (sizeflag
& AFLAG
)
10559 *ins
->obufp
++ = ins
->address_mode
== mode_64bit
? 'q' : 'l';
10561 *ins
->obufp
++ = ins
->address_mode
== mode_64bit
? 'l' : 'w';
10562 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_ADDR
);
10565 else if (l
== 1 && last
[0] == 'C')
10571 if (ins
->intel_syntax
|| (ins
->obufp
[-1] != 's'
10572 && !(sizeflag
& SUFFIX_ALWAYS
)))
10574 if ((ins
->rex
& REX_W
) || (sizeflag
& DFLAG
))
10575 *ins
->obufp
++ = 'l';
10577 *ins
->obufp
++ = 'w';
10578 if (!(ins
->rex
& REX_W
))
10579 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10584 if (ins
->intel_syntax
)
10586 if ((ins
->prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10587 || (ins
->prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10589 ins
->used_prefixes
|= ins
->prefixes
& (PREFIX_CS
| PREFIX_DS
);
10590 *ins
->obufp
++ = ',';
10591 *ins
->obufp
++ = 'p';
10593 /* Set active_seg_prefix even if not set in 64-bit mode
10594 because here it is a valid branch hint. */
10595 if (ins
->prefixes
& PREFIX_DS
)
10597 ins
->active_seg_prefix
= PREFIX_DS
;
10598 *ins
->obufp
++ = 't';
10602 ins
->active_seg_prefix
= PREFIX_CS
;
10603 *ins
->obufp
++ = 'n';
10607 else if (l
== 1 && last
[0] == 'X')
10610 *ins
->obufp
++ = 'h';
10612 oappend (ins
, "{bad}");
10619 if (ins
->rex
& REX_W
)
10620 *ins
->obufp
++ = 'q';
10622 *ins
->obufp
++ = 'd';
10625 if (ins
->intel_syntax
)
10627 if (sizeflag
& SUFFIX_ALWAYS
)
10629 if (ins
->rex
& REX_W
)
10630 *ins
->obufp
++ = 'q';
10632 *ins
->obufp
++ = 'l';
10636 if (ins
->intel_mnemonic
!= cond
)
10637 *ins
->obufp
++ = 'r';
10640 if ((ins
->prefixes
& PREFIX_FWAIT
) == 0)
10641 *ins
->obufp
++ = 'n';
10643 ins
->used_prefixes
|= PREFIX_FWAIT
;
10647 if (ins
->rex
& REX_W
)
10648 *ins
->obufp
++ = 'o';
10649 else if (ins
->intel_syntax
&& (sizeflag
& DFLAG
))
10650 *ins
->obufp
++ = 'q';
10652 *ins
->obufp
++ = 'd';
10653 if (!(ins
->rex
& REX_W
))
10654 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10657 if (ins
->address_mode
== mode_64bit
10658 && (ins
->isa64
== intel64
|| (ins
->rex
& REX_W
)
10659 || !(ins
->prefixes
& PREFIX_DATA
)))
10661 if (sizeflag
& SUFFIX_ALWAYS
)
10662 *ins
->obufp
++ = 'q';
10665 /* Fall through. */
10669 if (!cond
&& ins
->last_rex2_prefix
>= 0 && (ins
->rex
& REX_W
))
10671 /* For pushp and popp, p is printed and do not print {rex2}
10673 *ins
->obufp
++ = 'p';
10674 ins
->rex2
|= REX2_SPECIAL
;
10678 /* For "!P" print nothing else in Intel syntax. */
10679 if (!cond
&& ins
->intel_syntax
)
10682 if ((ins
->modrm
.mod
== 3 || !cond
)
10683 && !(sizeflag
& SUFFIX_ALWAYS
))
10685 /* Fall through. */
10687 if ((!(ins
->rex
& REX_W
) && (ins
->prefixes
& PREFIX_DATA
))
10688 || ((sizeflag
& SUFFIX_ALWAYS
)
10689 && ins
->address_mode
!= mode_64bit
))
10691 *ins
->obufp
++ = (sizeflag
& DFLAG
)
10692 ? ins
->intel_syntax
? 'd' : 'l' : 'w';
10693 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10695 else if (sizeflag
& SUFFIX_ALWAYS
)
10696 *ins
->obufp
++ = 'q';
10698 else if (l
== 1 && last
[0] == 'L')
10700 if ((ins
->prefixes
& PREFIX_DATA
)
10701 || (ins
->rex
& REX_W
)
10702 || (sizeflag
& SUFFIX_ALWAYS
))
10705 if (ins
->rex
& REX_W
)
10706 *ins
->obufp
++ = 'q';
10709 if (sizeflag
& DFLAG
)
10710 *ins
->obufp
++ = ins
->intel_syntax
? 'd' : 'l';
10712 *ins
->obufp
++ = 'w';
10713 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10723 if (ins
->intel_syntax
&& !alt
)
10726 if ((ins
->need_modrm
&& ins
->modrm
.mod
!= 3 && !ins
->vex
.nd
)
10727 || (sizeflag
& SUFFIX_ALWAYS
))
10729 if (ins
->rex
& REX_W
)
10730 *ins
->obufp
++ = 'q';
10733 if (sizeflag
& DFLAG
)
10734 *ins
->obufp
++ = ins
->intel_syntax
? 'd' : 'l';
10736 *ins
->obufp
++ = 'w';
10737 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10741 else if (l
== 1 && last
[0] == 'D')
10742 *ins
->obufp
++ = ins
->vex
.w
? 'q' : 'd';
10743 else if (l
== 1 && last
[0] == 'L')
10745 if (cond
? ins
->modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
10746 : ins
->address_mode
!= mode_64bit
)
10748 if ((ins
->rex
& REX_W
))
10751 *ins
->obufp
++ = 'q';
10753 else if ((ins
->address_mode
== mode_64bit
&& cond
)
10754 || (sizeflag
& SUFFIX_ALWAYS
))
10755 *ins
->obufp
++ = ins
->intel_syntax
? 'd' : 'l';
10762 if (ins
->rex
& REX_W
)
10763 *ins
->obufp
++ = 'q';
10764 else if (sizeflag
& DFLAG
)
10766 if (ins
->intel_syntax
)
10767 *ins
->obufp
++ = 'd';
10769 *ins
->obufp
++ = 'l';
10772 *ins
->obufp
++ = 'w';
10773 if (ins
->intel_syntax
&& !p
[1]
10774 && ((ins
->rex
& REX_W
) || (sizeflag
& DFLAG
)))
10775 *ins
->obufp
++ = 'e';
10776 if (!(ins
->rex
& REX_W
))
10777 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10783 if (ins
->intel_syntax
)
10785 if (sizeflag
& SUFFIX_ALWAYS
)
10787 if (ins
->rex
& REX_W
)
10788 *ins
->obufp
++ = 'q';
10791 if (sizeflag
& DFLAG
)
10792 *ins
->obufp
++ = 'l';
10794 *ins
->obufp
++ = 'w';
10795 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10805 if (ins
->address_mode
== mode_64bit
10806 && !(ins
->prefixes
& PREFIX_ADDR
))
10808 *ins
->obufp
++ = 'a';
10809 *ins
->obufp
++ = 'b';
10810 *ins
->obufp
++ = 's';
10815 if (!ins
->vex
.evex
|| !ins
->vex
.w
)
10816 *ins
->obufp
++ = 's';
10818 oappend (ins
, "{bad}");
10828 *ins
->obufp
++ = 'v';
10837 *ins
->obufp
++ = '{';
10838 *ins
->obufp
++ = 'v';
10839 *ins
->obufp
++ = 'e';
10840 *ins
->obufp
++ = 'x';
10841 *ins
->obufp
++ = '}';
10842 *ins
->obufp
++ = ' ';
10845 if (ins
->rex
& REX_W
)
10847 *ins
->obufp
++ = 'a';
10848 *ins
->obufp
++ = 'b';
10849 *ins
->obufp
++ = 's';
10862 /* operand size flag for cwtl, cbtw */
10864 if (ins
->rex
& REX_W
)
10866 if (ins
->intel_syntax
)
10867 *ins
->obufp
++ = 'd';
10869 *ins
->obufp
++ = 'l';
10871 else if (sizeflag
& DFLAG
)
10872 *ins
->obufp
++ = 'w';
10874 *ins
->obufp
++ = 'b';
10875 if (!(ins
->rex
& REX_W
))
10876 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10880 if (!ins
->need_vex
)
10882 if (last
[0] == 'X')
10883 *ins
->obufp
++ = ins
->vex
.w
? 'd': 's';
10884 else if (last
[0] == 'B')
10885 *ins
->obufp
++ = ins
->vex
.w
? 'w': 'b';
10896 ? ins
->vex
.prefix
== DATA_PREFIX_OPCODE
10897 : ins
->prefixes
& PREFIX_DATA
)
10899 *ins
->obufp
++ = 'd';
10900 ins
->used_prefixes
|= PREFIX_DATA
;
10903 *ins
->obufp
++ = 's';
10908 if (ins
->vex
.mask_register_specifier
)
10909 ins
->illegal_masking
= true;
10911 else if (l
== 1 && last
[0] == 'X')
10913 if (!ins
->need_vex
)
10915 if (ins
->intel_syntax
10916 || ((ins
->modrm
.mod
== 3 || ins
->vex
.b
)
10917 && !(sizeflag
& SUFFIX_ALWAYS
)))
10919 switch (ins
->vex
.length
)
10922 *ins
->obufp
++ = 'x';
10925 *ins
->obufp
++ = 'y';
10928 if (!ins
->vex
.evex
)
10939 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10940 ins
->modrm
.mod
= 3;
10941 if (!ins
->intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
10942 *ins
->obufp
++ = ins
->address_mode
== mode_64bit
? 'q' : 'l';
10944 else if (l
== 1 && last
[0] == 'X')
10946 if (!ins
->vex
.evex
)
10948 if (ins
->intel_syntax
10949 || ((ins
->modrm
.mod
== 3 || ins
->vex
.b
)
10950 && !(sizeflag
& SUFFIX_ALWAYS
)))
10952 switch (ins
->vex
.length
)
10955 *ins
->obufp
++ = 'x';
10958 *ins
->obufp
++ = 'y';
10961 *ins
->obufp
++ = 'z';
10971 if (ins
->intel_syntax
)
10973 if (ins
->isa64
== intel64
&& (ins
->rex
& REX_W
))
10976 *ins
->obufp
++ = 'q';
10979 if ((ins
->prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10981 if (sizeflag
& DFLAG
)
10982 *ins
->obufp
++ = 'l';
10984 *ins
->obufp
++ = 'w';
10985 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
10994 ins
->mnemonicendp
= ins
->obufp
;
10998 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
10999 the buffer pointed to by INS->obufp has space. A style marker is made
11000 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11001 digit, followed by another STYLE_MARKER_CHAR. This function assumes
11002 that the number of styles is not greater than 16. */
11005 oappend_insert_style (instr_info
*ins
, enum disassembler_style style
)
11007 unsigned num
= (unsigned) style
;
11009 /* We currently assume that STYLE can be encoded as a single hex
11010 character. If more styles are added then this might start to fail,
11011 and we'll need to expand this code. */
11015 *ins
->obufp
++ = STYLE_MARKER_CHAR
;
11016 *ins
->obufp
++ = (num
< 10 ? ('0' + num
)
11017 : ((num
< 16) ? ('a' + (num
- 10)) : '0'));
11018 *ins
->obufp
++ = STYLE_MARKER_CHAR
;
11020 /* This final null character is not strictly necessary, after inserting a
11021 style marker we should always be inserting some additional content.
11022 However, having the buffer null terminated doesn't cost much, and make
11023 it easier to debug what's going on. Also, if we do ever forget to add
11024 any additional content after this style marker, then the buffer will
11025 still be well formed. */
11026 *ins
->obufp
= '\0';
11030 oappend_with_style (instr_info
*ins
, const char *s
,
11031 enum disassembler_style style
)
11033 oappend_insert_style (ins
, style
);
11034 ins
->obufp
= stpcpy (ins
->obufp
, s
);
11037 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11038 the style for the character as STYLE. */
11041 oappend_char_with_style (instr_info
*ins
, const char c
,
11042 enum disassembler_style style
)
11044 oappend_insert_style (ins
, style
);
11046 *ins
->obufp
= '\0';
11049 /* Like oappend_char_with_style, but always uses dis_style_text. */
11052 oappend_char (instr_info
*ins
, const char c
)
11054 oappend_char_with_style (ins
, c
, dis_style_text
);
11058 append_seg (instr_info
*ins
)
11060 /* Only print the active segment register. */
11061 if (!ins
->active_seg_prefix
)
11064 ins
->used_prefixes
|= ins
->active_seg_prefix
;
11065 switch (ins
->active_seg_prefix
)
11068 oappend_register (ins
, att_names_seg
[1]);
11071 oappend_register (ins
, att_names_seg
[3]);
11074 oappend_register (ins
, att_names_seg
[2]);
11077 oappend_register (ins
, att_names_seg
[0]);
11080 oappend_register (ins
, att_names_seg
[4]);
11083 oappend_register (ins
, att_names_seg
[5]);
11088 oappend_char (ins
, ':');
11092 print_operand_value (instr_info
*ins
, bfd_vma disp
,
11093 enum disassembler_style style
)
11097 if (ins
->address_mode
!= mode_64bit
)
11098 disp
&= 0xffffffff;
11099 sprintf (tmp
, "0x%" PRIx64
, (uint64_t) disp
);
11100 oappend_with_style (ins
, tmp
, style
);
11103 /* Like oappend, but called for immediate operands. */
11106 oappend_immediate (instr_info
*ins
, bfd_vma imm
)
11108 if (!ins
->intel_syntax
)
11109 oappend_char_with_style (ins
, '$', dis_style_immediate
);
11110 print_operand_value (ins
, imm
, dis_style_immediate
);
11113 /* Put DISP in BUF as signed hex number. */
11116 print_displacement (instr_info
*ins
, bfd_signed_vma val
)
11122 oappend_char_with_style (ins
, '-', dis_style_address_offset
);
11123 val
= (bfd_vma
) 0 - val
;
11125 /* Check for possible overflow. */
11128 switch (ins
->address_mode
)
11131 oappend_with_style (ins
, "0x8000000000000000",
11132 dis_style_address_offset
);
11135 oappend_with_style (ins
, "0x80000000",
11136 dis_style_address_offset
);
11139 oappend_with_style (ins
, "0x8000",
11140 dis_style_address_offset
);
11147 sprintf (tmp
, "0x%" PRIx64
, (int64_t) val
);
11148 oappend_with_style (ins
, tmp
, dis_style_address_offset
);
11152 intel_operand_size (instr_info
*ins
, int bytemode
, int sizeflag
)
11154 /* Check if there is a broadcast, when evex.b is not treated as evex.nd. */
11155 if (ins
->vex
.b
&& ins
->evex_type
== evex_default
)
11157 if (!ins
->vex
.no_broadcast
)
11161 case evex_half_bcst_xmmq_mode
:
11163 oappend (ins
, "QWORD BCST ");
11165 oappend (ins
, "DWORD BCST ");
11168 case evex_half_bcst_xmmqh_mode
:
11169 case evex_half_bcst_xmmqdh_mode
:
11170 oappend (ins
, "WORD BCST ");
11173 ins
->vex
.no_broadcast
= true;
11183 oappend (ins
, "BYTE PTR ");
11188 oappend (ins
, "WORD PTR ");
11191 if (ins
->address_mode
== mode_64bit
&& ins
->isa64
== intel64
)
11193 oappend (ins
, "QWORD PTR ");
11196 /* Fall through. */
11198 if (ins
->address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
)
11199 || (ins
->rex
& REX_W
)))
11201 oappend (ins
, "QWORD PTR ");
11204 /* Fall through. */
11209 if (ins
->rex
& REX_W
)
11210 oappend (ins
, "QWORD PTR ");
11211 else if (bytemode
== dq_mode
)
11212 oappend (ins
, "DWORD PTR ");
11215 if (sizeflag
& DFLAG
)
11216 oappend (ins
, "DWORD PTR ");
11218 oappend (ins
, "WORD PTR ");
11219 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
11223 if ((ins
->rex
& REX_W
) || (sizeflag
& DFLAG
))
11224 *ins
->obufp
++ = 'D';
11225 oappend (ins
, "WORD PTR ");
11226 if (!(ins
->rex
& REX_W
))
11227 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
11230 if (sizeflag
& DFLAG
)
11231 oappend (ins
, "QWORD PTR ");
11233 oappend (ins
, "DWORD PTR ");
11234 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
11237 if (!(sizeflag
& DFLAG
) && ins
->isa64
== intel64
)
11238 oappend (ins
, "WORD PTR ");
11240 oappend (ins
, "DWORD PTR ");
11241 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
11245 oappend (ins
, "DWORD PTR ");
11249 oappend (ins
, "QWORD PTR ");
11252 if (ins
->address_mode
== mode_64bit
)
11253 oappend (ins
, "QWORD PTR ");
11255 oappend (ins
, "DWORD PTR ");
11258 if (sizeflag
& DFLAG
)
11259 oappend (ins
, "FWORD PTR ");
11261 oappend (ins
, "DWORD PTR ");
11262 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
11265 oappend (ins
, "TBYTE PTR ");
11270 case evex_x_gscat_mode
:
11271 case evex_x_nobcst_mode
:
11275 switch (ins
->vex
.length
)
11278 oappend (ins
, "XMMWORD PTR ");
11281 oappend (ins
, "YMMWORD PTR ");
11284 oappend (ins
, "ZMMWORD PTR ");
11291 oappend (ins
, "XMMWORD PTR ");
11294 oappend (ins
, "XMMWORD PTR ");
11297 oappend (ins
, "YMMWORD PTR ");
11300 case evex_half_bcst_xmmqh_mode
:
11301 case evex_half_bcst_xmmq_mode
:
11302 switch (ins
->vex
.length
)
11306 oappend (ins
, "QWORD PTR ");
11309 oappend (ins
, "XMMWORD PTR ");
11312 oappend (ins
, "YMMWORD PTR ");
11319 if (!ins
->need_vex
)
11322 switch (ins
->vex
.length
)
11325 oappend (ins
, "WORD PTR ");
11328 oappend (ins
, "DWORD PTR ");
11331 oappend (ins
, "QWORD PTR ");
11338 case evex_half_bcst_xmmqdh_mode
:
11339 if (!ins
->need_vex
)
11342 switch (ins
->vex
.length
)
11345 oappend (ins
, "DWORD PTR ");
11348 oappend (ins
, "QWORD PTR ");
11351 oappend (ins
, "XMMWORD PTR ");
11358 if (!ins
->need_vex
)
11361 switch (ins
->vex
.length
)
11364 oappend (ins
, "QWORD PTR ");
11367 oappend (ins
, "YMMWORD PTR ");
11370 oappend (ins
, "ZMMWORD PTR ");
11377 oappend (ins
, "OWORD PTR ");
11379 case vex_vsib_d_w_dq_mode
:
11380 case vex_vsib_q_w_dq_mode
:
11381 if (!ins
->need_vex
)
11384 oappend (ins
, "QWORD PTR ");
11386 oappend (ins
, "DWORD PTR ");
11389 if (!ins
->need_vex
|| ins
->vex
.length
!= 128)
11392 oappend (ins
, "DWORD PTR ");
11394 oappend (ins
, "BYTE PTR ");
11397 if (!ins
->need_vex
)
11400 oappend (ins
, "QWORD PTR ");
11402 oappend (ins
, "WORD PTR ");
11412 print_register (instr_info
*ins
, unsigned int reg
, unsigned int rexmask
,
11413 int bytemode
, int sizeflag
)
11415 const char (*names
)[8];
11417 /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11418 as the consumer will inspect it only for the destination operand. */
11419 if (bytemode
!= mask_mode
&& ins
->vex
.mask_register_specifier
)
11420 ins
->illegal_masking
= true;
11422 USED_REX (rexmask
);
11423 if (ins
->rex
& rexmask
)
11425 if (ins
->rex2
& rexmask
)
11434 if (ins
->rex
|| ins
->rex2
)
11435 names
= att_names8rex
;
11437 names
= att_names8
;
11440 names
= att_names16
;
11445 names
= att_names32
;
11448 names
= att_names64
;
11452 names
= ins
->address_mode
== mode_64bit
? att_names64
: att_names32
;
11455 case bnd_swap_mode
:
11458 oappend (ins
, "(bad)");
11461 names
= att_names_bnd
;
11464 if (ins
->address_mode
== mode_64bit
&& ins
->isa64
== intel64
)
11466 names
= att_names64
;
11469 /* Fall through. */
11471 if (ins
->address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
)
11472 || (ins
->rex
& REX_W
)))
11474 names
= att_names64
;
11478 /* Fall through. */
11483 if (ins
->rex
& REX_W
)
11484 names
= att_names64
;
11485 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11486 names
= att_names32
;
11489 if (sizeflag
& DFLAG
)
11490 names
= att_names32
;
11492 names
= att_names16
;
11493 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
11497 if (!(sizeflag
& DFLAG
) && ins
->isa64
== intel64
)
11498 names
= att_names16
;
11500 names
= att_names32
;
11501 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
11504 names
= (ins
->address_mode
== mode_64bit
11505 ? att_names64
: att_names32
);
11506 if (!(ins
->prefixes
& PREFIX_ADDR
))
11507 names
= (ins
->address_mode
== mode_16bit
11508 ? att_names16
: names
);
11511 /* Remove "addr16/addr32". */
11512 ins
->all_prefixes
[ins
->last_addr_prefix
] = 0;
11513 names
= (ins
->address_mode
!= mode_32bit
11514 ? att_names32
: att_names16
);
11515 ins
->used_prefixes
|= PREFIX_ADDR
;
11522 oappend (ins
, "(bad)");
11525 names
= att_names_mask
;
11530 oappend (ins
, INTERNAL_DISASSEMBLER_ERROR
);
11533 oappend_register (ins
, names
[reg
]);
11537 get8s (instr_info
*ins
, bfd_vma
*res
)
11539 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
11541 *res
= ((bfd_vma
) *ins
->codep
++ ^ 0x80) - 0x80;
11546 get16 (instr_info
*ins
, bfd_vma
*res
)
11548 if (!fetch_code (ins
->info
, ins
->codep
+ 2))
11550 *res
= *ins
->codep
++;
11551 *res
|= (bfd_vma
) *ins
->codep
++ << 8;
11556 get16s (instr_info
*ins
, bfd_vma
*res
)
11558 if (!get16 (ins
, res
))
11560 *res
= (*res
^ 0x8000) - 0x8000;
11565 get32 (instr_info
*ins
, bfd_vma
*res
)
11567 if (!fetch_code (ins
->info
, ins
->codep
+ 4))
11569 *res
= *ins
->codep
++;
11570 *res
|= (bfd_vma
) *ins
->codep
++ << 8;
11571 *res
|= (bfd_vma
) *ins
->codep
++ << 16;
11572 *res
|= (bfd_vma
) *ins
->codep
++ << 24;
11577 get32s (instr_info
*ins
, bfd_vma
*res
)
11579 if (!get32 (ins
, res
))
11582 *res
= (*res
^ ((bfd_vma
) 1 << 31)) - ((bfd_vma
) 1 << 31);
11588 get64 (instr_info
*ins
, uint64_t *res
)
11593 if (!fetch_code (ins
->info
, ins
->codep
+ 8))
11596 a
|= (unsigned int) *ins
->codep
++ << 8;
11597 a
|= (unsigned int) *ins
->codep
++ << 16;
11598 a
|= (unsigned int) *ins
->codep
++ << 24;
11600 b
|= (unsigned int) *ins
->codep
++ << 8;
11601 b
|= (unsigned int) *ins
->codep
++ << 16;
11602 b
|= (unsigned int) *ins
->codep
++ << 24;
11603 *res
= a
+ ((uint64_t) b
<< 32);
11608 set_op (instr_info
*ins
, bfd_vma op
, bool riprel
)
11610 ins
->op_index
[ins
->op_ad
] = ins
->op_ad
;
11611 if (ins
->address_mode
== mode_64bit
)
11612 ins
->op_address
[ins
->op_ad
] = op
;
11613 else /* Mask to get a 32-bit address. */
11614 ins
->op_address
[ins
->op_ad
] = op
& 0xffffffff;
11615 ins
->op_riprel
[ins
->op_ad
] = riprel
;
11619 BadOp (instr_info
*ins
)
11621 /* Throw away prefixes and 1st. opcode byte. */
11622 struct dis_private
*priv
= ins
->info
->private_data
;
11624 ins
->codep
= priv
->the_buffer
+ ins
->nr_prefixes
+ ins
->need_vex
+ 1;
11625 ins
->obufp
= stpcpy (ins
->obufp
, "(bad)");
11630 OP_Skip_MODRM (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
11631 int sizeflag ATTRIBUTE_UNUSED
)
11633 if (ins
->modrm
.mod
!= 3)
11634 return BadOp (ins
);
11636 /* Skip mod/rm byte. */
11639 ins
->has_skipped_modrm
= true;
11644 OP_E_memory (instr_info
*ins
, int bytemode
, int sizeflag
)
11646 int add
= (ins
->rex
& REX_B
) ? 8 : 0;
11650 add
+= (ins
->rex2
& REX_B
) ? 16 : 0;
11652 /* Handles EVEX other than APX EVEX-promoted instructions. */
11653 if (ins
->vex
.evex
&& ins
->evex_type
== evex_default
)
11656 /* Zeroing-masking is invalid for memory destinations. Set the flag
11657 uniformly, as the consumer will inspect it only for the destination
11659 if (ins
->vex
.zeroing
)
11660 ins
->illegal_masking
= true;
11674 if (ins
->address_mode
!= mode_64bit
)
11682 case vex_vsib_d_w_dq_mode
:
11683 case vex_vsib_q_w_dq_mode
:
11684 case evex_x_gscat_mode
:
11685 shift
= ins
->vex
.w
? 3 : 2;
11688 case evex_half_bcst_xmmqh_mode
:
11689 case evex_half_bcst_xmmqdh_mode
:
11692 shift
= ins
->vex
.w
? 2 : 1;
11695 /* Fall through. */
11697 case evex_half_bcst_xmmq_mode
:
11700 shift
= ins
->vex
.w
? 3 : 2;
11703 /* Fall through. */
11708 case evex_x_nobcst_mode
:
11710 switch (ins
->vex
.length
)
11724 /* Make necessary corrections to shift for modes that need it. */
11725 if (bytemode
== xmmq_mode
11726 || bytemode
== evex_half_bcst_xmmqh_mode
11727 || bytemode
== evex_half_bcst_xmmq_mode
11728 || (bytemode
== ymmq_mode
&& ins
->vex
.length
== 128))
11730 else if (bytemode
== xmmqd_mode
11731 || bytemode
== evex_half_bcst_xmmqdh_mode
)
11733 else if (bytemode
== xmmdw_mode
)
11747 shift
= ins
->vex
.w
? 1 : 0;
11757 if (ins
->intel_syntax
)
11758 intel_operand_size (ins
, bytemode
, sizeflag
);
11761 if ((sizeflag
& AFLAG
) || ins
->address_mode
== mode_64bit
)
11763 /* 32/64 bit address mode */
11772 int addr32flag
= !((sizeflag
& AFLAG
)
11773 || bytemode
== v_bnd_mode
11774 || bytemode
== v_bndmk_mode
11775 || bytemode
== bnd_mode
11776 || bytemode
== bnd_swap_mode
);
11777 bool check_gather
= false;
11778 const char (*indexes
)[8] = NULL
;
11781 base
= ins
->modrm
.rm
;
11785 vindex
= ins
->sib
.index
;
11787 if (ins
->rex
& REX_X
)
11791 case vex_vsib_d_w_dq_mode
:
11792 case vex_vsib_q_w_dq_mode
:
11793 if (!ins
->need_vex
)
11797 /* S/G EVEX insns require EVEX.X4 not to be set. */
11798 if (ins
->rex2
& REX_X
)
11800 oappend (ins
, "(bad)");
11806 check_gather
= ins
->obufp
== ins
->op_out
[1];
11809 switch (ins
->vex
.length
)
11812 indexes
= att_names_xmm
;
11816 || bytemode
== vex_vsib_q_w_dq_mode
)
11817 indexes
= att_names_ymm
;
11819 indexes
= att_names_xmm
;
11823 || bytemode
== vex_vsib_q_w_dq_mode
)
11824 indexes
= att_names_zmm
;
11826 indexes
= att_names_ymm
;
11833 if (ins
->rex2
& REX_X
)
11837 indexes
= ins
->address_mode
== mode_64bit
&& !addr32flag
11838 ? att_names64
: att_names32
;
11841 scale
= ins
->sib
.scale
;
11842 base
= ins
->sib
.base
;
11847 /* Check for mandatory SIB. */
11848 if (bytemode
== vex_vsib_d_w_dq_mode
11849 || bytemode
== vex_vsib_q_w_dq_mode
11850 || bytemode
== vex_sibmem_mode
)
11852 oappend (ins
, "(bad)");
11856 rbase
= base
+ add
;
11858 switch (ins
->modrm
.mod
)
11864 if (ins
->address_mode
== mode_64bit
&& !ins
->has_sib
)
11866 if (!get32s (ins
, &disp
))
11868 if (riprel
&& bytemode
== v_bndmk_mode
)
11870 oappend (ins
, "(bad)");
11876 if (!get8s (ins
, &disp
))
11878 if (ins
->vex
.evex
&& shift
> 0)
11882 if (!get32s (ins
, &disp
))
11892 && ins
->address_mode
!= mode_16bit
)
11894 if (ins
->address_mode
== mode_64bit
)
11898 /* Without base nor index registers, zero-extend the
11899 lower 32-bit displacement to 64 bits. */
11900 disp
&= 0xffffffff;
11907 /* In 32-bit mode, we need index register to tell [offset]
11908 from [eiz*1 + offset]. */
11913 havedisp
= (havebase
11915 || (ins
->has_sib
&& (indexes
|| scale
!= 0)));
11917 if (!ins
->intel_syntax
)
11918 if (ins
->modrm
.mod
!= 0 || base
== 5)
11920 if (havedisp
|| riprel
)
11921 print_displacement (ins
, disp
);
11923 print_operand_value (ins
, disp
, dis_style_address_offset
);
11926 set_op (ins
, disp
, true);
11927 oappend_char (ins
, '(');
11928 oappend_with_style (ins
, !addr32flag
? "%rip" : "%eip",
11929 dis_style_register
);
11930 oappend_char (ins
, ')');
11934 if ((havebase
|| indexes
|| needindex
|| needaddr32
|| riprel
)
11935 && (ins
->address_mode
!= mode_64bit
11936 || ((bytemode
!= v_bnd_mode
)
11937 && (bytemode
!= v_bndmk_mode
)
11938 && (bytemode
!= bnd_mode
)
11939 && (bytemode
!= bnd_swap_mode
))))
11940 ins
->used_prefixes
|= PREFIX_ADDR
;
11942 if (havedisp
|| (ins
->intel_syntax
&& riprel
))
11944 oappend_char (ins
, ins
->open_char
);
11945 if (ins
->intel_syntax
&& riprel
)
11947 set_op (ins
, disp
, true);
11948 oappend_with_style (ins
, !addr32flag
? "rip" : "eip",
11949 dis_style_register
);
11954 (ins
->address_mode
== mode_64bit
&& !addr32flag
11955 ? att_names64
: att_names32
)[rbase
]);
11958 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11959 print index to tell base + index from base. */
11963 || (havebase
&& base
!= ESP_REG_NUM
))
11965 if (!ins
->intel_syntax
|| havebase
)
11966 oappend_char (ins
, ins
->separator_char
);
11969 if (ins
->address_mode
== mode_64bit
|| vindex
< 16)
11970 oappend_register (ins
, indexes
[vindex
]);
11972 oappend (ins
, "(bad)");
11975 oappend_register (ins
,
11976 ins
->address_mode
== mode_64bit
11981 oappend_char (ins
, ins
->scale_char
);
11982 oappend_char_with_style (ins
, '0' + (1 << scale
),
11983 dis_style_immediate
);
11986 if (ins
->intel_syntax
11987 && (disp
|| ins
->modrm
.mod
!= 0 || base
== 5))
11989 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
11990 oappend_char (ins
, '+');
11992 print_displacement (ins
, disp
);
11994 print_operand_value (ins
, disp
, dis_style_address_offset
);
11997 oappend_char (ins
, ins
->close_char
);
12001 /* Both XMM/YMM/ZMM registers must be distinct. */
12002 int modrm_reg
= ins
->modrm
.reg
;
12004 if (ins
->rex
& REX_R
)
12006 if (ins
->rex2
& REX_R
)
12008 if (vindex
== modrm_reg
)
12009 oappend (ins
, "/(bad)");
12012 else if (ins
->intel_syntax
)
12014 if (ins
->modrm
.mod
!= 0 || base
== 5)
12016 if (!ins
->active_seg_prefix
)
12018 oappend_register (ins
, att_names_seg
[ds_reg
- es_reg
]);
12019 oappend (ins
, ":");
12021 print_operand_value (ins
, disp
, dis_style_text
);
12025 else if (bytemode
== v_bnd_mode
12026 || bytemode
== v_bndmk_mode
12027 || bytemode
== bnd_mode
12028 || bytemode
== bnd_swap_mode
12029 || bytemode
== vex_vsib_d_w_dq_mode
12030 || bytemode
== vex_vsib_q_w_dq_mode
)
12032 oappend (ins
, "(bad)");
12037 /* 16 bit address mode */
12040 ins
->used_prefixes
|= ins
->prefixes
& PREFIX_ADDR
;
12041 switch (ins
->modrm
.mod
)
12044 if (ins
->modrm
.rm
== 6)
12047 if (!get16s (ins
, &disp
))
12052 if (!get8s (ins
, &disp
))
12054 if (ins
->vex
.evex
&& shift
> 0)
12059 if (!ins
->intel_syntax
)
12060 if (ins
->modrm
.mod
!= 0 || ins
->modrm
.rm
== 6)
12061 print_displacement (ins
, disp
);
12063 if (ins
->modrm
.mod
!= 0 || ins
->modrm
.rm
!= 6)
12065 oappend_char (ins
, ins
->open_char
);
12066 oappend (ins
, ins
->intel_syntax
? intel_index16
[ins
->modrm
.rm
]
12067 : att_index16
[ins
->modrm
.rm
]);
12068 if (ins
->intel_syntax
12069 && (disp
|| ins
->modrm
.mod
!= 0 || ins
->modrm
.rm
== 6))
12071 if ((bfd_signed_vma
) disp
>= 0)
12072 oappend_char (ins
, '+');
12073 print_displacement (ins
, disp
);
12076 oappend_char (ins
, ins
->close_char
);
12078 else if (ins
->intel_syntax
)
12080 if (!ins
->active_seg_prefix
)
12082 oappend_register (ins
, att_names_seg
[ds_reg
- es_reg
]);
12083 oappend (ins
, ":");
12085 print_operand_value (ins
, disp
& 0xffff, dis_style_text
);
12088 if (ins
->vex
.b
&& ins
->evex_type
== evex_default
)
12090 ins
->evex_used
|= EVEX_b_used
;
12092 /* Broadcast can only ever be valid for memory sources. */
12093 if (ins
->obufp
== ins
->op_out
[0])
12094 ins
->vex
.no_broadcast
= true;
12096 if (!ins
->vex
.no_broadcast
12097 && (!ins
->intel_syntax
|| !(ins
->evex_used
& EVEX_len_used
)))
12099 if (bytemode
== xh_mode
)
12101 switch (ins
->vex
.length
)
12104 oappend (ins
, "{1to8}");
12107 oappend (ins
, "{1to16}");
12110 oappend (ins
, "{1to32}");
12116 else if (bytemode
== q_mode
12117 || bytemode
== ymmq_mode
)
12118 ins
->vex
.no_broadcast
= true;
12119 else if (ins
->vex
.w
12120 || bytemode
== evex_half_bcst_xmmqdh_mode
12121 || bytemode
== evex_half_bcst_xmmq_mode
)
12123 switch (ins
->vex
.length
)
12126 oappend (ins
, "{1to2}");
12129 oappend (ins
, "{1to4}");
12132 oappend (ins
, "{1to8}");
12138 else if (bytemode
== x_mode
12139 || bytemode
== evex_half_bcst_xmmqh_mode
)
12141 switch (ins
->vex
.length
)
12144 oappend (ins
, "{1to4}");
12147 oappend (ins
, "{1to8}");
12150 oappend (ins
, "{1to16}");
12157 ins
->vex
.no_broadcast
= true;
12159 if (ins
->vex
.no_broadcast
)
12160 oappend (ins
, "{bad}");
12167 OP_E (instr_info
*ins
, int bytemode
, int sizeflag
)
12169 /* Skip mod/rm byte. */
12171 if (!ins
->has_skipped_modrm
)
12174 ins
->has_skipped_modrm
= true;
12177 if (ins
->modrm
.mod
== 3)
12179 if ((sizeflag
& SUFFIX_ALWAYS
)
12180 && (bytemode
== b_swap_mode
12181 || bytemode
== bnd_swap_mode
12182 || bytemode
== v_swap_mode
))
12183 swap_operand (ins
);
12185 print_register (ins
, ins
->modrm
.rm
, REX_B
, bytemode
, sizeflag
);
12189 /* Masking is invalid for insns with GPR-like memory destination. Set the
12190 flag uniformly, as the consumer will inspect it only for the destination
12192 if (ins
->vex
.mask_register_specifier
)
12193 ins
->illegal_masking
= true;
12195 return OP_E_memory (ins
, bytemode
, sizeflag
);
12199 OP_indirE (instr_info
*ins
, int bytemode
, int sizeflag
)
12201 if (ins
->modrm
.mod
== 3 && bytemode
== f_mode
)
12202 /* bad lcall/ljmp */
12203 return BadOp (ins
);
12204 if (!ins
->intel_syntax
)
12205 oappend (ins
, "*");
12206 return OP_E (ins
, bytemode
, sizeflag
);
12210 OP_G (instr_info
*ins
, int bytemode
, int sizeflag
)
12212 print_register (ins
, ins
->modrm
.reg
, REX_R
, bytemode
, sizeflag
);
12217 OP_REG (instr_info
*ins
, int code
, int sizeflag
)
12224 case es_reg
: case ss_reg
: case cs_reg
:
12225 case ds_reg
: case fs_reg
: case gs_reg
:
12226 oappend_register (ins
, att_names_seg
[code
- es_reg
]);
12231 if (ins
->rex
& REX_B
)
12233 if (ins
->rex2
& REX_B
)
12238 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12239 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12240 s
= att_names16
[code
- ax_reg
+ add
];
12242 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12244 /* Fall through. */
12245 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12247 s
= att_names8rex
[code
- al_reg
+ add
];
12249 s
= att_names8
[code
- al_reg
];
12251 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12252 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12253 if (ins
->address_mode
== mode_64bit
12254 && ((sizeflag
& DFLAG
) || (ins
->rex
& REX_W
)))
12256 s
= att_names64
[code
- rAX_reg
+ add
];
12259 code
+= eAX_reg
- rAX_reg
;
12260 /* Fall through. */
12261 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12262 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12264 if (ins
->rex
& REX_W
)
12265 s
= att_names64
[code
- eAX_reg
+ add
];
12268 if (sizeflag
& DFLAG
)
12269 s
= att_names32
[code
- eAX_reg
+ add
];
12271 s
= att_names16
[code
- eAX_reg
+ add
];
12272 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12276 oappend (ins
, INTERNAL_DISASSEMBLER_ERROR
);
12279 oappend_register (ins
, s
);
12284 OP_IMREG (instr_info
*ins
, int code
, int sizeflag
)
12291 if (!ins
->intel_syntax
)
12293 oappend (ins
, "(%dx)");
12296 s
= att_names16
[dx_reg
- ax_reg
];
12298 case al_reg
: case cl_reg
:
12299 s
= att_names8
[code
- al_reg
];
12303 if (ins
->rex
& REX_W
)
12308 /* Fall through. */
12309 case z_mode_ax_reg
:
12310 if ((ins
->rex
& REX_W
) || (sizeflag
& DFLAG
))
12314 if (!(ins
->rex
& REX_W
))
12315 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12318 oappend (ins
, INTERNAL_DISASSEMBLER_ERROR
);
12321 oappend_register (ins
, s
);
12326 OP_I (instr_info
*ins
, int bytemode
, int sizeflag
)
12333 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
12335 op
= *ins
->codep
++;
12339 if (ins
->rex
& REX_W
)
12341 if (!get32s (ins
, &op
))
12346 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12347 if (sizeflag
& DFLAG
)
12350 if (!get32 (ins
, &op
))
12355 /* Fall through. */
12357 if (!get16 (ins
, &op
))
12363 if (ins
->intel_syntax
)
12364 oappend (ins
, "1");
12366 oappend (ins
, "$1");
12369 oappend (ins
, INTERNAL_DISASSEMBLER_ERROR
);
12373 oappend_immediate (ins
, op
);
12378 OP_I64 (instr_info
*ins
, int bytemode
, int sizeflag
)
12382 if (bytemode
!= v_mode
|| ins
->address_mode
!= mode_64bit
12383 || !(ins
->rex
& REX_W
))
12384 return OP_I (ins
, bytemode
, sizeflag
);
12388 if (!get64 (ins
, &op
))
12391 oappend_immediate (ins
, op
);
12396 OP_sI (instr_info
*ins
, int bytemode
, int sizeflag
)
12404 if (!get8s (ins
, &op
))
12406 if (bytemode
== b_T_mode
)
12408 if (ins
->address_mode
!= mode_64bit
12409 || !((sizeflag
& DFLAG
) || (ins
->rex
& REX_W
)))
12411 /* The operand-size prefix is overridden by a REX prefix. */
12412 if ((sizeflag
& DFLAG
) || (ins
->rex
& REX_W
))
12420 if (!(ins
->rex
& REX_W
))
12422 if (sizeflag
& DFLAG
)
12430 /* The operand-size prefix is overridden by a REX prefix. */
12431 if (!(sizeflag
& DFLAG
) && !(ins
->rex
& REX_W
))
12433 if (!get16 (ins
, &op
))
12436 else if (!get32s (ins
, &op
))
12440 oappend (ins
, INTERNAL_DISASSEMBLER_ERROR
);
12444 oappend_immediate (ins
, op
);
12449 OP_J (instr_info
*ins
, int bytemode
, int sizeflag
)
12453 bfd_vma segment
= 0;
12458 if (!get8s (ins
, &disp
))
12463 if ((sizeflag
& DFLAG
)
12464 || (ins
->address_mode
== mode_64bit
12465 && ((ins
->isa64
== intel64
&& bytemode
!= dqw_mode
)
12466 || (ins
->rex
& REX_W
))))
12468 if (!get32s (ins
, &disp
))
12473 if (!get16s (ins
, &disp
))
12475 /* In 16bit mode, address is wrapped around at 64k within
12476 the same segment. Otherwise, a data16 prefix on a jump
12477 instruction means that the pc is masked to 16 bits after
12478 the displacement is added! */
12480 if ((ins
->prefixes
& PREFIX_DATA
) == 0)
12481 segment
= ((ins
->start_pc
+ (ins
->codep
- ins
->start_codep
))
12482 & ~((bfd_vma
) 0xffff));
12484 if (ins
->address_mode
!= mode_64bit
12485 || (ins
->isa64
!= intel64
&& !(ins
->rex
& REX_W
)))
12486 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12489 oappend (ins
, INTERNAL_DISASSEMBLER_ERROR
);
12492 disp
= ((ins
->start_pc
+ (ins
->codep
- ins
->start_codep
) + disp
) & mask
)
12494 set_op (ins
, disp
, false);
12495 print_operand_value (ins
, disp
, dis_style_text
);
12500 OP_SEG (instr_info
*ins
, int bytemode
, int sizeflag
)
12502 if (bytemode
== w_mode
)
12504 oappend_register (ins
, att_names_seg
[ins
->modrm
.reg
]);
12507 return OP_E (ins
, ins
->modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12511 OP_DIR (instr_info
*ins
, int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12513 bfd_vma seg
, offset
;
12517 if (sizeflag
& DFLAG
)
12519 if (!get32 (ins
, &offset
))
12522 else if (!get16 (ins
, &offset
))
12524 if (!get16 (ins
, &seg
))
12526 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12528 res
= snprintf (scratch
, ARRAY_SIZE (scratch
),
12529 ins
->intel_syntax
? "0x%x:0x%x" : "$0x%x,$0x%x",
12530 (unsigned) seg
, (unsigned) offset
);
12531 if (res
< 0 || (size_t) res
>= ARRAY_SIZE (scratch
))
12533 oappend (ins
, scratch
);
12538 OP_OFF (instr_info
*ins
, int bytemode
, int sizeflag
)
12542 if (ins
->intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12543 intel_operand_size (ins
, bytemode
, sizeflag
);
12546 if ((sizeflag
& AFLAG
) || ins
->address_mode
== mode_64bit
)
12548 if (!get32 (ins
, &off
))
12553 if (!get16 (ins
, &off
))
12557 if (ins
->intel_syntax
)
12559 if (!ins
->active_seg_prefix
)
12561 oappend_register (ins
, att_names_seg
[ds_reg
- es_reg
]);
12562 oappend (ins
, ":");
12565 print_operand_value (ins
, off
, dis_style_address_offset
);
12570 OP_OFF64 (instr_info
*ins
, int bytemode
, int sizeflag
)
12574 if (ins
->address_mode
!= mode_64bit
12575 || (ins
->prefixes
& PREFIX_ADDR
))
12576 return OP_OFF (ins
, bytemode
, sizeflag
);
12578 if (ins
->intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12579 intel_operand_size (ins
, bytemode
, sizeflag
);
12582 if (!get64 (ins
, &off
))
12585 if (ins
->intel_syntax
)
12587 if (!ins
->active_seg_prefix
)
12589 oappend_register (ins
, att_names_seg
[ds_reg
- es_reg
]);
12590 oappend (ins
, ":");
12593 print_operand_value (ins
, off
, dis_style_address_offset
);
12598 ptr_reg (instr_info
*ins
, int code
, int sizeflag
)
12602 *ins
->obufp
++ = ins
->open_char
;
12603 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_ADDR
);
12604 if (ins
->address_mode
== mode_64bit
)
12606 if (!(sizeflag
& AFLAG
))
12607 s
= att_names32
[code
- eAX_reg
];
12609 s
= att_names64
[code
- eAX_reg
];
12611 else if (sizeflag
& AFLAG
)
12612 s
= att_names32
[code
- eAX_reg
];
12614 s
= att_names16
[code
- eAX_reg
];
12615 oappend_register (ins
, s
);
12616 oappend_char (ins
, ins
->close_char
);
12620 OP_ESreg (instr_info
*ins
, int code
, int sizeflag
)
12622 if (ins
->intel_syntax
)
12624 switch (ins
->codep
[-1])
12626 case 0x6d: /* insw/insl */
12627 intel_operand_size (ins
, z_mode
, sizeflag
);
12629 case 0xa5: /* movsw/movsl/movsq */
12630 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12631 case 0xab: /* stosw/stosl */
12632 case 0xaf: /* scasw/scasl */
12633 intel_operand_size (ins
, v_mode
, sizeflag
);
12636 intel_operand_size (ins
, b_mode
, sizeflag
);
12639 oappend_register (ins
, att_names_seg
[0]);
12640 oappend_char (ins
, ':');
12641 ptr_reg (ins
, code
, sizeflag
);
12646 OP_DSreg (instr_info
*ins
, int code
, int sizeflag
)
12648 if (ins
->intel_syntax
)
12650 switch (ins
->codep
[-1])
12652 case 0x6f: /* outsw/outsl */
12653 intel_operand_size (ins
, z_mode
, sizeflag
);
12655 case 0xa5: /* movsw/movsl/movsq */
12656 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12657 case 0xad: /* lodsw/lodsl/lodsq */
12658 intel_operand_size (ins
, v_mode
, sizeflag
);
12661 intel_operand_size (ins
, b_mode
, sizeflag
);
12664 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12665 default segment register DS is printed. */
12666 if (!ins
->active_seg_prefix
)
12667 ins
->active_seg_prefix
= PREFIX_DS
;
12669 ptr_reg (ins
, code
, sizeflag
);
12674 OP_C (instr_info
*ins
, int dummy ATTRIBUTE_UNUSED
,
12675 int sizeflag ATTRIBUTE_UNUSED
)
12680 if (ins
->rex
& REX_R
)
12685 else if (ins
->address_mode
!= mode_64bit
&& (ins
->prefixes
& PREFIX_LOCK
))
12687 ins
->all_prefixes
[ins
->last_lock_prefix
] = 0;
12688 ins
->used_prefixes
|= PREFIX_LOCK
;
12693 res
= snprintf (scratch
, ARRAY_SIZE (scratch
), "%%cr%d",
12694 ins
->modrm
.reg
+ add
);
12695 if (res
< 0 || (size_t) res
>= ARRAY_SIZE (scratch
))
12697 oappend_register (ins
, scratch
);
12702 OP_D (instr_info
*ins
, int dummy ATTRIBUTE_UNUSED
,
12703 int sizeflag ATTRIBUTE_UNUSED
)
12709 if (ins
->rex
& REX_R
)
12713 res
= snprintf (scratch
, ARRAY_SIZE (scratch
),
12714 ins
->intel_syntax
? "dr%d" : "%%db%d",
12715 ins
->modrm
.reg
+ add
);
12716 if (res
< 0 || (size_t) res
>= ARRAY_SIZE (scratch
))
12718 oappend (ins
, scratch
);
12723 OP_T (instr_info
*ins
, int dummy ATTRIBUTE_UNUSED
,
12724 int sizeflag ATTRIBUTE_UNUSED
)
12729 res
= snprintf (scratch
, ARRAY_SIZE (scratch
), "%%tr%d", ins
->modrm
.reg
);
12730 if (res
< 0 || (size_t) res
>= ARRAY_SIZE (scratch
))
12732 oappend_register (ins
, scratch
);
12737 OP_MMX (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
12738 int sizeflag ATTRIBUTE_UNUSED
)
12740 int reg
= ins
->modrm
.reg
;
12741 const char (*names
)[8];
12743 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12744 if (ins
->prefixes
& PREFIX_DATA
)
12746 names
= att_names_xmm
;
12748 if (ins
->rex
& REX_R
)
12752 names
= att_names_mm
;
12753 oappend_register (ins
, names
[reg
]);
12758 print_vector_reg (instr_info
*ins
, unsigned int reg
, int bytemode
)
12760 const char (*names
)[8];
12762 if (bytemode
== xmmq_mode
12763 || bytemode
== evex_half_bcst_xmmqh_mode
12764 || bytemode
== evex_half_bcst_xmmq_mode
)
12766 switch (ins
->vex
.length
)
12771 names
= att_names_xmm
;
12774 names
= att_names_ymm
;
12775 ins
->evex_used
|= EVEX_len_used
;
12781 else if (bytemode
== ymm_mode
)
12782 names
= att_names_ymm
;
12783 else if (bytemode
== tmm_mode
)
12787 oappend (ins
, "(bad)");
12790 names
= att_names_tmm
;
12792 else if (ins
->need_vex
12793 && bytemode
!= xmm_mode
12794 && bytemode
!= scalar_mode
12795 && bytemode
!= xmmdw_mode
12796 && bytemode
!= xmmqd_mode
12797 && bytemode
!= evex_half_bcst_xmmqdh_mode
12798 && bytemode
!= w_swap_mode
12799 && bytemode
!= b_mode
12800 && bytemode
!= w_mode
12801 && bytemode
!= d_mode
12802 && bytemode
!= q_mode
)
12804 ins
->evex_used
|= EVEX_len_used
;
12805 switch (ins
->vex
.length
)
12808 names
= att_names_xmm
;
12812 || bytemode
!= vex_vsib_q_w_dq_mode
)
12813 names
= att_names_ymm
;
12815 names
= att_names_xmm
;
12819 || bytemode
!= vex_vsib_q_w_dq_mode
)
12820 names
= att_names_zmm
;
12822 names
= att_names_ymm
;
12829 names
= att_names_xmm
;
12830 oappend_register (ins
, names
[reg
]);
12834 OP_XMM (instr_info
*ins
, int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
12836 unsigned int reg
= ins
->modrm
.reg
;
12839 if (ins
->rex
& REX_R
)
12843 if (ins
->rex2
& REX_R
)
12847 if (bytemode
== tmm_mode
)
12848 ins
->modrm
.reg
= reg
;
12849 else if (bytemode
== scalar_mode
)
12850 ins
->vex
.no_broadcast
= true;
12852 print_vector_reg (ins
, reg
, bytemode
);
12857 OP_EM (instr_info
*ins
, int bytemode
, int sizeflag
)
12860 const char (*names
)[8];
12862 if (ins
->modrm
.mod
!= 3)
12864 if (ins
->intel_syntax
12865 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
12867 bytemode
= (ins
->prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12868 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12870 return OP_E (ins
, bytemode
, sizeflag
);
12873 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
12874 swap_operand (ins
);
12876 /* Skip mod/rm byte. */
12879 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12880 reg
= ins
->modrm
.rm
;
12881 if (ins
->prefixes
& PREFIX_DATA
)
12883 names
= att_names_xmm
;
12885 if (ins
->rex
& REX_B
)
12889 names
= att_names_mm
;
12890 oappend_register (ins
, names
[reg
]);
12894 /* cvt* are the only instructions in sse2 which have
12895 both SSE and MMX operands and also have 0x66 prefix
12896 in their opcode. 0x66 was originally used to differentiate
12897 between SSE and MMX instruction(operands). So we have to handle the
12898 cvt* separately using OP_EMC and OP_MXC */
12900 OP_EMC (instr_info
*ins
, int bytemode
, int sizeflag
)
12902 if (ins
->modrm
.mod
!= 3)
12904 if (ins
->intel_syntax
&& bytemode
== v_mode
)
12906 bytemode
= (ins
->prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12907 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12909 return OP_E (ins
, bytemode
, sizeflag
);
12912 /* Skip mod/rm byte. */
12915 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12916 oappend_register (ins
, att_names_mm
[ins
->modrm
.rm
]);
12921 OP_MXC (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
12922 int sizeflag ATTRIBUTE_UNUSED
)
12924 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
12925 oappend_register (ins
, att_names_mm
[ins
->modrm
.reg
]);
12930 OP_EX (instr_info
*ins
, int bytemode
, int sizeflag
)
12934 /* Skip mod/rm byte. */
12938 if (bytemode
== dq_mode
)
12939 bytemode
= ins
->vex
.w
? q_mode
: d_mode
;
12941 if (ins
->modrm
.mod
!= 3)
12942 return OP_E_memory (ins
, bytemode
, sizeflag
);
12944 reg
= ins
->modrm
.rm
;
12946 if (ins
->rex
& REX_B
)
12948 if (ins
->rex2
& REX_B
)
12953 if ((ins
->rex
& REX_X
))
12957 if ((sizeflag
& SUFFIX_ALWAYS
)
12958 && (bytemode
== x_swap_mode
12959 || bytemode
== w_swap_mode
12960 || bytemode
== d_swap_mode
12961 || bytemode
== q_swap_mode
))
12962 swap_operand (ins
);
12964 if (bytemode
== tmm_mode
)
12965 ins
->modrm
.rm
= reg
;
12967 print_vector_reg (ins
, reg
, bytemode
);
12972 OP_R (instr_info
*ins
, int bytemode
, int sizeflag
)
12974 if (ins
->modrm
.mod
!= 3)
12975 return BadOp (ins
);
12983 return OP_E (ins
, bytemode
, sizeflag
);
12985 return OP_EM (ins
, x_mode
, sizeflag
);
12987 if (ins
->vex
.length
<= 128)
12989 return BadOp (ins
);
12992 return OP_EX (ins
, bytemode
, sizeflag
);
12996 OP_M (instr_info
*ins
, int bytemode
, int sizeflag
)
12998 /* Skip mod/rm byte. */
13002 if (ins
->modrm
.mod
== 3)
13003 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13004 return BadOp (ins
);
13006 if (bytemode
== x_mode
)
13007 ins
->vex
.no_broadcast
= true;
13009 return OP_E_memory (ins
, bytemode
, sizeflag
);
13013 OP_0f07 (instr_info
*ins
, int bytemode
, int sizeflag
)
13015 if (ins
->modrm
.mod
!= 3 || ins
->modrm
.rm
!= 0)
13016 return BadOp (ins
);
13017 return OP_E (ins
, bytemode
, sizeflag
);
13020 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13021 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13024 NOP_Fixup (instr_info
*ins
, int opnd
, int sizeflag
)
13026 if ((ins
->prefixes
& PREFIX_DATA
) == 0 && (ins
->rex
& REX_B
) == 0)
13028 ins
->mnemonicendp
= stpcpy (ins
->obuf
, "nop");
13032 return OP_REG (ins
, eAX_reg
, sizeflag
);
13033 return OP_IMREG (ins
, eAX_reg
, sizeflag
);
13036 static const char *const Suffix3DNow
[] = {
13037 /* 00 */ NULL
, NULL
, NULL
, NULL
,
13038 /* 04 */ NULL
, NULL
, NULL
, NULL
,
13039 /* 08 */ NULL
, NULL
, NULL
, NULL
,
13040 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
13041 /* 10 */ NULL
, NULL
, NULL
, NULL
,
13042 /* 14 */ NULL
, NULL
, NULL
, NULL
,
13043 /* 18 */ NULL
, NULL
, NULL
, NULL
,
13044 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
13045 /* 20 */ NULL
, NULL
, NULL
, NULL
,
13046 /* 24 */ NULL
, NULL
, NULL
, NULL
,
13047 /* 28 */ NULL
, NULL
, NULL
, NULL
,
13048 /* 2C */ NULL
, NULL
, NULL
, NULL
,
13049 /* 30 */ NULL
, NULL
, NULL
, NULL
,
13050 /* 34 */ NULL
, NULL
, NULL
, NULL
,
13051 /* 38 */ NULL
, NULL
, NULL
, NULL
,
13052 /* 3C */ NULL
, NULL
, NULL
, NULL
,
13053 /* 40 */ NULL
, NULL
, NULL
, NULL
,
13054 /* 44 */ NULL
, NULL
, NULL
, NULL
,
13055 /* 48 */ NULL
, NULL
, NULL
, NULL
,
13056 /* 4C */ NULL
, NULL
, NULL
, NULL
,
13057 /* 50 */ NULL
, NULL
, NULL
, NULL
,
13058 /* 54 */ NULL
, NULL
, NULL
, NULL
,
13059 /* 58 */ NULL
, NULL
, NULL
, NULL
,
13060 /* 5C */ NULL
, NULL
, NULL
, NULL
,
13061 /* 60 */ NULL
, NULL
, NULL
, NULL
,
13062 /* 64 */ NULL
, NULL
, NULL
, NULL
,
13063 /* 68 */ NULL
, NULL
, NULL
, NULL
,
13064 /* 6C */ NULL
, NULL
, NULL
, NULL
,
13065 /* 70 */ NULL
, NULL
, NULL
, NULL
,
13066 /* 74 */ NULL
, NULL
, NULL
, NULL
,
13067 /* 78 */ NULL
, NULL
, NULL
, NULL
,
13068 /* 7C */ NULL
, NULL
, NULL
, NULL
,
13069 /* 80 */ NULL
, NULL
, NULL
, NULL
,
13070 /* 84 */ NULL
, NULL
, NULL
, NULL
,
13071 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
13072 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
13073 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
13074 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
13075 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
13076 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
13077 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
13078 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
13079 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
13080 /* AC */ NULL
, NULL
, "pfacc", NULL
,
13081 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
13082 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
13083 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
13084 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
13085 /* C0 */ NULL
, NULL
, NULL
, NULL
,
13086 /* C4 */ NULL
, NULL
, NULL
, NULL
,
13087 /* C8 */ NULL
, NULL
, NULL
, NULL
,
13088 /* CC */ NULL
, NULL
, NULL
, NULL
,
13089 /* D0 */ NULL
, NULL
, NULL
, NULL
,
13090 /* D4 */ NULL
, NULL
, NULL
, NULL
,
13091 /* D8 */ NULL
, NULL
, NULL
, NULL
,
13092 /* DC */ NULL
, NULL
, NULL
, NULL
,
13093 /* E0 */ NULL
, NULL
, NULL
, NULL
,
13094 /* E4 */ NULL
, NULL
, NULL
, NULL
,
13095 /* E8 */ NULL
, NULL
, NULL
, NULL
,
13096 /* EC */ NULL
, NULL
, NULL
, NULL
,
13097 /* F0 */ NULL
, NULL
, NULL
, NULL
,
13098 /* F4 */ NULL
, NULL
, NULL
, NULL
,
13099 /* F8 */ NULL
, NULL
, NULL
, NULL
,
13100 /* FC */ NULL
, NULL
, NULL
, NULL
,
13104 OP_3DNowSuffix (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13105 int sizeflag ATTRIBUTE_UNUSED
)
13107 const char *mnemonic
;
13109 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
13111 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13112 place where an 8-bit immediate would normally go. ie. the last
13113 byte of the instruction. */
13114 ins
->obufp
= ins
->mnemonicendp
;
13115 mnemonic
= Suffix3DNow
[*ins
->codep
++];
13117 ins
->obufp
= stpcpy (ins
->obufp
, mnemonic
);
13120 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13121 of the opcode (0x0f0f) and the opcode suffix, we need to do
13122 all the ins->modrm processing first, and don't know until now that
13123 we have a bad opcode. This necessitates some cleaning up. */
13124 ins
->op_out
[0][0] = '\0';
13125 ins
->op_out
[1][0] = '\0';
13128 ins
->mnemonicendp
= ins
->obufp
;
13132 static const struct op simd_cmp_op
[] =
13134 { STRING_COMMA_LEN ("eq") },
13135 { STRING_COMMA_LEN ("lt") },
13136 { STRING_COMMA_LEN ("le") },
13137 { STRING_COMMA_LEN ("unord") },
13138 { STRING_COMMA_LEN ("neq") },
13139 { STRING_COMMA_LEN ("nlt") },
13140 { STRING_COMMA_LEN ("nle") },
13141 { STRING_COMMA_LEN ("ord") }
13144 static const struct op vex_cmp_op
[] =
13146 { STRING_COMMA_LEN ("eq_uq") },
13147 { STRING_COMMA_LEN ("nge") },
13148 { STRING_COMMA_LEN ("ngt") },
13149 { STRING_COMMA_LEN ("false") },
13150 { STRING_COMMA_LEN ("neq_oq") },
13151 { STRING_COMMA_LEN ("ge") },
13152 { STRING_COMMA_LEN ("gt") },
13153 { STRING_COMMA_LEN ("true") },
13154 { STRING_COMMA_LEN ("eq_os") },
13155 { STRING_COMMA_LEN ("lt_oq") },
13156 { STRING_COMMA_LEN ("le_oq") },
13157 { STRING_COMMA_LEN ("unord_s") },
13158 { STRING_COMMA_LEN ("neq_us") },
13159 { STRING_COMMA_LEN ("nlt_uq") },
13160 { STRING_COMMA_LEN ("nle_uq") },
13161 { STRING_COMMA_LEN ("ord_s") },
13162 { STRING_COMMA_LEN ("eq_us") },
13163 { STRING_COMMA_LEN ("nge_uq") },
13164 { STRING_COMMA_LEN ("ngt_uq") },
13165 { STRING_COMMA_LEN ("false_os") },
13166 { STRING_COMMA_LEN ("neq_os") },
13167 { STRING_COMMA_LEN ("ge_oq") },
13168 { STRING_COMMA_LEN ("gt_oq") },
13169 { STRING_COMMA_LEN ("true_us") },
13173 CMP_Fixup (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13174 int sizeflag ATTRIBUTE_UNUSED
)
13176 unsigned int cmp_type
;
13178 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
13180 cmp_type
= *ins
->codep
++;
13181 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13184 char *p
= ins
->mnemonicendp
- 2;
13188 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13189 ins
->mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13191 else if (ins
->need_vex
13192 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13195 char *p
= ins
->mnemonicendp
- 2;
13199 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13200 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13201 ins
->mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13205 /* We have a reserved extension byte. Output it directly. */
13206 oappend_immediate (ins
, cmp_type
);
13212 OP_Mwait (instr_info
*ins
, int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13214 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13215 if (!ins
->intel_syntax
)
13217 strcpy (ins
->op_out
[0], att_names32
[0] + ins
->intel_syntax
);
13218 strcpy (ins
->op_out
[1], att_names32
[1] + ins
->intel_syntax
);
13219 if (bytemode
== eBX_reg
)
13220 strcpy (ins
->op_out
[2], att_names32
[3] + ins
->intel_syntax
);
13221 ins
->two_source_ops
= true;
13223 /* Skip mod/rm byte. */
13230 OP_Monitor (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13231 int sizeflag ATTRIBUTE_UNUSED
)
13233 /* monitor %{e,r,}ax,%ecx,%edx" */
13234 if (!ins
->intel_syntax
)
13236 const char (*names
)[8] = (ins
->address_mode
== mode_64bit
13237 ? att_names64
: att_names32
);
13239 if (ins
->prefixes
& PREFIX_ADDR
)
13241 /* Remove "addr16/addr32". */
13242 ins
->all_prefixes
[ins
->last_addr_prefix
] = 0;
13243 names
= (ins
->address_mode
!= mode_32bit
13244 ? att_names32
: att_names16
);
13245 ins
->used_prefixes
|= PREFIX_ADDR
;
13247 else if (ins
->address_mode
== mode_16bit
)
13248 names
= att_names16
;
13249 strcpy (ins
->op_out
[0], names
[0] + ins
->intel_syntax
);
13250 strcpy (ins
->op_out
[1], att_names32
[1] + ins
->intel_syntax
);
13251 strcpy (ins
->op_out
[2], att_names32
[2] + ins
->intel_syntax
);
13252 ins
->two_source_ops
= true;
13254 /* Skip mod/rm byte. */
13261 REP_Fixup (instr_info
*ins
, int bytemode
, int sizeflag
)
13263 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13265 if (ins
->prefixes
& PREFIX_REPZ
)
13266 ins
->all_prefixes
[ins
->last_repz_prefix
] = REP_PREFIX
;
13273 return OP_IMREG (ins
, bytemode
, sizeflag
);
13275 return OP_ESreg (ins
, bytemode
, sizeflag
);
13277 return OP_DSreg (ins
, bytemode
, sizeflag
);
13286 SEP_Fixup (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13287 int sizeflag ATTRIBUTE_UNUSED
)
13289 if (ins
->isa64
!= amd64
)
13292 ins
->obufp
= ins
->obuf
;
13294 ins
->mnemonicendp
= ins
->obufp
;
13299 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13303 BND_Fixup (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13304 int sizeflag ATTRIBUTE_UNUSED
)
13306 if (ins
->prefixes
& PREFIX_REPNZ
)
13307 ins
->all_prefixes
[ins
->last_repnz_prefix
] = BND_PREFIX
;
13311 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13315 NOTRACK_Fixup (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13316 int sizeflag ATTRIBUTE_UNUSED
)
13318 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13319 we've seen a PREFIX_DS. */
13320 if ((ins
->prefixes
& PREFIX_DS
) != 0
13321 && (ins
->address_mode
!= mode_64bit
|| ins
->last_data_prefix
< 0))
13323 /* NOTRACK prefix is only valid on indirect branch instructions.
13324 NB: DATA prefix is unsupported for Intel64. */
13325 ins
->active_seg_prefix
= 0;
13326 ins
->all_prefixes
[ins
->last_seg_prefix
] = NOTRACK_PREFIX
;
13331 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13332 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13336 HLE_Fixup1 (instr_info
*ins
, int bytemode
, int sizeflag
)
13338 if (ins
->modrm
.mod
!= 3
13339 && (ins
->prefixes
& PREFIX_LOCK
) != 0)
13341 if (ins
->prefixes
& PREFIX_REPZ
)
13342 ins
->all_prefixes
[ins
->last_repz_prefix
] = XRELEASE_PREFIX
;
13343 if (ins
->prefixes
& PREFIX_REPNZ
)
13344 ins
->all_prefixes
[ins
->last_repnz_prefix
] = XACQUIRE_PREFIX
;
13347 return OP_E (ins
, bytemode
, sizeflag
);
13350 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13351 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13355 HLE_Fixup2 (instr_info
*ins
, int bytemode
, int sizeflag
)
13357 if (ins
->modrm
.mod
!= 3)
13359 if (ins
->prefixes
& PREFIX_REPZ
)
13360 ins
->all_prefixes
[ins
->last_repz_prefix
] = XRELEASE_PREFIX
;
13361 if (ins
->prefixes
& PREFIX_REPNZ
)
13362 ins
->all_prefixes
[ins
->last_repnz_prefix
] = XACQUIRE_PREFIX
;
13365 return OP_E (ins
, bytemode
, sizeflag
);
13368 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13369 "xrelease" for memory operand. No check for LOCK prefix. */
13372 HLE_Fixup3 (instr_info
*ins
, int bytemode
, int sizeflag
)
13374 if (ins
->modrm
.mod
!= 3
13375 && ins
->last_repz_prefix
> ins
->last_repnz_prefix
13376 && (ins
->prefixes
& PREFIX_REPZ
) != 0)
13377 ins
->all_prefixes
[ins
->last_repz_prefix
] = XRELEASE_PREFIX
;
13379 return OP_E (ins
, bytemode
, sizeflag
);
13383 CMPXCHG8B_Fixup (instr_info
*ins
, int bytemode
, int sizeflag
)
13386 if (ins
->rex
& REX_W
)
13388 /* Change cmpxchg8b to cmpxchg16b. */
13389 char *p
= ins
->mnemonicendp
- 2;
13390 ins
->mnemonicendp
= stpcpy (p
, "16b");
13393 else if ((ins
->prefixes
& PREFIX_LOCK
) != 0)
13395 if (ins
->prefixes
& PREFIX_REPZ
)
13396 ins
->all_prefixes
[ins
->last_repz_prefix
] = XRELEASE_PREFIX
;
13397 if (ins
->prefixes
& PREFIX_REPNZ
)
13398 ins
->all_prefixes
[ins
->last_repnz_prefix
] = XACQUIRE_PREFIX
;
13401 return OP_M (ins
, bytemode
, sizeflag
);
13405 XMM_Fixup (instr_info
*ins
, int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13407 const char (*names
)[8] = att_names_xmm
;
13411 switch (ins
->vex
.length
)
13416 names
= att_names_ymm
;
13422 oappend_register (ins
, names
[reg
]);
13427 FXSAVE_Fixup (instr_info
*ins
, int bytemode
, int sizeflag
)
13429 /* Add proper suffix to "fxsave" and "fxrstor". */
13431 if (ins
->rex
& REX_W
)
13433 char *p
= ins
->mnemonicendp
;
13437 ins
->mnemonicendp
= p
;
13439 return OP_M (ins
, bytemode
, sizeflag
);
13442 /* Display the destination register operand for instructions with
13446 OP_VEX (instr_info
*ins
, int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13448 int reg
, modrm_reg
, sib_index
= -1;
13449 const char (*names
)[8];
13451 if (!ins
->need_vex
)
13454 if (ins
->evex_type
== evex_from_legacy
)
13456 ins
->evex_used
|= EVEX_b_used
;
13461 reg
= ins
->vex
.register_specifier
;
13462 ins
->vex
.register_specifier
= 0;
13463 if (ins
->address_mode
!= mode_64bit
)
13465 if (ins
->vex
.evex
&& !ins
->vex
.v
)
13467 oappend (ins
, "(bad)");
13473 else if (ins
->vex
.evex
&& !ins
->vex
.v
)
13479 oappend_register (ins
, att_names_xmm
[reg
]);
13482 case vex_vsib_d_w_dq_mode
:
13483 case vex_vsib_q_w_dq_mode
:
13484 /* This must be the 3rd operand. */
13485 if (ins
->obufp
!= ins
->op_out
[2])
13487 if (ins
->vex
.length
== 128
13488 || (bytemode
!= vex_vsib_d_w_dq_mode
13490 oappend_register (ins
, att_names_xmm
[reg
]);
13492 oappend_register (ins
, att_names_ymm
[reg
]);
13494 /* All 3 XMM/YMM registers must be distinct. */
13495 modrm_reg
= ins
->modrm
.reg
;
13496 if (ins
->rex
& REX_R
)
13499 if (ins
->has_sib
&& ins
->modrm
.rm
== 4)
13501 sib_index
= ins
->sib
.index
;
13502 if (ins
->rex
& REX_X
)
13506 if (reg
== modrm_reg
|| reg
== sib_index
)
13507 strcpy (ins
->obufp
, "/(bad)");
13508 if (modrm_reg
== sib_index
|| modrm_reg
== reg
)
13509 strcat (ins
->op_out
[0], "/(bad)");
13510 if (sib_index
== modrm_reg
|| sib_index
== reg
)
13511 strcat (ins
->op_out
[1], "/(bad)");
13516 /* All 3 TMM registers must be distinct. */
13518 oappend (ins
, "(bad)");
13521 /* This must be the 3rd operand. */
13522 if (ins
->obufp
!= ins
->op_out
[2])
13524 oappend_register (ins
, att_names_tmm
[reg
]);
13525 if (reg
== ins
->modrm
.reg
|| reg
== ins
->modrm
.rm
)
13526 strcpy (ins
->obufp
, "/(bad)");
13529 if (ins
->modrm
.reg
== ins
->modrm
.rm
|| ins
->modrm
.reg
== reg
13530 || ins
->modrm
.rm
== reg
)
13532 if (ins
->modrm
.reg
<= 8
13533 && (ins
->modrm
.reg
== ins
->modrm
.rm
|| ins
->modrm
.reg
== reg
))
13534 strcat (ins
->op_out
[0], "/(bad)");
13535 if (ins
->modrm
.rm
<= 8
13536 && (ins
->modrm
.rm
== ins
->modrm
.reg
|| ins
->modrm
.rm
== reg
))
13537 strcat (ins
->op_out
[1], "/(bad)");
13543 switch (ins
->vex
.length
)
13549 names
= att_names_xmm
;
13550 ins
->evex_used
|= EVEX_len_used
;
13554 if (ins
->rex
& REX_W
)
13555 names
= att_names64
;
13556 else if (bytemode
== v_mode
13557 && !(sizeflag
& DFLAG
))
13558 names
= att_names16
;
13560 names
= att_names32
;
13563 names
= att_names8rex
;
13566 names
= att_names64
;
13572 oappend (ins
, "(bad)");
13575 names
= att_names_mask
;
13586 names
= att_names_ymm
;
13587 ins
->evex_used
|= EVEX_len_used
;
13593 names
= att_names_mask
;
13596 /* Fall through. */
13598 /* See PR binutils/20893 for a reproducer. */
13599 oappend (ins
, "(bad)");
13604 names
= att_names_zmm
;
13605 ins
->evex_used
|= EVEX_len_used
;
13611 oappend_register (ins
, names
[reg
]);
13616 OP_VexR (instr_info
*ins
, int bytemode
, int sizeflag
)
13618 if (ins
->modrm
.mod
== 3)
13619 return OP_VEX (ins
, bytemode
, sizeflag
);
13624 OP_VexW (instr_info
*ins
, int bytemode
, int sizeflag
)
13626 OP_VEX (ins
, bytemode
, sizeflag
);
13630 /* Swap 2nd and 3rd operands. */
13631 char *tmp
= ins
->op_out
[2];
13633 ins
->op_out
[2] = ins
->op_out
[1];
13634 ins
->op_out
[1] = tmp
;
13640 OP_REG_VexI4 (instr_info
*ins
, int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13643 const char (*names
)[8] = att_names_xmm
;
13645 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
13647 reg
= *ins
->codep
++;
13649 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13653 if (ins
->address_mode
!= mode_64bit
)
13656 if (bytemode
== x_mode
&& ins
->vex
.length
== 256)
13657 names
= att_names_ymm
;
13659 oappend_register (ins
, names
[reg
]);
13663 /* Swap 3rd and 4th operands. */
13664 char *tmp
= ins
->op_out
[3];
13666 ins
->op_out
[3] = ins
->op_out
[2];
13667 ins
->op_out
[2] = tmp
;
13673 OP_VexI4 (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13674 int sizeflag ATTRIBUTE_UNUSED
)
13676 oappend_immediate (ins
, ins
->codep
[-1] & 0xf);
13681 VPCMP_Fixup (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13682 int sizeflag ATTRIBUTE_UNUSED
)
13684 unsigned int cmp_type
;
13686 if (!ins
->vex
.evex
)
13689 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
13691 cmp_type
= *ins
->codep
++;
13692 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13693 If it's the case, print suffix, otherwise - print the immediate. */
13694 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
13699 char *p
= ins
->mnemonicendp
- 2;
13701 /* vpcmp* can have both one- and two-lettered suffix. */
13715 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13716 ins
->mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13720 /* We have a reserved extension byte. Output it directly. */
13721 oappend_immediate (ins
, cmp_type
);
13726 static const struct op xop_cmp_op
[] =
13728 { STRING_COMMA_LEN ("lt") },
13729 { STRING_COMMA_LEN ("le") },
13730 { STRING_COMMA_LEN ("gt") },
13731 { STRING_COMMA_LEN ("ge") },
13732 { STRING_COMMA_LEN ("eq") },
13733 { STRING_COMMA_LEN ("neq") },
13734 { STRING_COMMA_LEN ("false") },
13735 { STRING_COMMA_LEN ("true") }
13739 VPCOM_Fixup (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13740 int sizeflag ATTRIBUTE_UNUSED
)
13742 unsigned int cmp_type
;
13744 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
13746 cmp_type
= *ins
->codep
++;
13747 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
13750 char *p
= ins
->mnemonicendp
- 2;
13752 /* vpcom* can have both one- and two-lettered suffix. */
13766 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
13767 ins
->mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
13771 /* We have a reserved extension byte. Output it directly. */
13772 oappend_immediate (ins
, cmp_type
);
13777 static const struct op pclmul_op
[] =
13779 { STRING_COMMA_LEN ("lql") },
13780 { STRING_COMMA_LEN ("hql") },
13781 { STRING_COMMA_LEN ("lqh") },
13782 { STRING_COMMA_LEN ("hqh") }
13786 PCLMUL_Fixup (instr_info
*ins
, int bytemode ATTRIBUTE_UNUSED
,
13787 int sizeflag ATTRIBUTE_UNUSED
)
13789 unsigned int pclmul_type
;
13791 if (!fetch_code (ins
->info
, ins
->codep
+ 1))
13793 pclmul_type
= *ins
->codep
++;
13794 switch (pclmul_type
)
13805 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
13808 char *p
= ins
->mnemonicendp
- 3;
13813 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
13814 ins
->mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
13818 /* We have a reserved extension byte. Output it directly. */
13819 oappend_immediate (ins
, pclmul_type
);
13825 MOVSXD_Fixup (instr_info
*ins
, int bytemode
, int sizeflag
)
13827 /* Add proper suffix to "movsxd". */
13828 char *p
= ins
->mnemonicendp
;
13833 if (!ins
->intel_syntax
)
13836 if (ins
->rex
& REX_W
)
13848 oappend (ins
, INTERNAL_DISASSEMBLER_ERROR
);
13852 ins
->mnemonicendp
= p
;
13854 return OP_E (ins
, bytemode
, sizeflag
);
13858 DistinctDest_Fixup (instr_info
*ins
, int bytemode
, int sizeflag
)
13860 unsigned int reg
= ins
->vex
.register_specifier
;
13861 unsigned int modrm_reg
= ins
->modrm
.reg
;
13862 unsigned int modrm_rm
= ins
->modrm
.rm
;
13864 /* Calc destination register number. */
13865 if (ins
->rex
& REX_R
)
13867 if (ins
->rex2
& REX_R
)
13870 /* Calc src1 register number. */
13871 if (ins
->address_mode
!= mode_64bit
)
13873 else if (ins
->vex
.evex
&& !ins
->vex
.v
)
13876 /* Calc src2 register number. */
13877 if (ins
->modrm
.mod
== 3)
13879 if (ins
->rex
& REX_B
)
13881 if (ins
->rex
& REX_X
)
13885 /* Destination and source registers must be distinct, output bad if
13886 dest == src1 or dest == src2. */
13887 if (modrm_reg
== reg
13888 || (ins
->modrm
.mod
== 3
13889 && modrm_reg
== modrm_rm
))
13891 oappend (ins
, "(bad)");
13894 return OP_XMM (ins
, bytemode
, sizeflag
);
13898 OP_Rounding (instr_info
*ins
, int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13900 if (ins
->modrm
.mod
!= 3 || !ins
->vex
.b
)
13905 case evex_rounding_64_mode
:
13906 if (ins
->address_mode
!= mode_64bit
|| !ins
->vex
.w
)
13908 /* Fall through. */
13909 case evex_rounding_mode
:
13910 ins
->evex_used
|= EVEX_b_used
;
13911 oappend (ins
, names_rounding
[ins
->vex
.ll
]);
13913 case evex_sae_mode
:
13914 ins
->evex_used
|= EVEX_b_used
;
13915 oappend (ins
, "{");
13920 oappend (ins
, "sae}");
13925 PREFETCHI_Fixup (instr_info
*ins
, int bytemode
, int sizeflag
)
13927 if (ins
->modrm
.mod
!= 0 || ins
->modrm
.rm
!= 5)
13929 if (ins
->intel_syntax
)
13931 ins
->mnemonicendp
= stpcpy (ins
->obuf
, "nop ");
13936 if (ins
->rex
& REX_W
)
13937 ins
->mnemonicendp
= stpcpy (ins
->obuf
, "nopq ");
13940 if (sizeflag
& DFLAG
)
13941 ins
->mnemonicendp
= stpcpy (ins
->obuf
, "nopl ");
13943 ins
->mnemonicendp
= stpcpy (ins
->obuf
, "nopw ");
13944 ins
->used_prefixes
|= (ins
->prefixes
& PREFIX_DATA
);
13950 return OP_M (ins
, bytemode
, sizeflag
);
13954 PUSH2_POP2_Fixup (instr_info
*ins
, int bytemode
, int sizeflag
)
13956 if (ins
->modrm
.mod
!= 3)
13959 unsigned int vvvv_reg
= ins
->vex
.register_specifier
13960 | (!ins
->vex
.v
<< 4);
13961 unsigned int rm_reg
= ins
->modrm
.rm
+ (ins
->rex
& REX_B
? 8 : 0)
13962 + (ins
->rex2
& REX_B
? 16 : 0);
13964 /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */
13965 if (!ins
->vex
.nd
|| vvvv_reg
== 0x4 || rm_reg
== 0x4
13966 || (!ins
->modrm
.reg
13967 && vvvv_reg
== rm_reg
))
13969 oappend (ins
, "(bad)");
13973 return OP_VEX (ins
, bytemode
, sizeflag
);
13977 JMPABS_Fixup (instr_info
*ins
, int bytemode
, int sizeflag
)
13979 if (ins
->last_rex2_prefix
>= 0)
13983 if ((ins
->prefixes
& (PREFIX_OPCODE
| PREFIX_ADDR
| PREFIX_LOCK
)) != 0x0
13984 || (ins
->rex
& REX_W
) != 0x0)
13986 oappend (ins
, "(bad)");
13990 if (bytemode
== eAX_reg
)
13993 if (!get64 (ins
, &op
))
13996 ins
->mnemonicendp
= stpcpy (ins
->obuf
, "jmpabs");
13997 ins
->rex2
|= REX2_SPECIAL
;
13998 oappend_immediate (ins
, op
);
14003 if (bytemode
== eAX_reg
)
14004 return OP_IMREG (ins
, bytemode
, sizeflag
);
14005 return OP_OFF64 (ins
, bytemode
, sizeflag
);